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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_fsh_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_csr_fsh_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | fsh_csrbus_read_data | |
46 | ); | |
47 | ||
48 | //==================================================================== | |
49 | // Polarity declarations | |
50 | //==================================================================== | |
51 | // synopsys translate_off | |
52 | input omni_ld; // Omni load | |
53 | // vlint flag_input_port_not_connected off | |
54 | input [`FIRE_DLC_MMU_CSR_FSH_WIDTH - 1:0] omni_data; // Omni write data | |
55 | // synopsys translate_on | |
56 | // vlint flag_input_port_not_connected on | |
57 | input clk; // Clock signal | |
58 | input rst_l; // Reset signal | |
59 | input w_ld; // SW load | |
60 | // vlint flag_input_port_not_connected off | |
61 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
62 | // vlint flag_input_port_not_connected on | |
63 | output [`FIRE_DLC_MMU_CSR_FSH_WIDTH-1:0] fsh_csrbus_read_data; // SW read data | |
64 | ||
65 | //==================================================================== | |
66 | // Type declarations | |
67 | //==================================================================== | |
68 | // synopsys translate_off | |
69 | wire omni_ld; // Omni load | |
70 | // vlint flag_dangling_net_within_module off | |
71 | // vlint flag_net_has_no_load off | |
72 | wire [`FIRE_DLC_MMU_CSR_FSH_WIDTH - 1:0] omni_data; // Omni write data | |
73 | // synopsys translate_on | |
74 | // vlint flag_dangling_net_within_module on | |
75 | // vlint flag_net_has_no_load on | |
76 | wire clk; // Clock signal | |
77 | wire rst_l; // Reset signal | |
78 | wire w_ld; // SW load | |
79 | // vlint flag_dangling_net_within_module off | |
80 | // vlint flag_net_has_no_load off | |
81 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
82 | // vlint flag_dangling_net_within_module on | |
83 | // vlint flag_net_has_no_load on | |
84 | wire [`FIRE_DLC_MMU_CSR_FSH_WIDTH-1:0] fsh_csrbus_read_data; // SW read data | |
85 | ||
86 | //==================================================================== | |
87 | // Logic | |
88 | //==================================================================== | |
89 | ||
90 | //----- Reset values | |
91 | // verilint 531 off | |
92 | wire [32:0] reset_flsh_addr = 33'h0; | |
93 | // verilint 531 on | |
94 | ||
95 | //----- Active high reset wires | |
96 | wire rst_l_active_high = ~rst_l; | |
97 | ||
98 | //==================================================== | |
99 | // Instantiation of flops | |
100 | //==================================================== | |
101 | ||
102 | assign fsh_csrbus_read_data[0] = 1'b0; // bit 0 | |
103 | assign fsh_csrbus_read_data[1] = 1'b0; // bit 1 | |
104 | assign fsh_csrbus_read_data[2] = 1'b0; // bit 2 | |
105 | assign fsh_csrbus_read_data[3] = 1'b0; // bit 3 | |
106 | assign fsh_csrbus_read_data[4] = 1'b0; // bit 4 | |
107 | assign fsh_csrbus_read_data[5] = 1'b0; // bit 5 | |
108 | // bit 6 | |
109 | csr_sw csr_sw_6 | |
110 | ( | |
111 | // synopsys translate_off | |
112 | .omni_ld (omni_ld), | |
113 | .omni_data (omni_data[6]), | |
114 | .omni_rw_alias (1'b1), | |
115 | .omni_rw1c_alias (1'b0), | |
116 | .omni_rw1s_alias (1'b0), | |
117 | // synopsys translate_on | |
118 | .rst (rst_l_active_high), | |
119 | .rst_val (reset_flsh_addr[0]), | |
120 | .csr_ld (w_ld), | |
121 | .csr_data (csrbus_wr_data[6]), | |
122 | .rw_alias (1'b1), | |
123 | .rw1c_alias (1'b0), | |
124 | .rw1s_alias (1'b0), | |
125 | .hw_ld (1'b0), | |
126 | .hw_data (1'b0), | |
127 | .cp (clk), | |
128 | .q (fsh_csrbus_read_data[6]) | |
129 | ); | |
130 | ||
131 | // bit 7 | |
132 | csr_sw csr_sw_7 | |
133 | ( | |
134 | // synopsys translate_off | |
135 | .omni_ld (omni_ld), | |
136 | .omni_data (omni_data[7]), | |
137 | .omni_rw_alias (1'b1), | |
138 | .omni_rw1c_alias (1'b0), | |
139 | .omni_rw1s_alias (1'b0), | |
140 | // synopsys translate_on | |
141 | .rst (rst_l_active_high), | |
142 | .rst_val (reset_flsh_addr[1]), | |
143 | .csr_ld (w_ld), | |
144 | .csr_data (csrbus_wr_data[7]), | |
145 | .rw_alias (1'b1), | |
146 | .rw1c_alias (1'b0), | |
147 | .rw1s_alias (1'b0), | |
148 | .hw_ld (1'b0), | |
149 | .hw_data (1'b0), | |
150 | .cp (clk), | |
151 | .q (fsh_csrbus_read_data[7]) | |
152 | ); | |
153 | ||
154 | // bit 8 | |
155 | csr_sw csr_sw_8 | |
156 | ( | |
157 | // synopsys translate_off | |
158 | .omni_ld (omni_ld), | |
159 | .omni_data (omni_data[8]), | |
160 | .omni_rw_alias (1'b1), | |
161 | .omni_rw1c_alias (1'b0), | |
162 | .omni_rw1s_alias (1'b0), | |
163 | // synopsys translate_on | |
164 | .rst (rst_l_active_high), | |
165 | .rst_val (reset_flsh_addr[2]), | |
166 | .csr_ld (w_ld), | |
167 | .csr_data (csrbus_wr_data[8]), | |
168 | .rw_alias (1'b1), | |
169 | .rw1c_alias (1'b0), | |
170 | .rw1s_alias (1'b0), | |
171 | .hw_ld (1'b0), | |
172 | .hw_data (1'b0), | |
173 | .cp (clk), | |
174 | .q (fsh_csrbus_read_data[8]) | |
175 | ); | |
176 | ||
177 | // bit 9 | |
178 | csr_sw csr_sw_9 | |
179 | ( | |
180 | // synopsys translate_off | |
181 | .omni_ld (omni_ld), | |
182 | .omni_data (omni_data[9]), | |
183 | .omni_rw_alias (1'b1), | |
184 | .omni_rw1c_alias (1'b0), | |
185 | .omni_rw1s_alias (1'b0), | |
186 | // synopsys translate_on | |
187 | .rst (rst_l_active_high), | |
188 | .rst_val (reset_flsh_addr[3]), | |
189 | .csr_ld (w_ld), | |
190 | .csr_data (csrbus_wr_data[9]), | |
191 | .rw_alias (1'b1), | |
192 | .rw1c_alias (1'b0), | |
193 | .rw1s_alias (1'b0), | |
194 | .hw_ld (1'b0), | |
195 | .hw_data (1'b0), | |
196 | .cp (clk), | |
197 | .q (fsh_csrbus_read_data[9]) | |
198 | ); | |
199 | ||
200 | // bit 10 | |
201 | csr_sw csr_sw_10 | |
202 | ( | |
203 | // synopsys translate_off | |
204 | .omni_ld (omni_ld), | |
205 | .omni_data (omni_data[10]), | |
206 | .omni_rw_alias (1'b1), | |
207 | .omni_rw1c_alias (1'b0), | |
208 | .omni_rw1s_alias (1'b0), | |
209 | // synopsys translate_on | |
210 | .rst (rst_l_active_high), | |
211 | .rst_val (reset_flsh_addr[4]), | |
212 | .csr_ld (w_ld), | |
213 | .csr_data (csrbus_wr_data[10]), | |
214 | .rw_alias (1'b1), | |
215 | .rw1c_alias (1'b0), | |
216 | .rw1s_alias (1'b0), | |
217 | .hw_ld (1'b0), | |
218 | .hw_data (1'b0), | |
219 | .cp (clk), | |
220 | .q (fsh_csrbus_read_data[10]) | |
221 | ); | |
222 | ||
223 | // bit 11 | |
224 | csr_sw csr_sw_11 | |
225 | ( | |
226 | // synopsys translate_off | |
227 | .omni_ld (omni_ld), | |
228 | .omni_data (omni_data[11]), | |
229 | .omni_rw_alias (1'b1), | |
230 | .omni_rw1c_alias (1'b0), | |
231 | .omni_rw1s_alias (1'b0), | |
232 | // synopsys translate_on | |
233 | .rst (rst_l_active_high), | |
234 | .rst_val (reset_flsh_addr[5]), | |
235 | .csr_ld (w_ld), | |
236 | .csr_data (csrbus_wr_data[11]), | |
237 | .rw_alias (1'b1), | |
238 | .rw1c_alias (1'b0), | |
239 | .rw1s_alias (1'b0), | |
240 | .hw_ld (1'b0), | |
241 | .hw_data (1'b0), | |
242 | .cp (clk), | |
243 | .q (fsh_csrbus_read_data[11]) | |
244 | ); | |
245 | ||
246 | // bit 12 | |
247 | csr_sw csr_sw_12 | |
248 | ( | |
249 | // synopsys translate_off | |
250 | .omni_ld (omni_ld), | |
251 | .omni_data (omni_data[12]), | |
252 | .omni_rw_alias (1'b1), | |
253 | .omni_rw1c_alias (1'b0), | |
254 | .omni_rw1s_alias (1'b0), | |
255 | // synopsys translate_on | |
256 | .rst (rst_l_active_high), | |
257 | .rst_val (reset_flsh_addr[6]), | |
258 | .csr_ld (w_ld), | |
259 | .csr_data (csrbus_wr_data[12]), | |
260 | .rw_alias (1'b1), | |
261 | .rw1c_alias (1'b0), | |
262 | .rw1s_alias (1'b0), | |
263 | .hw_ld (1'b0), | |
264 | .hw_data (1'b0), | |
265 | .cp (clk), | |
266 | .q (fsh_csrbus_read_data[12]) | |
267 | ); | |
268 | ||
269 | // bit 13 | |
270 | csr_sw csr_sw_13 | |
271 | ( | |
272 | // synopsys translate_off | |
273 | .omni_ld (omni_ld), | |
274 | .omni_data (omni_data[13]), | |
275 | .omni_rw_alias (1'b1), | |
276 | .omni_rw1c_alias (1'b0), | |
277 | .omni_rw1s_alias (1'b0), | |
278 | // synopsys translate_on | |
279 | .rst (rst_l_active_high), | |
280 | .rst_val (reset_flsh_addr[7]), | |
281 | .csr_ld (w_ld), | |
282 | .csr_data (csrbus_wr_data[13]), | |
283 | .rw_alias (1'b1), | |
284 | .rw1c_alias (1'b0), | |
285 | .rw1s_alias (1'b0), | |
286 | .hw_ld (1'b0), | |
287 | .hw_data (1'b0), | |
288 | .cp (clk), | |
289 | .q (fsh_csrbus_read_data[13]) | |
290 | ); | |
291 | ||
292 | // bit 14 | |
293 | csr_sw csr_sw_14 | |
294 | ( | |
295 | // synopsys translate_off | |
296 | .omni_ld (omni_ld), | |
297 | .omni_data (omni_data[14]), | |
298 | .omni_rw_alias (1'b1), | |
299 | .omni_rw1c_alias (1'b0), | |
300 | .omni_rw1s_alias (1'b0), | |
301 | // synopsys translate_on | |
302 | .rst (rst_l_active_high), | |
303 | .rst_val (reset_flsh_addr[8]), | |
304 | .csr_ld (w_ld), | |
305 | .csr_data (csrbus_wr_data[14]), | |
306 | .rw_alias (1'b1), | |
307 | .rw1c_alias (1'b0), | |
308 | .rw1s_alias (1'b0), | |
309 | .hw_ld (1'b0), | |
310 | .hw_data (1'b0), | |
311 | .cp (clk), | |
312 | .q (fsh_csrbus_read_data[14]) | |
313 | ); | |
314 | ||
315 | // bit 15 | |
316 | csr_sw csr_sw_15 | |
317 | ( | |
318 | // synopsys translate_off | |
319 | .omni_ld (omni_ld), | |
320 | .omni_data (omni_data[15]), | |
321 | .omni_rw_alias (1'b1), | |
322 | .omni_rw1c_alias (1'b0), | |
323 | .omni_rw1s_alias (1'b0), | |
324 | // synopsys translate_on | |
325 | .rst (rst_l_active_high), | |
326 | .rst_val (reset_flsh_addr[9]), | |
327 | .csr_ld (w_ld), | |
328 | .csr_data (csrbus_wr_data[15]), | |
329 | .rw_alias (1'b1), | |
330 | .rw1c_alias (1'b0), | |
331 | .rw1s_alias (1'b0), | |
332 | .hw_ld (1'b0), | |
333 | .hw_data (1'b0), | |
334 | .cp (clk), | |
335 | .q (fsh_csrbus_read_data[15]) | |
336 | ); | |
337 | ||
338 | // bit 16 | |
339 | csr_sw csr_sw_16 | |
340 | ( | |
341 | // synopsys translate_off | |
342 | .omni_ld (omni_ld), | |
343 | .omni_data (omni_data[16]), | |
344 | .omni_rw_alias (1'b1), | |
345 | .omni_rw1c_alias (1'b0), | |
346 | .omni_rw1s_alias (1'b0), | |
347 | // synopsys translate_on | |
348 | .rst (rst_l_active_high), | |
349 | .rst_val (reset_flsh_addr[10]), | |
350 | .csr_ld (w_ld), | |
351 | .csr_data (csrbus_wr_data[16]), | |
352 | .rw_alias (1'b1), | |
353 | .rw1c_alias (1'b0), | |
354 | .rw1s_alias (1'b0), | |
355 | .hw_ld (1'b0), | |
356 | .hw_data (1'b0), | |
357 | .cp (clk), | |
358 | .q (fsh_csrbus_read_data[16]) | |
359 | ); | |
360 | ||
361 | // bit 17 | |
362 | csr_sw csr_sw_17 | |
363 | ( | |
364 | // synopsys translate_off | |
365 | .omni_ld (omni_ld), | |
366 | .omni_data (omni_data[17]), | |
367 | .omni_rw_alias (1'b1), | |
368 | .omni_rw1c_alias (1'b0), | |
369 | .omni_rw1s_alias (1'b0), | |
370 | // synopsys translate_on | |
371 | .rst (rst_l_active_high), | |
372 | .rst_val (reset_flsh_addr[11]), | |
373 | .csr_ld (w_ld), | |
374 | .csr_data (csrbus_wr_data[17]), | |
375 | .rw_alias (1'b1), | |
376 | .rw1c_alias (1'b0), | |
377 | .rw1s_alias (1'b0), | |
378 | .hw_ld (1'b0), | |
379 | .hw_data (1'b0), | |
380 | .cp (clk), | |
381 | .q (fsh_csrbus_read_data[17]) | |
382 | ); | |
383 | ||
384 | // bit 18 | |
385 | csr_sw csr_sw_18 | |
386 | ( | |
387 | // synopsys translate_off | |
388 | .omni_ld (omni_ld), | |
389 | .omni_data (omni_data[18]), | |
390 | .omni_rw_alias (1'b1), | |
391 | .omni_rw1c_alias (1'b0), | |
392 | .omni_rw1s_alias (1'b0), | |
393 | // synopsys translate_on | |
394 | .rst (rst_l_active_high), | |
395 | .rst_val (reset_flsh_addr[12]), | |
396 | .csr_ld (w_ld), | |
397 | .csr_data (csrbus_wr_data[18]), | |
398 | .rw_alias (1'b1), | |
399 | .rw1c_alias (1'b0), | |
400 | .rw1s_alias (1'b0), | |
401 | .hw_ld (1'b0), | |
402 | .hw_data (1'b0), | |
403 | .cp (clk), | |
404 | .q (fsh_csrbus_read_data[18]) | |
405 | ); | |
406 | ||
407 | // bit 19 | |
408 | csr_sw csr_sw_19 | |
409 | ( | |
410 | // synopsys translate_off | |
411 | .omni_ld (omni_ld), | |
412 | .omni_data (omni_data[19]), | |
413 | .omni_rw_alias (1'b1), | |
414 | .omni_rw1c_alias (1'b0), | |
415 | .omni_rw1s_alias (1'b0), | |
416 | // synopsys translate_on | |
417 | .rst (rst_l_active_high), | |
418 | .rst_val (reset_flsh_addr[13]), | |
419 | .csr_ld (w_ld), | |
420 | .csr_data (csrbus_wr_data[19]), | |
421 | .rw_alias (1'b1), | |
422 | .rw1c_alias (1'b0), | |
423 | .rw1s_alias (1'b0), | |
424 | .hw_ld (1'b0), | |
425 | .hw_data (1'b0), | |
426 | .cp (clk), | |
427 | .q (fsh_csrbus_read_data[19]) | |
428 | ); | |
429 | ||
430 | // bit 20 | |
431 | csr_sw csr_sw_20 | |
432 | ( | |
433 | // synopsys translate_off | |
434 | .omni_ld (omni_ld), | |
435 | .omni_data (omni_data[20]), | |
436 | .omni_rw_alias (1'b1), | |
437 | .omni_rw1c_alias (1'b0), | |
438 | .omni_rw1s_alias (1'b0), | |
439 | // synopsys translate_on | |
440 | .rst (rst_l_active_high), | |
441 | .rst_val (reset_flsh_addr[14]), | |
442 | .csr_ld (w_ld), | |
443 | .csr_data (csrbus_wr_data[20]), | |
444 | .rw_alias (1'b1), | |
445 | .rw1c_alias (1'b0), | |
446 | .rw1s_alias (1'b0), | |
447 | .hw_ld (1'b0), | |
448 | .hw_data (1'b0), | |
449 | .cp (clk), | |
450 | .q (fsh_csrbus_read_data[20]) | |
451 | ); | |
452 | ||
453 | // bit 21 | |
454 | csr_sw csr_sw_21 | |
455 | ( | |
456 | // synopsys translate_off | |
457 | .omni_ld (omni_ld), | |
458 | .omni_data (omni_data[21]), | |
459 | .omni_rw_alias (1'b1), | |
460 | .omni_rw1c_alias (1'b0), | |
461 | .omni_rw1s_alias (1'b0), | |
462 | // synopsys translate_on | |
463 | .rst (rst_l_active_high), | |
464 | .rst_val (reset_flsh_addr[15]), | |
465 | .csr_ld (w_ld), | |
466 | .csr_data (csrbus_wr_data[21]), | |
467 | .rw_alias (1'b1), | |
468 | .rw1c_alias (1'b0), | |
469 | .rw1s_alias (1'b0), | |
470 | .hw_ld (1'b0), | |
471 | .hw_data (1'b0), | |
472 | .cp (clk), | |
473 | .q (fsh_csrbus_read_data[21]) | |
474 | ); | |
475 | ||
476 | // bit 22 | |
477 | csr_sw csr_sw_22 | |
478 | ( | |
479 | // synopsys translate_off | |
480 | .omni_ld (omni_ld), | |
481 | .omni_data (omni_data[22]), | |
482 | .omni_rw_alias (1'b1), | |
483 | .omni_rw1c_alias (1'b0), | |
484 | .omni_rw1s_alias (1'b0), | |
485 | // synopsys translate_on | |
486 | .rst (rst_l_active_high), | |
487 | .rst_val (reset_flsh_addr[16]), | |
488 | .csr_ld (w_ld), | |
489 | .csr_data (csrbus_wr_data[22]), | |
490 | .rw_alias (1'b1), | |
491 | .rw1c_alias (1'b0), | |
492 | .rw1s_alias (1'b0), | |
493 | .hw_ld (1'b0), | |
494 | .hw_data (1'b0), | |
495 | .cp (clk), | |
496 | .q (fsh_csrbus_read_data[22]) | |
497 | ); | |
498 | ||
499 | // bit 23 | |
500 | csr_sw csr_sw_23 | |
501 | ( | |
502 | // synopsys translate_off | |
503 | .omni_ld (omni_ld), | |
504 | .omni_data (omni_data[23]), | |
505 | .omni_rw_alias (1'b1), | |
506 | .omni_rw1c_alias (1'b0), | |
507 | .omni_rw1s_alias (1'b0), | |
508 | // synopsys translate_on | |
509 | .rst (rst_l_active_high), | |
510 | .rst_val (reset_flsh_addr[17]), | |
511 | .csr_ld (w_ld), | |
512 | .csr_data (csrbus_wr_data[23]), | |
513 | .rw_alias (1'b1), | |
514 | .rw1c_alias (1'b0), | |
515 | .rw1s_alias (1'b0), | |
516 | .hw_ld (1'b0), | |
517 | .hw_data (1'b0), | |
518 | .cp (clk), | |
519 | .q (fsh_csrbus_read_data[23]) | |
520 | ); | |
521 | ||
522 | // bit 24 | |
523 | csr_sw csr_sw_24 | |
524 | ( | |
525 | // synopsys translate_off | |
526 | .omni_ld (omni_ld), | |
527 | .omni_data (omni_data[24]), | |
528 | .omni_rw_alias (1'b1), | |
529 | .omni_rw1c_alias (1'b0), | |
530 | .omni_rw1s_alias (1'b0), | |
531 | // synopsys translate_on | |
532 | .rst (rst_l_active_high), | |
533 | .rst_val (reset_flsh_addr[18]), | |
534 | .csr_ld (w_ld), | |
535 | .csr_data (csrbus_wr_data[24]), | |
536 | .rw_alias (1'b1), | |
537 | .rw1c_alias (1'b0), | |
538 | .rw1s_alias (1'b0), | |
539 | .hw_ld (1'b0), | |
540 | .hw_data (1'b0), | |
541 | .cp (clk), | |
542 | .q (fsh_csrbus_read_data[24]) | |
543 | ); | |
544 | ||
545 | // bit 25 | |
546 | csr_sw csr_sw_25 | |
547 | ( | |
548 | // synopsys translate_off | |
549 | .omni_ld (omni_ld), | |
550 | .omni_data (omni_data[25]), | |
551 | .omni_rw_alias (1'b1), | |
552 | .omni_rw1c_alias (1'b0), | |
553 | .omni_rw1s_alias (1'b0), | |
554 | // synopsys translate_on | |
555 | .rst (rst_l_active_high), | |
556 | .rst_val (reset_flsh_addr[19]), | |
557 | .csr_ld (w_ld), | |
558 | .csr_data (csrbus_wr_data[25]), | |
559 | .rw_alias (1'b1), | |
560 | .rw1c_alias (1'b0), | |
561 | .rw1s_alias (1'b0), | |
562 | .hw_ld (1'b0), | |
563 | .hw_data (1'b0), | |
564 | .cp (clk), | |
565 | .q (fsh_csrbus_read_data[25]) | |
566 | ); | |
567 | ||
568 | // bit 26 | |
569 | csr_sw csr_sw_26 | |
570 | ( | |
571 | // synopsys translate_off | |
572 | .omni_ld (omni_ld), | |
573 | .omni_data (omni_data[26]), | |
574 | .omni_rw_alias (1'b1), | |
575 | .omni_rw1c_alias (1'b0), | |
576 | .omni_rw1s_alias (1'b0), | |
577 | // synopsys translate_on | |
578 | .rst (rst_l_active_high), | |
579 | .rst_val (reset_flsh_addr[20]), | |
580 | .csr_ld (w_ld), | |
581 | .csr_data (csrbus_wr_data[26]), | |
582 | .rw_alias (1'b1), | |
583 | .rw1c_alias (1'b0), | |
584 | .rw1s_alias (1'b0), | |
585 | .hw_ld (1'b0), | |
586 | .hw_data (1'b0), | |
587 | .cp (clk), | |
588 | .q (fsh_csrbus_read_data[26]) | |
589 | ); | |
590 | ||
591 | // bit 27 | |
592 | csr_sw csr_sw_27 | |
593 | ( | |
594 | // synopsys translate_off | |
595 | .omni_ld (omni_ld), | |
596 | .omni_data (omni_data[27]), | |
597 | .omni_rw_alias (1'b1), | |
598 | .omni_rw1c_alias (1'b0), | |
599 | .omni_rw1s_alias (1'b0), | |
600 | // synopsys translate_on | |
601 | .rst (rst_l_active_high), | |
602 | .rst_val (reset_flsh_addr[21]), | |
603 | .csr_ld (w_ld), | |
604 | .csr_data (csrbus_wr_data[27]), | |
605 | .rw_alias (1'b1), | |
606 | .rw1c_alias (1'b0), | |
607 | .rw1s_alias (1'b0), | |
608 | .hw_ld (1'b0), | |
609 | .hw_data (1'b0), | |
610 | .cp (clk), | |
611 | .q (fsh_csrbus_read_data[27]) | |
612 | ); | |
613 | ||
614 | // bit 28 | |
615 | csr_sw csr_sw_28 | |
616 | ( | |
617 | // synopsys translate_off | |
618 | .omni_ld (omni_ld), | |
619 | .omni_data (omni_data[28]), | |
620 | .omni_rw_alias (1'b1), | |
621 | .omni_rw1c_alias (1'b0), | |
622 | .omni_rw1s_alias (1'b0), | |
623 | // synopsys translate_on | |
624 | .rst (rst_l_active_high), | |
625 | .rst_val (reset_flsh_addr[22]), | |
626 | .csr_ld (w_ld), | |
627 | .csr_data (csrbus_wr_data[28]), | |
628 | .rw_alias (1'b1), | |
629 | .rw1c_alias (1'b0), | |
630 | .rw1s_alias (1'b0), | |
631 | .hw_ld (1'b0), | |
632 | .hw_data (1'b0), | |
633 | .cp (clk), | |
634 | .q (fsh_csrbus_read_data[28]) | |
635 | ); | |
636 | ||
637 | // bit 29 | |
638 | csr_sw csr_sw_29 | |
639 | ( | |
640 | // synopsys translate_off | |
641 | .omni_ld (omni_ld), | |
642 | .omni_data (omni_data[29]), | |
643 | .omni_rw_alias (1'b1), | |
644 | .omni_rw1c_alias (1'b0), | |
645 | .omni_rw1s_alias (1'b0), | |
646 | // synopsys translate_on | |
647 | .rst (rst_l_active_high), | |
648 | .rst_val (reset_flsh_addr[23]), | |
649 | .csr_ld (w_ld), | |
650 | .csr_data (csrbus_wr_data[29]), | |
651 | .rw_alias (1'b1), | |
652 | .rw1c_alias (1'b0), | |
653 | .rw1s_alias (1'b0), | |
654 | .hw_ld (1'b0), | |
655 | .hw_data (1'b0), | |
656 | .cp (clk), | |
657 | .q (fsh_csrbus_read_data[29]) | |
658 | ); | |
659 | ||
660 | // bit 30 | |
661 | csr_sw csr_sw_30 | |
662 | ( | |
663 | // synopsys translate_off | |
664 | .omni_ld (omni_ld), | |
665 | .omni_data (omni_data[30]), | |
666 | .omni_rw_alias (1'b1), | |
667 | .omni_rw1c_alias (1'b0), | |
668 | .omni_rw1s_alias (1'b0), | |
669 | // synopsys translate_on | |
670 | .rst (rst_l_active_high), | |
671 | .rst_val (reset_flsh_addr[24]), | |
672 | .csr_ld (w_ld), | |
673 | .csr_data (csrbus_wr_data[30]), | |
674 | .rw_alias (1'b1), | |
675 | .rw1c_alias (1'b0), | |
676 | .rw1s_alias (1'b0), | |
677 | .hw_ld (1'b0), | |
678 | .hw_data (1'b0), | |
679 | .cp (clk), | |
680 | .q (fsh_csrbus_read_data[30]) | |
681 | ); | |
682 | ||
683 | // bit 31 | |
684 | csr_sw csr_sw_31 | |
685 | ( | |
686 | // synopsys translate_off | |
687 | .omni_ld (omni_ld), | |
688 | .omni_data (omni_data[31]), | |
689 | .omni_rw_alias (1'b1), | |
690 | .omni_rw1c_alias (1'b0), | |
691 | .omni_rw1s_alias (1'b0), | |
692 | // synopsys translate_on | |
693 | .rst (rst_l_active_high), | |
694 | .rst_val (reset_flsh_addr[25]), | |
695 | .csr_ld (w_ld), | |
696 | .csr_data (csrbus_wr_data[31]), | |
697 | .rw_alias (1'b1), | |
698 | .rw1c_alias (1'b0), | |
699 | .rw1s_alias (1'b0), | |
700 | .hw_ld (1'b0), | |
701 | .hw_data (1'b0), | |
702 | .cp (clk), | |
703 | .q (fsh_csrbus_read_data[31]) | |
704 | ); | |
705 | ||
706 | // bit 32 | |
707 | csr_sw csr_sw_32 | |
708 | ( | |
709 | // synopsys translate_off | |
710 | .omni_ld (omni_ld), | |
711 | .omni_data (omni_data[32]), | |
712 | .omni_rw_alias (1'b1), | |
713 | .omni_rw1c_alias (1'b0), | |
714 | .omni_rw1s_alias (1'b0), | |
715 | // synopsys translate_on | |
716 | .rst (rst_l_active_high), | |
717 | .rst_val (reset_flsh_addr[26]), | |
718 | .csr_ld (w_ld), | |
719 | .csr_data (csrbus_wr_data[32]), | |
720 | .rw_alias (1'b1), | |
721 | .rw1c_alias (1'b0), | |
722 | .rw1s_alias (1'b0), | |
723 | .hw_ld (1'b0), | |
724 | .hw_data (1'b0), | |
725 | .cp (clk), | |
726 | .q (fsh_csrbus_read_data[32]) | |
727 | ); | |
728 | ||
729 | // bit 33 | |
730 | csr_sw csr_sw_33 | |
731 | ( | |
732 | // synopsys translate_off | |
733 | .omni_ld (omni_ld), | |
734 | .omni_data (omni_data[33]), | |
735 | .omni_rw_alias (1'b1), | |
736 | .omni_rw1c_alias (1'b0), | |
737 | .omni_rw1s_alias (1'b0), | |
738 | // synopsys translate_on | |
739 | .rst (rst_l_active_high), | |
740 | .rst_val (reset_flsh_addr[27]), | |
741 | .csr_ld (w_ld), | |
742 | .csr_data (csrbus_wr_data[33]), | |
743 | .rw_alias (1'b1), | |
744 | .rw1c_alias (1'b0), | |
745 | .rw1s_alias (1'b0), | |
746 | .hw_ld (1'b0), | |
747 | .hw_data (1'b0), | |
748 | .cp (clk), | |
749 | .q (fsh_csrbus_read_data[33]) | |
750 | ); | |
751 | ||
752 | // bit 34 | |
753 | csr_sw csr_sw_34 | |
754 | ( | |
755 | // synopsys translate_off | |
756 | .omni_ld (omni_ld), | |
757 | .omni_data (omni_data[34]), | |
758 | .omni_rw_alias (1'b1), | |
759 | .omni_rw1c_alias (1'b0), | |
760 | .omni_rw1s_alias (1'b0), | |
761 | // synopsys translate_on | |
762 | .rst (rst_l_active_high), | |
763 | .rst_val (reset_flsh_addr[28]), | |
764 | .csr_ld (w_ld), | |
765 | .csr_data (csrbus_wr_data[34]), | |
766 | .rw_alias (1'b1), | |
767 | .rw1c_alias (1'b0), | |
768 | .rw1s_alias (1'b0), | |
769 | .hw_ld (1'b0), | |
770 | .hw_data (1'b0), | |
771 | .cp (clk), | |
772 | .q (fsh_csrbus_read_data[34]) | |
773 | ); | |
774 | ||
775 | // bit 35 | |
776 | csr_sw csr_sw_35 | |
777 | ( | |
778 | // synopsys translate_off | |
779 | .omni_ld (omni_ld), | |
780 | .omni_data (omni_data[35]), | |
781 | .omni_rw_alias (1'b1), | |
782 | .omni_rw1c_alias (1'b0), | |
783 | .omni_rw1s_alias (1'b0), | |
784 | // synopsys translate_on | |
785 | .rst (rst_l_active_high), | |
786 | .rst_val (reset_flsh_addr[29]), | |
787 | .csr_ld (w_ld), | |
788 | .csr_data (csrbus_wr_data[35]), | |
789 | .rw_alias (1'b1), | |
790 | .rw1c_alias (1'b0), | |
791 | .rw1s_alias (1'b0), | |
792 | .hw_ld (1'b0), | |
793 | .hw_data (1'b0), | |
794 | .cp (clk), | |
795 | .q (fsh_csrbus_read_data[35]) | |
796 | ); | |
797 | ||
798 | // bit 36 | |
799 | csr_sw csr_sw_36 | |
800 | ( | |
801 | // synopsys translate_off | |
802 | .omni_ld (omni_ld), | |
803 | .omni_data (omni_data[36]), | |
804 | .omni_rw_alias (1'b1), | |
805 | .omni_rw1c_alias (1'b0), | |
806 | .omni_rw1s_alias (1'b0), | |
807 | // synopsys translate_on | |
808 | .rst (rst_l_active_high), | |
809 | .rst_val (reset_flsh_addr[30]), | |
810 | .csr_ld (w_ld), | |
811 | .csr_data (csrbus_wr_data[36]), | |
812 | .rw_alias (1'b1), | |
813 | .rw1c_alias (1'b0), | |
814 | .rw1s_alias (1'b0), | |
815 | .hw_ld (1'b0), | |
816 | .hw_data (1'b0), | |
817 | .cp (clk), | |
818 | .q (fsh_csrbus_read_data[36]) | |
819 | ); | |
820 | ||
821 | // bit 37 | |
822 | csr_sw csr_sw_37 | |
823 | ( | |
824 | // synopsys translate_off | |
825 | .omni_ld (omni_ld), | |
826 | .omni_data (omni_data[37]), | |
827 | .omni_rw_alias (1'b1), | |
828 | .omni_rw1c_alias (1'b0), | |
829 | .omni_rw1s_alias (1'b0), | |
830 | // synopsys translate_on | |
831 | .rst (rst_l_active_high), | |
832 | .rst_val (reset_flsh_addr[31]), | |
833 | .csr_ld (w_ld), | |
834 | .csr_data (csrbus_wr_data[37]), | |
835 | .rw_alias (1'b1), | |
836 | .rw1c_alias (1'b0), | |
837 | .rw1s_alias (1'b0), | |
838 | .hw_ld (1'b0), | |
839 | .hw_data (1'b0), | |
840 | .cp (clk), | |
841 | .q (fsh_csrbus_read_data[37]) | |
842 | ); | |
843 | ||
844 | // bit 38 | |
845 | csr_sw csr_sw_38 | |
846 | ( | |
847 | // synopsys translate_off | |
848 | .omni_ld (omni_ld), | |
849 | .omni_data (omni_data[38]), | |
850 | .omni_rw_alias (1'b1), | |
851 | .omni_rw1c_alias (1'b0), | |
852 | .omni_rw1s_alias (1'b0), | |
853 | // synopsys translate_on | |
854 | .rst (rst_l_active_high), | |
855 | .rst_val (reset_flsh_addr[32]), | |
856 | .csr_ld (w_ld), | |
857 | .csr_data (csrbus_wr_data[38]), | |
858 | .rw_alias (1'b1), | |
859 | .rw1c_alias (1'b0), | |
860 | .rw1s_alias (1'b0), | |
861 | .hw_ld (1'b0), | |
862 | .hw_data (1'b0), | |
863 | .cp (clk), | |
864 | .q (fsh_csrbus_read_data[38]) | |
865 | ); | |
866 | ||
867 | assign fsh_csrbus_read_data[39] = 1'b0; // bit 39 | |
868 | assign fsh_csrbus_read_data[40] = 1'b0; // bit 40 | |
869 | assign fsh_csrbus_read_data[41] = 1'b0; // bit 41 | |
870 | assign fsh_csrbus_read_data[42] = 1'b0; // bit 42 | |
871 | assign fsh_csrbus_read_data[43] = 1'b0; // bit 43 | |
872 | assign fsh_csrbus_read_data[44] = 1'b0; // bit 44 | |
873 | assign fsh_csrbus_read_data[45] = 1'b0; // bit 45 | |
874 | assign fsh_csrbus_read_data[46] = 1'b0; // bit 46 | |
875 | assign fsh_csrbus_read_data[47] = 1'b0; // bit 47 | |
876 | assign fsh_csrbus_read_data[48] = 1'b0; // bit 48 | |
877 | assign fsh_csrbus_read_data[49] = 1'b0; // bit 49 | |
878 | assign fsh_csrbus_read_data[50] = 1'b0; // bit 50 | |
879 | assign fsh_csrbus_read_data[51] = 1'b0; // bit 51 | |
880 | assign fsh_csrbus_read_data[52] = 1'b0; // bit 52 | |
881 | assign fsh_csrbus_read_data[53] = 1'b0; // bit 53 | |
882 | assign fsh_csrbus_read_data[54] = 1'b0; // bit 54 | |
883 | assign fsh_csrbus_read_data[55] = 1'b0; // bit 55 | |
884 | assign fsh_csrbus_read_data[56] = 1'b0; // bit 56 | |
885 | assign fsh_csrbus_read_data[57] = 1'b0; // bit 57 | |
886 | assign fsh_csrbus_read_data[58] = 1'b0; // bit 58 | |
887 | assign fsh_csrbus_read_data[59] = 1'b0; // bit 59 | |
888 | assign fsh_csrbus_read_data[60] = 1'b0; // bit 60 | |
889 | assign fsh_csrbus_read_data[61] = 1'b0; // bit 61 | |
890 | assign fsh_csrbus_read_data[62] = 1'b0; // bit 62 | |
891 | assign fsh_csrbus_read_data[63] = 1'b0; // bit 63 | |
892 | ||
893 | endmodule // dmu_mmu_csr_fsh_entry |