[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_prfc_entry.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_mmu_csr_prfc_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_mmu_csr_prfc_entry 
	(
	// synopsys translate_off
	  omni_ld,
	  omni_data,
	// synopsys translate_on
	clk,
	rst_l,
	w_ld,
	csrbus_wr_data,
	prfc_csrbus_read_data
	);

//====================================================================
//     Polarity declarations
//====================================================================
// synopsys translate_off
  input  omni_ld;  // Omni load
// vlint flag_input_port_not_connected off
  input  [`FIRE_DLC_MMU_CSR_PRFC_WIDTH - 1:0] omni_data;  // Omni write data
// synopsys translate_on
// vlint flag_input_port_not_connected on
input  clk;  // Clock signal
input  rst_l;  // Reset signal
input  w_ld;  // SW load
// vlint flag_input_port_not_connected off
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_MMU_CSR_PRFC_WIDTH-1:0] prfc_csrbus_read_data;  // SW read
                                                                  // data

//====================================================================
//     Type declarations
//====================================================================
// synopsys translate_off
  wire omni_ld;  // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
  wire [`FIRE_DLC_MMU_CSR_PRFC_WIDTH - 1:0] omni_data;  // Omni write data
// synopsys translate_on
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk;  // Clock signal
wire rst_l;  // Reset signal
wire w_ld;  // SW load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_MMU_CSR_PRFC_WIDTH-1:0] prfc_csrbus_read_data;  // SW read data

//====================================================================
//     Logic     
//====================================================================

//----- Reset values
// verilint 531 off
wire [7:0] reset_sel1 = 8'h0;
wire [7:0] reset_sel0 = 8'h0;
// verilint 531 on

//----- Active high reset wires 
wire rst_l_active_high = ~rst_l;

//====================================================
//     Instantiation of flops
//====================================================

// bit 0
csr_sw csr_sw_0
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[0]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[0]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[0])
	);

// bit 1
csr_sw csr_sw_1
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[1]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[1]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[1])
	);

// bit 2
csr_sw csr_sw_2
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[2]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[2]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[2])
	);

// bit 3
csr_sw csr_sw_3
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[3]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[3]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[3])
	);

// bit 4
csr_sw csr_sw_4
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[4]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[4]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[4]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[4])
	);

// bit 5
csr_sw csr_sw_5
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[5]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[5]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[5]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[5])
	);

// bit 6
csr_sw csr_sw_6
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[6]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[6]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[6]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[6])
	);

// bit 7
csr_sw csr_sw_7
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[7]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel0[7]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[7]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[7])
	);

// bit 8
csr_sw csr_sw_8
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[8]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[8]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[8])
	);

// bit 9
csr_sw csr_sw_9
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[9]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[9]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[9])
	);

// bit 10
csr_sw csr_sw_10
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[10]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[10]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[10])
	);

// bit 11
csr_sw csr_sw_11
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[11]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[11]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[11])
	);

// bit 12
csr_sw csr_sw_12
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[12]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[4]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[12]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[12])
	);

// bit 13
csr_sw csr_sw_13
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[13]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[5]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[13]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[13])
	);

// bit 14
csr_sw csr_sw_14
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[14]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[6]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[14]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[14])
	);

// bit 15
csr_sw csr_sw_15
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[15]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sel1[7]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[15]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (prfc_csrbus_read_data[15])
	);

assign  prfc_csrbus_read_data[16] = 1'b0;  // bit 16
assign  prfc_csrbus_read_data[17] = 1'b0;  // bit 17
assign  prfc_csrbus_read_data[18] = 1'b0;  // bit 18
assign  prfc_csrbus_read_data[19] = 1'b0;  // bit 19
assign  prfc_csrbus_read_data[20] = 1'b0;  // bit 20
assign  prfc_csrbus_read_data[21] = 1'b0;  // bit 21
assign  prfc_csrbus_read_data[22] = 1'b0;  // bit 22
assign  prfc_csrbus_read_data[23] = 1'b0;  // bit 23
assign  prfc_csrbus_read_data[24] = 1'b0;  // bit 24
assign  prfc_csrbus_read_data[25] = 1'b0;  // bit 25
assign  prfc_csrbus_read_data[26] = 1'b0;  // bit 26
assign  prfc_csrbus_read_data[27] = 1'b0;  // bit 27
assign  prfc_csrbus_read_data[28] = 1'b0;  // bit 28
assign  prfc_csrbus_read_data[29] = 1'b0;  // bit 29
assign  prfc_csrbus_read_data[30] = 1'b0;  // bit 30
assign  prfc_csrbus_read_data[31] = 1'b0;  // bit 31
assign  prfc_csrbus_read_data[32] = 1'b0;  // bit 32
assign  prfc_csrbus_read_data[33] = 1'b0;  // bit 33
assign  prfc_csrbus_read_data[34] = 1'b0;  // bit 34
assign  prfc_csrbus_read_data[35] = 1'b0;  // bit 35
assign  prfc_csrbus_read_data[36] = 1'b0;  // bit 36
assign  prfc_csrbus_read_data[37] = 1'b0;  // bit 37
assign  prfc_csrbus_read_data[38] = 1'b0;  // bit 38
assign  prfc_csrbus_read_data[39] = 1'b0;  // bit 39
assign  prfc_csrbus_read_data[40] = 1'b0;  // bit 40
assign  prfc_csrbus_read_data[41] = 1'b0;  // bit 41
assign  prfc_csrbus_read_data[42] = 1'b0;  // bit 42
assign  prfc_csrbus_read_data[43] = 1'b0;  // bit 43
assign  prfc_csrbus_read_data[44] = 1'b0;  // bit 44
assign  prfc_csrbus_read_data[45] = 1'b0;  // bit 45
assign  prfc_csrbus_read_data[46] = 1'b0;  // bit 46
assign  prfc_csrbus_read_data[47] = 1'b0;  // bit 47
assign  prfc_csrbus_read_data[48] = 1'b0;  // bit 48
assign  prfc_csrbus_read_data[49] = 1'b0;  // bit 49
assign  prfc_csrbus_read_data[50] = 1'b0;  // bit 50
assign  prfc_csrbus_read_data[51] = 1'b0;  // bit 51
assign  prfc_csrbus_read_data[52] = 1'b0;  // bit 52
assign  prfc_csrbus_read_data[53] = 1'b0;  // bit 53
assign  prfc_csrbus_read_data[54] = 1'b0;  // bit 54
assign  prfc_csrbus_read_data[55] = 1'b0;  // bit 55
assign  prfc_csrbus_read_data[56] = 1'b0;  // bit 56
assign  prfc_csrbus_read_data[57] = 1'b0;  // bit 57
assign  prfc_csrbus_read_data[58] = 1'b0;  // bit 58
assign  prfc_csrbus_read_data[59] = 1'b0;  // bit 59
assign  prfc_csrbus_read_data[60] = 1'b0;  // bit 60
assign  prfc_csrbus_read_data[61] = 1'b0;  // bit 61
assign  prfc_csrbus_read_data[62] = 1'b0;  // bit 62
assign  prfc_csrbus_read_data[63] = 1'b0;  // bit 63

endmodule // dmu_mmu_csr_prfc_entry
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_mmu_csr_prfc_entry.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_mmu_csr_prfc_entry
	36	(
	37	// synopsys translate_off
	38	omni_ld,
	39	omni_data,
	40	// synopsys translate_on
	41	clk,
	42	rst_l,
	43	w_ld,
	44	csrbus_wr_data,
	45	prfc_csrbus_read_data
	46	);
	47
	48	//====================================================================
	49	// Polarity declarations
	50	//====================================================================
	51	// synopsys translate_off
	52	input omni_ld; // Omni load
	53	// vlint flag_input_port_not_connected off
	54	input [`FIRE_DLC_MMU_CSR_PRFC_WIDTH - 1:0] omni_data; // Omni write data
	55	// synopsys translate_on
	56	// vlint flag_input_port_not_connected on
	57	input clk; // Clock signal
	58	input rst_l; // Reset signal
	59	input w_ld; // SW load
	60	// vlint flag_input_port_not_connected off
	61	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
	62	// vlint flag_input_port_not_connected on
	63	output [`FIRE_DLC_MMU_CSR_PRFC_WIDTH-1:0] prfc_csrbus_read_data; // SW read
	64	// data
65
66	//====================================================================
67	// Type declarations
68	//====================================================================
69	// synopsys translate_off
70	wire omni_ld; // Omni load
71	// vlint flag_dangling_net_within_module off
72	// vlint flag_net_has_no_load off
73	wire [`FIRE_DLC_MMU_CSR_PRFC_WIDTH - 1:0] omni_data; // Omni write data
74	// synopsys translate_on
75	// vlint flag_dangling_net_within_module on
76	// vlint flag_net_has_no_load on
77	wire clk; // Clock signal
78	wire rst_l; // Reset signal
79	wire w_ld; // SW load
80	// vlint flag_dangling_net_within_module off
81	// vlint flag_net_has_no_load off
82	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
83	// vlint flag_dangling_net_within_module on
84	// vlint flag_net_has_no_load on
85	wire [`FIRE_DLC_MMU_CSR_PRFC_WIDTH-1:0] prfc_csrbus_read_data; // SW read data
86
87	//====================================================================
88	// Logic
89	//====================================================================
90
91	//----- Reset values
92	// verilint 531 off
93	wire [7:0] reset_sel1 = 8'h0;
94	wire [7:0] reset_sel0 = 8'h0;
95	// verilint 531 on
96
97	//----- Active high reset wires
98	wire rst_l_active_high = ~rst_l;
99
100	//====================================================
101	// Instantiation of flops
102	//====================================================
103
104	// bit 0
105	csr_sw csr_sw_0
106	(
107	// synopsys translate_off
108	.omni_ld (omni_ld),
109	.omni_data (omni_data[0]),
110	.omni_rw_alias (1'b1),
111	.omni_rw1c_alias (1'b0),
112	.omni_rw1s_alias (1'b0),
113	// synopsys translate_on
114	.rst (rst_l_active_high),
115	.rst_val (reset_sel0[0]),
116	.csr_ld (w_ld),
117	.csr_data (csrbus_wr_data[0]),
118	.rw_alias (1'b1),
119	.rw1c_alias (1'b0),
120	.rw1s_alias (1'b0),
121	.hw_ld (1'b0),
122	.hw_data (1'b0),
123	.cp (clk),
124	.q (prfc_csrbus_read_data[0])
125	);
126
127	// bit 1
128	csr_sw csr_sw_1
129	(
130	// synopsys translate_off
131	.omni_ld (omni_ld),
132	.omni_data (omni_data[1]),
133	.omni_rw_alias (1'b1),
134	.omni_rw1c_alias (1'b0),
135	.omni_rw1s_alias (1'b0),
136	// synopsys translate_on
137	.rst (rst_l_active_high),
138	.rst_val (reset_sel0[1]),
139	.csr_ld (w_ld),
140	.csr_data (csrbus_wr_data[1]),
141	.rw_alias (1'b1),
142	.rw1c_alias (1'b0),
143	.rw1s_alias (1'b0),
144	.hw_ld (1'b0),
145	.hw_data (1'b0),
146	.cp (clk),
147	.q (prfc_csrbus_read_data[1])
148	);
149
150	// bit 2
151	csr_sw csr_sw_2
152	(
153	// synopsys translate_off
154	.omni_ld (omni_ld),
155	.omni_data (omni_data[2]),
156	.omni_rw_alias (1'b1),
157	.omni_rw1c_alias (1'b0),
158	.omni_rw1s_alias (1'b0),
159	// synopsys translate_on
160	.rst (rst_l_active_high),
161	.rst_val (reset_sel0[2]),
162	.csr_ld (w_ld),
163	.csr_data (csrbus_wr_data[2]),
164	.rw_alias (1'b1),
165	.rw1c_alias (1'b0),
166	.rw1s_alias (1'b0),
167	.hw_ld (1'b0),
168	.hw_data (1'b0),
169	.cp (clk),
170	.q (prfc_csrbus_read_data[2])
171	);
172
173	// bit 3
174	csr_sw csr_sw_3
175	(
176	// synopsys translate_off
177	.omni_ld (omni_ld),
178	.omni_data (omni_data[3]),
179	.omni_rw_alias (1'b1),
180	.omni_rw1c_alias (1'b0),
181	.omni_rw1s_alias (1'b0),
182	// synopsys translate_on
183	.rst (rst_l_active_high),
184	.rst_val (reset_sel0[3]),
185	.csr_ld (w_ld),
186	.csr_data (csrbus_wr_data[3]),
187	.rw_alias (1'b1),
188	.rw1c_alias (1'b0),
189	.rw1s_alias (1'b0),
190	.hw_ld (1'b0),
191	.hw_data (1'b0),
192	.cp (clk),
193	.q (prfc_csrbus_read_data[3])
194	);
195
196	// bit 4
197	csr_sw csr_sw_4
198	(
199	// synopsys translate_off
200	.omni_ld (omni_ld),
201	.omni_data (omni_data[4]),
202	.omni_rw_alias (1'b1),
203	.omni_rw1c_alias (1'b0),
204	.omni_rw1s_alias (1'b0),
205	// synopsys translate_on
206	.rst (rst_l_active_high),
207	.rst_val (reset_sel0[4]),
208	.csr_ld (w_ld),
209	.csr_data (csrbus_wr_data[4]),
210	.rw_alias (1'b1),
211	.rw1c_alias (1'b0),
212	.rw1s_alias (1'b0),
213	.hw_ld (1'b0),
214	.hw_data (1'b0),
215	.cp (clk),
216	.q (prfc_csrbus_read_data[4])
217	);
218
219	// bit 5
220	csr_sw csr_sw_5
221	(
222	// synopsys translate_off
223	.omni_ld (omni_ld),
224	.omni_data (omni_data[5]),
225	.omni_rw_alias (1'b1),
226	.omni_rw1c_alias (1'b0),
227	.omni_rw1s_alias (1'b0),
228	// synopsys translate_on
229	.rst (rst_l_active_high),
230	.rst_val (reset_sel0[5]),
231	.csr_ld (w_ld),
232	.csr_data (csrbus_wr_data[5]),
233	.rw_alias (1'b1),
234	.rw1c_alias (1'b0),
235	.rw1s_alias (1'b0),
236	.hw_ld (1'b0),
237	.hw_data (1'b0),
238	.cp (clk),
239	.q (prfc_csrbus_read_data[5])
240	);
241
242	// bit 6
243	csr_sw csr_sw_6
244	(
245	// synopsys translate_off
246	.omni_ld (omni_ld),
247	.omni_data (omni_data[6]),
248	.omni_rw_alias (1'b1),
249	.omni_rw1c_alias (1'b0),
250	.omni_rw1s_alias (1'b0),
251	// synopsys translate_on
252	.rst (rst_l_active_high),
253	.rst_val (reset_sel0[6]),
254	.csr_ld (w_ld),
255	.csr_data (csrbus_wr_data[6]),
256	.rw_alias (1'b1),
257	.rw1c_alias (1'b0),
258	.rw1s_alias (1'b0),
259	.hw_ld (1'b0),
260	.hw_data (1'b0),
261	.cp (clk),
262	.q (prfc_csrbus_read_data[6])
263	);
264
265	// bit 7
266	csr_sw csr_sw_7
267	(
268	// synopsys translate_off
269	.omni_ld (omni_ld),
270	.omni_data (omni_data[7]),
271	.omni_rw_alias (1'b1),
272	.omni_rw1c_alias (1'b0),
273	.omni_rw1s_alias (1'b0),
274	// synopsys translate_on
275	.rst (rst_l_active_high),
276	.rst_val (reset_sel0[7]),
277	.csr_ld (w_ld),
278	.csr_data (csrbus_wr_data[7]),
279	.rw_alias (1'b1),
280	.rw1c_alias (1'b0),
281	.rw1s_alias (1'b0),
282	.hw_ld (1'b0),
283	.hw_data (1'b0),
284	.cp (clk),
285	.q (prfc_csrbus_read_data[7])
286	);
287
288	// bit 8
289	csr_sw csr_sw_8
290	(
291	// synopsys translate_off
292	.omni_ld (omni_ld),
293	.omni_data (omni_data[8]),
294	.omni_rw_alias (1'b1),
295	.omni_rw1c_alias (1'b0),
296	.omni_rw1s_alias (1'b0),
297	// synopsys translate_on
298	.rst (rst_l_active_high),
299	.rst_val (reset_sel1[0]),
300	.csr_ld (w_ld),
301	.csr_data (csrbus_wr_data[8]),
302	.rw_alias (1'b1),
303	.rw1c_alias (1'b0),
304	.rw1s_alias (1'b0),
305	.hw_ld (1'b0),
306	.hw_data (1'b0),
307	.cp (clk),
308	.q (prfc_csrbus_read_data[8])
309	);
310
311	// bit 9
312	csr_sw csr_sw_9
313	(
314	// synopsys translate_off
315	.omni_ld (omni_ld),
316	.omni_data (omni_data[9]),
317	.omni_rw_alias (1'b1),
318	.omni_rw1c_alias (1'b0),
319	.omni_rw1s_alias (1'b0),
320	// synopsys translate_on
321	.rst (rst_l_active_high),
322	.rst_val (reset_sel1[1]),
323	.csr_ld (w_ld),
324	.csr_data (csrbus_wr_data[9]),
325	.rw_alias (1'b1),
326	.rw1c_alias (1'b0),
327	.rw1s_alias (1'b0),
328	.hw_ld (1'b0),
329	.hw_data (1'b0),
330	.cp (clk),
331	.q (prfc_csrbus_read_data[9])
332	);
333
334	// bit 10
335	csr_sw csr_sw_10
336	(
337	// synopsys translate_off
338	.omni_ld (omni_ld),
339	.omni_data (omni_data[10]),
340	.omni_rw_alias (1'b1),
341	.omni_rw1c_alias (1'b0),
342	.omni_rw1s_alias (1'b0),
343	// synopsys translate_on
344	.rst (rst_l_active_high),
345	.rst_val (reset_sel1[2]),
346	.csr_ld (w_ld),
347	.csr_data (csrbus_wr_data[10]),
348	.rw_alias (1'b1),
349	.rw1c_alias (1'b0),
350	.rw1s_alias (1'b0),
351	.hw_ld (1'b0),
352	.hw_data (1'b0),
353	.cp (clk),
354	.q (prfc_csrbus_read_data[10])
355	);
356
357	// bit 11
358	csr_sw csr_sw_11
359	(
360	// synopsys translate_off
361	.omni_ld (omni_ld),
362	.omni_data (omni_data[11]),
363	.omni_rw_alias (1'b1),
364	.omni_rw1c_alias (1'b0),
365	.omni_rw1s_alias (1'b0),
366	// synopsys translate_on
367	.rst (rst_l_active_high),
368	.rst_val (reset_sel1[3]),
369	.csr_ld (w_ld),
370	.csr_data (csrbus_wr_data[11]),
371	.rw_alias (1'b1),
372	.rw1c_alias (1'b0),
373	.rw1s_alias (1'b0),
374	.hw_ld (1'b0),
375	.hw_data (1'b0),
376	.cp (clk),
377	.q (prfc_csrbus_read_data[11])
378	);
379
380	// bit 12
381	csr_sw csr_sw_12
382	(
383	// synopsys translate_off
384	.omni_ld (omni_ld),
385	.omni_data (omni_data[12]),
386	.omni_rw_alias (1'b1),
387	.omni_rw1c_alias (1'b0),
388	.omni_rw1s_alias (1'b0),
389	// synopsys translate_on
390	.rst (rst_l_active_high),
391	.rst_val (reset_sel1[4]),
392	.csr_ld (w_ld),
393	.csr_data (csrbus_wr_data[12]),
394	.rw_alias (1'b1),
395	.rw1c_alias (1'b0),
396	.rw1s_alias (1'b0),
397	.hw_ld (1'b0),
398	.hw_data (1'b0),
399	.cp (clk),
400	.q (prfc_csrbus_read_data[12])
401	);
402
403	// bit 13
404	csr_sw csr_sw_13
405	(
406	// synopsys translate_off
407	.omni_ld (omni_ld),
408	.omni_data (omni_data[13]),
409	.omni_rw_alias (1'b1),
410	.omni_rw1c_alias (1'b0),
411	.omni_rw1s_alias (1'b0),
412	// synopsys translate_on
413	.rst (rst_l_active_high),
414	.rst_val (reset_sel1[5]),
415	.csr_ld (w_ld),
416	.csr_data (csrbus_wr_data[13]),
417	.rw_alias (1'b1),
418	.rw1c_alias (1'b0),
419	.rw1s_alias (1'b0),
420	.hw_ld (1'b0),
421	.hw_data (1'b0),
422	.cp (clk),
423	.q (prfc_csrbus_read_data[13])
424	);
425
426	// bit 14
427	csr_sw csr_sw_14
428	(
429	// synopsys translate_off
430	.omni_ld (omni_ld),
431	.omni_data (omni_data[14]),
432	.omni_rw_alias (1'b1),
433	.omni_rw1c_alias (1'b0),
434	.omni_rw1s_alias (1'b0),
435	// synopsys translate_on
436	.rst (rst_l_active_high),
437	.rst_val (reset_sel1[6]),
438	.csr_ld (w_ld),
439	.csr_data (csrbus_wr_data[14]),
440	.rw_alias (1'b1),
441	.rw1c_alias (1'b0),
442	.rw1s_alias (1'b0),
443	.hw_ld (1'b0),
444	.hw_data (1'b0),
445	.cp (clk),
446	.q (prfc_csrbus_read_data[14])
447	);
448
449	// bit 15
450	csr_sw csr_sw_15
451	(
452	// synopsys translate_off
453	.omni_ld (omni_ld),
454	.omni_data (omni_data[15]),
455	.omni_rw_alias (1'b1),
456	.omni_rw1c_alias (1'b0),
457	.omni_rw1s_alias (1'b0),
458	// synopsys translate_on
459	.rst (rst_l_active_high),
460	.rst_val (reset_sel1[7]),
461	.csr_ld (w_ld),
462	.csr_data (csrbus_wr_data[15]),
463	.rw_alias (1'b1),
464	.rw1c_alias (1'b0),
465	.rw1s_alias (1'b0),
466	.hw_ld (1'b0),
467	.hw_data (1'b0),
468	.cp (clk),
469	.q (prfc_csrbus_read_data[15])
470	);
471
472	assign prfc_csrbus_read_data[16] = 1'b0; // bit 16
473	assign prfc_csrbus_read_data[17] = 1'b0; // bit 17
474	assign prfc_csrbus_read_data[18] = 1'b0; // bit 18
475	assign prfc_csrbus_read_data[19] = 1'b0; // bit 19
476	assign prfc_csrbus_read_data[20] = 1'b0; // bit 20
477	assign prfc_csrbus_read_data[21] = 1'b0; // bit 21
478	assign prfc_csrbus_read_data[22] = 1'b0; // bit 22
479	assign prfc_csrbus_read_data[23] = 1'b0; // bit 23
480	assign prfc_csrbus_read_data[24] = 1'b0; // bit 24
481	assign prfc_csrbus_read_data[25] = 1'b0; // bit 25
482	assign prfc_csrbus_read_data[26] = 1'b0; // bit 26
483	assign prfc_csrbus_read_data[27] = 1'b0; // bit 27
484	assign prfc_csrbus_read_data[28] = 1'b0; // bit 28
485	assign prfc_csrbus_read_data[29] = 1'b0; // bit 29
486	assign prfc_csrbus_read_data[30] = 1'b0; // bit 30
487	assign prfc_csrbus_read_data[31] = 1'b0; // bit 31
488	assign prfc_csrbus_read_data[32] = 1'b0; // bit 32
489	assign prfc_csrbus_read_data[33] = 1'b0; // bit 33
490	assign prfc_csrbus_read_data[34] = 1'b0; // bit 34
491	assign prfc_csrbus_read_data[35] = 1'b0; // bit 35
492	assign prfc_csrbus_read_data[36] = 1'b0; // bit 36
493	assign prfc_csrbus_read_data[37] = 1'b0; // bit 37
494	assign prfc_csrbus_read_data[38] = 1'b0; // bit 38
495	assign prfc_csrbus_read_data[39] = 1'b0; // bit 39
496	assign prfc_csrbus_read_data[40] = 1'b0; // bit 40
497	assign prfc_csrbus_read_data[41] = 1'b0; // bit 41
498	assign prfc_csrbus_read_data[42] = 1'b0; // bit 42
499	assign prfc_csrbus_read_data[43] = 1'b0; // bit 43
500	assign prfc_csrbus_read_data[44] = 1'b0; // bit 44
501	assign prfc_csrbus_read_data[45] = 1'b0; // bit 45
502	assign prfc_csrbus_read_data[46] = 1'b0; // bit 46
503	assign prfc_csrbus_read_data[47] = 1'b0; // bit 47
504	assign prfc_csrbus_read_data[48] = 1'b0; // bit 48
505	assign prfc_csrbus_read_data[49] = 1'b0; // bit 49
506	assign prfc_csrbus_read_data[50] = 1'b0; // bit 50
507	assign prfc_csrbus_read_data[51] = 1'b0; // bit 51
508	assign prfc_csrbus_read_data[52] = 1'b0; // bit 52
509	assign prfc_csrbus_read_data[53] = 1'b0; // bit 53
510	assign prfc_csrbus_read_data[54] = 1'b0; // bit 54
511	assign prfc_csrbus_read_data[55] = 1'b0; // bit 55
512	assign prfc_csrbus_read_data[56] = 1'b0; // bit 56
513	assign prfc_csrbus_read_data[57] = 1'b0; // bit 57
514	assign prfc_csrbus_read_data[58] = 1'b0; // bit 58
515	assign prfc_csrbus_read_data[59] = 1'b0; // bit 59
516	assign prfc_csrbus_read_data[60] = 1'b0; // bit 60
517	assign prfc_csrbus_read_data[61] = 1'b0; // bit 61
518	assign prfc_csrbus_read_data[62] = 1'b0; // bit 62
519	assign prfc_csrbus_read_data[63] = 1'b0; // bit 63
520
521	endmodule // dmu_mmu_csr_prfc_entry