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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_qcb.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_qcb | |
36 | ( | |
37 | clk, // clock | |
38 | rst_l, // reset | |
39 | csr2qcb_ds_a, // csr debug select a | |
40 | csr2qcb_ds_b, // csr debug select b | |
41 | irb2qcb_enq, // irb srm enqueue | |
42 | orb2qcb_full, // orb isr queue full | |
43 | tcb2qcb_hld, // tcb hold | |
44 | tcb2qcb_vld, // tcb valid bits | |
45 | qcb2csr_dbg_a, // csr debug bus a | |
46 | qcb2csr_dbg_b, // csr debug bus b | |
47 | qcb2csr_paq, // csr physical address queue not empty | |
48 | qcb2csr_vaq, // csr virtual address queue not empty | |
49 | qcb2irb_full, // irb queue full | |
50 | qcb2orb_enq, // orb srm enqueue | |
51 | qcb2paq_ld, // paq load | |
52 | qcb2paq_ds, // paq data select | |
53 | qcb2rdq_ld, // rdq load | |
54 | qcb2rdq_ds, // rdq data select | |
55 | qcb2tcb_hld, // tcb hold | |
56 | qcb2tcb_vld, // tcb valid | |
57 | qcb2vaq_ld, // vaq load | |
58 | qcb2vaq_ds // vaq data select | |
59 | ); | |
60 | ||
61 | // ---------------------------------------------------------------------------- | |
62 | // Ports | |
63 | // ---------------------------------------------------------------------------- | |
64 | input clk; | |
65 | input rst_l; | |
66 | ||
67 | input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_a; | |
68 | input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_b; | |
69 | input irb2qcb_enq; | |
70 | input orb2qcb_full; | |
71 | input tcb2qcb_hld; | |
72 | input [`FIRE_DLC_MMU_PLS_DPTH:1] tcb2qcb_vld; | |
73 | ||
74 | output [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_a; | |
75 | output [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_b; | |
76 | output qcb2csr_paq; | |
77 | output qcb2csr_vaq; | |
78 | output qcb2irb_full; | |
79 | output qcb2orb_enq; | |
80 | output [`FIRE_DLC_MMU_PAQ_DPTH-1:0] qcb2paq_ld; | |
81 | output [`FIRE_DLC_MMU_PAQ_DPTH-2:0] qcb2paq_ds; | |
82 | output [`FIRE_DLC_MMU_RDQ_DPTH-1:0] qcb2rdq_ld; | |
83 | output [`FIRE_DLC_MMU_RDQ_DPTH-2:0] qcb2rdq_ds; | |
84 | output qcb2tcb_hld; | |
85 | output qcb2tcb_vld; | |
86 | output [`FIRE_DLC_MMU_VAQ_DPTH-1:0] qcb2vaq_ld; | |
87 | output [`FIRE_DLC_MMU_VAQ_DPTH-2:0] qcb2vaq_ds; | |
88 | ||
89 | // ---------------------------------------------------------------------------- | |
90 | // Variables | |
91 | // ---------------------------------------------------------------------------- | |
92 | wire [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_a; | |
93 | wire [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_b; | |
94 | wire qcb2irb_full; | |
95 | wire qcb2orb_enq; | |
96 | wire [`FIRE_DLC_MMU_PAQ_DPTH-1:0] qcb2paq_ld; | |
97 | wire [`FIRE_DLC_MMU_PAQ_DPTH-2:0] qcb2paq_ds; | |
98 | wire [`FIRE_DLC_MMU_RDQ_DPTH-1:0] qcb2rdq_ld; | |
99 | wire [`FIRE_DLC_MMU_RDQ_DPTH-2:0] qcb2rdq_ds; | |
100 | wire qcb2tcb_hld; | |
101 | wire qcb2tcb_vld; | |
102 | wire [`FIRE_DLC_MMU_VAQ_DPTH-1:0] qcb2vaq_ld; | |
103 | wire [`FIRE_DLC_MMU_VAQ_DPTH-2:0] qcb2vaq_ds; | |
104 | ||
105 | wire [`FIRE_DLC_MMU_PAQ_DPTH-1:0] qpc2qmc_vld; | |
106 | wire [`FIRE_DLC_MMU_RDQ_DPTH-1:0] qrc2qmc_vld; | |
107 | wire qmc2qpc_enq; | |
108 | wire qmc2qpc_deq; | |
109 | wire qmc2qrc_enq; | |
110 | wire qmc2qrc_deq; | |
111 | wire qmc2qvc_enq; | |
112 | wire qmc2qvc_deq; | |
113 | wire [`FIRE_DLC_MMU_VAQ_DPTH-1:0] qvc2qmc_vld; | |
114 | ||
115 | // ---------------------------------------------------------------------------- | |
116 | // Instantiations | |
117 | // ---------------------------------------------------------------------------- | |
118 | dmu_mmu_qcb_qmc qmc | |
119 | ( | |
120 | .clk (clk), | |
121 | .rst_l (rst_l), | |
122 | .csr2qcb_ds_a (csr2qcb_ds_a), | |
123 | .csr2qcb_ds_b (csr2qcb_ds_b), | |
124 | .irb2qcb_enq (irb2qcb_enq), | |
125 | .orb2qcb_full (orb2qcb_full), | |
126 | .tcb2qcb_hld (tcb2qcb_hld), | |
127 | .tcb2qcb_vld (tcb2qcb_vld), | |
128 | .qpc2qmc_vld (qpc2qmc_vld), | |
129 | .qrc2qmc_vld (qrc2qmc_vld), | |
130 | .qvc2qmc_vld (qvc2qmc_vld), | |
131 | .qcb2csr_dbg_a (qcb2csr_dbg_a), | |
132 | .qcb2csr_dbg_b (qcb2csr_dbg_b), | |
133 | .qcb2csr_paq (qcb2csr_paq), | |
134 | .qcb2csr_vaq (qcb2csr_vaq), | |
135 | .qcb2irb_full (qcb2irb_full), | |
136 | .qcb2orb_enq (qcb2orb_enq), | |
137 | .qcb2tcb_hld (qcb2tcb_hld), | |
138 | .qcb2tcb_vld (qcb2tcb_vld), | |
139 | .qmc2qpc_enq (qmc2qpc_enq), | |
140 | .qmc2qpc_deq (qmc2qpc_deq), | |
141 | .qmc2qrc_enq (qmc2qrc_enq), | |
142 | .qmc2qrc_deq (qmc2qrc_deq), | |
143 | .qmc2qvc_enq (qmc2qvc_enq), | |
144 | .qmc2qvc_deq (qmc2qvc_deq) | |
145 | ); | |
146 | ||
147 | dmu_mmu_qcb_qgc #(`FIRE_DLC_MMU_PAQ_DPTH) qpc | |
148 | ( | |
149 | .clk (clk), | |
150 | .rst_l (rst_l), | |
151 | .enq (qmc2qpc_enq), | |
152 | .deq (qmc2qpc_deq), | |
153 | .ld (qcb2paq_ld), | |
154 | .ds (qcb2paq_ds), | |
155 | .vld (qpc2qmc_vld) | |
156 | ); | |
157 | ||
158 | dmu_mmu_qcb_qgc #(`FIRE_DLC_MMU_RDQ_DPTH) qrc | |
159 | ( | |
160 | .clk (clk), | |
161 | .rst_l (rst_l), | |
162 | .enq (qmc2qrc_enq), | |
163 | .deq (qmc2qrc_deq), | |
164 | .ld (qcb2rdq_ld), | |
165 | .ds (qcb2rdq_ds), | |
166 | .vld (qrc2qmc_vld) | |
167 | ); | |
168 | ||
169 | dmu_mmu_qcb_qgc #(`FIRE_DLC_MMU_VAQ_DPTH) qvc | |
170 | ( | |
171 | .clk (clk), | |
172 | .rst_l (rst_l), | |
173 | .enq (qmc2qvc_enq), | |
174 | .deq (qmc2qvc_deq), | |
175 | .ld (qcb2vaq_ld), | |
176 | .ds (qcb2vaq_ds), | |
177 | .vld (qvc2qmc_vld) | |
178 | ); | |
179 | ||
180 | endmodule // dmu_mmu_qcb |