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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_rcb.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_rcb | |
36 | ( | |
37 | clk, // clock | |
38 | rst_l, // Synchronous reset | |
39 | j2d_mmu_addr, // jbc snoop address | |
40 | j2d_mmu_addr_vld, // jbc snoop address valid | |
41 | cl2mm_tcr_ack, // clu tcr acknowledge | |
42 | cl2mm_tdr_rcd, // clu tdr record | |
43 | cl2mm_tdr_vld, // clu tdr valid | |
44 | csr2rcb_se, // csr snoop enable | |
45 | // csr2rcb_tb, // csr tsb base address | |
46 | // csr2rcb_ts, // csr tsb size | |
47 | tcb2rcb_tag, // tcb tcr tag | |
48 | tcb2rcb_req, // tcb tcr request | |
49 | tlb2rcb_addr, // tlb tcr address | |
50 | // d2j_tsb_enable, // jbc tsb snoop enable | |
51 | // d2j_tsb_base, // jbc tsb base address | |
52 | // d2j_tsb_size, // jbc tsb size | |
53 | mm2cl_tcr_rcd, // clu tcr record | |
54 | mm2cl_tcr_req, // clu tcr request | |
55 | rcb2ptb_addr, // ptb snoop address | |
56 | rcb2ptb_vld, // ptb snoop valid | |
57 | rcb2tcb_ack, // tcb tcr acknowledge | |
58 | rcb2tcb_err, // tcb tdr errors | |
59 | rcb2tcb_tag, // tcb tdr tag | |
60 | rcb2tcb_vld, // tcb tdr valid | |
61 | rcb2tlb_dhi, // tlb tdr data high | |
62 | rcb2tlb_dlo // tlb tdr data low | |
63 | ); | |
64 | ||
65 | // ---------------------------------------------------------------------------- | |
66 | // Ports | |
67 | // ---------------------------------------------------------------------------- | |
68 | input clk; | |
69 | input rst_l; | |
70 | ||
71 | input [`FIRE_J2D_MMU_ADDR_BITS] j2d_mmu_addr; | |
72 | input j2d_mmu_addr_vld; | |
73 | input cl2mm_tcr_ack; | |
74 | input [`FIRE_DLC_TDR_BITS] cl2mm_tdr_rcd; | |
75 | input cl2mm_tdr_vld; | |
76 | input csr2rcb_se; | |
77 | // input [`FIRE_DLC_MMU_CSR_TB_BITS] csr2rcb_tb; | |
78 | // input [`FIRE_DLC_MMU_CSR_TS_BITS] csr2rcb_ts; | |
79 | input [`FIRE_DLC_MMU_TAG_PTR_BITS] tcb2rcb_tag; | |
80 | input tcb2rcb_req; | |
81 | input [`FIRE_DLC_MMU_PTD_TAG_BITS] tlb2rcb_addr; | |
82 | ||
83 | // output d2j_tsb_enable; | |
84 | // output [`FIRE_D2J_TSB_BASE_BITS] d2j_tsb_base; | |
85 | // output [`FIRE_D2J_TSB_SIZE_BITS] d2j_tsb_size; | |
86 | output [`FIRE_DLC_TCR_BITS] mm2cl_tcr_rcd; | |
87 | output mm2cl_tcr_req; | |
88 | output [`FIRE_DLC_MMU_PTD_TAG_BITS] rcb2ptb_addr; | |
89 | output rcb2ptb_vld; | |
90 | output rcb2tcb_ack; | |
91 | output [`FIRE_DLC_MMU_RCB_ERR_BITS] rcb2tcb_err; | |
92 | output [`FIRE_DLC_MMU_TAG_PTR_BITS] rcb2tcb_tag; | |
93 | output rcb2tcb_vld; | |
94 | output [`FIRE_DLC_MMU_TDR_DATA_BITS] rcb2tlb_dhi; | |
95 | output [`FIRE_DLC_MMU_TDR_DATA_BITS] rcb2tlb_dlo; | |
96 | ||
97 | // ---------------------------------------------------------------------------- | |
98 | // Variables | |
99 | // ---------------------------------------------------------------------------- | |
100 | // wire [`FIRE_D2J_TSB_BASE_BITS] d2j_tsb_base; | |
101 | // wire [`FIRE_D2J_TSB_SIZE_BITS] d2j_tsb_size; | |
102 | wire [`FIRE_DLC_TCR_BITS] mm2cl_tcr_rcd; | |
103 | wire [`FIRE_DLC_MMU_RCB_ERR_BITS] rcb2tcb_err; | |
104 | wire [`FIRE_DLC_MMU_TAG_PTR_BITS] rcb2tcb_tag; | |
105 | wire [`FIRE_DLC_MMU_TDR_DATA_BITS] rcb2tlb_dhi, rcb2tlb_dlo; | |
106 | wire [127:0] data; | |
107 | wire [3:0] dpar, dpe; | |
108 | ||
109 | reg [`FIRE_DLC_MMU_PTD_TAG_BITS] rcb2ptb_addr; | |
110 | reg rcb2ptb_vld; | |
111 | ||
112 | // ---------------------------------------------------------------------------- | |
113 | // Zero In Checkers | |
114 | // ---------------------------------------------------------------------------- | |
115 | ||
116 | // 0in odd_parity -var {data[127:96], dpar[3]} -active cl2mm_tdr_vld | |
117 | // 0in odd_parity -var {data[95:64], dpar[2]} -active cl2mm_tdr_vld | |
118 | // 0in odd_parity -var {data[63:32], dpar[1]} -active cl2mm_tdr_vld | |
119 | // 0in odd_parity -var {data[31:0], dpar[0]} -active cl2mm_tdr_vld | |
120 | ||
121 | // ---------------------------------------------------------------------------- | |
122 | // Combinational | |
123 | // ---------------------------------------------------------------------------- | |
124 | ||
125 | // jbc tsb enable, base, and size | |
126 | // wire d2j_tsb_enable = csr2rcb_se; | |
127 | // assign d2j_tsb_base = csr2rcb_tb; | |
128 | // assign d2j_tsb_size = csr2rcb_ts; | |
129 | ||
130 | // clu tablewalk command request record | |
131 | assign mm2cl_tcr_rcd[`FIRE_DLC_TCR_MTAG_BITS] = tcb2rcb_tag; | |
132 | assign mm2cl_tcr_rcd[`FIRE_DLC_TCR_ADDR_BITS] = { {4{1'b0}},tlb2rcb_addr}; | |
133 | ||
134 | // clu tablewalk command record request and acknowledge | |
135 | wire mm2cl_tcr_req = tcb2rcb_req; | |
136 | wire rcb2tcb_ack = cl2mm_tcr_ack; | |
137 | ||
138 | // tdr record parsing | |
139 | assign data = cl2mm_tdr_rcd[`FIRE_DLC_TDR_DATA_BITS]; | |
140 | assign dpar = cl2mm_tdr_rcd[`FIRE_DLC_TDR_DPAR_BITS]; | |
141 | ||
142 | // dpe is data parity error bits, one per 32 bits of data | |
143 | assign dpe[3] = ^data[127:96] ^ ~dpar[3]; | |
144 | assign dpe[2] = ^data[95:64] ^ ~dpar[2]; | |
145 | assign dpe[1] = ^data[63:32] ^ ~dpar[1]; | |
146 | assign dpe[0] = ^data[31:0] ^ ~dpar[0]; | |
147 | ||
148 | // tcb tablewalk mtag | |
149 | assign rcb2tcb_tag = cl2mm_tdr_rcd[`FIRE_DLC_TDR_MTAG_BITS]; | |
150 | ||
151 | // tcb tablewalk valid | |
152 | wire rcb2tcb_vld = cl2mm_tdr_vld; | |
153 | ||
154 | // tcb tablewalk errors | |
155 | assign rcb2tcb_err[0] = cl2mm_tdr_rcd[`FIRE_DLC_TDR_CERR_BITS]; | |
156 | assign rcb2tcb_err[1] = cl2mm_tdr_rcd[`FIRE_DLC_TDR_DERR_BITS]; | |
157 | assign rcb2tcb_err[2] = |dpe; | |
158 | ||
159 | // tlb tablewalk data | |
160 | assign rcb2tlb_dhi[`FIRE_DLC_MMU_TDR_KEY_BITS] = data[`FIRE_DLC_MMU_TDD_KEY_BITS]; // 16-bit Key value | |
161 | assign rcb2tlb_dhi[`FIRE_DLC_MMU_TDR_PPN_BITS] = data[`FIRE_DLC_MMU_TDD_PPN_BITS]; // physical page number | |
162 | assign rcb2tlb_dhi[`FIRE_DLC_MMU_TDR_FNM_BITS] = data[`FIRE_DLC_MMU_TDD_FNM_BITS]; // 3-bit Function Number | |
163 | assign rcb2tlb_dhi[`FIRE_DLC_MMU_TDR_KEYVLD_BITS] = data[`FIRE_DLC_MMU_TDD_KEYVLD_BITS]; // valKeyid | |
164 | assign rcb2tlb_dhi[`FIRE_DLC_MMU_TDR_WRT_BITS] = data[`FIRE_DLC_MMU_TDD_WRT_BITS]; // write enable | |
165 | assign rcb2tlb_dhi[`FIRE_DLC_MMU_TDR_VLD_BITS] = data[`FIRE_DLC_MMU_TDD_VLD_BITS]; // valid | |
166 | ||
167 | wire [63:0] datalo = data[127:64]; | |
168 | ||
169 | assign rcb2tlb_dlo[`FIRE_DLC_MMU_TDR_KEY_BITS] = datalo[`FIRE_DLC_MMU_TDD_KEY_BITS]; // 16-bit Key value | |
170 | assign rcb2tlb_dlo[`FIRE_DLC_MMU_TDR_PPN_BITS] = datalo[`FIRE_DLC_MMU_TDD_PPN_BITS]; // physical page number | |
171 | assign rcb2tlb_dlo[`FIRE_DLC_MMU_TDR_FNM_BITS] = datalo[`FIRE_DLC_MMU_TDD_FNM_BITS]; // 3-bit Function Number | |
172 | assign rcb2tlb_dlo[`FIRE_DLC_MMU_TDR_KEYVLD_BITS] = datalo[`FIRE_DLC_MMU_TDD_KEYVLD_BITS]; // valKeyid | |
173 | assign rcb2tlb_dlo[`FIRE_DLC_MMU_TDR_WRT_BITS] = datalo[`FIRE_DLC_MMU_TDD_WRT_BITS]; // write enable | |
174 | assign rcb2tlb_dlo[`FIRE_DLC_MMU_TDR_VLD_BITS] = datalo[`FIRE_DLC_MMU_TDD_VLD_BITS]; // valid | |
175 | // assign rcb2tlb_dlo[31:2] = {4'b0,data[102:77]}; // physical page number | |
176 | // assign rcb2tlb_dlo[1] = data[65]; // write enable | |
177 | // assign rcb2tlb_dlo[0] = data[64]; // valid | |
178 | ||
179 | // ---------------------------------------------------------------------------- | |
180 | // Sequential | |
181 | // ---------------------------------------------------------------------------- | |
182 | always @ (posedge clk) | |
183 | if(~rst_l) begin | |
184 | rcb2ptb_addr <= {`FIRE_DLC_MMU_PTD_TAG_WDTH{1'b0}}; | |
185 | rcb2ptb_vld <= {{1'b0}}; | |
186 | end | |
187 | else begin | |
188 | rcb2ptb_addr <= j2d_mmu_addr[38:6]; | |
189 | rcb2ptb_vld <= j2d_mmu_addr_vld & csr2rcb_se; | |
190 | end | |
191 | ||
192 | endmodule // dmu_mmu_rcb |