[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_psb.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_psb.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
module dmu_psb 
  (
   // Control Signals
   clk,
   rst_l,

   // PMU PRM interface
   pm2ps_i_req,
   pm2ps_i_cmd_type,
   pm2ps_i_trn,
   pm2ps_i_wr_data,
   
   ps2pm_i_full,
   ps2pm_i_gnt,
   ps2pm_i_n_trn,
   ps2pm_i_rd_data,

   //CLU CRM interface
   cl2ps_e_req,
   cl2ps_e_cmd_type, 
   cl2ps_e_trn,
   cl2ps_e_wr_data,

   ps2cl_e_gnt,
   ps2cl_e_rd_data,
   
   // CSR interface
   
   cr2ps_csrbus_valid,
   cr2ps_csrbus_src_bus,
   cr2ps_csrbus_addr,
   cr2ps_csrbus_wr,
   cr2ps_csrbus_wr_data,
   
   ps2cr_csrbus_mapped,
   ps2cr_csrbus_read_data,
   ps2cr_csrbus_done,
   ps2cr_csrbus_acc_vio,
   j2d_instance_id,

   // Debug Ports
   cr2ps_dbg_sel_a,
   cr2ps_dbg_sel_b,

   ps2cr_dbg_a,
   ps2cr_dbg_b

   );
  
  // synopsys sync_set_reset "rst_l"
  
  //////////////////////////////////////////////////////////////////////
  //*************************   Port Declarations   *******************
  //////////////////////////////////////////////////////////////////////
  
  // Control signals
  input                                       clk;
  input 				      rst_l;

  // Debug Ports
  input [5:0] 				      cr2ps_dbg_sel_a;
  input [5:0] 				      cr2ps_dbg_sel_b;
  
  output [`FIRE_DBG_DATA_BITS] 		      ps2cr_dbg_a;
  output [`FIRE_DBG_DATA_BITS] 		      ps2cr_dbg_b;


  // PMU's PRM Interface Signals
  input 				      pm2ps_i_req;        // PRM request for access 
  input [`FIRE_DLC_PSR_CMD_TYPE_WDTH-1:0]     pm2ps_i_cmd_type;   // type of access requested (TRN req w/ Write)
  input [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      pm2ps_i_trn;        // pktag to be read from
  input [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0]     pm2ps_i_wr_data;    // dma wr data to be put on scbd
  
  output 				      ps2pm_i_full;       // flow control, no request for pktag can be made
  output [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      ps2pm_i_n_trn;      // next pktag returned on trn request
  output 				      ps2pm_i_gnt;        // grant signal for request
  output [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0]    ps2pm_i_rd_data;    // pio data read from scbd (pktag is address read from)
  
  // CLU's CRM Interface Signals
  input 				      cl2ps_e_req;        // CRM request for access 
  input [`FIRE_DLC_PSR_CMD_TYPE_WDTH-1:0]     cl2ps_e_cmd_type;   // type of access requested (Read, Write, Clear, Read w/ Clear)
  input [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      cl2ps_e_trn;        // pktag to be cleared, read from or written to
  input [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0]     cl2ps_e_wr_data;   // dma wr data to be put on scoreboard
  
  output 				      ps2cl_e_gnt;        // grant signal for request
  output [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0]    ps2cl_e_rd_data;    // data read from scbd (pktag is address read from)
  
  // CRU's DCC PIO Interface Signals 
  input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0]      cr2ps_csrbus_src_bus; 
  input 				      cr2ps_csrbus_valid;
  input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] 	      cr2ps_csrbus_addr;
  input 				      cr2ps_csrbus_wr; 
  input [`FIRE_CSR_DATA_WIDTH-1:0] 	      cr2ps_csrbus_wr_data;
  input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0]      j2d_instance_id; 
 
  output [`FIRE_CSR_DATA_WIDTH-1:0] 	      ps2cr_csrbus_read_data;
  output 				      ps2cr_csrbus_done;
  output 				      ps2cr_csrbus_mapped; 
  output 				      ps2cr_csrbus_acc_vio;
  
  //////////////////////////////////////////////////////////////////////
  //*************************    Wires   ******************************* 
  //////////////////////////////////////////////////////////////////////  
  
  // PIC-PTG Interface
  wire 					      pic2ptg_deq;        // dequeue next pktag 
  wire 					      ptg2pic_pktag_full; // flow control from PTG to controller, no more pktags
  wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      ptg2pic_n_pktag;    // pktag returned to controller on deq
  
  // PCE-PTG Interface
  wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      pce2ptg_pktag;      // pktag retired on enq
  wire 					      pce2ptg_enq;        // enqueue pktag (clear/retire)
  
  // PIC-PDL Interface for DMA Write data
  wire 					      pic2pdl_req;        // PIC req
  wire 					      pic2pdl_dma_wr;     // dma write enable
  wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      pic2pdl_pktag;      // pic-pdl wr address decode select
  wire 					      pic2pdl_type;       // type to pdl to determine  pio or dma
  wire [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0]      pic2pdl_dma_wr_data;// dma data to wr to scbd

  // PIC-PDL Interface for PIO Read
  wire [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0]      pdl2pic_pio_rd_data;// pio data to rd from scbd
  
  // PCE-PDL Interface for Write data
  wire 					      pce2pdl_req;        // PCE req
  wire 					      pce2pdl_pio_wr;     // pio write enable
  wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      pce2pdl_pktag;      // pce-pdl rd/wr address decode select
  wire 					      pce2pdl_type;       // type to pdl to determine pio or dma
  wire [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0]      pce2pdl_pio_wr_data;// pio/dma data to wr to scbd

  // PCE-PDL Interface for DMA read
  wire [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0]      pdl2pce_dma_rd_data;// dma read date from pdl

  // CSR Interface
  wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] 	      ext_addr;            // External address bus for dcm dlc_psb
  wire 					      psb_dma_ext_done;    // acknowledges rd and wr operations for psb_dma.
  wire 					      psb_pio_ext_done;    // acknowledges rd and wr operations for psb_pio.
  wire 					      psb_dma_ext_select;  // When set, register psb_dma is selected.
  wire [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0]      psb_dma_ext_rd_data; // Read data from the external bypass dma register
  wire 					      psb_pio_ext_select;  // When set, register psb_pio is selected.
  wire [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0]      psb_pio_ext_rd_data; // Read data from the external bypass pio register

  // Debug Port Interface
  // PSB 
  wire [5:0] 				      cr2ps_dbg_sel_a;   // PSB debug select a
  wire [5:0] 				      cr2ps_dbg_sel_b;   // PSB debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      ps2cr_dbg_a;       // PSB debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      ps2cr_dbg_b;       // PSB debug output b
   
   // PTG
  wire [2:0] 				      dbg2ptg_dbg_sel_a; // PTG debug select a
  wire [2:0] 				      dbg2ptg_dbg_sel_b; // PTG debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      ptg2dbg_dbg_a;     // PTG debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      ptg2dbg_dbg_b;     // PTG debug output b
   
   // PDL
  wire [2:0] 				      dbg2pdl_dbg_sel_a; // PDL debug select a
  wire [2:0] 				      dbg2pdl_dbg_sel_b; // PDL debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      pdl2dbg_dbg_a;     // PDL debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      pdl2dbg_dbg_b;     // PDL debug output b
   
   // PIC
  wire [2:0] 				      dbg2pic_dbg_sel_a; // PIC debug select a
  wire [2:0] 				      dbg2pic_dbg_sel_b; // PIC debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      pic2dbg_dbg_a;     // PIC debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      pic2dbg_dbg_b;     // PIC debug output b
   
   // PCE 
  wire [2:0] 				      dbg2pce_dbg_sel_a; // PCE debug select a
  wire [2:0] 				      dbg2pce_dbg_sel_b; // PCE debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      pce2dbg_dbg_a;     // PCE debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      pce2dbg_dbg_b;     // PCE debug output b
  
  //////////////////////////////////////////////////////////////////////
  //***************   Zero in Checkers  ***********************
  //////////////////////////////////////////////////////////////////////
  
  // 0in req_ack -req pm2ps_i_req -ack ps2pm_i_gnt -req_until_ack -new_req_after_ack
  // 0in req_ack -req cl2ps_e_req -ack ps2cl_e_gnt -req_until_ack -new_req_after_ack
  
  // 0in known_driven -var pm2ps_i_req
  // 0in known_driven -var pm2ps_i_cmd_type -active pm2ps_i_req
  // 0in known_driven -var pm2ps_i_trn -active pm2ps_i_req
  // 0in known_driven -var pm2ps_i_wr_data -active pm2ps_i_req
  // 0in known_driven -var ps2pm_i_full
  // 0in known_driven -var ps2pm_i_gnt
  // 0in known_driven -var ps2pm_i_n_trn -active ps2pm_i_gnt
  // 0in known_driven -var ps2pm_i_rd_data -active ps2pm_i_gnt
  
  // 0in known_driven -var cl2ps_e_req
  // 0in known_driven -var cl2ps_e_cmd_type -active cl2ps_e_req
  // 0in known_driven -var cl2ps_e_trn -active cl2ps_e_req
  // 0in known_driven -var cl2ps_e_wr_data -active (cl2ps_e_req & cl2ps_e_cmd_type[3])
  // 0in known_driven -var ps2cl_e_gnt
  // 0in known_driven -var ps2cl_e_rd_data -active ps2cl_e_gnt

// PIO memory access checker
  /* 0in memory_access 
     -read  (pm2ps_i_req & (pm2ps_i_cmd_type == 4'b1001) & ps2pm_i_gnt)
     -write (cl2ps_e_req & (cl2ps_e_cmd_type == 4'b1100) & ps2cl_e_gnt)
     -read_addr pm2ps_i_trn[3:0] 
     -write_addr cl2ps_e_trn[3:0] 
     -initialized
     -single_write
     -single_read
     -read_data ps2pm_i_rd_data[6:0]
     -write_data cl2ps_e_wr_data[6:0]
   */
//     -read_data ps2pm_i_rd_data[5:0]
//BP n2 5-24-04
//     -write_data cl2ps_e_wr_data[5:0]

// DMA memory access checker
  /* 0in memory_access 
     -read (cl2ps_e_req & (cl2ps_e_cmd_type == 4'b0011) & ps2cl_e_gnt)
     -write (pm2ps_i_req & (pm2ps_i_cmd_type == 4'b0101) & ps2pm_i_gnt)
     -read_addr cl2ps_e_trn
     -write_addr ps2pm_i_n_trn
     -initialized
     -single_write
     -single_read
     -read_data ps2cl_e_rd_data
     -write_data pm2ps_i_wr_data
     */

  //////////////////////////////////////////////////////////////////////
  //***************   Submodule Instantiations   ***********************
  //////////////////////////////////////////////////////////////////////
   
  //*************************************************************
  // PTG (Packet Tag Generator)
  //*************************************************************
  
  
  dmu_psb_ptg ptg
    (
     // Control Signals    
     .clk                   (clk), 
     .rst_l                 (rst_l),
     
     // PIC-TTG INTERFACE
     // PIC-TTG Interface (Internal Input from PIC to PTG)
     .tag_deq               (pic2ptg_deq),                        // dequeue next pktag 
     
     // PTG-PIC Interface (Internal Output to PIC)
     .no_tag_avail          (ptg2pic_pktag_full),                 // no transaction tags available for issue
     .tag_issue             (ptg2pic_n_pktag),                    // next pktag to issue
     
     // PCE-PTG Interface (Internal Input from PCE to PTG)
     .tag_enq               (pce2ptg_enq),                        // enqueue pktag (Clear / Retire)
     .tag_retire            (pce2ptg_pktag),                      // packet tag to retire from pce controller

     // Debug Ports
     .ptg2dbg_dbg_a         (ptg2dbg_dbg_a),
     .ptg2dbg_dbg_b         (ptg2dbg_dbg_b),
     .dbg2ptg_dbg_sel_a     (dbg2ptg_dbg_sel_a),
     .dbg2ptg_dbg_sel_b     (dbg2ptg_dbg_sel_b)
          
     );
  
  //*************************************************************
  // PIC (Packet Ingress Scoreboard Controller)
  //*************************************************************
 
  // Parameters : CMD_TYPE_WIDTH, TAG_WIDTH, WR_DATA_WIDTH, RD_DATA_WIDTH
//BP n2 5-25-04
//  dmu_common_scoreboard_controller #(4,5,41,6) pic
  dmu_common_scoreboard_controller #(4,5,41,7) pic
    (
     // Control Signals     
     .clk            (clk),
     .rst_l          (rst_l),
     
     // PRM INTERFACE (PRM Command Type is Read and TRN request w/ write)
     // PMU's PRM-PIC Interface (External Input from PRM to PIC)
     .req_in         (pm2ps_i_req),                               // request for access
     .cmd_type_in    (pm2ps_i_cmd_type),                          // type of action requested (Read, TRN request w/ write)
     .trn_in         (pm2ps_i_trn),                               // pktag                    (for Read)
     .wr_data_in     (pm2ps_i_wr_data),                           // DMA data to be written to the scoreboard
     
     // PIC-PMU's PRM (External Output to PRM)
     .full_out       (ps2pm_i_full),                              // no pktags available so no request can be made
     .n_trn_out      (ps2pm_i_n_trn),                             // next pktag issued to PRM
     .rd_data_out    (ps2pm_i_rd_data),                           // PIO data sent to PRM
     .grant_out      (ps2pm_i_gnt),                               // grant for prm's request
     
     // PDL-PIC INTERFACE
     // PDL-PIC (Internal Input from PDL to PIC)
     .rd_data_in     (pdl2pic_pio_rd_data),                           // PIO data read from the scoreboard
     
     // PIC-PDL (Internal Output to PDL)
     .wr1_out        (pic2pdl_dma_wr),                            // DMA write enable to PDL
     .wr2_out        (),
     .trn1_out       (pic2pdl_pktag),                             // pktag is address to read from and write to scoreboard
     .type_out       (pic2pdl_type),                              // cmd type to pdl to determine  pio or dma
     .wr_data_out    (pic2pdl_dma_wr_data),                           // DMA data written to Scoreboard
     .req_out        (pic2pdl_req),                               // PIC to PDL req
     
     // PTG INTERFACE
     // PTG-PIC (Internal Input from PTG to PIC)
     .full_in        (ptg2pic_pktag_full),                        // full signal from ptg (no packet tags available for issue)
     .n_trn_in       (ptg2pic_n_pktag),                           // next pktag to issue
     
     // PIC-PTG (Internal Output to PTG)
     .deq_out        (pic2ptg_deq),                               // dequeue next pktag for trn request
     .trn2_out       (),      
     .enq_out        (),

     // debug Ports
     .dbg_a          (pic2dbg_dbg_a),         // PIC debug output a
     .dbg_b          (pic2dbg_dbg_b),         // PIC debug output b
     .dbg_sel_a      (dbg2pic_dbg_sel_a),     // PIC debug select a
     .dbg_sel_b      (dbg2pic_dbg_sel_b)      // PIC debug select b
  
     );


  //*************************************************************
  //  PCE (Packet Egress Scoreboard Controller)
  //*************************************************************
  
  // Parameters : CMD_TYPE_WIDTH, TAG_WIDTH, WR_DATA_WIDTH, RD_DATA_WIDTH
//BP n2 5-24-04
//  dmu_common_scoreboard_controller #(4,5,6,41) pce
  dmu_common_scoreboard_controller #(4,5,7,41) pce
    (
     // Control Signals
     .clk            (clk),
     .rst_l          (rst_l),
     
     // CRM INTERFACE  (CRM command type includes Read, Write, Clear and Read w/ Clear)
     // CLU's CRM-PCE Interface (External Input from CRM to PCE)
     .req_in         (cl2ps_e_req),            // request for access
     .cmd_type_in    (cl2ps_e_cmd_type),       // type of action requested (Read, Write, Clear and Read w/ Clear)
     .trn_in         (cl2ps_e_trn),            // pktag                    (for Read, Clear and Read w/ Clear)
     .wr_data_in     (cl2ps_e_wr_data),        // DMA data to be written to the scoreboard
     
     // PCE-CLU's CRM Interface (External Output to CRM)
     .full_out       (),
     .n_trn_out      (),
     .rd_data_out    (ps2cl_e_rd_data),        // DMA data to be read from the scoreboard
     .grant_out      (ps2cl_e_gnt),            // grant for crm's request

     // PDL-PCE INTERFACE
     // PDL-PCE (Internal Input from PDL to PCE)
     .rd_data_in     (pdl2pce_dma_rd_data),        // DMA data read from PDL
     
     // PCE-PDL (Internal Output to PDL)
     .wr1_out        (),                       
     .wr2_out        (pce2pdl_pio_wr),         // pio write enable to PDL
     .trn1_out       (pce2pdl_pktag),          // pktag is address to read from and write to scoreboard
     .type_out       (pce2pdl_type),           // pio = 1 dma = 0
     .wr_data_out    (pce2pdl_pio_wr_data),    // data written to PDL
     .req_out        (pce2pdl_req),            // PCE req to PDL

     // PTG INTERFACE
     // PTG-PCE (Internal Input from PTG to PCE)
     .full_in        (1'b0),
     .n_trn_in       (5'b0),
     
     // PCE-PTG (Internal Output to PTG)
     .deq_out        (),
     .trn2_out       (pce2ptg_pktag),         // pktag to retire (Clear)
     .enq_out        (pce2ptg_enq),           // enqueue to retire pktag

     // debug Ports
     .dbg_a          (pce2dbg_dbg_a),         // PCE debug output a
     .dbg_b          (pce2dbg_dbg_b),         // PCE debug output b
     .dbg_sel_a      (dbg2pce_dbg_sel_a),     // PCE debug select a
     .dbg_sel_b      (dbg2pce_dbg_sel_b)      // PCE debug select b
     );

  //*************************************************************
  // PDL (PSB DECODE LOGIC and Register Storage array for Scoreboard)
  //*************************************************************

  dmu_psb_pdl pdl
    ( 
      // Control Signals
      .clk                            (clk),
      .rst_l                          (rst_l),
      
      // PIC-PDL Interface (Internal Input from PIC to PDL)
      .pic2pdl_dma_wr_in              (pic2pdl_dma_wr),
      .pic2pdl_pktag_in               (pic2pdl_pktag),
      .pic2pdl_type_in                (pic2pdl_type),
      .pic2pdl_dma_wr_data_in         (pic2pdl_dma_wr_data),
      .pic2pdl_req_in                 (pic2pdl_req),

      // Output from PDL to PIC Controller
      .pdl2pic_pio_rd_data_out        (pdl2pic_pio_rd_data),   
      
      // PCE-PDL Interface (Internal Input from PCE to PDL)
      .pce2pdl_pio_wr_in              (pce2pdl_pio_wr),
      .pce2pdl_pktag_in               (pce2pdl_pktag),
      .pce2pdl_type_in                (pce2pdl_type),
      .pce2pdl_pio_wr_data_in         (pce2pdl_pio_wr_data),
      .pce2pdl_req_in                 (pce2pdl_req),

      // Output from PDL to PCE Controller
      .pdl2pce_dma_rd_data_out        (pdl2pce_dma_rd_data),

      // CSR interface
      .ext_addr                       (ext_addr),
      .psb_dma_ext_done               (psb_dma_ext_done),
      .psb_pio_ext_done               (psb_pio_ext_done),
      .psb_dma_ext_select             (psb_dma_ext_select),
      .psb_dma_ext_rd_data            (psb_dma_ext_rd_data),
      .psb_pio_ext_select             (psb_pio_ext_select),
      .psb_pio_ext_rd_data            (psb_pio_ext_rd_data),

      // Debug Ports
      .pdl2dbg_dbg_a                  (pdl2dbg_dbg_a),
      .pdl2dbg_dbg_b                  (pdl2dbg_dbg_b),
      .dbg2pdl_dbg_sel_a              (dbg2pdl_dbg_sel_a),
      .dbg2pdl_dbg_sel_b              (dbg2pdl_dbg_sel_b)
      );
  
  //*************************************************************
  // PSB CSR Packet Scoreboard CSR's
  //*************************************************************
  
  dmu_psb_csr csr
    (
     .clk                            (clk),
     .rst_l                          (rst_l),
     .csrbus_valid                   (cr2ps_csrbus_valid),
     .csrbus_done                    (ps2cr_csrbus_done),
     .csrbus_mapped                  (ps2cr_csrbus_mapped),
     .csrbus_wr_data                 (cr2ps_csrbus_wr_data),
     .csrbus_wr                      (cr2ps_csrbus_wr),
     .csrbus_read_data               (ps2cr_csrbus_read_data),
     .csrbus_addr                    (cr2ps_csrbus_addr),
     .csrbus_src_bus                 (cr2ps_csrbus_src_bus),
     .csrbus_acc_vio                 (ps2cr_csrbus_acc_vio),
     .instance_id                    (j2d_instance_id),
     .ext_addr                       (ext_addr),
     .psb_dma_ext_done               (psb_dma_ext_done),
     .psb_pio_ext_done               (psb_pio_ext_done),
     .psb_dma_ext_select             (psb_dma_ext_select),
     .psb_dma_entry_ext_read_data    (psb_dma_ext_rd_data),
     .psb_pio_ext_select             (psb_pio_ext_select),
     .psb_pio_entry_ext_read_data    (psb_pio_ext_rd_data)
     ); 
  //*************************************************************
  // PSB Debug Module
  //*************************************************************
  dmu_psb_dbg dbg
    (
     .clk                     (clk), 	
     .rst_l                   (rst_l),

     // PSB 
     .cr2ps_dbg_sel_a         (cr2ps_dbg_sel_a),   // PSB debug select a
     .cr2ps_dbg_sel_b         (cr2ps_dbg_sel_b),   // PSB debug select b
     
     .ps2cr_dbg_a             (ps2cr_dbg_a),       // PSB debug output a
     .ps2cr_dbg_b             (ps2cr_dbg_b),       // PSB debug output b

     // PTG
     .dbg2ptg_dbg_sel_a       (dbg2ptg_dbg_sel_a), // PTG debug select a
     .dbg2ptg_dbg_sel_b       (dbg2ptg_dbg_sel_b), // PTG debug select b
     
     .ptg2dbg_dbg_a           (ptg2dbg_dbg_a),     // PTG debug output a
     .ptg2dbg_dbg_b           (ptg2dbg_dbg_b),     // PTG debug output b
     
     // PDL
     .dbg2pdl_dbg_sel_a       (dbg2pdl_dbg_sel_a), // PDL debug select a
     .dbg2pdl_dbg_sel_b       (dbg2pdl_dbg_sel_b), // PDL debug select b
     
     .pdl2dbg_dbg_a           (pdl2dbg_dbg_a),     // PDL debug output a
     .pdl2dbg_dbg_b           (pdl2dbg_dbg_b),     // PDL debug output b

     // PIC
     .dbg2pic_dbg_sel_a       (dbg2pic_dbg_sel_a), // PIC debug select a
     .dbg2pic_dbg_sel_b       (dbg2pic_dbg_sel_b), // PIC debug select b
     
     .pic2dbg_dbg_a           (pic2dbg_dbg_a),     // PIC debug output a
     .pic2dbg_dbg_b           (pic2dbg_dbg_b),     // PIC debug output b
     
     // PCE 
     .dbg2pce_dbg_sel_a       (dbg2pce_dbg_sel_a), // PCE debug select a
     .dbg2pce_dbg_sel_b       (dbg2pce_dbg_sel_b), // PCE debug select b
     
     .pce2dbg_dbg_a           (pce2dbg_dbg_a),     // PCE debug output a
     .pce2dbg_dbg_b           (pce2dbg_dbg_b)      // PCE debug output b
     );

endmodule // dmu_psb
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_psb.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_psb
	36	(
	37	// Control Signals
	38	clk,
	39	rst_l,
	40
	41	// PMU PRM interface
	42	pm2ps_i_req,
	43	pm2ps_i_cmd_type,
	44	pm2ps_i_trn,
	45	pm2ps_i_wr_data,
	46
	47	ps2pm_i_full,
	48	ps2pm_i_gnt,
	49	ps2pm_i_n_trn,
	50	ps2pm_i_rd_data,
	51
	52	//CLU CRM interface
	53	cl2ps_e_req,
	54	cl2ps_e_cmd_type,
	55	cl2ps_e_trn,
	56	cl2ps_e_wr_data,
	57
	58	ps2cl_e_gnt,
	59	ps2cl_e_rd_data,
	60
	61	// CSR interface
	62
	63	cr2ps_csrbus_valid,
	64	cr2ps_csrbus_src_bus,
65	cr2ps_csrbus_addr,
66	cr2ps_csrbus_wr,
67	cr2ps_csrbus_wr_data,
68
69	ps2cr_csrbus_mapped,
70	ps2cr_csrbus_read_data,
71	ps2cr_csrbus_done,
72	ps2cr_csrbus_acc_vio,
73	j2d_instance_id,
74
75	// Debug Ports
76	cr2ps_dbg_sel_a,
77	cr2ps_dbg_sel_b,
78
79	ps2cr_dbg_a,
80	ps2cr_dbg_b
81
82	);
83
84	// synopsys sync_set_reset "rst_l"
85
86	//////////////////////////////////////////////////////////////////////
87	//*********************** Port Declarations *****************
88	//////////////////////////////////////////////////////////////////////
89
90	// Control signals
91	input clk;
92	input rst_l;
93
94	// Debug Ports
95	input [5:0] cr2ps_dbg_sel_a;
96	input [5:0] cr2ps_dbg_sel_b;
97
98	output [`FIRE_DBG_DATA_BITS] ps2cr_dbg_a;
99	output [`FIRE_DBG_DATA_BITS] ps2cr_dbg_b;
100
101
102	// PMU's PRM Interface Signals
103	input pm2ps_i_req; // PRM request for access
104	input [`FIRE_DLC_PSR_CMD_TYPE_WDTH-1:0] pm2ps_i_cmd_type; // type of access requested (TRN req w/ Write)
105	input [`FIRE_DLC_PSR_TRN_WDTH-1:0] pm2ps_i_trn; // pktag to be read from
106	input [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0] pm2ps_i_wr_data; // dma wr data to be put on scbd
107
108	output ps2pm_i_full; // flow control, no request for pktag can be made
109	output [`FIRE_DLC_PSR_TRN_WDTH-1:0] ps2pm_i_n_trn; // next pktag returned on trn request
110	output ps2pm_i_gnt; // grant signal for request
111	output [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0] ps2pm_i_rd_data; // pio data read from scbd (pktag is address read from)
112
113	// CLU's CRM Interface Signals
114	input cl2ps_e_req; // CRM request for access
115	input [`FIRE_DLC_PSR_CMD_TYPE_WDTH-1:0] cl2ps_e_cmd_type; // type of access requested (Read, Write, Clear, Read w/ Clear)
116	input [`FIRE_DLC_PSR_TRN_WDTH-1:0] cl2ps_e_trn; // pktag to be cleared, read from or written to
117	input [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0] cl2ps_e_wr_data; // dma wr data to be put on scoreboard
118
119	output ps2cl_e_gnt; // grant signal for request
120	output [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0] ps2cl_e_rd_data; // data read from scbd (pktag is address read from)
121
122	// CRU's DCC PIO Interface Signals
123	input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] cr2ps_csrbus_src_bus;
124	input cr2ps_csrbus_valid;
125	input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] cr2ps_csrbus_addr;
126	input cr2ps_csrbus_wr;
127	input [`FIRE_CSR_DATA_WIDTH-1:0] cr2ps_csrbus_wr_data;
128	input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id;
129
130	output [`FIRE_CSR_DATA_WIDTH-1:0] ps2cr_csrbus_read_data;
131	output ps2cr_csrbus_done;
132	output ps2cr_csrbus_mapped;
133	output ps2cr_csrbus_acc_vio;
134
135	//////////////////////////////////////////////////////////////////////
136	//*********************** Wires *****************************
137	//////////////////////////////////////////////////////////////////////
138
139	// PIC-PTG Interface
140	wire pic2ptg_deq; // dequeue next pktag
141	wire ptg2pic_pktag_full; // flow control from PTG to controller, no more pktags
142	wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] ptg2pic_n_pktag; // pktag returned to controller on deq
143
144	// PCE-PTG Interface
145	wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] pce2ptg_pktag; // pktag retired on enq
146	wire pce2ptg_enq; // enqueue pktag (clear/retire)
147
148	// PIC-PDL Interface for DMA Write data
149	wire pic2pdl_req; // PIC req
150	wire pic2pdl_dma_wr; // dma write enable
151	wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] pic2pdl_pktag; // pic-pdl wr address decode select
152	wire pic2pdl_type; // type to pdl to determine pio or dma
153	wire [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0] pic2pdl_dma_wr_data;// dma data to wr to scbd
154
155	// PIC-PDL Interface for PIO Read
156	wire [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0] pdl2pic_pio_rd_data;// pio data to rd from scbd
157
158	// PCE-PDL Interface for Write data
159	wire pce2pdl_req; // PCE req
160	wire pce2pdl_pio_wr; // pio write enable
161	wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] pce2pdl_pktag; // pce-pdl rd/wr address decode select
162	wire pce2pdl_type; // type to pdl to determine pio or dma
163	wire [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0] pce2pdl_pio_wr_data;// pio/dma data to wr to scbd
164
165	// PCE-PDL Interface for DMA read
166	wire [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0] pdl2pce_dma_rd_data;// dma read date from pdl
167
168	// CSR Interface
169	wire [`FIRE_DLC_PSR_TRN_WDTH-1:0] ext_addr; // External address bus for dcm dlc_psb
170	wire psb_dma_ext_done; // acknowledges rd and wr operations for psb_dma.
171	wire psb_pio_ext_done; // acknowledges rd and wr operations for psb_pio.
172	wire psb_dma_ext_select; // When set, register psb_dma is selected.
173	wire [`FIRE_DLC_PSR_DMA_DATA_WDTH-1:0] psb_dma_ext_rd_data; // Read data from the external bypass dma register
174	wire psb_pio_ext_select; // When set, register psb_pio is selected.
175	wire [`FIRE_DLC_PSR_PIO_DATA_WDTH-1:0] psb_pio_ext_rd_data; // Read data from the external bypass pio register
176
177	// Debug Port Interface
178	// PSB
179	wire [5:0] cr2ps_dbg_sel_a; // PSB debug select a
180	wire [5:0] cr2ps_dbg_sel_b; // PSB debug select b
181
182	wire [`FIRE_DBG_DATA_BITS] ps2cr_dbg_a; // PSB debug output a
183	wire [`FIRE_DBG_DATA_BITS] ps2cr_dbg_b; // PSB debug output b
184
185	// PTG
186	wire [2:0] dbg2ptg_dbg_sel_a; // PTG debug select a
187	wire [2:0] dbg2ptg_dbg_sel_b; // PTG debug select b
188
189	wire [`FIRE_DBG_DATA_BITS] ptg2dbg_dbg_a; // PTG debug output a
190	wire [`FIRE_DBG_DATA_BITS] ptg2dbg_dbg_b; // PTG debug output b
191
192	// PDL
193	wire [2:0] dbg2pdl_dbg_sel_a; // PDL debug select a
194	wire [2:0] dbg2pdl_dbg_sel_b; // PDL debug select b
195
196	wire [`FIRE_DBG_DATA_BITS] pdl2dbg_dbg_a; // PDL debug output a
197	wire [`FIRE_DBG_DATA_BITS] pdl2dbg_dbg_b; // PDL debug output b
198
199	// PIC
200	wire [2:0] dbg2pic_dbg_sel_a; // PIC debug select a
201	wire [2:0] dbg2pic_dbg_sel_b; // PIC debug select b
202
203	wire [`FIRE_DBG_DATA_BITS] pic2dbg_dbg_a; // PIC debug output a
204	wire [`FIRE_DBG_DATA_BITS] pic2dbg_dbg_b; // PIC debug output b
205
206	// PCE
207	wire [2:0] dbg2pce_dbg_sel_a; // PCE debug select a
208	wire [2:0] dbg2pce_dbg_sel_b; // PCE debug select b
209
210	wire [`FIRE_DBG_DATA_BITS] pce2dbg_dbg_a; // PCE debug output a
211	wire [`FIRE_DBG_DATA_BITS] pce2dbg_dbg_b; // PCE debug output b
212
213	//////////////////////////////////////////////////////////////////////
214	//************* Zero in Checkers *********************
215	//////////////////////////////////////////////////////////////////////
216
217	// 0in req_ack -req pm2ps_i_req -ack ps2pm_i_gnt -req_until_ack -new_req_after_ack
218	// 0in req_ack -req cl2ps_e_req -ack ps2cl_e_gnt -req_until_ack -new_req_after_ack
219
220	// 0in known_driven -var pm2ps_i_req
221	// 0in known_driven -var pm2ps_i_cmd_type -active pm2ps_i_req
222	// 0in known_driven -var pm2ps_i_trn -active pm2ps_i_req
223	// 0in known_driven -var pm2ps_i_wr_data -active pm2ps_i_req
224	// 0in known_driven -var ps2pm_i_full
225	// 0in known_driven -var ps2pm_i_gnt
226	// 0in known_driven -var ps2pm_i_n_trn -active ps2pm_i_gnt
227	// 0in known_driven -var ps2pm_i_rd_data -active ps2pm_i_gnt
228
229	// 0in known_driven -var cl2ps_e_req
230	// 0in known_driven -var cl2ps_e_cmd_type -active cl2ps_e_req
231	// 0in known_driven -var cl2ps_e_trn -active cl2ps_e_req
232	// 0in known_driven -var cl2ps_e_wr_data -active (cl2ps_e_req & cl2ps_e_cmd_type[3])
233	// 0in known_driven -var ps2cl_e_gnt
234	// 0in known_driven -var ps2cl_e_rd_data -active ps2cl_e_gnt
235
236	// PIO memory access checker
237	/* 0in memory_access
238	-read (pm2ps_i_req & (pm2ps_i_cmd_type == 4'b1001) & ps2pm_i_gnt)
239	-write (cl2ps_e_req & (cl2ps_e_cmd_type == 4'b1100) & ps2cl_e_gnt)
240	-read_addr pm2ps_i_trn[3:0]
241	-write_addr cl2ps_e_trn[3:0]
242	-initialized
243	-single_write
244	-single_read
245	-read_data ps2pm_i_rd_data[6:0]
246	-write_data cl2ps_e_wr_data[6:0]
247	*/
248	// -read_data ps2pm_i_rd_data[5:0]
249	//BP n2 5-24-04
250	// -write_data cl2ps_e_wr_data[5:0]
251
252	// DMA memory access checker
253	/* 0in memory_access
254	-read (cl2ps_e_req & (cl2ps_e_cmd_type == 4'b0011) & ps2cl_e_gnt)
255	-write (pm2ps_i_req & (pm2ps_i_cmd_type == 4'b0101) & ps2pm_i_gnt)
256	-read_addr cl2ps_e_trn
257	-write_addr ps2pm_i_n_trn
258	-initialized
259	-single_write
260	-single_read
261	-read_data ps2cl_e_rd_data
262	-write_data pm2ps_i_wr_data
263	*/
264
265	//////////////////////////////////////////////////////////////////////
266	//************* Submodule Instantiations *********************
267	//////////////////////////////////////////////////////////////////////
268
269	//*************************************************************
270	// PTG (Packet Tag Generator)
271	//*************************************************************
272
273
274	dmu_psb_ptg ptg
275	(
276	// Control Signals
277	.clk (clk),
278	.rst_l (rst_l),
279
280	// PIC-TTG INTERFACE
281	// PIC-TTG Interface (Internal Input from PIC to PTG)
282	.tag_deq (pic2ptg_deq), // dequeue next pktag
283
284	// PTG-PIC Interface (Internal Output to PIC)
285	.no_tag_avail (ptg2pic_pktag_full), // no transaction tags available for issue
286	.tag_issue (ptg2pic_n_pktag), // next pktag to issue
287
288	// PCE-PTG Interface (Internal Input from PCE to PTG)
289	.tag_enq (pce2ptg_enq), // enqueue pktag (Clear / Retire)
290	.tag_retire (pce2ptg_pktag), // packet tag to retire from pce controller
291
292	// Debug Ports
293	.ptg2dbg_dbg_a (ptg2dbg_dbg_a),
294	.ptg2dbg_dbg_b (ptg2dbg_dbg_b),
295	.dbg2ptg_dbg_sel_a (dbg2ptg_dbg_sel_a),
296	.dbg2ptg_dbg_sel_b (dbg2ptg_dbg_sel_b)
297
298	);
299
300	//*************************************************************
301	// PIC (Packet Ingress Scoreboard Controller)
302	//*************************************************************
303
304	// Parameters : CMD_TYPE_WIDTH, TAG_WIDTH, WR_DATA_WIDTH, RD_DATA_WIDTH
305	//BP n2 5-25-04
306	// dmu_common_scoreboard_controller #(4,5,41,6) pic
307	dmu_common_scoreboard_controller #(4,5,41,7) pic
308	(
309	// Control Signals
310	.clk (clk),
311	.rst_l (rst_l),
312
313	// PRM INTERFACE (PRM Command Type is Read and TRN request w/ write)
314	// PMU's PRM-PIC Interface (External Input from PRM to PIC)
315	.req_in (pm2ps_i_req), // request for access
316	.cmd_type_in (pm2ps_i_cmd_type), // type of action requested (Read, TRN request w/ write)
317	.trn_in (pm2ps_i_trn), // pktag (for Read)
318	.wr_data_in (pm2ps_i_wr_data), // DMA data to be written to the scoreboard
319
320	// PIC-PMU's PRM (External Output to PRM)
321	.full_out (ps2pm_i_full), // no pktags available so no request can be made
322	.n_trn_out (ps2pm_i_n_trn), // next pktag issued to PRM
323	.rd_data_out (ps2pm_i_rd_data), // PIO data sent to PRM
324	.grant_out (ps2pm_i_gnt), // grant for prm's request
325
326	// PDL-PIC INTERFACE
327	// PDL-PIC (Internal Input from PDL to PIC)
328	.rd_data_in (pdl2pic_pio_rd_data), // PIO data read from the scoreboard
329
330	// PIC-PDL (Internal Output to PDL)
331	.wr1_out (pic2pdl_dma_wr), // DMA write enable to PDL
332	.wr2_out (),
333	.trn1_out (pic2pdl_pktag), // pktag is address to read from and write to scoreboard
334	.type_out (pic2pdl_type), // cmd type to pdl to determine pio or dma
335	.wr_data_out (pic2pdl_dma_wr_data), // DMA data written to Scoreboard
336	.req_out (pic2pdl_req), // PIC to PDL req
337
338	// PTG INTERFACE
339	// PTG-PIC (Internal Input from PTG to PIC)
340	.full_in (ptg2pic_pktag_full), // full signal from ptg (no packet tags available for issue)
341	.n_trn_in (ptg2pic_n_pktag), // next pktag to issue
342
343	// PIC-PTG (Internal Output to PTG)
344	.deq_out (pic2ptg_deq), // dequeue next pktag for trn request
345	.trn2_out (),
346	.enq_out (),
347
348	// debug Ports
349	.dbg_a (pic2dbg_dbg_a), // PIC debug output a
350	.dbg_b (pic2dbg_dbg_b), // PIC debug output b
351	.dbg_sel_a (dbg2pic_dbg_sel_a), // PIC debug select a
352	.dbg_sel_b (dbg2pic_dbg_sel_b) // PIC debug select b
353
354	);
355
356
357	//*************************************************************
358	// PCE (Packet Egress Scoreboard Controller)
359	//*************************************************************
360
361	// Parameters : CMD_TYPE_WIDTH, TAG_WIDTH, WR_DATA_WIDTH, RD_DATA_WIDTH
362	//BP n2 5-24-04
363	// dmu_common_scoreboard_controller #(4,5,6,41) pce
364	dmu_common_scoreboard_controller #(4,5,7,41) pce
365	(
366	// Control Signals
367	.clk (clk),
368	.rst_l (rst_l),
369
370	// CRM INTERFACE (CRM command type includes Read, Write, Clear and Read w/ Clear)
371	// CLU's CRM-PCE Interface (External Input from CRM to PCE)
372	.req_in (cl2ps_e_req), // request for access
373	.cmd_type_in (cl2ps_e_cmd_type), // type of action requested (Read, Write, Clear and Read w/ Clear)
374	.trn_in (cl2ps_e_trn), // pktag (for Read, Clear and Read w/ Clear)
375	.wr_data_in (cl2ps_e_wr_data), // DMA data to be written to the scoreboard
376
377	// PCE-CLU's CRM Interface (External Output to CRM)
378	.full_out (),
379	.n_trn_out (),
380	.rd_data_out (ps2cl_e_rd_data), // DMA data to be read from the scoreboard
381	.grant_out (ps2cl_e_gnt), // grant for crm's request
382
383	// PDL-PCE INTERFACE
384	// PDL-PCE (Internal Input from PDL to PCE)
385	.rd_data_in (pdl2pce_dma_rd_data), // DMA data read from PDL
386
387	// PCE-PDL (Internal Output to PDL)
388	.wr1_out (),
389	.wr2_out (pce2pdl_pio_wr), // pio write enable to PDL
390	.trn1_out (pce2pdl_pktag), // pktag is address to read from and write to scoreboard
391	.type_out (pce2pdl_type), // pio = 1 dma = 0
392	.wr_data_out (pce2pdl_pio_wr_data), // data written to PDL
393	.req_out (pce2pdl_req), // PCE req to PDL
394
395	// PTG INTERFACE
396	// PTG-PCE (Internal Input from PTG to PCE)
397	.full_in (1'b0),
398	.n_trn_in (5'b0),
399
400	// PCE-PTG (Internal Output to PTG)
401	.deq_out (),
402	.trn2_out (pce2ptg_pktag), // pktag to retire (Clear)
403	.enq_out (pce2ptg_enq), // enqueue to retire pktag
404
405	// debug Ports
406	.dbg_a (pce2dbg_dbg_a), // PCE debug output a
407	.dbg_b (pce2dbg_dbg_b), // PCE debug output b
408	.dbg_sel_a (dbg2pce_dbg_sel_a), // PCE debug select a
409	.dbg_sel_b (dbg2pce_dbg_sel_b) // PCE debug select b
410	);
411
412	//*************************************************************
413	// PDL (PSB DECODE LOGIC and Register Storage array for Scoreboard)
414	//*************************************************************
415
416	dmu_psb_pdl pdl
417	(
418	// Control Signals
419	.clk (clk),
420	.rst_l (rst_l),
421
422	// PIC-PDL Interface (Internal Input from PIC to PDL)
423	.pic2pdl_dma_wr_in (pic2pdl_dma_wr),
424	.pic2pdl_pktag_in (pic2pdl_pktag),
425	.pic2pdl_type_in (pic2pdl_type),
426	.pic2pdl_dma_wr_data_in (pic2pdl_dma_wr_data),
427	.pic2pdl_req_in (pic2pdl_req),
428
429	// Output from PDL to PIC Controller
430	.pdl2pic_pio_rd_data_out (pdl2pic_pio_rd_data),
431
432	// PCE-PDL Interface (Internal Input from PCE to PDL)
433	.pce2pdl_pio_wr_in (pce2pdl_pio_wr),
434	.pce2pdl_pktag_in (pce2pdl_pktag),
435	.pce2pdl_type_in (pce2pdl_type),
436	.pce2pdl_pio_wr_data_in (pce2pdl_pio_wr_data),
437	.pce2pdl_req_in (pce2pdl_req),
438
439	// Output from PDL to PCE Controller
440	.pdl2pce_dma_rd_data_out (pdl2pce_dma_rd_data),
441
442	// CSR interface
443	.ext_addr (ext_addr),
444	.psb_dma_ext_done (psb_dma_ext_done),
445	.psb_pio_ext_done (psb_pio_ext_done),
446	.psb_dma_ext_select (psb_dma_ext_select),
447	.psb_dma_ext_rd_data (psb_dma_ext_rd_data),
448	.psb_pio_ext_select (psb_pio_ext_select),
449	.psb_pio_ext_rd_data (psb_pio_ext_rd_data),
450
451	// Debug Ports
452	.pdl2dbg_dbg_a (pdl2dbg_dbg_a),
453	.pdl2dbg_dbg_b (pdl2dbg_dbg_b),
454	.dbg2pdl_dbg_sel_a (dbg2pdl_dbg_sel_a),
455	.dbg2pdl_dbg_sel_b (dbg2pdl_dbg_sel_b)
456	);
457
458	//*************************************************************
459	// PSB CSR Packet Scoreboard CSR's
460	//*************************************************************
461
462	dmu_psb_csr csr
463	(
464	.clk (clk),
465	.rst_l (rst_l),
466	.csrbus_valid (cr2ps_csrbus_valid),
467	.csrbus_done (ps2cr_csrbus_done),
468	.csrbus_mapped (ps2cr_csrbus_mapped),
469	.csrbus_wr_data (cr2ps_csrbus_wr_data),
470	.csrbus_wr (cr2ps_csrbus_wr),
471	.csrbus_read_data (ps2cr_csrbus_read_data),
472	.csrbus_addr (cr2ps_csrbus_addr),
473	.csrbus_src_bus (cr2ps_csrbus_src_bus),
474	.csrbus_acc_vio (ps2cr_csrbus_acc_vio),
475	.instance_id (j2d_instance_id),
476	.ext_addr (ext_addr),
477	.psb_dma_ext_done (psb_dma_ext_done),
478	.psb_pio_ext_done (psb_pio_ext_done),
479	.psb_dma_ext_select (psb_dma_ext_select),
480	.psb_dma_entry_ext_read_data (psb_dma_ext_rd_data),
481	.psb_pio_ext_select (psb_pio_ext_select),
482	.psb_pio_entry_ext_read_data (psb_pio_ext_rd_data)
483	);
484	//*************************************************************
485	// PSB Debug Module
486	//*************************************************************
487	dmu_psb_dbg dbg
488	(
489	.clk (clk),
490	.rst_l (rst_l),
491
492	// PSB
493	.cr2ps_dbg_sel_a (cr2ps_dbg_sel_a), // PSB debug select a
494	.cr2ps_dbg_sel_b (cr2ps_dbg_sel_b), // PSB debug select b
495
496	.ps2cr_dbg_a (ps2cr_dbg_a), // PSB debug output a
497	.ps2cr_dbg_b (ps2cr_dbg_b), // PSB debug output b
498
499	// PTG
500	.dbg2ptg_dbg_sel_a (dbg2ptg_dbg_sel_a), // PTG debug select a
501	.dbg2ptg_dbg_sel_b (dbg2ptg_dbg_sel_b), // PTG debug select b
502
503	.ptg2dbg_dbg_a (ptg2dbg_dbg_a), // PTG debug output a
504	.ptg2dbg_dbg_b (ptg2dbg_dbg_b), // PTG debug output b
505
506	// PDL
507	.dbg2pdl_dbg_sel_a (dbg2pdl_dbg_sel_a), // PDL debug select a
508	.dbg2pdl_dbg_sel_b (dbg2pdl_dbg_sel_b), // PDL debug select b
509
510	.pdl2dbg_dbg_a (pdl2dbg_dbg_a), // PDL debug output a
511	.pdl2dbg_dbg_b (pdl2dbg_dbg_b), // PDL debug output b
512
513	// PIC
514	.dbg2pic_dbg_sel_a (dbg2pic_dbg_sel_a), // PIC debug select a
515	.dbg2pic_dbg_sel_b (dbg2pic_dbg_sel_b), // PIC debug select b
516
517	.pic2dbg_dbg_a (pic2dbg_dbg_a), // PIC debug output a
518	.pic2dbg_dbg_b (pic2dbg_dbg_b), // PIC debug output b
519
520	// PCE
521	.dbg2pce_dbg_sel_a (dbg2pce_dbg_sel_a), // PCE debug select a
522	.dbg2pce_dbg_sel_b (dbg2pce_dbg_sel_b), // PCE debug select b
523
524	.pce2dbg_dbg_a (pce2dbg_dbg_a), // PCE debug output a
525	.pce2dbg_dbg_b (pce2dbg_dbg_b) // PCE debug output b
526	);
527
528	endmodule // dmu_psb