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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_psb_addr_decode.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_psb_addr_decode | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | daemon_csrbus_valid, | |
40 | daemon_csrbus_addr, | |
41 | csrbus_src_bus, | |
42 | daemon_csrbus_wr, | |
43 | daemon_csrbus_mapped, | |
44 | csrbus_acc_vio, | |
45 | daemon_transaction_in_progress, | |
46 | instance_id, | |
47 | daemon_csrbus_done, | |
48 | stage_mux_only_ext_done_0_out, | |
49 | psb_dma_select, | |
50 | psb_pio_select | |
51 | ); | |
52 | ||
53 | //==================================================================== | |
54 | // Polarity declarations | |
55 | //==================================================================== | |
56 | input clk; // Clock signal | |
57 | input rst_l; // Reset | |
58 | input daemon_csrbus_valid; // Daemon_Valid | |
59 | input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
60 | input [1:0] csrbus_src_bus; // Source bus | |
61 | input daemon_csrbus_wr; // Read/Write signal | |
62 | output daemon_csrbus_mapped; // mapped | |
63 | output csrbus_acc_vio; // acc_vio | |
64 | input daemon_transaction_in_progress; // daemon_transaction_in_progress | |
65 | input instance_id; // Instance ID | |
66 | output daemon_csrbus_done; // Operation is done | |
67 | input stage_mux_only_ext_done_0_out; // Operation is done | |
68 | output psb_dma_select; // select signal | |
69 | output psb_pio_select; // select signal | |
70 | ||
71 | //==================================================================== | |
72 | // Type declarations | |
73 | //==================================================================== | |
74 | wire clk; // Clock signal | |
75 | wire rst_l; // Reset | |
76 | wire daemon_csrbus_valid; // Daemon_Valid | |
77 | wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
78 | wire [1:0] csrbus_src_bus; // Source bus | |
79 | wire daemon_csrbus_wr; // Read/Write signal | |
80 | wire daemon_csrbus_mapped; // mapped | |
81 | wire csrbus_acc_vio; // acc_vio | |
82 | wire daemon_transaction_in_progress; // daemon_transaction_in_progress | |
83 | wire instance_id; // Instance ID | |
84 | wire daemon_csrbus_done; // Operation is done | |
85 | wire stage_mux_only_ext_done_0_out; // Operation is done | |
86 | reg psb_dma_select; // select signal | |
87 | reg psb_pio_select; // select signal | |
88 | ||
89 | ||
90 | //==================================================================== | |
91 | // Clocked valid | |
92 | //==================================================================== | |
93 | reg clocked_valid; | |
94 | reg clocked_valid_pulse; | |
95 | always @(posedge clk) | |
96 | begin | |
97 | if(~rst_l) | |
98 | begin | |
99 | clocked_valid <= 1'b0; | |
100 | clocked_valid_pulse <= 1'b0; | |
101 | end | |
102 | else | |
103 | begin | |
104 | clocked_valid <= daemon_csrbus_valid; | |
105 | clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid; | |
106 | end | |
107 | end | |
108 | ||
109 | //==================================================================== | |
110 | // Address Decode | |
111 | //==================================================================== | |
112 | reg psb_dma_addr_decoded; | |
113 | reg psb_pio_addr_decoded; | |
114 | ||
115 | always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id) | |
116 | begin | |
117 | if (~daemon_csrbus_valid) | |
118 | begin | |
119 | psb_dma_addr_decoded = 1'b0; | |
120 | psb_pio_addr_decoded = 1'b0; | |
121 | end | |
122 | else | |
123 | case (instance_id) | |
124 | ||
125 | `FIRE_DLC_PSB_INSTANCE_ID_VALUE_A: | |
126 | begin | |
127 | psb_dma_addr_decoded = | |
128 | {5'b0,daemon_csrbus_addr[26:5]} == | |
129 | `FIRE_DLC_PSB_CSR_A_PSB_DMA_HW_ADDR >> | |
130 | `FIRE_DLC_PSB_CSR_PSB_DMA_LOW_ADDR_WIDTH; | |
131 | psb_pio_addr_decoded = | |
132 | {4'b0,daemon_csrbus_addr[26:4]} == | |
133 | `FIRE_DLC_PSB_CSR_A_PSB_PIO_HW_ADDR >> | |
134 | `FIRE_DLC_PSB_CSR_PSB_PIO_LOW_ADDR_WIDTH; | |
135 | end | |
136 | ||
137 | `FIRE_DLC_PSB_INSTANCE_ID_VALUE_B: | |
138 | begin | |
139 | psb_dma_addr_decoded = | |
140 | {5'b0,daemon_csrbus_addr[26:5]} == | |
141 | `FIRE_DLC_PSB_CSR_B_PSB_DMA_HW_ADDR >> | |
142 | `FIRE_DLC_PSB_CSR_PSB_DMA_LOW_ADDR_WIDTH; | |
143 | psb_pio_addr_decoded = | |
144 | {4'b0,daemon_csrbus_addr[26:4]} == | |
145 | `FIRE_DLC_PSB_CSR_B_PSB_PIO_HW_ADDR >> | |
146 | `FIRE_DLC_PSB_CSR_PSB_PIO_LOW_ADDR_WIDTH; | |
147 | end | |
148 | ||
149 | default: | |
150 | begin | |
151 | psb_dma_addr_decoded = 1'b0; | |
152 | psb_pio_addr_decoded = 1'b0; | |
153 | // vlint flag_system_call off | |
154 | // synopsys translate_off | |
155 | if(daemon_csrbus_valid) | |
156 | begin // axis tbcall_region | |
157 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_psb_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_psb_csr is bad"); `endif | |
158 | end // end of tbcall_region | |
159 | // synopsys translate_on | |
160 | // vlint flag_system_call on | |
161 | end | |
162 | endcase | |
163 | end | |
164 | ||
165 | //==================================================================== | |
166 | // Register violations | |
167 | //==================================================================== | |
168 | //----- reg_acc_vio: psb_dma | |
169 | reg psb_dma_acc_vio; | |
170 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
171 | psb_dma_addr_decoded or | |
172 | daemon_transaction_in_progress) | |
173 | begin | |
174 | if (daemon_transaction_in_progress | ~psb_dma_addr_decoded) | |
175 | psb_dma_acc_vio = 1'b0; | |
176 | else | |
177 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
178 | // reads | |
179 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
180 | psb_dma_acc_vio = 1'b0; | |
181 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
182 | psb_dma_acc_vio = 1'b0; | |
183 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
184 | psb_dma_acc_vio = 1'b0; | |
185 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
186 | psb_dma_acc_vio = 1'b0; | |
187 | // writes | |
188 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
189 | psb_dma_acc_vio = 1'b0; | |
190 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
191 | psb_dma_acc_vio = 1'b0; | |
192 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
193 | psb_dma_acc_vio = 1'b0; | |
194 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
195 | psb_dma_acc_vio = 1'b0; | |
196 | ||
197 | default: | |
198 | begin | |
199 | psb_dma_acc_vio = 1'b0; | |
200 | begin // axis tbcall_region | |
201 | // vlint flag_system_call off | |
202 | // synopsys translate_off | |
203 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_psb_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_psb_csr_a_psb_dma"); `endif | |
204 | // synopsys translate_on | |
205 | // vlint flag_system_call on | |
206 | end // end of tbcall_region | |
207 | end | |
208 | endcase | |
209 | end | |
210 | //----- reg_acc_vio: psb_pio | |
211 | reg psb_pio_acc_vio; | |
212 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
213 | psb_pio_addr_decoded or | |
214 | daemon_transaction_in_progress) | |
215 | begin | |
216 | if (daemon_transaction_in_progress | ~psb_pio_addr_decoded) | |
217 | psb_pio_acc_vio = 1'b0; | |
218 | else | |
219 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
220 | // reads | |
221 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
222 | psb_pio_acc_vio = 1'b0; | |
223 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
224 | psb_pio_acc_vio = 1'b0; | |
225 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
226 | psb_pio_acc_vio = 1'b0; | |
227 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
228 | psb_pio_acc_vio = 1'b0; | |
229 | // writes | |
230 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
231 | psb_pio_acc_vio = 1'b0; | |
232 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
233 | psb_pio_acc_vio = 1'b0; | |
234 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
235 | psb_pio_acc_vio = 1'b0; | |
236 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
237 | psb_pio_acc_vio = 1'b0; | |
238 | ||
239 | default: | |
240 | begin | |
241 | psb_pio_acc_vio = 1'b0; | |
242 | begin // axis tbcall_region | |
243 | // vlint flag_system_call off | |
244 | // synopsys translate_off | |
245 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_psb_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_psb_csr_a_psb_pio"); `endif | |
246 | // synopsys translate_on | |
247 | // vlint flag_system_call on | |
248 | end // end of tbcall_region | |
249 | end | |
250 | endcase | |
251 | end | |
252 | ||
253 | //==================================================================== | |
254 | // Status: daemon_csrbus_mapped / csrbus_acc_vio | |
255 | //==================================================================== | |
256 | //----- OUTPUT: daemon_csrbus_mapped | |
257 | assign daemon_csrbus_mapped = clocked_valid_pulse & | |
258 | ( | |
259 | psb_dma_addr_decoded | | |
260 | psb_pio_addr_decoded | |
261 | ); | |
262 | ||
263 | ||
264 | //----- OUTPUT: csrbus_acc_vio | |
265 | assign csrbus_acc_vio = clocked_valid_pulse & | |
266 | psb_dma_acc_vio | | |
267 | psb_pio_acc_vio; | |
268 | ||
269 | //==================================================================== | |
270 | // Select | |
271 | //==================================================================== | |
272 | always @(posedge clk) | |
273 | begin | |
274 | if(~rst_l) | |
275 | begin | |
276 | psb_dma_select <= 1'b0; | |
277 | psb_pio_select <= 1'b0; | |
278 | end | |
279 | else | |
280 | begin | |
281 | psb_dma_select <= | |
282 | ~ psb_dma_acc_vio & | |
283 | psb_dma_addr_decoded; | |
284 | ||
285 | psb_pio_select <= | |
286 | ~ psb_pio_acc_vio & | |
287 | psb_pio_addr_decoded; | |
288 | ||
289 | end | |
290 | end | |
291 | ||
292 | //==================================================================== | |
293 | // Cycle Counter: Used for ExtReadTiming / ExtWriteTiming | |
294 | //==================================================================== | |
295 | ||
296 | //==================================================================== | |
297 | // OUTPUT: daemon_csrbus_done (pipelining) | |
298 | //==================================================================== | |
299 | //----- DONE for internal/extern registers | |
300 | reg stage_1_daemon_csrbus_done_internal_0; | |
301 | reg stage_2_daemon_csrbus_done_internal_0; | |
302 | ||
303 | always @(posedge clk) | |
304 | begin | |
305 | if(~rst_l) | |
306 | begin | |
307 | stage_1_daemon_csrbus_done_internal_0 <= 1'b0; | |
308 | end | |
309 | else | |
310 | begin | |
311 | stage_1_daemon_csrbus_done_internal_0 <= | |
312 | psb_dma_select & clocked_valid_pulse & daemon_csrbus_wr | | |
313 | psb_pio_select & clocked_valid_pulse & daemon_csrbus_wr; | |
314 | end | |
315 | if(~rst_l) | |
316 | begin | |
317 | stage_2_daemon_csrbus_done_internal_0 <= 1'b0; | |
318 | end | |
319 | else | |
320 | begin | |
321 | stage_2_daemon_csrbus_done_internal_0 <= | |
322 | stage_1_daemon_csrbus_done_internal_0; | |
323 | end | |
324 | end | |
325 | ||
326 | //----- OUTPUT: daemon_csrbus_done | |
327 | assign daemon_csrbus_done = daemon_csrbus_valid & | |
328 | ( | |
329 | stage_2_daemon_csrbus_done_internal_0 | | |
330 | stage_mux_only_ext_done_0_out | |
331 | ); | |
332 | ||
333 | ||
334 | endmodule // dmu_psb_addr_decode |