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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_psb_stage_mux_only.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_psb_stage_mux_only | |
36 | ( | |
37 | clk, | |
38 | read_data_0, | |
39 | ext_done_0, | |
40 | psb_dma_select, | |
41 | psb_dma_select_out, | |
42 | psb_pio_select, | |
43 | psb_pio_select_out, | |
44 | ext_addr_in, | |
45 | ext_addr_out, | |
46 | read_data_0_out, | |
47 | ext_done_0_out, | |
48 | rst_l, | |
49 | rst_l_out | |
50 | ); | |
51 | ||
52 | //==================================================== | |
53 | // Polarity declarations | |
54 | //==================================================== | |
55 | input clk; // Clock signal | |
56 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
57 | input ext_done_0; // Ext Done | |
58 | input psb_dma_select; // select | |
59 | output psb_dma_select_out; // select | |
60 | input psb_pio_select; // select | |
61 | output psb_pio_select_out; // select | |
62 | input [4:0] ext_addr_in; // Ext addr | |
63 | output [4:0] ext_addr_out; // Ext addr | |
64 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
65 | output ext_done_0_out; // Ext Done | |
66 | input rst_l; // HW reset | |
67 | output rst_l_out; // HW reset | |
68 | ||
69 | //==================================================== | |
70 | // Type declarations | |
71 | //==================================================== | |
72 | wire clk; // Clock signal | |
73 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
74 | wire ext_done_0; // Ext Done | |
75 | wire psb_dma_select; // select | |
76 | wire psb_dma_select_out; // select | |
77 | wire psb_pio_select; // select | |
78 | wire psb_pio_select_out; // select | |
79 | wire [4:0] ext_addr_in; // Ext addr | |
80 | wire [4:0] ext_addr_out; // Ext addr | |
81 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
82 | wire ext_done_0_out; // Ext Done | |
83 | wire rst_l; // HW reset | |
84 | wire rst_l_out; // HW reset | |
85 | ||
86 | ||
87 | //==================================================== | |
88 | // Assignments only | |
89 | //==================================================== | |
90 | assign ext_done_0_out = | |
91 | ext_done_0; | |
92 | assign psb_dma_select_out = psb_dma_select; | |
93 | assign psb_pio_select_out = psb_pio_select; | |
94 | assign rst_l_out = rst_l; | |
95 | assign ext_addr_out = ext_addr_in; | |
96 | ||
97 | ||
98 | //===================================================== | |
99 | // OUTPUT: read_data_out | |
100 | //===================================================== | |
101 | dmu_psb_csrpipe_1 dmu_psb_csrpipe_1_inst_1 | |
102 | ( | |
103 | .clk (clk), | |
104 | .rst_l (rst_l), | |
105 | .reg_in (1'b0), | |
106 | .reg_out (1'b0), | |
107 | .data0 (read_data_0), | |
108 | .sel0 (1'b1), | |
109 | .out (read_data_0_out) | |
110 | ); | |
111 | ||
112 | endmodule // dmu_psb_stage_mux_only |