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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_rmu_rrm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_rmu_rrm ( | |
36 | clk, | |
37 | rst_l, | |
38 | ||
39 | // Outputs to JBC Block - PIO credit release | |
40 | d2j_p_wrack_tag, | |
41 | d2j_p_wrack_vld, | |
42 | ||
43 | // Inputs from ILU (EIL) Block - Release Record for PIO Cpl/DMA Rd | |
44 | y2k_rel_rcd, | |
45 | y2k_rel_enq, | |
46 | ||
47 | // Outputs to ILU - EPE Record (Egress PEC Record) | |
48 | k2y_rcd, | |
49 | k2y_rcd_enq, | |
50 | ||
51 | // Input from ILU | |
52 | y2k_rcd_deq, | |
53 | ||
54 | // Outputs to IMU - Mondo Reply Record (RRM to IMU) | |
55 | rm2im_rply, | |
56 | rm2im_rply_enq, | |
57 | ||
58 | // Input from IMU - Static CSR MEM64 Address Offset | |
59 | im2rm_mem64_offset_reg, | |
60 | ||
61 | // Outputs to TSB - Egress Pipeline | |
62 | rm2ts_e_cmd_type, | |
63 | rm2ts_e_wr_data, | |
64 | rm2ts_e_trn, | |
65 | rm2ts_e_req, | |
66 | ||
67 | // Inputs from TSB | |
68 | ts2rm_e_gnt, | |
69 | ts2rm_e_rd_data, | |
70 | ||
71 | // Inputs from CMU - Retire Record (TCM to RRM) | |
72 | cm2rm_rcd, | |
73 | cm2rm_rcd_enq, | |
74 | ||
75 | // Output to CMU | |
76 | rm2cm_rcd_full, | |
77 | ||
78 | // Outputs to CLU | |
79 | rm2cl_bufrel, | |
80 | rm2cl_bufrel_enq, | |
81 | ||
82 | // Input from CRU - static REQID (PIO)/ Completion ID (DMA) for EPE rcd | |
83 | cr2rm_req_id, | |
84 | ||
85 | // Internal sub-block Inputs - PIO Transaction Credit Record | |
86 | lrm2rrm_cpl, | |
87 | lrm2rrm_cpl_enq, | |
88 | ||
89 | // RRM Debug Ports - Inputs (Selects) | |
90 | dbg2rrm_dbg_sel_a, | |
91 | dbg2rrm_dbg_sel_b, | |
92 | ||
93 | // RRM Debug Ports - Onputs | |
94 | rrm2dbg_dbg_a, | |
95 | rrm2dbg_dbg_b, | |
96 | ||
97 | // BP npwr wrack to crm | |
98 | rm2crm_npwr_wrack | |
99 | ||
100 | ); | |
101 | ||
102 | // synopsys sync_set_reset "rst_l" | |
103 | ||
104 | ||
105 | //############################################################################ | |
106 | // PORT DECLARATIONS | |
107 | //############################################################################ | |
108 | ||
109 | //------------------------------------------------------------------------ | |
110 | // Clock and Reset Signals | |
111 | //------------------------------------------------------------------------ | |
112 | input clk; | |
113 | input rst_l; | |
114 | ||
115 | ||
116 | //------------------------------------------------------------------------ | |
117 | // JBC Interface | |
118 | //------------------------------------------------------------------------ | |
119 | ||
120 | // Copy of original 4 bit JBC PIO request tag - and corresponding valid | |
121 | // signal PIO credit release mechanism | |
122 | output [`FIRE_D2J_P_WRACK_WDTH-1:0] d2j_p_wrack_tag; | |
123 | output d2j_p_wrack_vld; | |
124 | ||
125 | ||
126 | //------------------------------------------------------------------------ | |
127 | // ILU Interface | |
128 | //------------------------------------------------------------------------ | |
129 | ||
130 | // 9 bit Downbound Release Rcd from EIL - (PIO Cpl and DMA Rd buffer release) | |
131 | input [`FIRE_DLC_DRR_REC_WDTH-1:0] y2k_rel_rcd; | |
132 | input y2k_rel_enq; | |
133 | ||
134 | // Egress pipeline interface - EPE (Egress PEC record) (RRM to ILU) | |
135 | output [`FIRE_DLC_EPE_REC_WDTH-1:0] k2y_rcd; | |
136 | output k2y_rcd_enq; | |
137 | input y2k_rcd_deq; | |
138 | ||
139 | ||
140 | //------------------------------------------------------------------------ | |
141 | // IMU Interface | |
142 | //------------------------------------------------------------------------ | |
143 | ||
144 | // Mondo Reply Record (RRM to IMU) | |
145 | output [`FIRE_DLC_MRR_REC_WDTH-1:0] rm2im_rply; | |
146 | output rm2im_rply_enq; | |
147 | ||
148 | input [`FIRE_DLC_SCW_MEM64_WDTH-1:0] im2rm_mem64_offset_reg; // 40 bit field | |
149 | ||
150 | ||
151 | //------------------------------------------------------------------------ | |
152 | // TSB Interfacs | |
153 | //------------------------------------------------------------------------ | |
154 | ||
155 | // RRM <-> TSB interface (Egress Pipeline) | |
156 | ||
157 | output [`FIRE_DLC_TSR_CMD_TYPE_WDTH-1:0] rm2ts_e_cmd_type; // 4 bits | |
158 | output [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] rm2ts_e_wr_data; // 48 bit | |
159 | output [`FIRE_DLC_TSR_TRN_WDTH-1:0] rm2ts_e_trn; // 5 bits | |
160 | output rm2ts_e_req; | |
161 | ||
162 | input ts2rm_e_gnt; | |
163 | input [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] ts2rm_e_rd_data; // 48 bits | |
164 | ||
165 | ||
166 | //------------------------------------------------------------------------ | |
167 | // CMU Interface | |
168 | //------------------------------------------------------------------------ | |
169 | ||
170 | // Egress pipeline interface - Egress RETIRE RECORD (TCM to RRM) | |
171 | input [`FIRE_DLC_ERR_REC_WDTH-1:0] cm2rm_rcd; | |
172 | input cm2rm_rcd_enq; | |
173 | output rm2cm_rcd_full; | |
174 | ||
175 | ||
176 | //------------------------------------------------------------------------ | |
177 | // CLU Interface | |
178 | //------------------------------------------------------------------------ | |
179 | ||
180 | // DMA Rd Buffer Release Record - 5 bit DOU Buffer Release | |
181 | ||
182 | output [`FIRE_DLC_DOU_REL_WDTH-1:0] rm2cl_bufrel; | |
183 | output rm2cl_bufrel_enq; | |
184 | ||
185 | //------------------------------------------------------------------------ | |
186 | // CRU Interface | |
187 | //------------------------------------------------------------------------ | |
188 | ||
189 | // FIRE's 16 bit Prog. ReqID (PIO) CplID (DMA) - was 16'b0 prior to P1731 | |
190 | input [`FIRE_PCIE_REQ_ID_WDTH-1:0] cr2rm_req_id; | |
191 | ||
192 | ||
193 | //------------------------------------------------------------------------ | |
194 | // Sub-block Interface to LRM | |
195 | //------------------------------------------------------------------------ | |
196 | ||
197 | // 4 bit (non-posted) PIO Transaction Credit Record | |
198 | input [`FIRE_DLC_RMU_LRM_REL_WDTH-1:0] lrm2rrm_cpl; | |
199 | input lrm2rrm_cpl_enq; | |
200 | ||
201 | //------------------------------------------------------------------------ | |
202 | // Sub Block Level Selects and Output Ports | |
203 | //------------------------------------------------------------------------ | |
204 | ||
205 | input [2:0] dbg2rrm_dbg_sel_a; | |
206 | input [2:0] dbg2rrm_dbg_sel_b; | |
207 | ||
208 | output [`FIRE_DEBUG_WDTH-1:0] rrm2dbg_dbg_a; | |
209 | output [`FIRE_DEBUG_WDTH-1:0] rrm2dbg_dbg_b; | |
210 | ||
211 | ||
212 | //------------------------------------------------------------------------ | |
213 | // npwr wrack to crm | |
214 | //------------------------------------------------------------------------ | |
215 | output rm2crm_npwr_wrack; | |
216 | ||
217 | //############################################################################ | |
218 | // PARAMETERS | |
219 | //############################################################################ | |
220 | ||
221 | ||
222 | //############################################################################ | |
223 | // SIGNAL DECLARATIONS | |
224 | //############################################################################ | |
225 | ||
226 | ||
227 | //************************************************** | |
228 | // Internal Sub-Block Wires | |
229 | //************************************************** | |
230 | ||
231 | // single bit wires connecting EFSM and ETSBFSM modules | |
232 | wire tsb_fsm_idle; // ETSB FSM is idle | |
233 | wire ld_epe_rcd_tsb; // RRM record soriced from TSB | |
234 | wire gen_tsb_access; // Generate TSB cycle | |
235 | wire sr_err_last_pkt; // ERR Rcd last packet bit set | |
236 | ||
237 | // Internal wires pulled out for debug visibility or idle checks | |
238 | wire [2:0] ilu_credit_cnt; // EPE credit - starts at 4 | |
239 | wire [2:0] e_state; // 3 bit Egress 1-hot FSM | |
240 | wire [1:0] type_decode; // Egress transaction type decode | |
241 | wire [12:0] wrb_bcnt; // 13 bit DMA Rd remaining bcnt | |
242 | wire [3:0] e_tsb_state; // 4 bit Egress TSB 1 hot FSM | |
243 | wire [1:0] rel_state; // 2 bit REL rcd 1 hot FSM | |
244 | wire sr_err_empty; // ERR SR FIFO empty | |
245 | wire i_pio_rel_empty;// non posted pio rel queue empty | |
246 | wire e_pio_rel_empty;// posted (egress) pio rel queue empty | |
247 | wire rmu_rrm_idle; // RRM sub-block idle | |
248 | ||
249 | ||
250 | //************************************************** | |
251 | // Registers that Are Not Flops | |
252 | //************************************************** | |
253 | ||
254 | reg [`FIRE_DEBUG_WDTH-1:0] next_dbg_a; // 8 bit debug ports | |
255 | reg [`FIRE_DEBUG_WDTH-1:0] next_dbg_b; // 8 bit debup port | |
256 | ||
257 | ||
258 | //************************************************** | |
259 | // Registers that Are Flops | |
260 | //************************************************** | |
261 | ||
262 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_a; // 8 bit debug reg | |
263 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_b; // 8 bit debug reg | |
264 | ||
265 | ||
266 | //############################################################################ | |
267 | // ZERO IN CHECKERS | |
268 | //############################################################################ | |
269 | ||
270 | ||
271 | //############################################################################ | |
272 | // COMBINATIONAL LOGIC | |
273 | //############################################################################ | |
274 | ||
275 | //----------------------------------------------------- | |
276 | // Debug Ports | |
277 | //----------------------------------------------------- | |
278 | ||
279 | always @ (dbg2rrm_dbg_sel_a or sr_err_empty or cm2rm_rcd_enq or rm2cm_rcd_full or k2y_rcd_enq or | |
280 | y2k_rcd_deq or ilu_credit_cnt or e_state or rm2ts_e_trn or wrb_bcnt or | |
281 | ts2rm_e_gnt or rm2ts_e_req or e_tsb_state or gen_tsb_access or ld_epe_rcd_tsb or | |
282 | sr_err_last_pkt or tsb_fsm_idle or type_decode or d2j_p_wrack_tag or | |
283 | d2j_p_wrack_vld or rm2cl_bufrel_enq or y2k_rel_rcd or y2k_rel_enq or | |
284 | rel_state or lrm2rrm_cpl or lrm2rrm_cpl_enq or rmu_rrm_idle) | |
285 | begin | |
286 | case (dbg2rrm_dbg_sel_a) // synopsys infer_mux | |
287 | 3'b000: next_dbg_a = {sr_err_empty, cm2rm_rcd_enq, rm2cm_rcd_full, k2y_rcd_enq, y2k_rcd_deq, ilu_credit_cnt[2:0]}; | |
288 | 3'b001: next_dbg_a = {e_state[2:0], rm2ts_e_trn[4:0]}; | |
289 | 3'b010: next_dbg_a = {rm2ts_e_req, wrb_bcnt[12:6]}; | |
290 | 3'b011: next_dbg_a = {rm2ts_e_req, ts2rm_e_gnt, wrb_bcnt[5:0]}; | |
291 | 3'b100: next_dbg_a = {e_tsb_state[3:0], gen_tsb_access, ld_epe_rcd_tsb, sr_err_last_pkt, tsb_fsm_idle}; | |
292 | 3'b101: next_dbg_a = {sr_err_empty, type_decode[1:0], d2j_p_wrack_tag[3:0], d2j_p_wrack_vld}; | |
293 | 3'b110: next_dbg_a = {rm2cl_bufrel_enq, y2k_rel_rcd[8], y2k_rel_rcd[4:0], y2k_rel_enq}; | |
294 | 3'b111: next_dbg_a = {rmu_rrm_idle, rel_state[1:0], lrm2rrm_cpl[3:0], lrm2rrm_cpl_enq}; | |
295 | endcase | |
296 | end | |
297 | ||
298 | ||
299 | always @ (dbg2rrm_dbg_sel_b or sr_err_empty or cm2rm_rcd_enq or rm2cm_rcd_full or k2y_rcd_enq or | |
300 | y2k_rcd_deq or ilu_credit_cnt or e_state or rm2ts_e_trn or wrb_bcnt or | |
301 | ts2rm_e_gnt or rm2ts_e_req or e_tsb_state or gen_tsb_access or ld_epe_rcd_tsb or | |
302 | sr_err_last_pkt or tsb_fsm_idle or type_decode or d2j_p_wrack_tag or | |
303 | d2j_p_wrack_vld or rm2cl_bufrel_enq or y2k_rel_rcd or y2k_rel_enq or | |
304 | rel_state or lrm2rrm_cpl or lrm2rrm_cpl_enq or rmu_rrm_idle) | |
305 | begin | |
306 | case (dbg2rrm_dbg_sel_b) // synopsys infer_mux | |
307 | 3'b000: next_dbg_b = {sr_err_empty, cm2rm_rcd_enq, rm2cm_rcd_full, k2y_rcd_enq, y2k_rcd_deq, ilu_credit_cnt[2:0]}; | |
308 | 3'b001: next_dbg_b = {e_state[2:0], rm2ts_e_trn[4:0]}; | |
309 | 3'b010: next_dbg_b = {rm2ts_e_req, wrb_bcnt[12:6]}; | |
310 | 3'b011: next_dbg_b = {rm2ts_e_req, ts2rm_e_gnt, wrb_bcnt[5:0]}; | |
311 | 3'b100: next_dbg_b = {e_tsb_state[3:0], gen_tsb_access, ld_epe_rcd_tsb, sr_err_last_pkt, tsb_fsm_idle}; | |
312 | 3'b101: next_dbg_b = {sr_err_empty, type_decode[1:0], d2j_p_wrack_tag[3:0], d2j_p_wrack_vld}; | |
313 | 3'b110: next_dbg_b = {rm2cl_bufrel_enq, y2k_rel_rcd[8], y2k_rel_rcd[4:0], y2k_rel_enq}; | |
314 | 3'b111: next_dbg_b = {rmu_rrm_idle, rel_state[1:0], lrm2rrm_cpl[3:0], lrm2rrm_cpl_enq}; | |
315 | endcase | |
316 | end | |
317 | ||
318 | // RRM Debug Outputs | |
319 | assign rrm2dbg_dbg_a = dbg_a; | |
320 | assign rrm2dbg_dbg_b = dbg_b; | |
321 | ||
322 | ||
323 | //----------------------------------------------------- | |
324 | // Idle Checker Logic | |
325 | //----------------------------------------------------- | |
326 | ||
327 | assign rmu_rrm_idle = (sr_err_empty & i_pio_rel_empty & e_pio_rel_empty); | |
328 | ||
329 | ||
330 | //############################################################################ | |
331 | // SEQUENTIAL LOGIC | |
332 | //############################################################################ | |
333 | ||
334 | // RRM debug registered outputs | |
335 | always @ (posedge clk) | |
336 | if(~rst_l) begin | |
337 | dbg_a <= {`FIRE_DEBUG_WDTH{1'b0}}; | |
338 | dbg_b <= {`FIRE_DEBUG_WDTH{1'b0}}; | |
339 | end | |
340 | else begin | |
341 | dbg_a <= next_dbg_a; | |
342 | dbg_b <= next_dbg_b; | |
343 | end | |
344 | ||
345 | ||
346 | //############################################################################ | |
347 | // MODULE INSTANTIATIONS | |
348 | //############################################################################ | |
349 | ||
350 | dmu_rmu_rrm_efsm efsm( | |
351 | ||
352 | .clk (clk), | |
353 | .rst_l (rst_l), | |
354 | ||
355 | // Inputs from CMU - Retire Record (TCM to RRM) | |
356 | .cm2rm_rcd (cm2rm_rcd), | |
357 | .cm2rm_rcd_enq (cm2rm_rcd_enq), | |
358 | ||
359 | // Output to CMU | |
360 | .rm2cm_rcd_full (rm2cm_rcd_full), | |
361 | ||
362 | // Outputs to ILU - EPE Record | |
363 | .k2y_rcd (k2y_rcd), | |
364 | .k2y_rcd_enq (k2y_rcd_enq), | |
365 | ||
366 | // Input from ILU - EPE Revord Dequeue | |
367 | .y2k_rcd_deq (y2k_rcd_deq), | |
368 | ||
369 | // Outputs to IMU - Mondo Reply Record (RRM to IMU) | |
370 | .rm2im_rply (rm2im_rply), | |
371 | .rm2im_rply_enq (rm2im_rply_enq), | |
372 | ||
373 | // Input from IMU - PIO mem64 offset register | |
374 | .im2rm_mem64_offset_reg (im2rm_mem64_offset_reg), | |
375 | ||
376 | // Outputs to TSB | |
377 | .rm2ts_e_trn (rm2ts_e_trn), | |
378 | .rm2ts_e_wr_data (rm2ts_e_wr_data), | |
379 | ||
380 | // Inputs from TSB | |
381 | .ts2rm_e_rd_data (ts2rm_e_rd_data), | |
382 | ||
383 | // Input from CRU | |
384 | .cr2rm_req_id (cr2rm_req_id), | |
385 | ||
386 | // Outputs to Local ETSB module | |
387 | .gen_tsb_access (gen_tsb_access), | |
388 | .sr_err_last_pkt (sr_err_last_pkt), | |
389 | ||
390 | // Inputs from Local ETSB module | |
391 | .tsb_fsm_idle (tsb_fsm_idle), | |
392 | .ld_epe_rcd_tsb (ld_epe_rcd_tsb), | |
393 | ||
394 | // Outputs for debug port visibility | |
395 | .wrb_bcnt (wrb_bcnt), | |
396 | .ilu_credit_cnt (ilu_credit_cnt), | |
397 | .type_decode (type_decode), | |
398 | .sr_err_empty (sr_err_empty), | |
399 | .e_state (e_state) | |
400 | ); | |
401 | ||
402 | ||
403 | dmu_rmu_rrm_etsbfsm etsbfsm( | |
404 | ||
405 | .clk (clk), | |
406 | .rst_l (rst_l), | |
407 | ||
408 | // Outputs to TSB - Egress Pipeline | |
409 | .rm2ts_e_cmd_type (rm2ts_e_cmd_type), | |
410 | .rm2ts_e_req (rm2ts_e_req), | |
411 | ||
412 | // Inputs from TSB | |
413 | .ts2rm_e_gnt (ts2rm_e_gnt), | |
414 | ||
415 | // Outputs to EFSM module | |
416 | .tsb_fsm_idle (tsb_fsm_idle), | |
417 | .ld_epe_rcd_tsb (ld_epe_rcd_tsb), | |
418 | ||
419 | // Inputs from EFSM module | |
420 | .gen_tsb_access (gen_tsb_access), | |
421 | .sr_err_last_pkt (sr_err_last_pkt), | |
422 | ||
423 | // Outputs for debug port visibility | |
424 | .e_tsb_state (e_tsb_state) | |
425 | ); | |
426 | ||
427 | ||
428 | ||
429 | dmu_rmu_rrm_erel erel( | |
430 | .clk (clk), | |
431 | .rst_l (rst_l), | |
432 | ||
433 | // Outputs to JBC Block - PIO credit release | |
434 | .d2j_p_wrack_tag (d2j_p_wrack_tag), | |
435 | .d2j_p_wrack_vld (d2j_p_wrack_vld), | |
436 | ||
437 | // Inputs from ILU (EIL) Block - Release Record for PIO Cpl/DMA Rd | |
438 | .y2k_rel_rcd (y2k_rel_rcd), | |
439 | .y2k_rel_enq (y2k_rel_enq), | |
440 | ||
441 | // Outputs to CLU | |
442 | .rm2cl_bufrel (rm2cl_bufrel), | |
443 | .rm2cl_bufrel_enq (rm2cl_bufrel_enq), | |
444 | ||
445 | // Internal sub-block Inputs - PIO Transaction Credit Record | |
446 | .lrm2rrm_cpl (lrm2rrm_cpl), | |
447 | .lrm2rrm_cpl_enq (lrm2rrm_cpl_enq), | |
448 | ||
449 | // Output for IDLE checkers | |
450 | .i_pio_rel_empty (i_pio_rel_empty), | |
451 | .e_pio_rel_empty (e_pio_rel_empty), | |
452 | ||
453 | // Outputs for debug port visibility | |
454 | .rel_state (rel_state), | |
455 | ||
456 | // | |
457 | .rm2crm_npwr_wrack (rm2crm_npwr_wrack) | |
458 | ); | |
459 | ||
460 | ||
461 | endmodule |