[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_tmu_dim.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_tmu_dim.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_tmu_dim (
			 clk,
			 rst_l,

                         // ilu -> peu-idb BP n2 5-06-05 rd enable to peu idb ram
                         d2p_idb_rd,
		     		     
			 // ilu <-> dmu-tmu
			 y2k_rcd,
			 y2k_rcd_enq,
			 k2y_rcd_deq,
			 k2y_rel_rcd,
			 k2y_rel_enq,			 
			 
			 // data path
			 y2k_buf_addr_vld_monitor,
			 k2y_buf_addr_vld_monitor,
			 k2y_buf_addr,
			 y2k_buf_data,
			 y2k_buf_dpar,
			 
			 // DIU interface
			 tm2di_wr,
			 tm2di_addr,
			 tm2di_data,
			 tm2di_bmask,
			 tm2di_dpar,
			 
			 // CLU buf rel, DIU pointer interface
			 cl2tm_dma_rptr,
			 cl2tm_int_rptr,
			 tm2cl_dma_wptr,
			 tm2cl_pio_wptr,
			 
			 // RMU interface
			 tm2rm_rcd,
			 tm2rm_rcd_enq,
			 rm2tm_rcd_full,
			 
			 // IMU interface
			 tm2im_data_enq,
			 tm2im_data,
			 im2tm_msi32_addr_reg,
			 im2tm_msi64_addr_reg,

			 // CRU (debug) interface
			 cr2tm_dbg_sel_a,
			 cr2tm_dbg_sel_b,
			 tm2cr_dbg_a,
			 tm2cr_dbg_b,
			 
			 // idle check
			 dim_is_idle,
			 tmu_is_idle,
			 // for sun4v msi_64 compare
			 csr_sun4v_en,
			 im2tm_eqs_adr_63
);
  
  //synopsys sync_set_reset "rst_l"

  // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<  

  //------------------------------------------------------------------------
  //  Clock and Reset Signals
  //------------------------------------------------------------------------
  input		  clk;		    
  input		  rst_l;
  
  //------------------------------------------------------------------------
  //   BP n2 5-06-05 rd enable to peu idb ram
  //------------------------------------------------------------------------
  output 	                       d2p_idb_rd;
  //------------------------------------------------------------------------
  //   data path to ILU
  //------------------------------------------------------------------------
  input 	                       y2k_buf_addr_vld_monitor;
  output 	                       k2y_buf_addr_vld_monitor;
  output [`FIRE_DLC_ITI_ADDR_WDTH-1:0] k2y_buf_addr;        // read pointer to IDB
  input [`FIRE_DLC_ITI_DATA_WDTH-1:0]  y2k_buf_data;        // 16-byte data    
  input [`FIRE_DLC_ITI_DPAR_WDTH-1:0]  y2k_buf_dpar;        // data parity
  
  //------------------------------------------------------------------------
  //   record interface to ILU
  //------------------------------------------------------------------------
  output 			       k2y_rcd_deq;         // ingress rcd dequeue
  input [`FIRE_DLC_IPE_REC_WDTH-1:0]   y2k_rcd;             // ingress PEC record
  input 			       y2k_rcd_enq;         // ingress PEC record enqueue
  
  //------------------------------------------------------------------------
  //   release interface with ILU
  //------------------------------------------------------------------------
  output [`FIRE_DLC_URR_REC_WDTH-1:0]  k2y_rel_rcd;         // ingress release rcd
  output 			       k2y_rel_enq;         // ingress enqueue
  
  //------------------------------------------------------------------------
  //   DIU interface
  //------------------------------------------------------------------------
  output 			       tm2di_wr;            // write
  output [`FIRE_DLC_TRD_ADDR_WDTH-1:0] tm2di_addr;          // DIU address
  output [`FIRE_DLC_TRD_DATA_WDTH-1:0] tm2di_data;          // data to DIU
  output [`FIRE_DLC_TRD_BMASK_WDTH-1:0] tm2di_bmask;         // byte mask
  output [`FIRE_DLC_TRD_DPAR_WDTH-1:0] 	tm2di_dpar;          // data parity

  //------------------------------------------------------------------------
  //   CLU buf rel, DIU wr pointer interface
  //------------------------------------------------------------------------
  input [`FIRE_DLC_DMA_RPTR_WDTH-1:0]  cl2tm_dma_rptr;
  input [`FIRE_DLC_INT_RPTR_WDTH-1:0]  cl2tm_int_rptr;    
  output [`FIRE_DLC_DMA_WPTR_WDTH-1:0] tm2cl_dma_wptr;
  output [`FIRE_DLC_PIO_WPTR_WDTH-1:0] tm2cl_pio_wptr;
				      
  //------------------------------------------------------------------------
  //   RMU interface
  //------------------------------------------------------------------------
  output [`FIRE_DLC_DIM_REC_WDTH-1:0]  tm2rm_rcd;
  output 			       tm2rm_rcd_enq;
  input 			       rm2tm_rcd_full;

  //------------------------------------------------------------------------
  //   IMU interface
  //------------------------------------------------------------------------
  output 			       tm2im_data_enq;
  output [`FIRE_DLC_MDF_REC_WDTH-1:0]  tm2im_data;          // ingress
  input [`FIRE_DLC_SCW_MSI32_WDTH-1:0] im2tm_msi32_addr_reg;
  input [`FIRE_DLC_SCW_MSI64_WDTH-1:0] im2tm_msi64_addr_reg;

  //------------------------------------------------------------------------
  //    CRU (debug) interface
  //------------------------------------------------------------------------
  input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2tm_dbg_sel_a;
  input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2tm_dbg_sel_b;
  output [`FIRE_DBG_DATA_BITS] 	       tm2cr_dbg_a;
  output [`FIRE_DBG_DATA_BITS] 	       tm2cr_dbg_b;
  
  //---------------------------------------------------------------------
  // idle check
  //---------------------------------------------------------------------
  output 			       dim_is_idle;
  input 			       tmu_is_idle;
  //---------------------------------------------------------------------
  // for sun4v msi_64 compare
  //---------------------------------------------------------------------
  input 			       csr_sun4v_en;
  input 			       im2tm_eqs_adr_63;

  // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

  //---------------------------------------------------------------------
  // outputs from bufmgr.v
  // --------------------------------------------------------------------
  wire 				       diu_dma_full;          //   to xfrfsm.v, datafsm.v
  wire 				       diu_int_full;          //   to xfrfsm.v
  wire [`FIRE_DLC_DMA_WPTR_WDTH-2:0]   diu_dma_cl_wptr;       //   to datafsm.v
  wire [`FIRE_DLC_PIO_WPTR_WDTH-2:0]   diu_pio_cl_wptr;       //   to datafsm.v
  wire [`FIRE_DLC_DIM_DPTR_WDTH-1:0]   d_ptr_out;             //   to rcdbldr.v
  
  //---------------------------------------------------------------------
  // outputs from datafsm.v
  // --------------------------------------------------------------------
  wire 				       data_done;      //   to xfrfsm.v
  wire 				       dma_cl_req;     //   to bufmgr.v
  wire 				       dma_cl_inc;     //   to bufmgr.v
  wire 				       pio_cl_inc;     //   to bufmgr.v
  wire 				       idb_rptr_inc;
  wire [4:0] 			       data_mux_select;    // to datapath.v
  wire [3:0] 			       first_dwbe_dp;     // to datapath.v
  wire [3:0] 			       last_dwbe_dp;      // to datapath.v
  wire [3:2] 			       align_addr_dp; // to datapath.v
  wire [3:2] 			       end_addr_dp;       // to datapth.v
  wire 				       rcd_is_cpld_reg;    // to relgen.v
  wire 				       payld_len_is_one_dp;
  wire 				       ld_saved_data_dp;
  wire [`FIRE_DBG_DATA_BITS] 	       datafsm_dbg_a;
  wire [`FIRE_DBG_DATA_BITS] 	       datafsm_dbg_b;
  wire 				       datafsm_is_idle;
  
  //---------------------------------------------------------------------
  // outputs from rcdbldr.v
  // --------------------------------------------------------------------
  wire 				       rcd_empty;             //   to xfrfsm.v
  wire 				       rcd_is_msg;            //   to xfrfsm.v, bufmgr.v
  wire 				       rcd_is_msi;            //   to xfrfsm.v, bufmgr.v, datafsm.v
  wire 				       rcd_is_cpld;           //   to xfrfsm.v, bufmgr.v, datafsm.v
  wire 				       rcd_is_dmawr;          //   to xfrfsm.v, bufmgr.v, datafsm.v
  wire [5:2] 			       align_addr;            //   to diufsm.v
  wire [7:0] 			       payld_len;             //   to datafsm.v
  wire [3:0] 			       first_dwbe;   // to diufsm.v
  wire [3:0] 			       last_dwbe;    // to diufsm.v
  
  //---------------------------------------------------------------------
  // outputs from xfrfsm.v
  // --------------------------------------------------------------------
  wire 				       int_cl_req;            //   to bufmgr.v
  wire 				       data_start;            //   to datafsm.v
  wire 				       rcd_deq;               //   to rcdbldr.v
  wire [`FIRE_DBG_DATA_BITS] 	       xfrfsm_dbg_a;
  wire [`FIRE_DBG_DATA_BITS] 	       xfrfsm_dbg_b;
  wire 				       xfrfsm_is_idle;

  //---------------------------------------------------------------------
  //  debug
  //---------------------------------------------------------------------
  reg [`FIRE_DBG_DATA_BITS] 	      dbg_bus_a;
  reg [`FIRE_DBG_DATA_BITS] 	      dbg_bus_b;
  reg [`FIRE_DBG_DATA_BITS] 	      nxt_dbg_bus_a;
  reg [`FIRE_DBG_DATA_BITS] 	      nxt_dbg_bus_b;

assign	d2p_idb_rd	= idb_rptr_inc; 

  // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
  
  //---------------------------------------------------------------------
  //  debug
  //---------------------------------------------------------------------
  always @ (cr2tm_dbg_sel_a[5:3]
	    or datafsm_dbg_a or xfrfsm_dbg_a) begin
    case (cr2tm_dbg_sel_a[5:3]) // synopsys infer_mux
      3'b000: nxt_dbg_bus_a = datafsm_dbg_a;
      3'b001: nxt_dbg_bus_a = xfrfsm_dbg_a;
      3'b010: nxt_dbg_bus_a = 8'b0;
      3'b011: nxt_dbg_bus_a = 8'b0;
      3'b100: nxt_dbg_bus_a = 8'b0;
      3'b101: nxt_dbg_bus_a = 8'b0;
      3'b110: nxt_dbg_bus_a = 8'b0;
      3'b111: nxt_dbg_bus_a = 8'b0;
    endcase
  end

  always @ (cr2tm_dbg_sel_b[5:3]
	    or datafsm_dbg_b or xfrfsm_dbg_b ) begin
    case (cr2tm_dbg_sel_b[5:3]) // synopsys infer_mux
      3'b000: nxt_dbg_bus_b = datafsm_dbg_b;
      3'b001: nxt_dbg_bus_b = xfrfsm_dbg_b;
      3'b010: nxt_dbg_bus_b = 8'b0;
      3'b011: nxt_dbg_bus_b = 8'b0;
      3'b100: nxt_dbg_bus_b = 8'b0;
      3'b101: nxt_dbg_bus_b = 8'b0;
      3'b110: nxt_dbg_bus_b = 8'b0;
      3'b111: nxt_dbg_bus_b = 8'b0;
    endcase
  end

  assign tm2cr_dbg_a = dbg_bus_a;
  assign tm2cr_dbg_b = dbg_bus_b;
    
  always @ (posedge clk) 
	if(~rst_l) begin
    dbg_bus_a <= {8{1'b0}};
    dbg_bus_b <= {8{1'b0}};
	end
  else begin
    dbg_bus_a <= nxt_dbg_bus_a;
    dbg_bus_b <= nxt_dbg_bus_b;
  end

  //---------------------------------------------------------------------
  // idle check
  //---------------------------------------------------------------------
  assign dim_is_idle = rcd_empty & xfrfsm_is_idle & datafsm_is_idle;
  
  //---------------------------------------------------------------------
  // output k2y_buf_addr_vld_monitor
  //---------------------------------------------------------------------
  assign k2y_buf_addr_vld_monitor = idb_rptr_inc;

  // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
dmu_tmu_dim_bufmgr bufmgr
  (     .clk 		 (clk),
        .rst_l 		 (rst_l),
        .cl2tm_dma_rptr  (cl2tm_dma_rptr),
        .cl2tm_int_rptr  (cl2tm_int_rptr),
        .tm2cl_dma_wptr  (tm2cl_dma_wptr),
        .tm2cl_pio_wptr  (tm2cl_pio_wptr),
        .diu_dma_full 	 (diu_dma_full),
        .diu_int_full 	 (diu_int_full),
        .int_cl_req 	 (int_cl_req),
	.rcd_deq         (rcd_deq),
        .dma_cl_req 	 (dma_cl_req),
        .dma_cl_inc 	 (dma_cl_inc),
        .pio_cl_inc 	 (pio_cl_inc),
        .diu_pio_cl_wptr (diu_pio_cl_wptr),
        .diu_dma_cl_wptr (diu_dma_cl_wptr),
        .d_ptr_out 	 (d_ptr_out));

dmu_tmu_dim_datafsm datafsm
  (     .clk 		    (clk),
        .rst_l 		    (rst_l),
        .tm2di_wr 	    (tm2di_wr),
        .tm2di_addr 	    (tm2di_addr),
        .tm2im_data_enq     (tm2im_data_enq),
        .data_start 	    (data_start),
        .data_done 	    (data_done),
        .diu_dma_full 	    (diu_dma_full),
        .dma_cl_req 	    (dma_cl_req),
        .dma_cl_inc 	    (dma_cl_inc),
        .pio_cl_inc 	    (pio_cl_inc),
        .diu_dma_cl_wptr    (diu_dma_cl_wptr),
        .diu_pio_cl_wptr    (diu_pio_cl_wptr),
        .rcd_is_cpld 	    (rcd_is_cpld),
        .rcd_is_msi 	    (rcd_is_msi),
        .align_addr 	    (align_addr),
        .payld_len 	    (payld_len),
        .first_dwbe 	    (first_dwbe),
        .last_dwbe 	    (last_dwbe),
        .idb_rptr_inc 	    (idb_rptr_inc),
        .data_mux_select    (data_mux_select),
        .first_dwbe_dp      (first_dwbe_dp),
        .last_dwbe_dp 	    (last_dwbe_dp),
        .align_addr_dp      (align_addr_dp),
        .end_addr_dp 	    (end_addr_dp),
	.payld_len_is_one_dp (payld_len_is_one_dp),
        .ld_saved_data_dp   (ld_saved_data_dp),
        .rcd_is_cpld_reg    (rcd_is_cpld_reg),
	.y2k_buf_addr_vld_monitor   (y2k_buf_addr_vld_monitor),
	.rel_type           (k2y_rel_rcd[8]),
	.k2y_rel_enq        (k2y_rel_enq),
	.low_dbg_sel_a      (cr2tm_dbg_sel_a[2:0]),
	.low_dbg_sel_b      (cr2tm_dbg_sel_b[2:0]),
	.datafsm_dbg_a      (datafsm_dbg_a),
	.datafsm_dbg_b      (datafsm_dbg_b),
	.datafsm_is_idle    (datafsm_is_idle) );
 
dmu_tmu_dim_datapath  datapath
  (     .clk 		    (clk),
        .rst_l 		    (rst_l),
        .k2y_buf_addr 	    (k2y_buf_addr),
        .y2k_buf_data 	    (y2k_buf_data),
        .y2k_buf_dpar 	    (y2k_buf_dpar),
        .tm2di_data 	    (tm2di_data),
        .tm2di_bmask 	    (tm2di_bmask),
        .tm2di_dpar 	    (tm2di_dpar),
        .tm2im_data 	    (tm2im_data),
        .idb_rptr_inc 	    (idb_rptr_inc),
        .data_mux_select    (data_mux_select),
        .first_dwbe_dp      (first_dwbe_dp),
        .last_dwbe_dp 	    (last_dwbe_dp),
        .align_addr_dp      (align_addr_dp),
        .end_addr_dp 	    (end_addr_dp),
	.payld_len_is_one_dp (payld_len_is_one_dp),
        .ld_saved_data_dp   (ld_saved_data_dp) );
  
dmu_tmu_dim_rcdbldr rcdbldr
  (    .clk 		      (clk),
        .rst_l 		      (rst_l),
        .y2k_rcd 	      (y2k_rcd),
        .y2k_rcd_enq 	      (y2k_rcd_enq),
        .tm2rm_rcd 	      (tm2rm_rcd),
        .im2tm_msi32_addr_reg (im2tm_msi32_addr_reg),
        .im2tm_msi64_addr_reg (im2tm_msi64_addr_reg),
        .rcd_deq 	      (rcd_deq),
        .rcd_empty 	      (rcd_empty),
        .rcd_is_msg 	      (rcd_is_msg),
        .rcd_is_msi 	      (rcd_is_msi),
        .rcd_is_cpld 	      (rcd_is_cpld),
        .rcd_is_dmawr 	      (rcd_is_dmawr),
        .align_addr 	      (align_addr),
        .payld_len 	      (payld_len),
        .d_ptr_out 	      (d_ptr_out),
        .first_dwbe 	      (first_dwbe),
        .last_dwbe 	      (last_dwbe),
        .csr_sun4v_en 	      (csr_sun4v_en),
        .im2tm_eqs_adr_63     (im2tm_eqs_adr_63)
	);

dmu_tmu_dim_relgen relgen 
  (    .clk 		 (clk),
        .rst_l 		 (rst_l),
        .k2y_rel_rcd 	 (k2y_rel_rcd),
        .k2y_rel_enq 	 (k2y_rel_enq),
        .rcd_is_cpld_reg (rcd_is_cpld_reg),
        .k2y_buf_addr 	 (k2y_buf_addr));

dmu_tmu_dim_xfrfsm xfrfsm 
  (    .clk 		(clk),
        .rst_l 		(rst_l),
        .k2y_rcd_deq 	(k2y_rcd_deq),
        .tm2rm_rcd_enq 	(tm2rm_rcd_enq),
        .rm2tm_rcd_full (rm2tm_rcd_full),
        .diu_dma_full 	(diu_dma_full),
        .diu_int_full 	(diu_int_full),
        .int_cl_req 	(int_cl_req),
        .rcd_is_msg 	(rcd_is_msg),
        .rcd_is_msi 	(rcd_is_msi),
        .rcd_is_cpld 	(rcd_is_cpld),
        .rcd_is_dmawr 	(rcd_is_dmawr),
        .data_start 	(data_start),
        .data_done 	(data_done),
        .rcd_empty 	(rcd_empty),
        .rcd_deq 	(rcd_deq),
	.low_dbg_sel_a  (cr2tm_dbg_sel_a[2:0]),
	.low_dbg_sel_b  (cr2tm_dbg_sel_b[2:0]),
	.xfrfsm_dbg_a   (xfrfsm_dbg_a),
	.xfrfsm_dbg_b   (xfrfsm_dbg_b),
        .xfrfsm_is_idle (xfrfsm_is_idle),
        .tmu_is_idle    (tmu_is_idle) );
  
endmodule // dmu_tmu_dim
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_tmu_dim.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_tmu_dim (
	36	clk,
	37	rst_l,
	38
	39	// ilu -> peu-idb BP n2 5-06-05 rd enable to peu idb ram
	40	d2p_idb_rd,
	41
	42	// ilu <-> dmu-tmu
	43	y2k_rcd,
	44	y2k_rcd_enq,
	45	k2y_rcd_deq,
	46	k2y_rel_rcd,
	47	k2y_rel_enq,
	48
	49	// data path
	50	y2k_buf_addr_vld_monitor,
	51	k2y_buf_addr_vld_monitor,
	52	k2y_buf_addr,
	53	y2k_buf_data,
	54	y2k_buf_dpar,
	55
	56	// DIU interface
	57	tm2di_wr,
	58	tm2di_addr,
	59	tm2di_data,
	60	tm2di_bmask,
	61	tm2di_dpar,
	62
	63	// CLU buf rel, DIU pointer interface
	64	cl2tm_dma_rptr,
65	cl2tm_int_rptr,
66	tm2cl_dma_wptr,
67	tm2cl_pio_wptr,
68
69	// RMU interface
70	tm2rm_rcd,
71	tm2rm_rcd_enq,
72	rm2tm_rcd_full,
73
74	// IMU interface
75	tm2im_data_enq,
76	tm2im_data,
77	im2tm_msi32_addr_reg,
78	im2tm_msi64_addr_reg,
79
80	// CRU (debug) interface
81	cr2tm_dbg_sel_a,
82	cr2tm_dbg_sel_b,
83	tm2cr_dbg_a,
84	tm2cr_dbg_b,
85
86	// idle check
87	dim_is_idle,
88	tmu_is_idle,
89	// for sun4v msi_64 compare
90	csr_sun4v_en,
91	im2tm_eqs_adr_63
92	);
93
94	//synopsys sync_set_reset "rst_l"
95
96	// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
97
98	//------------------------------------------------------------------------
99	// Clock and Reset Signals
100	//------------------------------------------------------------------------
101	input clk;
102	input rst_l;
103
104	//------------------------------------------------------------------------
105	// BP n2 5-06-05 rd enable to peu idb ram
106	//------------------------------------------------------------------------
107	output d2p_idb_rd;
108	//------------------------------------------------------------------------
109	// data path to ILU
110	//------------------------------------------------------------------------
111	input y2k_buf_addr_vld_monitor;
112	output k2y_buf_addr_vld_monitor;
113	output [`FIRE_DLC_ITI_ADDR_WDTH-1:0] k2y_buf_addr; // read pointer to IDB
114	input [`FIRE_DLC_ITI_DATA_WDTH-1:0] y2k_buf_data; // 16-byte data
115	input [`FIRE_DLC_ITI_DPAR_WDTH-1:0] y2k_buf_dpar; // data parity
116
117	//------------------------------------------------------------------------
118	// record interface to ILU
119	//------------------------------------------------------------------------
120	output k2y_rcd_deq; // ingress rcd dequeue
121	input [`FIRE_DLC_IPE_REC_WDTH-1:0] y2k_rcd; // ingress PEC record
122	input y2k_rcd_enq; // ingress PEC record enqueue
123
124	//------------------------------------------------------------------------
125	// release interface with ILU
126	//------------------------------------------------------------------------
127	output [`FIRE_DLC_URR_REC_WDTH-1:0] k2y_rel_rcd; // ingress release rcd
128	output k2y_rel_enq; // ingress enqueue
129
130	//------------------------------------------------------------------------
131	// DIU interface
132	//------------------------------------------------------------------------
133	output tm2di_wr; // write
134	output [`FIRE_DLC_TRD_ADDR_WDTH-1:0] tm2di_addr; // DIU address
135	output [`FIRE_DLC_TRD_DATA_WDTH-1:0] tm2di_data; // data to DIU
136	output [`FIRE_DLC_TRD_BMASK_WDTH-1:0] tm2di_bmask; // byte mask
137	output [`FIRE_DLC_TRD_DPAR_WDTH-1:0] tm2di_dpar; // data parity
138
139	//------------------------------------------------------------------------
140	// CLU buf rel, DIU wr pointer interface
141	//------------------------------------------------------------------------
142	input [`FIRE_DLC_DMA_RPTR_WDTH-1:0] cl2tm_dma_rptr;
143	input [`FIRE_DLC_INT_RPTR_WDTH-1:0] cl2tm_int_rptr;
144	output [`FIRE_DLC_DMA_WPTR_WDTH-1:0] tm2cl_dma_wptr;
145	output [`FIRE_DLC_PIO_WPTR_WDTH-1:0] tm2cl_pio_wptr;
146
147	//------------------------------------------------------------------------
148	// RMU interface
149	//------------------------------------------------------------------------
150	output [`FIRE_DLC_DIM_REC_WDTH-1:0] tm2rm_rcd;
151	output tm2rm_rcd_enq;
152	input rm2tm_rcd_full;
153
154	//------------------------------------------------------------------------
155	// IMU interface
156	//------------------------------------------------------------------------
157	output tm2im_data_enq;
158	output [`FIRE_DLC_MDF_REC_WDTH-1:0] tm2im_data; // ingress
159	input [`FIRE_DLC_SCW_MSI32_WDTH-1:0] im2tm_msi32_addr_reg;
160	input [`FIRE_DLC_SCW_MSI64_WDTH-1:0] im2tm_msi64_addr_reg;
161
162	//------------------------------------------------------------------------
163	// CRU (debug) interface
164	//------------------------------------------------------------------------
165	input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2tm_dbg_sel_a;
166	input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2tm_dbg_sel_b;
167	output [`FIRE_DBG_DATA_BITS] tm2cr_dbg_a;
168	output [`FIRE_DBG_DATA_BITS] tm2cr_dbg_b;
169
170	//---------------------------------------------------------------------
171	// idle check
172	//---------------------------------------------------------------------
173	output dim_is_idle;
174	input tmu_is_idle;
175	//---------------------------------------------------------------------
176	// for sun4v msi_64 compare
177	//---------------------------------------------------------------------
178	input csr_sun4v_en;
179	input im2tm_eqs_adr_63;
180
181	// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
182
183	// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
184
185	//---------------------------------------------------------------------
186	// outputs from bufmgr.v
187	// --------------------------------------------------------------------
188	wire diu_dma_full; // to xfrfsm.v, datafsm.v
189	wire diu_int_full; // to xfrfsm.v
190	wire [`FIRE_DLC_DMA_WPTR_WDTH-2:0] diu_dma_cl_wptr; // to datafsm.v
191	wire [`FIRE_DLC_PIO_WPTR_WDTH-2:0] diu_pio_cl_wptr; // to datafsm.v
192	wire [`FIRE_DLC_DIM_DPTR_WDTH-1:0] d_ptr_out; // to rcdbldr.v
193
194	//---------------------------------------------------------------------
195	// outputs from datafsm.v
196	// --------------------------------------------------------------------
197	wire data_done; // to xfrfsm.v
198	wire dma_cl_req; // to bufmgr.v
199	wire dma_cl_inc; // to bufmgr.v
200	wire pio_cl_inc; // to bufmgr.v
201	wire idb_rptr_inc;
202	wire [4:0] data_mux_select; // to datapath.v
203	wire [3:0] first_dwbe_dp; // to datapath.v
204	wire [3:0] last_dwbe_dp; // to datapath.v
205	wire [3:2] align_addr_dp; // to datapath.v
206	wire [3:2] end_addr_dp; // to datapth.v
207	wire rcd_is_cpld_reg; // to relgen.v
208	wire payld_len_is_one_dp;
209	wire ld_saved_data_dp;
210	wire [`FIRE_DBG_DATA_BITS] datafsm_dbg_a;
211	wire [`FIRE_DBG_DATA_BITS] datafsm_dbg_b;
212	wire datafsm_is_idle;
213
214	//---------------------------------------------------------------------
215	// outputs from rcdbldr.v
216	// --------------------------------------------------------------------
217	wire rcd_empty; // to xfrfsm.v
218	wire rcd_is_msg; // to xfrfsm.v, bufmgr.v
219	wire rcd_is_msi; // to xfrfsm.v, bufmgr.v, datafsm.v
220	wire rcd_is_cpld; // to xfrfsm.v, bufmgr.v, datafsm.v
221	wire rcd_is_dmawr; // to xfrfsm.v, bufmgr.v, datafsm.v
222	wire [5:2] align_addr; // to diufsm.v
223	wire [7:0] payld_len; // to datafsm.v
224	wire [3:0] first_dwbe; // to diufsm.v
225	wire [3:0] last_dwbe; // to diufsm.v
226
227	//---------------------------------------------------------------------
228	// outputs from xfrfsm.v
229	// --------------------------------------------------------------------
230	wire int_cl_req; // to bufmgr.v
231	wire data_start; // to datafsm.v
232	wire rcd_deq; // to rcdbldr.v
233	wire [`FIRE_DBG_DATA_BITS] xfrfsm_dbg_a;
234	wire [`FIRE_DBG_DATA_BITS] xfrfsm_dbg_b;
235	wire xfrfsm_is_idle;
236
237	//---------------------------------------------------------------------
238	// debug
239	//---------------------------------------------------------------------
240	reg [`FIRE_DBG_DATA_BITS] dbg_bus_a;
241	reg [`FIRE_DBG_DATA_BITS] dbg_bus_b;
242	reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus_a;
243	reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus_b;
244
245	assign d2p_idb_rd = idb_rptr_inc;
246
247	// >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
248
249	//---------------------------------------------------------------------
250	// debug
251	//---------------------------------------------------------------------
252	always @ (cr2tm_dbg_sel_a[5:3]
253	or datafsm_dbg_a or xfrfsm_dbg_a) begin
254	case (cr2tm_dbg_sel_a[5:3]) // synopsys infer_mux
255	3'b000: nxt_dbg_bus_a = datafsm_dbg_a;
256	3'b001: nxt_dbg_bus_a = xfrfsm_dbg_a;
257	3'b010: nxt_dbg_bus_a = 8'b0;
258	3'b011: nxt_dbg_bus_a = 8'b0;
259	3'b100: nxt_dbg_bus_a = 8'b0;
260	3'b101: nxt_dbg_bus_a = 8'b0;
261	3'b110: nxt_dbg_bus_a = 8'b0;
262	3'b111: nxt_dbg_bus_a = 8'b0;
263	endcase
264	end
265
266	always @ (cr2tm_dbg_sel_b[5:3]
267	or datafsm_dbg_b or xfrfsm_dbg_b ) begin
268	case (cr2tm_dbg_sel_b[5:3]) // synopsys infer_mux
269	3'b000: nxt_dbg_bus_b = datafsm_dbg_b;
270	3'b001: nxt_dbg_bus_b = xfrfsm_dbg_b;
271	3'b010: nxt_dbg_bus_b = 8'b0;
272	3'b011: nxt_dbg_bus_b = 8'b0;
273	3'b100: nxt_dbg_bus_b = 8'b0;
274	3'b101: nxt_dbg_bus_b = 8'b0;
275	3'b110: nxt_dbg_bus_b = 8'b0;
276	3'b111: nxt_dbg_bus_b = 8'b0;
277	endcase
278	end
279
280	assign tm2cr_dbg_a = dbg_bus_a;
281	assign tm2cr_dbg_b = dbg_bus_b;
282
283	always @ (posedge clk)
284	if(~rst_l) begin
285	dbg_bus_a <= {8{1'b0}};
286	dbg_bus_b <= {8{1'b0}};
287	end
288	else begin
289	dbg_bus_a <= nxt_dbg_bus_a;
290	dbg_bus_b <= nxt_dbg_bus_b;
291	end
292
293	//---------------------------------------------------------------------
294	// idle check
295	//---------------------------------------------------------------------
296	assign dim_is_idle = rcd_empty & xfrfsm_is_idle & datafsm_is_idle;
297
298	//---------------------------------------------------------------------
299	// output k2y_buf_addr_vld_monitor
300	//---------------------------------------------------------------------
301	assign k2y_buf_addr_vld_monitor = idb_rptr_inc;
302
303	// >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
304	dmu_tmu_dim_bufmgr bufmgr
305	( .clk (clk),
306	.rst_l (rst_l),
307	.cl2tm_dma_rptr (cl2tm_dma_rptr),
308	.cl2tm_int_rptr (cl2tm_int_rptr),
309	.tm2cl_dma_wptr (tm2cl_dma_wptr),
310	.tm2cl_pio_wptr (tm2cl_pio_wptr),
311	.diu_dma_full (diu_dma_full),
312	.diu_int_full (diu_int_full),
313	.int_cl_req (int_cl_req),
314	.rcd_deq (rcd_deq),
315	.dma_cl_req (dma_cl_req),
316	.dma_cl_inc (dma_cl_inc),
317	.pio_cl_inc (pio_cl_inc),
318	.diu_pio_cl_wptr (diu_pio_cl_wptr),
319	.diu_dma_cl_wptr (diu_dma_cl_wptr),
320	.d_ptr_out (d_ptr_out));
321
322	dmu_tmu_dim_datafsm datafsm
323	( .clk (clk),
324	.rst_l (rst_l),
325	.tm2di_wr (tm2di_wr),
326	.tm2di_addr (tm2di_addr),
327	.tm2im_data_enq (tm2im_data_enq),
328	.data_start (data_start),
329	.data_done (data_done),
330	.diu_dma_full (diu_dma_full),
331	.dma_cl_req (dma_cl_req),
332	.dma_cl_inc (dma_cl_inc),
333	.pio_cl_inc (pio_cl_inc),
334	.diu_dma_cl_wptr (diu_dma_cl_wptr),
335	.diu_pio_cl_wptr (diu_pio_cl_wptr),
336	.rcd_is_cpld (rcd_is_cpld),
337	.rcd_is_msi (rcd_is_msi),
338	.align_addr (align_addr),
339	.payld_len (payld_len),
340	.first_dwbe (first_dwbe),
341	.last_dwbe (last_dwbe),
342	.idb_rptr_inc (idb_rptr_inc),
343	.data_mux_select (data_mux_select),
344	.first_dwbe_dp (first_dwbe_dp),
345	.last_dwbe_dp (last_dwbe_dp),
346	.align_addr_dp (align_addr_dp),
347	.end_addr_dp (end_addr_dp),
348	.payld_len_is_one_dp (payld_len_is_one_dp),
349	.ld_saved_data_dp (ld_saved_data_dp),
350	.rcd_is_cpld_reg (rcd_is_cpld_reg),
351	.y2k_buf_addr_vld_monitor (y2k_buf_addr_vld_monitor),
352	.rel_type (k2y_rel_rcd[8]),
353	.k2y_rel_enq (k2y_rel_enq),
354	.low_dbg_sel_a (cr2tm_dbg_sel_a[2:0]),
355	.low_dbg_sel_b (cr2tm_dbg_sel_b[2:0]),
356	.datafsm_dbg_a (datafsm_dbg_a),
357	.datafsm_dbg_b (datafsm_dbg_b),
358	.datafsm_is_idle (datafsm_is_idle) );
359
360	dmu_tmu_dim_datapath datapath
361	( .clk (clk),
362	.rst_l (rst_l),
363	.k2y_buf_addr (k2y_buf_addr),
364	.y2k_buf_data (y2k_buf_data),
365	.y2k_buf_dpar (y2k_buf_dpar),
366	.tm2di_data (tm2di_data),
367	.tm2di_bmask (tm2di_bmask),
368	.tm2di_dpar (tm2di_dpar),
369	.tm2im_data (tm2im_data),
370	.idb_rptr_inc (idb_rptr_inc),
371	.data_mux_select (data_mux_select),
372	.first_dwbe_dp (first_dwbe_dp),
373	.last_dwbe_dp (last_dwbe_dp),
374	.align_addr_dp (align_addr_dp),
375	.end_addr_dp (end_addr_dp),
376	.payld_len_is_one_dp (payld_len_is_one_dp),
377	.ld_saved_data_dp (ld_saved_data_dp) );
378
379	dmu_tmu_dim_rcdbldr rcdbldr
380	( .clk (clk),
381	.rst_l (rst_l),
382	.y2k_rcd (y2k_rcd),
383	.y2k_rcd_enq (y2k_rcd_enq),
384	.tm2rm_rcd (tm2rm_rcd),
385	.im2tm_msi32_addr_reg (im2tm_msi32_addr_reg),
386	.im2tm_msi64_addr_reg (im2tm_msi64_addr_reg),
387	.rcd_deq (rcd_deq),
388	.rcd_empty (rcd_empty),
389	.rcd_is_msg (rcd_is_msg),
390	.rcd_is_msi (rcd_is_msi),
391	.rcd_is_cpld (rcd_is_cpld),
392	.rcd_is_dmawr (rcd_is_dmawr),
393	.align_addr (align_addr),
394	.payld_len (payld_len),
395	.d_ptr_out (d_ptr_out),
396	.first_dwbe (first_dwbe),
397	.last_dwbe (last_dwbe),
398	.csr_sun4v_en (csr_sun4v_en),
399	.im2tm_eqs_adr_63 (im2tm_eqs_adr_63)
400	);
401
402	dmu_tmu_dim_relgen relgen
403	( .clk (clk),
404	.rst_l (rst_l),
405	.k2y_rel_rcd (k2y_rel_rcd),
406	.k2y_rel_enq (k2y_rel_enq),
407	.rcd_is_cpld_reg (rcd_is_cpld_reg),
408	.k2y_buf_addr (k2y_buf_addr));
409
410	dmu_tmu_dim_xfrfsm xfrfsm
411	( .clk (clk),
412	.rst_l (rst_l),
413	.k2y_rcd_deq (k2y_rcd_deq),
414	.tm2rm_rcd_enq (tm2rm_rcd_enq),
415	.rm2tm_rcd_full (rm2tm_rcd_full),
416	.diu_dma_full (diu_dma_full),
417	.diu_int_full (diu_int_full),
418	.int_cl_req (int_cl_req),
419	.rcd_is_msg (rcd_is_msg),
420	.rcd_is_msi (rcd_is_msi),
421	.rcd_is_cpld (rcd_is_cpld),
422	.rcd_is_dmawr (rcd_is_dmawr),
423	.data_start (data_start),
424	.data_done (data_done),
425	.rcd_empty (rcd_empty),
426	.rcd_deq (rcd_deq),
427	.low_dbg_sel_a (cr2tm_dbg_sel_a[2:0]),
428	.low_dbg_sel_b (cr2tm_dbg_sel_b[2:0]),
429	.xfrfsm_dbg_a (xfrfsm_dbg_a),
430	.xfrfsm_dbg_b (xfrfsm_dbg_b),
431	.xfrfsm_is_idle (xfrfsm_is_idle),
432	.tmu_is_idle (tmu_is_idle) );
433
434	endmodule // dmu_tmu_dim
435
436
437
438