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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_tmu_dim_bufmgr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_tmu_dim_bufmgr ( | |
36 | clk, | |
37 | rst_l, | |
38 | ||
39 | // CLU buf rel, DIU pointer interface | |
40 | cl2tm_dma_rptr, | |
41 | cl2tm_int_rptr, | |
42 | tm2cl_dma_wptr, | |
43 | tm2cl_pio_wptr, | |
44 | ||
45 | // talk to xfrfsm.v | |
46 | diu_dma_full, | |
47 | diu_int_full, | |
48 | int_cl_req, | |
49 | rcd_deq, | |
50 | ||
51 | // talk to datafsm.v | |
52 | dma_cl_req, | |
53 | dma_cl_inc, | |
54 | pio_cl_inc, | |
55 | diu_pio_cl_wptr, | |
56 | diu_dma_cl_wptr, | |
57 | ||
58 | d_ptr_out ); | |
59 | ||
60 | //synopsys sync_set_reset "rst_l" | |
61 | ||
62 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
63 | ||
64 | //------------------------------------------------------------------------ | |
65 | // Clock and Reset Signals | |
66 | //------------------------------------------------------------------------ | |
67 | input clk; | |
68 | input rst_l; | |
69 | ||
70 | //------------------------------------------------------------------------ | |
71 | // CLU - TMU interface | |
72 | //------------------------------------------------------------------------ | |
73 | input [`FIRE_DLC_DMA_RPTR_WDTH-1:0] cl2tm_dma_rptr; | |
74 | input [`FIRE_DLC_INT_RPTR_WDTH-1:0] cl2tm_int_rptr; | |
75 | output [`FIRE_DLC_DMA_WPTR_WDTH-1:0] tm2cl_dma_wptr; | |
76 | output [`FIRE_DLC_PIO_WPTR_WDTH-1:0] tm2cl_pio_wptr; | |
77 | ||
78 | //------------------------------------------------------------------------ | |
79 | // talk to xfrfsm.v | |
80 | //------------------------------------------------------------------------ | |
81 | output diu_dma_full; // to xfrfsm.v & datafsm.v | |
82 | output diu_int_full; | |
83 | input int_cl_req; | |
84 | input rcd_deq; | |
85 | ||
86 | //------------------------------------------------------------------------ | |
87 | // talk to datafsm.v | |
88 | //------------------------------------------------------------------------ | |
89 | input dma_cl_req; | |
90 | input dma_cl_inc; | |
91 | input pio_cl_inc; | |
92 | output [`FIRE_DLC_DMA_WPTR_WDTH-2:0] diu_dma_cl_wptr; | |
93 | output [`FIRE_DLC_PIO_WPTR_WDTH-2:0] diu_pio_cl_wptr; | |
94 | ||
95 | //------------------------------------------------------------------------ | |
96 | // talk to rcdbldr.v | |
97 | //------------------------------------------------------------------------ | |
98 | output [`FIRE_DLC_DIM_DPTR_WDTH-1:0] d_ptr_out; | |
99 | ||
100 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
101 | ||
102 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
103 | reg [`FIRE_DLC_DMA_WPTR_WDTH-1:0] dma_wptr; // MSB is rollover bit | |
104 | reg [`FIRE_DLC_DMA_WPTR_WDTH-1:0] dma_sd_wptr; // for buffer fullness | |
105 | reg [`FIRE_DLC_PIO_WPTR_WDTH-1:0] pio_wptr; // MSB is rollover bit | |
106 | reg [`FIRE_DLC_INT_RPTR_WDTH-1:0] int_wptr; | |
107 | ||
108 | reg [`FIRE_DLC_DIM_DPTR_WDTH-1:0] tran_id; | |
109 | ||
110 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
111 | ||
112 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
113 | wire [`FIRE_DLC_DIM_DPTR_WDTH-1:0] d_ptr_out; | |
114 | ||
115 | // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
116 | ||
117 | // 0in max -var int_wptr[`FIRE_DLC_INT_RPTR_WDTH-2:0] -val 4'b1011 | |
118 | ||
119 | ||
120 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< | |
121 | ||
122 | //--------------------------------------------------------------------- | |
123 | // buffer credit management - *_cl_req will not be asserted | |
124 | // if there is no corresponding credit | |
125 | //--------------------------------------------------------------------- | |
126 | ||
127 | // ~~~~~~~ increment dma_sd_wptr ~~~~~~~~ | |
128 | always @(posedge clk) | |
129 | if (~rst_l) | |
130 | dma_sd_wptr <= {`FIRE_DLC_DMA_WPTR_WDTH{1'b0}}; | |
131 | else if (dma_cl_req) | |
132 | dma_sd_wptr <= dma_sd_wptr + 1'b1; | |
133 | ||
134 | // ~~~~~~~ dma buffer fullness ~~~~~~~~ | |
135 | assign diu_dma_full = (cl2tm_dma_rptr[4:0] == dma_sd_wptr[4:0]) & | |
136 | (cl2tm_dma_rptr[5] ^ dma_sd_wptr[5]); | |
137 | ||
138 | // ~~~~~~~ int buffer fullness ~~~~~~~~ | |
139 | assign diu_int_full = (cl2tm_int_rptr[3:0] == int_wptr[3:0]) & | |
140 | (cl2tm_int_rptr[4] ^ int_wptr[4]); | |
141 | ||
142 | //--------------------------------------------------------------------- | |
143 | // buffer write pointer management | |
144 | //--------------------------------------------------------------------- | |
145 | ||
146 | // ~~~~~~~ increment dma_wptr ~~~~~~~~ | |
147 | always @(posedge clk) | |
148 | if (~rst_l) | |
149 | dma_wptr <= {`FIRE_DLC_DMA_WPTR_WDTH{1'b0}}; | |
150 | else if (dma_cl_inc) | |
151 | dma_wptr <= dma_wptr + 1'b1; | |
152 | ||
153 | ||
154 | // ~~~~~~~ increment pio_wptr ~~~~~~~~ | |
155 | always @(posedge clk) | |
156 | if (~rst_l) | |
157 | pio_wptr <= {`FIRE_DLC_PIO_WPTR_WDTH{1'b0}}; | |
158 | else if (pio_cl_inc) | |
159 | pio_wptr <= pio_wptr + 1'b1; | |
160 | ||
161 | // ~~~~~~~ increment int_wptr ~~~~~~~~ | |
162 | // there are 16 cache lines in DIU INT buf, 0000->1011 for EQ writes | |
163 | // 1100->1111 for Mondo | |
164 | always @(posedge clk) | |
165 | if (~rst_l) | |
166 | int_wptr <= {`FIRE_DLC_INT_RPTR_WDTH{1'b0}}; | |
167 | else if (int_cl_req) | |
168 | begin | |
169 | if (int_wptr[`FIRE_DLC_INT_RPTR_WDTH-2:0] == 4'b1011) | |
170 | begin | |
171 | int_wptr[`FIRE_DLC_INT_RPTR_WDTH-2:0] <= 4'b0; | |
172 | int_wptr[`FIRE_DLC_INT_RPTR_WDTH-1] <= ~int_wptr[`FIRE_DLC_INT_RPTR_WDTH-1]; | |
173 | end | |
174 | else | |
175 | begin | |
176 | int_wptr[`FIRE_DLC_INT_RPTR_WDTH-2:0] <= int_wptr[`FIRE_DLC_INT_RPTR_WDTH-2:0] + 1'b1; | |
177 | end | |
178 | end | |
179 | ||
180 | // ~~~~~~~ increment tran_id ~~~~~~~~ | |
181 | always @(posedge clk) | |
182 | if (~rst_l) | |
183 | tran_id <= {`FIRE_DLC_DIM_DPTR_WDTH{1'b0}}; | |
184 | else if (rcd_deq) | |
185 | tran_id <= tran_id + 1'b1; | |
186 | ||
187 | // ~~~~~~~ output d_ptr_out ~~~~~~~~ | |
188 | assign d_ptr_out = tran_id; | |
189 | ||
190 | // ~~~~~~~ output cacheline addr ~~~~~~~~ | |
191 | assign diu_dma_cl_wptr = dma_wptr[`FIRE_DLC_DMA_WPTR_WDTH-2:0]; | |
192 | assign diu_pio_cl_wptr = pio_wptr[`FIRE_DLC_PIO_WPTR_WDTH-2:0]; | |
193 | ||
194 | ||
195 | // ~~~~~~~ output tm2cl_dma_wptr & tm2cl_pio_wptr ~~~~~~~~ | |
196 | assign tm2cl_dma_wptr = dma_wptr; | |
197 | assign tm2cl_pio_wptr = pio_wptr; | |
198 | ||
199 | endmodule // dmu_tmu_dim_bufmgr | |
200 | ||
201 | ||
202 | ||
203 |