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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_tsb_csr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_tsb_csr | |
36 | ( | |
37 | clk, | |
38 | csrbus_addr, | |
39 | csrbus_wr_data, | |
40 | csrbus_wr, | |
41 | csrbus_valid, | |
42 | csrbus_mapped, | |
43 | csrbus_done, | |
44 | csrbus_read_data, | |
45 | rst_l, | |
46 | csrbus_src_bus, | |
47 | csrbus_acc_vio, | |
48 | instance_id, | |
49 | ext_addr, | |
50 | tsb_dma_ext_select, | |
51 | tsb_dma_entry_ext_read_data, | |
52 | tsb_dma_ext_done, | |
53 | tsb_sts_ext_select, | |
54 | tsb_sts_full_ext_read_data, | |
55 | tsb_sts_num_pnd_dma_ext_read_data, | |
56 | tsb_sts_empty_ext_read_data, | |
57 | tsb_sts_ext_done | |
58 | ); | |
59 | ||
60 | //==================================================== | |
61 | // Polarity declarations | |
62 | //==================================================== | |
63 | input clk; // Clock signal | |
64 | input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus | |
65 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
66 | input csrbus_wr; // Read/Write signal | |
67 | input csrbus_valid; // Valid address | |
68 | output csrbus_mapped; // Address is mapped | |
69 | output csrbus_done; // Operation is done | |
70 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus | |
71 | input rst_l; // Reset signal | |
72 | input [1:0] csrbus_src_bus; // Source bus | |
73 | output csrbus_acc_vio; // Violation signal | |
74 | input instance_id; // Instance ID | |
75 | output [4:0] ext_addr; // External address bus for dcm tsb | |
76 | output tsb_dma_ext_select; // When set, register tsb_dma is selected. This | |
77 | // signal is a level. | |
78 | input [47:0] tsb_dma_entry_ext_read_data; // Read data from the external | |
79 | // bypass register | |
80 | input tsb_dma_ext_done; // This signal acknowledges read and write operations | |
81 | // for register tsb_dma. For read operations, it | |
82 | // indicates that the tsb_dma_ext_read_data signals | |
83 | // are valid. For write operations, it indicates that | |
84 | // the write operation is complete, and that | |
85 | // <dcm>_ext_wr_data may be removed on the next cycle. | |
86 | output tsb_sts_ext_select; // When set, register tsb_sts is selected. This | |
87 | // signal is a level. | |
88 | input [0:0] tsb_sts_full_ext_read_data; // Ext read data (decode) | |
89 | input [5:0] tsb_sts_num_pnd_dma_ext_read_data; // Ext read data (decode) | |
90 | input [0:0] tsb_sts_empty_ext_read_data; // Ext read data (decode) | |
91 | input tsb_sts_ext_done; // This signal acknowledges read and write operations | |
92 | // for register tsb_sts. For read operations, it | |
93 | // indicates that the tsb_sts_ext_read_data signals | |
94 | // are valid. For write operations, it indicates that | |
95 | // the write operation is complete, and that | |
96 | // <dcm>_ext_wr_data may be removed on the next cycle. | |
97 | ||
98 | //==================================================== | |
99 | // Type declarations | |
100 | //==================================================== | |
101 | wire clk; // Clock signal | |
102 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus | |
103 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
104 | wire csrbus_wr; // Read/Write signal | |
105 | wire csrbus_valid; // Valid address | |
106 | wire csrbus_mapped; // Address is mapped | |
107 | wire csrbus_done; // Operation is done | |
108 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus | |
109 | wire rst_l; // Reset signal | |
110 | wire [1:0] csrbus_src_bus; // Source bus | |
111 | wire csrbus_acc_vio; // Violation signal | |
112 | wire instance_id; // Instance ID | |
113 | wire [4:0] ext_addr; // External address bus for dcm tsb | |
114 | wire tsb_dma_ext_select; // When set, register tsb_dma is selected. This signal | |
115 | // is a level. | |
116 | wire [47:0] tsb_dma_entry_ext_read_data; // Read data from the external bypass | |
117 | // register | |
118 | wire tsb_dma_ext_done; // This signal acknowledges read and write operations | |
119 | // for register tsb_dma. For read operations, it | |
120 | // indicates that the tsb_dma_ext_read_data signals are | |
121 | // valid. For write operations, it indicates that the | |
122 | // write operation is complete, and that | |
123 | // <dcm>_ext_wr_data may be removed on the next cycle. | |
124 | wire tsb_sts_ext_select; // When set, register tsb_sts is selected. This signal | |
125 | // is a level. | |
126 | wire [0:0] tsb_sts_full_ext_read_data; // Ext read data (decode) | |
127 | wire [5:0] tsb_sts_num_pnd_dma_ext_read_data; // Ext read data (decode) | |
128 | wire [0:0] tsb_sts_empty_ext_read_data; // Ext read data (decode) | |
129 | wire tsb_sts_ext_done; // This signal acknowledges read and write operations | |
130 | // for register tsb_sts. For read operations, it | |
131 | // indicates that the tsb_sts_ext_read_data signals are | |
132 | // valid. For write operations, it indicates that the | |
133 | // write operation is complete, and that | |
134 | // <dcm>_ext_wr_data may be removed on the next cycle. | |
135 | ||
136 | //==================================================== | |
137 | // Local signals | |
138 | //==================================================== | |
139 | //==================================================== | |
140 | // Logic | |
141 | //==================================================== | |
142 | wire daemon_transaction_in_progress; | |
143 | wire daemon_csrbus_mapped; | |
144 | wire daemon_csrbus_valid; | |
145 | // vlint flag_dangling_net_within_module off | |
146 | // vlint flag_net_has_no_load off | |
147 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; | |
148 | // vlint flag_dangling_net_within_module on | |
149 | // vlint flag_net_has_no_load on | |
150 | wire daemon_csrbus_done; | |
151 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr; | |
152 | wire daemon_csrbus_wr; | |
153 | ||
154 | //summit modcovoff -bepgnv | |
155 | pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon ( | |
156 | .daemon_csrbus_valid (daemon_csrbus_valid), | |
157 | .daemon_csrbus_mapped (daemon_csrbus_mapped), | |
158 | .daemon_csrbus_wr_data (daemon_csrbus_wr_data), | |
159 | .daemon_csrbus_done (daemon_csrbus_done), | |
160 | .daemon_csrbus_addr (daemon_csrbus_addr), | |
161 | .daemon_csrbus_wr (daemon_csrbus_wr), | |
162 | .daemon_transaction_in_progress (daemon_transaction_in_progress), | |
163 | // synopsys translate_off | |
164 | .clk(clk), | |
165 | .rst_l (rst_l), | |
166 | .csrbus_read_data (csrbus_read_data), | |
167 | // synopsys translate_on | |
168 | .csrbus_valid (csrbus_valid), | |
169 | .csrbus_mapped (csrbus_mapped), | |
170 | .csrbus_wr_data (csrbus_wr_data), | |
171 | .csrbus_done (csrbus_done), | |
172 | .csrbus_addr (csrbus_addr), | |
173 | .csrbus_wr (csrbus_wr) | |
174 | ); | |
175 | //summit modcovon -bepgnv | |
176 | ||
177 | //----- ext_reset | |
178 | ||
179 | //----- Common ext_addr | |
180 | assign ext_addr[4:0] = daemon_csrbus_addr[4:0]; | |
181 | ||
182 | ||
183 | ||
184 | //==================================================================== | |
185 | // Address Decode | |
186 | //==================================================================== | |
187 | reg tsb_dma_addr_decoded; | |
188 | reg tsb_sts_addr_decoded; | |
189 | ||
190 | always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id) | |
191 | begin | |
192 | if (~daemon_csrbus_valid) | |
193 | begin | |
194 | tsb_dma_addr_decoded = 1'b0; | |
195 | tsb_sts_addr_decoded = 1'b0; | |
196 | end | |
197 | else | |
198 | case (instance_id) | |
199 | ||
200 | `FIRE_DLC_TSB_INSTANCE_ID_VALUE_A: | |
201 | begin | |
202 | tsb_dma_addr_decoded = | |
203 | {5'b0,daemon_csrbus_addr[26:5]} == | |
204 | `FIRE_DLC_TSB_CSR_A_TSB_DMA_HW_ADDR >> | |
205 | `FIRE_DLC_TSB_CSR_TSB_DMA_LOW_ADDR_WIDTH; | |
206 | tsb_sts_addr_decoded = | |
207 | daemon_csrbus_addr[26:0] == `FIRE_DLC_TSB_CSR_A_TSB_STS_HW_ADDR; | |
208 | end | |
209 | ||
210 | `FIRE_DLC_TSB_INSTANCE_ID_VALUE_B: | |
211 | begin | |
212 | tsb_dma_addr_decoded = | |
213 | {5'b0,daemon_csrbus_addr[26:5]} == | |
214 | `FIRE_DLC_TSB_CSR_B_TSB_DMA_HW_ADDR >> | |
215 | `FIRE_DLC_TSB_CSR_TSB_DMA_LOW_ADDR_WIDTH; | |
216 | tsb_sts_addr_decoded = | |
217 | daemon_csrbus_addr[26:0] == `FIRE_DLC_TSB_CSR_B_TSB_STS_HW_ADDR; | |
218 | end | |
219 | ||
220 | default: | |
221 | begin | |
222 | tsb_dma_addr_decoded = 1'b0; | |
223 | tsb_sts_addr_decoded = 1'b0; | |
224 | // vlint flag_system_call off | |
225 | // synopsys translate_off | |
226 | if(daemon_csrbus_valid) | |
227 | begin // axis tbcall_region | |
228 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_tsb_csr",`MON_ERROR,"ERROR: Instance ID for module dmu_tsb_csr is bad"); `endif | |
229 | end // end of tbcall_region | |
230 | // synopsys translate_on | |
231 | // vlint flag_system_call on | |
232 | end | |
233 | endcase | |
234 | end | |
235 | ||
236 | //==================================================================== | |
237 | // Register violations | |
238 | //==================================================================== | |
239 | //----- reg_acc_vio: tsb_dma | |
240 | reg tsb_dma_acc_vio; | |
241 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
242 | tsb_dma_addr_decoded or | |
243 | daemon_transaction_in_progress) | |
244 | begin | |
245 | if (daemon_transaction_in_progress | ~tsb_dma_addr_decoded) | |
246 | tsb_dma_acc_vio = 1'b0; | |
247 | else | |
248 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
249 | // reads | |
250 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
251 | tsb_dma_acc_vio = 1'b0; | |
252 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
253 | tsb_dma_acc_vio = 1'b0; | |
254 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
255 | tsb_dma_acc_vio = 1'b0; | |
256 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
257 | tsb_dma_acc_vio = 1'b0; | |
258 | // writes | |
259 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
260 | tsb_dma_acc_vio = 1'b0; | |
261 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
262 | tsb_dma_acc_vio = 1'b0; | |
263 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
264 | tsb_dma_acc_vio = 1'b0; | |
265 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
266 | tsb_dma_acc_vio = 1'b0; | |
267 | ||
268 | default: | |
269 | begin | |
270 | tsb_dma_acc_vio = 1'b0; | |
271 | begin // axis tbcall_region | |
272 | // vlint flag_system_call off | |
273 | // synopsys translate_off | |
274 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_tsb_csr",`MON_ERROR,"acc_vio: default case of dmu_tsb_csr_a_tsb_dma"); `endif | |
275 | // synopsys translate_on | |
276 | // vlint flag_system_call on | |
277 | end // end of tbcall_region | |
278 | end | |
279 | endcase | |
280 | end | |
281 | //----- reg_acc_vio: tsb_sts | |
282 | reg tsb_sts_acc_vio; | |
283 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
284 | tsb_sts_addr_decoded or | |
285 | daemon_transaction_in_progress) | |
286 | begin | |
287 | if (daemon_transaction_in_progress | ~tsb_sts_addr_decoded) | |
288 | tsb_sts_acc_vio = 1'b0; | |
289 | else | |
290 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
291 | // reads | |
292 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
293 | tsb_sts_acc_vio = 1'b0; | |
294 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
295 | tsb_sts_acc_vio = 1'b0; | |
296 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
297 | tsb_sts_acc_vio = 1'b0; | |
298 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
299 | tsb_sts_acc_vio = 1'b0; | |
300 | // writes | |
301 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
302 | tsb_sts_acc_vio = 1'b0; | |
303 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
304 | tsb_sts_acc_vio = 1'b0; | |
305 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
306 | tsb_sts_acc_vio = 1'b0; | |
307 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
308 | tsb_sts_acc_vio = 1'b0; | |
309 | ||
310 | default: | |
311 | begin | |
312 | tsb_sts_acc_vio = 1'b0; | |
313 | begin // axis tbcall_region | |
314 | // vlint flag_system_call off | |
315 | // synopsys translate_off | |
316 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_tsb_csr",`MON_ERROR,"acc_vio: default case of dmu_tsb_csr_a_tsb_sts"); `endif | |
317 | // synopsys translate_on | |
318 | // vlint flag_system_call on | |
319 | end // end of tbcall_region | |
320 | end | |
321 | endcase | |
322 | end | |
323 | ||
324 | //==================================================================== | |
325 | // clocked_mapped | |
326 | //==================================================================== | |
327 | //----- clocked_mapped is to assure that | |
328 | //----- csrbus_mapped is asserted for one cycle | |
329 | reg clocked_mapped; | |
330 | always @(posedge clk) | |
331 | begin | |
332 | if(~rst_l) | |
333 | begin | |
334 | clocked_mapped <= 1'b0; | |
335 | ||
336 | end | |
337 | else | |
338 | begin | |
339 | clocked_mapped <= daemon_csrbus_mapped | | |
340 | clocked_mapped & daemon_csrbus_valid; | |
341 | end | |
342 | end | |
343 | ||
344 | //==================================================================== | |
345 | // Status: daemon_csrbus_mapped / csrbus_acc_vio | |
346 | //==================================================================== | |
347 | //----- OUTPUT: daemon_csrbus_mapped | |
348 | assign daemon_csrbus_mapped = ~clocked_mapped & | |
349 | ( | |
350 | tsb_dma_addr_decoded | | |
351 | tsb_sts_addr_decoded | |
352 | ); | |
353 | ||
354 | ||
355 | //----- OUTPUT: csrbus_acc_vio | |
356 | assign csrbus_acc_vio = ~clocked_mapped & | |
357 | tsb_dma_acc_vio | | |
358 | tsb_sts_acc_vio; | |
359 | ||
360 | //==================================================================== | |
361 | // Select | |
362 | //==================================================================== | |
363 | wire tsb_dma_select = | |
364 | ~ tsb_dma_acc_vio & | |
365 | tsb_dma_addr_decoded; | |
366 | ||
367 | wire tsb_sts_select = | |
368 | ~tsb_sts_acc_vio & | |
369 | tsb_sts_addr_decoded; | |
370 | ||
371 | ||
372 | //==================================================================== | |
373 | // Cycle Counter: Used for ExtReadTiming / ExtWriteTiming | |
374 | //==================================================================== | |
375 | ||
376 | //==================================================== | |
377 | // Automatic hw_ld / hw_write | |
378 | //==================================================== | |
379 | ||
380 | //==================================================== | |
381 | // Extern select | |
382 | //==================================================== | |
383 | assign tsb_dma_ext_select = | |
384 | tsb_dma_select; | |
385 | assign tsb_sts_ext_select = | |
386 | tsb_sts_select; | |
387 | ||
388 | ||
389 | ||
390 | //==================================================== | |
391 | // ext_read_data: field-based to register-based | |
392 | //==================================================== | |
393 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] tsb_dma_ext_read_data = | |
394 | { | |
395 | 16'b0, | |
396 | tsb_dma_entry_ext_read_data | |
397 | }; | |
398 | ||
399 | //===================================================== | |
400 | // OUTPUT: csrbus_read_data | |
401 | //===================================================== | |
402 | assign csrbus_read_data = | |
403 | {`FIRE_CSRBUS_DATA_WIDTH { tsb_dma_select } } & | |
404 | tsb_dma_ext_read_data | | |
405 | {`FIRE_CSRBUS_DATA_WIDTH { tsb_sts_select } } & | |
406 | ||
407 | { | |
408 | 56'b0, | |
409 | tsb_sts_full_ext_read_data, | |
410 | tsb_sts_num_pnd_dma_ext_read_data, | |
411 | tsb_sts_empty_ext_read_data | |
412 | }; | |
413 | ||
414 | //===================================================== | |
415 | // OUTPUT: daemon_csrbus_done | |
416 | //===================================================== | |
417 | assign daemon_csrbus_done = daemon_csrbus_valid & | |
418 | ( | |
419 | tsb_dma_select & ~clocked_mapped & daemon_csrbus_wr | | |
420 | tsb_sts_select & ~clocked_mapped & daemon_csrbus_wr | | |
421 | tsb_dma_ext_done | | |
422 | tsb_sts_ext_done | |
423 | ); | |
424 | ||
425 | //==================================================== | |
426 | // Instantiation of registers | |
427 | //==================================================== | |
428 | ||
429 | ||
430 | endmodule // dmu_tsb_csr |