[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_tsb_dbg.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_tsb_dbg.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_tsb_dbg 
  (
   clk, 	
   rst_l,
   
   // TSB 
   cr2ts_dbg_sel_a,   // TSB debug select a
   cr2ts_dbg_sel_b,   // TSB debug select b
   
   ts2cr_dbg_a,       // TSB debug output a
   ts2cr_dbg_b,       // TSB debug output b
   
   // TTG
   dbg2ttg_dbg_sel_a, // TTG debug select a
   dbg2ttg_dbg_sel_b, // TTG debug select b
   
   ttg2dbg_dbg_a,     // TTG debug output a
   ttg2dbg_dbg_b,     // TTG debug output b
   
   // TDL
   dbg2tdl_dbg_sel_a, // TDL debug select a
   dbg2tdl_dbg_sel_b, // TDL debug select b
   
   tdl2dbg_dbg_a,     // TDL debug output a
   tdl2dbg_dbg_b,     // TDL debug output b
   
   // TIC
   dbg2tic_dbg_sel_a, // TIC debug select a
   dbg2tic_dbg_sel_b, // TIC debug select b
   
   tic2dbg_dbg_a,     // TIC debug output a
   tic2dbg_dbg_b,     // TIC debug output b
   
   // TEC
   dbg2tec_dbg_sel_a, // TEC debug select a
   dbg2tec_dbg_sel_b, // TEC debug select b
   
   tec2dbg_dbg_a,     // TEC debug output a
   tec2dbg_dbg_b      // TEC debug output b
   );
  
  // synopsys sync_set_reset "rst_l"
  
  //************************************************
  //				PORTS
  //************************************************
  
  input                                        clk;                                 
  input 				       rst_l;                               
  
  // TSB Debug
  input [5:0] 				       cr2ts_dbg_sel_a;
  input [5:0] 				       cr2ts_dbg_sel_b;
  output [`FIRE_DBG_DATA_BITS] 		       ts2cr_dbg_a;
  output [`FIRE_DBG_DATA_BITS] 		       ts2cr_dbg_b;
  
  // TTG debug   
  input [`FIRE_DBG_DATA_BITS] 		       ttg2dbg_dbg_a;
  input [`FIRE_DBG_DATA_BITS] 		       ttg2dbg_dbg_b; 	
  output [2:0] 				       dbg2ttg_dbg_sel_a;			       
  output [2:0] 				       dbg2ttg_dbg_sel_b;
  
  // TDL debug
  input [`FIRE_DBG_DATA_BITS] 		       tdl2dbg_dbg_a;
  input [`FIRE_DBG_DATA_BITS] 		       tdl2dbg_dbg_b;
  output [2:0] 				       dbg2tdl_dbg_sel_a;
  output [2:0] 				       dbg2tdl_dbg_sel_b;
  
  // TIC debug
  input [`FIRE_DBG_DATA_BITS] 		       tic2dbg_dbg_a;
  input [`FIRE_DBG_DATA_BITS] 		       tic2dbg_dbg_b;
  output [2:0] 				       dbg2tic_dbg_sel_a;
  output [2:0] 				       dbg2tic_dbg_sel_b;
  
  // TEC debug
  input [`FIRE_DBG_DATA_BITS] 		       tec2dbg_dbg_a;
  input [`FIRE_DBG_DATA_BITS] 		       tec2dbg_dbg_b;
  output [2:0] 				       dbg2tec_dbg_sel_a;
  output [2:0] 				       dbg2tec_dbg_sel_b;
  
  
  //************************************************
  //				SIGNALS
  //************************************************
  
  // Debug Port Interface

  // TSB 
  wire [5:0] 				      cr2ts_dbg_sel_a;   // TSB debug select a
  wire [5:0] 				      cr2ts_dbg_sel_b;   // TSB debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      ts2cr_dbg_a;       // TSB debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      ts2cr_dbg_b;       // TSB debug output b
   
  // TTG
  wire [2:0] 				      dbg2ttg_dbg_sel_a; // TTG debug select a
  wire [2:0] 				      dbg2ttg_dbg_sel_b; // TTG debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      ttg2dbg_dbg_a;     // TTG debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      ttg2dbg_dbg_b;     // TTG debug output b
   
  // TDL
  wire [2:0] 				      dbg2tdl_dbg_sel_a; // TDL debug select a
  wire [2:0] 				      dbg2tdl_dbg_sel_b; // TDL debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      tdl2dbg_dbg_a;     // TDL debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      tdl2dbg_dbg_b;     // TDL debug output b
   
  // TIC
  wire [2:0] 				      dbg2tic_dbg_sel_a; // TIC debug select a
  wire [2:0] 				      dbg2tic_dbg_sel_b; // TIC debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      tic2dbg_dbg_a;     // TIC debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      tic2dbg_dbg_b;     // TIC debug output b
   
  // TEC 
  wire [2:0] 				      dbg2tec_dbg_sel_a; // TEC debug select a
  wire [2:0] 				      dbg2tec_dbg_sel_b; // TEC debug select b
   
  wire [`FIRE_DBG_DATA_BITS] 		      tec2dbg_dbg_a;     // TEC debug output a
  wire [`FIRE_DBG_DATA_BITS] 		      tec2dbg_dbg_b;     // TEC debug output b

  // *************** Local Declarations *************************************
  reg [`FIRE_DBG_DATA_BITS] 		      dbg_bus [0:1];
  reg [`FIRE_DBG_DATA_BITS] 		      nxt_dbg_bus [0:1];
  
  integer 				      i;
  
  //************************************************
  // Zero In checkers
  //************************************************
  
  
  // *************** Procedures *************************************
  
  // ********************** signal registers *************************/
  
  always @ (cr2ts_dbg_sel_a or ttg2dbg_dbg_a or tdl2dbg_dbg_a 
            or tic2dbg_dbg_a  or tec2dbg_dbg_a) 
    begin
      case (cr2ts_dbg_sel_a[5:3]) // synopsys infer_mux
	3'b000: nxt_dbg_bus[0] = ttg2dbg_dbg_a;
	3'b001: nxt_dbg_bus[0] = tdl2dbg_dbg_a;
	3'b010: nxt_dbg_bus[0] = tic2dbg_dbg_a;
	3'b011: nxt_dbg_bus[0] = tec2dbg_dbg_a;
	3'b100: nxt_dbg_bus[0] = 8'h00;
	3'b101: nxt_dbg_bus[0] = 8'h00;
	3'b110: nxt_dbg_bus[0] = 8'h00;
	3'b111: nxt_dbg_bus[0] = 8'h00;
      endcase // case(cr2ts_dbg_sel_a[5:3])
    end // always @ (cr2ts_dbg_sel_a or ttg2dbg_dbg_a or tdl2dbg_dbg_a...
  
  always @ (cr2ts_dbg_sel_b or ttg2dbg_dbg_b or tdl2dbg_dbg_b 
            or tic2dbg_dbg_b or tec2dbg_dbg_b ) 
    begin
      case (cr2ts_dbg_sel_b[5:3]) // synopsys infer_mux
	3'b000: nxt_dbg_bus[1] = ttg2dbg_dbg_b;
	3'b001: nxt_dbg_bus[1] = tdl2dbg_dbg_b;
	3'b010: nxt_dbg_bus[1] = tic2dbg_dbg_b;
	3'b011: nxt_dbg_bus[1] = tec2dbg_dbg_b;
	3'b100: nxt_dbg_bus[1] = 8'h00;
	3'b101: nxt_dbg_bus[1] = 8'h00;
	3'b110: nxt_dbg_bus[1] = 8'h00;
	3'b111: nxt_dbg_bus[1] = 8'h00;
      endcase // case(cr2ts_dbg_sel_b[5:3])
    end // always @ (cr2ts_dbg_sel_b or ttg2dbg_dbg_b or tdl2dbg_dbg_b...
  
  // ********************** Output Procedures ***********************/
  
  always @ (posedge clk)
    begin 
      if(~rst_l) 
	for (i = 0; i < 2; i = i + 1)
	  dbg_bus[i] <= 8'h00;
      else 
	for (i = 0; i < 2; i = i + 1)
	  dbg_bus[i] <= nxt_dbg_bus[i];
    end // always @ (posedge clk)
  
  
  // ***********************Assignments *****************************/
  
  // debug select ab data port distribution
  assign dbg2ttg_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
  assign dbg2ttg_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
  assign dbg2tdl_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
  assign dbg2tdl_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
  assign dbg2tic_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
  assign dbg2tic_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
  assign dbg2tec_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
  assign dbg2tec_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
  
  // Output
  assign ts2cr_dbg_a = dbg_bus[0];
  assign ts2cr_dbg_b = dbg_bus[1];
  
endmodule // dmu_tsb_dbg
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_tsb_dbg.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_tsb_dbg
	36	(
	37	clk,
	38	rst_l,
	39
	40	// TSB
	41	cr2ts_dbg_sel_a, // TSB debug select a
	42	cr2ts_dbg_sel_b, // TSB debug select b
	43
	44	ts2cr_dbg_a, // TSB debug output a
	45	ts2cr_dbg_b, // TSB debug output b
	46
	47	// TTG
	48	dbg2ttg_dbg_sel_a, // TTG debug select a
	49	dbg2ttg_dbg_sel_b, // TTG debug select b
	50
	51	ttg2dbg_dbg_a, // TTG debug output a
	52	ttg2dbg_dbg_b, // TTG debug output b
	53
	54	// TDL
	55	dbg2tdl_dbg_sel_a, // TDL debug select a
	56	dbg2tdl_dbg_sel_b, // TDL debug select b
	57
	58	tdl2dbg_dbg_a, // TDL debug output a
	59	tdl2dbg_dbg_b, // TDL debug output b
	60
	61	// TIC
	62	dbg2tic_dbg_sel_a, // TIC debug select a
	63	dbg2tic_dbg_sel_b, // TIC debug select b
	64
65	tic2dbg_dbg_a, // TIC debug output a
66	tic2dbg_dbg_b, // TIC debug output b
67
68	// TEC
69	dbg2tec_dbg_sel_a, // TEC debug select a
70	dbg2tec_dbg_sel_b, // TEC debug select b
71
72	tec2dbg_dbg_a, // TEC debug output a
73	tec2dbg_dbg_b // TEC debug output b
74	);
75
76	// synopsys sync_set_reset "rst_l"
77
78	//************************************************
79	// PORTS
80	//************************************************
81
82	input clk;
83	input rst_l;
84
85	// TSB Debug
86	input [5:0] cr2ts_dbg_sel_a;
87	input [5:0] cr2ts_dbg_sel_b;
88	output [`FIRE_DBG_DATA_BITS] ts2cr_dbg_a;
89	output [`FIRE_DBG_DATA_BITS] ts2cr_dbg_b;
90
91	// TTG debug
92	input [`FIRE_DBG_DATA_BITS] ttg2dbg_dbg_a;
93	input [`FIRE_DBG_DATA_BITS] ttg2dbg_dbg_b;
94	output [2:0] dbg2ttg_dbg_sel_a;
95	output [2:0] dbg2ttg_dbg_sel_b;
96
97	// TDL debug
98	input [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_a;
99	input [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_b;
100	output [2:0] dbg2tdl_dbg_sel_a;
101	output [2:0] dbg2tdl_dbg_sel_b;
102
103	// TIC debug
104	input [`FIRE_DBG_DATA_BITS] tic2dbg_dbg_a;
105	input [`FIRE_DBG_DATA_BITS] tic2dbg_dbg_b;
106	output [2:0] dbg2tic_dbg_sel_a;
107	output [2:0] dbg2tic_dbg_sel_b;
108
109	// TEC debug
110	input [`FIRE_DBG_DATA_BITS] tec2dbg_dbg_a;
111	input [`FIRE_DBG_DATA_BITS] tec2dbg_dbg_b;
112	output [2:0] dbg2tec_dbg_sel_a;
113	output [2:0] dbg2tec_dbg_sel_b;
114
115
116	//************************************************
117	// SIGNALS
118	//************************************************
119
120	// Debug Port Interface
121
122	// TSB
123	wire [5:0] cr2ts_dbg_sel_a; // TSB debug select a
124	wire [5:0] cr2ts_dbg_sel_b; // TSB debug select b
125
126	wire [`FIRE_DBG_DATA_BITS] ts2cr_dbg_a; // TSB debug output a
127	wire [`FIRE_DBG_DATA_BITS] ts2cr_dbg_b; // TSB debug output b
128
129	// TTG
130	wire [2:0] dbg2ttg_dbg_sel_a; // TTG debug select a
131	wire [2:0] dbg2ttg_dbg_sel_b; // TTG debug select b
132
133	wire [`FIRE_DBG_DATA_BITS] ttg2dbg_dbg_a; // TTG debug output a
134	wire [`FIRE_DBG_DATA_BITS] ttg2dbg_dbg_b; // TTG debug output b
135
136	// TDL
137	wire [2:0] dbg2tdl_dbg_sel_a; // TDL debug select a
138	wire [2:0] dbg2tdl_dbg_sel_b; // TDL debug select b
139
140	wire [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_a; // TDL debug output a
141	wire [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_b; // TDL debug output b
142
143	// TIC
144	wire [2:0] dbg2tic_dbg_sel_a; // TIC debug select a
145	wire [2:0] dbg2tic_dbg_sel_b; // TIC debug select b
146
147	wire [`FIRE_DBG_DATA_BITS] tic2dbg_dbg_a; // TIC debug output a
148	wire [`FIRE_DBG_DATA_BITS] tic2dbg_dbg_b; // TIC debug output b
149
150	// TEC
151	wire [2:0] dbg2tec_dbg_sel_a; // TEC debug select a
152	wire [2:0] dbg2tec_dbg_sel_b; // TEC debug select b
153
154	wire [`FIRE_DBG_DATA_BITS] tec2dbg_dbg_a; // TEC debug output a
155	wire [`FIRE_DBG_DATA_BITS] tec2dbg_dbg_b; // TEC debug output b
156
157	// ************* Local Declarations ***********************************
158	reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1];
159	reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1];
160
161	integer i;
162
163	//************************************************
164	// Zero In checkers
165	//************************************************
166
167
168	// ************* Procedures ***********************************
169
170	// ******************** signal registers ***********************/
171
172	always @ (cr2ts_dbg_sel_a or ttg2dbg_dbg_a or tdl2dbg_dbg_a
173	or tic2dbg_dbg_a or tec2dbg_dbg_a)
174	begin
175	case (cr2ts_dbg_sel_a[5:3]) // synopsys infer_mux
176	3'b000: nxt_dbg_bus[0] = ttg2dbg_dbg_a;
177	3'b001: nxt_dbg_bus[0] = tdl2dbg_dbg_a;
178	3'b010: nxt_dbg_bus[0] = tic2dbg_dbg_a;
179	3'b011: nxt_dbg_bus[0] = tec2dbg_dbg_a;
180	3'b100: nxt_dbg_bus[0] = 8'h00;
181	3'b101: nxt_dbg_bus[0] = 8'h00;
182	3'b110: nxt_dbg_bus[0] = 8'h00;
183	3'b111: nxt_dbg_bus[0] = 8'h00;
184	endcase // case(cr2ts_dbg_sel_a[5:3])
185	end // always @ (cr2ts_dbg_sel_a or ttg2dbg_dbg_a or tdl2dbg_dbg_a...
186
187	always @ (cr2ts_dbg_sel_b or ttg2dbg_dbg_b or tdl2dbg_dbg_b
188	or tic2dbg_dbg_b or tec2dbg_dbg_b )
189	begin
190	case (cr2ts_dbg_sel_b[5:3]) // synopsys infer_mux
191	3'b000: nxt_dbg_bus[1] = ttg2dbg_dbg_b;
192	3'b001: nxt_dbg_bus[1] = tdl2dbg_dbg_b;
193	3'b010: nxt_dbg_bus[1] = tic2dbg_dbg_b;
194	3'b011: nxt_dbg_bus[1] = tec2dbg_dbg_b;
195	3'b100: nxt_dbg_bus[1] = 8'h00;
196	3'b101: nxt_dbg_bus[1] = 8'h00;
197	3'b110: nxt_dbg_bus[1] = 8'h00;
198	3'b111: nxt_dbg_bus[1] = 8'h00;
199	endcase // case(cr2ts_dbg_sel_b[5:3])
200	end // always @ (cr2ts_dbg_sel_b or ttg2dbg_dbg_b or tdl2dbg_dbg_b...
201
202	// ******************** Output Procedures *********************/
203
204	always @ (posedge clk)
205	begin
206	if(~rst_l)
207	for (i = 0; i < 2; i = i + 1)
208	dbg_bus[i] <= 8'h00;
209	else
210	for (i = 0; i < 2; i = i + 1)
211	dbg_bus[i] <= nxt_dbg_bus[i];
212	end // always @ (posedge clk)
213
214
215	// *********************Assignments ***************************/
216
217	// debug select ab data port distribution
218	assign dbg2ttg_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
219	assign dbg2ttg_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
220	assign dbg2tdl_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
221	assign dbg2tdl_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
222	assign dbg2tic_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
223	assign dbg2tic_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
224	assign dbg2tec_dbg_sel_a = cr2ts_dbg_sel_a [2:0];
225	assign dbg2tec_dbg_sel_b = cr2ts_dbg_sel_b [2:0];
226
227	// Output
228	assign ts2cr_dbg_a = dbg_bus[0];
229	assign ts2cr_dbg_b = dbg_bus[1];
230
231	endmodule // dmu_tsb_dbg
232