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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_tsb_tdl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_tsb_tdl | |
36 | ( | |
37 | // Control Signals | |
38 | ||
39 | clk, | |
40 | rst_l, | |
41 | ||
42 | // Input from TIC Controller to TDL (Write Data) | |
43 | tic2tdl_wr_in, | |
44 | tic2tdl_trtag_in, | |
45 | tic2tdl_wr_data_in, | |
46 | tic2tdl_req_in, | |
47 | ||
48 | // Input from TEC Controller to TDL (Write Data) | |
49 | tec2tdl_wr_in, | |
50 | tec2tdl_trtag_in, | |
51 | tec2tdl_wr_data_in, | |
52 | tec2tdl_req_in, | |
53 | ||
54 | // Output from TDL to TEC Controller (Read Data) | |
55 | tdl2tec_rd_data_out, | |
56 | ||
57 | // CSR interface | |
58 | ext_addr, | |
59 | ||
60 | tsb_dma_ext_done, | |
61 | tsb_dma_ext_select, | |
62 | tsb_dma_ext_rd_data, | |
63 | ||
64 | // Debug Ports | |
65 | tdl2dbg_dbg_a, | |
66 | tdl2dbg_dbg_b, | |
67 | dbg2tdl_dbg_sel_a, | |
68 | dbg2tdl_dbg_sel_b | |
69 | ); | |
70 | ||
71 | // synopsys sync_set_reset "rst_l" | |
72 | ||
73 | ////////////////////////////////////////////////////////////////////// | |
74 | //************************* Parameters ************************* | |
75 | ////////////////////////////////////////////////////////////////////// | |
76 | ||
77 | parameter DEPTH = 32; //32 | |
78 | parameter DCD_TAG_WIDTH = 32; //32 | |
79 | ||
80 | ////////////////////////////////////////////////////////////////////// | |
81 | //************************* Port Declarations ******************* | |
82 | ////////////////////////////////////////////////////////////////////// | |
83 | ||
84 | // Control signals | |
85 | input clk; | |
86 | input rst_l; | |
87 | ||
88 | // TIC to TDL Interface | |
89 | input tic2tdl_wr_in; | |
90 | input [`FIRE_DLC_TSR_TRN_WDTH-1:0] tic2tdl_trtag_in; | |
91 | input [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] tic2tdl_wr_data_in; | |
92 | input tic2tdl_req_in; | |
93 | ||
94 | // TEC to TDL Interface | |
95 | input tec2tdl_wr_in; | |
96 | input [`FIRE_DLC_TSR_TRN_WDTH-1:0] tec2tdl_trtag_in; | |
97 | input [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] tec2tdl_wr_data_in; | |
98 | input tec2tdl_req_in; | |
99 | ||
100 | // TDL to TEC Interface | |
101 | output [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] tdl2tec_rd_data_out; | |
102 | ||
103 | // CSR Interface | |
104 | input [`FIRE_DLC_TSR_TRN_WDTH-1:0] ext_addr; | |
105 | input tsb_dma_ext_select; | |
106 | ||
107 | output tsb_dma_ext_done; | |
108 | output [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] tsb_dma_ext_rd_data; // SAME AS tdl2tec_rd_data_out | |
109 | ||
110 | ||
111 | // Debug Ports | |
112 | ||
113 | output [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_a; | |
114 | output [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_b; | |
115 | ||
116 | input [2:0] dbg2tdl_dbg_sel_a; | |
117 | input [2:0] dbg2tdl_dbg_sel_b; | |
118 | ||
119 | ////////////////////////////////////////////////////////////////////// | |
120 | //*********************** Wires and Regs ************************ | |
121 | ////////////////////////////////////////////////////////////////////// | |
122 | ||
123 | wire tic2tdl_wr_in; | |
124 | wire [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] tic2tdl_wr_data_in; | |
125 | ||
126 | wire tec2tdl_wr_in; | |
127 | wire [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] tec2tdl_wr_data_in; | |
128 | wire [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] tdl2tec_rd_data_out; | |
129 | ||
130 | wire req_in; | |
131 | reg [DCD_TAG_WIDTH - 1:0] trtag1_dcd; // decoded trtag1 4 bit to 16 bit | |
132 | reg [DCD_TAG_WIDTH - 1:0] trtag2_dcd; // decoded trtag2 4 bit to 16 bit | |
133 | wire [`FIRE_DLC_TSR_TRN_WDTH-1:0] trtag1; | |
134 | wire [`FIRE_DLC_TSR_TRN_WDTH-1:0] trtag2; | |
135 | ||
136 | wire [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] tsb_dma_ext_rd_data; | |
137 | reg tsb_dma_ext_done; | |
138 | ||
139 | reg [`FIRE_DLC_TSR_TRN_WDTH-1:0] dma_addr; | |
140 | reg [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] nxt_wr_data_in [0:DEPTH-1]; | |
141 | ||
142 | wire [DEPTH-1:0] wr_data_ld; | |
143 | wire [DEPTH-1:0] tic_wr_data_ld; | |
144 | wire [DEPTH-1:0] tec_wr_data_ld; | |
145 | ||
146 | integer i, j, k, l; | |
147 | ||
148 | // memory array | |
149 | reg [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] dma_data[0:DEPTH-1]; // memory with 32 - 48 bit entries | |
150 | ||
151 | // debug | |
152 | reg [2:0] dbg_sel [0:1]; | |
153 | reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1]; | |
154 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1]; | |
155 | ||
156 | // debug wires | |
157 | wire [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_a; // TDL debug output a | |
158 | wire [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_b; // TDL debug output b | |
159 | wire [2:0] dbg2tdl_dbg_sel_a; // TDL debug select a | |
160 | wire [2:0] dbg2tdl_dbg_sel_b; // TDL debug select b | |
161 | ||
162 | ////////////////////////////////////////////////////////////////////// | |
163 | // ******** Zero-in checkers************************************ | |
164 | ////////////////////////////////////////////////////////////////////// | |
165 | ||
166 | // 0in decoder -in trtag1 -out trtag1_dcd | |
167 | // 0in decoder -in trtag2 -out trtag2_dcd | |
168 | ||
169 | // 0in bits_on -var tic_wr_data_ld -max 1 | |
170 | // 0in bits_on -var tec_wr_data_ld -max 1 | |
171 | // 0in bits_on -var wr_data_ld -max 2 | |
172 | ||
173 | ////////////////////////////////////////////////////////////////////// | |
174 | // ******** Combinational Logic ************************************ | |
175 | ////////////////////////////////////////////////////////////////////// | |
176 | ||
177 | // debug | |
178 | ||
179 | always @ (dbg2tdl_dbg_sel_a or dbg2tdl_dbg_sel_b) | |
180 | begin | |
181 | dbg_sel[0] = dbg2tdl_dbg_sel_a; | |
182 | dbg_sel[1] = dbg2tdl_dbg_sel_b; | |
183 | end | |
184 | ||
185 | always @ (dbg_sel[0] or dbg_sel[1] or tic2tdl_wr_in or tic2tdl_req_in or tic2tdl_trtag_in | |
186 | or tec2tdl_wr_in or tec2tdl_req_in or tec2tdl_trtag_in or | |
187 | tsb_dma_ext_done or tsb_dma_ext_select or ext_addr) | |
188 | begin | |
189 | for (i = 0; i < 2; i = i + 1) | |
190 | begin | |
191 | case (dbg_sel[i]) // synopsys parallel_case infer_mux | |
192 | 3'b000: nxt_dbg_bus[i] = {1'b0, tic2tdl_wr_in, tic2tdl_req_in, tic2tdl_trtag_in}; | |
193 | 3'b001: nxt_dbg_bus[i] = {1'b0, tec2tdl_wr_in, tec2tdl_req_in, tec2tdl_trtag_in}; | |
194 | 3'b010: nxt_dbg_bus[i] = {1'b0, tsb_dma_ext_done,tsb_dma_ext_select, ext_addr}; | |
195 | 3'b011: nxt_dbg_bus[i] = 8'b0; | |
196 | 3'b100: nxt_dbg_bus[i] = 8'b0; | |
197 | 3'b101: nxt_dbg_bus[i] = 8'b0; | |
198 | 3'b110: nxt_dbg_bus[i] = 8'b0; | |
199 | 3'b111: nxt_dbg_bus[i] = 8'b0; | |
200 | endcase | |
201 | end | |
202 | end | |
203 | ||
204 | assign tdl2dbg_dbg_a = dbg_bus[0]; | |
205 | assign tdl2dbg_dbg_b = dbg_bus[1]; | |
206 | ||
207 | // end debug | |
208 | ||
209 | //-------------------------------------------------------------------- | |
210 | // trtag1 and trtag2 decode | |
211 | //-------------------------------------------------------------------- | |
212 | assign trtag1 = tic2tdl_trtag_in; | |
213 | ||
214 | always @(trtag1) | |
215 | begin | |
216 | trtag1_dcd = {DCD_TAG_WIDTH{1'b0}}; | |
217 | trtag1_dcd[trtag1] = 1'b1; | |
218 | end | |
219 | ||
220 | assign trtag2 = tec2tdl_trtag_in; | |
221 | ||
222 | always @(trtag2) | |
223 | begin | |
224 | trtag2_dcd = {DCD_TAG_WIDTH{1'b0}}; | |
225 | trtag2_dcd[trtag2] = 1'b1; | |
226 | end | |
227 | ||
228 | //-------------------------------------------------------------------- | |
229 | // Scoreboard Controller read from tdl | |
230 | //-------------------------------------------------------------------- | |
231 | ||
232 | assign tdl2tec_rd_data_out = dma_data[dma_addr]; | |
233 | assign tsb_dma_ext_rd_data = tdl2tec_rd_data_out; | |
234 | ||
235 | assign req_in = tic2tdl_req_in | tec2tdl_req_in; | |
236 | ||
237 | // dcm read from tdl | |
238 | ||
239 | always @ (req_in or tsb_dma_ext_select or ext_addr or tec2tdl_trtag_in) | |
240 | if (!req_in && tsb_dma_ext_select) | |
241 | begin | |
242 | dma_addr = ext_addr; | |
243 | tsb_dma_ext_done = 1'b1; | |
244 | end | |
245 | else | |
246 | begin | |
247 | dma_addr = tec2tdl_trtag_in; | |
248 | tsb_dma_ext_done = 1'b0; | |
249 | end | |
250 | ||
251 | // Register array load is determined by the wr_data_load for the individual | |
252 | // address row. This value is generated from a decode of the transaction tag | |
253 | // input and the wr_data input for each agent wanting to perform a write. | |
254 | ||
255 | // load logic to determine which row will get written to | |
256 | assign tic_wr_data_ld = trtag1_dcd & {DEPTH{tic2tdl_wr_in}}; | |
257 | assign tec_wr_data_ld = trtag2_dcd & {DEPTH{tec2tdl_wr_in}}; | |
258 | assign wr_data_ld = tic_wr_data_ld | tec_wr_data_ld; | |
259 | ||
260 | //-------------------------------------------------------------------- | |
261 | // write from scoreboard controllers | |
262 | //-------------------------------------------------------------------- | |
263 | ||
264 | // mux for each row of the flop array to select data from controller 1 or 2 | |
265 | ||
266 | always @ (tec_wr_data_ld or tic2tdl_wr_data_in or tec2tdl_wr_data_in) | |
267 | begin | |
268 | for (j=0; j < DEPTH; j=j+1) | |
269 | begin | |
270 | case(tec_wr_data_ld[j]) // synopsys parallel_case | |
271 | 1'b0 : nxt_wr_data_in[j] = tic2tdl_wr_data_in; | |
272 | 1'b1 : nxt_wr_data_in[j] = tec2tdl_wr_data_in; | |
273 | endcase // case(tec_wr_data_ld [j]) | |
274 | end | |
275 | end | |
276 | ////////////////////////////////////////////////////////////////////// | |
277 | // *********** Sequential Logic ************************************ | |
278 | ////////////////////////////////////////////////////////////////////// | |
279 | ||
280 | always @(posedge clk) | |
281 | begin | |
282 | for (k=0; k < DEPTH; k=k+1) | |
283 | begin | |
284 | if (!rst_l) | |
285 | dma_data[k] <= {`FIRE_DLC_TSR_WR_DATA_WDTH{1'b0}}; | |
286 | else if(wr_data_ld[k]) | |
287 | dma_data[k] <= nxt_wr_data_in[k]; | |
288 | end | |
289 | end | |
290 | ||
291 | // Debug port outputs | |
292 | always @ (posedge clk) | |
293 | begin | |
294 | for (l = 0; l < 2; l = l + 1) | |
295 | begin | |
296 | if(!rst_l) | |
297 | dbg_bus[l] <= 8'h00; | |
298 | else | |
299 | dbg_bus[l] <= nxt_dbg_bus[l]; | |
300 | end | |
301 | end // always @ (posedge clk) | |
302 | ||
303 | endmodule // dmu_tsb_tdl |