projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / synopsys / script / user_cfg.scr
CommitLineData
86530b38
AT		 1# ========== Copyright Header Begin ==========================================
2#
3# OpenSPARC T2 Processor File: user_cfg.scr
4# Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5# 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6#
7# * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8#
9# This program is free software; you can redistribute it and/or modify
10# it under the terms of the GNU General Public License as published by
11# the Free Software Foundation; version 2 of the License.
12#
13# This program is distributed in the hope that it will be useful,
14# but WITHOUT ANY WARRANTY; without even the implied warranty of
15# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16# GNU General Public License for more details.
17#
18# You should have received a copy of the GNU General Public License
19# along with this program; if not, write to the Free Software
20# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21#
22# For the avoidance of doubt, and except that if any non-GPL license
23# choice is available it will apply instead, Sun elects to use only
24# the General Public License version 2 (GPLv2) at this time for any
25# software where a choice of GPL license versions is made
26# available with the language indicating that GPLv2 or any later version
27# may be used, or where a choice of which version of the GPL is applied is
28# otherwise unspecified.
29#
30# Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31# CA 95054 USA or visit www.sun.com if you need additional information or
32# have any questions.
33#
34# ========== Copyright Header End ============================================
35source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr
36
37set rtl_files {\
38libs/cl/cl_rtl_ext.v
39libs/cl/cl_a1/cl_a1.behV
40libs/cl/cl_sc1/cl_sc1.behV
41libs/cl/cl_u1/cl_u1.behV
42libs/cl/cl_dp1/cl_dp1.behV
43libs/cl/cl_mc1/cl_mc1.v
44
45libs/clk/rtl/clkgen_dmu_io.v
46
47libs/n2sram/dp/n2_dmu_dp_144x149s_cust_l/n2_dmu_dp_144x149s_cust/rtl/n2_dmu_dp_144x149s_cust.v
48libs/n2sram/dp/n2_dmu_dp_128x132s_cust_l/n2_dmu_dp_128x132s_cust/rtl/n2_dmu_dp_128x132s_cust.v
49libs/n2sram/dp/n2_dmu_dp_512x60s_cust_l/n2_dmu_dp_512x60s_cust/rtl/n2_dmu_dp_512x60s_cust.v
50libs/n2sram/compiler/physical/n2_com_dp_16x132s_cust_l/n2_com_dp_16x132s_cust/rtl/n2_com_dp_16x132s_cust.v
51libs/n2sram/cams/n2_mmu_cm_64x34s_cust_l/n2_mmu_cm_64x34s_cust/rtl/n2_mmu_cm_64x34s_cust.v
52
53libs/n2sram/sp/n2_iom_sp_devtsb_cust_l/n2_iom_sp_devtsb_cust/rtl/n2_iom_sp_devtsb_cust.v
54libs/clk/n2_clk_pgrid_cust_l/n2_clk_dmu_io_cust/rtl/n2_clk_dmu_io_cust.v
55libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
56
57design/sys/iop/dmu/rtl/dmu.h
58design/sys/iop/dmu/rtl/dmu_clu.h
59design/sys/iop/dmu/rtl/dmu_cmu.h
60design/sys/iop/dmu/rtl/dmu_imu.h
61design/sys/iop/dmu/rtl/dmu_mmu.h
62design/sys/iop/dmu/rtl/dmu_pmu.h
63design/sys/iop/dmu/rtl/dmu_rmu.h
64
65design/sys/iop/dmu/rtl/dmu_imu_iss_defines.h
66design/sys/iop/dmu/rtl/dmu_imu_eqs_defines.h
67design/sys/iop/dmu/rtl/dmu_imu_rds_intx_defines.h
68design/sys/iop/dmu/rtl/dmu_imu_rds_mess_defines.h
69design/sys/iop/dmu/rtl/dmu_imu_rds_msi_defines.h
70design/sys/iop/dmu/rtl/dmu_imu_ics_defines.h
71design/sys/iop/dmu/rtl/dmu_mmu_csr_defines.h
72design/sys/iop/dmu/rtl/dmu_ilu_cib_defines.h
73design/sys/iop/dmu/rtl/dmu_cru_defines.h
74design/sys/iop/dmu/rtl/dmu_psb_defines.h
75design/sys/iop/dmu/rtl/dmu_tsb_defines.h
76
77design/sys/iop/pcie_common/rtl/pcie.h
78design/sys/iop/pcie_common/rtl/pcie_csr_defines.h
79design/sys/iop/pcie_common/rtl/dmu_csrtool_enable_all.h
80design/sys/iop/pcie_common/rtl/dmu_csrtool_enable_none.h
81design/sys/iop/pcie_common/rtl/dmu_pathto_defines.h
82design/sys/iop/pcie_common/rtl/dmu_user_defines.h
83
84design/sys/iop/dmu/rtl/dmu_cb0.v
85design/sys/iop/dmu/rtl/dmu_clu.v
86design/sys/iop/dmu/rtl/dmu_clu_crm.v
87design/sys/iop/dmu/rtl/dmu_clu_crm_arb.v
88design/sys/iop/dmu/rtl/dmu_clu_crm_datactl.v
89design/sys/iop/dmu/rtl/dmu_clu_crm_datapipe.v
90design/sys/iop/dmu/rtl/dmu_clu_crm_pktctlfsm.v
91design/sys/iop/dmu/rtl/dmu_clu_crm_pktgen.v
92design/sys/iop/dmu/rtl/dmu_clu_crm_psbctlfsm.v
93design/sys/iop/dmu/rtl/dmu_clu_ctm.v
94design/sys/iop/dmu/rtl/dmu_clu_ctm_bufmgr.v
95design/sys/iop/dmu/rtl/dmu_clu_ctm_cmdctlfsm.v
96design/sys/iop/dmu/rtl/dmu_clu_ctm_cmdgen.v
97design/sys/iop/dmu/rtl/dmu_clu_ctm_datactlfsm.v
98design/sys/iop/dmu/rtl/dmu_clu_ctm_datapipe.v
99design/sys/iop/dmu/rtl/dmu_clu_ctm_tagmgr.v
100design/sys/iop/dmu/rtl/dmu_clu_debug.v
101design/sys/iop/dmu/rtl/dmu_cmu.v
102design/sys/iop/dmu/rtl/dmu_cmu_clst_aloc.v
103design/sys/iop/dmu/rtl/dmu_cmu_ctx.v
104design/sys/iop/dmu/rtl/dmu_cmu_ctx_aloc.v
105design/sys/iop/dmu/rtl/dmu_cmu_ctx_clstreg_array.v
106design/sys/iop/dmu/rtl/dmu_cmu_ctx_pkseqaloc.v
107design/sys/iop/dmu/rtl/dmu_cmu_ctx_reg_array.v
108design/sys/iop/dmu/rtl/dmu_cmu_dbg.v
109design/sys/iop/dmu/rtl/dmu_cmu_rcm.v
110design/sys/iop/dmu/rtl/dmu_cmu_rcm_schrcd_q.v
111design/sys/iop/dmu/rtl/dmu_cmu_tcm.v
112design/sys/iop/dmu/rtl/dmu_cmu_tcm_pkrcd_q.v
113design/sys/iop/dmu/rtl/dmu_cru.v
114design/sys/iop/dmu/rtl/dmu_cru_addr_decode.v
115design/sys/iop/dmu/rtl/dmu_cru_csr.v
116design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_a_reg.v
117design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_a_reg_entry.v
118design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_b_reg.v
119design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_b_reg_entry.v
120design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_pcie_cfg.v
121design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_pcie_cfg_entry.v
122design/sys/iop/dmu/rtl/dmu_cru_csrpipe_3.v
123design/sys/iop/dmu/rtl/dmu_cru_csrpipe_5.v
124design/sys/iop/dmu/rtl/dmu_cru_default_grp.v
125design/sys/iop/dmu/rtl/dmu_cru_stage_mux_only.v
126design/sys/iop/dmu/rtl/dmu_diu.v
127design/sys/iop/dmu/rtl/dmu_diu_idm.v
128design/sys/iop/dmu/rtl/dmu_diu_idr.v
129design/sys/iop/dmu/rtl/dmu_dou.v
130design/sys/iop/dmu/rtl/dmu_dou_edr.v
131design/sys/iop/dmu/rtl/dmu_dou_epr.v
132design/sys/iop/dmu/rtl/dmu_dsn.v
133design/sys/iop/dmu/rtl/dmu_dsn_ccc_dep.v
134design/sys/iop/dmu/rtl/dmu_dsn_ccc_fsm.v
135design/sys/iop/dmu/rtl/dmu_dsn_ccc_pkt.v
136design/sys/iop/dmu/rtl/dmu_dsn_ctl.v
137design/sys/iop/dmu/rtl/dmu_dsn_mondo_fifo.v
138design/sys/iop/dmu/rtl/dmu_dsn_ucb_flow.v
139design/sys/iop/dmu/rtl/dmu_dsn_ucb_in32.v
140design/sys/iop/dmu/rtl/dmu_dsn_ucb_out32.v
141design/sys/iop/dmu/rtl/dmu_imu.v
142design/sys/iop/dmu/rtl/dmu_imu_dbg.v
143design/sys/iop/dmu/rtl/dmu_imu_dms.v
144design/sys/iop/dmu/rtl/dmu_imu_eqs.v
145design/sys/iop/dmu/rtl/dmu_imu_eqs_addr_decode.v
146design/sys/iop/dmu/rtl/dmu_imu_eqs_csr.v
147design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_base_address.v
148design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_base_address_entry.v
149design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_head.v
150design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_head_entry.v
151design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_tail.v
152design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_tail_entry.v
153design/sys/iop/dmu/rtl/dmu_imu_eqs_csrpipe_109.v
154design/sys/iop/dmu/rtl/dmu_imu_eqs_csrpipe_5.v
155design/sys/iop/dmu/rtl/dmu_imu_eqs_default_grp.v
156design/sys/iop/dmu/rtl/dmu_imu_eqs_fsm.v
157design/sys/iop/dmu/rtl/dmu_imu_eqs_stage_mux_only.v
158design/sys/iop/dmu/rtl/dmu_imu_gcs.v
159design/sys/iop/dmu/rtl/dmu_imu_gcs_arb.v
160design/sys/iop/dmu/rtl/dmu_imu_gcs_csm.v
161design/sys/iop/dmu/rtl/dmu_imu_gcs_gc.v
162design/sys/iop/dmu/rtl/dmu_imu_gcs_gc_cnt.v
163design/sys/iop/dmu/rtl/dmu_imu_gcs_gc_fsm.v
164design/sys/iop/dmu/rtl/dmu_imu_ics.v
165design/sys/iop/dmu/rtl/dmu_imu_ics_addr_decode.v
166design/sys/iop/dmu/rtl/dmu_imu_ics_csr.v
167design/sys/iop/dmu/rtl/dmu_imu_ics_csr_dmc_interrupt_mask_reg.v
168design/sys/iop/dmu/rtl/dmu_imu_ics_csr_dmc_interrupt_mask_reg_entry.v
169design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_eqs_error_log_reg.v
170design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_eqs_error_log_reg_entry.v
171design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_error_log_en_reg.v
172design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_error_log_en_reg_entry.v
173design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_int_en_reg.v
174design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_int_en_reg_entry.v
175design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_logged_error_status_reg.v
176design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_logged_error_status_reg_entry.v
177design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt0.v
178design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt0_entry.v
179design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt1.v
180design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt1_entry.v
181design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cntrl.v
182design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cntrl_entry.v
183design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_rds_error_log_reg.v
184design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_rds_error_log_reg_entry.v
185design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_scs_error_log_reg.v
186design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_scs_error_log_reg_entry.v
187design/sys/iop/dmu/rtl/dmu_imu_ics_csr_mem_64_pcie_offset_reg.v
188design/sys/iop/dmu/rtl/dmu_imu_ics_csr_mem_64_pcie_offset_reg_entry.v
189design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_32_addr_reg.v
190design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_32_addr_reg_entry.v
191design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_64_addr_reg.v
192design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_64_addr_reg_entry.v
193design/sys/iop/dmu/rtl/dmu_imu_ics_csrpipe_15.v
194design/sys/iop/dmu/rtl/dmu_imu_ics_csrpipe_5.v
195design/sys/iop/dmu/rtl/dmu_imu_ics_default_grp.v
196design/sys/iop/dmu/rtl/dmu_imu_ics_stage_mux_only.v
197design/sys/iop/dmu/rtl/dmu_imu_irs.v
198design/sys/iop/dmu/rtl/dmu_imu_iss.v
199design/sys/iop/dmu/rtl/dmu_imu_iss_addr_decode.v
200design/sys/iop/dmu/rtl/dmu_imu_iss_csr.v
201design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_20.v
202design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_20_entry.v
203design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_21.v
204design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_21_entry.v
205design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_22.v
206design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_22_entry.v
207design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_23.v
208design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_23_entry.v
209design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_24.v
210design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_24_entry.v
211design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_25.v
212design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_25_entry.v
213design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_26.v
214design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_26_entry.v
215design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_27.v
216design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_27_entry.v
217design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_28.v
218design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_28_entry.v
219design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_29.v
220design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_29_entry.v
221design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_30.v
222design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_30_entry.v
223design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_31.v
224design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_31_entry.v
225design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_32.v
226design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_32_entry.v
227design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_33.v
228design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_33_entry.v
229design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_34.v
230design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_34_entry.v
231design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_35.v
232design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_35_entry.v
233design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_36.v
234design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_36_entry.v
235design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_37.v
236design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_37_entry.v
237design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_38.v
238design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_38_entry.v
239design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_39.v
240design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_39_entry.v
241design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_40.v
242design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_40_entry.v
243design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_41.v
244design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_41_entry.v
245design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_42.v
246design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_42_entry.v
247design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_43.v
248design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_43_entry.v
249design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_44.v
250design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_44_entry.v
251design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_45.v
252design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_45_entry.v
253design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_46.v
254design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_46_entry.v
255design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_47.v
256design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_47_entry.v
257design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_48.v
258design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_48_entry.v
259design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_49.v
260design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_49_entry.v
261design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_50.v
262design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_50_entry.v
263design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_51.v
264design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_51_entry.v
265design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_52.v
266design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_52_entry.v
267design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_53.v
268design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_53_entry.v
269design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_54.v
270design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_54_entry.v
271design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_55.v
272design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_55_entry.v
273design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_56.v
274design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_56_entry.v
275design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_57.v
276design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_57_entry.v
277design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_58.v
278design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_58_entry.v
279design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_59.v
280design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_59_entry.v
281design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_62.v
282design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_62_entry.v
283design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_63.v
284design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_63_entry.v
285design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_retry_timer.v
286design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_retry_timer_entry.v
287design/sys/iop/dmu/rtl/dmu_imu_iss_csrpipe_5.v
288design/sys/iop/dmu/rtl/dmu_imu_iss_csrpipe_87.v
289design/sys/iop/dmu/rtl/dmu_imu_iss_default_grp.v
290design/sys/iop/dmu/rtl/dmu_imu_iss_fsm.v
291design/sys/iop/dmu/rtl/dmu_imu_iss_stage_mux_only.v
292design/sys/iop/dmu/rtl/dmu_imu_ors.v
293design/sys/iop/dmu/rtl/dmu_imu_rds.v
294design/sys/iop/dmu/rtl/dmu_imu_rds_intx.v
295design/sys/iop/dmu/rtl/dmu_imu_rds_intx_addr_decode.v
296design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr.v
297design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_a_int_clr_reg.v
298design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_a_int_clr_reg_entry.v
299design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_b_int_clr_reg.v
300design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_b_int_clr_reg_entry.v
301design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_c_int_clr_reg.v
302design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_c_int_clr_reg_entry.v
303design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_d_int_clr_reg.v
304design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_d_int_clr_reg_entry.v
305design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csrpipe_1.v
306design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csrpipe_5.v
307design/sys/iop/dmu/rtl/dmu_imu_rds_intx_default_grp.v
308design/sys/iop/dmu/rtl/dmu_imu_rds_intx_stage_mux_only.v
309design/sys/iop/dmu/rtl/dmu_imu_rds_mess.v
310design/sys/iop/dmu/rtl/dmu_imu_rds_mess_addr_decode.v
311design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr.v
312design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_cor_mapping.v
313design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_cor_mapping_entry.v
314design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_fatal_mapping.v
315design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_fatal_mapping_entry.v
316design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_nonfatal_mapping.v
317design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_nonfatal_mapping_entry.v
318design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pm_pme_mapping.v
319design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pm_pme_mapping_entry.v
320design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pme_to_ack_mapping.v
321design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pme_to_ack_mapping_entry.v
322design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csrpipe_1.v
323design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csrpipe_6.v
324design/sys/iop/dmu/rtl/dmu_imu_rds_mess_default_grp.v
325design/sys/iop/dmu/rtl/dmu_imu_rds_mess_stage_mux_only.v
326design/sys/iop/dmu/rtl/dmu_imu_rds_mondo.v
327design/sys/iop/dmu/rtl/dmu_imu_rds_msi.v
328design/sys/iop/dmu/rtl/dmu_imu_rds_msi_addr_decode.v
329design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr.v
330design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_0_reg.v
331design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_0_reg_entry.v
332design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_1_reg.v
333design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_1_reg_entry.v
334design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csrpipe_1.v
335design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csrpipe_3.v
336design/sys/iop/dmu/rtl/dmu_imu_rds_msi_default_grp.v
337design/sys/iop/dmu/rtl/dmu_imu_rds_msi_stage_2_default_grp.v
338design/sys/iop/dmu/rtl/dmu_imu_rds_msi_stage_mux_only.v
339design/sys/iop/dmu/rtl/dmu_imu_rss.v
340design/sys/iop/dmu/rtl/dmu_imu_scs.v
341
342design/sys/iop/dmu/rtl/dmu_mb0.v
343design/sys/iop/dmu/rtl/dmu_pmu.v
344design/sys/iop/dmu/rtl/dmu_pmu_prcd_q.v
345design/sys/iop/dmu/rtl/dmu_pmu_prm.v
346design/sys/iop/dmu/rtl/dmu_psb.v
347design/sys/iop/dmu/rtl/dmu_psb_addr_decode.v
348design/sys/iop/dmu/rtl/dmu_psb_csr.v
349design/sys/iop/dmu/rtl/dmu_psb_csrpipe_1.v
350design/sys/iop/dmu/rtl/dmu_psb_csrpipe_2.v
351design/sys/iop/dmu/rtl/dmu_psb_dbg.v
352design/sys/iop/dmu/rtl/dmu_psb_default_grp.v
353design/sys/iop/dmu/rtl/dmu_psb_pdl.v
354design/sys/iop/dmu/rtl/dmu_psb_ptg.v
355design/sys/iop/dmu/rtl/dmu_psb_stage_mux_only.v
356design/sys/iop/dmu/rtl/dmu_rmu.v
357design/sys/iop/dmu/rtl/dmu_rmu_dbg.v
358design/sys/iop/dmu/rtl/dmu_rmu_lrm.v
359design/sys/iop/dmu/rtl/dmu_rmu_lrm_ictl.v
360design/sys/iop/dmu/rtl/dmu_rmu_lrm_itsb_fsm.v
361design/sys/iop/dmu/rtl/dmu_rmu_lrm_octl.v
362design/sys/iop/dmu/rtl/dmu_rmu_rrm.v
363design/sys/iop/dmu/rtl/dmu_rmu_rrm_efsm.v
364design/sys/iop/dmu/rtl/dmu_rmu_rrm_erel.v
365design/sys/iop/dmu/rtl/dmu_rmu_rrm_etsbfsm.v
366design/sys/iop/dmu/rtl/dmu_tmu.v
367design/sys/iop/dmu/rtl/dmu_tmu_dim.v
368design/sys/iop/dmu/rtl/dmu_tmu_dim_bufmgr.v
369design/sys/iop/dmu/rtl/dmu_tmu_dim_datafsm.v
370design/sys/iop/dmu/rtl/dmu_tmu_dim_datapath.v
371design/sys/iop/dmu/rtl/dmu_tmu_dim_rcdbldr.v
372design/sys/iop/dmu/rtl/dmu_tmu_dim_relgen.v
373design/sys/iop/dmu/rtl/dmu_tmu_dim_xfrfsm.v
374design/sys/iop/dmu/rtl/dmu_tsb.v
375design/sys/iop/dmu/rtl/dmu_tsb_csr.v
376design/sys/iop/dmu/rtl/dmu_tsb_dbg.v
377design/sys/iop/dmu/rtl/dmu_tsb_tdl.v
378design/sys/iop/dmu/rtl/dmu_tsb_ttg.v
379design/sys/iop/dmu/rtl/dmu_mmu.v
380design/sys/iop/dmu/rtl/dmu_mmu_arbiter_rrobin.v
381design/sys/iop/dmu/rtl/dmu_mmu_crb.v
382design/sys/iop/dmu/rtl/dmu_mmu_csr.v
383design/sys/iop/dmu/rtl/dmu_mmu_csr_addr_decode.v
384design/sys/iop/dmu/rtl/dmu_mmu_csr_cim.v
385design/sys/iop/dmu/rtl/dmu_mmu_csr_csr.v
386design/sys/iop/dmu/rtl/dmu_mmu_csr_csrpipe_1.v
387design/sys/iop/dmu/rtl/dmu_mmu_csr_csrpipe_15.v
388design/sys/iop/dmu/rtl/dmu_mmu_csr_ctl.v
389design/sys/iop/dmu/rtl/dmu_mmu_csr_ctl_entry.v
390design/sys/iop/dmu/rtl/dmu_mmu_csr_default_grp.v
391design/sys/iop/dmu/rtl/dmu_mmu_csr_err.v
392design/sys/iop/dmu/rtl/dmu_mmu_csr_err_entry.v
393design/sys/iop/dmu/rtl/dmu_mmu_csr_flta.v
394design/sys/iop/dmu/rtl/dmu_mmu_csr_flta_entry.v
395design/sys/iop/dmu/rtl/dmu_mmu_csr_flts.v
396design/sys/iop/dmu/rtl/dmu_mmu_csr_flts_entry.v
397design/sys/iop/dmu/rtl/dmu_mmu_csr_fsh.v
398design/sys/iop/dmu/rtl/dmu_mmu_csr_fsh_entry.v
399design/sys/iop/dmu/rtl/dmu_mmu_csr_int_en.v
400design/sys/iop/dmu/rtl/dmu_mmu_csr_int_en_entry.v
401design/sys/iop/dmu/rtl/dmu_mmu_csr_log.v
402design/sys/iop/dmu/rtl/dmu_mmu_csr_log_entry.v
403design/sys/iop/dmu/rtl/dmu_mmu_csr_prf0.v
404design/sys/iop/dmu/rtl/dmu_mmu_csr_prf0_entry.v
405design/sys/iop/dmu/rtl/dmu_mmu_csr_prf1.v
406design/sys/iop/dmu/rtl/dmu_mmu_csr_prf1_entry.v
407design/sys/iop/dmu/rtl/dmu_mmu_csr_prfc.v
408design/sys/iop/dmu/rtl/dmu_mmu_csr_prfc_entry.v
409design/sys/iop/dmu/rtl/dmu_mmu_csr_stage_2_default_grp.v
410design/sys/iop/dmu/rtl/dmu_mmu_csr_stage_mux_only.v
411design/sys/iop/dmu/rtl/dmu_mmu_csr_tsb.v
412design/sys/iop/dmu/rtl/dmu_mmu_csr_tsb_entry.v
413design/sys/iop/dmu/rtl/dmu_mmu_irb.v
414design/sys/iop/dmu/rtl/dmu_mmu_orb.v
415design/sys/iop/dmu/rtl/dmu_mmu_pab.v
416design/sys/iop/dmu/rtl/dmu_mmu_ptb.v
417design/sys/iop/dmu/rtl/dmu_mmu_qcb.v
418design/sys/iop/dmu/rtl/dmu_mmu_qcb_qgc.v
419design/sys/iop/dmu/rtl/dmu_mmu_qcb_qmc.v
420design/sys/iop/dmu/rtl/dmu_mmu_rcb.v
421design/sys/iop/dmu/rtl/dmu_mmu_srq.v
422design/sys/iop/dmu/rtl/dmu_mmu_srq_iommu.v
423design/sys/iop/dmu/rtl/dmu_mmu_tcb.v
424design/sys/iop/dmu/rtl/dmu_mmu_tcb_tcc.v
425design/sys/iop/dmu/rtl/dmu_mmu_tcb_tdc.v
426design/sys/iop/dmu/rtl/dmu_mmu_tcb_tmc.v
427design/sys/iop/dmu/rtl/dmu_mmu_tdb.v
428design/sys/iop/dmu/rtl/dmu_mmu_tlb.v
429design/sys/iop/dmu/rtl/dmu_mmu_vab.v
430design/sys/iop/dmu/rtl/dmu_mmu_vtb.v
431design/sys/iop/dmu/rtl/dmu_ilu.v
432design/sys/iop/dmu/rtl/dmu_ilu_cib.v
433design/sys/iop/dmu/rtl/dmu_ilu_cib_addr_decode.v
434design/sys/iop/dmu/rtl/dmu_ilu_cib_cim.v
435design/sys/iop/dmu/rtl/dmu_ilu_cib_csr.v
436design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos.v
437design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos_entry.v
438design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en.v
439design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en_entry.v
440design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en.v
441design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en_entry.v
442design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err.v
443design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err_entry.v
444design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en.v
445design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en_entry.v
446design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_5.v
447design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_6.v
448design/sys/iop/dmu/rtl/dmu_ilu_cib_default_grp.v
449design/sys/iop/dmu/rtl/dmu_ilu_cib_stage_mux_only.v
450design/sys/iop/dmu/rtl/dmu_ilu_eil.v
451design/sys/iop/dmu/rtl/dmu_ilu_eil_bufmgr.v
452design/sys/iop/dmu/rtl/dmu_ilu_eil_datafsm.v
453design/sys/iop/dmu/rtl/dmu_ilu_eil_rcdbldr.v
454design/sys/iop/dmu/rtl/dmu_ilu_eil_relgen.v
455design/sys/iop/dmu/rtl/dmu_ilu_eil_xfrfsm.v
456design/sys/iop/dmu/rtl/dmu_ilu_iil.v
457design/sys/iop/dmu/rtl/dmu_ilu_iil_bufmgr.v
458design/sys/iop/dmu/rtl/dmu_ilu_iil_crdtcnt.v
459design/sys/iop/dmu/rtl/dmu_ilu_iil_parchk.v
460design/sys/iop/dmu/rtl/dmu_ilu_iil_rcdbldr.v
461design/sys/iop/dmu/rtl/dmu_ilu_iil_xfrfsm.v
462design/sys/iop/dmu/rtl/dmu_ilu_isb.v
463design/sys/iop/pcie_common/rtl/csr_sw.v
464design/sys/iop/pcie_common/rtl/dmu_common_ccc.v
465design/sys/iop/pcie_common/rtl/dmu_common_ccc_arb.v
466design/sys/iop/pcie_common/rtl/dmu_common_ccc_cdp.v
467design/sys/iop/pcie_common/rtl/dmu_common_ccc_dep.v
468design/sys/iop/pcie_common/rtl/dmu_common_ccc_fsm.v
469design/sys/iop/pcie_common/rtl/dmu_common_ccc_pkt.v
470design/sys/iop/pcie_common/rtl/pcie_common_dcb.v
471design/sys/iop/pcie_common/rtl/pcie_common_dcc.v
472design/sys/iop/pcie_common/rtl/pcie_common_dcd.v
473design/sys/iop/pcie_common/rtl/pcie_common_dcs.v
474design/sys/iop/pcie_common/rtl/pcie_common_dcs_ism.v
475design/sys/iop/pcie_common/rtl/pcie_common_dcs_osm.v
476design/sys/iop/pcie_common/rtl/pcie_common_dcs_sdp.v
477design/sys/iop/pcie_common/rtl/pcie_dcm_daemon.v
478design/sys/iop/pcie_common/rtl/pcie_common_frr_arbiter.v
479design/sys/iop/pcie_common/rtl/dmu_common_scoreboard_controller.v
480design/sys/iop/pcie_common/rtl/fire_dmc_common_srfifo.v
481design/sys/iop/pcie_common/rtl/dmu_common_simple_fifo.v
482design/sys/iop/pcie_common/rtl/pcie_common_srq.v
483design/sys/iop/pcie_common/rtl/pcie_common_srq_qci.v
484design/sys/iop/pcie_common/rtl/pcie_common_srq_qcp.v
485design/sys/iop/pcie_common/rtl/pcie_common_srq_qdp.v
486design/sys/iop/pcie_common/rtl/pcie_common_sync_flop.v
487
488design/sys/iop/dmu/rtl/dmu_dmc.v
489design/sys/iop/dmu/rtl/dmu.v
490}
491
492set link_library [concat $link_library \
493 dw_foundation.sldb \
494]
495
496
497set mix_files {}
498set top_module dmu
499
500set include_paths {\
501design/sys/iop/pcie_common/rtl \
502design/sys/iop/dmu/rtl \
503}
504
505set black_box_libs {}
506set black_box_designs {}
507set mem_libs {}
508
509set dont_touch_modules {\
510n2_com_dp_16x132s_cust \
511n2_dmu_dp_128x132s_cust \
512n2_dmu_dp_144x149s_cust \
513n2_dmu_dp_512x60s_cust \
514n2_mmu_cm_64x34s_cust \
515n2_iom_sp_devtsb_cust \
516n2_clk_clstr_hdr_cust \
517n2_clk_dmu_io_cust \
518}
519
520set compile_effort "medium"
521
522set compile_flatten_all 1
523
524set compile_no_new_cells_at_top_level false
525
526set default_clk gclk
527set default_clk_freq 350
528set default_setup_skew 0.0
529set default_hold_skew 0.0
530set default_clk_transition 0.05
531set clk_list { \
532 { gclk 350.0 0.000 0.000 0.05} \
533}
534
535set ideal_net_list {}
536set false_path_list {}
537set enforce_input_fanout_one 0
538set allow_outport_drive_innodes 1
539set skip_scan 0
540set add_lockup_latch false
541set chain_count 1
542set scanin_port_list {}
543set scanout_port_list {}
544set scanenable_port global_shift_enable
545set has_test_stub 1
546set scanenable_pin test_stub_no_bist/se
547set long_chain_so_0_net long_chain_so_0
548set short_chain_so_0_net short_chain_so_0
549set so_0_net so_0
550set insert_extra_lockup_latch 0
551set extra_lockup_latch_clk_list {}
Full OpenSPARC design & verification tarball including full HDL.