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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fsr_lib.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module wiz6c2a8n6d2t ( amux, fdo, rd0, rd1, rd2, rd3, rd4, rd5, | |
36 | rdll0, rdll1, rdll2, rdll3, rdll4, rdll5, | |
37 | rxbclk, rxbclklln, rxbclkllp, | |
38 | stciq, stspll, | |
39 | stsrx0, stsrx1, stsrx2, stsrx3, stsrx4, stsrx5, | |
40 | ststx0, ststx1, // STSTX2, STSTX3, | |
41 | txbclk, | |
42 | txn0, txn1, // TXN2, TXN3, | |
43 | txp0, txp1, // TXP2, TXP3, | |
44 | bsinitclk, cfgpll, | |
45 | cfgrx0, cfgrx1, cfgrx2, cfgrx3, cfgrx4, cfgrx5, | |
46 | cfgtx0, cfgtx1, // CFGTX2, CFGTX3, | |
47 | fclk, fclrz, fdi, refclkn, refclkp, rxbclkin, | |
48 | rxn0, rxn1, rxn2, rxn3, rxn4, rxn5, | |
49 | rxp0, rxp1, rxp2, rxp3, rxp4, rxp5, | |
50 | stcicfg, stciclk, stcid, | |
51 | td0, td1, // TD2, TD3, | |
52 | testcfg, testclkr, testclkt, txbclkin, | |
53 | atpgmd, atpgmq, atpgrd, atpgrq, atpgtd, atpgtq, | |
54 | vdd, vdda, vddd, vddr, vddt, vss, vssa ); | |
55 | wire scan_in; | |
56 | wire siclk; | |
57 | wire soclk; | |
58 | wire pce_ov; | |
59 | wire stop; | |
60 | wire se; | |
61 | wire scan_out; | |
62 | ||
63 | ||
64 | output amux, fdo, stciq, | |
65 | txn0, txn1, // TXN2, TXN3, | |
66 | txp0, txp1 //, TXP2, TXP3 | |
67 | ; | |
68 | ||
69 | input bsinitclk, fclk, fclrz, fdi, refclkn, refclkp, | |
70 | rxn0, rxn1, rxn2, rxn3, rxn4, rxn5, | |
71 | rxp0, rxp1, rxp2, rxp3, rxp4, rxp5, | |
72 | stciclk, stcid, testclkr, testclkt, | |
73 | vdd, vdda, vddd, vddr, vddt, vss, vssa; | |
74 | ||
75 | output [11:0] rd0; | |
76 | output [11:0] rd1; | |
77 | output [11:0] rd2; | |
78 | output [11:0] rd3; | |
79 | output [11:0] rd4; // added | |
80 | output [11:0] rd5; // added | |
81 | output [3:0] ststx0; | |
82 | output [3:0] ststx1; | |
83 | //output [3:0] STSTX2; | |
84 | //output [3:0] STSTX3; | |
85 | output [3:0] stspll; | |
86 | output [1:0] rdll0; | |
87 | output [1:0] rdll1; | |
88 | output [1:0] rdll2; | |
89 | output [1:0] rdll3; | |
90 | output [1:0] rdll4; // added | |
91 | output [1:0] rdll5; // added | |
92 | output [7:0] stsrx0; | |
93 | output [7:0] stsrx1; | |
94 | output [7:0] stsrx2; | |
95 | output [7:0] stsrx3; | |
96 | output [7:0] stsrx4; // added | |
97 | output [7:0] stsrx5; // added | |
98 | output [5:0] rxbclk; // added 5:4 | |
99 | output [1:0] txbclk; // deleted 3:2 | |
100 | output [5:0] rxbclklln; // added 5:4 | |
101 | output [5:0] rxbclkllp; // added 5:4 | |
102 | ||
103 | input [11:0] cfgpll; | |
104 | input [27:0] cfgrx0; | |
105 | input [27:0] cfgrx1; | |
106 | input [27:0] cfgrx2; | |
107 | input [27:0] cfgrx3; | |
108 | input [27:0] cfgrx4; // added | |
109 | input [27:0] cfgrx5; // added | |
110 | input [19:0] cfgtx0; | |
111 | input [19:0] cfgtx1; | |
112 | //input [19:0] CFGTX2; | |
113 | //input [19:0] CFGTX3; | |
114 | input [1:0] stcicfg; | |
115 | input [11:0] td0; | |
116 | input [11:0] td1; | |
117 | //input [11:0] TD2; | |
118 | //input [11:0] TD3; | |
119 | input [19:0] testcfg; | |
120 | input [1:0] txbclkin; // deleted 3:2 | |
121 | input [5:0] rxbclkin; // added 5:4 | |
122 | ||
123 | input atpgmd; | |
124 | input [5:0] atpgrd; | |
125 | input [1:0] atpgtd; | |
126 | output atpgmq; | |
127 | output [5:0] atpgrq; | |
128 | output [1:0] atpgtq; | |
129 | ||
130 | wire pll_lock; | |
131 | wire [7:0] pll_lock_cnt_in, pll_lock_cnt; | |
132 | ||
133 | // Misc. outputs | |
134 | assign rdll0 = 2'b00; | |
135 | assign rdll1 = 2'b00; | |
136 | assign rdll2 = 2'b11; | |
137 | assign rdll3 = 2'b11; | |
138 | assign rdll4 = 2'b00; | |
139 | assign rdll5 = 2'b00; | |
140 | assign amux = 1'b0; | |
141 | assign fdo = 1'b0; | |
142 | assign stciq = 1'b0; | |
143 | assign stspll = {3'b000, pll_lock}; | |
144 | ||
145 | // Scan signals for sunv | |
146 | assign scan_in = 1'b0; | |
147 | assign siclk = `CPU.tcu_aclk & `CPU.tcu_mcu_testmode; | |
148 | assign soclk = `CPU.tcu_bclk & `CPU.tcu_mcu_testmode; | |
149 | assign pce_ov = `CPU.tcu_pce_ov; | |
150 | assign stop = 1'b0; | |
151 | assign se = `CPU.tcu_scan_en & `CPU.tcu_mcu_testmode; | |
152 | ||
153 | // ATPG | |
154 | assign atpgmq = atpgmd; | |
155 | assign atpgrq[5:0] = atpgrd[5:0]; | |
156 | assign atpgtq[1:0] = atpgtd[1:0]; | |
157 | ||
158 | assign pll_lock = pll_lock_cnt[7:0] == 8'hff; | |
159 | assign pll_lock_cnt_in[7:0] = pll_lock & cfgpll[0] ? 8'hff : cfgpll[0] ? pll_lock_cnt[7:0] + 8'h1 : 8'h0; | |
160 | dff #(8) ff_pll_lock_cnt ( | |
161 | .l1clk(refclkp), | |
162 | .siclk(siclk), | |
163 | .soclk(soclk), | |
164 | .d(pll_lock_cnt_in[7:0]), | |
165 | .si(8'h0), | |
166 | .so(), | |
167 | .q(pll_lock_cnt[7:0]) | |
168 | ); | |
169 | ||
170 | // Receive SERDES | |
171 | fsr_rx rx0 ( | |
172 | // Outputs | |
173 | .rd (rd0[11:0]), | |
174 | .stsrx (stsrx0[7:0]), | |
175 | .rxbclklln (rxbclklln[0]), | |
176 | .rxbclkllp (rxbclkllp[0]), | |
177 | .rxbclk (rxbclk[0]), | |
178 | ||
179 | // Inputs | |
180 | .rxp (rxp0), | |
181 | .rxn (rxn0), | |
182 | .cfgrx (cfgrx0[27:0]), | |
183 | .rxbclkin (rxbclkin[0]), | |
184 | .pll_ck (refclkp ), | |
185 | .scan_in(scan_in), | |
186 | .scan_out(scan_out), | |
187 | .se(se), | |
188 | .siclk(siclk), | |
189 | .soclk(soclk), | |
190 | .stop(stop), | |
191 | .pce_ov(pce_ov) | |
192 | ); | |
193 | ||
194 | fsr_rx rx1 ( | |
195 | // Outputs | |
196 | .rd (rd1[11:0]), | |
197 | .stsrx (stsrx1[7:0]), | |
198 | .rxbclklln (rxbclklln[1]), | |
199 | .rxbclkllp (rxbclkllp[1]), | |
200 | .rxbclk (rxbclk[1]), | |
201 | ||
202 | // Inputs | |
203 | .rxp (rxp1), | |
204 | .rxn (rxn1), | |
205 | .cfgrx (cfgrx1[27:0]), | |
206 | .rxbclkin (rxbclkin[1]), | |
207 | .pll_ck (refclkp ), | |
208 | .scan_in(scan_in), | |
209 | .scan_out(scan_out), | |
210 | .se(se), | |
211 | .siclk(siclk), | |
212 | .soclk(soclk), | |
213 | .stop(stop), | |
214 | .pce_ov(pce_ov) | |
215 | ); | |
216 | ||
217 | fsr_rx rx2 ( | |
218 | // Outputs | |
219 | .rd (rd2[11:0]), | |
220 | .stsrx (stsrx2[7:0]), | |
221 | .rxbclklln (rxbclklln[2]), | |
222 | .rxbclkllp (rxbclkllp[2]), | |
223 | .rxbclk (rxbclk[2]), | |
224 | ||
225 | // Inputs | |
226 | .rxp (rxp2), | |
227 | .rxn (rxn2), | |
228 | .cfgrx (cfgrx2[27:0]), | |
229 | .rxbclkin (rxbclkin[2]), | |
230 | .pll_ck (refclkp ), | |
231 | .scan_in(scan_in), | |
232 | .scan_out(scan_out), | |
233 | .se(se), | |
234 | .siclk(siclk), | |
235 | .soclk(soclk), | |
236 | .stop(stop), | |
237 | .pce_ov(pce_ov) | |
238 | ); | |
239 | ||
240 | fsr_rx rx3 ( | |
241 | // Outputs | |
242 | .rd (rd3[11:0]), | |
243 | .stsrx (stsrx3[7:0]), | |
244 | .rxbclklln (rxbclklln[3]), | |
245 | .rxbclkllp (rxbclkllp[3]), | |
246 | .rxbclk (rxbclk[3]), | |
247 | ||
248 | // Inputs | |
249 | .rxp (rxp3), | |
250 | .rxn (rxn3), | |
251 | .cfgrx (cfgrx3[27:0]), | |
252 | .rxbclkin (rxbclkin[3]), | |
253 | .pll_ck (refclkp ), | |
254 | .scan_in(scan_in), | |
255 | .scan_out(scan_out), | |
256 | .se(se), | |
257 | .siclk(siclk), | |
258 | .soclk(soclk), | |
259 | .stop(stop), | |
260 | .pce_ov(pce_ov) | |
261 | ); | |
262 | ||
263 | fsr_rx rx4 ( | |
264 | // Outputs | |
265 | .rd (rd4[11:0]), | |
266 | .stsrx (stsrx4[7:0]), | |
267 | .rxbclklln (rxbclklln[4]), | |
268 | .rxbclkllp (rxbclkllp[4]), | |
269 | .rxbclk (rxbclk[4]), | |
270 | ||
271 | // Inputs | |
272 | .rxp (rxp4), | |
273 | .rxn (rxn4), | |
274 | .cfgrx (cfgrx4[27:0]), | |
275 | .rxbclkin (rxbclkin[4]), | |
276 | .pll_ck (refclkp ), | |
277 | .scan_in(scan_in), | |
278 | .scan_out(scan_out), | |
279 | .se(se), | |
280 | .siclk(siclk), | |
281 | .soclk(soclk), | |
282 | .stop(stop), | |
283 | .pce_ov(pce_ov) | |
284 | ); | |
285 | ||
286 | fsr_rx rx5 ( | |
287 | // Outputs | |
288 | .rd (rd5[11:0]), | |
289 | .stsrx (stsrx5[7:0]), | |
290 | .rxbclklln (rxbclklln[5]), | |
291 | .rxbclkllp (rxbclkllp[5]), | |
292 | .rxbclk (rxbclk[5]), | |
293 | ||
294 | // Inputs | |
295 | .rxp (rxp5), | |
296 | .rxn (rxn5), | |
297 | .cfgrx (cfgrx5[27:0]), | |
298 | .rxbclkin (rxbclkin[5]), | |
299 | .pll_ck (refclkp ), | |
300 | .scan_in(scan_in), | |
301 | .scan_out(scan_out), | |
302 | .se(se), | |
303 | .siclk(siclk), | |
304 | .soclk(soclk), | |
305 | .stop(stop), | |
306 | .pce_ov(pce_ov) | |
307 | ); | |
308 | ||
309 | ||
310 | // Transmit SERDES | |
311 | fsr_tx tx0 ( | |
312 | // Outputs | |
313 | .td (td0[11:0]), | |
314 | .ststx (ststx0[3:0]), | |
315 | .txbclk (txbclk[0]), | |
316 | ||
317 | // Inputs | |
318 | .txp (txp0), | |
319 | .txn (txn0), | |
320 | .cfgtx (cfgtx0[19:0]), | |
321 | .txbclkin (txbclkin[0]), | |
322 | .pll_ck (refclkp ), | |
323 | .scan_in(scan_in), | |
324 | .scan_out(scan_out), | |
325 | .se(se), | |
326 | .siclk(siclk), | |
327 | .soclk(soclk), | |
328 | .stop(stop), | |
329 | .pce_ov(pce_ov) | |
330 | ); | |
331 | ||
332 | fsr_tx tx1 ( | |
333 | // Outputs | |
334 | .td (td1[11:0]), | |
335 | .ststx (ststx1[3:0]), | |
336 | .txbclk (txbclk[1]), | |
337 | ||
338 | // Inputs | |
339 | .txp (txp1), | |
340 | .txn (txn1), | |
341 | .cfgtx (cfgtx1[19:0]), | |
342 | .txbclkin (txbclkin[1]), | |
343 | .pll_ck (refclkp ), | |
344 | .scan_in(scan_in), | |
345 | .scan_out(scan_out), | |
346 | .se(se), | |
347 | .siclk(siclk), | |
348 | .soclk(soclk), | |
349 | .stop(stop), | |
350 | .pce_ov(pce_ov) | |
351 | ); | |
352 | ||
353 | endmodule | |
354 | ||
355 | // Created from the WIZ6C2B8N6DX schematic view, | |
356 | // NETLIST TIME: Nov 22 14:38:43 2004 | |
357 | ||
358 | ||
359 | module wiz6c2b8n6d2t ( amux, fdo, rd0, rd1, rd2, rd3, rdll0, rdll1, rdll2, rdll3, rxbclk, rxbclklln, | |
360 | rxbclkllp, stciq, stspll, stsrx0, stsrx1, stsrx2, stsrx3, ststx0, ststx1, | |
361 | ststx2, ststx3, txbclk, | |
362 | txn0, txn1, txn2, txn3, txp0, txp1, txp2, txp3, bsinitclk, cfgpll, cfgrx0, | |
363 | cfgrx1, cfgrx2, cfgrx3, cfgtx0, cfgtx1, cfgtx2, cfgtx3, fclk, fclrz, fdi, | |
364 | refclkn, refclkp, rxbclkin, rxn0, rxn1, rxn2, | |
365 | rxn3, rxp0, rxp1, rxp2, rxp3, stcicfg, stciclk, stcid, td0, td1, td2, td3, | |
366 | testcfg, testclkr, testclkt, txbclkin, | |
367 | atpgmd, atpgmq, atpgrd, atpgrq, atpgtd, atpgtq, | |
368 | vdd, vdda, vddd, vddr, vddt, vss, vssa ); | |
369 | wire scan_in; | |
370 | wire siclk; | |
371 | wire soclk; | |
372 | wire pce_ov; | |
373 | wire stop; | |
374 | wire se; | |
375 | wire scan_out; | |
376 | ||
377 | ||
378 | output amux, fdo, stciq, txn0, txn1, txn2, txn3, txp0, txp1, txp2, txp3; | |
379 | ||
380 | input bsinitclk, fclk, fclrz, fdi, refclkn, refclkp, rxn0, rxn1, rxn2, rxn3, rxp0, rxp1, rxp2, rxp3, stciclk, stcid, testclkr, testclkt, vdd, vdda, vddd, vddr, vddt, vss, vssa; | |
381 | ||
382 | output [11:0] rd0; | |
383 | output [11:0] rd1; | |
384 | output [11:0] rd2; | |
385 | output [11:0] rd3; | |
386 | output [3:0] ststx0; | |
387 | output [3:0] ststx1; | |
388 | output [3:0] ststx2; | |
389 | output [3:0] ststx3; | |
390 | output [3:0] stspll; | |
391 | output [1:0] rdll0; | |
392 | output [1:0] rdll1; | |
393 | output [1:0] rdll3; | |
394 | output [7:0] stsrx0; | |
395 | output [7:0] stsrx1; | |
396 | output [7:0] stsrx2; | |
397 | output [7:0] stsrx3; | |
398 | output [3:0] rxbclk; | |
399 | output [3:0] txbclk; | |
400 | output [3:0] rxbclklln; | |
401 | output [1:0] rdll2; | |
402 | output [3:0] rxbclkllp; | |
403 | ||
404 | input [11:0] cfgpll; | |
405 | input [27:0] cfgrx0; | |
406 | input [27:0] cfgrx1; | |
407 | input [27:0] cfgrx2; | |
408 | input [27:0] cfgrx3; | |
409 | input [19:0] cfgtx0; | |
410 | input [19:0] cfgtx1; | |
411 | input [19:0] cfgtx2; | |
412 | input [19:0] cfgtx3; | |
413 | input [1:0] stcicfg; | |
414 | input [11:0] td0; | |
415 | input [11:0] td1; | |
416 | input [11:0] td2; | |
417 | input [11:0] td3; | |
418 | input [19:0] testcfg; | |
419 | input [3:0] txbclkin; | |
420 | input [3:0] rxbclkin; | |
421 | ||
422 | input atpgmd; | |
423 | input [3:0] atpgrd; | |
424 | input [3:0] atpgtd; | |
425 | output atpgmq; | |
426 | output [3:0] atpgrq; | |
427 | output [3:0] atpgtq; | |
428 | ||
429 | wire pll_lock; | |
430 | wire [7:0] pll_lock_cnt_in, pll_lock_cnt; | |
431 | ||
432 | // Misc. outputs | |
433 | assign rdll0 = 2'b00; | |
434 | assign rdll1 = 2'b00; | |
435 | assign rdll2 = 2'b11; | |
436 | assign rdll3 = 2'b11; | |
437 | assign amux = 1'b0; | |
438 | assign fdo = 1'b0; | |
439 | assign stciq = 1'b0; | |
440 | assign stspll = {3'b000,pll_lock}; | |
441 | ||
442 | // Scan signals for sunv | |
443 | assign scan_in = 1'b0; | |
444 | assign siclk = `CPU.tcu_aclk & `CPU.tcu_mcu_testmode; | |
445 | assign soclk = `CPU.tcu_bclk & `CPU.tcu_mcu_testmode; | |
446 | assign pce_ov = `CPU.tcu_pce_ov; | |
447 | assign stop = 1'b0; | |
448 | assign se = `CPU.tcu_scan_en & `CPU.tcu_mcu_testmode; | |
449 | ||
450 | ||
451 | // ATPG | |
452 | assign atpgmq = atpgmd; | |
453 | assign atpgrq[3:0] = atpgrd[3:0]; | |
454 | assign atpgtq[3:0] = atpgtd[3:0]; | |
455 | ||
456 | assign pll_lock = pll_lock_cnt[7:0] == 8'hff; | |
457 | assign pll_lock_cnt_in[7:0] = pll_lock & cfgpll[0] ? 8'hff : cfgpll[0] ? pll_lock_cnt[7:0] + 8'h1 : 8'h0; | |
458 | dff #(8) ff_pll_lock_cnt ( | |
459 | .l1clk(refclkp), | |
460 | .siclk(siclk), | |
461 | .soclk(soclk), | |
462 | .d(pll_lock_cnt_in[7:0]), | |
463 | .si(8'h0), | |
464 | .so(), | |
465 | .q(pll_lock_cnt[7:0]) | |
466 | ); | |
467 | ||
468 | // 4 Rx ports | |
469 | ||
470 | fsr_rx rx0 ( | |
471 | // Outputs | |
472 | .rd (rd0[11:0]), | |
473 | .stsrx (stsrx0[7:0]), | |
474 | .rxbclklln (rxbclklln[0]), | |
475 | .rxbclkllp (rxbclkllp[0]), | |
476 | .rxbclk (rxbclk[0]), | |
477 | ||
478 | // Inputs | |
479 | .rxp (rxp0), | |
480 | .rxn (rxn0), | |
481 | .cfgrx (cfgrx0[27:0]), | |
482 | .rxbclkin (rxbclkin[0]), | |
483 | .pll_ck (refclkp ), | |
484 | .scan_in(scan_in), | |
485 | .scan_out(scan_out), | |
486 | .se(se), | |
487 | .siclk(siclk), | |
488 | .soclk(soclk), | |
489 | .stop(stop), | |
490 | .pce_ov(pce_ov) | |
491 | ); | |
492 | ||
493 | fsr_rx rx1 ( | |
494 | // Outputs | |
495 | .rd (rd1[11:0]), | |
496 | .stsrx (stsrx1[7:0]), | |
497 | .rxbclklln (rxbclklln[1]), | |
498 | .rxbclkllp (rxbclkllp[1]), | |
499 | .rxbclk (rxbclk[1]), | |
500 | ||
501 | // Inputs | |
502 | .rxp (rxp1), | |
503 | .rxn (rxn1), | |
504 | .cfgrx (cfgrx1[27:0]), | |
505 | .rxbclkin (rxbclkin[1]), | |
506 | .pll_ck (refclkp ), | |
507 | .scan_in(scan_in), | |
508 | .scan_out(scan_out), | |
509 | .se(se), | |
510 | .siclk(siclk), | |
511 | .soclk(soclk), | |
512 | .stop(stop), | |
513 | .pce_ov(pce_ov) | |
514 | ); | |
515 | ||
516 | fsr_rx rx2 ( | |
517 | // Outputs | |
518 | .rd (rd2[11:0]), | |
519 | .stsrx (stsrx2[7:0]), | |
520 | .rxbclklln (rxbclklln[2]), | |
521 | .rxbclkllp (rxbclkllp[2]), | |
522 | .rxbclk (rxbclk[2]), | |
523 | ||
524 | // Inputs | |
525 | .rxp (rxp2), | |
526 | .rxn (rxn2), | |
527 | .cfgrx (cfgrx2[27:0]), | |
528 | .rxbclkin (rxbclkin[2]), | |
529 | .pll_ck (refclkp ), | |
530 | .scan_in(scan_in), | |
531 | .scan_out(scan_out), | |
532 | .se(se), | |
533 | .siclk(siclk), | |
534 | .soclk(soclk), | |
535 | .stop(stop), | |
536 | .pce_ov(pce_ov) | |
537 | ); | |
538 | ||
539 | fsr_rx rx3 ( | |
540 | // Outputs | |
541 | .rd (rd3[11:0]), | |
542 | .stsrx (stsrx3[7:0]), | |
543 | .rxbclklln (rxbclklln[3]), | |
544 | .rxbclkllp (rxbclkllp[3]), | |
545 | .rxbclk (rxbclk[3]), | |
546 | ||
547 | // Inputs | |
548 | .rxp (rxp3), | |
549 | .rxn (rxn3), | |
550 | .cfgrx (cfgrx3[27:0]), | |
551 | .rxbclkin (rxbclkin[3]), | |
552 | .pll_ck (refclkp ), | |
553 | .scan_in(scan_in), | |
554 | .scan_out(scan_out), | |
555 | .se(se), | |
556 | .siclk(siclk), | |
557 | .soclk(soclk), | |
558 | .stop(stop), | |
559 | .pce_ov(pce_ov) | |
560 | ); | |
561 | ||
562 | ||
563 | // 4 Tx ports | |
564 | ||
565 | fsr_tx tx0 ( | |
566 | // Outputs | |
567 | .td (td0[11:0]), | |
568 | .ststx (ststx0[3:0]), | |
569 | .txbclk (txbclk[0]), | |
570 | ||
571 | // Inputs | |
572 | .txp (txp0), | |
573 | .txn (txn0), | |
574 | .cfgtx (cfgtx0[19:0]), | |
575 | .txbclkin (txbclkin[0]), | |
576 | .pll_ck (refclkp ), | |
577 | .scan_in(scan_in), | |
578 | .scan_out(scan_out), | |
579 | .se(se), | |
580 | .siclk(siclk), | |
581 | .soclk(soclk), | |
582 | .stop(stop), | |
583 | .pce_ov(pce_ov) | |
584 | ); | |
585 | ||
586 | fsr_tx tx1 ( | |
587 | // Outputs | |
588 | .td (td1[11:0]), | |
589 | .ststx (ststx1[3:0]), | |
590 | .txbclk (txbclk[1]), | |
591 | ||
592 | // Inputs | |
593 | .txp (txp1), | |
594 | .txn (txn1), | |
595 | .cfgtx (cfgtx1[19:0]), | |
596 | .txbclkin (txbclkin[1]), | |
597 | .pll_ck (refclkp ), | |
598 | .scan_in(scan_in), | |
599 | .scan_out(scan_out), | |
600 | .se(se), | |
601 | .siclk(siclk), | |
602 | .soclk(soclk), | |
603 | .stop(stop), | |
604 | .pce_ov(pce_ov) | |
605 | ); | |
606 | ||
607 | fsr_tx tx2 ( | |
608 | // Outputs | |
609 | .td (td2[11:0]), | |
610 | .ststx (ststx2[3:0]), | |
611 | .txbclk (txbclk[2]), | |
612 | ||
613 | // Inputs | |
614 | .txp (txp2), | |
615 | .txn (txn2), | |
616 | .cfgtx (cfgtx2[19:0]), | |
617 | .txbclkin (txbclkin[2]), | |
618 | .pll_ck (refclkp ), | |
619 | .scan_in(scan_in), | |
620 | .scan_out(scan_out), | |
621 | .se(se), | |
622 | .siclk(siclk), | |
623 | .soclk(soclk), | |
624 | .stop(stop), | |
625 | .pce_ov(pce_ov) | |
626 | ); | |
627 | ||
628 | fsr_tx tx3 ( | |
629 | // Outputs | |
630 | .td (td3[11:0]), | |
631 | .ststx (ststx3[3:0]), | |
632 | .txbclk (txbclk[3]), | |
633 | ||
634 | // Inputs | |
635 | .txp (txp3), | |
636 | .txn (txn3), | |
637 | .cfgtx (cfgtx3[19:0]), | |
638 | .txbclkin (txbclkin[3]), | |
639 | .pll_ck (refclkp ), | |
640 | .scan_in(scan_in), | |
641 | .scan_out(scan_out), | |
642 | .se(se), | |
643 | .siclk(siclk), | |
644 | .soclk(soclk), | |
645 | .stop(stop), | |
646 | .pce_ov(pce_ov) | |
647 | ); | |
648 | ||
649 | ||
650 | endmodule | |
651 | ||
652 | module fsr_rx ( | |
653 | rd, | |
654 | stsrx, | |
655 | rxbclklln, | |
656 | rxbclkllp, | |
657 | rxbclk, | |
658 | rxp, | |
659 | rxn, | |
660 | cfgrx, | |
661 | rxbclkin, | |
662 | pll_ck, | |
663 | scan_in, | |
664 | scan_out, | |
665 | se, | |
666 | siclk, | |
667 | soclk, | |
668 | stop, | |
669 | pce_ov); | |
670 | wire elect_idle; | |
671 | wire sync; | |
672 | wire pll_ck_l; | |
673 | wire l1clk; | |
674 | wire l1clk_l; | |
675 | wire ff_sn0_scanin; | |
676 | wire ff_sn0_scanout; | |
677 | wire sn0; | |
678 | wire ff_sn1_scanin; | |
679 | wire ff_sn1_scanout; | |
680 | wire sn1; | |
681 | wire match_in; | |
682 | wire match_even; | |
683 | wire match_odd; | |
684 | wire match; | |
685 | wire ff_match_scanin; | |
686 | wire ff_match_scanout; | |
687 | wire match_ptr_en; | |
688 | wire ff_match_ptr_scanin; | |
689 | wire ff_match_ptr_scanout; | |
690 | wire [2:0] cnt; | |
691 | wire [2:0] match_ptr; | |
692 | wire [11:0] rd_in; | |
693 | wire [12:0] nb_data; | |
694 | wire rd_en; | |
695 | wire ff_rd_scanin; | |
696 | wire ff_rd_scanout; | |
697 | wire [12:0] nb_data_in; | |
698 | wire ff_nb_data_scanin; | |
699 | wire ff_nb_data_scanout; | |
700 | wire [2:0] cnt_in; | |
701 | wire ff_cnt_scanin; | |
702 | wire ff_cnt_scanout; | |
703 | wire rxbclk_in; | |
704 | wire [2:0] match_ptr_plus_4; | |
705 | wire [2:0] match_ptr_plus_1; | |
706 | wire ff_rxbclk_scanin; | |
707 | wire ff_rxbclk_scanout; | |
708 | wire sync_en; | |
709 | wire ff_sync_scanin; | |
710 | wire ff_sync_scanout; | |
711 | wire [11:0] rd_rev; | |
712 | ||
713 | output [11:0] rd; | |
714 | output [7:0] stsrx; | |
715 | output rxbclklln; | |
716 | output rxbclkllp; | |
717 | output rxbclk; | |
718 | ||
719 | input rxp; | |
720 | input rxn; | |
721 | input [27:0] cfgrx; | |
722 | input rxbclkin; | |
723 | input pll_ck; | |
724 | ||
725 | input scan_in; | |
726 | output scan_out; | |
727 | input se; | |
728 | input siclk; | |
729 | input soclk; | |
730 | input stop; | |
731 | input pce_ov; | |
732 | ||
733 | assign stsrx[7:0] = {4'h0, elect_idle, 1'b0, sync & cfgrx[0], 1'b0}; | |
734 | assign elect_idle = ~rxp & ~rxn & cfgrx[0]; | |
735 | assign pll_ck_l = ~pll_ck; | |
736 | assign rxbclklln = 1'b1; | |
737 | assign rxbclkllp = 1'b0; | |
738 | ||
739 | l1clkhdr_ctl_macro clkgen0 ( | |
740 | .l2clk(pll_ck), | |
741 | .l1en (1'b1 ), | |
742 | .l1clk(l1clk), | |
743 | .pce_ov(pce_ov), | |
744 | .stop(stop), | |
745 | .se(se)); | |
746 | ||
747 | l1clkhdr_ctl_macro clkgen1 ( | |
748 | .l2clk(pll_ck_l), | |
749 | .l1en (1'b1 ), | |
750 | .l1clk(l1clk_l), | |
751 | .pce_ov(pce_ov), | |
752 | .stop(stop), | |
753 | .se(se)); | |
754 | ||
755 | //assign l1clk_l = ~l1clk; | |
756 | ||
757 | msff_ctl_macro ff_sn0 ( | |
758 | .scan_in(ff_sn0_scanin), | |
759 | .scan_out(ff_sn0_scanout), | |
760 | .din(rxp), | |
761 | .dout(sn0), | |
762 | .l1clk(l1clk_l), | |
763 | .siclk(siclk), | |
764 | .soclk(soclk)); | |
765 | ||
766 | msff_ctl_macro ff_sn1 ( | |
767 | .scan_in(ff_sn1_scanin), | |
768 | .scan_out(ff_sn1_scanout), | |
769 | .din(rxp), | |
770 | .dout(sn1), | |
771 | .l1clk(l1clk), | |
772 | .siclk(siclk), | |
773 | .soclk(soclk)); | |
774 | ||
775 | assign match_in = (match_even | match_odd) & (cfgrx[13:12] == 2'h1) ? match_odd & ~match_even : match; | |
776 | msff_ctl_macro ff_match ( | |
777 | .scan_in(ff_match_scanin), | |
778 | .scan_out(ff_match_scanout), | |
779 | .din(match_in), | |
780 | .dout(match), | |
781 | .l1clk(l1clk), | |
782 | .siclk(siclk), | |
783 | .soclk(soclk)); | |
784 | ||
785 | assign match_ptr_en = (match_even | match_odd) & (cfgrx[13:12] == 2'h1); | |
786 | msff_ctl_macro__en_1__width_3 ff_match_ptr ( | |
787 | .scan_in(ff_match_ptr_scanin), | |
788 | .scan_out(ff_match_ptr_scanout), | |
789 | .din(cnt[2:0]), | |
790 | .dout(match_ptr[2:0]), | |
791 | .en(match_ptr_en), | |
792 | .l1clk(l1clk), | |
793 | .siclk(siclk), | |
794 | .soclk(soclk)); | |
795 | ||
796 | assign rd_in[11:0] = {12{cfgrx[0]}} & (match ? nb_data[11:0] : nb_data[12:1]); | |
797 | assign rd_en = cnt[2:0] == match_ptr[2:0]; | |
798 | msff_ctl_macro__en_1__width_12 ff_rd ( | |
799 | .scan_in(ff_rd_scanin), | |
800 | .scan_out(ff_rd_scanout), | |
801 | .din(rd_in[11:0]), | |
802 | .dout(rd_rev[11:0]), | |
803 | .en(rd_en), | |
804 | .l1clk(l1clk), | |
805 | .siclk(siclk), | |
806 | .soclk(soclk)); | |
807 | ||
808 | assign rd[11:0] = {rd_rev[0],rd_rev[1],rd_rev[2],rd_rev[3],rd_rev[4],rd_rev[5], | |
809 | rd_rev[6],rd_rev[7],rd_rev[8],rd_rev[9],rd_rev[10],rd_rev[11]}; | |
810 | ||
811 | assign nb_data_in[12:0] = {sn0,sn1,nb_data[12:2]}; | |
812 | msff_ctl_macro__width_13 ff_nb_data ( | |
813 | .scan_in(ff_nb_data_scanin), | |
814 | .scan_out(ff_nb_data_scanout), | |
815 | .din(nb_data_in[12:0]), | |
816 | .dout(nb_data[12:0]), | |
817 | .l1clk(l1clk), | |
818 | .siclk(siclk), | |
819 | .soclk(soclk)); | |
820 | ||
821 | assign match_odd = nb_data[11:0] == 12'hbfe; | |
822 | assign match_even = nb_data[12:1] == 12'hbfe; | |
823 | ||
824 | assign cnt_in[2:0] = cnt[2:0] == 3'h5 ? 3'h0 : cnt[2:0] + 3'h1; | |
825 | msff_ctl_macro__width_3 ff_cnt ( | |
826 | .scan_in(ff_cnt_scanin), | |
827 | .scan_out(ff_cnt_scanout), | |
828 | .din(cnt_in[2:0]), | |
829 | .dout(cnt[2:0]), | |
830 | .l1clk(l1clk), | |
831 | .siclk(siclk), | |
832 | .soclk(soclk)); | |
833 | ||
834 | assign rxbclk_in = cfgrx[0] & ((cnt[2:0] == match_ptr_plus_4[2:0]) ? 1'b0 : (cnt[2:0] == match_ptr_plus_1[2:0]) ? 1'b1 : rxbclk); | |
835 | msff_ctl_macro ff_rxbclk ( | |
836 | .scan_in(ff_rxbclk_scanin), | |
837 | .scan_out(ff_rxbclk_scanout), | |
838 | .din(rxbclk_in), | |
839 | .dout(rxbclk), | |
840 | .l1clk(l1clk), | |
841 | .siclk(siclk), | |
842 | .soclk(soclk)); | |
843 | ||
844 | assign match_ptr_plus_4[2:0] = match_ptr[2:0] == 3'h0 ? 3'h4 : | |
845 | match_ptr[2:0] == 3'h1 ? 3'h5 : | |
846 | match_ptr[2:0] == 3'h2 ? 3'h0 : | |
847 | match_ptr[2:0] == 3'h3 ? 3'h1 : | |
848 | match_ptr[2:0] == 3'h4 ? 3'h2 : | |
849 | match_ptr[2:0] == 3'h5 ? 3'h3 : 3'h0; | |
850 | ||
851 | ||
852 | assign match_ptr_plus_1[2:0] = match_ptr[2:0] == 3'h0 ? 3'h1 : | |
853 | match_ptr[2:0] == 3'h1 ? 3'h2 : | |
854 | match_ptr[2:0] == 3'h2 ? 3'h3 : | |
855 | match_ptr[2:0] == 3'h3 ? 3'h4 : | |
856 | match_ptr[2:0] == 3'h4 ? 3'h5 : | |
857 | match_ptr[2:0] == 3'h5 ? 3'h0 : 3'h0; | |
858 | ||
859 | ||
860 | assign sync_en = (match_ptr[2:0] == cnt[2:0]) & (cfgrx[13:12] == 2'h1); | |
861 | msff_ctl_macro__en_1 ff_sync ( | |
862 | .scan_in(ff_sync_scanin), | |
863 | .scan_out(ff_sync_scanout), | |
864 | .din(match_ptr_en), | |
865 | .dout(sync), | |
866 | .en(sync_en), | |
867 | .l1clk(l1clk), | |
868 | .siclk(siclk), | |
869 | .soclk(soclk)); | |
870 | ||
871 | // fixscan start: | |
872 | assign ff_sn0_scanin = scan_in ; | |
873 | assign ff_sn1_scanin = ff_sn0_scanout ; | |
874 | assign ff_match_scanin = ff_sn1_scanout ; | |
875 | assign ff_match_ptr_scanin = ff_match_scanout ; | |
876 | assign ff_rd_scanin = ff_match_ptr_scanout ; | |
877 | assign ff_nb_data_scanin = ff_rd_scanout ; | |
878 | assign ff_cnt_scanin = ff_nb_data_scanout ; | |
879 | assign ff_rxbclk_scanin = ff_cnt_scanout ; | |
880 | assign ff_sync_scanin = ff_rxbclk_scanout ; | |
881 | assign scan_out = ff_sync_scanout ; | |
882 | // fixscan end: | |
883 | endmodule | |
884 | ||
885 | module fsr_tx ( | |
886 | txp, | |
887 | txn, | |
888 | ststx, | |
889 | txbclk, | |
890 | td, | |
891 | cfgtx, | |
892 | txbclkin, | |
893 | pll_ck, | |
894 | scan_in, | |
895 | scan_out, | |
896 | se, | |
897 | siclk, | |
898 | soclk, | |
899 | stop, | |
900 | pce_ov); | |
901 | wire l1clk; | |
902 | wire ff_td_reg_scanin; | |
903 | wire ff_td_reg_scanout; | |
904 | wire [11:0] td_reg; | |
905 | wire td_sync_en; | |
906 | wire [2:0] cnt; | |
907 | wire ff_td_sync_in_scanin; | |
908 | wire ff_td_sync_in_scanout; | |
909 | wire [11:0] td_sync_in; | |
910 | wire ff_td_sync_scanin; | |
911 | wire ff_td_sync_scanout; | |
912 | wire [11:0] td_sync; | |
913 | wire [2:0] cnt_in; | |
914 | wire ff_cnt_scanin; | |
915 | wire ff_cnt_scanout; | |
916 | wire txp_out; | |
917 | wire [11:0] td_rev; | |
918 | ||
919 | ||
920 | output txp; | |
921 | output txn; | |
922 | output [3:0] ststx; | |
923 | output txbclk; | |
924 | ||
925 | input [11:0] td; | |
926 | input [19:0] cfgtx; | |
927 | input txbclkin; | |
928 | input pll_ck; | |
929 | ||
930 | input scan_in; | |
931 | output scan_out; | |
932 | input se; | |
933 | input siclk; | |
934 | input soclk; | |
935 | input stop; | |
936 | input pce_ov; | |
937 | ||
938 | assign ststx[3:0] = 4'h0; | |
939 | assign txbclk = 1'b0; | |
940 | ||
941 | l1clkhdr_ctl_macro clkgen ( | |
942 | .l2clk(pll_ck), | |
943 | .l1en (1'b1 ), | |
944 | .l1clk(l1clk), | |
945 | .pce_ov(pce_ov), | |
946 | .stop(stop), | |
947 | .se(se)); | |
948 | ||
949 | assign td_rev[11:0] = {td[0],td[1],td[2],td[3],td[4],td[5],td[6],td[7],td[8],td[9],td[10],td[11]}; | |
950 | msff_ctl_macro__width_12 ff_td_reg ( | |
951 | .scan_in(ff_td_reg_scanin), | |
952 | .scan_out(ff_td_reg_scanout), | |
953 | .din(td_rev[11:0]), | |
954 | .dout(td_reg[11:0]), | |
955 | .l1clk(txbclkin), | |
956 | .siclk(siclk), | |
957 | .soclk(soclk)); | |
958 | ||
959 | assign td_sync_en = cnt[2:0] == 3'h4; | |
960 | msff_ctl_macro__en_1__width_12 ff_td_sync_in ( | |
961 | .scan_in(ff_td_sync_in_scanin), | |
962 | .scan_out(ff_td_sync_in_scanout), | |
963 | .din(td_reg[11:0]), | |
964 | .dout(td_sync_in[11:0]), | |
965 | .en(td_sync_en), | |
966 | .l1clk(l1clk), | |
967 | .siclk(siclk), | |
968 | .soclk(soclk)); | |
969 | ||
970 | msff_ctl_macro__width_12 ff_td_sync ( | |
971 | .scan_in(ff_td_sync_scanin), | |
972 | .scan_out(ff_td_sync_scanout), | |
973 | .din(td_sync_in[11:0]), | |
974 | .dout(td_sync[11:0]), | |
975 | .l1clk(l1clk), | |
976 | .siclk(siclk), | |
977 | .soclk(soclk)); | |
978 | ||
979 | assign cnt_in[2:0] = cnt[2:0] == 3'h5 ? 3'h0 : cnt[2:0] + 3'h1; | |
980 | msff_ctl_macro__width_3 ff_cnt ( | |
981 | .scan_in(ff_cnt_scanin), | |
982 | .scan_out(ff_cnt_scanout), | |
983 | .din(cnt_in[2:0]), | |
984 | .dout(cnt[2:0]), | |
985 | .l1clk(l1clk), | |
986 | .siclk(siclk), | |
987 | .soclk(soclk)); | |
988 | ||
989 | assign txp_out = cnt[2:0] == 3'h0 ? td_sync[0] & pll_ck | td_sync[1] & ~pll_ck : | |
990 | cnt[2:0] == 3'h1 ? td_sync[2] & pll_ck | td_sync[3] & ~pll_ck : | |
991 | cnt[2:0] == 3'h2 ? td_sync[4] & pll_ck | td_sync[5] & ~pll_ck : | |
992 | cnt[2:0] == 3'h3 ? td_sync[6] & pll_ck | td_sync[7] & ~pll_ck : | |
993 | cnt[2:0] == 3'h4 ? td_sync[8] & pll_ck | td_sync[9] & ~pll_ck : | |
994 | cnt[2:0] == 3'h5 ? td_sync[10] & pll_ck | td_sync[11] & ~pll_ck : 1'b0; | |
995 | assign txp = ~cfgtx[18] & cfgtx[0] & txp_out; | |
996 | assign txn = ~cfgtx[18] & cfgtx[0] & ~txp_out; | |
997 | ||
998 | // fixscan start: | |
999 | assign ff_td_reg_scanin = scan_in ; | |
1000 | assign ff_td_sync_in_scanin = ff_td_reg_scanout ; | |
1001 | assign ff_td_sync_scanin = ff_td_sync_in_scanout ; | |
1002 | assign ff_cnt_scanin = ff_td_sync_scanout ; | |
1003 | assign scan_out = ff_cnt_scanout ; | |
1004 | // fixscan end: | |
1005 | endmodule | |
1006 | ||
1007 | ||
1008 | module l1clkhdr_ctl_macro ( | |
1009 | l2clk, | |
1010 | l1en, | |
1011 | pce_ov, | |
1012 | stop, | |
1013 | se, | |
1014 | l1clk); | |
1015 | ||
1016 | ||
1017 | input l2clk; | |
1018 | input l1en; | |
1019 | input pce_ov; | |
1020 | input stop; | |
1021 | input se; | |
1022 | output l1clk; | |
1023 | ||
1024 | ||
1025 | ||
1026 | ||
1027 | ||
1028 | cl_sc1_l1hdr_8x c_0 ( | |
1029 | ||
1030 | ||
1031 | .l2clk(l2clk), | |
1032 | .pce(l1en), | |
1033 | .l1clk(l1clk), | |
1034 | .se(se), | |
1035 | .pce_ov(pce_ov), | |
1036 | .stop(stop) | |
1037 | ); | |
1038 | ||
1039 | ||
1040 | ||
1041 | endmodule | |
1042 | ||
1043 | ||
1044 | ||
1045 | ||
1046 | ||
1047 | ||
1048 | ||
1049 | ||
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | // any PARAMS parms go into naming of macro | |
1056 | ||
1057 | module msff_ctl_macro ( | |
1058 | din, | |
1059 | l1clk, | |
1060 | scan_in, | |
1061 | siclk, | |
1062 | soclk, | |
1063 | dout, | |
1064 | scan_out); | |
1065 | wire [0:0] fdin; | |
1066 | ||
1067 | input [0:0] din; | |
1068 | input l1clk; | |
1069 | input scan_in; | |
1070 | ||
1071 | ||
1072 | input siclk; | |
1073 | input soclk; | |
1074 | ||
1075 | output [0:0] dout; | |
1076 | output scan_out; | |
1077 | assign fdin[0:0] = din[0:0]; | |
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | ||
1083 | ||
1084 | dff #(1) d0_0 ( | |
1085 | .l1clk(l1clk), | |
1086 | .siclk(siclk), | |
1087 | .soclk(soclk), | |
1088 | .d(fdin[0:0]), | |
1089 | .si(scan_in), | |
1090 | .so(scan_out), | |
1091 | .q(dout[0:0]) | |
1092 | ); | |
1093 | ||
1094 | ||
1095 | ||
1096 | ||
1097 | ||
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | ||
1104 | ||
1105 | endmodule | |
1106 | ||
1107 | ||
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | // any PARAMS parms go into naming of macro | |
1120 | ||
1121 | module msff_ctl_macro__en_1__width_3 ( | |
1122 | din, | |
1123 | en, | |
1124 | l1clk, | |
1125 | scan_in, | |
1126 | siclk, | |
1127 | soclk, | |
1128 | dout, | |
1129 | scan_out); | |
1130 | wire [2:0] fdin; | |
1131 | wire [1:0] so; | |
1132 | ||
1133 | input [2:0] din; | |
1134 | input en; | |
1135 | input l1clk; | |
1136 | input scan_in; | |
1137 | ||
1138 | ||
1139 | input siclk; | |
1140 | input soclk; | |
1141 | ||
1142 | output [2:0] dout; | |
1143 | output scan_out; | |
1144 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | dff #(3) d0_0 ( | |
1152 | .l1clk(l1clk), | |
1153 | .siclk(siclk), | |
1154 | .soclk(soclk), | |
1155 | .d(fdin[2:0]), | |
1156 | .si({scan_in,so[1:0]}), | |
1157 | .so({so[1:0],scan_out}), | |
1158 | .q(dout[2:0]) | |
1159 | ); | |
1160 | ||
1161 | ||
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | ||
1171 | ||
1172 | endmodule | |
1173 | ||
1174 | ||
1175 | ||
1176 | ||
1177 | ||
1178 | ||
1179 | ||
1180 | ||
1181 | ||
1182 | ||
1183 | ||
1184 | ||
1185 | ||
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | ||
1191 | ||
1192 | ||
1193 | ||
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | // any PARAMS parms go into naming of macro | |
1199 | ||
1200 | module msff_ctl_macro__width_13 ( | |
1201 | din, | |
1202 | l1clk, | |
1203 | scan_in, | |
1204 | siclk, | |
1205 | soclk, | |
1206 | dout, | |
1207 | scan_out); | |
1208 | wire [12:0] fdin; | |
1209 | wire [11:0] so; | |
1210 | ||
1211 | input [12:0] din; | |
1212 | input l1clk; | |
1213 | input scan_in; | |
1214 | ||
1215 | ||
1216 | input siclk; | |
1217 | input soclk; | |
1218 | ||
1219 | output [12:0] dout; | |
1220 | output scan_out; | |
1221 | assign fdin[12:0] = din[12:0]; | |
1222 | ||
1223 | ||
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | dff #(13) d0_0 ( | |
1229 | .l1clk(l1clk), | |
1230 | .siclk(siclk), | |
1231 | .soclk(soclk), | |
1232 | .d(fdin[12:0]), | |
1233 | .si({scan_in,so[11:0]}), | |
1234 | .so({so[11:0],scan_out}), | |
1235 | .q(dout[12:0]) | |
1236 | ); | |
1237 | ||
1238 | ||
1239 | ||
1240 | ||
1241 | ||
1242 | ||
1243 | ||
1244 | ||
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | endmodule | |
1250 | ||
1251 | ||
1252 | ||
1253 | ||
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | // any PARAMS parms go into naming of macro | |
1275 | ||
1276 | module msff_ctl_macro__en_1 ( | |
1277 | din, | |
1278 | en, | |
1279 | l1clk, | |
1280 | scan_in, | |
1281 | siclk, | |
1282 | soclk, | |
1283 | dout, | |
1284 | scan_out); | |
1285 | wire [0:0] fdin; | |
1286 | ||
1287 | input [0:0] din; | |
1288 | input en; | |
1289 | input l1clk; | |
1290 | input scan_in; | |
1291 | ||
1292 | ||
1293 | input siclk; | |
1294 | input soclk; | |
1295 | ||
1296 | output [0:0] dout; | |
1297 | output scan_out; | |
1298 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
1299 | ||
1300 | ||
1301 | ||
1302 | ||
1303 | ||
1304 | ||
1305 | dff #(1) d0_0 ( | |
1306 | .l1clk(l1clk), | |
1307 | .siclk(siclk), | |
1308 | .soclk(soclk), | |
1309 | .d(fdin[0:0]), | |
1310 | .si(scan_in), | |
1311 | .so(scan_out), | |
1312 | .q(dout[0:0]) | |
1313 | ); | |
1314 | ||
1315 | ||
1316 | ||
1317 | ||
1318 | ||
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | endmodule | |
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | // any PARAMS parms go into naming of macro | |
1338 | ||
1339 | module msff_ctl_macro__width_12 ( | |
1340 | din, | |
1341 | l1clk, | |
1342 | scan_in, | |
1343 | siclk, | |
1344 | soclk, | |
1345 | dout, | |
1346 | scan_out); | |
1347 | wire [11:0] fdin; | |
1348 | wire [10:0] so; | |
1349 | ||
1350 | input [11:0] din; | |
1351 | input l1clk; | |
1352 | input scan_in; | |
1353 | ||
1354 | ||
1355 | input siclk; | |
1356 | input soclk; | |
1357 | ||
1358 | output [11:0] dout; | |
1359 | output scan_out; | |
1360 | assign fdin[11:0] = din[11:0]; | |
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | dff #(12) d0_0 ( | |
1368 | .l1clk(l1clk), | |
1369 | .siclk(siclk), | |
1370 | .soclk(soclk), | |
1371 | .d(fdin[11:0]), | |
1372 | .si({scan_in,so[10:0]}), | |
1373 | .so({so[10:0],scan_out}), | |
1374 | .q(dout[11:0]) | |
1375 | ); | |
1376 | ||
1377 | ||
1378 | ||
1379 | ||
1380 | ||
1381 | ||
1382 | ||
1383 | ||
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | endmodule | |
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | ||
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | // any PARAMS parms go into naming of macro | |
1403 | ||
1404 | module msff_ctl_macro__en_1__width_12 ( | |
1405 | din, | |
1406 | en, | |
1407 | l1clk, | |
1408 | scan_in, | |
1409 | siclk, | |
1410 | soclk, | |
1411 | dout, | |
1412 | scan_out); | |
1413 | wire [11:0] fdin; | |
1414 | wire [10:0] so; | |
1415 | ||
1416 | input [11:0] din; | |
1417 | input en; | |
1418 | input l1clk; | |
1419 | input scan_in; | |
1420 | ||
1421 | ||
1422 | input siclk; | |
1423 | input soclk; | |
1424 | ||
1425 | output [11:0] dout; | |
1426 | output scan_out; | |
1427 | assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}}); | |
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | dff #(12) d0_0 ( | |
1435 | .l1clk(l1clk), | |
1436 | .siclk(siclk), | |
1437 | .soclk(soclk), | |
1438 | .d(fdin[11:0]), | |
1439 | .si({scan_in,so[10:0]}), | |
1440 | .so({so[10:0],scan_out}), | |
1441 | .q(dout[11:0]) | |
1442 | ); | |
1443 | ||
1444 | ||
1445 | ||
1446 | ||
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | endmodule | |
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | // any PARAMS parms go into naming of macro | |
1470 | ||
1471 | module msff_ctl_macro__width_3 ( | |
1472 | din, | |
1473 | l1clk, | |
1474 | scan_in, | |
1475 | siclk, | |
1476 | soclk, | |
1477 | dout, | |
1478 | scan_out); | |
1479 | wire [2:0] fdin; | |
1480 | wire [1:0] so; | |
1481 | ||
1482 | input [2:0] din; | |
1483 | input l1clk; | |
1484 | input scan_in; | |
1485 | ||
1486 | ||
1487 | input siclk; | |
1488 | input soclk; | |
1489 | ||
1490 | output [2:0] dout; | |
1491 | output scan_out; | |
1492 | assign fdin[2:0] = din[2:0]; | |
1493 | ||
1494 | ||
1495 | ||
1496 | ||
1497 | ||
1498 | ||
1499 | dff #(3) d0_0 ( | |
1500 | .l1clk(l1clk), | |
1501 | .siclk(siclk), | |
1502 | .soclk(soclk), | |
1503 | .d(fdin[2:0]), | |
1504 | .si({scan_in,so[1:0]}), | |
1505 | .so({so[1:0],scan_out}), | |
1506 | .q(dout[2:0]) | |
1507 | ); | |
1508 | ||
1509 | ||
1510 | ||
1511 | ||
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | endmodule | |
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | ||
1528 |