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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2b_siu_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2b_siu_dp ( | |
36 | sii_l2t_req, | |
37 | sii_l2b_ecc, | |
38 | tcu_aclk, | |
39 | tcu_bclk, | |
40 | tcu_scan_en, | |
41 | tcu_pce_ov, | |
42 | tcu_clk_stop, | |
43 | scan_in, | |
44 | l2clk, | |
45 | scan_out, | |
46 | evict_l2b_rdma_array_din); | |
47 | wire pce_ov; | |
48 | wire siclk; | |
49 | wire soclk; | |
50 | wire se; | |
51 | wire stop; | |
52 | wire ff_sii_l2t_req_ecc_s3_scanin; | |
53 | wire ff_sii_l2t_req_ecc_s3_scanout; | |
54 | wire [38:0] sii_l2t_req_ecc_s3; | |
55 | wire ff_sii_l2t_req_ecc_s3a_scanin; | |
56 | wire ff_sii_l2t_req_ecc_s3a_scanout; | |
57 | wire [38:0] sii_l2t_req_ecc_s4; | |
58 | ||
59 | ||
60 | input [31:0] sii_l2t_req ; | |
61 | input [6:0] sii_l2b_ecc ; | |
62 | ||
63 | input tcu_aclk; | |
64 | input tcu_bclk; | |
65 | input tcu_scan_en; | |
66 | input tcu_pce_ov; | |
67 | input tcu_clk_stop; | |
68 | input scan_in; | |
69 | input l2clk; | |
70 | ||
71 | ||
72 | output scan_out; | |
73 | output [623:0] evict_l2b_rdma_array_din ; | |
74 | ||
75 | assign pce_ov = tcu_pce_ov; | |
76 | assign siclk = tcu_aclk; | |
77 | assign soclk = tcu_bclk; | |
78 | assign se = tcu_scan_en; | |
79 | assign stop = tcu_clk_stop; | |
80 | ||
81 | wire [623:0] evict_l2b_rdma_array_din; | |
82 | wire [38:0] sii_l2t_req_ecc_s2; | |
83 | ||
84 | //////////////////////////////////////////////////////////////////////////////// | |
85 | // Data arriving from jbus is flopped and fanned out to 624 bits here. | |
86 | //////////////////////////////////////////////////////////////////////////////// | |
87 | ||
88 | ||
89 | l2b_siu_dp_buff_macro__stack_40r__width_39 sii_l2t_req_ecc_s2_slice | |
90 | ( | |
91 | .din ({sii_l2t_req[31:0], sii_l2b_ecc[6:0]}), | |
92 | .dout (sii_l2t_req_ecc_s2) | |
93 | ); | |
94 | ||
95 | ||
96 | l2b_siu_dp_msff_macro__stack_40r__width_39 ff_sii_l2t_req_ecc_s3 | |
97 | ( | |
98 | .scan_in(ff_sii_l2t_req_ecc_s3_scanin), | |
99 | .scan_out(ff_sii_l2t_req_ecc_s3_scanout), | |
100 | .din (sii_l2t_req_ecc_s2[38:0]), | |
101 | .clk (l2clk), | |
102 | .dout (sii_l2t_req_ecc_s3[38:0]), | |
103 | .en (1'b1), | |
104 | .se(se), | |
105 | .siclk(siclk), | |
106 | .soclk(soclk), | |
107 | .pce_ov(pce_ov), | |
108 | .stop(stop) | |
109 | ); | |
110 | ||
111 | ||
112 | ||
113 | // | |
114 | // Phase 2 : SIU inteface and packet format change 2/7/04 | |
115 | // Data is delayed by one clock. | |
116 | // | |
117 | ||
118 | ||
119 | l2b_siu_dp_msff_macro__stack_40r__width_39 ff_sii_l2t_req_ecc_s3a | |
120 | ( | |
121 | .scan_in(ff_sii_l2t_req_ecc_s3a_scanin), | |
122 | .scan_out(ff_sii_l2t_req_ecc_s3a_scanout), | |
123 | .din (sii_l2t_req_ecc_s3[38:0]), | |
124 | .clk (l2clk), | |
125 | .dout (sii_l2t_req_ecc_s4[38:0]), | |
126 | .en (1'b1), | |
127 | .se(se), | |
128 | .siclk(siclk), | |
129 | .soclk(soclk), | |
130 | .pce_ov(pce_ov), | |
131 | .stop(stop) | |
132 | ); | |
133 | ||
134 | ||
135 | //assign evict_l2b_rdma_array_din = {16{sii_l2t_req_ecc_s4[38:0]}} ; | |
136 | ||
137 | ||
138 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_1 | |
139 | ( | |
140 | .dout (evict_l2b_rdma_array_din[38:0]), | |
141 | .din (sii_l2t_req_ecc_s4[38:0]) | |
142 | ); | |
143 | ||
144 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_2 | |
145 | ( | |
146 | .dout (evict_l2b_rdma_array_din[77:39]), | |
147 | .din (sii_l2t_req_ecc_s4[38:0]) | |
148 | ); | |
149 | ||
150 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_3 | |
151 | ( | |
152 | .dout (evict_l2b_rdma_array_din[116:78]), | |
153 | .din (sii_l2t_req_ecc_s4[38:0]) | |
154 | ); | |
155 | ||
156 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_4 | |
157 | ( | |
158 | .dout (evict_l2b_rdma_array_din[155:117]), | |
159 | .din (sii_l2t_req_ecc_s4[38:0]) | |
160 | ); | |
161 | ||
162 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_5 | |
163 | ( | |
164 | .dout (evict_l2b_rdma_array_din[194:156]), | |
165 | .din (sii_l2t_req_ecc_s4[38:0]) | |
166 | ); | |
167 | ||
168 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_6 | |
169 | ( | |
170 | .dout (evict_l2b_rdma_array_din[233:195]), | |
171 | .din (sii_l2t_req_ecc_s4[38:0]) | |
172 | ); | |
173 | ||
174 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_7 | |
175 | ( | |
176 | .dout (evict_l2b_rdma_array_din[272:234]), | |
177 | .din (sii_l2t_req_ecc_s4[38:0]) | |
178 | ); | |
179 | ||
180 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_8 | |
181 | ( | |
182 | .dout (evict_l2b_rdma_array_din[311:273]), | |
183 | .din (sii_l2t_req_ecc_s4[38:0]) | |
184 | ); | |
185 | ||
186 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_9 | |
187 | ( | |
188 | .dout (evict_l2b_rdma_array_din[350:312]), | |
189 | .din (sii_l2t_req_ecc_s4[38:0]) | |
190 | ); | |
191 | ||
192 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_10 | |
193 | ( | |
194 | .dout (evict_l2b_rdma_array_din[389:351]), | |
195 | .din (sii_l2t_req_ecc_s4[38:0]) | |
196 | ); | |
197 | ||
198 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_11 | |
199 | ( | |
200 | .dout (evict_l2b_rdma_array_din[428:390]), | |
201 | .din (sii_l2t_req_ecc_s4[38:0]) | |
202 | ); | |
203 | ||
204 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_12 | |
205 | ( | |
206 | .dout (evict_l2b_rdma_array_din[467:429]), | |
207 | .din (sii_l2t_req_ecc_s4[38:0]) | |
208 | ); | |
209 | ||
210 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_13 | |
211 | ( | |
212 | .dout (evict_l2b_rdma_array_din[506:468]), | |
213 | .din (sii_l2t_req_ecc_s4[38:0]) | |
214 | ); | |
215 | ||
216 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_14 | |
217 | ( | |
218 | .dout (evict_l2b_rdma_array_din[545:507]), | |
219 | .din (sii_l2t_req_ecc_s4[38:0]) | |
220 | ); | |
221 | ||
222 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_15 | |
223 | ( | |
224 | .dout (evict_l2b_rdma_array_din[584:546]), | |
225 | .din (sii_l2t_req_ecc_s4[38:0]) | |
226 | ); | |
227 | ||
228 | l2b_siu_dp_buff_macro__stack_40r__width_39 buff_ff_sii_l2t_req_ecc_s3a_16 | |
229 | ( | |
230 | .dout (evict_l2b_rdma_array_din[623:585]), | |
231 | .din (sii_l2t_req_ecc_s4[38:0]) | |
232 | ); | |
233 | ||
234 | ||
235 | // fixscan start: | |
236 | assign ff_sii_l2t_req_ecc_s3_scanin = scan_in ; | |
237 | assign ff_sii_l2t_req_ecc_s3a_scanin = ff_sii_l2t_req_ecc_s3_scanout; | |
238 | assign scan_out = ff_sii_l2t_req_ecc_s3a_scanout; | |
239 | // fixscan end: | |
240 | endmodule | |
241 | ||
242 | ||
243 | // | |
244 | // buff macro | |
245 | // | |
246 | // | |
247 | ||
248 | ||
249 | ||
250 | ||
251 | ||
252 | module l2b_siu_dp_buff_macro__stack_40r__width_39 ( | |
253 | din, | |
254 | dout); | |
255 | input [38:0] din; | |
256 | output [38:0] dout; | |
257 | ||
258 | ||
259 | ||
260 | ||
261 | ||
262 | ||
263 | buff #(39) d0_0 ( | |
264 | .in(din[38:0]), | |
265 | .out(dout[38:0]) | |
266 | ); | |
267 | ||
268 | ||
269 | ||
270 | ||
271 | ||
272 | ||
273 | ||
274 | ||
275 | endmodule | |
276 | ||
277 | ||
278 | ||
279 | ||
280 | ||
281 | ||
282 | ||
283 | ||
284 | ||
285 | // any PARAMS parms go into naming of macro | |
286 | ||
287 | module l2b_siu_dp_msff_macro__stack_40r__width_39 ( | |
288 | din, | |
289 | clk, | |
290 | en, | |
291 | se, | |
292 | scan_in, | |
293 | siclk, | |
294 | soclk, | |
295 | pce_ov, | |
296 | stop, | |
297 | dout, | |
298 | scan_out); | |
299 | wire l1clk; | |
300 | wire siclk_out; | |
301 | wire soclk_out; | |
302 | wire [37:0] so; | |
303 | ||
304 | input [38:0] din; | |
305 | ||
306 | ||
307 | input clk; | |
308 | input en; | |
309 | input se; | |
310 | input scan_in; | |
311 | input siclk; | |
312 | input soclk; | |
313 | input pce_ov; | |
314 | input stop; | |
315 | ||
316 | ||
317 | ||
318 | output [38:0] dout; | |
319 | ||
320 | ||
321 | output scan_out; | |
322 | ||
323 | ||
324 | ||
325 | ||
326 | cl_dp1_l1hdr_8x c0_0 ( | |
327 | .l2clk(clk), | |
328 | .pce(en), | |
329 | .aclk(siclk), | |
330 | .bclk(soclk), | |
331 | .l1clk(l1clk), | |
332 | .se(se), | |
333 | .pce_ov(pce_ov), | |
334 | .stop(stop), | |
335 | .siclk_out(siclk_out), | |
336 | .soclk_out(soclk_out) | |
337 | ); | |
338 | dff #(39) d0_0 ( | |
339 | .l1clk(l1clk), | |
340 | .siclk(siclk_out), | |
341 | .soclk(soclk_out), | |
342 | .d(din[38:0]), | |
343 | .si({scan_in,so[37:0]}), | |
344 | .so({so[37:0],scan_out}), | |
345 | .q(dout[38:0]) | |
346 | ); | |
347 | ||
348 | ||
349 | ||
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | ||
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | ||
366 | ||
367 | endmodule | |
368 | ||
369 | ||
370 | ||
371 | ||
372 | ||
373 | ||
374 | ||
375 |