projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define SYSCLK_PERIOD 5000
36
37
38// Afara Link Defines
39// ==================
40
41// Reliable Link
42`define AL_RB_CNT 16
43`define AL_RB_IDX 4
44`define AL_RB_WINDOW `AL_RB_IDX'd8
45
46// Afara Link Objects
47`define AL_OBJ_SZ 112
48
49// Afara Link Object Format - Reliable Link
50`define AL_RL_HI 111
51`define AL_RL_LO 103
52`define AL_RL_SZ 9
53
54`define AL_ESN_HI 111
55`define AL_ESN_LO 108
56`define AL_SSN_HI 107
57`define AL_SSN_LO 104
58`define AL_ED 103
59
60// Afara Link Object Format - Congestion
61`define AL_CNG_HI 102
62`define AL_CNG_LO 94
63`define AL_CNG_SZ 9
64
65`define AL_REQ_CNG 102
66`define AL_BSCT_HI 101
67`define AL_BSCT_LO 96
68`define AL_EGR_P_CNG 95
69`define AL_MARK 94
70
71
72// Afara Link Object Format - Acknowledge
73`define AL_ACK_SZ 21
74`define AL_A_COS 93
75`define AL_A_TYP_HI 92
76`define AL_A_TYP_LO 91
77`define AL_A_NACK 90
78`define AL_A_TAG_HI 89
79`define AL_A_TAG_LO 80
80`define AL_A_PORT_HI 79
81`define AL_A_PORT_LO 73
82
83
84// Afara Link Object Format - Request
85`define AL_REQ_SZ 73
86`define AL_R_COS 72
87`define AL_R_TYP_HI 71
88`define AL_R_TYP_LO 70
89`define AL_R_SCR_HI 69
90`define AL_R_SCR_LO 67
91`define AL_R_TCR_HI 66
92`define AL_R_TCR_LO 64
93`define AL_R_TAG_HI 63
94`define AL_R_TAG_LO 54
95`define AL_R_PORT_HI 53
96`define AL_R_PORT_LO 47
97`define AL_R_LEN_HI 46
98`define AL_R_LEN_LO 40
99`define AL_R_ADD_HI 39
100`define AL_R_ADD_LO 0
101
102// Afara Link Object Format - Message
103`define AL_M_MQID_HI 2
104`define AL_M_MQID_LO 0
105
106// Acknowledge Types
107`define AL_ACK_NONE 2'b00
108`define AL_ACK_NPAY 2'b01
109`define AL_ACK_WPAY 2'b10
110
111// Request Types
112`define AL_REQ_NONE 2'b00
113`define AL_REQ_NPAY 2'b01
114`define AL_REQ_WPAY 2'b10
115`define AL_REQ_MSG 2'b11
116
117// Afara Link Frame
118`define AL_FRAME_SZ 144
119
120
121//
122// UCB Packet Type
123// ===============
124//
125`define UCB_READ_NACK 4'b0000 // ack/nack types
126`define UCB_READ_ACK 4'b0001
127`define UCB_WRITE_ACK 4'b0010
128`define UCB_IFILL_ACK 4'b0011
129`define UCB_IFILL_NACK 4'b0111
130
131`define UCB_READ_REQ 4'b0100 // req types
132`define UCB_WRITE_REQ 4'b0101
133`define UCB_IFILL_REQ 4'b0110
134
135`define UCB_INT 4'b1000 // plain interrupt
136`define UCB_INT_VEC 4'b1100 // interrupt with vector
137`define UCB_RESET_VEC 4'b1101 // reset with vector
138`define UCB_IDLE_VEC 4'b1110 // idle with vector
139`define UCB_RESUME_VEC 4'b1111 // resume with vector
140
141
142//
143// UCB Data Packet Format
144// ======================
145//
146`define UCB_NOPAY_PKT_WIDTH 64 // packet without payload
147`define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload
148`define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload
149
150`define UCB_DATA_EXT_HI 191 // (64) extended data
151`define UCB_DATA_EXT_LO 128
152`define UCB_DATA_HI 127 // (64) data
153`define UCB_DATA_LO 64
154`define UCB_RSV_HI 63 // (9) reserved bits
155`define UCB_RSV_LO 55
156`define UCB_ADDR_HI 54 // (40) bit address
157`define UCB_ADDR_LO 15
158`define UCB_SIZE_HI 14 // (3) request size
159`define UCB_SIZE_LO 12
160`define UCB_BUF_HI 11 // (2) buffer ID
161`define UCB_BUF_LO 10
162`define UCB_THR_HI 9 // (6) cpu/thread ID
163`define UCB_THR_LO 4
164`define UCB_PKT_HI 3 // (4) packet type
165`define UCB_PKT_LO 0
166
167`define UCB_DATA_EXT_WIDTH 64
168`define UCB_DATA_WIDTH 64
169`define UCB_RSV_WIDTH 9
170`define UCB_ADDR_WIDTH 40
171`define UCB_SIZE_WIDTH 3
172`define UCB_BUFID_WIDTH 2
173`define UCB_THR_WIDTH 6
174`define UCB_PKT_WIDTH 4
175
176// Size encoding for the UCB_SIZE_HI/LO field
177// 000 - byte
178// 001 - half-word
179// 010 - word
180// 011 - double-word
181`define UCB_SIZE_1B 3'b000
182`define UCB_SIZE_2B 3'b001
183`define UCB_SIZE_4B 3'b010
184`define UCB_SIZE_8B 3'b011
185`define UCB_SIZE_16B 3'b100
186
187
188//
189// UCB Interrupt Packet Format
190// ===========================
191//
192`define UCB_INT_PKT_WIDTH 64
193
194`define UCB_INT_RSV_HI 63 // (7) reserved bits
195`define UCB_INT_RSV_LO 57
196`define UCB_INT_VEC_HI 56 // (6) interrupt vector
197`define UCB_INT_VEC_LO 51
198`define UCB_INT_STAT_HI 50 // (32) interrupt status
199`define UCB_INT_STAT_LO 19
200`define UCB_INT_DEV_HI 18 // (9) device ID
201`define UCB_INT_DEV_LO 10
202//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
203//`define UCB_THR_LO 4 data packet format
204//`define UCB_PKT_HI 3 // (4) packet type shared with
205//`define UCB_PKT_LO 0 // data packet format
206
207`define UCB_INT_RSV_WIDTH 7
208`define UCB_INT_VEC_WIDTH 6
209`define UCB_INT_STAT_WIDTH 32
210`define UCB_INT_DEV_WIDTH 9
211
212
213//
214// FCRAM Bus Widths
215// ================
216//
217`define FCRAM_DQ_WIDTH 16
218`define FCRAM_DQS_WIDTH 2
219`define FCRAM_ADDR_WIDTH 15
220`define FCRAM_BA_WIDTH 2
221
222
223//
224// ENET clock periods
225// ==================
226//
227`define AXGRMII_CLK_PERIOD 6400 // 312.5MHz/2
228`define ENET_GMAC_CLK_PERIOD 8000 // 125MHz
229
230
231//
232// Tomatillo defines
233// =================
234//
235`define SYS_UPA_CLK `SYS.upa_clk
236`define SYS_J_CLK `SYS.j_clk
237`define SYS_P_CLK `SYS.p_clk
238`define SYS_G_CLK `SYS.g_clk
239`define P_PCI33 `TOM_ENV.p_pci33
240`define UPA_RST_N `TOM_ENV.g_rst_l
241`define EXPR_32 `SYS_TOM.`TOM_RST.`COUNT_5
242`define RST_COUNT `SYS_TOM_TOM_RST_COUNT
243`define ARTHUR_MODE 1'b0
244`define JP_TIMESCALE `timescale 1 ps / 1 ps
245`define PCI_CLK_PERIOD 15152 // 66 MHz
246`define UPA_RD_CLK_PERIOD 6666 // 150 MHz
247`define UPA_REF_CLK_PERIOD 7576 // 132 MHz
248`define ICHIP_CLK_PERIOD 30304 // 33 MHz
249
250
251//
252// PCI Device Address Configuration
253// ================================
254//
255`define PRIM_SLAVE1_MEM0_L 64'h0000000000000000
256`define PRIM_SLAVE1_MEM0_H 64'h000000003fff0000
257`define PRIM_SLAVE1_IO0_L 64'h0000000000000000
258`define PRIM_SLAVE1_IO0_H 64'h00000000002f0000
259`define PRIM_SLAVE1_JBUS_BASE 64'h000007ff00000000
260
261`define PRIM_SLAVE2_MEM0_L 64'h0000000040000000
262`define PRIM_SLAVE2_MEM0_H 64'h000000007fffffff
263`define PRIM_SLAVE2_IO0_L 64'h0000000000300000
264`define PRIM_SLAVE2_IO0_H 64'h00000000005fffff
265`define PRIM_SLAVE2_JBUS_BASE 64'h000007ff40000000
266
267`define PCIB_SLAVE1_MEM0_L 64'h0000000000000000
268`define PCIB_SLAVE1_MEM0_H 64'h000000003fff0000
269`define PCIB_SLAVE1_IO0_L 64'h0000000000000000
270`define PCIB_SLAVE1_IO0_H 64'h00000000002fffff
271`define PCIB_SLAVE1_JBUS_BASE 64'h000007f780000000
272
273`define PCIB_SLAVE2_MEM0_L 64'h0000000040000000
274`define PCIB_SLAVE2_MEM0_H 64'h000000007fffffff
275`define PCIB_SLAVE2_IO0_L 64'h0000000000300000
276`define PCIB_SLAVE2_IO0_H 64'h00000000007fffff
277`define PCIB_SLAVE2_JBUS_BASE 64'h000007f7c0000000
278
279
280
281
282
283// Address Map Defines
284// ===================
285`define ADDR_MAP_HI 39
286`define ADDR_MAP_LO 32
287`define IO_ADDR_BIT 39
288
289// CMP space
290`define DRAM_DATA_LO 8'h00
291`define DRAM_DATA_HI 8'h7f
292
293// IOP space
294`define JBUS1 8'h80
295`define HASH_TBL_NRAM_CSR 8'h81
296`define RESERVED_1 8'h82
297`define ENET_MAC_CSR 8'h83
298`define ENET_ING_CSR 8'h84
299`define ENET_EGR_CMD_CSR 8'h85
300`define ENET_EGR_DP_CSR 8'h86
301`define RESERVED_2_LO 8'h87
302`define RESERVED_2_HI 8'h92
303`define BSC_CSR 8'h93
304`define RESERVED_3 8'h94
305`define RAND_GEN_CSR 8'h95
306`define CLOCK_UNIT_CSR 8'h96
307`define DRAM_CSR 8'h97
308`define IOB_MAN_CSR 8'h98
309`define TAP_CSR 8'h99
310`define RESERVED_4_L0 8'h9a
311`define RESERVED_4_HI 8'h9d
312`define CPU_ASI 8'h9e
313`define IOB_INT_CSR 8'h9f
314
315// L2 space
316`define L2C_CSR_LO 8'ha0
317`define L2C_CSR_HI 8'hbf
318
319// More IOP space
320`define JBUS2_LO 8'hc0
321`define JBUS2_HI 8'hfe
322`define SPI_CSR 8'hff
323
324
325//Cache Crossbar Width and Field Defines
326//======================================
327`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
328`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
329`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
330`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
331`define CPX_WIDTH11 134
332`define CPX_WIDTH11c 134c
333`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
334
335`define PCX_VLD 123 //PCX packet valid
336`define PCX_RQ_HI 122 //PCX request type field
337`define PCX_RQ_LO 118
338`define PCX_NC 117 //PCX non-cacheable bit
339`define PCX_R 117 //PCX read/!write bit
340`define PCX_CP_HI 116 //PCX cpu_id field
341`define PCX_CP_LO 114
342`define PCX_TH_HI 113 //PCX Thread field
343`define PCX_TH_LO 112
344`define PCX_BF_HI 111 //PCX buffer id field
345`define PCX_INVALL 111
346`define PCX_BF_LO 109
347`define PCX_WY_HI 108 //PCX replaced L1 way field
348`define PCX_WY_LO 107
349`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
350`define PCX_P_LO 107
351`define PCX_SZ_HI 106 //PCX load/store size field
352`define PCX_SZ_LO 104
353`define PCX_ERR_HI 106 //PCX error field
354`define PCX_ERR_LO 104
355`define PCX_AD_HI 103 //PCX address field
356`define PCX_AD_LO 64
357`define PCX_DA_HI 63 //PCX Store data
358`define PCX_DA_LO 0
359
360`define PCX_SZ_1B 3'b000 // encoding for 1B access
361`define PCX_SZ_2B 3'b001 // encoding for 2B access
362`define PCX_SZ_4B 3'b010 // encoding for 4B access
363`define PCX_SZ_8B 3'b011 // encoding for 8B access
364`define PCX_SZ_16B 3'b100 // encoding for 16B access
365
366`define CPX_VLD 145 //CPX payload packet valid
367
368`define CPX_RQ_HI 144 //CPX Request type
369`define CPX_RQ_LO 141
370`define CPX_L2MISS 140
371`define CPX_ERR_HI 140 //CPX error field
372`define CPX_ERR_LO 138
373`define CPX_NC 137 //CPX non-cacheable
374`define CPX_R 137 //CPX read/!write bit
375`define CPX_TH_HI 136 //CPX thread ID field
376`define CPX_TH_LO 134
377
378//bits 133:128 are shared by different fields
379//for different packet types.
380
381`define CPX_IN_HI 133 //CPX Interrupt source
382`define CPX_IN_LO 128
383
384`define CPX_WYVLD 133 //CPX replaced way valid
385`define CPX_WY_HI 132 //CPX replaced I$/D$ way
386`define CPX_WY_LO 131
387`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
388`define CPX_BF_LO 128
389
390`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
391`define CPX_SI_LO 128 //used for invalidates
392
393`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
394`define CPX_P_LO 130
395
396`define CPX_ASI 130 //CPX forward request to ASI
397`define CPX_IF4B 130
398`define CPX_IINV 124
399`define CPX_DINV 123
400`define CPX_INVPA5 122
401`define CPX_INVPA4 121
402`define CPX_CPUID_HI 120
403`define CPX_CPUID_LO 118
404`define CPX_INV_PA_HI 116
405`define CPX_INV_PA_LO 112
406`define CPX_INV_IDX_HI 117
407`define CPX_INV_IDX_LO 112
408
409`define CPX_DA_HI 127 //CPX data payload
410`define CPX_DA_LO 0
411
412`define LOAD_RQ 5'b00000
413`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
414`define IMISS_RQ 5'b10000
415`define STORE_RQ 5'b00001
416`define CAS1_RQ 5'b00010
417`define CAS2_RQ 5'b00011
418`define SWAP_RQ 5'b00111
419`define STRLOAD_RQ 5'b00100
420`define STRST_RQ 5'b00101
421`define STQ_RQ 5'b00111
422`define INT_RQ 5'b01001
423`define FWD_RQ 5'b01101
424`define FWD_RPY 5'b01110
425`define RSVD_RQ 5'b11111
426
427`define LOAD_RET 4'b0000
428`define INV_RET 4'b0011
429`define ST_ACK 4'b0100
430`define AT_ACK 4'b0011
431`define INT_RET 4'b0111
432`define TEST_RET 4'b0101
433`define FP_RET 4'b1000
434`define IFILL_RET 4'b0001
435`define EVICT_REQ 4'b0011
436//`define INVAL_ACK 4'b1000
437`define INVAL_ACK 4'b0100
438`define ERR_RET 4'b1100
439`define STRLOAD_RET 4'b0010
440`define STRST_ACK 4'b0110
441`define FWD_RQ_RET 4'b1010
442`define FWD_RPY_RET 4'b1011
443`define RSVD_RET 4'b1111
444
445//End cache crossbar defines
446
447
448// Number of COS supported by EECU
449`define EECU_COS_NUM 2
450
451
452//
453// BSC bus sizes
454// =============
455//
456
457// General
458`define BSC_ADDRESS 40
459`define MAX_XFER_LEN 7'b0
460`define XFER_LEN_WIDTH 6
461
462// CTags
463`define BSC_CTAG_SZ 12
464`define EICU_CTAG_PRE 5'b11101
465`define EICU_CTAG_REM 7
466`define EIPU_CTAG_PRE 3'b011
467`define EIPU_CTAG_REM 9
468`define EECU_CTAG_PRE 8'b11010000
469`define EECU_CTAG_REM 4
470`define EEPU_CTAG_PRE 6'b010000
471`define EEPU_CTAG_REM 6
472`define L2C_CTAG_PRE 2'b00
473`define L2C_CTAG_REM 10
474`define JBI_CTAG_PRE 2'b10
475`define JBI_CTAG_REM 10
476// reinstated temporarily
477`define PCI_CTAG_PRE 7'b1101100
478`define PCI_CTAG_REM 5
479
480
481// CoS
482`define EICU_COS 1'b0
483`define EIPU_COS 1'b1
484`define EECU_COS 1'b0
485`define EEPU_COS 1'b1
486`define PCI_COS 1'b0
487
488// L2$ Bank
489`define BSC_L2_BNK_HI 8
490`define BSC_L2_BNK_LO 6
491
492// L2$ Req
493`define BSC_L2_REQ_SZ 62
494`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
495`define BSC_L2_BUS 64
496`define BSC_L2_CTAG_HI 61
497`define BSC_L2_CTAG_LO 50
498`define BSC_L2_ADD_HI 49
499`define BSC_L2_ADD_LO 10
500`define BSC_L2_LEN_HI 9
501`define BSC_L2_LEN_LO 3
502`define BSC_L2_ALLOC 2
503`define BSC_L2_COS 1
504`define BSC_L2_READ 0
505
506// L2$ Ack
507`define L2_BSC_ACK_SZ 16
508`define L2_BSC_BUS 64
509`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
510`define L2_BSC_CBA_LO 13
511`define L2_BSC_READ 12
512`define L2_BSC_CTAG_HI 11
513`define L2_BSC_CTAG_LO 0
514
515// Enet Egress Command Unit
516`define EECU_REQ_BUS 44
517`define EECU_REQ_SZ 44
518`define EECU_R_QID_HI 43
519`define EECU_R_QID_LO 40
520`define EECU_R_ADD_HI 39
521`define EECU_R_ADD_LO 0
522
523`define EECU_ACK_BUS 64
524`define EECU_ACK_SZ 5
525`define EECU_A_NACK 4
526`define EECU_A_QID_HI 3
527`define EECU_A_QID_LO 0
528
529
530// Enet Egress Packet Unit
531`define EEPU_REQ_BUS 55
532`define EEPU_REQ_SZ 55
533`define EEPU_R_TLEN_HI 54
534`define EEPU_R_TLEN_LO 48
535`define EEPU_R_SOF 47
536`define EEPU_R_EOF 46
537`define EEPU_R_PORT_HI 45
538`define EEPU_R_PORT_LO 44
539`define EEPU_R_QID_HI 43
540`define EEPU_R_QID_LO 40
541`define EEPU_R_ADD_HI 39
542`define EEPU_R_ADD_LO 0
543
544// This is cleaved in between Egress Datapath Ack's
545`define EEPU_ACK_BUS 6
546`define EEPU_ACK_SZ 6
547`define EEPU_A_EOF 5
548`define EEPU_A_NACK 4
549`define EEPU_A_QID_HI 3
550`define EEPU_A_QID_LO 0
551
552
553// Enet Egress Datapath
554`define EEDP_ACK_BUS 128
555`define EEDP_ACK_SZ 28
556`define EEDP_A_NACK 27
557`define EEDP_A_QID_HI 26
558`define EEDP_A_QID_LO 21
559`define EEDP_A_SOF 20
560`define EEDP_A_EOF 19
561`define EEDP_A_LEN_HI 18
562`define EEDP_A_LEN_LO 12
563`define EEDP_A_TAG_HI 11
564`define EEDP_A_TAG_LO 0
565`define EEDP_A_PORT_HI 5
566`define EEDP_A_PORT_LO 4
567`define EEDP_A_PORT_WIDTH 2
568
569
570// In-Order / Ordered Queue: EEPU
571// Tag is: TLEN, SOF, EOF, QID = 15
572`define EEPU_TAG_ARY (7+1+1+6)
573`define EEPU_ENTRIES 16
574`define EEPU_E_IDX 4
575`define EEPU_PORTS 4
576`define EEPU_P_IDX 2
577
578// Nack + Tag Info + CTag
579`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
580`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
581
582
583// ENET Ingress Queue Management Req
584`define EICU_REQ_BUS 64
585`define EICU_REQ_SZ 62
586`define EICU_R_CTAG_HI 61
587`define EICU_R_CTAG_LO 50
588`define EICU_R_ADD_HI 49
589`define EICU_R_ADD_LO 10
590`define EICU_R_LEN_HI 9
591`define EICU_R_LEN_LO 3
592`define EICU_R_COS 1
593`define EICU_R_READ 0
594
595
596// ENET Ingress Queue Management Ack
597`define EICU_ACK_BUS 64
598`define EICU_ACK_SZ 14
599`define EICU_A_NACK 13
600`define EICU_A_READ 12
601`define EICU_A_CTAG_HI 11
602`define EICU_A_CTAG_LO 0
603
604
605// Enet Ingress Packet Unit
606`define EIPU_REQ_BUS 128
607`define EIPU_REQ_SZ 59
608`define EIPU_R_CTAG_HI 58
609`define EIPU_R_CTAG_LO 50
610`define EIPU_R_ADD_HI 49
611`define EIPU_R_ADD_LO 10
612`define EIPU_R_LEN_HI 9
613`define EIPU_R_LEN_LO 3
614`define EIPU_R_COS 1
615`define EIPU_R_READ 0
616
617
618// ENET Ingress Packet Unit Ack
619`define EIPU_ACK_BUS 10
620`define EIPU_ACK_SZ 10
621`define EIPU_A_NACK 9
622`define EIPU_A_CTAG_HI 8
623`define EIPU_A_CTAG_LO 0
624
625
626// In-Order / Ordered Queue: PCI
627// Tag is: CTAG
628`define PCI_TAG_ARY 12
629`define PCI_ENTRIES 16
630`define PCI_E_IDX 4
631`define PCI_PORTS 2
632
633// PCI-X Request
634`define PCI_REQ_BUS 64
635`define PCI_REQ_SZ 62
636`define PCI_R_CTAG_HI 61
637`define PCI_R_CTAG_LO 50
638`define PCI_R_ADD_HI 49
639`define PCI_R_ADD_LO 10
640`define PCI_R_LEN_HI 9
641`define PCI_R_LEN_LO 3
642`define PCI_R_COS 1
643`define PCI_R_READ 0
644
645// PCI_X Acknowledge
646`define PCI_ACK_BUS 64
647`define PCI_ACK_SZ 14
648`define PCI_A_NACK 13
649`define PCI_A_READ 12
650`define PCI_A_CTAG_HI 11
651`define PCI_A_CTAG_LO 0
652
653
654`define BSC_MAX_REQ_SZ 62
655
656
657//
658// BSC array sizes
659//================
660//
661`define BSC_REQ_ARY_INDEX 6
662`define BSC_REQ_ARY_DEPTH 64
663`define BSC_REQ_ARY_WIDTH 62
664`define BSC_REQ_NXT_WIDTH 12
665`define BSC_ACK_ARY_INDEX 6
666`define BSC_ACK_ARY_DEPTH 64
667`define BSC_ACK_ARY_WIDTH 14
668`define BSC_ACK_NXT_WIDTH 12
669`define BSC_PAY_ARY_INDEX 6
670`define BSC_PAY_ARY_DEPTH 64
671`define BSC_PAY_ARY_WIDTH 256
672
673// ECC syndrome bits per memory element
674`define BSC_PAY_ECC 10
675`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
676
677
678//
679// BSC Port Definitions
680// ====================
681//
682// Bits 7 to 4 of curr_port_id
683`define BSC_PORT_NULL 4'h0
684`define BSC_PORT_SC 4'h1
685`define BSC_PORT_EICU 4'h2
686`define BSC_PORT_EIPU 4'h3
687`define BSC_PORT_EECU 4'h4
688`define BSC_PORT_EEPU 4'h8
689`define BSC_PORT_PCI 4'h9
690
691// Number of ports of each type
692`define BSC_PORT_SC_CNT 8
693
694// Bits needed to represent above
695`define BSC_PORT_SC_IDX 3
696
697// How wide the linked list pointers are
698// 60b for no payload (2CoS)
699// 80b for payload (2CoS)
700
701//`define BSC_OBJ_PTR 80
702//`define BSC_HD1_HI 69
703//`define BSC_HD1_LO 60
704//`define BSC_TL1_HI 59
705//`define BSC_TL1_LO 50
706//`define BSC_CT1_HI 49
707//`define BSC_CT1_LO 40
708//`define BSC_HD0_HI 29
709//`define BSC_HD0_LO 20
710//`define BSC_TL0_HI 19
711//`define BSC_TL0_LO 10
712//`define BSC_CT0_HI 9
713//`define BSC_CT0_LO 0
714
715`define BSC_OBJP_PTR 48
716`define BSC_PYP1_HI 47
717`define BSC_PYP1_LO 42
718`define BSC_HDP1_HI 41
719`define BSC_HDP1_LO 36
720`define BSC_TLP1_HI 35
721`define BSC_TLP1_LO 30
722`define BSC_CTP1_HI 29
723`define BSC_CTP1_LO 24
724`define BSC_PYP0_HI 23
725`define BSC_PYP0_LO 18
726`define BSC_HDP0_HI 17
727`define BSC_HDP0_LO 12
728`define BSC_TLP0_HI 11
729`define BSC_TLP0_LO 6
730`define BSC_CTP0_HI 5
731`define BSC_CTP0_LO 0
732
733`define BSC_PTR_WIDTH 192
734`define BSC_PTR_REQ_HI 191
735`define BSC_PTR_REQ_LO 144
736`define BSC_PTR_REQP_HI 143
737`define BSC_PTR_REQP_LO 96
738`define BSC_PTR_ACK_HI 95
739`define BSC_PTR_ACK_LO 48
740`define BSC_PTR_ACKP_HI 47
741`define BSC_PTR_ACKP_LO 0
742
743`define BSC_PORT_SC_PTR 96 // R, R+P
744`define BSC_PORT_EECU_PTR 48 // A+P
745`define BSC_PORT_EICU_PTR 96 // A, A+P
746`define BSC_PORT_EIPU_PTR 48 // A
747
748// I2C STATES in DRAMctl
749`define I2C_CMD_NOP 4'b0000
750`define I2C_CMD_START 4'b0001
751`define I2C_CMD_STOP 4'b0010
752`define I2C_CMD_WRITE 4'b0100
753`define I2C_CMD_READ 4'b1000
754
755
756//
757// IOB defines
758// ===========
759//
760`define IOB_ADDR_WIDTH 40
761`define IOB_LOCAL_ADDR_WIDTH 32
762
763`define IOB_CPU_INDEX 3
764`define IOB_CPU_WIDTH 8
765`define IOB_THR_INDEX 2
766`define IOB_THR_WIDTH 4
767`define IOB_CPUTHR_INDEX 5
768`define IOB_CPUTHR_WIDTH 32
769
770`define IOB_MONDO_DATA_INDEX 5
771`define IOB_MONDO_DATA_DEPTH 32
772`define IOB_MONDO_DATA_WIDTH 64
773`define IOB_MONDO_SRC_WIDTH 5
774`define IOB_MONDO_BUSY 5
775
776`define IOB_INT_TAB_INDEX 6
777`define IOB_INT_TAB_DEPTH 64
778
779`define IOB_INT_STAT_WIDTH 32
780`define IOB_INT_STAT_HI 31
781`define IOB_INT_STAT_LO 0
782
783`define IOB_INT_VEC_WIDTH 6
784`define IOB_INT_VEC_HI 5
785`define IOB_INT_VEC_LO 0
786
787`define IOB_INT_CPU_WIDTH 5
788`define IOB_INT_CPU_HI 12
789`define IOB_INT_CPU_LO 8
790
791`define IOB_INT_MASK 2
792`define IOB_INT_CLEAR 1
793`define IOB_INT_PEND 0
794
795`define IOB_DISP_TYPE_HI 17
796`define IOB_DISP_TYPE_LO 16
797`define IOB_DISP_THR_HI 12
798`define IOB_DISP_THR_LO 8
799`define IOB_DISP_VEC_HI 5
800`define IOB_DISP_VEC_LO 0
801
802`define IOB_JBI_RESET 1
803`define IOB_ENET_RESET 0
804
805`define IOB_RESET_STAT_WIDTH 3
806`define IOB_RESET_STAT_HI 3
807`define IOB_RESET_STAT_LO 1
808
809`define IOB_SERNUM_WIDTH 64
810
811`define IOB_FUSE_WIDTH 22
812
813`define IOB_TMSTAT_THERM 63
814
815`define IOB_POR_TT 6'b01 // power-on-reset trap type
816
817`define IOB_CPU_BUF_INDEX 4
818
819`define IOB_INT_BUF_INDEX 4
820`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
821
822`define IOB_IO_BUF_INDEX 4
823`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
824
825`define IOB_L2_VIS_BUF_INDEX 5
826`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
827
828`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
829`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
830
831// fixme - double check address mapping
832// CREG in `IOB_INT_CSR space
833`define IOB_DEV_ADDR_MASK 32'hfffffe07
834`define IOB_CREG_INTSTAT 32'h00000000
835`define IOB_CREG_MDATA0 32'h00000400
836`define IOB_CREG_MDATA1 32'h00000500
837`define IOB_CREG_MBUSY 32'h00000900
838`define IOB_THR_ADDR_MASK 32'hffffff07
839`define IOB_CREG_MDATA0_ALIAS 32'h00000600
840`define IOB_CREG_MDATA1_ALIAS 32'h00000700
841`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
842
843// CREG in `IOB_MAN_CSR space
844`define IOB_CREG_INTMAN 32'h00000000
845`define IOB_CREG_INTCTL 32'h00000400
846`define IOB_CREG_INTVECDISP 32'h00000800
847`define IOB_CREG_RESETSTAT 32'h00000810
848`define IOB_CREG_SERNUM 32'h00000820
849`define IOB_CREG_TMSTATCTRL 32'h00000828
850`define IOB_CREG_COREAVAIL 32'h00000830
851`define IOB_CREG_SSYSRESET 32'h00000838
852`define IOB_CREG_FUSESTAT 32'h00000840
853`define IOB_CREG_JINTV 32'h00000a00
854
855`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
856`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
857`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
858`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
859`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
860`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
861`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
862`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
863`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
864`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
865`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
866`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
867`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
868`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
869`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
870`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
871`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
872`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
873`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
874`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
875`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
876`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
877
878`define IOB_CREG_TESTSTUB 32'h80000000
879
880// Address map for TAP access of SPARC ASI
881`define IOB_ASI_PC 4'b0000
882`define IOB_ASI_BIST 4'b0001
883`define IOB_ASI_MARGIN 4'b0010
884`define IOB_ASI_DEFEATURE 4'b0011
885`define IOB_ASI_L1DD 4'b0100
886`define IOB_ASI_L1ID 4'b0101
887`define IOB_ASI_L1DT 4'b0110
888
889`define IOB_INT 2'b00
890`define IOB_RESET 2'b01
891`define IOB_IDLE 2'b10
892`define IOB_RESUME 2'b11
893
894//
895// CIOP UCB Bus Width
896// ==================
897//
898`define IOB_EECU_WIDTH 16 // ethernet egress command
899`define EECU_IOB_WIDTH 16
900
901`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
902`define NRAM_IOB_WIDTH 4
903
904`define IOB_JBI_WIDTH 16 // JBI
905`define JBI_IOB_WIDTH 16
906
907`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
908`define ENET_ING_IOB_WIDTH 8
909
910`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
911`define ENET_EGR_IOB_WIDTH 4
912
913`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
914`define ENET_MAC_IOB_WIDTH 4
915
916`define IOB_DRAM_WIDTH 4 // DRAM controller
917`define DRAM_IOB_WIDTH 4
918
919`define IOB_BSC_WIDTH 4 // BSC
920`define BSC_IOB_WIDTH 4
921
922`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
923`define SPI_IOB_WIDTH 4
924
925`define IOB_CLK_WIDTH 4 // clk unit
926`define CLK_IOB_WIDTH 4
927
928`define IOB_CLSP_WIDTH 4 // clk spine unit
929`define CLSP_IOB_WIDTH 4
930
931`define IOB_TAP_WIDTH 8 // TAP
932`define TAP_IOB_WIDTH 8
933
934
935//
936// CIOP UCB Buf ID Type
937// ====================
938//
939`define UCB_BID_CMP 2'b00
940`define UCB_BID_TAP 2'b01
941
942//
943// Interrupt Device ID
944// ===================
945//
946// Caution: DUMMY_DEV_ID has to be 9 bit wide
947// for fields to line up properly in the IOB.
948`define DUMMY_DEV_ID 9'h10 // 16
949`define UNCOR_ECC_DEV_ID 7'd17 // 17
950
951//
952// Soft Error related definitions
953// ==============================
954//
955`define COR_ECC_CNT_WIDTH 16
956
957
958//
959// CMP clock
960// =========
961//
962
963`define CMP_CLK_PERIOD 1333
964
965
966//
967// NRAM/IO Interface
968// =================
969//
970
971`define DRAM_CLK_PERIOD 6000
972
973`define NRAM_IO_DQ_WIDTH 32
974`define IO_NRAM_DQ_WIDTH 32
975
976`define NRAM_IO_ADDR_WIDTH 15
977`define NRAM_IO_BA_WIDTH 2
978
979
980//
981// NRAM/ENET Interface
982// ===================
983//
984
985`define NRAM_ENET_DATA_WIDTH 64
986`define ENET_NRAM_ADDR_WIDTH 20
987
988`define NRAM_DBG_DATA_WIDTH 40
989
990
991//
992// IO/FCRAM Interface
993// ==================
994//
995
996`define FCRAM_DATA1_HI 63
997`define FCRAM_DATA1_LO 32
998`define FCRAM_DATA0_HI 31
999`define FCRAM_DATA0_LO 0
1000
1001//
1002// PCI Interface
1003// ==================
1004// Load/store size encodings
1005// -------------------------
1006// Size encoding
1007// 000 - byte
1008// 001 - half-word
1009// 010 - word
1010// 011 - double-word
1011// 100 - quad
1012`define LDST_SZ_BYTE 3'b000
1013`define LDST_SZ_HALF_WORD 3'b001
1014`define LDST_SZ_WORD 3'b010
1015`define LDST_SZ_DOUBLE_WORD 3'b011
1016`define LDST_SZ_QUAD 3'b100
1017
1018//
1019// JBI<->SCTAG Interface
1020// =======================
1021// Outbound Header Format
1022`define JBI_BTU_OUT_ADDR_LO 0
1023`define JBI_BTU_OUT_ADDR_HI 42
1024`define JBI_BTU_OUT_RSV0_LO 43
1025`define JBI_BTU_OUT_RSV0_HI 43
1026`define JBI_BTU_OUT_TYPE_LO 44
1027`define JBI_BTU_OUT_TYPE_HI 48
1028`define JBI_BTU_OUT_RSV1_LO 49
1029`define JBI_BTU_OUT_RSV1_HI 51
1030`define JBI_BTU_OUT_REPLACE_LO 52
1031`define JBI_BTU_OUT_REPLACE_HI 56
1032`define JBI_BTU_OUT_RSV2_LO 57
1033`define JBI_BTU_OUT_RSV2_HI 59
1034`define JBI_BTU_OUT_BTU_ID_LO 60
1035`define JBI_BTU_OUT_BTU_ID_HI 71
1036`define JBI_BTU_OUT_DATA_RTN 72
1037`define JBI_BTU_OUT_RSV3_LO 73
1038`define JBI_BTU_OUT_RSV3_HI 75
1039`define JBI_BTU_OUT_CE 76
1040`define JBI_BTU_OUT_RSV4_LO 77
1041`define JBI_BTU_OUT_RSV4_HI 79
1042`define JBI_BTU_OUT_UE 80
1043`define JBI_BTU_OUT_RSV5_LO 81
1044`define JBI_BTU_OUT_RSV5_HI 83
1045`define JBI_BTU_OUT_DRAM 84
1046`define JBI_BTU_OUT_RSV6_LO 85
1047`define JBI_BTU_OUT_RSV6_HI 127
1048
1049// Inbound Header Format
1050`define JBI_SCTAG_IN_ADDR_LO 0
1051`define JBI_SCTAG_IN_ADDR_HI 39
1052`define JBI_SCTAG_IN_SZ_LO 40
1053`define JBI_SCTAG_IN_SZ_HI 42
1054`define JBI_SCTAG_IN_RSV0 43
1055`define JBI_SCTAG_IN_TAG_LO 44
1056`define JBI_SCTAG_IN_TAG_HI 55
1057`define JBI_SCTAG_IN_REQ_LO 56
1058`define JBI_SCTAG_IN_REQ_HI 58
1059`define JBI_SCTAG_IN_POISON 59
1060`define JBI_SCTAG_IN_RSV1_LO 60
1061`define JBI_SCTAG_IN_RSV1_HI 63
1062
1063`define JBI_SCTAG_REQ_WRI 3'b100
1064`define JBI_SCTAG_REQ_WR8 3'b010
1065`define JBI_SCTAG_REQ_RDD 3'b001
1066`define JBI_SCTAG_REQ_WRI_BIT 2
1067`define JBI_SCTAG_REQ_WR8_BIT 1
1068`define JBI_SCTAG_REQ_RDD_BIT 0
1069
1070//
1071// JBI->IOB Mondo Header Format
1072// ============================
1073//
1074`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
1075`define JBI_IOB_MONDO_RSV1_LO 13
1076`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
1077`define JBI_IOB_MONDO_TRG_LO 8
1078`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
1079`define JBI_IOB_MONDO_RSV0_LO 5
1080`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
1081`define JBI_IOB_MONDO_SRC_LO 0
1082
1083`define JBI_IOB_MONDO_RSV1_WIDTH 3
1084`define JBI_IOB_MONDO_TRG_WIDTH 5
1085`define JBI_IOB_MONDO_RSV0_WIDTH 3
1086`define JBI_IOB_MONDO_SRC_WIDTH 5
1087
1088// JBI->IOB Mondo Bus Width/Cycle
1089// ==============================
1090// Cycle 1 Header[15:8]
1091// Cycle 2 Header[ 7:0]
1092// Cycle 3 J_AD[127:120]
1093// Cycle 4 J_AD[119:112]
1094// .....
1095// Cycle 18 J_AD[ 7: 0]
1096`define JBI_IOB_MONDO_BUS_WIDTH 8
1097`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
1098
1099
1100
1101
1102`define IQ_SIZE 8
1103`define OQ_SIZE 12
1104`define TAG_WIDTH 28
1105`define TAG_WIDTH_LESS1 27
1106`define TAG_WIDTHr 28r
1107`define TAG_WIDTHc 28c
1108`define TAG_WIDTH6 22
1109`define TAG_WIDTH6r 22r
1110`define TAG_WIDTH6c 22c
1111
1112
1113`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
1114
1115// BS and SR 11/12/03 N2 Xbar Packet format change
1116
1117`define MBD_ECC_HI 105
1118`define MBD_ECC_HI_PLUS1 106
1119`define MBD_ECC_HI_PLUS5 110
1120`define MBD_ECC_LO 100
1121`define MBD_EVICT 99
1122`define MBD_DEP 98
1123`define MBD_TECC 97
1124`define MBD_ENTRY_HI 96
1125`define MBD_ENTRY_LO 93
1126
1127`define MBD_POISON 92
1128`define MBD_RDMA_HI 91
1129`define MBD_RDMA_LO 90
1130`define MBD_RQ_HI 89
1131`define MBD_RQ_LO 85
1132`define MBD_NC 84
1133`define MBD_RSVD 83
1134`define MBD_CP_HI 82
1135`define MBD_CP_LO 80
1136`define MBD_TH_HI 79
1137`define MBD_TH_LO 77
1138`define MBD_BF_HI 76
1139`define MBD_BF_LO 74
1140`define MBD_WY_HI 73
1141`define MBD_WY_LO 72
1142`define MBD_SZ_HI 71
1143`define MBD_SZ_LO 64
1144`define MBD_DATA_HI 63
1145`define MBD_DATA_LO 0
1146
1147// BS and SR 11/12/03 N2 Xbar Packet format change
1148`define L2_FBF 40
1149`define L2_MBF 39
1150`define L2_SNP 38
1151`define L2_CTRUE 37
1152`define L2_EVICT 36
1153`define L2_DEP 35
1154`define L2_TECC 34
1155`define L2_ENTRY_HI 33
1156`define L2_ENTRY_LO 29
1157
1158`define L2_POISON 28
1159`define L2_RDMA_HI 27
1160`define L2_RDMA_LO 26
1161// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
1162`define L2_RQTYP_HI 25
1163`define L2_RQTYP_LO 21
1164`define L2_NC 20
1165`define L2_RSVD 19
1166`define L2_CPUID_HI 18
1167`define L2_CPUID_LO 16
1168`define L2_TID_HI 15
1169`define L2_TID_LO 13
1170`define L2_BUFID_HI 12
1171`define L2_BUFID_LO 10
1172`define L2_L1WY_HI 9
1173`define L2_L1WY_LO 8
1174`define L2_SZ_HI 7
1175`define L2_SZ_LO 0
1176
1177
1178`define ERR_MEU 63
1179`define ERR_MEC 62
1180`define ERR_RW 61
1181`define ERR_ASYNC 60
1182`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
1183`define ERR_TID_LO 54
1184`define ERR_LDAC 53
1185`define ERR_LDAU 52
1186`define ERR_LDWC 51
1187`define ERR_LDWU 50
1188`define ERR_LDRC 49
1189`define ERR_LDRU 48
1190`define ERR_LDSC 47
1191`define ERR_LDSU 46
1192`define ERR_LTC 45
1193`define ERR_LRU 44
1194`define ERR_LVU 43
1195`define ERR_DAC 42
1196`define ERR_DAU 41
1197`define ERR_DRC 40
1198`define ERR_DRU 39
1199`define ERR_DSC 38
1200`define ERR_DSU 37
1201`define ERR_VEC 36
1202`define ERR_VEU 35
1203`define ERR_LVC 34
1204`define ERR_SYN_HI 31
1205`define ERR_SYN_LO 0
1206
1207
1208
1209`define ERR_MEND 51
1210`define ERR_NDRW 50
1211`define ERR_NDSP 49
1212`define ERR_NDDM 48
1213`define ERR_NDVCID_HI 45
1214`define ERR_NDVCID_LO 40
1215`define ERR_NDADR_HI 39
1216`define ERR_NDADR_LO 4
1217
1218
1219// Phase 2 : SIU Inteface and format change
1220
1221`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
1222`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
1223`define JBI_HDR_SZ4 23
1224`define JBI_HDR_SZc 27c
1225`define JBI_HDR_SZ4c 23c
1226
1227`define JBI_ADDR_LO 0
1228`define JBI_ADDR_HI 7
1229`define JBI_SZ_LO 8
1230`define JBI_SZ_HI 15
1231// `define JBI_RSVD 16 NOt used
1232`define JBI_CTAG_LO 16
1233`define JBI_CTAG_HI 23
1234`define JBI_RQ_RD 24
1235`define JBI_RQ_WR8 25
1236`define JBI_RQ_WR64 26
1237`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
1238`define JBI_OPES_HI 30
1239`define JBI_RQ_POISON 31
1240`define JBI_ENTRY_LO 32
1241`define JBI_ENTRY_HI 33
1242
1243// Phase 2 : SIU Inteface and format change
1244// BS and SR 11/12/03 N2 Xbar Packet format change :
1245`define JBINST_SZ_LO 0
1246`define JBINST_SZ_HI 7
1247// `define JBINST_RSVD 8 NOT used
1248`define JBINST_CTAG_LO 8
1249`define JBINST_CTAG_HI 15
1250`define JBINST_RQ_RD 16
1251`define JBINST_RQ_WR8 17
1252`define JBINST_RQ_WR64 18
1253`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1254`define JBINST_OPES_HI 22
1255`define JBINST_ENTRY_LO 23
1256`define JBINST_ENTRY_HI 24
1257`define JBINST_POISON 25
1258
1259
1260`define ST_REQ_ST 1
1261`define LD_REQ_ST 2
1262`define IDLE 0
1263
1264
1265
1266module l2t (
1267 vnw_ary,
1268 l2t_cpx_req_cq,
1269 l2t_cpx_atom_cq,
1270 l2t_cpx_data_ca,
1271 l2t_pcx_stall_pq,
1272 pcx_l2t_data_rdy_px1,
1273 pcx_l2t_data_px2,
1274 pcx_l2t_atm_px1,
1275 cpx_l2t_grant_cx,
1276 ncu_l2t_pm,
1277 ncu_l2t_ba01,
1278 ncu_l2t_ba23,
1279 ncu_l2t_ba45,
1280 ncu_l2t_ba67,
1281 ncu_spc0_core_enable_status,
1282 ncu_spc1_core_enable_status,
1283 ncu_spc2_core_enable_status,
1284 ncu_spc3_core_enable_status,
1285 ncu_spc4_core_enable_status,
1286 ncu_spc5_core_enable_status,
1287 ncu_spc6_core_enable_status,
1288 ncu_spc7_core_enable_status,
1289 l2d_l2t_decc_c6,
1290 l2t_l2d_way_sel_c2,
1291 l2t_l2d_rd_wr_c2,
1292 l2t_l2d_set_c2,
1293 l2t_l2d_col_offset_c2,
1294 l2t_l2d_word_en_c2,
1295 l2t_l2d_fbrd_c3,
1296 l2t_l2d_fb_hit_c3,
1297 l2t_l2d_stdecc_c2,
1298 l2t_l2b_fbrd_en_c3,
1299 l2t_l2b_fbrd_wl_c3,
1300 l2t_l2b_fbwr_wen_r2,
1301 l2t_l2b_fbwr_wl_r2,
1302 l2t_l2b_fbd_stdatasel_c3,
1303 l2t_l2b_wbwr_wen_c6,
1304 l2t_l2b_wbwr_wl_c6,
1305 l2t_l2b_wbrd_en_r0,
1306 l2t_l2b_wbrd_wl_r0,
1307 l2t_l2b_ev_dword_r0,
1308 l2t_l2b_evict_en_r0,
1309 l2b_l2t_ev_uerr_r5,
1310 l2b_l2t_ev_cerr_r5,
1311 l2t_l2b_rdma_wren_s2,
1312 l2t_l2b_rdma_wrwl_s2,
1313 l2t_l2b_rdma_rdwl_r0,
1314 l2t_l2b_rdma_rden_r0,
1315 l2t_l2b_ctag_en_c7,
1316 l2t_l2b_ctag_c7,
1317 l2t_l2b_word_c7,
1318 l2t_l2b_req_en_c7,
1319 l2t_l2b_word_vld_c7,
1320 l2t_rst_fatal_error,
1321 l2b_l2t_rdma_uerr_c10,
1322 l2b_l2t_rdma_cerr_c10,
1323 l2b_l2t_rdma_notdata_c10,
1324 l2t_mcu_rd_req,
1325 l2t_mcu_rd_dummy_req,
1326 l2t_mcu_rd_req_id,
1327 l2t_mcu_addr,
1328 l2t_mcu_addr_5,
1329 l2t_mcu_wr_req,
1330 mcu_l2t_rd_ack,
1331 mcu_l2t_wr_ack,
1332 mcu_l2t_chunk_id_r0,
1333 mcu_l2t_data_vld_r0,
1334 mcu_l2t_rd_req_id_r0,
1335 mcu_l2t_secc_err_r2,
1336 mcu_l2t_mecc_err_r2,
1337 mcu_l2t_scb_mecc_err,
1338 mcu_l2t_scb_secc_err,
1339 scan_in,
1340 l2t_siu_delay,
1341 sii_l2t_req_vld,
1342 sii_l2t_req,
1343 sii_l2b_ecc,
1344 l2t_sii_iq_dequeue,
1345 l2t_sii_wib_dequeue,
1346 gclk,
1347 rst_por_,
1348 rst_wmr_,
1349 rst_wmr_protect,
1350 tcu_pce_ov,
1351 tcu_clk_stop,
1352 tcu_aclk,
1353 tcu_bclk,
1354 tcu_scan_en,
1355 tcu_muxtest,
1356 tcu_dectest,
1357 ccu_slow_cmp_sync_en,
1358 ccu_cmp_slow_sync_en,
1359 tcu_atpg_mode,
1360 tcu_se_scancollar_in,
1361 tcu_se_scancollar_out,
1362 tcu_array_wr_inhibit,
1363 tcu_array_bypass,
1364 scan_out,
1365 cluster_arst_l,
1366 l2t_dbg_sii_iq_dequeue,
1367 l2t_dbg_sii_wib_dequeue,
1368 l2t_dbg_xbar_vcid,
1369 l2t_dbg_err_event,
1370 l2t_dbg_pa_match,
1371 efu_l2t_fuse_clr,
1372 efu_l2t_fuse_xfer_en,
1373 efu_l2t_fuse_data,
1374 l2t_efu_fuse_data,
1375 l2t_efu_fuse_xfer_en,
1376 tcu_mbist_bisi_en,
1377 tcu_l2t_mbist_start,
1378 tcu_l2t_mbist_scan_in,
1379 tcu_mbist_user_mode,
1380 l2t_tcu_mbist_done,
1381 l2t_tcu_mbist_fail,
1382 l2t_tcu_mbist_scan_out,
1383 l2t_rep_in0,
1384 l2t_rep_in1,
1385 l2t_rep_in2,
1386 l2t_rep_in3,
1387 l2t_rep_in4,
1388 l2t_rep_in5,
1389 l2t_rep_in6,
1390 l2t_rep_in7,
1391 l2t_rep_in8,
1392 l2t_rep_in9,
1393 l2t_rep_in10,
1394 l2t_rep_in11,
1395 l2t_rep_in12,
1396 l2t_rep_in13,
1397 l2t_rep_in14,
1398 l2t_rep_in15,
1399 l2t_rep_in16,
1400 l2t_rep_in17,
1401 l2t_rep_in18,
1402 l2t_rep_in19,
1403 l2t_rep_out0,
1404 l2t_rep_out1,
1405 l2t_rep_out2,
1406 l2t_rep_out3,
1407 l2t_rep_out4,
1408 l2t_rep_out5,
1409 l2t_rep_out6,
1410 l2t_rep_out7,
1411 l2t_rep_out8,
1412 l2t_rep_out9,
1413 l2t_rep_out10,
1414 l2t_rep_out11,
1415 l2t_rep_out12,
1416 l2t_rep_out13,
1417 l2t_rep_out14,
1418 l2t_rep_out15,
1419 l2t_rep_out16,
1420 l2t_rep_out17,
1421 l2t_rep_out18,
1422 l2t_rep_out19,
1423 l2t_lstg_in,
1424 l2t_rstg_in,
1425 l2t_lstg_out,
1426 l2t_rstg_out,
1427 tcu_l2t_shscan_scan_in,
1428 tcu_l2t_shscan_aclk,
1429 tcu_l2t_shscan_bclk,
1430 tcu_l2t_shscan_scan_en,
1431 tcu_l2t_shscan_pce_ov,
1432 tcu_l2t_shscan_clk_stop,
1433 l2t_tcu_shscan_scan_out,
1434 tcu_l2t_coresel,
1435 tcu_l2t_tag_or_data_sel,
1436 l2t_tcu_dmo_out_prev,
1437 l2t_tcu_dmo_out) ;
1438wire array_wr_inhibit;
1439wire l2t_clk_header_scanin;
1440wire l2t_clk_header_scanout;
1441wire aclk;
1442wire bclk;
1443wire ce_ovrd;
1444wire wmr_protect;
1445wire wmr_l;
1446wire aclk_wmr;
1447wire por_l;
1448wire cmp_io_sync_en;
1449wire io_cmp_sync_en;
1450wire vuad_scanin;
1451wire vuad_scanout;
1452wire arbadr_idx_c1c2comp_c1_n;
1453wire arbadr_idx_c1c3comp_c1_n;
1454wire arbadr_idx_c1c4comp_c1_n;
1455wire arbadr_idx_c1c5comp_c1_n;
1456wire [1:0] vlddir_vd_ce_c2;
1457wire vuadpm_scanin;
1458wire vuadpm_scanout;
1459wire usaloc_vlddir_arb_vuad_ce_err_c3_rep1_v1;
1460wire [15:0] tag_hit_way_vld_c3_rep2;
1461wire vlddir_scanin;
1462wire vlddir_scanout;
1463wire [15:0] tagdp_lru_way_sel_c3_rep2;
1464wire tagdp_evict_c3_2_rep1;
1465wire tag_st_to_data_array_c3_rep1;
1466wire usaloc_vlddir_arb_vuad_ce_err_c3_rep1_v2;
1467wire [15:0] tag_hit_way_vld_c3_rep20;
1468wire usaloc_scanin;
1469wire usaloc_scanout;
1470wire [15:0] tagdp_lru_way_sel_c3_rep20;
1471wire tagdp_evict_c3_1_rep1;
1472wire [8:0] tagd_arbdp_tag_idx_px2_buf_1;
1473wire [8:0] tagd_arbdp_tag_idx_px2_buf_2;
1474wire tag_scanin;
1475wire tag_scanout;
1476wire [6:0] l2t_tag_rvalue;
1477wire [3:0] l2t_tag_rid;
1478wire l2t_tag_wr_en;
1479wire l2t_tag_fuse_clr;
1480wire mbist_run;
1481wire [5:0] tag_fuse_read_data;
1482wire [27:0] tag_way12_tag_c2;
1483wire [27:0] tag_way13_tag_c2;
1484wire [27:0] tag_way14_tag_c2;
1485wire [27:0] tag_way15_tag_c2;
1486wire tagl_1_scanin;
1487wire tagl_1_scanout;
1488wire tagl_2_scanin;
1489wire tagl_2_scanout;
1490wire tagdp_evict_c3_1;
1491wire tagdp_evict_c3_2;
1492wire [15:0] tag_way_sel_c2_buff;
1493wire tagctl_arb_vuad_ce_err_c3;
1494wire arb_pf_ice_inst_c2;
1495wire [15:0] vlddir_vuad_valid_c2_rep1;
1496wire [3:0] arbdp_diag_wr_way_c2;
1497wire tagdp_scanin;
1498wire tagdp_scanout;
1499wire [27:0] tagd_evict_tag_c3;
1500wire [27:0] tagd_dmo_evict_tag_c4;
1501wire arbadr_tagd_2bnk_true_enbld_dist;
1502wire arbadr_tagd_4bnk_true_enbld_dist;
1503wire arbadr_tagd_ncu_l2t_pm_n_dist;
1504wire tagd_scanin;
1505wire tagd_scanout;
1506wire [38:0] l2t_tcu_dmo_out_unbuff;
1507wire [38:0] l2t_tcu_dmo_out_prev_buff;
1508wire dmologic_scanin;
1509wire dmologic_scanout;
1510wire tcu_l2t_shscan_clk_stop_d2;
1511wire mbist_start_mb0;
1512wire mbist_start_mb2;
1513wire l2t_tcu_mbist0_done;
1514wire l2t_tcu_mbist2_done;
1515wire l2t_tcu_mbist0_fail;
1516wire l2t_tcu_mbist2_fail;
1517wire [7:0] mbist_write_data_decck;
1518wire tcu_l2t_mbist_scan_in1;
1519wire [27:0] mbist_tag_lkup_addr;
1520wire tagctl_scanin;
1521wire tagctl_scanin_1;
1522wire misbuf_tag_hit_unqual_c2_rep2;
1523wire arb_inst_vld_c2_prev;
1524wire [1:0] filbuf_dis_nderr_c3;
1525wire misbuf_arb_hit_c3;
1526wire filbuf_match_c3;
1527wire misbuf_tag_hit_unqual_c2_rep1;
1528wire misbuf_notdata_err_c2_rep1;
1529wire filbuf_tag_tag_hit_frm_mb_c2_rep;
1530wire [3:0] filbuf_tag_evict_way_c3_rep1;
1531wire filbuf_dis_cerr_c3_rep1;
1532wire filbuf_dis_uerr_c3_rep1;
1533wire tagctl_scanout;
1534wire l2t_mb2_mbdata_wr_en;
1535wire l2t_mb2_mbdata_rd_en;
1536wire l2t_mb2_mbtag_rd_en;
1537wire l2t_mb2_mbtag_wr_en;
1538wire [4:0] l2t_mb2_addr;
1539wire arb_vuad_ce_err_c2;
1540wire misbuf_vuad_ce_instr_c2;
1541wire mb_mbist_cam_hit;
1542wire [3:0] mbist_cam_sel;
1543wire misbuf_vuad_ce_err_c8;
1544wire misbuf_notdata_err_c2;
1545wire misbuf_vuad_ce_err_c6;
1546wire arbdec_arbdp_inst_bufidhi_c8;
1547wire deccck_notdata_err_c8;
1548wire tag_miss_unqual_c2_rep1;
1549wire tag_misbuf_rdma_reg_vld_c2_rep1a;
1550wire arb_pf_ice_inst_c7;
1551wire arbadr_misbuf_idx_c1c2comp_c1;
1552wire arbadr_misbuf_idx_c1c3comp_c1;
1553wire filbuf_misbuf_tag_hit_frm_mb_c2;
1554wire misbuf_scanin;
1555wire misbuf_scanout;
1556wire [127:64] mbdata_din;
1557wire mbdata_scanin;
1558wire mbdata_scanout;
1559wire [41:7] arbadr_mbcam_addr_px2_buff;
1560wire mbtag_scanin;
1561wire mbtag_scanout;
1562wire l2t_mb2_fbtag_wr_en;
1563wire l2t_mb2_fbtag_rd_en;
1564wire fb_mbist_cam_hit;
1565wire [110:83] mb_data_read_data_rep;
1566wire filbuf_arb_tag_hit_frm_mb_c2;
1567wire rdmat_rdmard_notdata_c12;
1568wire tag_misbuf_rdma_reg_vld_c2_rep1b;
1569wire deccck_bscd_notdata_err_c8;
1570wire arb_fill_vld_c2_rep1;
1571wire tag_rdma_gate_off_c2_rep1;
1572wire filbuf_scanin;
1573wire filbuf_scanout;
1574wire [7:0] fb_match_idx_unused;
1575wire [39:0] fbtag_din;
1576wire arb_inst_vld_c1_v1;
1577wire fbtag_scanin;
1578wire fbtag_scanout;
1579wire [3:0] mbdata_cmp_sel;
1580wire [7:0] l2t_mb2_wdata;
1581wire arb_arbdat_mux2_snpsel_px2;
1582wire arb_arbdat_mux3_bufsel_px2;
1583wire arb_arbdat_mux4_c1sel_px2;
1584wire arbdat_scanin;
1585wire arbdat_scanout;
1586wire l2t_mb2_run;
1587wire [33:2] arbadr_csr_debug_addr;
1588wire arbadr_dirvec_2bnk_true_enbld_dist;
1589wire arbadr_dirvec_4bnk_true_enbld_dist;
1590wire arbadr_dirvec_ncu_l2t_pm_n_dist;
1591wire arbadr_evctag_2bnk_true_enbld_dist;
1592wire arbadr_evctag_4bnk_true_enbld_dist;
1593wire arbadr_evctag_ncu_l2t_pm_n_dist;
1594wire arbadr_arbctl_2bnk_true_enbld_dist;
1595wire arbadr_arbctl_4bnk_true_enbld_dist;
1596wire arbadr_arbctl_ncu_l2t_pm_n_dist;
1597wire [39:4] arbdp_csr_addr_c9;
1598wire mb2_l2t_wk1_cam_init;
1599wire mb2_l2t_wk1_cam_shift;
1600wire arb_arbadr_mux2_snpsel_px2;
1601wire arb_mux3_bufsel_px1;
1602wire arb_arbadr_mux4_c1sel_px2;
1603wire arbadr_scanin;
1604wire arbadr_scanout;
1605wire arb_dc_ic_rd_bit_4;
1606wire arb_arbdec_mux2_snpsel_px2;
1607wire arb_arbdec_mux3_bufsel_px2;
1608wire arb_arbdec_mux4_c1sel_px2;
1609wire arb_dc_evict_c4;
1610wire arb_ic_evict_c4;
1611wire arb_inval_inst_vld_c3;
1612wire ique_arb_pf_ice_px2;
1613wire filbuf_arb_tag_hit_frm_mb_c2_rep;
1614wire usaloc_vlddir_arb_vuad_ce_err_c3;
1615wire l2t_mb2_mbtag_lookup_en;
1616wire l2t_mb2_fbtag_lookup_en;
1617wire l2t_mb2_wbtag_lookup_en;
1618wire l2t_mb2_rdmatag_lookup_en;
1619wire arbdec_arbdp_inst_rsvd_c1_1;
1620wire arb_scanin;
1621wire arb_scanout;
1622wire [5:0] l2t_dbg_xbar_vcid_transfer;
1623wire arbdec_scanin;
1624wire arbdec_scanout_1;
1625wire arbdec_scanout;
1626wire l2t_mb2_rdmatag_rd_en;
1627wire l2t_mb2_wbtag_wr_en;
1628wire l2t_mb2_wbtag_rd_en;
1629wire wb_mbist_cam_hit;
1630wire wbuf_scanin;
1631wire wbuf_scanout;
1632wire [7:0] wb_match_idx_unused;
1633wire arb_inst_vld_c1_v2;
1634wire wbtag_scanin;
1635wire wbtag_scanout;
1636wire iqu_fail_reg;
1637wire ique_pcx_l2t_data_103_px2;
1638wire ique_scanin;
1639wire ique_scanout;
1640wire iqu_hold_rd_n;
1641wire l2t_mb2_iqarray_wr_en;
1642wire l2t_mb2_iqarray_rd_en;
1643wire iqu_scanin;
1644wire iqu_scanout;
1645wire [129:0] pcx_l2t_data_px2_fnl;
1646wire iqarray_scanin;
1647wire iqarray_scanout;
1648wire [3:0] dirrep_dc_lkup_row_dec_c4;
1649wire [5:0] l2t_mb0_addr;
1650wire oqu_scanin;
1651wire oqu_scanout;
1652wire oqarray_scanin;
1653wire oqarray_scanout;
1654wire [7:0] mb0_l2t_mbist_write_data;
1655wire l2t_mb0_run;
1656wire oqarray_rw_fail;
1657wire [3:0] mbist_oqarray_sel;
1658wire csr_report_ldrc;
1659wire [127:0] decc_ret_data_c7;
1660wire [5:4] arbadr_arbdp_line_addr_c7;
1661wire oque_scanin;
1662wire oque_scanout;
1663wire [1:0] ic_cam_fail;
1664wire [1:0] dc_cam_fail;
1665wire mb0_l2t_cambist;
1666wire dirvec_scanin;
1667wire dirvec_scanout;
1668wire [3:0] deccck_muxsel_diag_out_c7;
1669wire deccck_spcd_notdata_err_c8;
1670wire deccck_scanin;
1671wire deccck_scanout;
1672wire decc_scanin;
1673wire decc_scanout;
1674wire [63:0] shadow_error_status_reg;
1675wire [51:4] shadow_notdata_reg;
1676wire [39:4] shadow_l2erraddr_reg;
1677wire csreg_l2_cmpr_reg_wr_en_c8;
1678wire csreg_l2_mask_reg_wr_en_c8;
1679wire csr_error_status_notdata;
1680wire csreg_notdata_error_rw_en;
1681wire csreg_csr_notdata_wr_en_c8;
1682wire csreg_wr_enable_notdata_vcid_c9;
1683wire csreg_csr_notdata_vcid_wr_en;
1684wire csreg_notdata_err_state_in_rw;
1685wire csreg_notdata_err_state_in_mend;
1686wire [49:48] csreg_notdata_err_state_in;
1687wire csreg_notdata_diag_wr_en;
1688wire csreg_csr_notdata_addr_wr_en;
1689wire csr_scanin;
1690wire csr_scanout;
1691wire [1:0] csreg_csr_rd_mux4_sel_c7;
1692wire [1:0] csreg_csr_rd_mux_fnl_c7;
1693wire csreg_scanin;
1694wire csreg_scanout;
1695wire l2t_dbg_sii_iq_dequeue_unreg;
1696wire snp_scanin;
1697wire snp_scanout;
1698wire snpd_scanin;
1699wire snpd_scanout;
1700wire [6:0] arbdec_snpd_ecc_c8;
1701wire cam_mb2_rw_fail;
1702wire evctag_scanin;
1703wire evctag_scanout;
1704wire [7:0] rd_match_idx_unused;
1705wire arb_inst_vld_c1_v3;
1706wire rdmatag_scanin;
1707wire rdmatag_scanout;
1708wire rdmarpt_scanout;
1709wire rdma_mbist_cam_hit;
1710wire rdmat_scanout;
1711wire dirrep_dir_wr_par_c4;
1712wire arbadr_arbdp_addr4_c4;
1713wire arbadr_arbdp_dc_addr4_c4;
1714wire arbadr_arbdp_ic_addr4_c4;
1715wire arbadr_arbdp_index_ic_addr4_c4;
1716wire arbadr_arbdp_index_dc_addr4_c4;
1717wire dirrep_scanin;
1718wire dirrep_scanout;
1719wire [3:0] subarray_0_unused;
1720wire subarray_0_scanin;
1721wire subarray_0_scanout;
1722wire [3:0] subarray_1_unused;
1723wire subarray_1_scanin;
1724wire subarray_1_scanout;
1725wire [3:0] subarray_2_unused;
1726wire subarray_2_scanin;
1727wire subarray_2_scanout;
1728wire [3:0] subarray_3_unused;
1729wire subarray_3_scanin;
1730wire subarray_3_scanout;
1731wire [3:0] subarray_8_unused;
1732wire subarray_8_scanin;
1733wire subarray_8_scanout;
1734wire [3:0] subarray_9_unused;
1735wire subarray_9_scanin;
1736wire subarray_9_scanout;
1737wire [3:0] subarray_10_unused;
1738wire subarray_10_scanin;
1739wire subarray_10_scanout;
1740wire [3:0] subarray_11_unused;
1741wire subarray_11_scanin;
1742wire subarray_11_scanout;
1743wire ic_row0_scanin;
1744wire ic_row0_scanout;
1745wire ic_force_hit_row0_c4;
1746wire out_col0_scanin;
1747wire out_col0_scanout;
1748wire [2:0] out_col0_dirout_parity_vld_out_unused;
1749wire [1:0] l2t_mb0_icrow_row_en;
1750wire [15:0] l2t_mb0_lookup_wdata;
1751wire [3:0] ic_cam_read_fail;
1752wire ic_row0_select_panel0;
1753wire ic_row1_select_panel0;
1754wire out_col1_scanin;
1755wire out_col1_scanout;
1756wire [2:0] out_col1_dirout_parity_vld_out_unused;
1757wire ic_row0_select_panel1;
1758wire ic_row1_select_panel1;
1759wire out_col2_scanin;
1760wire out_col2_scanout;
1761wire [2:0] out_col2_dirout_parity_vld_out_unused;
1762wire [15:0] ic_rd_dataae_row1;
1763wire ic_row0_select_panel2;
1764wire ic_row1_select_panel2;
1765wire out_col3_scanin;
1766wire out_col3_scanout;
1767wire [15:0] ic_rd_databf_row1;
1768wire ic_row0_select_panel3;
1769wire ic_row1_select_panel3;
1770wire ic_row2_scanin;
1771wire ic_row2_scanout;
1772wire ic_force_hit_row2_c4;
1773wire dc_row0_scanin;
1774wire dc_row0_scanout;
1775wire dc_force_hit_row0_c4;
1776wire dc_out_col0_scanin;
1777wire dc_out_col0_scanout;
1778wire [2:0] dc_out_col0parity_vld_out_unused;
1779wire [1:0] l2t_mb0_dcrow_row_en;
1780wire [3:0] dc_cam_read_fail;
1781wire dc_row0_select_panel0;
1782wire dc_row1_select_panel0;
1783wire dc_out_col1_scanin;
1784wire dc_out_col1_scanout;
1785wire [2:0] dc_out_col1parity_vld_out_unused;
1786wire dc_row0_select_panel1;
1787wire dc_row1_select_panel1;
1788wire dc_out_col2_scanin;
1789wire dc_out_col2_scanout;
1790wire [2:0] dc_out_col2parity_vld_out_unused;
1791wire dc_row0_select_panel2;
1792wire dc_row1_select_panel2;
1793wire dc_out_col3_scanin;
1794wire dc_out_col3_scanout;
1795wire dc_row0_select_panel3;
1796wire dc_row1_select_panel3;
1797wire ic_row0_ctl_scanin;
1798wire ic_row0_ctl_scanout;
1799wire [7:0] l2t_mb0_mask;
1800wire [3:0] l2t_mb0_icrow_panel_en;
1801wire [3:0] l2t_mb0_icrow_lookup_en;
1802wire l2t_mb0_icrow_wr_en;
1803wire l2t_mb0_icrow_rd_en;
1804wire [17:9] tagd_lkup_ic_addr_c4;
1805wire ic_row2_ctl_scanin;
1806wire ic_row2_ctl_scanout;
1807wire dc_row0_ctl_scanin;
1808wire dc_row0_ctl_scanout;
1809wire [3:0] l2t_mb0_dcrow_panel_en;
1810wire [3:0] l2t_mb0_dcrow_lookup_en;
1811wire l2t_mb0_dcrow_wr_en;
1812wire l2t_mb0_dcrow_rd_en;
1813wire [17:9] tagd_lkup_dc_addr_c4;
1814wire dc_row2_ctl_scanin;
1815wire dc_row2_ctl_scanout;
1816wire dc_force_hit_row2_c4;
1817wire dc_row2_scanin;
1818wire dc_row2_scanout;
1819wire left_ffrptr_scanin;
1820wire left_ffrptr_scanout;
1821wire right_ffrptr_scanin;
1822wire right_ffrptr_scanout;
1823wire [12:0] mrep_besides_tagl0_unused;
1824wire [15:0] mrep_besides_tagl1_unused;
1825wire [15:0] mrep_besides_tagl2_unused;
1826wire [15:0] mrep_besides_tagl3_unused;
1827wire [15:0] mrep_besides_tagl4_unused;
1828wire [15:0] mrep_besides_tagl5_unused;
1829wire [15:0] mrep_besides_tagl6_unused;
1830wire [7:0] mrep_besides_mbdata1_unused;
1831wire [7:0] mrep_besides_mbdata2_unused;
1832wire [7:0] mrep_besides_mbdata3_unused;
1833wire [7:0] mrep_besides_mbdata4_unused;
1834wire [7:0] mrep_besides_mbdata5_unused;
1835wire [7:0] mrep_besides_mbdata6_unused;
1836wire [7:0] mrep_besides_mbdata7_unused;
1837wire [5:0] mrep_besides_mbdata15_unused;
1838wire [15:0] tagdp_lru_way_sel_c3_rep1;
1839wire [15:0] tag_hit_way_vld_c3_rep1;
1840wire [31:0] mrep_arbdat_top1_unused;
1841wire [31:0] mrep_arbdat_top2_unused;
1842wire [31:0] mrep_arbdat_top3_unused;
1843wire [31:0] mrep_arbdat_bot0_unused;
1844wire [31:0] mrep_arbdat_bot1_unused;
1845wire [19:0] mrep_arbdec_top_1_unused;
1846wire [31:0] mrep_arbdec_top1_unused;
1847wire [31:0] mrep_arbdec_top2_unused;
1848wire mrep_besides_arbadr_out0_unused;
1849wire mrep_besides_arbadr_unused;
1850wire [1:0] mrep_besides_arbadr11_unused;
1851wire [1:0] mrep_besides_arbadr12_unused;
1852wire [1:0] mrep_besides_arbadr13_unused;
1853wire [1:0] mrep_besides_arbadr14_unused;
1854wire [1:0] mrep_besides_arbadr15_unused;
1855wire [1:0] mrep_besides_arbadr16_unused;
1856wire [1:0] mrep_besides_arbadr17_unused;
1857wire [1:0] mrep_besides_arbadr18_unused;
1858wire [1:0] mrep_besides_arbadr19_unused;
1859wire [1:0] mrep_besides_arbadr20_unused;
1860wire [1:0] mrep_besides_arbadr21_unused;
1861wire [1:0] mrep_besides_arbadr22_unused;
1862wire [1:0] mrep_besides_arbadr23_unused;
1863wire [1:0] mrep_besides_arbadr24_unused;
1864wire [1:0] mrep_besides_arbadr25_unused;
1865wire [1:0] mrep_besides_arbadr26_unused;
1866wire [1:0] mrep_besides_arbadr27_unused;
1867wire [1:0] mrep_besides_arbadr28_unused;
1868wire [1:0] mrep_besides_arbadr29_unused;
1869wire [1:0] mrep_besides_arbadr30_unused;
1870wire [1:0] mrep_besides_arbadr31_unused;
1871wire [1:0] mrep_besides_arbadr32_unused;
1872wire [1:0] mrep_besides_arbadr33_unused;
1873wire [1:0] mrep_besides_arbadr34_unused;
1874wire [1:0] mrep_besides_arbadr35_unused;
1875wire [1:0] mrep_besides_arbadr36_unused;
1876wire [1:0] mrep_besides_arbadr37_unused;
1877wire [1:0] mrep_besides_arbadr38_unused;
1878wire [1:0] mrep_besides_arbadr39_unused;
1879wire [1:0] mrep_besides_arbadr40_unused;
1880wire [1:0] mrep_besides_arbadr41_unused;
1881wire [1:0] mrep_besides_arbadr42_unused;
1882wire [1:0] mrep_besides_arbadr43_unused;
1883wire [1:0] mrep_besides_arbadr44_unused;
1884wire [1:0] mrep_besides_arbadr45_unused;
1885wire [1:0] mrep_besides_arbadr46_unused;
1886wire [1:0] mrep_besides_arbadr47_unused;
1887wire [1:0] mrep_besides_arbadr48_unused;
1888wire [1:0] mrep_besides_arbadr49_unused;
1889wire [1:0] mrep_besides_arbadr50_unused;
1890wire [1:0] mrep_besides_arbadr51_unused;
1891wire [1:0] mrep_besides_arbadr52_unused;
1892wire [1:0] mrep_besides_arbadr53_unused;
1893wire [1:0] mrep_besides_arbadr54_unused;
1894wire [1:0] mrep_besides_arbadr55_unused;
1895wire [1:0] mrep_besides_arbadr56_unused;
1896wire [1:0] mrep_besides_arbadr57_unused;
1897wire [1:0] mrep_besides_arbadr58_unused;
1898wire [1:0] mrep_besides_arbadr59_unused;
1899wire [1:0] mrep_besides_arbadr60_unused;
1900wire [1:0] mrep_besides_arbadr61_unused;
1901wire [1:0] mrep_besides_arbadr62_unused;
1902wire [1:0] mrep_besides_arbadr63_unused;
1903wire [1:0] mrep_besides_arbadr64_unused;
1904wire [2:0] mrep_for_dir0_unused;
1905wire [2:0] mrep_for_dir3_unused;
1906wire l2t_mb2_rdmatag_wr_en;
1907wire mbdata_fail;
1908wire tcu_l2t_mbist_scan_in2;
1909wire l2t_mb0_oqarray_wr_en;
1910wire l2t_mb0_oqarray_rd_en;
1911wire l2tag_sram_hdr_scanin;
1912wire l2tag_sram_hdr_scanout;
1913wire rdmat_scanin;
1914wire vuad_usaloc_mux_used_and_alloc_comb_sel0;
1915wire vuad_usaloc_mux_used_and_alloc_comb_sel1;
1916wire vuad_usaloc_mux_used_and_alloc_comb_sel2;
1917wire vuad_usaloc_mux_used_and_alloc_comb_sel3;
1918wire vuad_usaloc_mux_used_and_alloc_comb_sel4;
1919wire vuad_usaloc_mux_used_and_alloc_comb_sel5;
1920wire mux_valid_dirty_c1_sel0;
1921wire mux_valid_dirty_c1_sel1;
1922wire mux_valid_dirty_c1_sel2;
1923wire [38:0] mbist_dmo_data_out;
1924wire arb_l2drpt_waysel_gate_c1;
1925wire [15:0] tagctl_l2drpt_mux4_way_sel_c1;
1926wire tag_data_array_wr_active_c1;
1927wire tag_hit_unqual_c3;
1928wire misbuf_uncorr_err_c1;
1929wire misbuf_notdata_err_c1;
1930wire tag_misbuf_int_ack_c3;
1931wire [3:0] dec_col_offset_prev_c1;
1932wire decdp_cas2_from_mb_ctrue_c1;
1933wire misbuf_vuad_ce_instr_ack_c2;
1934wire arb_arbdp_dword_st_c1;
1935wire arbdec_pf_ice_inst_c1;
1936wire filbuf_misbuf_ue_offmode_c7;
1937wire filbuf_misbuf_ce_offmode_c7;
1938wire arb_misbuf_inval_inst_c2;
1939wire mbdata_fail_bot;
1940wire mbist_lookupen;
1941wire iqu_iq_arb_vld_px2_v1;
1942wire arb_iqsel_px2_v1;
1943wire arb_snp_snpsel_px2;
1944wire [4:0] arbdec_csr_ttype_c6;
1945wire [5:0] arbdec_csr_vcid_c6;
1946wire wbuf_wbufrpt_leave_state0;
1947wire wbuf_wbufrpt_next_state_1;
1948wire cycle_count_less_than_7_din;
1949wire mcu_l2t_wr_ack_d1;
1950wire [2:0] rtn_err_field_c7;
1951wire [3:0] deccdp_decck_uncorr_err_c7;
1952wire [3:0] deccdp_decck_corr_err_c7;
1953wire csreg_report_ldrc_inpkt;
1954wire notdata_higher_priority_err;
1955wire csreg_wr_enable_notdata_nddm_vcid_c9;
1956wire set_async_c9;
1957wire error_rw_en;
1958wire diag_wr_en;
1959
1960
1961input vnw_ary; // 2.0
1962//////////////////////////////////////////////////////////////////////////////
1963// CCX interface
1964//////////////////////////////////////////////////////////////////////////////
1965
1966output [7:0] l2t_cpx_req_cq; // l2t to processor request //
1967output l2t_cpx_atom_cq; //
1968output [`CPX_WIDTH_LESS1:0] l2t_cpx_data_ca; // l2t to cpx data pkt //
1969output l2t_pcx_stall_pq; // l2t to pcx IQ_full stall //
1970
1971input pcx_l2t_data_rdy_px1; //
1972input [`PCX_WIDTH_LESS1:0] pcx_l2t_data_px2; //
1973input pcx_l2t_atm_px1; //
1974input [7:0] cpx_l2t_grant_cx; //
1975
1976//////////////////////////////////////////////////////////////////////////////
1977// NCU interface : BS 03/25/04 for partial bank/core modes support
1978//////////////////////////////////////////////////////////////////////////////
1979
1980input ncu_l2t_pm; // 0:all 8 banks available, 1:partial mode
1981 //and need to look at each *ba* signals)
1982input ncu_l2t_ba01; // 0:bank0 and bank1 unavailable, 1:both banks available
1983input ncu_l2t_ba23; // 0:bank2 and bank3 unavailable, 1:both banks available
1984input ncu_l2t_ba45; // 0:bank4 and bank5 unavailable, 1:both banks available
1985input ncu_l2t_ba67; // 0:bank6 and bank7 unavailable, 1:both banks available
1986
1987input ncu_spc0_core_enable_status; // 0 : spc0 unavailable, 1 : available
1988input ncu_spc1_core_enable_status; // 0 : spc1 unavailable, 1 : available
1989input ncu_spc2_core_enable_status; // 0 : spc2 unavailable, 1 : available
1990input ncu_spc3_core_enable_status; // 0 : spc3 unavailable, 1 : available
1991input ncu_spc4_core_enable_status; // 0 : spc4 unavailable, 1 : available
1992input ncu_spc5_core_enable_status; // 0 : spc5 unavailable, 1 : available
1993input ncu_spc6_core_enable_status; // 0 : spc6 unavailable, 1 : available
1994input ncu_spc7_core_enable_status; // 0 : spc7 unavailable, 1 : available
1995
1996
1997
1998//////////////////////////////////////////////////////////////////////////////
1999// Interface with l2d
2000//////////////////////////////////////////////////////////////////////////////
2001
2002input [155:0] l2d_l2t_decc_c6; // From data of l2d_data.v //
2003
2004output [15:0] l2t_l2d_way_sel_c2; //
2005output l2t_l2d_rd_wr_c2; //
2006output [8:0] l2t_l2d_set_c2; //
2007output [3:0] l2t_l2d_col_offset_c2; //
2008output [15:0] l2t_l2d_word_en_c2; //
2009output l2t_l2d_fbrd_c3; // From arb of l2t_arb_ctl.sv //
2010output l2t_l2d_fb_hit_c3; // bypass data from Fb //
2011output [77:0] l2t_l2d_stdecc_c2;// store data. //
2012
2013
2014//////////////////////////////////////////////////////////////////////////////
2015// Interface with l2b
2016//////////////////////////////////////////////////////////////////////////////
2017
2018//output [77:0] l2t_l2b_stdecc_c3;// store data. staged version to l2b //
2019output l2t_l2b_fbrd_en_c3; // rd en for a fill operation or fb bypass //
2020output [2:0] l2t_l2b_fbrd_wl_c3 ; // read entry //
2021output [15:0] l2t_l2b_fbwr_wen_r2 ; // mcu Fill or store in OFF mode. //
2022output [2:0] l2t_l2b_fbwr_wl_r2 ; // mcu Fill entry. //
2023output l2t_l2b_fbd_stdatasel_c3; // select store data in OFF mode //
2024
2025output [3:0] l2t_l2b_wbwr_wen_c6; // write en //
2026output [2:0] l2t_l2b_wbwr_wl_c6; // from wbuf //
2027output l2t_l2b_wbrd_en_r0; // triggerred by a wr_ack from mcu //
2028output [2:0] l2t_l2b_wbrd_wl_r0; //
2029
2030output [2:0] l2t_l2b_ev_dword_r0; //
2031output l2t_l2b_evict_en_r0;// From wbuf of l2t_wbuf_ctl.sv //
2032input l2b_l2t_ev_uerr_r5; //
2033input l2b_l2t_ev_cerr_r5; //
2034
2035// START interface with l2b for handling rdma reads and writes
2036
2037output [15:0] l2t_l2b_rdma_wren_s2; // may be all 1s //
2038output [1:0] l2t_l2b_rdma_wrwl_s2; //
2039output [1:0] l2t_l2b_rdma_rdwl_r0; //
2040output l2t_l2b_rdma_rden_r0; //
2041
2042output l2t_l2b_ctag_en_c7 ; //
2043output [31:0] l2t_l2b_ctag_c7 ; //
2044
2045// RAS implementation changes 10/14/04
2046output [3:0] l2t_l2b_word_c7 ; // //
2047output l2t_l2b_req_en_c7 ; // This signal is s one cycle pulse //
2048output l2t_l2b_word_vld_c7; // This signal is high for 16 signals. //
2049output l2t_rst_fatal_error; // Fatal error to rst block on LVU and LRU
2050
2051input l2b_l2t_rdma_uerr_c10; //
2052input l2b_l2t_rdma_cerr_c10; //
2053input l2b_l2t_rdma_notdata_c10; //
2054
2055//////////////////////////////////////////////////////////////////////////////
2056// Interface with the MCU
2057//////////////////////////////////////////////////////////////////////////////
2058
2059
2060output l2t_mcu_rd_req; //
2061output l2t_mcu_rd_dummy_req; //
2062output [2:0] l2t_mcu_rd_req_id; //
2063output [39:7] l2t_mcu_addr; //
2064output l2t_mcu_addr_5;//
2065output l2t_mcu_wr_req; //
2066
2067input mcu_l2t_rd_ack; //
2068input mcu_l2t_wr_ack; //
2069input [1:0] mcu_l2t_chunk_id_r0; //
2070input mcu_l2t_data_vld_r0; //
2071input [2:0] mcu_l2t_rd_req_id_r0; //
2072input mcu_l2t_secc_err_r2 ; //
2073input mcu_l2t_mecc_err_r2 ; //
2074input mcu_l2t_scb_mecc_err; //
2075input mcu_l2t_scb_secc_err; //
2076input scan_in; //
2077
2078
2079//////////////////////////////////////////////////////////////////////////////
2080// Snoop / RDMA interface.
2081//////////////////////////////////////////////////////////////////////////////
2082
2083input l2t_siu_delay;
2084input sii_l2t_req_vld ; //
2085input [31:0] sii_l2t_req; //
2086input [ 6:0] sii_l2b_ecc; // RAS implementation 10/14/04
2087output l2t_sii_iq_dequeue; //
2088output l2t_sii_wib_dequeue; //
2089
2090
2091
2092//////////////////////////////////////////////////////////////////////////////
2093// Global IOs
2094//////////////////////////////////////////////////////////////////////////////
2095input gclk; // clock from global distribution
2096input rst_por_; // power-on, from RST
2097input rst_wmr_; // warm-reset, from RST
2098input rst_wmr_protect; // warm-reset, from RST
2099input tcu_pce_ov; // clock enable overide, from TCU
2100input tcu_clk_stop; // clock stop, from TCU
2101input tcu_aclk; // aclk, from TCU
2102input tcu_bclk; // bclk, from TCU
2103input tcu_scan_en; // Scan EN, from TCU
2104input tcu_muxtest; // for pass muxes, from TCU
2105input tcu_dectest; // for pass muxes, from TCU
2106input ccu_slow_cmp_sync_en;
2107input ccu_cmp_slow_sync_en;
2108
2109input tcu_atpg_mode;
2110input tcu_se_scancollar_in;
2111input tcu_se_scancollar_out;
2112input tcu_array_wr_inhibit;
2113input tcu_array_bypass;
2114output scan_out; //scan chain output //
2115
2116input cluster_arst_l;
2117
2118//////////////////////////////////////////////////////////////////////////////
2119// DEBUG ports
2120//////////////////////////////////////////////////////////////////////////////
2121
2122output l2t_dbg_sii_iq_dequeue;
2123output l2t_dbg_sii_wib_dequeue;
2124output [5:0] l2t_dbg_xbar_vcid;
2125output l2t_dbg_err_event;
2126output l2t_dbg_pa_match;
2127
2128//////////////////////////////////////////////////////////////////////////////
2129// Efuse interface signals
2130//////////////////////////////////////////////////////////////////////////////
2131input efu_l2t_fuse_clr;
2132input efu_l2t_fuse_xfer_en;
2133input efu_l2t_fuse_data;
2134output l2t_efu_fuse_data;
2135output l2t_efu_fuse_xfer_en;
2136/////////////////////////////////////////////////////////////////////////////////
2137// MBIST related pins
2138//////////////////////////////////////////////////////////////////////////////
2139input tcu_mbist_bisi_en;
2140input tcu_l2t_mbist_start;
2141input tcu_l2t_mbist_scan_in;
2142input tcu_mbist_user_mode;
2143
2144output l2t_tcu_mbist_done;
2145output l2t_tcu_mbist_fail;
2146output l2t_tcu_mbist_scan_out;
2147
2148/////////////////////////////////////////////////////////////////////////////////
2149// Repeaters
2150/////////////////////////////////////////////////////////////////////////////////
2151
2152input [23:0] l2t_rep_in0;
2153input [23:0] l2t_rep_in1;
2154input [23:0] l2t_rep_in2;
2155input [23:0] l2t_rep_in3;
2156input [23:0] l2t_rep_in4;
2157input [23:0] l2t_rep_in5;
2158input [23:0] l2t_rep_in6;
2159input [23:0] l2t_rep_in7;
2160input [23:0] l2t_rep_in8;
2161input [23:0] l2t_rep_in9;
2162input [23:0] l2t_rep_in10;
2163input [23:0] l2t_rep_in11;
2164input [23:0] l2t_rep_in12;
2165input [23:0] l2t_rep_in13;
2166input [23:0] l2t_rep_in14;
2167input [23:0] l2t_rep_in15;
2168input [23:0] l2t_rep_in16;
2169input [23:0] l2t_rep_in17;
2170input [23:0] l2t_rep_in18;
2171input [23:0] l2t_rep_in19;
2172
2173output [23:0] l2t_rep_out0;
2174output [23:0] l2t_rep_out1;
2175output [23:0] l2t_rep_out2;
2176output [23:0] l2t_rep_out3;
2177output [23:0] l2t_rep_out4;
2178output [23:0] l2t_rep_out5;
2179output [23:0] l2t_rep_out6;
2180output [23:0] l2t_rep_out7;
2181output [23:0] l2t_rep_out8;
2182output [23:0] l2t_rep_out9;
2183output [23:0] l2t_rep_out10;
2184output [23:0] l2t_rep_out11;
2185output [23:0] l2t_rep_out12;
2186output [23:0] l2t_rep_out13;
2187output [23:0] l2t_rep_out14;
2188output [23:0] l2t_rep_out15;
2189output [23:0] l2t_rep_out16;
2190output [23:0] l2t_rep_out17;
2191output [23:0] l2t_rep_out18;
2192output [23:0] l2t_rep_out19;
2193
2194input [191:0] l2t_lstg_in;
2195input [191:0] l2t_rstg_in;
2196output [191:0] l2t_lstg_out;
2197output [191:0] l2t_rstg_out;
2198
2199
2200/////////////////////////////////////////////////////////////////////////////////
2201// shadow scan
2202/////////////////////////////////////////////////////////////////////////////////
2203input tcu_l2t_shscan_scan_in;
2204input tcu_l2t_shscan_aclk;
2205input tcu_l2t_shscan_bclk;
2206input tcu_l2t_shscan_scan_en;
2207input tcu_l2t_shscan_pce_ov;
2208input tcu_l2t_shscan_clk_stop;
2209output l2t_tcu_shscan_scan_out;
2210
2211/////////////////////////////////////////////////////////////////////////////////
2212// DMO interface changes
2213/////////////////////////////////////////////////////////////////////////////////
2214input tcu_l2t_coresel; // 1= select current bank dmo out
2215input tcu_l2t_tag_or_data_sel;// 1= tag read data 0 = data read data
2216input [38:0] l2t_tcu_dmo_out_prev; // dmo output from prev bank
2217output [38:0] l2t_tcu_dmo_out; // dmo output from this bank
2218
2219//////////////////////////////////////////////////////////////////////////////
2220
2221wire [2:0] arb_cpuid_c5;
2222wire arb_oqu_swap_cas2_req_c2;
2223wire [2:0] csreg_notdata_addr_mux_sel;
2224wire arb_bs_or_bis_inst_c2;
2225// BS 04/20/04 , taking out arb_bs_or_bis_inst_c2 to l2t_usaloc_dp.sv
2226// to clear Use bit on a BST or BIST to mitigate pollution effect in L2 cache
2227// for Copy routines
2228wire [1:0] arbadr_arbdp_addr87_c2; // BS 03/25/04 for partial bank/core modes support
2229
2230wire arb_upper_four_byte_access_c1; // BS 05/04/04 : taking out upper_four_byte_access info to word_en_c2[15:0] gen logic in tag_ctl
2231wire arb_lower_four_byte_access_c1; // BS 05/04/04 : taking out upper_four_byte_access info to word_en_c2[15:0] gen logic in tag_ctl
2232wire [7:0] st_ack_bmask; // BS and SR 1/30/04,Bmask for store ack including Diagnostic store ack
2233wire [3:0] filbuf_tag_evict_way_c3; // BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Miss
2234wire tag_store_inst_c3; //BS and SR 11/07/03, store pipelining support
2235wire misbuf_hit_st_dep_zero; //BS and SR 11/07/03, store pipelining support
2236wire sel_st_ack_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
2237wire arbadr_dirvec_addr3_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
2238wire [63:0] st_ack_data; // BS and SR 11/12/03 N2 Xbar Packet format change
2239 // BS and SR 12/22/03, store ack generation for diagnostic store
2240wire sel_diag_store_data_c7; // BS and SR 12/22/03, store ack generation for diagnostic store
2241wire tag_inval_req_c5; // BS and SR 11/12/03 N2 Xbar Packet format change
2242wire arb_decdp_mmuld_inst_c6; // BS and SR 11/12/03 N2 Xbar Packet format change
2243wire oqu_mmu_ld_hit_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
2244
2245wire [3:0] tag_dir_l2way_sel_c4; // BS and SR 11/18/03 Reverse Directory change
2246
2247wire [3:0] ic_cam_en_row0; // To ic_row0 of dcm_row.v
2248wire [3:0] ic_cam_en_row2; // To ic_row2 of dcm_row.v
2249wire [3:0] ic_rd_en_row0; // To ic_row0 of dcm_row.v
2250wire [3:0] ic_rd_en_row2; // To ic_row2 of dcm_row.v
2251wire [3:0] ic_wr_en_row0; // To ic_row0 of dcm_row.v
2252wire [3:0] ic_wr_en_row2; // To ic_row2 of dcm_row.v
2253wire [3:0] dc_cam_en_row0; // To dc_row0 of dcm_row.v
2254wire [3:0] dc_cam_en_row2; // To dc_row2 of dcm_row.v
2255wire [3:0] dc_rd_en_row0; // To dc_row0 of dcm_row.v
2256wire [3:0] dc_rd_en_row2; // To dc_row2 of dcm_row.v
2257wire [3:0] dc_wr_en_row0; // To dc_row0 of dcm_row.v
2258wire [3:0] dc_wr_en_row2; // To dc_row2 of dcm_row.v
2259wire l2clk;
2260wire [38:0] arbdata_wr_data_c2 ;
2261wire [38:0] vuad_diag_data_c7;
2262wire [38:0] tagdp_vuad_dp_diag_data_c7_buf;
2263
2264// BS and SR VUAD ECC Change 8/9/04
2265
2266wire [77:0] write_data;
2267wire usaloc_ua_ue_c2;
2268wire usaloc_ua_ce_c2;
2269wire [5:0] usaloc_ua_synd_c2;
2270wire vlddir_vd_ue_c2;
2271wire [5:0] vlddir_vd_synd_c2;
2272
2273//////////////////
2274wire [5:2] arbdp_dbg_addr_c3;
2275wire arb_mb_camen_px2; //
2276wire [39:0] arbdp_cam_addr_px2; //
2277wire [41:7] arbadr_mbcam_addr_px2; //
2278wire arb_inst_vld_c1;
2279
2280
2281wire [`L2_POISON:`L2_SZ_LO]arbdp_inst_c8; //
2282
2283wire filbuf_buf_rd_en; //
2284wire [7:0] filbuf_fbtag_rd_ptr; //
2285wire filbuf_fbtag_wr_en; //
2286wire [7:0] filbuf_fbtag_wr_ptr; //
2287
2288wire iq_array_rd_en; //
2289wire [3:0] iq_array_rd_wl; //
2290wire iq_array_wr_en; //
2291wire [3:0] iq_array_wr_wl; //
2292
2293wire [31:0] mb_write_wl; // BS & SR 11/04/03, MB grows to 32
2294wire misbuf_dep_c8; //
2295wire misbuf_evict_c8; //
2296wire [4:0] misbuf_mbentry_c8; // BS & SR 11/04/03, MB grows to 32
2297wire misbuf_tecc_c8; //
2298wire [63:0] mbdata_inst_data_c8; //
2299wire [5:0] mbdata_inst_tecc_c8; //
2300wire mbtag_wr_en_c2; //
2301wire [31:0] mb_read_wl ; // BS & SR 11/04/03, MB grows to 32
2302wire [31:0] mb_data_write_wl; // BS & SR 11/04/03, MB grows to 32
2303wire mbdata_wr_en_c8;
2304
2305
2306wire [159:0] oq_array_data_in; //
2307wire oqarray_rd_en; //
2308wire [3:0] oqarray_rd_ptr; //
2309wire oqarray_wr_en; //
2310wire [3:0] oqarray_wr_ptr; //
2311
2312
2313wire [39:0] rdma_read_data;
2314wire [39:0] wb_read_data; // To arbadr of l2t_arbadr_dp.sv
2315
2316wire [7:0] fb_cam_match; // To filbuf of l2t_filbuf_ctl.sv // BS and SR 8 deep change 3/3/04
2317wire [39:0] fb_read_data; // To arbadr of l2t_arbadr_dp.sv
2318
2319wire [159:0] iq_array_rd_data_c1; // To ique of l2t_ique_dp.sv
2320wire [31:0] mb_cam_match; // To misbuf of l2t_misbuf_ctl.sv , BS & SR 11/04/03, MB grows to 32
2321wire [31:0] mb_cam_match_idx; // To misbuf of l2t_misbuf_ctl.sv, BS & SR 11/05/03 MB grows to 32
2322
2323wire [41:0] mb_read_data; // To l2t_evctag_dp.sv
2324wire [39:0] evctag_mb_read_data; // from l2t_evctag_dp.sv to fbtag and mbist module
2325
2326wire [159:0] oq_array_data_out; // To oque of l2t_oque_dp.sv
2327
2328wire [7:0] wb_cam_match_c2; // To wbuf of l2t_wbuf_ctl.sv // BS and SR 8 deep change 3/3/04
2329// wire [31:0] wr_data; // To icdir of l2t_dirblock.v, ...
2330wire [7:0] rdmat_cam_match_c2; // BS and SR 8 deep change 3/3/04
2331wire [3:0] rdmat_wr_wl_s2;
2332wire [39:6] rdmatag_wr_addr_s2;
2333wire rdmatag_wr_en_s2;
2334wire [3:0] rdmat_read_wl;
2335wire rdmat_read_en;
2336
2337wire [127:0] ic_cam_hit; //
2338wire ic_inval_vld_c7; //
2339
2340wire [127:0] dc_cam_hit; //
2341wire dc_inval_vld_c7; //
2342
2343// test related.
2344wire mbist_l2vuad_fail;
2345wire mbist_l2tag_fail;
2346wire mbist_l2data_fail;
2347
2348
2349wire [2:0] lkup_row_addr_icd_c3; //
2350wire [2:0] lkup_row_addr_dcd_c3; //
2351wire [17:9] tagd_lkup_addr_c4; // From tagd of l2t_tagd_dp.sv, BS and SR 11/18/03 Reverse Directory change
2352wire [41:0] mb_write_addr; //
2353wire [39:7] lkup_addr_c1; //
2354
2355wire wb_read_en; //
2356wire [7:0] wb_read_wl; //
2357wire [39:0] wb_write_addr; //
2358wire wbtag_write_en_c4; //
2359wire [7:0] wbtag_write_wl_c4; //
2360
2361// End of automatics
2362/*AUTOWIRE*/
2363// Beginning of automatic wires (for undeclared instantiated-module outputs)
2364wire alloc_rst_cond_c3; // From vuaddp of l2t_vuaddp_ctl.sv
2365wire alloc_set_cond_c3; // From vuaddp of l2t_vuaddp_ctl.sv
2366wire tag_alt_tag_miss_unqual_c3;// From tag of l2t_tag_ctl.sv
2367wire arbaddr_addr22_c2; // From arbadr of l2t_arbadr_dp.sv
2368wire [10:0] arbaddr_idx_c3; // From arbadr of l2t_arbadr_dp.sv
2369wire arbadr_addr2_c8; // From arbadr of l2t_arbadr_dp.sv
2370wire arb_acc_ua_c2; // From arb of l2t_arb_ctl.sv
2371wire arb_acc_vd_c2; // From arb of l2t_arb_ctl.sv
2372wire arb_csr_rd_en_c3; // From arb of l2t_arb_ctl.sv
2373wire arb_csr_rd_en_c7; // From arb of l2t_arb_ctl.sv
2374wire arb_csr_st_c2; // From arb of l2t_arb_ctl.sv
2375wire arb_csr_wr_en_c3; // From arb of l2t_arb_ctl.sv
2376wire arb_csr_wr_en_c7; // From arb of l2t_arb_ctl.sv
2377wire arb_data_diag_st_c2; // From arb of l2t_arb_ctl.sv
2378wire arb_dc_rd_en_c3; // From arb of l2t_arb_ctl.sv
2379wire arb_dc_wr_en_c3; // From arb of l2t_arb_ctl.sv
2380wire arb_decc_data_sel_c9;// From arb of l2t_arb_ctl.sv
2381wire arb_diag_complete_c3;// From arb of l2t_arb_ctl.sv
2382wire [4:0] arb_dir_panel_dcd_c3;// From arb of l2t_arb_ctl.sv
2383wire [4:0] arb_dir_panel_icd_c3;// From arb of l2t_arb_ctl.sv
2384wire arb_dir_vld_c3_l; // From arb of l2t_arb_ctl.sv
2385wire arb_dir_wr_en_c4; // From arb of l2t_arb_ctl.sv
2386wire arb_evict_c3; // From arb of l2t_arb_ctl.sv
2387wire arb_evict_c4; // From arb of l2t_arb_ctl.sv
2388wire arb_evict_c5; // From arb of l2t_arb_ctl.sv
2389wire arb_evict_tecc_vld_c2;// From arb of l2t_arb_ctl.sv
2390wire arb_evict_vld_c2; // From arb of l2t_arb_ctl.sv
2391wire arb_filbuf_fbsel_c1; // From arb of l2t_arb_ctl.sv
2392wire arb_filbuf_hit_off_c1;// From arb of l2t_arb_ctl.sv
2393//wire arb_filbuf_inst_vld_c2;// From arb of l2t_arb_ctl.sv
2394wire arb_fill_vld_c2; // From arb of l2t_arb_ctl.sv
2395wire arb_ic_rd_en_c3; // From arb of l2t_arb_ctl.sv
2396wire arb_ic_wr_en_c3; // From arb of l2t_arb_ctl.sv
2397wire arb_imiss_hit_c10; // From arb of l2t_arb_ctl.sv
2398wire arb_imiss_hit_c4; // From arb of l2t_arb_ctl.sv
2399wire arb_imiss_vld_c2; // From arb of l2t_arb_ctl.sv
2400wire arb_inst_diag_c1; // From arb of l2t_arb_ctl.sv
2401wire arb_inst_l2data_vld_c6;// From arb of l2t_arb_ctl.sv
2402wire arb_inst_l2tag_vld_c6;// From arb of l2t_arb_ctl.sv
2403wire arb_inst_l2vuad_vld_c3;// From arb of l2t_arb_ctl.sv
2404wire arb_inst_l2vuad_vld_c6;// From arb of l2t_arb_ctl.sv
2405wire arb_inst_vld_c2; // From arb of l2t_arb_ctl.sv
2406wire arb_inval_inst_c2; // From arb of l2t_arb_ctl.sv
2407wire [7:0] arb_inval_mask_dcd_c3;// From arb of l2t_arb_ctl.sv
2408wire [7:0] arb_inval_mask_icd_c3;// From arb of l2t_arb_ctl.sv
2409wire arb_iqsel_px2; // From arb of l2t_arb_ctl.sv
2410wire arb_l2tag_vld_c4; // From arb of l2t_arb_ctl.sv
2411wire [3:0] arb_lkup_bank_ena_dcd_c3;// From arb of l2t_arb_ctl.sv
2412wire [3:0] arb_lkup_bank_ena_icd_c3;// From arb of l2t_arb_ctl.sv
2413wire arb_misbuf_cas1_hit_c8;// From arb of l2t_arb_ctl.sv
2414wire arb_misbuf_ctrue_c9; // From arb of l2t_arb_ctl.sv
2415wire arb_misbuf_hit_off_c1;// From arb of l2t_arb_ctl.sv
2416wire arb_misbuf_inst_vld_c2;// From arb of l2t_arb_ctl.sv
2417wire arb_misbuf_mbsel_c1; // From arb of l2t_arb_ctl.sv
2418wire arb_normal_tagacc_c2;// From arb of l2t_arb_ctl.sv
2419wire arb_pst_ctrue_en_c8; // From arb of l2t_arb_ctl.sv
2420wire arb_rdwr_inst_vld_c2;// From arb of l2t_arb_ctl.sv
2421wire arb_tag_rd_px2; // From arb of l2t_arb_ctl.sv
2422wire tagd_arb_tag_rd_px2_buf; // From tagd of l2t_tagd_dp.sv
2423wire [15:0] arb_tag_way_px2; // From arb of l2t_arb_ctl.sv
2424wire [15:0] tagd_arb_tag_way_px2_buf; // From tagd of l2t_tagd_dp.sv
2425wire arb_tag_wr_px2; // From arb of l2t_arb_ctl.sv
2426wire tagd_arb_tag_wr_px2_buf; // From tagd of l2t_tagd_dp.sv
2427wire arb_tag_inst_vld_c2;// From arb of l2t_arb_ctl.sv
2428wire arb_tag_pst_with_ctrue_c1;// From arb of l2t_arb_ctl.sv
2429wire arb_tagd_perr_vld_c2;// From arb of l2t_arb_ctl.sv
2430wire arb_tagd_tecc_c2; // From arb of l2t_arb_ctl.sv
2431wire arb_tecc_c2; // From arb of l2t_arb_ctl.sv
2432wire [3:0] arb_tecc_way_c2; // From arb of l2t_arb_ctl.sv
2433wire arb_vuad_acc_px2; // From arb of l2t_arb_ctl.sv
2434wire arb_vuad_idx2_sel_px2_n;// From arb of l2t_arb_ctl.sv
2435wire arb_waysel_gate_c2; // From arb of l2t_arb_ctl.sv
2436wire arb_waysel_inst_vld_c2;// From arb of l2t_arb_ctl.sv
2437wire arb_wbuf_hit_off_c1;// From arb of l2t_arb_ctl.sv
2438wire arb_wbuf_inst_vld_c2;// From arb of l2t_arb_ctl.sv
2439wire [4:0] arb_wr_dc_dir_entry_c3;// From arb of l2t_arb_ctl.sv
2440wire [4:0] arb_wr_ic_dir_entry_c3;// From arb of l2t_arb_ctl.sv
2441wire [31:0] arbdec_ctag_c6; // From arbdec of l2t_arbdec_dp.sv// Phase 2 : SIU inteface and packet format change 2/7/04
2442wire [7:0] arbadr_arbdp_addr11to4_c3; // From arbadr of l2t_arbadr_dp.sv
2443wire arbadr_arbdp_addr22_c7; // From arbadr of l2t_arbadr_dp.sv
2444wire [1:0] arbadr_arbdp_addr3to2_c1; // From arbadr of l2t_arbadr_dp.sv
2445wire [1:0] arbadr_arbdp_addr5to4_c1; // From arbadr of l2t_arbadr_dp.sv
2446wire [1:0] arbadr_arbdp_addr5to4_c3; // From arbadr of l2t_arbadr_dp.sv
2447wire arbadr_arbdp_addr_c1c2comp_c1; // From arbadr of l2t_arbadr_dp.sv
2448wire arbadr_arbdp_addr_c1c3comp_c1; // From arbadr of l2t_arbadr_dp.sv
2449wire arbadr_arbdp_addr_start_c2; // From arbadr of l2t_arbadr_dp.sv
2450wire [2:0] arbadr_arbdp_byte_addr_c6; // From arbadr of l2t_arbadr_dp.sv // Phase 2 of SIU changes
2451wire [2:0] arbdec_arbdp_cpuid_c2; // From arbdec of l2t_arbdec_dp.sv
2452wire [2:0] arbdec_arbdp_cpuid_c5; // From arbdec of l2t_arbdec_dp.sv
2453wire [39:4] arbadr_arbdp_csr_addr_c9; // From arbadr of l2t_arbadr_dp.sv
2454wire [3:0] arbadr_arbdp_diag_wr_way_c2; // From arbadr of l2t_arbadr_dp.sv
2455wire arbdec_arbdp_evict_c1; // From arbdec of l2t_arbdec_dp.sv
2456wire arbdec_arbdp_inst_bufid1_c1; // From arbdec of l2t_arbdec_dp.sv
2457wire arbdec_arbdp_inst_bufidhi_c1; // From arbdec of l2t_arbdec_dp.sv
2458wire arbdec_arbdp_inst_bufidlo_c2; // From arbdec of l2t_arbdec_dp.sv
2459wire [2:0] arbdec_arbdp_inst_cpuid_c7; // From arbdec of l2t_arbdec_dp.sv
2460wire arbdec_arbdp_inst_ctrue_c1; // From arbdec of l2t_arbdec_dp.sv
2461wire arbdec_arbdp_inst_dep_c2; // From arbdec of l2t_arbdec_dp.sv
2462wire arbdec_arbdp_inst_fb_c1; // From arbdec of l2t_arbdec_dp.sv
2463wire arbdec_arbdp_inst_fb_c2; // From arbdec of l2t_arbdec_dp.sv
2464wire [1:0] arbdec_arbdp_inst_l1way_c7; // From arbdec of l2t_arbdec_dp.sv
2465wire arbdec_arbdp_inst_mb_c1; // From arbdec of l2t_arbdec_dp.sv
2466wire arbdec_arbdp_inst_mb_c2; // From arbdec of l2t_arbdec_dp.sv
2467wire arbdec_arbdp_inst_mb_c3; // From arbdec of l2t_arbdec_dp.sv
2468wire [4:0] arbdec_arbdp_inst_mb_entry_c1; // From arbdec of l2t_arbdec_dp.sv, BS & SR 11/04/03, MB grows to 32
2469wire arbdec_arbdp_inst_nc_c1; // From arbdec of l2t_arbdec_dp.sv
2470wire arbdec_arbdp_inst_nc_c3; // From arbdec of l2t_arbdec_dp.sv
2471wire arbdec_arbdp_inst_nc_c7; // From arbdec of l2t_arbdec_dp.sv
2472wire [`L2_RQTYP_HI:`L2_RQTYP_LO]arbdec_arbdp_inst_rqtyp_c1;// From arbdec of l2t_arbdec_dp.sv
2473wire [`L2_RQTYP_HI:`L2_RQTYP_LO]arbdec_arbdp_inst_rqtyp_c2;// From arbdec of l2t_arbdec_dp.sv
2474wire [`L2_RQTYP_HI:`L2_RQTYP_LO]arbdec_arbdp_inst_rqtyp_c6;// From arbdec of l2t_arbdec_dp.sv
2475//wire arbdec_arbdp_inst_rsvd_c1; // From arbdec of l2t_arbdec_dp.sv
2476wire [`L2_SZ_HI:`L2_SZ_LO]arbdec_arbdp_inst_size_c1; // From arbdec of l2t_arbdec_dp.sv
2477wire [7:0] arbdec_arbdp_inst_size_c7; // From arbdec of l2t_arbdec_dp.sv, BS and SR 11/12/03 N2 Xbar Packet format change
2478wire arbdec_arbdp_inst_tecc_c3; // From arbdec of l2t_arbdec_dp.sv
2479wire [2:0] arbdec_arbdp_inst_tid_c7; // From arbdec of l2t_arbdec_dp.sv, BS and SR 11/12/03 N2 Xbar Packet format change
2480wire [3:0] arbdec_arbdp_inst_way_c1; // From arbdec of l2t_arbdec_dp.sv
2481wire [3:0] arbdec_arbdp_inst_way_c2; // From arbdec of l2t_arbdec_dp.sv
2482wire [3:0] arbdec_arbdp_inst_way_c3; // From arbdec of l2t_arbdec_dp.sv
2483wire arbdec_arbdp_int_bcast_c5; // From arbdec of l2t_arbdec_dp.sv
2484wire [39:32] arbadr_arbdp_ioaddr_c1; // From arbadr of l2t_arbadr_dp.sv
2485wire [1:0] arbdec_arbdp_l1way_c3; // From arbdec of l2t_arbdec_dp.sv
2486wire [5:4] arbadr_arbdp_line_addr_c6; // From arbadr of l2t_arbadr_dp.sv
2487wire arb_arbdp_misbuf_pst_no_ctrue_c2;// From arb of l2t_arb_ctl.sv
2488wire [1:0] arbadr_arbdp_new_addr5to4_px2; // From arbadr of l2t_arbadr_dp.sv
2489wire [17:0] arbdat_arbdp_oque_int_ret_c7; // From arbdat of l2t_arbdat_dp.sv
2490wire [11:6] arbadr_arbdp_oque_l1_index_c7; // From arbadr of l2t_arbadr_dp.sv
2491wire arbdec_arbdp_poison_c1; // From arbdec of l2t_arbdec_dp.sv
2492wire arb_arbdp_pst_with_ctrue_c2;// From arb of l2t_arb_ctl.sv
2493wire [1:0] arbdec_arbdp_rdma_entry_c3; // From arbdec of l2t_arbdec_dp.sv
2494wire arbdec_arbdp_rdma_inst_c1; // From arbdec of l2t_arbdec_dp.sv
2495wire arbdec_arbdp_rdma_inst_c2; // From arbdec of l2t_arbdec_dp.sv
2496wire [5:2] arbadr_arbdp_rdmat_addr_c6; // From arbadr of l2t_arbadr_dp.sv
2497wire [8:0] arbadr_arbdp_tag_idx_px2; // From arbadr of l2t_arbadr_dp.sv
2498wire arb_arbdp_tag_pst_no_ctrue_c2;// From arb of l2t_arb_ctl.sv
2499wire [27:6] arbadr_arbdp_tagdata_px2; // From arbadr of l2t_arbadr_dp.sv
2500wire arbdec_arbdp_tecc_c1; // From arbdec of l2t_arbdec_dp.sv
2501wire arb_arbdp_tecc_inst_mb_c8; // From arb of l2t_arb_ctl.sv
2502wire [8:0] arbadr_arbdp_vuad_idx1_px2; // From arbadr of l2t_arbadr_dp.sv
2503wire [8:0] arbadr_arbdp_vuad_idx2_px2; // From arbadr of l2t_arbadr_dp.sv
2504wire arb_arbdp_vuadctl_pst_no_ctrue_c2;// From arb of l2t_arb_ctl.sv
2505wire [1:0] arbadr_arbdp_waddr_c6; // From arbadr of l2t_arbadr_dp.sv
2506wire [4:0] arbadr_arbdp_word_addr_c6; // From arbadr of l2t_arbadr_dp.sv
2507wire oqu_atm_inst_ack_c7; // From oqu of l2t_oqu_ctl.sv
2508wire arb_bist_or_diag_acc_c1;// From arb of l2t_arb_ctl.sv
2509wire [38:0] vuadpm_bistordiag_ua_data; // From vuadpm of l2t_vuadpm_dp.sv
2510wire [38:0] vuadpm_bistordiag_vd_data; // From vuadpm of l2t_vuadpm_dp.sv
2511wire vuaddp_bistordiag_wr_ua_c4;// From vuaddp of l2t_vuaddp_ctl.sv
2512wire vuaddp_bistordiag_wr_vd_c4; // From vuaddp of l2t_vuaddp_ctl.sv
2513wire arbadr_c1_addr_eq_wb_c4; // From arbadr of l2t_arbadr_dp.sv
2514wire tag_cerr_ack_tmp_c4; // From tag of l2t_tag_ctl.sv
2515wire csreg_csr_addr_wr_en; // From csreg of l2t_csreg_ctl.sv
2516wire csreg_csr_async_wr_en; // From csreg of l2t_csreg_ctl.sv
2517wire csreg_csr_bist_wr_en_c8; // From csreg of l2t_csreg_ctl.sv
2518wire csreg_csr_wr_en_c8; // From csreg of l2t_csreg_ctl.sv
2519wire csreg_csr_erren_wr_en_c8; // From csreg of l2t_csreg_ctl.sv
2520wire csreg_csr_errinj_wr_en_c8; // From csreg of l2t_csreg_ctl.sv
2521wire csreg_csr_errstate_wr_en_c8; // From csreg of l2t_csreg_ctl.sv
2522wire csr_filbuf_l2off; // From csr of l2t_csr_ctl.sv
2523wire csr_filbuf_scrub_ready; // From csr of l2t_csr_ctl.sv
2524wire [63:0] arbdat_csr_inst_wr_data_c8; // From arbdat of l2t_arbdat_dp.sv
2525wire csr_misbuf_l2off; // From csr of l2t_csr_ctl.sv
2526wire [63:0] csr_rd_data_c8; // From csr of l2t_csr_ctl.sv
2527wire [3:0] csreg_csr_rd_mux1_sel_c7; // From csreg of l2t_csreg_ctl.sv
2528wire csreg_csr_rd_mux2_sel_c7; // From csreg of l2t_csreg_ctl.sv
2529wire [1:0] csreg_csr_rd_mux3_sel_c7; // From csreg of l2t_csreg_ctl.sv
2530wire csreg_csr_synd_wr_en; // From csreg of l2t_csreg_ctl.sv
2531wire csr_tag_l2off; // From csr of l2t_csr_ctl.sv
2532wire csreg_csr_tid_wr_en; // From csreg of l2t_csreg_ctl.sv
2533wire csr_vuad_l2off; // From csr of l2t_csr_ctl.sv
2534wire csr_wbuf_l2off; // From csr of l2t_csr_ctl.sv
2535wire csr_wr_dirpinj_en; // From csr of l2t_csr_ctl.sv
2536wire tag_data_ecc_active_c3; // From tag of l2t_tag_ctl.sv
2537wire [8:0] arbadr_data_ecc_idx; // From arbadr of l2t_arbadr_dp.sv
2538wire arb_data_ecc_idx_en; // From arb of l2t_arb_ctl.sv
2539wire arb_data_ecc_idx_reset; // From arb of l2t_arb_ctl.sv
2540wire [155:0] data_in_h_r0; // From subarray_0 of lib_r_rf32x108_cust.sv
2541wire [155:0] data_in_h_r1; // From subarray_1 of lib_r_rf32x108_cust.sv
2542wire [155:0] data_in_h_r10; // From subarray_10 of lib_r_rf32x108_cust.sv
2543wire [155:0] data_in_h_r11; // From subarray_11 of lib_r_rf32x108_cust.sv
2544wire [155:0] data_in_h_r2; // From subarray_2 of lib_r_rf32x108_cust.sv
2545wire [155:0] data_in_h_r3; // From subarray_3 of lib_r_rf32x108_cust.sv
2546wire [155:0] data_in_h_r8; // From subarray_8 of lib_r_rf32x108_cust.sv
2547wire [155:0] data_in_h_r9; // From subarray_9 of lib_r_rf32x108_cust.sv
2548wire [38:0] data_out_col_r0; // From vuadcl_0 of l2t_vuadcl_dp.sv
2549wire [38:0] data_out_col_r10; // From vuadcl_10 of l2t_vuadcl_dp.sv
2550wire [38:0] data_out_col_r2; // From vuadcl_2 of l2t_vuadcl_dp.sv
2551wire [38:0] data_out_col_r8; // From vuadcl_8 of l2t_vuadcl_dp.sv
2552wire dirrep_dc_dir_clear_c4; // From dirrep of l2t_dirrep_ctl.sv
2553wire [7:0] dc_inv_mask_0145; // From dc_ctl_0145 of l2t_dir_ctl.sv
2554wire [7:0] dc_inv_mask_2367; // From dc_ctl_2367 of l2t_dir_ctl.sv
2555wire [7:0] dc_inv_mask_89cd; // From dc_ctl_89cd of l2t_dir_ctl.sv
2556wire [7:0] dc_inv_mask_abef; // From dc_ctl_abef of l2t_dir_ctl.sv
2557wire [3:0] dirrep_dc_lkup_panel_dec_c4; // From dirrep of l2t_dirrep_ctl.sv
2558wire [3:0] dc_lkup_row_dec_c4; // From dirrep of l2t_dirrep_ctl.sv
2559wire [15:0] dc_lkup_wr_data_c4_row0;// From dc_buf_row0 of l2t_dirlbf_dp.sv, BS and SR 11/18/03 Reverse Directory change
2560wire [15:0] dc_lkup_wr_data_c4_row2;// From dc_buf_row1 of l2t_dirlbf_dp.sv , BS and SR 11/18/03 Reverse Directory change
2561wire [2:0] dc_parity_in; // From dc_out_col0 of l2t_dirout_dp.sv, ...
2562wire [3:0] dc_parity_out; // From dc_out_col3 of l2t_dirout_dp.sv, ...
2563wire [15:0] dc_rd_data04_row0; // From dc_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2564wire [15:0] dc_rd_data15_row0; // From dc_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2565wire [15:0] dc_rd_data26_row0; // From dc_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2566wire [15:0] dc_rd_data37_row0; // From dc_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2567wire [15:0] dc_rd_data8c_row2; // From dc_row2 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2568wire [15:0] dc_rd_data9d_row2; // From dc_row2 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2569wire [15:0] dc_rd_dataae_row2; // From dc_row2 of lib_r_dcm_cust.sv
2570wire [15:0] dc_rd_databf_row2; // From dc_row2 of lib_r_dcm_cust.sv
2571wire dirrep_dc_rd_en_c4; // From dirrep of l2t_dirrep_ctl.sv
2572wire [3:0] dirrep_dc_rdwr_panel_dec_c4; // From dirrep of l2t_dirrep_ctl.sv
2573wire [3:0] dirrep_dc_rdwr_row_en_c4; // From dirrep of l2t_dirrep_ctl.sv
2574wire [5:0] dc_rw_addr_0145; // From dc_ctl_0145 of l2t_dir_ctl.sv, BS and SR 11/18/03 Reverse Directory change
2575wire [5:0] dc_rw_addr_89cd; // From dc_ctl_89cd of l2t_dir_ctl.sv, BS and SR 11/18/03 Reverse Directory change
2576wire [4:0] dc_rw_addr_abef; // From dc_ctl_abef of l2t_dir_ctl.sv, BS and SR 11/18/03 Reverse Directory change
2577wire dc_warm_rst_0145; // From dc_ctl_0145 of l2t_dir_ctl.sv
2578wire dc_warm_rst_89cd; // From dc_ctl_89cd of l2t_dir_ctl.sv
2579//wire dc_warm_rst_abef; // From dc_ctl_abef of l2t_dir_ctl.sv
2580wire dirrep_dc_wr_en_c4; // From dirrep of l2t_dirrep_ctl.sv
2581wire deccck_bscd_corr_err_c8; // From deccck of l2t_deccck_ctl.sv
2582wire deccck_bscd_uncorr_err_c8;// From deccck of l2t_deccck_ctl.sv
2583wire deccck_scrd_corr_err_c8; // From deccck of l2t_deccck_ctl.sv
2584wire deccck_scrd_uncorr_err_c8;// From deccck of l2t_deccck_ctl.sv
2585wire deccck_spcd_corr_err_c8; // From deccck of l2t_deccck_ctl.sv
2586wire deccck_spcd_uncorr_err_c8;// From deccck of l2t_deccck_ctl.sv
2587wire deccck_spcfb_corr_err_c8; // From deccck of l2t_deccck_ctl.sv
2588wire deccck_spcfb_uncorr_err_c8;// From deccck of l2t_deccck_ctl.sv
2589wire tag_decc_tag_acc_en_px2; // From tag of l2t_tag_ctl.sv
2590wire deccck_uncorr_err_c8; // From deccck of l2t_deccck_ctl.sv
2591wire deccck_corr_err_c8; // From deccck of l2t_deccck_ctl.sv
2592wire [63:0] decc_arbdp_data_c8; // From decc of l2t_decc_dp.sv
2593wire arb_decdp_atm_inst_c6; // From arb of l2t_arb_ctl.sv
2594wire arb_decdp_bis_inst_c3; // From arb of l2t_arb_ctl.sv
2595wire arb_decdp_cas1_inst_c2; // From arb of l2t_arb_ctl.sv
2596wire arb_decdp_cas2_from_mb_c2; // From arb of l2t_arb_ctl.sv
2597//wire arb_decdp_cas2_from_mb_ctrue_c2;// From arb of l2t_arb_ctl.sv
2598wire arb_decdp_cas2_inst_c2; // From arb of l2t_arb_ctl.sv
2599wire arb_decdp_fwd_req_c2; // From arb of l2t_arb_ctl.sv
2600wire arb_decdp_imiss_inst_c2; // From arb of l2t_arb_ctl.sv
2601wire arb_decdp_inst_int_c2; // From arb of l2t_arb_ctl.sv
2602wire arb_decdp_inst_int_c1; // From arb of l2t_arb_ctl.sv
2603wire arb_decdp_ld64_inst_c1; // From arb of l2t_arb_ctl.sv
2604wire arb_decdp_ld64_inst_c2; // From arb of l2t_arb_ctl.sv
2605wire arb_decdp_ld_inst_c2; // From arb of l2t_arb_ctl.sv
2606wire arb_decdp_pf_inst_c5; // From arb of l2t_arb_ctl.sv
2607wire arb_decdp_pst_inst_c2; // From arb of l2t_arb_ctl.sv
2608wire arb_decdp_rmo_st_c3; // From arb of l2t_arb_ctl.sv
2609wire arb_decdp_st_inst_c2; // From arb of l2t_arb_ctl.sv
2610wire arb_decdp_st_inst_c3; // From arb of l2t_arb_ctl.sv
2611wire arb_decdp_st_with_ctrue_c2; // From arb of l2t_arb_ctl.sv
2612wire arb_decdp_strld_inst_c6; // From arb of l2t_arb_ctl.sv
2613wire arb_decdp_strst_inst_c2; // From arb of l2t_arb_ctl.sv
2614wire arb_decdp_swap_inst_c2; // From arb of l2t_arb_ctl.sv
2615wire arb_decdp_tag_wr_c1; // From arb of l2t_arb_ctl.sv
2616wire arb_decdp_wr64_inst_c2; // From arb of l2t_arb_ctl.sv
2617wire arb_decdp_wr8_inst_c2; // From arb of l2t_arb_ctl.sv
2618wire arb_diag_or_tecc_write_px2; // From arb of l2t_arb_ctl.sv
2619wire [38:0] usaloc_diag_rd_ua_out; // From usaloc of l2t_usaloc_dp.sv
2620wire [38:0] vlddir_diag_rd_vd_out; // From vlddir of l2t_vlddir_dp.sv
2621wire [10:0] arb_dir_addr_c9; // From arb of l2t_arb_ctl.sv
2622wire [39:7] arbadr_dir_cam_addr_c3; // From arbadr of l2t_arbadr_dp.sv
2623wire dirrep_dir_error_c8; // From dirrep of l2t_dirrep_ctl.sv
2624wire dirrep_dir_vld_c4_l; // From dirrep of l2t_dirrep_ctl.sv
2625wire [111:0] dirvec_dirdp_inval_pckt_c7; // From dirvec of l2t_dirvec_dp.sv
2626wire [7:0] dirvec_dirdp_req_vec_c6; // From dirvec of l2t_dirvec_dp.sv
2627wire [3:0] dirvec_dirdp_way_info_c7; // From dirvec of l2t_dirvec_dp.sv, BS and SR 11/18/03 Support for 8 way I$
2628wire vlddir_dirty_evict_c3; // From vlddir of l2t_vlddir_dp.sv
2629wire filbuf_mcu_scb_mecc_err_d1; // From filbuf of l2t_filbuf_ctl.sv
2630wire filbuf_mcu_scb_secc_err_d1; // From filbuf of l2t_filbuf_ctl.sv
2631wire [1:0] filbuf_mcu_l2t_chunk_id_r1; // From filbuf of l2t_filbuf_ctl.sv
2632wire filbuf_mcu_l2t_data_vld_r1; // From filbuf of l2t_filbuf_ctl.sv
2633wire [7:0] arb_dword_mask_c8; // From arb of l2t_arb_ctl.sv
2634wire deccck_dword_sel_c7; // From deccck of l2t_deccck_ctl.sv
2635wire [`ERR_LDAC:`ERR_LVC] csreg_err_state_in; // From csreg of l2t_csreg_ctl.sv
2636wire csreg_err_state_in_mec; // From csreg of l2t_csreg_ctl.sv
2637wire csreg_err_state_in_meu; // From csreg of l2t_csreg_ctl.sv
2638wire csreg_err_state_in_rw; // From csreg of l2t_csreg_ctl.sv
2639wire csr_error_ceen; // From csr of l2t_csr_ctl.sv
2640wire csr_error_nceen; // From csr of l2t_csr_ctl.sv
2641wire csr_error_status_vec; // From csr of l2t_csr_ctl.sv
2642wire csr_error_status_veu; // From csr of l2t_csr_ctl.sv
2643wire rdmat_ev_cerr_r6; // From rdmat of l2t_rdmat_ctl.sv
2644wire rdmat_ev_uerr_r6; // From rdmat of l2t_rdmat_ctl.sv
2645wire [39:6] evctag_evict_addr; // From evctag of l2t_evctag_dp.sv
2646wire [39:0] evctag_addr_px2; // From evctag of l2t_evctag_dp.sv
2647wire filbuf_fb_count_eq_0; // From filbuf of l2t_filbuf_ctl.sv
2648wire filbuf_arb_l2rd_en; // From filbuf of l2t_filbuf_ctl.sv
2649wire filbuf_arb_vld_px1; // From filbuf of l2t_filbuf_ctl.sv
2650wire [2:0] filbuf_arbdp_entry_px2; // From filbuf of l2t_filbuf_ctl.sv
2651wire filbuf_arbdp_tecc_px2; // From filbuf of l2t_filbuf_ctl.sv
2652wire [3:0] filbuf_arbdp_way_px2; // From filbuf of l2t_filbuf_ctl.sv
2653wire filbuf_bsc_corr_err_c12; // From filbuf of l2t_filbuf_ctl.sv
2654wire filbuf_corr_err_c8; // From filbuf of l2t_filbuf_ctl.sv
2655wire filbuf_dis_cerr_c3; // From filbuf of l2t_filbuf_ctl.sv
2656wire filbuf_dis_uerr_c3; // From filbuf of l2t_filbuf_ctl.sv
2657wire filbuf_fbd_rd_en_c2; // From filbuf of l2t_filbuf_ctl.sv
2658wire [2:0] filbuf_fbd_rd_entry_c2; // From filbuf of l2t_filbuf_ctl.sv
2659wire [2:0] filbuf_fbd_wr_entry_r1; // From filbuf of l2t_filbuf_ctl.sv
2660wire filbuf_ld64_fb_hit_c12; // From filbuf of l2t_filbuf_ctl.sv
2661wire filbuf_misbuf_entry_avail;// From filbuf of l2t_filbuf_ctl.sv
2662wire [2:0] filbuf_misbuf_fbid_d2; // From filbuf of l2t_filbuf_ctl.sv
2663wire filbuf_misbuf_match_c2; // From filbuf of l2t_filbuf_ctl.sv
2664wire filbuf_misbuf_nofill_d2; // From filbuf of l2t_filbuf_ctl.sv
2665wire filbuf_misbuf_stinst_match_c2;// From filbuf of l2t_filbuf_ctl.sv
2666wire filbuf_spc_corr_err_c6; // From filbuf of l2t_filbuf_ctl.sv
2667wire filbuf_spc_rd_vld_c6; // From filbuf of l2t_filbuf_ctl.sv
2668wire filbuf_spc_uncorr_err_c6;// From filbuf of l2t_filbuf_ctl.sv
2669wire filbuf_tag_hit_c2; // From filbuf of l2t_filbuf_ctl.sv
2670wire filbuf_uncorr_err_c8; // From filbuf of l2t_filbuf_ctl.sv
2671wire filbuf_vuad_bypassed_c3; // From filbuf of l2t_filbuf_ctl.sv
2672wire [4:0] filbuf_fbf_enc_dep_mbid_c4; // From filbuf of l2t_filbuf_ctl.sv,BS & SR 11/04/03, MB grows to 32
2673wire [4:0] filbuf_fbf_enc_ld_mbid_r1; // From filbuf of l2t_filbuf_ctl.sv, BS & SR 11/04/03, MB grows to 32
2674wire filbuf_fbf_ready_miss_r1; // From filbuf of l2t_filbuf_ctl.sv
2675wire filbuf_fbf_st_or_dep_rdy_c4; // From filbuf of l2t_filbuf_ctl.sv
2676wire [15:0] vuaddp_fill_way_c3; // From vuaddp of l2t_vuaddp_ctl.sv
2677wire oqu_fwd_req_ret_c7; // From oqu of l2t_oqu_ctl.sv
2678wire dirrep_ic_dir_clear_c4; // From dirrep of l2t_dirrep_ctl.sv
2679wire [7:0] ic_inv_mask_0145; // From ic_ctl_0145 of l2t_dir_ctl.sv
2680wire [7:0] ic_inv_mask_2367; // From ic_ctl_2367 of l2t_dir_ctl.sv
2681wire [7:0] ic_inv_mask_89cd; // From ic_ctl_89cd of l2t_dir_ctl.sv
2682wire [7:0] ic_inv_mask_abef; // From ic_ctl_abef of l2t_dir_ctl.sv
2683wire [3:0] dirrep_ic_lkup_panel_dec_c4; // From dirrep of l2t_dirrep_ctl.sv
2684wire [3:0] dirrep_ic_lkup_row_dec_c4; // From dirrep of l2t_dirrep_ctl.sv
2685wire [15:0] ic_lkup_wr_data_c4_row0;// From ic_buf_row0 of l2t_dirlbf_dp.sv, BS and SR 11/18/03 Reverse Directory change
2686wire [15:0] ic_lkup_wr_data_c4_row2;// From ic_buf_row1 of l2t_dirlbf_dp.sv, BS and SR 11/18/03 Reverse Directory change
2687wire [2:0] ic_parity_in; // From out_col0 of l2t_dirout_dp.sv, ...
2688wire [3:0] ic_parity_out; // From out_col3 of l2t_dirout_dp.sv, ...
2689wire [15:0] ic_rd_data04_row0; // From ic_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2690wire [15:0] ic_rd_data15_row0; // From ic_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2691wire [15:0] ic_rd_data26_row0; // From ic_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2692wire [15:0] ic_rd_data37_row0; // From ic_row0 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2693wire [15:0] ic_rd_data8c_row1; // From ic_row2 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2694wire [15:0] ic_rd_data9d_row1; // From ic_row2 of lib_r_dcm_cust.sv, BS and SR 11/18/03 Reverse Directory change
2695wire dirrep_ic_rd_en_c4; // From dirrep of l2t_dirrep_ctl.sv
2696wire [3:0] dirrep_ic_rdwr_panel_dec_c4; // From dirrep of l2t_dirrep_ctl.sv
2697wire [3:0] dirrep_ic_rdwr_row_en_c4; // From dirrep of l2t_dirrep_ctl.sv
2698wire [5:0] ic_rw_addr_0145; // From ic_ctl_0145 of l2t_dir_ctl.sv , BS and SR 11/18/03 Reverse Directory change
2699wire [5:0] ic_rw_addr_2367; // From ic_ctl_2367 of l2t_dir_ctl.sv , BS and SR 11/18/03 Reverse Directory change
2700wire [5:0] ic_rw_addr_89cd; // From ic_ctl_89cd of l2t_dir_ctl.sv , BS and SR 11/18/03 Reverse Directory change
2701wire [5:0] ic_rw_addr_abef; // From ic_ctl_abef of l2t_dir_ctl.sv , BS and SR 11/18/03 Reverse Directory change
2702wire ic_warm_rst_0145; // From ic_ctl_0145 of l2t_dir_ctl.sv
2703wire ic_warm_rst_89cd; // From ic_ctl_89cd of l2t_dir_ctl.sv
2704wire dirrep_ic_wr_en_c4; // From dirrep of l2t_dirrep_ctl.sv
2705//wire arbadr_idx_c1c4comp_c1; // From arbadr of l2t_arbadr_dp.sv
2706//wire arbadr_idx_c1c5comp_c1; // From arbadr of l2t_arbadr_dp.sv
2707wire arb_inc_tag_ecc_cnt_c3_n; // From arb of l2t_arb_ctl.sv
2708wire [7:0] dirrep_inval_mask_dcd_c4; // From dirrep of l2t_dirrep_ctl.sv
2709wire [7:0] dirrep_inval_mask_icd_c4; // From dirrep of l2t_dirrep_ctl.sv
2710wire tagdp_invalid_evict_c3; // From tagdp of l2t_tagdp_ctl.sv
2711wire ique_iq_arb_atm_px2; // From ique of l2t_ique_dp.sv
2712wire ique_iq_arb_csr_px2; // From ique of l2t_ique_dp.sv
2713wire ique_iq_arb_st_px2; // From ique of l2t_ique_dp.sv
2714wire ique_iq_arb_vbit_px2; // From ique of l2t_ique_dp.sv
2715wire iqu_iq_arb_vld_px2; // From iqu of l2t_iqu_ctl.sv
2716wire [39:0] ique_iq_arbdp_addr_px2; // From ique of l2t_ique_dp.sv
2717wire [63:0] ique_iq_arbdp_data_px2; // From ique of l2t_ique_dp.sv
2718wire [24:0] ique_iq_arbdp_inst_px2; // From ique of l2t_ique_dp.sv // BS and SR 11/12/03 N2 Xbar Packet format
2719wire iqu_sel_c1; // From iqu of l2t_iqu_ctl.sv
2720wire iqu_sel_pcx; // From iqu of l2t_iqu_ctl.sv
2721//wire rdmat_sii_req_vld_buf; // From rdmat of l2t_rdmat_ctl.sv
2722wire csr_l2_bypass_mode_on; // From csr of l2t_csr_ctl.sv
2723//wire csr_l2_dbg_en; // From csr of l2t_csr_ctl.sv
2724wire csr_l2_dir_map_on; // From csr of l2t_csr_ctl.sv
2725wire csreg_tagdp_l2_dir_map_on; // From csreg of l2t_csreg_ctl.sv
2726wire csreg_misbuf_l2_dir_map_on; // From csreg of l2t_csreg_ctl.sv
2727wire csreg_filbuf_l2_dir_map_on; // From csreg of l2t_csreg_ctl.sv
2728
2729wire [5:0] csr_l2_steering_tid; // From csr of l2t_csr_ctl.sv, BS and SR 11/12/03 N2 Xbar Packet format
2730wire [27:0] decc_lda_syndrome_c9; // From decc of l2t_decc_dp.sv
2731wire [`TAG_WIDTH_LESS1:1] tagd_lkup_tag_c1; // From tagd of l2t_tagd_dp.sv
2732
2733
2734wire [15:0] vuaddp_lru_way_c3; // From vuaddp of l2t_vuaddp_ctl.sv
2735wire [15:0] tagdp_lru_way_sel_c3; // From tagdp of l2t_tagdp_ctl.sv
2736wire [127:0] mb_data_read_data; // From mbdata of lib_r_rf16x128d_cust.sv
2737wire misbuf_arb_mcurd_en; // From misbuf of l2t_misbuf_ctl.sv
2738wire misbuf_arb_l2rd_en; // From misbuf of l2t_misbuf_ctl.sv
2739wire misbuf_arb_cnt28_px2_prev;// From misbuf of l2t_misbuf_ctl.sv
2740wire misbuf_arb_snp_cnt8_px1;// From misbuf of l2t_misbuf_ctl.sv
2741wire misbuf_arb_vld_px1; // From misbuf of l2t_misbuf_ctl.sv
2742wire misbuf_arbdp_ctrue_px2; // From misbuf of l2t_misbuf_ctl.sv
2743wire misbuf_buf_rd_en; // From misbuf of l2t_misbuf_ctl.sv
2744wire misbuf_corr_err_c2; // From misbuf of l2t_misbuf_ctl.sv
2745wire misbuf_filbuf_mcu_pick; // From misbuf of l2t_misbuf_ctl.sv
2746wire [2:0] misbuf_filbuf_fbid; // From misbuf of l2t_misbuf_ctl.sv
2747wire [4:0] misbuf_filbuf_next_link_c4;// From misbuf of l2t_misbuf_ctl.sv, BS & SR 11/04/03, MB grows to 32
2748
2749wire misbuf_filbuf_next_vld_c4;// From misbuf of l2t_misbuf_ctl.sv
2750wire [3:0] misbuf_filbuf_way; // From misbuf of l2t_misbuf_ctl.sv
2751wire misbuf_filbuf_way_fbid_vld;// From misbuf of l2t_misbuf_ctl.sv
2752wire misbuf_hit_c3; // From misbuf of l2t_misbuf_ctl.sv
2753wire misbuf_hit_c4; // From misbuf of l2t_misbuf_ctl.sv
2754wire misbuf_nondep_fbhit_c3; // From misbuf of l2t_misbuf_ctl.sv
2755wire tag_misbuf_rdma_reg_vld_c2; // From tag of l2t_tag_ctl.sv
2756wire misbuf_tag_hit_unqual_c2;// From misbuf of l2t_misbuf_ctl.sv
2757wire misbuf_uncorr_err_c2; // From misbuf of l2t_misbuf_ctl.sv
2758wire [4:0] misbuf_wbuf_mbid_c4; // From misbuf of l2t_misbuf_ctl.sv, BS & SR 11/04/03, MB grows to 32
2759wire misbuf_wr64_miss_comp_c3;// From misbuf of l2t_misbuf_ctl.sv
2760wire misbuf_mbf_delete_c4; // From misbuf of l2t_misbuf_ctl.sv
2761wire misbuf_mbf_insert_c4; // From misbuf of l2t_misbuf_ctl.sv
2762wire [4:0] misbuf_mbf_insert_mbid_c4; // From misbuf of l2t_misbuf_ctl.sv, BS & SR 11/04/03, MB grows to 32
2763wire mbist_arb_l2d_en; // From mbist of l2t_mbist_ctl.sv
2764wire mbist_arb_l2t_write; // From mbist of l2t_mbist_ctl.sv
2765wire mbist_arb_l2d_write; // From mbist of l2t_mbist_ctl.sv
2766wire mbist_l2d_en; // From mbist of l2t_mbist_ctl.sv
2767wire [8:0] mbist_l2d_index; // From mbist of l2t_mbist_ctl.sv
2768wire [3:0] mbist_l2d_way; // From mbist of l2t_mbist_ctl.sv
2769wire [3:0] mbist_l2d_word_sel; // From mbist of l2t_mbist_ctl.sv
2770wire mbist_l2d_write; // From mbist of l2t_mbist_ctl.sv
2771wire [15:0] mbist_l2t_dec_way; // From mbist of l2t_mbist_ctl.sv
2772wire [15:0] tagd_mbist_l2t_dec_way_buf; // From tagd of l2t_tagd_dp.sv
2773wire [8:0] mbist_l2t_index; // From mbist of l2t_mbist_ctl.sv
2774wire [8:0] tagd_mbist_l2t_index_buf; // From tagd of l2t_tagd_dp.sv
2775wire mbist_l2t_read; // From mbist of l2t_mbist_ctl.sv
2776wire tagd_mbist_l2t_read_buf; // From tagd of l2t_tagd_dp.sv
2777wire [3:0] mbist_l2t_way; // From mbist of l2t_mbist_ctl.sv
2778wire mbist_l2t_write; // From mbist of l2t_mbist_ctl.sv
2779wire tagd_mbist_l2t_write_buf; // From tagd of l2t_tagd_dp.sv
2780wire [8:0] mbist_l2v_index; // From mbist of l2t_mbist_ctl.sv
2781wire mbist_l2v_read; // From mbist of l2t_mbist_ctl.sv
2782wire mbist_l2v_vd; // From mbist of l2t_mbist_ctl.sv
2783wire mbist_l2v_write; // From mbist of l2t_mbist_ctl.sv
2784wire mbist_stop_on_next_fail;// From test_stub of test_stub_bist.v
2785wire [7:0] mbist_write_data; // From mbist of l2t_mbist_ctl.sv
2786wire [7:0] tagd_mbist_write_data_buf; // From tagd of l2t_tagd_dp.sv
2787wire [3:0] csreg_mux1_addr_sel; // From csreg of l2t_csreg_ctl.sv
2788wire [3:0] mux1_h_sel_r0; // From vuad of l2t_vuad_dp.sv
2789wire [3:0] mux1_h_sel_r2; // From vuad of l2t_vuad_dp.sv
2790wire [3:0] mux1_l_sel_r0; // From vuad of l2t_vuad_dp.sv
2791wire [3:0] mux1_l_sel_r2; // From vuad of l2t_vuad_dp.sv
2792wire arb_mux1_mbsel_px1; // From arb of l2t_arb_ctl.sv
2793wire arb_mux1_mbsel_px2; // From arb of l2t_arb_ctl.sv
2794wire [3:0] oqu_mux1_sel_data_c7; // From oqu of l2t_oqu_ctl.sv
2795wire [1:0] csreg_mux1_synd_sel; // From csreg of l2t_csreg_ctl.sv
2796wire [2:0] csreg_mux2_addr_sel; // From csreg of l2t_csreg_ctl.sv
2797wire vuad_mux2_sel_r0; // From vuad of l2t_vuad_dp.sv
2798wire vuad_mux2_sel_r2; // From vuad of l2t_vuad_dp.sv
2799wire [1:0] csreg_mux2_synd_sel; // From csreg of l2t_csreg_ctl.sv
2800//wire arb_mux3_bufsel_px2; // From arb of l2t_arb_ctl.sv
2801wire oqu_mux_csr_sel_c7; // From oqu of l2t_oqu_ctl.sv
2802wire [1:0] vuad_mux_sel; // From vuad of l2t_vuad_dp.sv
2803wire [3:0] oqu_mux_vec_sel_c6; // From oqu of l2t_oqu_ctl.sv
2804wire csr_oneshot_dir_clear_c3; // From csr of l2t_csr_ctl.sv
2805wire oqu_arb_full_px2; // From oqu of l2t_oqu_ctl.sv
2806wire oqu_cerr_ack_c7; // From oqu of l2t_oqu_ctl.sv
2807wire oqu_diag_acc_c8; // From oqu of l2t_oqu_ctl.sv
2808wire oqu_imiss_hit_c8; // From oqu of l2t_oqu_ctl.sv
2809wire oqu_int_ack_c7; // From oqu of l2t_oqu_ctl.sv
2810wire oqu_l2_miss_c7; // From oqu of l2t_oqu_ctl.sv
2811wire oqu_pf_ack_c7; // From oqu of l2t_oqu_ctl.sv
2812wire oqu_rmo_st_c7; // From oqu of l2t_oqu_ctl.sv
2813wire [3:0] oqu_rqtyp_rtn_c7; // From oqu of l2t_oqu_ctl.sv
2814wire oqu_st_complete_c7; // From oqu of l2t_oqu_ctl.sv
2815wire oqu_uerr_ack_c7; // From oqu of l2t_oqu_ctl.sv
2816wire [5:0] oque_tid_c8; // From oque of l2t_oque_dp.sv, BS and SR 11/12/03 N2 Xbar Packet format change
2817wire rdmat_or_rdmat_valid; // From rdmat of l2t_rdmat_ctl.sv
2818wire [2:0] oqu_out_mux1_sel_c7; // From oqu of l2t_oqu_ctl.sv
2819wire [2:0] oqu_out_mux2_sel_c7; // From oqu of l2t_oqu_ctl.sv
2820
2821wire vuadpm_vd_ue_c4;
2822wire vuadpm_ua_ue_c4;
2823
2824wire iqu_pcx_l2t_atm_px2_p; // From iqu of l2t_iqu_ctl.sv
2825wire [4:0] vuad_rd_addr1_r0; // From vuad of l2t_vuad_dp.sv
2826wire [4:0] vuad_rd_addr1_r1; // From vuad of l2t_vuad_dp.sv
2827wire [4:0] vuad_rd_addr1_r2; // From vuad of l2t_vuad_dp.sv
2828wire [4:0] vuad_rd_addr1_r3; // From vuad of l2t_vuad_dp.sv
2829wire [4:0] vuad_rd_addr2_r0; // From vuad of l2t_vuad_dp.sv
2830wire [4:0] vuad_rd_addr2_r1; // From vuad of l2t_vuad_dp.sv
2831wire [4:0] vuad_rd_addr2_r2; // From vuad of l2t_vuad_dp.sv
2832wire [4:0] vuad_rd_addr2_r3; // From vuad of l2t_vuad_dp.sv
2833wire vuad_rd_addr_sel_r0; // From vuad of l2t_vuad_dp.sv
2834wire vuad_rd_addr_sel_r1; // From vuad of l2t_vuad_dp.sv
2835wire vuad_rd_addr_sel_r2; // From vuad of l2t_vuad_dp.sv
2836wire vuad_rd_addr_sel_r3; // From vuad of l2t_vuad_dp.sv
2837wire vuad_rd_en_r0; // From vuad of l2t_vuad_dp.sv
2838wire vuad_rd_en_r1; // From vuad of l2t_vuad_dp.sv
2839wire vuad_rd_en_r2; // From vuad of l2t_vuad_dp.sv
2840wire vuad_rd_en_r3; // From vuad of l2t_vuad_dp.sv
2841wire [1:0] snp_rdmad_wr_entry_s2; // From snp of l2t_snp_ctl.sv
2842wire [39:6] arbadr_rdmard_addr_c12; // From arbadr of l2t_arbadr_dp.sv
2843wire rdmat_rdmard_cerr_c12; // From rdmat of l2t_rdmat_ctl.sv
2844wire rdmat_rdmard_uerr_c12; // From rdmat of l2t_rdmat_ctl.sv
2845wire [3:0] rdmat_pick_vec; // From rdmat of l2t_rdmat_ctl.sv
2846wire [1:0] rdmat_wr_entry_s1; // From rdmat of l2t_rdmat_ctl.sv
2847wire rdmat_hit_unqual_c2; // From rdmat of l2t_rdmat_ctl.sv
2848wire [4:0] rdmat_misbuf_dep_mbid;// From rdmat of l2t_rdmat_ctl.sv, BS & SR 11/04/03, MB grows to 32
2849wire rdmat_misbuf_dep_rdy_en;// From rdmat of l2t_rdmat_ctl.sv
2850wire [3:0] wbuf_reset_rdmat_vld; // From wbuf of l2t_wbuf_ctl.sv
2851wire [127:0] retbuf_ret_data_c7; // From retbuf2 of l2t_retbuf_dp.sv
2852wire [127:0] decc_ret_data_c8; // From decc of l2t_decc_dp.sv
2853wire [38:0] decc_ret_diag_data_c7; // From decc of l2t_decc_dp.sv
2854wire [27:0] retbuf_ret_ecc_c7; // From retbuf2 of l2t_retbuf_dp.sv
2855wire [2:0] deccck_ret_err_c8; // From deccck of l2t_deccck_ctl.sv
2856wire [15:0] tag_l2b_fbwr_wen_r2; // From tag of l2t_tag_ctl.sv
2857wire [3:0] tag_scrub_addr_way; // From tag of l2t_tag_ctl.sv
2858wire oqu_sel_array_out_l; // From oqu of l2t_oqu_ctl.sv
2859wire iqu_sel_c1reg_over_iqarray; // From iqu of l2t_iqu_ctl.sv
2860wire arb_sel_c2_stall_idx_c1; // From arb of l2t_arb_ctl.sv
2861wire arb_sel_deccck_addr_px2; // From arb of l2t_arb_ctl.sv
2862wire arb_sel_deccck_or_bist_idx; // From arb of l2t_arb_ctl.sv
2863wire vuaddp_sel_diag0_data_wr_c3; // From vuaddp of l2t_vuaddp_ctl.sv
2864wire vuaddp_sel_diag1_data_wr_c3; // From vuaddp of l2t_vuaddp_ctl.sv
2865wire arb_sel_diag_addr_px2; // From arb of l2t_arb_ctl.sv
2866wire arb_sel_diag_tag_addr_px2; // From arb of l2t_arb_ctl.sv
2867wire oqu_sel_inval_c7; // From oqu of l2t_oqu_ctl.sv
2868wire arb_sel_lkup_stalled_tag_px2;// From arb of l2t_arb_ctl.sv
2869wire [3:0] oqu_sel_mux1_c6; // From oqu of l2t_oqu_ctl.sv
2870wire [3:0] oqu_sel_mux2_c6; // From oqu of l2t_oqu_ctl.sv
2871wire oqu_sel_mux3_c6; // From oqu of l2t_oqu_ctl.sv
2872wire tag_sel_rdma_inval_vec_c5; // From tag of l2t_tag_ctl.sv
2873wire arb_sel_tecc_addr_px2; // From arb of l2t_arb_ctl.sv
2874wire vuaddp_sel_ua_wr_data_byp; // From vuaddp of l2t_vuaddp_ctl.sv
2875wire vuaddp_sel_vd_wr_data_byp; // From vuaddp of l2t_vuaddp_ctl.sv
2876wire arb_sel_vuad_bist_px2; // From arb of l2t_arb_ctl.sv
2877wire arb_sel_way_px2; // From arb of l2t_arb_ctl.sv
2878wire [3:0] wbuf_set_rdmat_acked; // From wbuf of l2t_wbuf_ctl.sv
2879wire [1:0] arbdec_size_field_c8; // From arbdec of l2t_arbdec_dp.sv
2880wire snp_data1_wen0_s2; // From snp of l2t_snp_ctl.sv
2881wire snp_data1_wen1_s2; // From snp of l2t_snp_ctl.sv
2882wire snp_data2_wen0_s3; // From snp of l2t_snp_ctl.sv
2883wire snp_data2_wen1_s3; // From snp of l2t_snp_ctl.sv
2884wire snp_hdr1_wen0_s0; // From snp of l2t_snp_ctl.sv
2885wire snp_hdr1_wen1_s0; // From snp of l2t_snp_ctl.sv
2886wire snp_hdr2_wen0_s1; // From snp of l2t_snp_ctl.sv
2887wire snp_hdr2_wen1_s1; // From snp of l2t_snp_ctl.sv
2888wire snp_rd_ptr; // From snp of l2t_snp_ctl.sv
2889wire snp_wr_ptr; // From snp of l2t_snp_ctl.sv
2890wire snpd_rq_winv_s1; // From snpd of l2t_snpd_dp.sv
2891wire snp_snpq_arb_vld_px1; // From snp of l2t_snp_ctl.sv
2892wire [39:0] snpd_snpq_arbdp_addr_px2; // From snpd of l2t_snpd_dp.sv
2893wire [6:0] snpd_ecc_px2; // From snpd of l2t_snpd_dp.sv
2894wire [63:0] snpd_snpq_arbdp_data_px2; // From snpd of l2t_snpd_dp.sv
2895wire [`JBI_HDR_SZ_LESS1:0] snpd_snpq_arbdp_inst_px2; // From snpd of l2t_snpd_dp.sv
2896wire tag_spc_rd_cond_c3; // From tag of l2t_tag_ctl.sv
2897//wire vuaddp_st_to_data_array_c3; // From vuaddp of l2t_vuaddp_ctl.sv
2898wire arb_store_err_c8; // From arb of l2t_arb_ctl.sv
2899wire oqu_str_ld_hit_c7; // From oqu of l2t_oqu_ctl.sv
2900wire oqu_strst_ack_c7; // From oqu of l2t_oqu_ctl.sv
2901wire tagdp_tag_error_c8; // From tagdp of l2t_tagdp_ctl.sv
2902wire [15:0] tagl_parity_c2; // From tagl_1 of l2t_tagl_dp.sv, ...
2903wire [3:0] tagdp_quad_muxsel_c3; // From tagdp of l2t_tagdp_ctl.sv
2904wire [`TAG_WIDTH_LESS1:0] tagl_quad0_c3; // From tagl_1 of l2t_tagl_dp.sv
2905wire [`TAG_WIDTH_LESS1:0] tagl_quad1_c3; // From tagl_1 of l2t_tagl_dp.sv
2906wire [`TAG_WIDTH_LESS1:0] tagl_quad2_c3; // From tagl_2 of l2t_tagl_dp.sv
2907wire [`TAG_WIDTH_LESS1:0] tagl_quad3_c3; // From tagl_2 of l2t_tagl_dp.sv
2908wire [27:0] tag_way0_tag_c2; // From tag of lib_r_l2t_cust.sv
2909wire [27:0] tag_way10_tag_c2; // From tag of lib_r_l2t_cust.sv
2910wire [27:0] tag_way11_tag_c2; // From tag of lib_r_l2t_cust.sv
2911wire [27:0] tag_way1_tag_c2; // From tag of lib_r_l2t_cust.sv
2912wire [27:0] tag_way2_tag_c2; // From tag of lib_r_l2t_cust.sv
2913wire [27:0] tag_way3_tag_c2; // From tag of lib_r_l2t_cust.sv
2914wire [27:0] tag_way4_tag_c2; // From tag of lib_r_l2t_cust.sv
2915wire [27:0] tag_way5_tag_c2; // From tag of lib_r_l2t_cust.sv
2916wire [27:0] tag_way6_tag_c2; // From tag of lib_r_l2t_cust.sv
2917wire [27:0] tag_way7_tag_c2; // From tag of lib_r_l2t_cust.sv
2918wire [27:0] tag_way8_tag_c2; // From tag of lib_r_l2t_cust.sv
2919wire [27:0] tag_way9_tag_c2; // From tag of lib_r_l2t_cust.sv
2920wire [15:0] tag_way_sel_c2; // From tag of lib_r_l2t_cust.sv
2921wire [27:0] arbadr_tag_wrdata_px2; // From arbadr of l2t_arbadr_dp.sv
2922wire [27:0] tagd_wrdata_px2_buf; // From tagd of l2t_tagd_dp.sv
2923wire tag_bsc_rd_vld_c7; // From tag of l2t_tag_ctl.sv
2924wire tag_cerr_ack_c5; // From tag of l2t_tag_ctl.sv
2925wire tag_deccck_addr3_c7; // From tag of l2t_tag_ctl.sv
2926wire tag_deccck_data_sel_c8;// From tag of l2t_tag_ctl.sv
2927wire tag_fwd_req_ld_c6; // From tag of l2t_tag_ctl.sv
2928wire tag_fwd_req_ret_c5; // From tag of l2t_tag_ctl.sv
2929wire tag_hit_c3; // From tag of l2t_tag_ctl.sv
2930wire tag_hit_c5; // From tag of l2t_tag_ctl.sv
2931wire tag_hit_l2orfb_c3; // From tag of l2t_tag_ctl.sv
2932wire tag_hit_not_comp_c3; // From tag of l2t_tag_ctl.sv
2933wire tag_hit_unqual_c2; // From tag of l2t_tag_ctl.sv
2934wire [15:0] tag_hit_way_vld_c3; // From tag of l2t_tag_ctl.sv
2935wire tag_imiss_hit_c5; // From tag of l2t_tag_ctl.sv
2936wire tag_inc_rdma_cnt_c4; // From tag of l2t_tag_ctl.sv
2937wire tag_inst_mb_c5; // From tag of l2t_tag_ctl.sv
2938wire tag_int_ack_c5; // From tag of l2t_tag_ctl.sv
2939wire tag_siu_req_en_c52; // From tag of l2t_tag_ctl.sv
2940wire tag_ld_hit_c5; // From tag of l2t_tag_ctl.sv
2941wire [3:0] tag_lru_way_c4; // From tag of l2t_tag_ctl.sv
2942wire tag_misbuf_par_err_c3;// From tag of l2t_tag_ctl.sv
2943wire tag_miss_unqual_c2; // From tag of l2t_tag_ctl.sv
2944wire tag_nonmem_comp_c6; // From tag of l2t_tag_ctl.sv
2945wire tag_rd64_complete_c11;// From tag of l2t_tag_ctl.sv
2946wire tag_rdma_ev_en_c4; // From tag of l2t_tag_ctl.sv
2947wire tag_rdma_gate_off_c2;// From tag of l2t_tag_ctl.sv
2948wire tag_rdma_vld_px0_p; // From tag of l2t_tag_ctl.sv
2949wire tag_rdma_vld_px1; // From tag of l2t_tag_ctl.sv
2950wire tag_rdma_wr_comp_c4; // From tag of l2t_tag_ctl.sv
2951wire tag_rmo_st_ack_c5; // From tag of l2t_tag_ctl.sv
2952wire tag_scrub_rd_vld_c7; // From tag of l2t_tag_ctl.sv
2953wire tag_set_rdma_reg_vld_c4;// From tag of l2t_tag_ctl.sv
2954wire tag_spc_rd_vld_c6; // From tag of l2t_tag_ctl.sv
2955wire tag_st_ack_c5; // From tag of l2t_tag_ctl.sv
2956wire tag_st_req_c5; // From tag of l2t_tag_ctl.sv
2957wire tag_st_to_data_array_c3;// From tag of l2t_tag_ctl.sv
2958wire tag_store_inst_c5; // From tag of l2t_tag_ctl.sv
2959wire tag_strst_ack_c5; // From tag of l2t_tag_ctl.sv
2960wire tag_uerr_ack_c5; // From tag of l2t_tag_ctl.sv
2961wire tagdp_arb_par_err_c3;// From tagdp of l2t_tagdp_ctl.sv
2962wire [`TAG_WIDTH_LESS1:0] tagd_diag_data_c7; // From tagd of l2t_tagd_dp.sv
2963wire [`TAG_WIDTH_LESS1:0] tagd_evict_tag_c4; // From tagd of l2t_tagd_dp.sv
2964wire tagdp_misbuf_par_err_c3; // From tagdp of l2t_tagdp_ctl.sv
2965wire tagdp_tag_par_err_c3;// From tagdp of l2t_tagdp_ctl.sv
2966wire [3:0] tagdp_quad0_muxsel_c3; // From tagdp of l2t_tagdp_ctl.sv
2967wire [3:0] tagdp_quad1_muxsel_c3; // From tagdp of l2t_tagdp_ctl.sv
2968wire [3:0] tagdp_quad2_muxsel_c3; // From tagdp of l2t_tagdp_ctl.sv
2969wire [3:0] tagdp_quad3_muxsel_c3; // From tagdp of l2t_tagdp_ctl.sv
2970wire tag_uerr_ack_tmp_c4; // From tag of l2t_tag_ctl.sv
2971wire [77:0] vuad_array_rd_data_c1; // From io_left of l2t_vuadio_dp.sv, ...
2972wire [77:0] vlddir_vuad_array_wr_data_c4; // From vlddir of l2t_vlddir_dp.sv, ...
2973wire vuaddp_vuad_array_wr_en0_c4; // From vuaddp of l2t_vuaddp_ctl.sv
2974wire vuaddp_vuad_array_wr_en1_c4; // From vuaddp of l2t_vuaddp_ctl.sv
2975wire [15:0] usaloc_vuad_alloc_c2; // From usaloc of l2t_usaloc_dp.sv
2976wire [15:0] usaloc_vuad_used_c2; // From usaloc of l2t_usaloc_dp.sv
2977wire [15:0] vlddir_vuad_valid_c2; // From vlddir of l2t_vlddir_dp.sv
2978wire vuaddp_vuad_error_c8; // From vuaddp of l2t_vuaddp_ctl.sv
2979wire [8:0] evctag_vuad_idx_c3; // From evctag of l2t_evctag_dp.sv
2980wire [8:0] vuaddp_vuad_idx_c4; // From vuaddp of l2t_vuaddp_ctl.sv
2981wire vuaddp_vuad_sel_c2; // From vuaddp of l2t_vuaddp_ctl.sv
2982wire vuaddp_vuad_sel_c2_d1; // From vuaddp of l2t_vuaddp_ctl.sv
2983wire vuaddp_vuad_sel_c4; // From vuaddp of l2t_vuaddp_ctl.sv
2984wire vuaddp_vuad_sel_rd; // From vuaddp of l2t_vuaddp_ctl.sv
2985wire [6:0] usaloc_ua_synd_c9;
2986wire [6:0] vlddir_vd_synd_c9;
2987
2988wire vuaddp_vuad_tagd_sel_c2_d1; // From vuaddp of l2t_vuaddp_ctl.sv
2989wire arb_vuadctl_no_bypass_px2; // From arb of l2t_arb_ctl.sv
2990wire wbuf_wb_or_rdma_wr_req_en; // From wbuf of l2t_wbuf_ctl.sv
2991wire wbuf_arb_full_px1; // From wbuf of l2t_wbuf_ctl.sv
2992wire wbuf_hit_unqual_c2; // From wbuf of l2t_wbuf_ctl.sv
2993wire [4:0] wbuf_misbuf_dep_mbid; // From wbuf of l2t_wbuf_ctl.sv, BS & SR 11/04/03, MB grows to 32
2994wire wbuf_misbuf_dep_rdy_en; // From wbuf of l2t_wbuf_ctl.sv
2995wire wbuf_wr_addr_sel; // From wbuf of l2t_wbuf_ctl.sv
2996wire [3:0] vuad_word_en_r0; // From vuad of l2t_vuad_dp.sv
2997wire [3:0] vuad_word_en_r1; // From vuad of l2t_vuad_dp.sv
2998wire [3:0] vuad_word_en_r2; // From vuad of l2t_vuad_dp.sv
2999wire [3:0] vuad_word_en_r3; // From vuad of l2t_vuad_dp.sv
3000wire arbdat_word_lower_cmp_c8; // From arbdat of l2t_arbdat_dp.sv
3001wire arbdat_word_upper_cmp_c8; // From arbdat of l2t_arbdat_dp.sv
3002wire vuaddp_wr64_inst_c3; // From vuaddp of l2t_vuaddp_ctl.sv
3003wire arb_wr8_inst_no_ctrue_c1; // From arb of l2t_arb_ctl.sv
3004wire [4:0] vuad_wr_addr_r0; // From vuad of l2t_vuad_dp.sv
3005wire [4:0] vuad_wr_addr_r1; // From vuad of l2t_vuad_dp.sv
3006wire [4:0] vuad_wr_addr_r2; // From vuad of l2t_vuad_dp.sv
3007wire [4:0] vuad_wr_addr_r3; // From vuad of l2t_vuad_dp.sv
3008wire [4:0] dirrep_wr_dc_dir_entry_c4; // From dirrep of l2t_dirrep_ctl.sv, BS and SR 11/18/03 Reverse Directory change
3009wire vuad_wr_en_r0c0; // From vuad of l2t_vuad_dp.sv
3010wire vuad_wr_en_r0c1; // From vuad of l2t_vuad_dp.sv
3011wire vuad_wr_en_r1c0; // From vuad of l2t_vuad_dp.sv
3012wire vuad_wr_en_r1c1; // From vuad of l2t_vuad_dp.sv
3013wire vuad_wr_en_r2c0; // From vuad of l2t_vuad_dp.sv
3014wire vuad_wr_en_r2c1; // From vuad of l2t_vuad_dp.sv
3015wire vuad_wr_en_r3c0; // From vuad of l2t_vuad_dp.sv
3016wire vuad_wr_en_r3c1; // From vuad of l2t_vuad_dp.sv
3017//wire csreg_wr_enable_async_c9; // From csreg of l2t_csreg_ctl.sv
3018wire csreg_wr_enable_tid_c9; // From csreg of l2t_csreg_ctl.sv
3019wire [4:0] dirrep_wr_ic_dir_entry_c4; // From dirrep of l2t_dirrep_ctl.sv, BS and SR 11/18/03 Reverse Directory change
3020wire [6:0] mb0_dcache_index_unused;
3021wire [1:0] mb0_dcache_way_unused;
3022wire [7:0] mb0_icache_index_unused;
3023wire [1:0] mb0_icache_way_unused;
3024wire [7:0] mb0_write_data_unused;
3025
3026
3027
3028clkgen_l2t_cmp l2t_clk_header
3029 (
3030 .array_wr_inhibit(array_wr_inhibit),
3031 .tcu_wr_inhibit (tcu_array_wr_inhibit),
3032 .tcu_atpg_mode(tcu_atpg_mode),
3033 .scan_in(l2t_clk_header_scanin),
3034 .scan_out(l2t_clk_header_scanout),
3035 .l2clk (l2clk ),
3036 .aclk (aclk ),
3037 .bclk (bclk ),
3038 .pce_ov (ce_ovrd ),
3039 .wmr_protect (wmr_protect ),
3040 .wmr_ (wmr_l ),
3041 .cluster_arst_l (cluster_arst_l ),
3042 .ccu_serdes_dtm (1'b0 ),
3043 .aclk_wmr (aclk_wmr ),
3044 .por_ (por_l ),
3045 .cmp_slow_sync_en (cmp_io_sync_en ),
3046 .slow_cmp_sync_en (io_cmp_sync_en ),
3047 .tcu_clk_stop (tcu_clk_stop ),
3048 .tcu_pce_ov (tcu_pce_ov ),
3049 .rst_wmr_protect (rst_wmr_protect ),
3050 .rst_wmr_ (rst_wmr_ ),
3051 .rst_por_ (rst_por_ ),
3052 .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en ),
3053 .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en ),
3054 .tcu_div_bypass (1'b0 ),
3055 .ccu_div_ph (1'b1 ),
3056 .cluster_div_en (1'b0 ),
3057 .gclk (gclk ),
3058 .clk_ext (1'b0 ),
3059 .tcu_aclk (tcu_aclk ),
3060 .tcu_bclk (tcu_bclk ),
3061 .scan_en (tcu_scan_en )
3062 );
3063
3064
3065
3066l2t_vuad_ctl vuad(
3067 .tcu_pce_ov(ce_ovrd),
3068 .tcu_aclk(aclk),
3069 .tcu_bclk(bclk),
3070 .tcu_scan_en(tcu_scan_en),
3071 .tcu_clk_stop(1'b0),
3072 // Outputs
3073 .vuad_rd_addr1_r0(vuad_rd_addr1_r0[4:0]),
3074 .vuad_rd_addr2_r0(vuad_rd_addr2_r0[4:0]),
3075 .vuad_rd_addr_sel_r0(vuad_rd_addr_sel_r0),
3076 .vuad_wr_addr_r0(vuad_wr_addr_r0[4:0]),
3077 .vuad_word_en_r0(vuad_word_en_r0[3:0]),
3078 .vuad_wr_en_r0c0(vuad_wr_en_r0c0),
3079 .vuad_wr_en_r0c1(vuad_wr_en_r0c1),
3080 .vuad_mux1_h_sel_r0(mux1_h_sel_r0[3:0]),
3081 .vuad_mux1_l_sel_r0(mux1_l_sel_r0[3:0]),
3082 .vuad_mux2_sel_r0(vuad_mux2_sel_r0),
3083 .vuad_rd_en_r0 (vuad_rd_en_r0),
3084 .vuad_rd_addr1_r1(vuad_rd_addr1_r1[4:0]),
3085 .vuad_rd_addr2_r1(vuad_rd_addr2_r1[4:0]),
3086 .vuad_rd_addr_sel_r1(vuad_rd_addr_sel_r1),
3087 .vuad_wr_addr_r1(vuad_wr_addr_r1[4:0]),
3088 .vuad_word_en_r1(vuad_word_en_r1[3:0]),
3089 .vuad_wr_en_r1c0(vuad_wr_en_r1c0),
3090 .vuad_wr_en_r1c1(vuad_wr_en_r1c1),
3091 .vuad_rd_en_r1 (vuad_rd_en_r1),
3092 .vuad_rd_addr1_r2(vuad_rd_addr1_r2[4:0]),
3093 .vuad_rd_addr2_r2(vuad_rd_addr2_r2[4:0]),
3094 .vuad_rd_addr_sel_r2(vuad_rd_addr_sel_r2),
3095 .vuad_wr_addr_r2(vuad_wr_addr_r2[4:0]),
3096 .vuad_word_en_r2(vuad_word_en_r2[3:0]),
3097 .vuad_wr_en_r2c0(vuad_wr_en_r2c0),
3098 .vuad_wr_en_r2c1(vuad_wr_en_r2c1),
3099 .vuad_mux1_h_sel_r2(mux1_h_sel_r2[3:0]),
3100 .vuad_mux1_l_sel_r2(mux1_l_sel_r2[3:0]),
3101 .vuad_mux2_sel_r2(vuad_mux2_sel_r2),
3102 .vuad_rd_en_r2 (vuad_rd_en_r2),
3103 .vuad_rd_addr1_r3(vuad_rd_addr1_r3[4:0]),
3104 .vuad_rd_addr2_r3(vuad_rd_addr2_r3[4:0]),
3105 .vuad_rd_addr_sel_r3(vuad_rd_addr_sel_r3),
3106 .vuad_wr_addr_r3(vuad_wr_addr_r3[4:0]),
3107 .vuad_word_en_r3(vuad_word_en_r3[3:0]),
3108 .vuad_wr_en_r3c0(vuad_wr_en_r3c0),
3109 .vuad_wr_en_r3c1(vuad_wr_en_r3c1),
3110 .vuad_rd_en_r3 (vuad_rd_en_r3),
3111 .vuad_mux_sel (vuad_mux_sel[1:0]),
3112 // Inputs
3113 .rd_addr1 (arbadr_arbdp_vuad_idx1_px2[8:0]), // Templated
3114 .rd_addr2 (arbadr_arbdp_vuad_idx2_px2[8:0]), // Templated
3115 .rd_addr_sel(arb_vuad_idx2_sel_px2_n), // Templated
3116 .wr_addr (vuaddp_vuad_idx_c4[8:0]), // Templated
3117 .wr_en0 (vuaddp_vuad_array_wr_en0_c4), // Templated
3118 .wr_en1 (vuaddp_vuad_array_wr_en1_c4), // Templated
3119 .array_rd_en(arb_vuad_acc_px2), // Templated
3120 .scan_in(vuad_scanin),
3121 .scan_out(vuad_scanout),
3122 .l2clk (l2clk),
3123 .vuaddp_vuad_sel_c2(vuaddp_vuad_sel_c2),
3124 .vuaddp_vuad_sel_c2_d1(vuaddp_vuad_sel_c2_d1),
3125 .vuaddp_vuad_sel_c4(vuaddp_vuad_sel_c4),
3126 .vuaddp_vuad_sel_rd(vuaddp_vuad_sel_rd),
3127 .vuaddp_vuad_tagd_sel_c2_d1(vuaddp_vuad_tagd_sel_c2_d1),
3128 //.vuaddp_st_to_data_array_c3(vuaddp_st_to_data_array_c3),
3129 .vuaddp_wr64_inst_c3(vuaddp_wr64_inst_c3),
3130// .vuaddp_vuad_evict_c3(vuaddp_vuad_evict_c3),
3131 .vuaddp_alloc_set_cond_c3(alloc_set_cond_c3),
3132 .vuaddp_alloc_rst_cond_c3(alloc_rst_cond_c3),
3133 .vuaddp_vuad_error_c8(vuaddp_vuad_error_c8),
3134 // .vuaddp_hit_wayvld_c3(vuaddp_hit_wayvld_c3[15:0]),
3135 .vuaddp_fill_way_c3(vuaddp_fill_way_c3[15:0]),
3136 // .vuaddp_lru_way_c3(vuaddp_lru_way_c3[15:0]),
3137 .vuaddp_bistordiag_wr_vd_c4(vuaddp_bistordiag_wr_vd_c4),
3138 .vuaddp_bistordiag_wr_ua_c4(vuaddp_bistordiag_wr_ua_c4),
3139 .vuaddp_sel_ua_wr_data_byp(vuaddp_sel_ua_wr_data_byp),
3140 .vuaddp_sel_vd_wr_data_byp(vuaddp_sel_vd_wr_data_byp),
3141 .vuaddp_sel_diag0_data_wr_c3(vuaddp_sel_diag0_data_wr_c3),
3142 .vuaddp_sel_diag1_data_wr_c3(vuaddp_sel_diag1_data_wr_c3),
3143 .vuaddp_vuad_array_wr_en0_c4(vuaddp_vuad_array_wr_en0_c4),
3144 .vuaddp_vuad_array_wr_en1_c4(vuaddp_vuad_array_wr_en1_c4),
3145 .vuaddp_vuad_idx_c4(vuaddp_vuad_idx_c4[8:0]),
3146 // Inputs
3147 .bist_vuad_idx_c3(mbist_l2v_index[8:0]), // Templated
3148 .evctag_vuad_idx_c3(evctag_vuad_idx_c3[8:0]),
3149 .bist_wr_vd_c3(mbist_l2v_vd), // Templated
3150 // .tag_hit_way_vld_c3(tag_hit_way_vld_c3[15:0]),
3151 // .tagdp_lru_way_sel_c3(tagdp_lru_way_sel_c3[15:0]),
3152 // .tag_st_to_data_array_c3(tag_st_to_data_array_c3),
3153 .arb_decdp_wr64_inst_c2(arb_decdp_wr64_inst_c2),
3154// .tagdp_evict_c3 (tagdp_evict_c3),
3155 .arb_acc_vd_c2(arb_acc_vd_c2),
3156 .arb_acc_ua_c2(arb_acc_ua_c2),
3157 .arbadr_idx_c1c2comp_c1_n(arbadr_idx_c1c2comp_c1_n),
3158 .arbadr_idx_c1c3comp_c1_n(arbadr_idx_c1c3comp_c1_n),
3159 .arbadr_idx_c1c4comp_c1_n(arbadr_idx_c1c4comp_c1_n),
3160 .arbadr_idx_c1c5comp_c1_n(arbadr_idx_c1c5comp_c1_n),
3161 .arb_decdp_inst_int_c1(arb_decdp_inst_int_c1),
3162 .csr_l2_bypass_mode_on(csr_vuad_l2off), // Templated
3163 .arb_inst_diag_c1(arb_inst_diag_c1),
3164 .bist_vuad_wr_en(mbist_l2v_write), // Templated
3165 .arb_inst_vld_c2(arb_inst_vld_c2),
3166 .arb_inst_l2vuad_vld_c3(arb_inst_l2vuad_vld_c3),
3167 .arb_decdp_st_inst_c3(arb_decdp_st_inst_c3),
3168 .arbdec_arbdp_inst_fb_c2(arbdec_arbdp_inst_fb_c2),
3169 .vuadpm_vd_ue_c4(vuadpm_vd_ue_c4), // vuad ecc change
3170 .vuadpm_ua_ue_c4(vuadpm_ua_ue_c4), // vuad ecc change
3171 .arbdec_arbdp_inst_way_c2(arbdec_arbdp_inst_way_c2[3:0]),
3172 .arb_arbdp_vuadctl_pst_no_ctrue_c2(arb_arbdp_vuadctl_pst_no_ctrue_c2),
3173 .arb_decdp_cas1_inst_c2(arb_decdp_cas1_inst_c2),
3174 .arb_arbdp_pst_with_ctrue_c2(arb_arbdp_pst_with_ctrue_c2),
3175 .arb_decdp_cas2_inst_c2(arb_decdp_cas2_inst_c2),
3176 .arbdec_arbdp_inst_mb_c2(arbdec_arbdp_inst_mb_c2),
3177 .arb_vuadctl_no_bypass_px2(arb_vuadctl_no_bypass_px2),
3178 .mbist_run(mbist_run),
3179 .vuad_usaloc_mux_used_and_alloc_comb_sel0(vuad_usaloc_mux_used_and_alloc_comb_sel0),
3180 .vuad_usaloc_mux_used_and_alloc_comb_sel1(vuad_usaloc_mux_used_and_alloc_comb_sel1),
3181 .vuad_usaloc_mux_used_and_alloc_comb_sel2(vuad_usaloc_mux_used_and_alloc_comb_sel2),
3182 .vuad_usaloc_mux_used_and_alloc_comb_sel3(vuad_usaloc_mux_used_and_alloc_comb_sel3),
3183 .vuad_usaloc_mux_used_and_alloc_comb_sel4(vuad_usaloc_mux_used_and_alloc_comb_sel4),
3184 .vuad_usaloc_mux_used_and_alloc_comb_sel5(vuad_usaloc_mux_used_and_alloc_comb_sel5),
3185 .mux_valid_dirty_c1_sel0(mux_valid_dirty_c1_sel0),
3186 .mux_valid_dirty_c1_sel1(mux_valid_dirty_c1_sel1),
3187 .mux_valid_dirty_c1_sel2(mux_valid_dirty_c1_sel2)
3188 );
3189
3190
3191
3192
3193
3194
3195
3196l2t_vuadpm_dp vuadpm(
3197 .tcu_pce_ov(ce_ovrd),
3198 .tcu_aclk(aclk),
3199 .tcu_bclk(bclk),
3200 .tcu_scan_en(tcu_scan_en),
3201 .tcu_clk_stop(1'b0),
3202 /*AUTOINST*/
3203 // Outputs
3204 .vuadpm_vuad_diag_data_c7(vuad_diag_data_c7[38:0]),
3205 .vuadpm_bistordiag_ua_data(vuadpm_bistordiag_ua_data[38:0]),
3206 .vuadpm_bistordiag_vd_data(vuadpm_bistordiag_vd_data[38:0]),
3207 .vlddir_vd_synd_c2 (vlddir_vd_synd_c2[5:0]),//BSandSR VUAD ECC Change 8/9/04
3208 .vlddir_vd_ce_c2(vlddir_vd_ce_c2[1]),
3209 // New
3210 .usaloc_ua_synd_c9 (usaloc_ua_synd_c9[6:0]),
3211 .vlddir_vd_synd_c9 (vlddir_vd_synd_c9[6:0]),
3212 .vuadpm_vd_ue_c4(vuadpm_vd_ue_c4),
3213 .vuadpm_ua_ue_c4(vuadpm_ua_ue_c4),
3214 .bist_vuad_rd_en_px1(mbist_l2v_read),
3215 // Inputs
3216 .scan_in(vuadpm_scanin),
3217 .scan_out(vuadpm_scanout),
3218 .l2clk (l2clk),
3219 .usaloc_diag_rd_ua_out(usaloc_diag_rd_ua_out[38:0]),
3220 .vlddir_diag_rd_vd_out(vlddir_diag_rd_vd_out[38:0]),
3221 .arb_acc_ua_c2(arb_acc_ua_c2),
3222 .arbdat_arbdata_wr_data_c2(arbdata_wr_data_c2[38:0]),
3223 .bist_vuad_data_in(mbist_write_data[7:0]), // Templated
3224 .vuaddp_sel_diag1_data_wr_c3(vuaddp_sel_diag1_data_wr_c3),
3225 .vuaddp_sel_diag0_data_wr_c3(vuaddp_sel_diag0_data_wr_c3),
3226 .usaloc_ua_ue_c2(usaloc_ua_ue_c2),
3227 .vlddir_vd_ue_c2(vlddir_vd_ue_c2),
3228 .usaloc_ua_synd_c2(usaloc_ua_synd_c2[5:0]),
3229 .usaloc_ua_ce_c2(usaloc_ua_ce_c2),
3230 .mbist_write_data(mbist_write_data[7:0]),
3231 .mbist_l2vuad_fail(mbist_l2vuad_fail));
3232
3233l2t_vlddir_dp vlddir(
3234 .tcu_pce_ov(ce_ovrd),
3235 .tcu_aclk(aclk),
3236 .tcu_bclk(bclk),
3237 .tcu_scan_en(tcu_scan_en),
3238 .tcu_clk_stop(1'b0),
3239 // Outputs
3240 .vlddir_vuad_array_wr_data_c4(vlddir_vuad_array_wr_data_c4[38:0]),
3241 .vlddir_dirty_evict_c3 (vlddir_dirty_evict_c3),
3242 .vlddir_vuad_valid_c2 (vlddir_vuad_valid_c2[15:0]),
3243 .vlddir_diag_rd_vd_out (vlddir_diag_rd_vd_out[38:0]),
3244 .vlddir_vd_ue_c2 (vlddir_vd_ue_c2), // BS and SR VUAD ECC Change 8/9/04
3245 .vlddir_vd_ce_c2 (vlddir_vd_ce_c2[1:0]), // BS and SR VUAD ECC Change 8/9/04
3246 .vlddir_vd_synd_c2 (vlddir_vd_synd_c2[5:0]),//BSandSR VUAD ECC Change 8/9/04
3247 // Inputs
3248 .arb_vuad_ce_err_c3 (usaloc_vlddir_arb_vuad_ce_err_c3_rep1_v1),
3249 .tag_hit_way_vld_c3(tag_hit_way_vld_c3_rep2[15:0]),
3250 .scan_in(vlddir_scanin),
3251 .scan_out(vlddir_scanout),
3252 .l2clk (l2clk),
3253// .vuaddp_lru_way_c3 (vuaddp_lru_way_c3[15:0]),
3254 .vuaddp_lru_way_c3 (tagdp_lru_way_sel_c3_rep2[15:0]),
3255 .vuaddp_fill_way_c3 (vuaddp_fill_way_c3[15:0]),
3256 //.vuaddp_hit_wayvld_c3 (vuaddp_hit_wayvld_c3[15:0]),
3257 .vuadpm_bistordiag_vd_data (vuadpm_bistordiag_vd_data[38:0]),
3258 .vuaddp_vuad_evict_c3 (tagdp_evict_c3_2_rep1),
3259 .vuaddp_wr64_inst_c3 (vuaddp_wr64_inst_c3),
3260 .vuaddp_st_to_data_array_c3(tag_st_to_data_array_c3_rep1),
3261 .vuaddp_vuad_sel_c2 (vuaddp_vuad_sel_c2),
3262 .vuaddp_vuad_sel_c4 (vuaddp_vuad_sel_c4),
3263 .vuaddp_vuad_sel_rd (vuaddp_vuad_sel_rd),
3264 .vuaddp_vuad_sel_c2_d1 (vuaddp_vuad_sel_c2_d1),
3265 .vuaddp_bistordiag_wr_vd_c4(vuaddp_bistordiag_wr_vd_c4),
3266 .vuaddp_sel_vd_wr_data_byp (vuaddp_sel_vd_wr_data_byp),
3267 .vuad_array_rd_data_c1(vuad_array_rd_data_c1[38:0]),
3268 .tcu_muxtest(tcu_muxtest),
3269 .mux_valid_dirty_c1_sel0(mux_valid_dirty_c1_sel0),
3270 .mux_valid_dirty_c1_sel1(mux_valid_dirty_c1_sel1),
3271 .mux_valid_dirty_c1_sel2(mux_valid_dirty_c1_sel2));
3272
3273l2t_usaloc_dp usaloc(
3274 .tcu_pce_ov(ce_ovrd),
3275 .tcu_aclk(aclk),
3276 .tcu_bclk(bclk),
3277 .tcu_scan_en(tcu_scan_en),
3278 .tcu_clk_stop(1'b0),
3279 // Outputs
3280 .usaloc_vuad_array_wr_data_c4(vlddir_vuad_array_wr_data_c4[77:39]),
3281 .usaloc_vuad_used_c2 (usaloc_vuad_used_c2[15:0]),
3282 .usaloc_vuad_alloc_c2 (usaloc_vuad_alloc_c2[15:0]),
3283 .usaloc_diag_rd_ua_out (usaloc_diag_rd_ua_out[38:0]),
3284 .usaloc_ua_ue_c2 (usaloc_ua_ue_c2), // BS and SR VUAD ECC Change 8/9/04
3285 .usaloc_ua_ce_c2 (usaloc_ua_ce_c2), // BS and SR VUAD ECC Change 8/9/04
3286 .usaloc_ua_synd_c2 (usaloc_ua_synd_c2[5:0]), //BS and SR VUAD ECC Change
3287 // Inputs
3288 .arb_vuad_ce_err_c3 (usaloc_vlddir_arb_vuad_ce_err_c3_rep1_v2),
3289 .tag_hit_way_vld_c3(tag_hit_way_vld_c3_rep20[15:0]),
3290 .scan_in(usaloc_scanin),
3291 .scan_out(usaloc_scanout),
3292 .l2clk (l2clk),
3293 .arb_bs_or_bis_inst_c2 (arb_bs_or_bis_inst_c2),
3294 .tagdp_lru_way_sel_c3 (tagdp_lru_way_sel_c3_rep20[15:0]),
3295 .vuaddp_fill_way_c3 (vuaddp_fill_way_c3[15:0]),
3296 // .vuaddp_hit_wayvld_c3 (vuaddp_hit_wayvld_c3[15:0]),
3297 .vuadpm_bistordiag_ua_data (vuadpm_bistordiag_ua_data[38:0]),
3298 .vuaddp_vuad_evict_c3 (tagdp_evict_c3_1_rep1),
3299 .vuaddp_wr64_inst_c3 (vuaddp_wr64_inst_c3),
3300 .vuaddp_vuad_sel_c4 (vuaddp_vuad_sel_c4),
3301 .vuaddp_vuad_sel_rd (vuaddp_vuad_sel_rd),
3302 .vuaddp_vuad_sel_c2_d1 (vuaddp_vuad_sel_c2_d1),
3303 .vuaddp_bistordiag_wr_ua_c4(vuaddp_bistordiag_wr_ua_c4),
3304 .vuaddp_sel_ua_wr_data_byp (vuaddp_sel_ua_wr_data_byp),
3305 .vuaddp_alloc_set_cond_c3 (alloc_set_cond_c3),
3306 .vuaddp_alloc_rst_cond_c3 (alloc_rst_cond_c3),
3307 .filbuf_vuad_bypassed_c3(filbuf_vuad_bypassed_c3),
3308 .vuad_array_rd_data_c1(vuad_array_rd_data_c1[77:39]),
3309 .tcu_muxtest(tcu_muxtest),
3310 .vuad_usaloc_mux_used_and_alloc_comb_sel0(vuad_usaloc_mux_used_and_alloc_comb_sel0),
3311 .vuad_usaloc_mux_used_and_alloc_comb_sel1(vuad_usaloc_mux_used_and_alloc_comb_sel1),
3312 .vuad_usaloc_mux_used_and_alloc_comb_sel2(vuad_usaloc_mux_used_and_alloc_comb_sel2),
3313 .vuad_usaloc_mux_used_and_alloc_comb_sel3(vuad_usaloc_mux_used_and_alloc_comb_sel3),
3314 .vuad_usaloc_mux_used_and_alloc_comb_sel4(vuad_usaloc_mux_used_and_alloc_comb_sel4),
3315 .vuad_usaloc_mux_used_and_alloc_comb_sel5(vuad_usaloc_mux_used_and_alloc_comb_sel5));
3316
3317
3318////////////////////////////
3319// tag array template
3320///////////////////////////
3321
3322
3323n2_l2t_sp_28kb_cust tag(
3324.bist_index0 (tagd_mbist_l2t_index_buf[8:0]),
3325.bist_index1 (tagd_mbist_l2t_index_buf[8:0]),
3326.bist_rd_en0 (tagd_mbist_l2t_read_buf),
3327.bist_rd_en1 (tagd_mbist_l2t_read_buf),
3328.bist_way (tagd_mbist_l2t_dec_way_buf[15:0]),
3329.bist_wr_en0 (tagd_mbist_l2t_write_buf),
3330.bist_wr_en1 (tagd_mbist_l2t_write_buf),
3331.bist_wrdata0 (tagd_mbist_write_data_buf[7:0] ),
3332.bist_wrdata1 (tagd_mbist_write_data_buf[7:0] ),
3333.tcu_clk_stop (1'b0),
3334.index0 (tagd_arbdp_tag_idx_px2_buf_1[8:0]),
3335.index1 (tagd_arbdp_tag_idx_px2_buf_2[8:0]),
3336.scan_in(tag_scanin),
3337.scan_out(tag_scanout),
3338.l2clk (l2clk),
3339.lkup_tag0 (tagd_lkup_tag_c1[`TAG_WIDTH_LESS1:1]),
3340.lkup_tag1 (tagd_lkup_tag_c1[`TAG_WIDTH_LESS1:1]),
3341.pce (1'b1),
3342.vnw_ary (vnw_ary),
3343.tcu_pce_ov (ce_ovrd),
3344.rd_en0 (tagd_arb_tag_rd_px2_buf),
3345.rd_en1 (tagd_arb_tag_rd_px2_buf),
3346.hdr_l2t_rvalue (l2t_tag_rvalue[5:0]),
3347.hdr_l2t_rid (l2t_tag_rid[3:0]),
3348.hdr_l2t_wr_en (l2t_tag_wr_en),
3349.hdr_l2t_red_clr (l2t_tag_fuse_clr),
3350// fuse
3351.tcu_scan_en0 (tcu_scan_en),
3352.tcu_scan_en1 (tcu_scan_en),
3353.tcu_se_scancollar_in0 (tcu_se_scancollar_in),
3354.tcu_se_scancollar_in1 (tcu_se_scancollar_in),
3355.tcu_se_scancollar_out0 (tcu_se_scancollar_out),
3356.tcu_se_scancollar_out1 (tcu_se_scancollar_out),
3357.tcu_aclk0 (aclk),
3358.tcu_aclk1 (aclk),
3359.tcu_bclk0 (bclk),
3360.tcu_bclk1 (bclk),
3361.w_inhibit0 (array_wr_inhibit),
3362.w_inhibit1 (array_wr_inhibit),
3363.way (tagd_arb_tag_way_px2_buf[15:0] ),
3364.wr_en0 (tagd_arb_tag_wr_px2_buf),
3365.wr_en1 (tagd_arb_tag_wr_px2_buf),
3366.wrdata0 (tagd_wrdata_px2_buf[27:0]),
3367.wrdata1 (tagd_wrdata_px2_buf[27:0]),
3368.l2t_bist_en0 (mbist_run),
3369.l2t_bist_en1 (mbist_run),
3370.wr_en_ov (1'b1),
3371.clk_en0 (1'b1),
3372.clk_en1 (1'b1),
3373.clk_en_ov (1'b1),
3374// outputs
3375.l2t_hdr_read_data (tag_fuse_read_data[5:0]),
3376.tag_way0 (tag_way0_tag_c2[27:0]),
3377.tag_way1 (tag_way1_tag_c2[27:0]),
3378.tag_way2 (tag_way2_tag_c2[27:0]),
3379.tag_way3 (tag_way3_tag_c2[27:0]),
3380.tag_way4 (tag_way4_tag_c2[27:0]),
3381.tag_way5 (tag_way5_tag_c2[27:0]),
3382.tag_way6 (tag_way6_tag_c2[27:0]),
3383.tag_way7 (tag_way7_tag_c2[27:0]),
3384.tag_way8 (tag_way8_tag_c2[27:0]),
3385.tag_way9 (tag_way9_tag_c2[27:0]),
3386.tag_way10 (tag_way10_tag_c2[27:0]),
3387.tag_way11 (tag_way11_tag_c2[27:0]),
3388.tag_way12 (tag_way12_tag_c2[27:0]),
3389.tag_way13 (tag_way13_tag_c2[27:0]),
3390.tag_way14 (tag_way14_tag_c2[27:0]),
3391.tag_way15 (tag_way15_tag_c2[27:0]),
3392.way_hit (tag_way_sel_c2[15:0])
3393);
3394
3395
3396////////////////////////////
3397// tag dp template
3398///////////////////////////
3399
3400l2t_tagl_dp tagl_1(
3401 .tcu_pce_ov(ce_ovrd),
3402 .tcu_aclk(aclk),
3403 .tcu_bclk(bclk),
3404 .tcu_scan_en(tcu_scan_en),
3405 .tcu_clk_stop(1'b0),
3406 .tcu_muxtest(tcu_muxtest),
3407 /*AUTOINST*/
3408 // Outputs
3409 .tagl_parity_c2 (tagl_parity_c2[7:0]), // Templated
3410 .tagl_tag_quad0_c3 (tagl_quad0_c3[`TAG_WIDTH_LESS1:0]), // Templated ,BS & SR 10/28/03
3411 .tagl_tag_quad1_c3 (tagl_quad1_c3[`TAG_WIDTH_LESS1:0]), // Templated ,BS & SR 10/28/03
3412 // Inputs
3413 .way0_tag_c2 (tag_way0_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3414 .way1_tag_c2 (tag_way1_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3415 .way2_tag_c2 (tag_way2_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3416 .way3_tag_c2 (tag_way3_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3417 .way4_tag_c2 (tag_way4_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3418 .way5_tag_c2 (tag_way5_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3419 .way6_tag_c2 (tag_way6_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated ,BS & SR 10/28/03
3420 .way7_tag_c2 (tag_way7_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated ,BS & SR 10/28/03
3421 .scan_in(tagl_1_scanin),
3422 .scan_out(tagl_1_scanout),
3423 .l2clk (l2clk),
3424 .tagdp_quad0_muxsel_c3(tagdp_quad0_muxsel_c3[3:0]), // Templated ,BS & SR 10/28/03
3425 .tagdp_quad1_muxsel_c3(tagdp_quad1_muxsel_c3[3:0]),
3426 .tcu_dectest(tcu_dectest)); // Templated ,BS & SR 10/28/03
3427
3428l2t_tagl_dp tagl_2(
3429 .tcu_pce_ov(ce_ovrd),
3430 .tcu_aclk(aclk),
3431 .tcu_bclk(bclk),
3432 .tcu_scan_en(tcu_scan_en),
3433 .tcu_clk_stop(1'b0),
3434 .tcu_muxtest(tcu_muxtest),
3435 /*AUTOINST*/
3436 // Outputs
3437 .tagl_parity_c2 (tagl_parity_c2[15:8]), // Templated
3438 .tagl_tag_quad0_c3 (tagl_quad2_c3[`TAG_WIDTH_LESS1:0]), // Templated, BS & SR 10/28/03
3439 .tagl_tag_quad1_c3 (tagl_quad3_c3[`TAG_WIDTH_LESS1:0]), // Templated, BS & SR 10/28/03
3440 // Inputs
3441 .way0_tag_c2 (tag_way8_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3442 .way1_tag_c2 (tag_way9_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3443 .way2_tag_c2 (tag_way10_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3444 .way3_tag_c2 (tag_way11_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3445 .way4_tag_c2 (tag_way12_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3446 .way5_tag_c2 (tag_way13_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated
3447 .way6_tag_c2 (tag_way14_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated, BS & SR 10/28/03
3448 .way7_tag_c2 (tag_way15_tag_c2[`TAG_WIDTH_LESS1:0]), // Templated, BS & SR 10/28/03
3449 .scan_in(tagl_2_scanin),
3450 .scan_out(tagl_2_scanout),
3451 .l2clk (l2clk),
3452 .tagdp_quad0_muxsel_c3(tagdp_quad2_muxsel_c3[3:0]), // Templated, BS & SR 10/28/03
3453 .tagdp_quad1_muxsel_c3(tagdp_quad3_muxsel_c3[3:0]),
3454 .tcu_dectest(tcu_dectest)); // Templated, BS & SR 10/28/03
3455
3456
3457l2t_tagdp_ctl tagdp(
3458 .tcu_pce_ov(ce_ovrd),
3459 .tcu_aclk(aclk),
3460 .tcu_bclk(bclk),
3461 .tcu_scan_en(tcu_scan_en),
3462 // Outputs
3463 .tagdp_quad0_muxsel_c3(tagdp_quad0_muxsel_c3[3:0]),
3464 .tagdp_quad1_muxsel_c3(tagdp_quad1_muxsel_c3[3:0]),
3465 .tagdp_quad2_muxsel_c3(tagdp_quad2_muxsel_c3[3:0]),
3466 .tagdp_quad3_muxsel_c3(tagdp_quad3_muxsel_c3[3:0]),
3467 .tagdp_tag_quad_muxsel_c3(tagdp_quad_muxsel_c3[3:0]),
3468 .tagdp_misbuf_par_err_c3(tagdp_misbuf_par_err_c3),
3469 .tagdp_tag_par_err_c3(tagdp_tag_par_err_c3),
3470 .tagdp_arb_par_err_c3(tagdp_arb_par_err_c3),
3471 .tagdp_tag_error_c8 (tagdp_tag_error_c8),
3472 .tagdp_lru_way_sel_c3(tagdp_lru_way_sel_c3[15:0]),
3473 .tagdp_evict_c3_1 (tagdp_evict_c3_1),
3474 .tagdp_evict_c3_2 (tagdp_evict_c3_2),
3475 .tagdp_invalid_evict_c3(tagdp_invalid_evict_c3),
3476 .tagdp_vuad_dp_diag_data_c7_buf(tagdp_vuad_dp_diag_data_c7_buf[38:0]),
3477 .tag_way_sel_c2_buff(tag_way_sel_c2_buff[15:0]),
3478
3479 // Inputs
3480 .arb_vuad_ce_err_c3 (tagctl_arb_vuad_ce_err_c3),
3481 .arb_pf_ice_inst_c2(arb_pf_ice_inst_c2),
3482 .vlddir_vuad_valid_c2(vlddir_vuad_valid_c2_rep1[15:0]),
3483 .tag_parity_c2(tagl_parity_c2[15:0]),
3484 .tag_way_sel_c2(tag_way_sel_c2[15:0]), // Templated
3485 .vuaddp_vuad_tagd_sel_c2_d1(vuaddp_vuad_tagd_sel_c2_d1),
3486 .bist_way_px (mbist_l2t_way[3:0]), // Templated
3487 .bist_enable_px(mbist_l2t_read), // Templated
3488 .arbadr_arbdp_diag_wr_way_c2(arbdp_diag_wr_way_c2[3:0]),
3489 .arb_tecc_way_c2(arb_tecc_way_c2[3:0]),
3490 .arb_normal_tagacc_c2(arb_normal_tagacc_c2),
3491 .arb_tagd_tecc_c2(arb_tagd_tecc_c2),
3492 .arb_tagd_perr_vld_c2(arb_tagd_perr_vld_c2),
3493 .misbuf_hit_c3 (misbuf_hit_c3),
3494 .csr_l2_dir_map_on(csreg_tagdp_l2_dir_map_on),
3495 .arb_l2tag_vld_c4(arb_l2tag_vld_c4),
3496 .vuad_dp_diag_data_c7(vuad_diag_data_c7[38:0]),
3497 .scan_in(tagdp_scanin),
3498 .scan_out(tagdp_scanout),
3499 .l2clk (l2clk),
3500 .wmr_l (wmr_l),
3501 .usaloc_vuad_used_c2(usaloc_vuad_used_c2[15:0]),
3502 .usaloc_vuad_alloc_c2(usaloc_vuad_alloc_c2[15:0]),
3503 .arb_evict_vld_c2(arb_evict_vld_c2),
3504 .mbist_run(mbist_run));
3505
3506
3507
3508l2t_tagd_dp tagd(
3509 .tcu_pce_ov(ce_ovrd),
3510 .tcu_aclk(aclk),
3511 .tcu_bclk(bclk),
3512 .tcu_scan_en(tcu_scan_en),
3513 .tcu_clk_stop(1'b0),
3514 .tcu_muxtest(tcu_muxtest),
3515 .tcu_dectest(tcu_dectest),
3516 .tagd_mbdata_inst_tecc_c8 (mbdata_inst_tecc_c8[5:0]),
3517 .tagd_lkup_addr_c4 (tagd_lkup_addr_c4[17:9]), // BS and SR 11/18/03 Reverse Directory change
3518
3519 /*AUTOINST*/
3520 // Outputs
3521 .tagd_evict_tag_c3 (tagd_evict_tag_c3[`TAG_WIDTH_LESS1:0]),
3522 .tagd_dmo_evict_tag_c4 (tagd_dmo_evict_tag_c4[`TAG_WIDTH_LESS1:0]),
3523 .tagd_diag_data_c7 (tagd_diag_data_c7[`TAG_WIDTH_LESS1:0]),
3524 .tagd_lkup_row_addr_dcd_c3 (lkup_row_addr_dcd_c3[2:0]),
3525 .tagd_lkup_row_addr_icd_c3 (lkup_row_addr_icd_c3[2:0]),
3526 .tagd_lkup_tag_c1 (tagd_lkup_tag_c1[`TAG_WIDTH_LESS1:1]),
3527 .tagd_arbdp_tag_idx_px2_buf_1(tagd_arbdp_tag_idx_px2_buf_1[8:0]), // BS & SR 10/28/03
3528 .tagd_arbdp_tag_idx_px2_buf_2(tagd_arbdp_tag_idx_px2_buf_2[8:0]), // BS & SR 10/28/03
3529 .tagd_mbist_l2t_index_buf (tagd_mbist_l2t_index_buf[8:0]), // BS & SR 10/28/03
3530 .tagd_arb_tag_way_px2_buf(tagd_arb_tag_way_px2_buf[15:0]), // BS & SR 10/28/03
3531 .tagd_mbist_l2t_dec_way_buf(tagd_mbist_l2t_dec_way_buf[15:0]), // BS & SR 10/28/03
3532 .tagd_arb_tag_rd_px2_buf(tagd_arb_tag_rd_px2_buf),
3533 .tagd_mbist_l2t_read_buf (tagd_mbist_l2t_read_buf),
3534 .tagd_arb_tag_wr_px2_buf(tagd_arb_tag_wr_px2_buf),
3535 .tagd_mbist_l2t_write_buf (tagd_mbist_l2t_write_buf),
3536 .tagd_tag_wrdata_px2_buf (tagd_wrdata_px2_buf[27:0]),
3537 .tagd_mbist_write_data_buf (tagd_mbist_write_data_buf[7:0]),
3538 // Inputs
3539 .arbadr_2bnk_true_enbld_dist(arbadr_tagd_2bnk_true_enbld_dist), // BS 03/25/04 for partial bank/core modes support
3540 .arbadr_4bnk_true_enbld_dist(arbadr_tagd_4bnk_true_enbld_dist), // BS 03/25/04 for partial bank/core modes support
3541 .arbadr_ncu_l2t_pm_n_dist(arbadr_tagd_ncu_l2t_pm_n_dist), // BS 03/25/04 for partial bank/core modes support
3542 .arbadr_dir_cam_addr_c3 (arbadr_dir_cam_addr_c3[39:7]),
3543 .arbadr_arbaddr_idx_c3 (arbaddr_idx_c3[10:0]),
3544 .arbadr_arbdp_tagdata_px2 (arbadr_arbdp_tagdata_px2[`TAG_WIDTH_LESS1:6]),
3545 .tagl_tag_quad0_c3 (tagl_quad0_c3[`TAG_WIDTH_LESS1:0]),
3546 .tagl_tag_quad1_c3 (tagl_quad1_c3[`TAG_WIDTH_LESS1:0]),
3547 .tagl_tag_quad2_c3 (tagl_quad2_c3[`TAG_WIDTH_LESS1:0]),
3548 .tagl_tag_quad3_c3 (tagl_quad3_c3[`TAG_WIDTH_LESS1:0]),
3549 .tagdp_tag_quad_muxsel_c3 (tagdp_quad_muxsel_c3[3:0]),
3550 .arbadr_arbdp_tag_idx_px2 (arbadr_arbdp_tag_idx_px2[8:0]), // BS & SR 10/28/03
3551 .mbist_l2t_index (mbist_l2t_index[8:0]), // BS & SR 10/28/03
3552 .arb_tag_way_px2 (arb_tag_way_px2[15:0]), // BS & SR 10/28/03
3553 .mbist_l2t_dec_way (mbist_l2t_dec_way[15:0]),
3554 .arb_tag_rd_px2 (arb_tag_rd_px2),
3555 .mbist_l2t_read (mbist_l2t_read),
3556 .arb_tag_wr_px2 (arb_tag_wr_px2),
3557 .mbist_l2t_write (mbist_l2t_write),
3558 .arbadr_tag_wrdata_px2 (arbadr_tag_wrdata_px2[27:0]),
3559 .mbist_write_data (mbist_write_data[7:0]),
3560 .arb_evict_c3 (arb_evict_c3),
3561 .scan_in(tagd_scanin),
3562 .scan_out(tagd_scanout),
3563 .l2clk (l2clk),
3564 .mbist_l2tag_fail(mbist_l2tag_fail));
3565
3566
3567l2t_dmorpt_dp dmorptr
3568 (
3569 .in_bus0 (l2t_tcu_dmo_out_prev[38:0]),
3570 .in_bus1 (l2t_tcu_dmo_out_unbuff[38:0]),
3571 .out_bus0 (l2t_tcu_dmo_out_prev_buff[38:0]),
3572 .out_bus1 (l2t_tcu_dmo_out[38:0])
3573 );
3574
3575l2t_dmo_dp dmologic (
3576 .tcu_l2t_coresel (tcu_l2t_coresel),
3577 .l2t_tcu_dmo_out_prev (l2t_tcu_dmo_out_prev_buff[38:0]),
3578 .scan_in(dmologic_scanin),
3579 .scan_out(dmologic_scanout),
3580 .l2clk (l2clk),
3581 .tcu_l2t_shscan_clk_stop_d2 (tcu_l2t_shscan_clk_stop_d2),
3582 .tcu_l2t_shscan_clk_stop (tcu_l2t_shscan_clk_stop),
3583 .tcu_clk_stop (1'b0),
3584 .tcu_pce_ov (tcu_pce_ov),
3585 .tcu_aclk (tcu_aclk),
3586 .tcu_bclk (tcu_bclk),
3587 .tcu_scan_en (tcu_scan_en),
3588 .l2t_tcu_dmo_out (l2t_tcu_dmo_out_unbuff[38:0]),
3589 .mbist_dmo_data_out(mbist_dmo_data_out[38:0]),
3590 .io_cmp_sync_en(io_cmp_sync_en)
3591 );
3592
3593
3594l2t_mbist_ctl mbist (
3595 // Outputs
3596 .mbist_run(mbist_run),
3597 .mbist_done (l2t_tcu_mbist_done),
3598 .mbist_fail (l2t_tcu_mbist_fail),
3599 .mbist_start_mb0(mbist_start_mb0),
3600 .mbist_start_mb2(mbist_start_mb2),
3601 // Inputs
3602 .mbist0_done (l2t_tcu_mbist0_done),
3603 .mbist2_done (l2t_tcu_mbist2_done),
3604 .mbist0_fail (l2t_tcu_mbist0_fail),
3605 .mbist2_fail (l2t_tcu_mbist2_fail),
3606 .tcu_pce_ov(ce_ovrd),
3607 .tcu_aclk(aclk),
3608 .tcu_bclk(bclk),
3609 .tcu_scan_en(tcu_scan_en),
3610 .tcu_clk_stop(1'b0),
3611 .mbist_l2tag_fail (mbist_l2tag_fail),
3612 .mbist_l2vuad_fail (mbist_l2vuad_fail),
3613 .mbist_l2data_fail (mbist_l2data_fail),
3614 .mbist_l2tag_index (mbist_l2t_index[8:0]), // Templated
3615 .mbist_l2tag_way (mbist_l2t_way[3:0]), // Templated
3616 .mbist_l2tag_dec_way(mbist_l2t_dec_way[15:0]), // Templated
3617 .mbist_l2tag_read (mbist_l2t_read), // Templated
3618 .mbist_l2tag_write (mbist_l2t_write), // Templated
3619 .mbist_l2vuad_read (mbist_l2v_read), // Templated
3620 .mbist_l2vuad_index(mbist_l2v_index[8:0]), // Templated
3621 .mbist_l2vuad_vd (mbist_l2v_vd), // Templated
3622 .mbist_l2vuad_write(mbist_l2v_write), // Templated
3623 .mbist_l2data_index(mbist_l2d_index[8:0]), // Templated
3624 .mbist_l2data_way (mbist_l2d_way[3:0]), // Templated
3625 .mbist_l2data_word (mbist_l2d_word_sel[3:0]), // Templated
3626 .mbist_l2data_write(mbist_l2d_write), // Templated
3627 .mbist_write_data (mbist_write_data[7:0]), // Templated
3628 .mbist_write_data_decck (mbist_write_data_decck[7:0]), // Templated
3629 .mbist_arb_l2t_write(mbist_arb_l2t_write),
3630 .mbist_arb_l2d_en (mbist_arb_l2d_en),
3631 .mbist_arb_l2d_write(mbist_arb_l2d_write),
3632 .mbist_l2d_en (mbist_l2d_en),
3633 .scan_in(tcu_l2t_mbist_scan_in),
3634 .scan_out(tcu_l2t_mbist_scan_in1),
3635 .l2clk (l2clk),
3636 .mbist_start (tcu_l2t_mbist_start),
3637 .mbist_user_mode(tcu_mbist_user_mode),
3638 .mbist_bisi_mode (tcu_mbist_bisi_en),
3639 .mbist_l2tag_hit_way (tag_way_sel_c2_buff[15:0]),
3640 .mbist_l2tag_lkup_tag (mbist_tag_lkup_addr[27:0]));
3641
3642
3643l2t_l2drpt_dp l2drpt (
3644 .scan_in (tagctl_scanin),
3645 .scan_out (tagctl_scanin_1),
3646 .tag_l2d_way_sel_c2(l2t_l2d_way_sel_c2[15:0]),
3647 .tcu_clk_stop(1'b0),
3648 .vlddir_vuad_valid_c2 (vlddir_vuad_valid_c2_rep1[15:0]),
3649 .misbuf_tag_hit_unqual_c2(misbuf_tag_hit_unqual_c2_rep2),
3650 .l2clk(l2clk),
3651 .tcu_pce_ov(tcu_pce_ov),
3652 .tcu_aclk(tcu_aclk),
3653 .tcu_bclk(tcu_bclk),
3654 .tcu_scan_en(tcu_scan_en),
3655 .arb_l2drpt_waysel_gate_c1(arb_l2drpt_waysel_gate_c1),
3656 .mbist_run(mbist_run),
3657 .arb_inst_vld_c2_prev(arb_inst_vld_c2_prev),
3658 .csr_l2_bypass_mode_on(csr_l2_bypass_mode_on),
3659 .arb_decdp_ld64_inst_c1(arb_decdp_ld64_inst_c1),
3660 .tag_way_sel_c2(tag_way_sel_c2[15:0]),
3661 .tagctl_l2drpt_mux4_way_sel_c1(tagctl_l2drpt_mux4_way_sel_c1[15:0]),
3662 .tag_rdma_gate_off_c2(tag_rdma_gate_off_c2),
3663 .tagdp_lru_way_sel_c3(tagdp_lru_way_sel_c3[15:0]),
3664 .arb_evict_vld_c2(arb_evict_vld_c2),
3665 .tagdp_tag_par_err_c3(tagdp_tag_par_err_c3)
3666 );
3667l2t_tag_ctl tagctl (
3668 .tcu_pce_ov(ce_ovrd),
3669 .tcu_aclk(aclk),
3670 .tcu_bclk(bclk),
3671 .tcu_scan_en(tcu_scan_en),
3672 .wmr_l (wmr_l),
3673 // Outputs
3674 .sel_diag_store_data_c7 (sel_diag_store_data_c7), // BS and SR 12/22/03, store ack generation for diagnostic store
3675
3676 .tag_dir_l2way_sel_c4 (tag_dir_l2way_sel_c4), // BS and SR 11/18/03 Reverse Directory change
3677 .tag_store_inst_c3 (tag_store_inst_c3), //BS and SR 11/07/03, store pipelining support
3678 .tag_hit_way_vld_c3(tag_hit_way_vld_c3[15:0]),
3679 .tag_st_to_data_array_c3(tag_st_to_data_array_c3),
3680 .tag_hit_l2orfb_c3(tag_hit_l2orfb_c3),
3681 .tag_miss_unqual_c2(tag_miss_unqual_c2),
3682 .tag_hit_unqual_c2(tag_hit_unqual_c2),
3683 .tag_hit_c3 (tag_hit_c3),
3684 .tag_lru_way_c4(tag_lru_way_c4[3:0]),
3685 .tag_rdma_vld_px0_p(tag_rdma_vld_px0_p),
3686 .tag_hit_not_comp_c3(tag_hit_not_comp_c3),
3687 .tag_alt_tag_miss_unqual_c3(tag_alt_tag_miss_unqual_c3),
3688 .tag_misbuf_rdma_reg_vld_c2(tag_misbuf_rdma_reg_vld_c2),
3689 // .tag_l2d_col_offset_c2(l2t_l2d_col_offset_c2[3:0]),
3690 .tag_l2d_rd_wr_c2 (l2t_l2d_rd_wr_c2),
3691 .tag_l2d_word_en_c2(l2t_l2d_word_en_c2[15:0]),
3692 .tag_deccck_addr3_c7(tag_deccck_addr3_c7),
3693 .tag_decc_tag_acc_en_px2(tag_decc_tag_acc_en_px2),
3694 .arb_inst_vld_c2_prev(arb_inst_vld_c2_prev),
3695 .tag_data_ecc_active_c3(tag_data_ecc_active_c3),
3696 .tag_deccck_data_sel_c8(tag_deccck_data_sel_c8),
3697 .tag_scrub_rd_vld_c7(tag_scrub_rd_vld_c7),
3698 .tag_spc_rd_vld_c6(tag_spc_rd_vld_c6),
3699 .tag_bsc_rd_vld_c7(tag_bsc_rd_vld_c7),
3700 .tag_scrub_addr_way (tag_scrub_addr_way[3:0]),
3701 .tag_imiss_hit_c5(tag_imiss_hit_c5),
3702 .tag_ld_hit_c5 (tag_ld_hit_c5),
3703 .tag_strst_ack_c5(tag_strst_ack_c5),
3704 .tag_st_ack_c5 (tag_st_ack_c5),
3705 .tag_st_req_c5 (tag_st_req_c5),
3706 .tag_inval_req_c5(tag_inval_req_c5), // BS and SR 11/12/03 N2 Xbar Packet format change
3707 .tag_nonmem_comp_c6(tag_nonmem_comp_c6),
3708 .tag_uerr_ack_c5(tag_uerr_ack_c5),
3709 .tag_cerr_ack_c5(tag_cerr_ack_c5),
3710 .tag_int_ack_c5(tag_int_ack_c5),
3711 .tag_fwd_req_ret_c5(tag_fwd_req_ret_c5),
3712 .tag_sel_rdma_inval_vec_c5(tag_sel_rdma_inval_vec_c5),
3713 .tag_rdma_wr_comp_c4(tag_rdma_wr_comp_c4),
3714 .tag_rmo_st_ack_c5(tag_rmo_st_ack_c5),
3715 .tag_inst_mb_c5(tag_inst_mb_c5),
3716 .tag_hit_c5 (tag_hit_c5),
3717 .tag_store_inst_c5(tag_store_inst_c5),
3718 .tag_fwd_req_ld_c6(tag_fwd_req_ld_c6),
3719 .tag_rdma_gate_off_c2(tag_rdma_gate_off_c2),
3720 .tag_rd64_complete_c11(tag_rd64_complete_c11),
3721 .tag_uerr_ack_tmp_c4 (tag_uerr_ack_tmp_c4),
3722 .tag_cerr_ack_tmp_c4 (tag_cerr_ack_tmp_c4),
3723 .tag_spc_rd_cond_c3 (tag_spc_rd_cond_c3),
3724 .tag_rdma_vld_px1(tag_rdma_vld_px1),
3725 .tag_rdma_ev_en_c4(tag_rdma_ev_en_c4),
3726 .tag_inc_rdma_cnt_c4(tag_inc_rdma_cnt_c4),
3727 .tag_set_rdma_reg_vld_c4(tag_set_rdma_reg_vld_c4),
3728 .tag_siu_req_en_c52(tag_siu_req_en_c52),
3729 .tag_misbuf_par_err_c3(tag_misbuf_par_err_c3),
3730 // Inputs
3731 .filbuf_dis_nderr_c3 (filbuf_dis_nderr_c3[1:0]),
3732 .arb_vuad_ce_err_c3 (tagctl_arb_vuad_ce_err_c3),
3733 .arb_upper_four_byte_access_c1(arb_upper_four_byte_access_c1), // BS 05/04/04 : taking out upper_four_byte_access info
3734 .arb_lower_four_byte_access_c1(arb_lower_four_byte_access_c1), // BS 05/04/04 : taking out lower_four_byte_access info
3735 .misbuf_hit_st_dep_zero (misbuf_hit_st_dep_zero), // BS and SR 11/07/03, store pipelining support
3736 .misbuf_arb_hit_c3(misbuf_arb_hit_c3), // BS and SR 1/31/04
3737 .tag_way_sel_c2 (tag_way_sel_c2[15:0]),
3738 .vlddir_vuad_valid_c2 (vlddir_vuad_valid_c2_rep1[15:0]),
3739 .tagdp_lru_way_sel_c3 (tagdp_lru_way_sel_c3[15:0]),
3740 .tagdp_tag_par_err_c3(tagdp_tag_par_err_c3),
3741 .bist_data_enc_way_sel_c1(mbist_l2d_way[3:0]), // Templated
3742 .bist_data_enable_c1(mbist_l2d_en), // Templated
3743 .bist_data_wr_enable_c1(mbist_l2d_write), // Templated
3744 .bist_data_waddr_c1(mbist_l2d_word_sel[3:0]), // Templated
3745 .arbadr_arbdp_addr5to4_c1(arbadr_arbdp_addr5to4_c1[1:0]),
3746 .arbadr_arbdp_addr3to2_c1(arbadr_arbdp_addr3to2_c1[1:0]),
3747 .arbadr_arbaddr_addr22_c2(arbaddr_addr22_c2),
3748 .arbadr_arbdp_diag_wr_way_c2(arbdp_diag_wr_way_c2[3:0]),
3749 .arbdec_arbdp_inst_way_c3(arbdec_arbdp_inst_way_c3[3:0]),
3750 .arb_decdp_tag_wr_c1(arb_decdp_tag_wr_c1),
3751 //.arb_decdp_cas2_from_mb_ctrue_c2(arb_decdp_cas2_from_mb_ctrue_c2),
3752 .arb_decdp_cas2_from_mb_c2(arb_decdp_cas2_from_mb_c2),
3753 .arb_decdp_strst_inst_c2(arb_decdp_strst_inst_c2),
3754 .arb_decdp_rmo_st_c3 (arb_decdp_rmo_st_c3),
3755 .arbdec_arbdp_rdma_inst_c1(arbdec_arbdp_rdma_inst_c1),
3756 .arb_decdp_ld64_inst_c1(arb_decdp_ld64_inst_c1),
3757 .arb_decdp_wr64_inst_c2(arb_decdp_wr64_inst_c2),
3758 .arb_decdp_wr8_inst_c2(arb_decdp_wr8_inst_c2),
3759 .arb_tag_pst_with_ctrue_c1(arb_tag_pst_with_ctrue_c1),
3760 .csr_l2_bypass_mode_on(csr_tag_l2off), // Templated
3761 .arb_bist_or_diag_acc_c1(arb_bist_or_diag_acc_c1),
3762 .arb_fill_vld_c2(arb_fill_vld_c2),
3763 .arb_imiss_vld_c2(arb_imiss_vld_c2),
3764 .arb_evict_vld_c2(arb_evict_vld_c2),
3765 .arb_tag_inst_vld_c2(arb_tag_inst_vld_c2),
3766 .filbuf_match_c3 (filbuf_match_c3),
3767 .arb_waysel_gate_c2(arb_waysel_gate_c2),
3768 .arb_data_diag_st_c2(arb_data_diag_st_c2),
3769 .arb_csr_wr_en_c3(arb_csr_wr_en_c3),
3770 .arb_csr_rd_en_c3(arb_csr_rd_en_c3),
3771 .arb_diag_complete_c3(arb_diag_complete_c3),
3772 .deccck_scrd_uncorr_err_c8(deccck_scrd_uncorr_err_c8),
3773 .misbuf_tag_hit_unqual_c2(misbuf_tag_hit_unqual_c2_rep1),
3774 .misbuf_uncorr_err_c2(misbuf_uncorr_err_c2),
3775 .misbuf_corr_err_c2(misbuf_corr_err_c2),
3776 .misbuf_notdata_err_c2 (misbuf_notdata_err_c2_rep1),
3777 .misbuf_wr64_miss_comp_c3(misbuf_wr64_miss_comp_c3),
3778 .arb_decdp_swap_inst_c2(arb_decdp_swap_inst_c2),
3779 .arb_arbdp_tag_pst_no_ctrue_c2(arb_arbdp_tag_pst_no_ctrue_c2),
3780 .arb_decdp_cas1_inst_c2(arb_decdp_cas1_inst_c2),
3781 .arb_decdp_ld_inst_c2 (arb_decdp_ld_inst_c2),
3782 .arbdec_arbdp_inst_mb_c2 (arbdec_arbdp_inst_mb_c2),
3783 .arbdec_arbdp_inst_dep_c2(arbdec_arbdp_inst_dep_c2),
3784 .arb_decdp_st_inst_c2 (arb_decdp_st_inst_c2),
3785 .arb_decdp_st_with_ctrue_c2(arb_decdp_st_with_ctrue_c2),
3786 .arb_decdp_inst_int_c2(arb_decdp_inst_int_c2),
3787 .arb_decdp_fwd_req_c2 (arb_decdp_fwd_req_c2),
3788 .arb_inval_inst_c2(arb_inval_inst_c2),
3789 .arb_waysel_inst_vld_c2(arb_waysel_inst_vld_c2),
3790 .arb_rdwr_inst_vld_c2(arb_rdwr_inst_vld_c2),
3791 .arb_wr8_inst_no_ctrue_c1(arb_wr8_inst_no_ctrue_c1),
3792 .filbuf_tag_hit_c2(filbuf_tag_hit_c2),
3793 .filbuf_tag_hit_frm_mb_c2(filbuf_tag_tag_hit_frm_mb_c2_rep),
3794 .filbuf_tag_evict_way_c3 (filbuf_tag_evict_way_c3_rep1[3:0]), // BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Miss
3795 .filbuf_mcu_l2t_chunk_id_r1(filbuf_mcu_l2t_chunk_id_r1[1:0]),
3796 .filbuf_mcu_l2t_data_vld_r1(filbuf_mcu_l2t_data_vld_r1),
3797 .filbuf_dis_cerr_c3(filbuf_dis_cerr_c3_rep1),
3798 .filbuf_dis_uerr_c3(filbuf_dis_uerr_c3_rep1),
3799 .oqu_st_complete_c7(oqu_st_complete_c7),
3800 .arbdec_arbdp_tecc_c1 (arbdec_arbdp_tecc_c1),
3801 .scan_in(tagctl_scanin_1),
3802 .scan_out(tagctl_scanout),
3803 .l2clk (l2clk),
3804 .csr_error_nceen (csr_error_nceen),
3805 .csr_error_ceen (csr_error_ceen),
3806 .tagdp_misbuf_par_err_c3(tagdp_misbuf_par_err_c3),
3807 .tag_data_array_wr_active_c1(tag_data_array_wr_active_c1),
3808 .tag_hit_unqual_c3(tag_hit_unqual_c3),
3809 .misbuf_uncorr_err_c1(misbuf_uncorr_err_c1),
3810 .misbuf_notdata_err_c1(misbuf_notdata_err_c1),
3811 .tag_misbuf_int_ack_c3(tag_misbuf_int_ack_c3),
3812 .l2t_l2b_fbwr_wen_r2(l2t_l2b_fbwr_wen_r2[15:0]),
3813 .l2t_l2b_fbd_stdatasel_c3(l2t_l2b_fbd_stdatasel_c3),
3814 .tagctl_l2drpt_mux4_way_sel_c1(tagctl_l2drpt_mux4_way_sel_c1[15:0]),
3815 .dec_col_offset_prev_c1(dec_col_offset_prev_c1[3:0]),
3816 .decdp_cas2_from_mb_ctrue_c1(decdp_cas2_from_mb_ctrue_c1),
3817 .misbuf_vuad_ce_instr_ack_c2(misbuf_vuad_ce_instr_ack_c2),
3818 .mbist_run(mbist_run),
3819 .arb_arbdp_dword_st_c1(arb_arbdp_dword_st_c1),
3820 .arb_inst_diag_c1(arb_inst_diag_c1),
3821 .mbist_arb_l2d_en(mbist_arb_l2d_en));
3822
3823
3824
3825
3826l2t_misbuf_ctl misbuf (
3827 .tcu_pce_ov(ce_ovrd),
3828 .tcu_aclk(aclk),
3829 .tcu_bclk(bclk),
3830 .tcu_scan_en(tcu_scan_en),
3831 .l2t_mb2_mbdata_wr_en (l2t_mb2_mbdata_wr_en),
3832 .l2t_mb2_mbdata_rd_en (l2t_mb2_mbdata_rd_en),
3833 .l2t_mb2_mbtag_rd_en (l2t_mb2_mbtag_rd_en),
3834 .l2t_mb2_mbtag_wr_en (l2t_mb2_mbtag_wr_en),
3835 .l2t_mb2_addr (l2t_mb2_addr[4:0]),
3836 .misbuf_mb_write_wl (mb_write_wl[31:0]),
3837 .misbuf_dep_c8 (misbuf_dep_c8),
3838 .misbuf_evict_c8 (misbuf_evict_c8),
3839 .arb_vuad_ce_err_c2 (arb_vuad_ce_err_c2),
3840 .misbuf_mbentry_c8 (misbuf_mbentry_c8[4:0]),
3841 .misbuf_tecc_c8 (misbuf_tecc_c8),
3842 .misbuf_vuad_ce_instr_c2 (misbuf_vuad_ce_instr_c2),
3843 .misbuf_mbtag_wr_en_c2 (mbtag_wr_en_c2),
3844 .misbuf_mb_read_wl (mb_read_wl[31:0]),
3845 .misbuf_mb_data_write_wl (mb_data_write_wl[31:0]),
3846 .misbuf_mbdata_wr_en_c8 (mbdata_wr_en_c8),
3847 .arb_decdp_ld_inst_c2 (arb_decdp_ld_inst_c2), // BS and SR 11/07/03, store pipelining support
3848 .arb_decdp_imiss_inst_c2 (arb_decdp_imiss_inst_c2), // BS and SR 11/07/03, store pipelining support
3849 .mb_cam_match (mb_cam_match[31:0]),
3850 .mb_cam_match_idx (mb_cam_match_idx[31:0]),
3851 .mb_mbist_cam_hit (mb_mbist_cam_hit),
3852 .mbtag_mbist_cam_sel(mbist_cam_sel[0]),
3853 .wmr_l (wmr_l),
3854 /*AUTOINST*/
3855 // Outputs
3856 .misbuf_vuad_ce_err_c8(misbuf_vuad_ce_err_c8),
3857 .misbuf_hit_st_dep_zero (misbuf_hit_st_dep_zero), // BS and SR 11/07/03, store pipelining support
3858 .misbuf_arb_cnt28_px2_prev(misbuf_arb_cnt28_px2_prev),
3859 .misbuf_arb_snp_cnt8_px1(misbuf_arb_snp_cnt8_px1),
3860 .misbuf_arb_vld_px1(misbuf_arb_vld_px1),
3861 .misbuf_nondep_fbhit_c3(misbuf_nondep_fbhit_c3),
3862 .misbuf_hit_c3 (misbuf_hit_c3),
3863 .misbuf_arbdp_ctrue_px2(misbuf_arbdp_ctrue_px2),
3864 .misbuf_arb_l2rd_en (misbuf_arb_l2rd_en),
3865 .misbuf_arb_mcurd_en (misbuf_arb_mcurd_en),
3866 .misbuf_tag_hit_unqual_c2(misbuf_tag_hit_unqual_c2),
3867 .misbuf_corr_err_c2 (misbuf_corr_err_c2),
3868 .misbuf_uncorr_err_c2 (misbuf_uncorr_err_c2),
3869 .misbuf_notdata_err_c2 (misbuf_notdata_err_c2),
3870 .misbuf_wr64_miss_comp_c3(misbuf_wr64_miss_comp_c3),
3871 .misbuf_wbuf_mbid_c4 (misbuf_wbuf_mbid_c4[4:0]),
3872 .misbuf_mbf_insert_mbid_c4 (misbuf_mbf_insert_mbid_c4[4:0]),
3873 .misbuf_mbf_insert_c4 (misbuf_mbf_insert_c4),
3874 .misbuf_hit_c4 (misbuf_hit_c4),
3875 .misbuf_mbf_delete_c4 (misbuf_mbf_delete_c4),
3876 .misbuf_filbuf_next_vld_c4(misbuf_filbuf_next_vld_c4),
3877 .misbuf_filbuf_next_link_c4(misbuf_filbuf_next_link_c4[4:0]),
3878 .misbuf_filbuf_mcu_pick(misbuf_filbuf_mcu_pick),
3879 .misbuf_filbuf_fbid (misbuf_filbuf_fbid[2:0]),
3880 .misbuf_filbuf_way (misbuf_filbuf_way[3:0]),
3881 .misbuf_filbuf_way_fbid_vld(misbuf_filbuf_way_fbid_vld),
3882 .misbuf_buf_rd_en (misbuf_buf_rd_en),
3883 .l2t_mcu_rd_req (l2t_mcu_rd_req),
3884 .l2t_mcu_rd_dummy_req(l2t_mcu_rd_dummy_req),
3885 .misbuf_vuad_ce_err_c6(misbuf_vuad_ce_err_c6), // vuad ecc change
3886 // Inputs
3887 .arbdec_arbdp_inst_bufidhi_c8(arbdec_arbdp_inst_bufidhi_c8),
3888 .deccck_notdata_err_c8(deccck_notdata_err_c8),
3889 .tag_store_inst_c3 (tag_store_inst_c3), //BS and SR 11/07/03, store pipelining support
3890 .tag_miss_unqual_c2(tag_miss_unqual_c2_rep1),
3891 .tag_hit_unqual_c2(tag_hit_unqual_c2),
3892 .tag_hit_c3 (tag_hit_c3),
3893 .tag_lru_way_c4 (tag_lru_way_c4[3:0]),
3894 .tag_rdma_vld_px0_p(tag_rdma_vld_px0_p),
3895 .tag_misbuf_rdma_reg_vld_c2(tag_misbuf_rdma_reg_vld_c2_rep1a),
3896 .tag_hit_not_comp_c3(tag_hit_not_comp_c3),
3897 .tag_alt_tag_miss_unqual_c3(tag_alt_tag_miss_unqual_c3),
3898 .arb_arbdp_pst_with_ctrue_c2(arb_arbdp_pst_with_ctrue_c2),
3899 .arb_arbdp_misbuf_pst_no_ctrue_c2(arb_arbdp_misbuf_pst_no_ctrue_c2),
3900 .arb_decdp_cas2_inst_c2 (arb_decdp_cas2_inst_c2),
3901 .arbdec_arbdp_inst_mb_c2 (arbdec_arbdp_inst_mb_c2),
3902 .arb_decdp_pst_inst_c2 (arb_decdp_pst_inst_c2),
3903 .arb_decdp_cas1_inst_c2 (arb_decdp_cas1_inst_c2),
3904 .arb_decdp_swap_inst_c2 (arb_decdp_swap_inst_c2),
3905 .arbdec_arbdp_inst_mb_entry_c1(arbdec_arbdp_inst_mb_entry_c1[4:0]),
3906 .arb_arbdp_tecc_inst_mb_c8(arb_arbdp_tecc_inst_mb_c8),
3907 .arbdec_arbdp_rdma_inst_c1 (arbdec_arbdp_rdma_inst_c1),
3908 .arb_decdp_ld64_inst_c2 (arb_decdp_ld64_inst_c2),
3909 .arb_decdp_wr64_inst_c2 (arb_decdp_wr64_inst_c2),
3910 .arb_decdp_bis_inst_c3 (arb_decdp_bis_inst_c3),
3911 .arb_csr_st_c2 (arb_csr_st_c2),
3912 .arb_evict_vld_c2 (arb_evict_vld_c2),
3913 .arb_misbuf_inst_vld_c2(arb_misbuf_inst_vld_c2),
3914 .arb_pst_ctrue_en_c8(arb_pst_ctrue_en_c8),
3915 .arb_pf_ice_inst_c2(arb_pf_ice_inst_c2),
3916 .arb_pf_ice_inst_c7(arb_pf_ice_inst_c7),
3917 .arb_misbuf_hit_off_c1(arb_misbuf_hit_off_c1),
3918 .arb_evict_tecc_vld_c2(arb_evict_tecc_vld_c2),
3919 .arbdec_arbdp_inst_dep_c2 (arbdec_arbdp_inst_dep_c2),
3920 .arbadr_arbdp_addr_c1c2comp_c1(arbadr_arbdp_addr_c1c2comp_c1),
3921 .arbadr_arbdp_addr_c1c3comp_c1(arbadr_arbdp_addr_c1c3comp_c1),
3922 .arbadr_idx_c1c2comp_c1 (arbadr_misbuf_idx_c1c2comp_c1),
3923 .arbadr_idx_c1c3comp_c1 (arbadr_misbuf_idx_c1c3comp_c1),
3924 .arb_misbuf_cas1_hit_c8(arb_misbuf_cas1_hit_c8),
3925 .arb_misbuf_ctrue_c9(arb_misbuf_ctrue_c9),
3926 .arb_misbuf_mbsel_c1(arb_misbuf_mbsel_c1),
3927 .deccck_uncorr_err_c8 (deccck_uncorr_err_c8),
3928 // .deccck_corr_err_c8 (deccck_corr_err_c8),
3929 .vlddir_vd_ce_c2(vlddir_vd_ce_c2[0]),
3930 .filbuf_tag_hit_frm_mb_c2(filbuf_misbuf_tag_hit_frm_mb_c2),
3931 .deccck_spcd_corr_err_c8(deccck_spcd_corr_err_c8),
3932 .deccck_spcfb_corr_err_c8(deccck_spcfb_corr_err_c8),
3933 .filbuf_misbuf_match_c2(filbuf_misbuf_match_c2),
3934 .filbuf_misbuf_stinst_match_c2(filbuf_misbuf_stinst_match_c2),
3935 .filbuf_misbuf_entry_avail(filbuf_misbuf_entry_avail),
3936 .filbuf_fbf_ready_miss_r1 (filbuf_fbf_ready_miss_r1),
3937 .filbuf_fbf_enc_ld_mbid_r1 (filbuf_fbf_enc_ld_mbid_r1[4:0]),
3938 .filbuf_fbf_st_or_dep_rdy_c4(filbuf_fbf_st_or_dep_rdy_c4),
3939 .filbuf_fbf_enc_dep_mbid_c4 (filbuf_fbf_enc_dep_mbid_c4[4:0]),
3940 .filbuf_fb_count_eq_0 (filbuf_fb_count_eq_0),
3941 .filbuf_misbuf_fbid_d2 (filbuf_misbuf_fbid_d2[2:0]),
3942 .filbuf_match_c3 (filbuf_match_c3),
3943 .filbuf_misbuf_nofill_d2(filbuf_misbuf_nofill_d2),
3944 .wbuf_hit_unqual_c2 (wbuf_hit_unqual_c2),
3945 .wbuf_misbuf_dep_rdy_en(wbuf_misbuf_dep_rdy_en),
3946 .wbuf_misbuf_dep_mbid(wbuf_misbuf_dep_mbid[4:0]),
3947 .rdmat_hit_unqual_c2(rdmat_hit_unqual_c2),
3948 .rdmat_misbuf_dep_mbid(rdmat_misbuf_dep_mbid[4:0]),
3949 .rdmat_misbuf_dep_rdy_en(rdmat_misbuf_dep_rdy_en),
3950 .tag_misbuf_par_err_c3(tag_misbuf_par_err_c3),
3951 .mcu_l2t_rd_ack (mcu_l2t_rd_ack),
3952 .csr_l2_bypass_mode_on (csr_misbuf_l2off), // Templated
3953 .csr_l2_dir_map_on (csreg_misbuf_l2_dir_map_on),
3954 .scan_in(misbuf_scanin),
3955 .scan_out(misbuf_scanout),
3956 .l2clk (l2clk),
3957 .arb_tecc_c2 (arb_tecc_c2),
3958 .tag_misbuf_int_ack_c3(tag_misbuf_int_ack_c3),
3959 .arbdec_pf_ice_inst_c1(arbdec_pf_ice_inst_c1),
3960 .arb_inst_vld_c2(arb_inst_vld_c2),
3961 .arb_decdp_wr8_inst_c2(arb_decdp_wr8_inst_c2),
3962 .usaloc_ua_ce_c2(usaloc_ua_ce_c2),
3963 .misbuf_vuad_ce_instr_ack_c2(misbuf_vuad_ce_instr_ack_c2),
3964 .arb_decdp_cas2_from_mb_c2(arb_decdp_cas2_from_mb_c2),
3965 .filbuf_misbuf_ue_offmode_c7(filbuf_misbuf_ue_offmode_c7),
3966 .filbuf_misbuf_ce_offmode_c7(filbuf_misbuf_ce_offmode_c7),
3967 .misbuf_arb_hit_c3(misbuf_arb_hit_c3),
3968 .arb_misbuf_inval_inst_c2(arb_misbuf_inval_inst_c2),
3969 .misbuf_notdata_err_c1(misbuf_notdata_err_c1),
3970 .misbuf_uncorr_err_c1(misbuf_uncorr_err_c1),
3971 .l2t_mb2_run(l2t_mb2_run));
3972
3973
3974
3975n2_l2t_dp_32x128_cust mbdata(
3976 // Outputs
3977 .dout (mb_data_read_data[127:0]), // Templated
3978 // Inputs
3979 .din ({mbdata_din[127:64],mbdata_inst_data_c8[63:0]}),
3980 //.din ({10'b0,arbdec_snpd_ecc_c8[6:0],misbuf_mbentry_c8[4:0],mbdata_inst_tecc_c8[5:0],misbuf_evict_c8,misbuf_dep_c8,misbuf_tecc_c8,4'b0,arbdp_inst_c8[`L2_POISON:`L2_SZ_LO],mbdata_inst_data_c8[63:0]}), // Templated
3981 // BS and SR 11/12/03 N2 Xbar Packet format change
3982 .rd_wl (mb_read_wl[31:0]), // Templated
3983 .wr_wl (mb_data_write_wl[31:0]), // Templated
3984 .read_en (misbuf_buf_rd_en), // Templated
3985 .wr_en (mbdata_wr_en_c8), // Templated
3986 .tcu_array_wr_inhibit (array_wr_inhibit), // Templated
3987 .tcu_aclk(aclk),
3988 .tcu_bclk(bclk),
3989 .tcu_pce_ov(ce_ovrd),
3990 .pce(1'b1),
3991 .scan_in(mbdata_scanin),
3992 .scan_out(mbdata_scanout),
3993 .l2clk (l2clk), // Templated
3994 .tcu_se_scancollar_in (tcu_se_scancollar_in),
3995 .tcu_scan_en(tcu_scan_en)); // Templated
3996
3997
3998
3999n2_com_cm_32x40_cust mbtag
4000 (
4001 .dout(mb_read_data[41:0]),
4002 .match(mb_cam_match[31:0]),
4003 .match_idx(mb_cam_match_idx[31:0]),
4004 .adr_w(mb_write_wl[31:0]),
4005 .din(mb_write_addr[41:0]), // C3 PH1 write.
4006 .write_en(mbtag_wr_en_c2),
4007 .adr_r(mb_read_wl[31:0]),
4008 .lookup_en(arb_mb_camen_px2),
4009 .key(arbadr_mbcam_addr_px2_buff[41:7]),
4010 .tcu_scan_en(tcu_scan_en),
4011 .scan_in(mbtag_scanin),
4012 .scan_out(mbtag_scanout),
4013 .l2clk(l2clk),
4014 .tcu_se_scancollar_in(tcu_se_scancollar_in),
4015 .tcu_array_wr_inhibit(array_wr_inhibit),
4016 .read_en(misbuf_buf_rd_en),
4017 .tcu_aclk(aclk),
4018 .tcu_bclk(bclk),
4019 .tcu_pce_ov(ce_ovrd),
4020 .pce(1'b1),
4021 .tcu_clk_stop(1'b0),
4022 .tcu_array_bypass (tcu_array_bypass));
4023
4024
4025
4026
4027l2t_filbuf_ctl filbuf(
4028 .tcu_pce_ov(ce_ovrd),
4029 .tcu_aclk(aclk),
4030 .tcu_bclk(bclk),
4031 .tcu_scan_en(tcu_scan_en),
4032 .l2t_mb2_fbtag_wr_en (l2t_mb2_fbtag_wr_en),
4033 .l2t_mb2_fbtag_rd_en (l2t_mb2_fbtag_rd_en),
4034 .l2t_mb2_addr (l2t_mb2_addr[2:0]),
4035 .filbuf_fbtag_wr_ptr (filbuf_fbtag_wr_ptr[7:0]),
4036 .filbuf_fbtag_wr_en (filbuf_fbtag_wr_en),
4037 .filbuf_buf_rd_en (filbuf_buf_rd_en),
4038 .filbuf_fbtag_rd_ptr (filbuf_fbtag_rd_ptr[7:0]),
4039 .fb_cam_match (fb_cam_match[7:0]),
4040 .fb_mbist_cam_hit (fb_mbist_cam_hit),
4041 .fb_mbist_cam_sel(mbist_cam_sel[1]),
4042 .mbdata_filbuf_mbf_entry(mb_data_read_data_rep[`MBD_ECC_HI_PLUS5:`MBD_ECC_HI_PLUS1]), // MBID, BS & SR 11/04/03, MB grows to 32
4043 .mbdata_filbuf_rqtyp_d1(mb_data_read_data_rep[`MBD_RQ_HI:`MBD_RQ_LO]),
4044 .mbdata_filbuf_rsvd_d1(mb_data_read_data_rep[`MBD_RSVD]),
4045 .wmr_l (wmr_l),
4046 .filbuf_dis_nderr_c3 (filbuf_dis_nderr_c3[1:0]),
4047 // Outputs
4048 .filbuf_tag_evict_way_c3 (filbuf_tag_evict_way_c3[3:0]),
4049 .filbuf_tag_hit_c2 (filbuf_tag_hit_c2),
4050 .filbuf_misbuf_tag_hit_frm_mb_c2(filbuf_misbuf_tag_hit_frm_mb_c2),
4051 .filbuf_arb_tag_hit_frm_mb_c2(filbuf_arb_tag_hit_frm_mb_c2),
4052 .filbuf_fbd_rd_en_c2 (filbuf_fbd_rd_en_c2),
4053 .filbuf_fbd_rd_entry_c2(filbuf_fbd_rd_entry_c2[2:0]),
4054 .filbuf_mcu_l2t_chunk_id_r1(filbuf_mcu_l2t_chunk_id_r1[1:0]),
4055 .filbuf_mcu_l2t_data_vld_r1(filbuf_mcu_l2t_data_vld_r1),
4056 .filbuf_fbd_wr_entry_r1(filbuf_fbd_wr_entry_r1[2:0]),
4057 .l2t_mcu_rd_req_id (l2t_mcu_rd_req_id[2:0]),
4058 .filbuf_fb_count_eq_0 (filbuf_fb_count_eq_0),
4059 .filbuf_misbuf_entry_avail(filbuf_misbuf_entry_avail),
4060 .filbuf_misbuf_match_c2 (filbuf_misbuf_match_c2),
4061 .filbuf_misbuf_fbid_d2 (filbuf_misbuf_fbid_d2[2:0]),
4062 .filbuf_fbf_enc_ld_mbid_r1 (filbuf_fbf_enc_ld_mbid_r1[4:0]),
4063 .filbuf_fbf_ready_miss_r1 (filbuf_fbf_ready_miss_r1),
4064 .filbuf_fbf_enc_dep_mbid_c4 (filbuf_fbf_enc_dep_mbid_c4[4:0]),
4065 .filbuf_fbf_st_or_dep_rdy_c4 (filbuf_fbf_st_or_dep_rdy_c4),
4066 .filbuf_misbuf_nofill_d2(filbuf_misbuf_nofill_d2),
4067 .filbuf_misbuf_stinst_match_c2(filbuf_misbuf_stinst_match_c2),
4068 .filbuf_l2d_fb_hit_c3 (l2t_l2d_fb_hit_c3),
4069 .filbuf_vuad_bypassed_c3(filbuf_vuad_bypassed_c3),
4070 .filbuf_arb_l2rd_en (filbuf_arb_l2rd_en),
4071 .filbuf_arbdp_way_px2 (filbuf_arbdp_way_px2[3:0]),
4072 .filbuf_arbdp_tecc_px2 (filbuf_arbdp_tecc_px2),
4073 .filbuf_arbdp_entry_px2(filbuf_arbdp_entry_px2[2:0]),
4074 .filbuf_arb_vld_px1 (filbuf_arb_vld_px1),
4075 .filbuf_corr_err_c8 (filbuf_corr_err_c8),
4076 .filbuf_uncorr_err_c8 (filbuf_uncorr_err_c8),
4077 .filbuf_mcu_scb_mecc_err_d1 (filbuf_mcu_scb_mecc_err_d1),
4078 .filbuf_mcu_scb_secc_err_d1 (filbuf_mcu_scb_secc_err_d1),
4079 .filbuf_spc_corr_err_c6(filbuf_spc_corr_err_c6),
4080 .filbuf_spc_uncorr_err_c6(filbuf_spc_uncorr_err_c6),
4081 .filbuf_spc_rd_vld_c6 (filbuf_spc_rd_vld_c6),
4082 .filbuf_bsc_corr_err_c12(filbuf_bsc_corr_err_c12),
4083 .filbuf_ld64_fb_hit_c12(filbuf_ld64_fb_hit_c12),
4084 .filbuf_dis_cerr_c3 (filbuf_dis_cerr_c3),
4085 .filbuf_dis_uerr_c3 (filbuf_dis_uerr_c3),
4086 // Inputs
4087 //.l2t_l2d_stdecc_c2(l2t_l2d_stdecc_c2[77:0]),
4088 .misbuf_vuad_ce_err_c8(misbuf_vuad_ce_err_c8),
4089 .rdmat_rdmard_cerr_c12 (rdmat_rdmard_cerr_c12),
4090 .rdmat_rdmard_uerr_c12 (rdmat_rdmard_uerr_c12),
4091 .rdmat_rdmard_notdata_c12 (rdmat_rdmard_notdata_c12),
4092 .rdmat_ev_cerr_r6 (rdmat_ev_cerr_r6),
4093 .rdmat_ev_uerr_r6 (rdmat_ev_uerr_r6),
4094 .misbuf_filbuf_next_vld_c4(misbuf_filbuf_next_vld_c4),
4095 .misbuf_filbuf_next_link_c4(misbuf_filbuf_next_link_c4[4:0]),
4096 .misbuf_mbf_delete_c4 (misbuf_mbf_delete_c4),
4097 .misbuf_hit_c4 (misbuf_hit_c4),
4098 .misbuf_mbf_insert_c4 (misbuf_mbf_insert_c4),
4099 .misbuf_filbuf_mcu_pick(misbuf_filbuf_mcu_pick),
4100 .misbuf_filbuf_fbid (misbuf_filbuf_fbid[2:0]),
4101 .misbuf_filbuf_way (misbuf_filbuf_way[3:0]),
4102 .misbuf_filbuf_way_fbid_vld(misbuf_filbuf_way_fbid_vld),
4103 .misbuf_mbf_insert_mbid_c4 (misbuf_mbf_insert_mbid_c4[4:0]),
4104 .arb_decdp_imiss_inst_c2 (arb_decdp_imiss_inst_c2),
4105 //.arb_decdp_ld_inst_c2 (arb_decdp_ld_inst_c2),
4106 .arbdec_arbdp_inst_mb_entry_c1(arbdec_arbdp_inst_mb_entry_c1[2:0]),
4107 .arb_decdp_cas1_inst_c2 (arb_decdp_cas1_inst_c2),
4108 .arbdec_arbdp_rdma_inst_c1 (arbdec_arbdp_rdma_inst_c1),
4109 .tag_misbuf_rdma_reg_vld_c2(tag_misbuf_rdma_reg_vld_c2_rep1b),
4110 .deccck_scrd_uncorr_err_c8(deccck_scrd_uncorr_err_c8),
4111 .deccck_scrd_corr_err_c8(deccck_scrd_corr_err_c8),
4112 .deccck_bscd_corr_err_c8(deccck_bscd_corr_err_c8),
4113 .deccck_bscd_uncorr_err_c8(deccck_bscd_uncorr_err_c8),
4114 .deccck_bscd_notdata_err_c8(deccck_bscd_notdata_err_c8),
4115 .tagdp_tag_error_c8 (tagdp_tag_error_c8),
4116 .tag_rd64_complete_c11(tag_rd64_complete_c11),
4117 .tag_cerr_ack_tmp_c4 (tag_cerr_ack_tmp_c4),
4118 .tag_uerr_ack_tmp_c4 (tag_uerr_ack_tmp_c4),
4119 .tag_spc_rd_cond_c3 (tag_spc_rd_cond_c3),
4120 .csr_filbuf_scrub_ready(csr_filbuf_scrub_ready),
4121 .arb_filbuf_fbsel_c1(arb_filbuf_fbsel_c1),
4122// .arb_fill_vld_c2 (arb_fill_vld_c2),
4123 .arb_fill_vld_c2 (arb_fill_vld_c2_rep1),
4124 .arb_filbuf_hit_off_c1(arb_filbuf_hit_off_c1),
4125// .arb_filbuf_inst_vld_c2(arb_filbuf_inst_vld_c2),
4126 .arb_decdp_wr8_inst_c2 (arb_decdp_wr8_inst_c2),
4127 .arbdec_arbdp_inst_mb_c2 (arbdec_arbdp_inst_mb_c2),
4128 .arb_decdp_ld64_inst_c2 (arb_decdp_ld64_inst_c2),
4129 .csr_l2_bypass_mode_on (csr_filbuf_l2off), // Templated
4130 .csr_l2_dir_map_on (csreg_filbuf_l2_dir_map_on),
4131 .mcu_l2t_data_vld_r0(mcu_l2t_data_vld_r0),
4132 .mcu_l2t_rd_req_id_r0(mcu_l2t_rd_req_id_r0[2:0]),
4133 .mcu_l2t_chunk_id_r0(mcu_l2t_chunk_id_r0[1:0]),
4134 .mcu_l2t_secc_err_r2(mcu_l2t_secc_err_r2),
4135 .mcu_l2t_mecc_err_r2(mcu_l2t_mecc_err_r2),
4136 .mcu_l2t_scb_mecc_err(mcu_l2t_scb_mecc_err),
4137 .mcu_l2t_scb_secc_err(mcu_l2t_scb_secc_err),
4138 .tag_rdma_gate_off_c2(tag_rdma_gate_off_c2_rep1),
4139 .scan_in(filbuf_scanin),
4140 .scan_out(filbuf_scanout),
4141 .l2clk (l2clk),
4142 .filbuf_misbuf_ue_offmode_c7(filbuf_misbuf_ue_offmode_c7),
4143 .filbuf_misbuf_ce_offmode_c7(filbuf_misbuf_ce_offmode_c7),
4144 .arb_inst_vld_c2_prev(arb_inst_vld_c2_prev),
4145 .l2t_mb2_run(l2t_mb2_run),
4146 .mbist_run(mbist_run));
4147
4148
4149n2_com_cm_8x40_cust fbtag
4150 (
4151 .dout(fb_read_data[39:0]), // BS and SR 8 deep change 3/3/04
4152 .match(fb_cam_match[7:0]),
4153 .match_idx(fb_match_idx_unused[7:0]),
4154 .adr_w(filbuf_fbtag_wr_ptr[7:0]),
4155 .din (fbtag_din[39:0]),
4156 //.din({evctag_mb_read_data[39:6],mb_data_read_data[`MBD_ECC_HI:`MBD_ECC_LO]}),
4157 .write_en(filbuf_fbtag_wr_en),
4158 .adr_r(filbuf_fbtag_rd_ptr[7:0]),
4159 .lookup_en(arb_inst_vld_c1_v1),
4160 .key(lkup_addr_c1[39:7]),
4161 .tcu_array_wr_inhibit(array_wr_inhibit),
4162 .tcu_scan_en(tcu_scan_en),
4163 .scan_in(fbtag_scanin),
4164 .scan_out(fbtag_scanout),
4165 .l2clk(l2clk),
4166 .read_en(filbuf_buf_rd_en),
4167 .tcu_aclk(aclk),
4168 .tcu_bclk(bclk),
4169 .tcu_pce_ov(ce_ovrd),
4170 .pce(1'b1),
4171 .tcu_clk_stop(1'b0),
4172 .tcu_array_bypass (tcu_array_bypass),
4173 .tcu_se_scancollar_out(tcu_se_scancollar_out),
4174 .tcu_se_scancollar_in(tcu_se_scancollar_in)
4175 );
4176
4177
4178
4179l2t_arbdat_dp arbdat (
4180 .tcu_pce_ov(ce_ovrd),
4181 .tcu_aclk(aclk),
4182 .tcu_bclk(bclk),
4183 .tcu_scan_en(tcu_scan_en),
4184 .tcu_clk_stop(1'b0),
4185 .arbdat_mbdata_inst_data_c8(mbdata_inst_data_c8[63:0]),
4186 .arbdat_arbdata_wr_data_c2(arbdata_wr_data_c2[38:0]),
4187 // Outputs
4188 .tag_l2d_col_offset_c2(l2t_l2d_col_offset_c2[3:0]),
4189 .st_ack_data(st_ack_data[63:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
4190 .arbdat_arbdp_oque_int_ret_c7(arbdat_arbdp_oque_int_ret_c7[17:0]),
4191 .arbdat_arbdp_store_data_c2(l2t_l2d_stdecc_c2[77:0]),
4192 .arbdat_csr_inst_wr_data_c8(arbdat_csr_inst_wr_data_c8[63:0]),
4193 .arbdat_word_lower_cmp_c8(arbdat_word_lower_cmp_c8),
4194 .arbdat_word_upper_cmp_c8(arbdat_word_upper_cmp_c8),
4195 // Inputs
4196 .arbdec_arbdp_inst_bufidhi_c1(arbdec_arbdp_inst_bufidhi_c1),
4197 .sel_diag_store_data_c7 (sel_diag_store_data_c7), // BS and SR 12/22/03, store ack generation for diagnostic store
4198
4199 .ique_iq_arbdp_data_px2(ique_iq_arbdp_data_px2[63:0]),
4200 .snpd_snpq_arbdp_data_px2(snpd_snpq_arbdp_data_px2[63:0]),
4201 .mb_data_read_data(mb_data_read_data[63:0]),
4202 .mbdata_cmp_sel(mbdata_cmp_sel[3:0]),
4203 .l2t_mb2_wdata(l2t_mb2_wdata[7:0]),
4204 .misbuf_buf_rd_en(misbuf_buf_rd_en),
4205 .misbuf_arb_l2rd_en(misbuf_arb_l2rd_en),
4206 .arb_mux2_snpsel_px2(arb_arbdat_mux2_snpsel_px2),
4207 .arb_mux3_bufsel_px2(arb_arbdat_mux3_bufsel_px2),
4208 .arb_mux4_c1sel_px2(arb_arbdat_mux4_c1sel_px2),
4209 .arb_decc_data_sel_c9(arb_decc_data_sel_c9),
4210 .arb_bist_or_diag_acc_c1(arb_bist_or_diag_acc_c1),
4211 .arbdec_arbdp_poison_c1(arbdec_arbdp_poison_c1),
4212 .bist_data_data_c1(mbist_write_data[7:0]), // Templated
4213 .bist_data_enable_c1(mbist_arb_l2d_write), // Templated
4214 .decc_arbdp_data_c8(decc_arbdp_data_c8[63:0]),
4215 .arb_dword_mask_c8(arb_dword_mask_c8[7:0]),
4216 .scan_in(arbdat_scanin),
4217 .scan_out(arbdat_scanout),
4218 .l2clk (l2clk),
4219 .tcu_dectest(tcu_dectest),
4220 .tcu_muxtest(tcu_muxtest),
4221 .mbdata_fail_bot(mbdata_fail_bot),
4222 .tag_data_array_wr_active_c1(tag_data_array_wr_active_c1),
4223 .l2t_mb2_run(l2t_mb2_run),
4224 .arb_inst_vld_c2_prev(arb_inst_vld_c2_prev),
4225 .dec_col_offset_prev_c1(dec_col_offset_prev_c1[3:0]),
4226 .arbadr_arbdp_addr5to4_c1(arbadr_arbdp_addr5to4_c1[1:0]));
4227
4228
4229l2t_arbadr_dp arbadr (
4230 .tcu_pce_ov(ce_ovrd),
4231 .tcu_aclk(aclk),
4232 .tcu_bclk(bclk),
4233 .tcu_scan_en(tcu_scan_en),
4234 .tcu_clk_stop(1'b0),
4235 .tcu_muxtest(tcu_muxtest),
4236 .tcu_dectest(tcu_dectest),
4237 .l2t_mb2_run (l2t_mb2_run),
4238 .arbadr_arbdp_cam_addr_px2(arbdp_cam_addr_px2[39:0]),
4239 .arbadr_mbcam_addr_px2(arbadr_mbcam_addr_px2[41:7]),
4240 // .arbadr_arbdp_dbg_addr_c3(arbdp_dbg_addr_c3[5:2]),
4241 .arbdat_arbdata_wr_data_c2(arbdata_wr_data_c2[27:0]),
4242 /*AUTOINST*/
4243 // Outputs
4244 .arbadr_csr_debug_addr (arbadr_csr_debug_addr[33:2]),
4245 // .arbadr_2bnk_true_enbld_dist(arbadr_2bnk_true_enbld_dist), // BS 03/25/04 for partial bank/core modes support
4246 // .arbadr_4bnk_true_enbld_dist(arbadr_4bnk_true_enbld_dist), // BS 03/25/04 for partial bank/core modes support
4247 // .arbadr_ncu_l2t_pm_n_dist(arbadr_ncu_l2t_pm_n_dist), // BS 03/25/04 for partial bank/core modes support
4248
4249 .arbadr_dirvec_2bnk_true_enbld_dist (arbadr_dirvec_2bnk_true_enbld_dist),
4250 .arbadr_dirvec_4bnk_true_enbld_dist (arbadr_dirvec_4bnk_true_enbld_dist),
4251 .arbadr_dirvec_ncu_l2t_pm_n_dist (arbadr_dirvec_ncu_l2t_pm_n_dist),
4252 .arbadr_evctag_2bnk_true_enbld_dist (arbadr_evctag_2bnk_true_enbld_dist),
4253 .arbadr_evctag_4bnk_true_enbld_dist (arbadr_evctag_4bnk_true_enbld_dist),
4254 .arbadr_evctag_ncu_l2t_pm_n_dist (arbadr_evctag_ncu_l2t_pm_n_dist),
4255 .arbadr_tagd_2bnk_true_enbld_dist (arbadr_tagd_2bnk_true_enbld_dist),
4256 .arbadr_tagd_4bnk_true_enbld_dist (arbadr_tagd_4bnk_true_enbld_dist),
4257 .arbadr_tagd_ncu_l2t_pm_n_dist (arbadr_tagd_ncu_l2t_pm_n_dist),
4258 .arbadr_arbctl_2bnk_true_enbld_dist (arbadr_arbctl_2bnk_true_enbld_dist),
4259 .arbadr_arbctl_4bnk_true_enbld_dist (arbadr_arbctl_4bnk_true_enbld_dist),
4260 .arbadr_arbctl_ncu_l2t_pm_n_dist (arbadr_arbctl_ncu_l2t_pm_n_dist),
4261
4262 .arbadr_arbdp_addr87_c2(arbadr_arbdp_addr87_c2[1:0]), // BS 03/25/04 for partial bank/core modes support
4263 .arbadr_dirvec_addr3_c7(arbadr_dirvec_addr3_c7), // BS and SR 11/12/03 N2 Xbar Packet format change
4264 // add3 for store ack including diagnostic stores
4265 .arbadr_arbdp_tag_idx_px2(arbadr_arbdp_tag_idx_px2[8:0]),
4266 .arbadr_arbdp_vuad_idx1_px2(arbadr_arbdp_vuad_idx1_px2[8:0]),
4267 .arbadr_arbdp_vuad_idx2_px2(arbadr_arbdp_vuad_idx2_px2[8:0]),
4268 .arbadr_arbdp_tagdata_px2(arbadr_arbdp_tagdata_px2[27:6]),
4269 .arbadr_arbdp_new_addr5to4_px2(arbadr_arbdp_new_addr5to4_px2[1:0]),
4270 .arbadr_arbdp_addr_c1c2comp_c1(arbadr_arbdp_addr_c1c2comp_c1),
4271 .arbadr_arbdp_addr_c1c3comp_c1(arbadr_arbdp_addr_c1c3comp_c1),
4272 .arbadr_idx_c1c2comp_c1_n(arbadr_idx_c1c2comp_c1_n),
4273 .arbadr_idx_c1c3comp_c1_n(arbadr_idx_c1c3comp_c1_n),
4274 .arbadr_idx_c1c4comp_c1_n(arbadr_idx_c1c4comp_c1_n),
4275 .arbadr_idx_c1c5comp_c1_n(arbadr_idx_c1c5comp_c1_n),
4276 // .arbadr_vuad_idx_c1c2comp_c1(arbadr_vuad_idx_c1c2comp_c1),
4277 // .arbadr_vuad_idx_c1c3comp_c1(arbadr_vuad_idx_c1c3comp_c1),
4278 .arbadr_misbuf_idx_c1c2comp_c1(arbadr_misbuf_idx_c1c2comp_c1),
4279 .arbadr_misbuf_idx_c1c3comp_c1(arbadr_misbuf_idx_c1c3comp_c1),
4280 //.arbadr_idx_c1c4comp_c1(arbadr_idx_c1c4comp_c1),
4281 //.arbadr_idx_c1c5comp_c1(arbadr_idx_c1c5comp_c1),
4282 .arbadr_arbdp_ioaddr_c1(arbadr_arbdp_ioaddr_c1[39:32]),
4283 .arbadr_arbdp_addr5to4_c1(arbadr_arbdp_addr5to4_c1[1:0]),
4284 .arbadr_arbdp_addr3to2_c1(arbadr_arbdp_addr3to2_c1[1:0]),
4285 .arbadr_arbdp_diag_wr_way_c2(arbdp_diag_wr_way_c2[3:0]),
4286 .l2t_l2d_set_c2(l2t_l2d_set_c2[8:0]), // Templated
4287 .arbadr_arbaddr_addr22_c2(arbaddr_addr22_c2),
4288 .arbadr_arbdp_addr_start_c2(arbadr_arbdp_addr_start_c2),
4289 .arbadr_arbaddr_idx_c3(arbaddr_idx_c3[10:0]),
4290 .arbadr_dir_cam_addr_c3(arbadr_dir_cam_addr_c3[39:7]),
4291 .arbadr_arbdp_addr11to4_c3(arbadr_arbdp_addr11to4_c3[7:0]),
4292 .arbadr_arbdp_addr5to4_c3(arbadr_arbdp_addr5to4_c3[1:0]),
4293 .arbadr_c1_addr_eq_wb_c4(arbadr_c1_addr_eq_wb_c4),
4294 .arbadr_arbdp_rdmat_addr_c6(arbadr_arbdp_rdmat_addr_c6[5:2]),
4295 .arbadr_arbdp_waddr_c6(arbadr_arbdp_waddr_c6[1:0]),
4296 .arbadr_arbdp_word_addr_c6(arbadr_arbdp_word_addr_c6[4:0]),
4297 .arbadr_arbdp_byte_addr_c6(arbadr_arbdp_byte_addr_c6[2:0]), // // Phase 2 : SIU inteface and packet format change 2/7/04
4298 .arbadr_arbdp_addr22_c7(arbadr_arbdp_addr22_c7),
4299 .arbadr_arbdp_csr_addr_c9(arbdp_csr_addr_c9[39:4]),
4300 .arbadr_rdmard_addr_c12(arbadr_rdmard_addr_c12[39:6]),
4301 .arbadr_arbdp_line_addr_c6(arbadr_arbdp_line_addr_c6[5:4]),
4302 .arbadr_arbdp_oque_l1_index_c7(arbadr_arbdp_oque_l1_index_c7[11:6]),
4303 .arbadr_addr2_c8(arbadr_addr2_c8),
4304 .arbadr_data_ecc_idx(arbadr_data_ecc_idx[8:0]),
4305 .arbadr_tag_wrdata_px2(arbadr_tag_wrdata_px2[27:0]),
4306 // Inputs
4307 .ncu_l2t_pm(ncu_l2t_pm), // BS 03/25/04 for partial bank/core modes support
4308 .ncu_l2t_ba01(ncu_l2t_ba01), // BS 03/25/04 for partial bank/core modes support
4309 .ncu_l2t_ba23(ncu_l2t_ba23), // BS 03/25/04 for partial bank/core modes support
4310 .ncu_l2t_ba45(ncu_l2t_ba45), // BS 03/25/04 for partial bank/core modes support
4311 .ncu_l2t_ba67(ncu_l2t_ba67), // BS 03/25/04 for partial bank/core modes support
4312 .sel_diag_store_data_c7 (sel_diag_store_data_c7), // BS and SR 12/22/03, store ack generation for diagnostic store
4313 .ique_iq_arbdp_addr_px2(ique_iq_arbdp_addr_px2[39:0]),
4314 .snpd_snpq_arbdp_addr_px2(snpd_snpq_arbdp_addr_px2[39:0]),
4315 .mbist_tag_lkup_addr (mbist_tag_lkup_addr[27:0]),
4316 .evctag_addr_px2(evctag_addr_px2[39:0]),
4317 .mb2_l2t_wk1_cam_init (mb2_l2t_wk1_cam_init),
4318 .mb2_l2t_wk1_cam_shift (mb2_l2t_wk1_cam_shift),
4319 .tagd_evict_tag_c4(tagd_evict_tag_c4[`TAG_WIDTH_LESS1:0]),
4320 .tagd_evict_tag_c3(tagd_evict_tag_c3[`TAG_WIDTH_LESS1:0]),
4321 .arb_mux2_snpsel_px2(arb_arbadr_mux2_snpsel_px2),
4322 .arb_mux3_bufsel_px1 (arb_mux3_bufsel_px1),
4323 .arb_mux4_c1sel_px2(arb_arbadr_mux4_c1sel_px2),
4324 .arb_inc_tag_ecc_cnt_c3_n(arb_inc_tag_ecc_cnt_c3_n),
4325 .arb_data_ecc_idx_reset(arb_data_ecc_idx_reset),
4326 .arb_data_ecc_idx_en(arb_data_ecc_idx_en),
4327 .arb_sel_vuad_bist_px2(arb_sel_vuad_bist_px2),
4328 .arb_sel_deccck_or_bist_idx(arb_sel_deccck_or_bist_idx),
4329 .arb_sel_diag_addr_px2(arb_sel_diag_addr_px2),
4330 .arb_sel_tecc_addr_px2(arb_sel_tecc_addr_px2),
4331 .arb_sel_deccck_addr_px2(arb_sel_deccck_addr_px2),
4332 .arb_sel_diag_tag_addr_px2(arb_sel_diag_tag_addr_px2),
4333 .arb_sel_lkup_stalled_tag_px2(arb_sel_lkup_stalled_tag_px2),
4334 .arb_imiss_hit_c10(arb_imiss_hit_c10),
4335 .tag_rd64_complete_c11(tag_rd64_complete_c11),
4336 .arb_imiss_hit_c4(arb_imiss_hit_c4),
4337 .arb_sel_c2_stall_idx_c1(arb_sel_c2_stall_idx_c1),
4338 .bist_data_set_c1(mbist_l2d_index[8:0]), // Templated, BS & SR 10/28/03
4339 .bist_data_enable_c1(mbist_arb_l2d_en), // Templated
4340 .bist_vuad_idx_px1(mbist_l2v_index[8:0]), // Templated, BS & SR 10/28/03
4341 .scan_in(arbadr_scanin),
4342 .scan_out(arbadr_scanout),
4343 .l2clk (l2clk),
4344 .arb_diag_or_tecc_write_px2(arb_diag_or_tecc_write_px2),
4345 .arb_sel_way_px2 (arb_sel_way_px2),
4346 .io_cmp_sync_en(io_cmp_sync_en),
4347 .mbist_lookupen(mbist_lookupen),
4348 .mbist_run(mbist_run),
4349 .l2t_mb2_wdata(l2t_mb2_wdata[7:0]));
4350
4351l2t_arb_ctl arb(
4352 .tcu_pce_ov(ce_ovrd),
4353 .tcu_aclk(aclk),
4354 .tcu_bclk(bclk),
4355 .tcu_scan_en(tcu_scan_en),
4356 .arb_mb_camen_px2(arb_mb_camen_px2),
4357 .wmr_l (wmr_l),
4358 .arb_inst_vld_c1(arb_inst_vld_c1),
4359 .arb_dc_ic_rd_bit_4(arb_dc_ic_rd_bit_4),
4360 // Outputs
4361 .arb_cpuid_c5 (arb_cpuid_c5[2:0]),
4362 .arb_upper_four_byte_access_c1(arb_upper_four_byte_access_c1), // BS 05/04/04 : taking out upper_four_byte_access info
4363 .arb_lower_four_byte_access_c1(arb_lower_four_byte_access_c1), // BS 05/04/04 : taking out lower_four_byte_access info
4364 .arb_decdp_mmuld_inst_c6(arb_decdp_mmuld_inst_c6), // BS and SR 11/12/03 N2 Xbar Packet format change
4365 .arb_acc_vd_c2 (arb_acc_vd_c2),
4366 .arb_acc_ua_c2 (arb_acc_ua_c2),
4367 .arb_oqu_swap_cas2_req_c2 (arb_oqu_swap_cas2_req_c2),
4368 .arb_mux1_mbsel_px2 (arb_mux1_mbsel_px2),
4369 .arb_arbdat_mux2_snpsel_px2(arb_arbdat_mux2_snpsel_px2),
4370 .arb_arbadr_mux2_snpsel_px2(arb_arbadr_mux2_snpsel_px2),
4371 .arb_mux3_bufsel_px1 (arb_mux3_bufsel_px1),
4372 .arb_arbdec_mux2_snpsel_px2(arb_arbdec_mux2_snpsel_px2),
4373
4374 .arb_arbdat_mux3_bufsel_px2 (arb_arbdat_mux3_bufsel_px2),
4375 .arb_arbdec_mux3_bufsel_px2 (arb_arbdec_mux3_bufsel_px2),
4376
4377 .arb_arbadr_mux4_c1sel_px2 (arb_arbadr_mux4_c1sel_px2),
4378 .arb_arbdat_mux4_c1sel_px2 (arb_arbdat_mux4_c1sel_px2),
4379 .arb_arbdec_mux4_c1sel_px2 (arb_arbdec_mux4_c1sel_px2),
4380
4381 .arb_data_ecc_idx_en (arb_data_ecc_idx_en),
4382 .arb_data_ecc_idx_reset(arb_data_ecc_idx_reset),
4383 .arb_sel_tecc_addr_px2 (arb_sel_tecc_addr_px2),
4384 .arb_sel_deccck_addr_px2 (arb_sel_deccck_addr_px2),
4385 .arb_sel_diag_addr_px2 (arb_sel_diag_addr_px2),
4386 .arb_sel_diag_tag_addr_px2(arb_sel_diag_tag_addr_px2),
4387 .arb_inc_tag_ecc_cnt_c3_n(arb_inc_tag_ecc_cnt_c3_n),
4388 .arb_sel_lkup_stalled_tag_px2(arb_sel_lkup_stalled_tag_px2),
4389 .arb_bist_or_diag_acc_c1(arb_bist_or_diag_acc_c1),
4390 .arb_sel_deccck_or_bist_idx(arb_sel_deccck_or_bist_idx),
4391 .arb_sel_vuad_bist_px2 (arb_sel_vuad_bist_px2),
4392 .arb_misbuf_inst_vld_c2(arb_misbuf_inst_vld_c2),
4393 // .arb_filbuf_inst_vld_c2(arb_filbuf_inst_vld_c2),
4394 .arb_inst_vld_c2(arb_inst_vld_c2),
4395 .arb_inst_vld_c2_prev(arb_inst_vld_c2_prev),
4396 .misbuf_vuad_ce_instr_c2(misbuf_vuad_ce_instr_c2),
4397 .arb_tag_inst_vld_c2(arb_tag_inst_vld_c2),
4398 .arb_wbuf_inst_vld_c2(arb_wbuf_inst_vld_c2),
4399 .arb_imiss_hit_c10(arb_imiss_hit_c10),
4400 .arb_imiss_hit_c4(arb_imiss_hit_c4),
4401 .arb_evict_c3 (arb_evict_c3),
4402 .arb_evict_c4 (arb_evict_c4),
4403 //.arb_arbdp_evict_c4 (arb_arbdp_evict_c4),
4404 .arb_dc_evict_c4 (arb_dc_evict_c4),
4405 .arb_ic_evict_c4 (arb_ic_evict_c4),
4406 .arb_inval_inst_vld_c3 (arb_inval_inst_vld_c3),
4407 .arb_sel_c2_stall_idx_c1(arb_sel_c2_stall_idx_c1),
4408 .arb_vuad_acc_px2(arb_vuad_acc_px2),
4409 .arb_tag_wr_px2 (arb_tag_wr_px2),
4410 .arb_vuad_idx2_sel_px2_n(arb_vuad_idx2_sel_px2_n),
4411 .arb_filbuf_fbsel_c1(arb_filbuf_fbsel_c1),
4412 .arb_misbuf_mbsel_c1(arb_misbuf_mbsel_c1),
4413 .arb_iqsel_px2 (arb_iqsel_px2),
4414 .arb_evict_vld_c2(arb_evict_vld_c2),
4415 .arb_inst_diag_c1(arb_inst_diag_c1),
4416 .arb_l2d_fbrd_c3 (l2t_l2d_fbrd_c3),
4417 .arb_misbuf_ctrue_c9(arb_misbuf_ctrue_c9),
4418 .arb_misbuf_cas1_hit_c8(arb_misbuf_cas1_hit_c8),
4419 .arb_pf_ice_inst_c2(arb_pf_ice_inst_c2),
4420 .arb_pf_ice_inst_c7(arb_pf_ice_inst_c7),
4421 .arb_decc_data_sel_c9(arb_decc_data_sel_c9),
4422 .arb_tecc_way_c2(arb_tecc_way_c2[3:0]),
4423 .arb_l2tag_vld_c4(arb_l2tag_vld_c4),
4424 .arb_dword_mask_c8 (arb_dword_mask_c8[7:0]),
4425 .arb_fill_vld_c2(arb_fill_vld_c2),
4426 .arb_imiss_vld_c2(arb_imiss_vld_c2),
4427 .arb_normal_tagacc_c2(arb_normal_tagacc_c2),
4428 .arb_tagd_tecc_c2(arb_tagd_tecc_c2),
4429 .arb_dir_vld_c3_l(arb_dir_vld_c3_l),
4430 .arb_dc_rd_en_c3(arb_dc_rd_en_c3),
4431 .arb_ic_rd_en_c3(arb_ic_rd_en_c3),
4432 .arb_dc_wr_en_c3(arb_dc_wr_en_c3),
4433 .arb_ic_wr_en_c3(arb_ic_wr_en_c3),
4434 .arb_dir_panel_dcd_c3(arb_dir_panel_dcd_c3[4:0]),
4435 .arb_dir_panel_icd_c3(arb_dir_panel_icd_c3[4:0]),
4436 .arb_lkup_bank_ena_dcd_c3(arb_lkup_bank_ena_dcd_c3[3:0]),
4437 .arb_lkup_bank_ena_icd_c3(arb_lkup_bank_ena_icd_c3[3:0]),
4438 .arb_inval_mask_dcd_c3(arb_inval_mask_dcd_c3[7:0]),
4439 .arb_inval_mask_icd_c3(arb_inval_mask_icd_c3[7:0]),
4440 .arb_wr_dc_dir_entry_c3(arb_wr_dc_dir_entry_c3[4:0]),
4441 .arb_wr_ic_dir_entry_c3(arb_wr_ic_dir_entry_c3[4:0]),
4442 .arb_dir_addr_c9 (arb_dir_addr_c9[10:0]),
4443 .arb_dir_wr_en_c4(arb_dir_wr_en_c4),
4444 .arb_csr_wr_en_c7(arb_csr_wr_en_c7),
4445 .arb_csr_rd_en_c7(arb_csr_rd_en_c7),
4446 .arb_evict_c5 (arb_evict_c5),
4447 .arb_waysel_gate_c2(arb_waysel_gate_c2),
4448 .arb_data_diag_st_c2(arb_data_diag_st_c2),
4449 .arb_inval_inst_c2(arb_inval_inst_c2),
4450 .arb_decdp_ld64_inst_c1(arb_decdp_ld64_inst_c1),
4451 .arb_waysel_inst_vld_c2(arb_waysel_inst_vld_c2),
4452 .ique_arb_pf_ice_px2 (ique_arb_pf_ice_px2),
4453 .arb_rdwr_inst_vld_c2(arb_rdwr_inst_vld_c2),
4454 .arb_ic_inval_vld_c7 (ic_inval_vld_c7),
4455 .arb_dc_inval_vld_c7 (dc_inval_vld_c7),
4456 .arb_inst_l2data_vld_c6(arb_inst_l2data_vld_c6),
4457 .arb_csr_wr_en_c3(arb_csr_wr_en_c3),
4458 .arb_csr_rd_en_c3(arb_csr_rd_en_c3),
4459 .arb_diag_complete_c3(arb_diag_complete_c3),
4460 .arb_tag_pst_with_ctrue_c1(arb_tag_pst_with_ctrue_c1),
4461 .arb_csr_st_c2 (arb_csr_st_c2),
4462 .arb_misbuf_hit_off_c1(arb_misbuf_hit_off_c1),
4463 .arb_pst_ctrue_en_c8(arb_pst_ctrue_en_c8),
4464 .arb_evict_tecc_vld_c2(arb_evict_tecc_vld_c2),
4465 .arb_filbuf_hit_off_c1(arb_filbuf_hit_off_c1),
4466 .arb_wbuf_hit_off_c1(arb_wbuf_hit_off_c1),
4467 .arb_inst_l2vuad_vld_c6(arb_inst_l2vuad_vld_c6),
4468 .arb_inst_l2tag_vld_c6(arb_inst_l2tag_vld_c6),
4469 .arb_decdp_tag_wr_c1(arb_decdp_tag_wr_c1),
4470 .arb_decdp_pst_inst_c2 (arb_decdp_pst_inst_c2),
4471 .arb_decdp_fwd_req_c2 (arb_decdp_fwd_req_c2),
4472 .arb_decdp_swap_inst_c2(arb_decdp_swap_inst_c2),
4473 .arb_decdp_imiss_inst_c2(arb_decdp_imiss_inst_c2),
4474 .arb_decdp_inst_int_c2 (arb_decdp_inst_int_c2),
4475 .arb_decdp_inst_int_c1 (arb_decdp_inst_int_c1),
4476 .arb_decdp_ld64_inst_c2(arb_decdp_ld64_inst_c2),
4477 .arb_decdp_bis_inst_c3 (arb_decdp_bis_inst_c3),
4478 .arb_decdp_rmo_st_c3 (arb_decdp_rmo_st_c3),
4479 .arb_decdp_strst_inst_c2(arb_decdp_strst_inst_c2),
4480 .arb_decdp_wr8_inst_c2 (arb_decdp_wr8_inst_c2),
4481 .arb_decdp_wr64_inst_c2(arb_decdp_wr64_inst_c2),
4482 .arb_decdp_st_inst_c2 (arb_decdp_st_inst_c2),
4483 .arb_decdp_st_inst_c3 (arb_decdp_st_inst_c3),
4484 .arb_decdp_st_with_ctrue_c2(arb_decdp_st_with_ctrue_c2),
4485 .arb_decdp_ld_inst_c2 (arb_decdp_ld_inst_c2),
4486 .arb_arbdp_pst_with_ctrue_c2(arb_arbdp_pst_with_ctrue_c2),
4487 .arb_decdp_cas1_inst_c2(arb_decdp_cas1_inst_c2),
4488 .arb_decdp_cas2_inst_c2(arb_decdp_cas2_inst_c2),
4489 .arb_decdp_cas2_from_mb_c2(arb_decdp_cas2_from_mb_c2),
4490 .filbuf_tag_hit_frm_mb_c2(filbuf_arb_tag_hit_frm_mb_c2_rep),
4491 // .arb_decdp_cas2_from_mb_ctrue_c2(arb_decdp_cas2_from_mb_ctrue_c2),
4492 .arb_inst_l2vuad_vld_c3(arb_inst_l2vuad_vld_c3),
4493 .arb_decdp_pf_inst_c5 (arb_decdp_pf_inst_c5),
4494 .arb_decdp_strld_inst_c6(arb_decdp_strld_inst_c6),
4495 .arb_decdp_atm_inst_c6 (arb_decdp_atm_inst_c6),
4496 .arb_store_err_c8 (arb_store_err_c8),
4497 .arb_arbdp_tecc_inst_mb_c8(arb_arbdp_tecc_inst_mb_c8),
4498 .arb_tagd_perr_vld_c2(arb_tagd_perr_vld_c2),
4499 .arb_arbdp_tag_pst_no_ctrue_c2(arb_arbdp_tag_pst_no_ctrue_c2),
4500 .arb_arbdp_misbuf_pst_no_ctrue_c2(arb_arbdp_misbuf_pst_no_ctrue_c2),
4501 .arb_arbdp_vuadctl_pst_no_ctrue_c2(arb_arbdp_vuadctl_pst_no_ctrue_c2),
4502 .arb_tecc_c2 (arb_tecc_c2),
4503 .arb_vuadctl_no_bypass_px2(arb_vuadctl_no_bypass_px2),
4504 .arb_sel_way_px2 (arb_sel_way_px2),
4505 .arb_diag_or_tecc_write_px2(arb_diag_or_tecc_write_px2),
4506 .arb_tag_rd_px2 (arb_tag_rd_px2),
4507 .arb_tag_way_px2(arb_tag_way_px2[15:0]), // BS & SR 10/28/03
4508 .arb_mux1_mbsel_px1 (arb_mux1_mbsel_px1),
4509 .arb_wr8_inst_no_ctrue_c1(arb_wr8_inst_no_ctrue_c1),
4510 .arb_bs_or_bis_inst_c2(arb_bs_or_bis_inst_c2),
4511 .usaloc_ua_ce_c2 (usaloc_ua_ce_c2),
4512 .vlddir_vd_ce_c2 (vlddir_vd_ce_c2[1]),
4513 .arb_vuad_ce_err_c2 (arb_vuad_ce_err_c2),
4514 .usaloc_vlddir_arb_vuad_ce_err_c3 (usaloc_vlddir_arb_vuad_ce_err_c3),
4515 .tagctl_arb_vuad_ce_err_c3 (tagctl_arb_vuad_ce_err_c3),
4516 //.arb_vuad_ce_err_c3 (arb_vuad_ce_err_c3),
4517 // Inputs
4518 .arbadr_2bnk_true_enbld_dist(arbadr_arbctl_2bnk_true_enbld_dist), // BS 03/25/04 for partial bank/core modes support
4519 .arbadr_4bnk_true_enbld_dist(arbadr_arbctl_4bnk_true_enbld_dist), // BS 03/25/04 for partial bank/core modes support
4520 .arbadr_arbdp_addr87_c2(arbadr_arbdp_addr87_c2[1:0]), // BS 03/25/04 for partial bank/core modes support
4521 .arbadr_ncu_l2t_pm_n_dist(arbadr_arbctl_ncu_l2t_pm_n_dist), // BS 03/25/04 for partial bank/core modes support
4522 .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4523 .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4524 .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4525 .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4526 .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4527 .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4528 .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4529 .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), // BS 03/25/04 for partial bank/core modes support
4530 .mbist_arb_l2t_write(mbist_arb_l2t_write),
4531 .oqu_arb_full_px2(oqu_arb_full_px2),
4532 .misbuf_arb_vld_px1(misbuf_arb_vld_px1),
4533 .misbuf_arb_cnt28_px2_prev(misbuf_arb_cnt28_px2_prev),
4534 .misbuf_arb_snp_cnt8_px1(misbuf_arb_snp_cnt8_px1),
4535 .wbuf_arb_full_px1(wbuf_arb_full_px1),
4536 .l2t_mb2_mbtag_lookup_en(l2t_mb2_mbtag_lookup_en),
4537 .l2t_mb2_fbtag_lookup_en(l2t_mb2_fbtag_lookup_en),
4538 .l2t_mb2_wbtag_lookup_en(l2t_mb2_wbtag_lookup_en),
4539 .l2t_mb2_rdmatag_lookup_en(l2t_mb2_rdmatag_lookup_en),
4540 .l2t_mb2_run(l2t_mb2_run),
4541 .filbuf_arb_vld_px1(filbuf_arb_vld_px1),
4542 .iqu_iq_arb_vld_px2 (iqu_iq_arb_vld_px2),
4543 .ique_iq_arb_vbit_px2(ique_iq_arb_vbit_px2),
4544 .ique_iq_arb_atm_px2 (ique_iq_arb_atm_px2),
4545 .ique_iq_arb_csr_px2 (ique_iq_arb_csr_px2),
4546 .ique_iq_arb_st_px2 (ique_iq_arb_st_px2),
4547 .snp_snpq_arb_vld_px1(snp_snpq_arb_vld_px1),
4548 .tag_deccck_data_sel_c8(tag_deccck_data_sel_c8),
4549 .tag_rdma_vld_px1(tag_rdma_vld_px1),
4550 .tag_data_ecc_active_c3(tag_data_ecc_active_c3),
4551 .tag_decc_tag_acc_en_px2(tag_decc_tag_acc_en_px2),
4552 .misbuf_nondep_fbhit_c3(misbuf_nondep_fbhit_c3),
4553 .mbist_arb_l2d_en (mbist_arb_l2d_en),
4554 .bist_vuad_rd_en_px1(mbist_l2v_read), // Templated
4555 .arbdec_arbdp_inst_fb_c2 (arbdec_arbdp_inst_fb_c2),
4556 .arbadr_arbdp_ioaddr_c1_39to37(arbadr_arbdp_ioaddr_c1[39:37]), // Templated
4557 .arbadr_arbdp_ioaddr_c1_35to33(arbadr_arbdp_ioaddr_c1[35:33]), // Templated
4558 .arbdec_size_field_c8 (arbdec_size_field_c8[1:0]),
4559 .arbdat_word_lower_cmp_c8 (arbdat_word_lower_cmp_c8),
4560 .arbdat_word_upper_cmp_c8 (arbdat_word_upper_cmp_c8),
4561 .arbadr_addr2_c8(arbadr_addr2_c8),
4562 .arbdec_arbdp_inst_size_c7(arbdec_arbdp_inst_size_c7[7:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
4563 .arbadr_arbdp_diag_wr_way_c2(arbdp_diag_wr_way_c2[3:0]),
4564 .arbdec_arbdp_inst_way_c1 (arbdec_arbdp_inst_way_c1[3:0]),
4565 .arbdec_arbdp_tecc_c1 (arbdec_arbdp_tecc_c1),
4566 .filbuf_arbdp_way_px2(filbuf_arbdp_way_px2[3:0]),
4567 .arbdec_arbdp_inst_mb_c2 (arbdec_arbdp_inst_mb_c2),
4568 .arbdec_arbdp_inst_fb_c1 (arbdec_arbdp_inst_fb_c1),
4569 .arbdec_arbdp_inst_dep_c2 (arbdec_arbdp_inst_dep_c2),
4570 .tag_hit_l2orfb_c3(tag_hit_l2orfb_c3),
4571 .tagdp_arb_par_err_c3(tagdp_arb_par_err_c3),
4572 .tagdp_invalid_evict_c3 (tagdp_invalid_evict_c3),
4573 .arbdec_arbdp_inst_nc_c3 (arbdec_arbdp_inst_nc_c3),
4574 .arbdec_arbdp_cpuid_c2 (arbdec_arbdp_cpuid_c2[2:0]),
4575 .arbdec_arbdp_l1way_c3 (arbdec_arbdp_l1way_c3[1:0]),
4576 .arbadr_arbdp_addr11to4_c3(arbadr_arbdp_addr11to4_c3[7:0]),
4577 .arbadr_arbdp_new_addr5to4_px2(arbadr_arbdp_new_addr5to4_px2[1:0]),
4578 .arbadr_arbdp_addr5to4_c1 (arbadr_arbdp_addr5to4_c1[1:0]),
4579 .arbadr_arbdp_addr5to4_c3 (arbadr_arbdp_addr5to4_c3[1:0]),
4580 .arbdec_arbdp_inst_mb_c3 (arbdec_arbdp_inst_mb_c3),
4581 .arbdec_arbdp_inst_tecc_c3(arbdec_arbdp_inst_tecc_c3),
4582 .arbdec_arbdp_inst_bufidhi_c1(arbdec_arbdp_inst_bufidhi_c1),
4583 .arbdec_arbdp_inst_bufid1_c1(arbdec_arbdp_inst_bufid1_c1),
4584 .arbdec_arbdp_inst_mb_c1 (arbdec_arbdp_inst_mb_c1),
4585 .arbdec_arbdp_evict_c1 (arbdec_arbdp_evict_c1),
4586 .arbdec_arbdp_inst_rqtyp_c1(arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO]),
4587 .arbdec_arbdp_inst_rsvd_c1(arbdec_arbdp_inst_rsvd_c1_1),
4588 .arbdec_arbdp_inst_nc_c1 (arbdec_arbdp_inst_nc_c1),
4589 .arbdec_arbdp_inst_ctrue_c1(arbdec_arbdp_inst_ctrue_c1),
4590 .arbdec_arbdp_inst_size_c1(arbdec_arbdp_inst_size_c1[`L2_SZ_HI:`L2_SZ_LO]),
4591 .arbadr_arbdp_addr_start_c2(arbadr_arbdp_addr_start_c2),
4592 .arbdec_arbdp_rdma_inst_c2(arbdec_arbdp_rdma_inst_c2),
4593 .arbdec_arbdp_inst_bufidlo_c2(arbdec_arbdp_inst_bufidlo_c2),
4594 .arbdec_arbdp_inst_rqtyp_c2(arbdec_arbdp_inst_rqtyp_c2[`L2_RQTYP_HI:`L2_RQTYP_LO]),
4595 .arbdec_arbdp_inst_rqtyp_c6(arbdec_arbdp_inst_rqtyp_c6[`L2_RQTYP_HI:`L2_RQTYP_LO]),
4596 .arbadr_arbaddr_addr22_c2 (arbaddr_addr22_c2),
4597 .bist_acc_vd_px1 (mbist_l2v_vd), // Templated
4598 .csr_l2_bypass_mode_on (csr_l2_bypass_mode_on),
4599 .scan_in(arb_scanin),
4600 .scan_out(arb_scanout),
4601 .l2clk (l2clk),
4602 .misbuf_arb_hit_c3(misbuf_arb_hit_c3),
4603 .arb_misbuf_inval_inst_c2(arb_misbuf_inval_inst_c2),
4604 .iqu_iq_arb_vld_px2_v1(iqu_iq_arb_vld_px2_v1),
4605 .arb_l2drpt_waysel_gate_c1(arb_l2drpt_waysel_gate_c1),
4606 .misbuf_hit_st_dep_zero(misbuf_hit_st_dep_zero),
4607 .tag_hit_unqual_c3(tag_hit_unqual_c3),
4608 .mbist_run(mbist_run),
4609 .mbist_lookupen(mbist_lookupen),
4610 .io_cmp_sync_en(io_cmp_sync_en),
4611 .arb_iqsel_px2_v1(arb_iqsel_px2_v1),
4612 .arb_snp_snpsel_px2(arb_snp_snpsel_px2),
4613 .arb_arbdp_dword_st_c1(arb_arbdp_dword_st_c1),
4614 .decdp_cas2_from_mb_ctrue_c1(decdp_cas2_from_mb_ctrue_c1));
4615
4616l2t_arbdec_dp arbdec(
4617 .tcu_pce_ov(ce_ovrd),
4618 .tcu_aclk(aclk),
4619 .tcu_bclk(bclk),
4620 .tcu_scan_en(tcu_scan_en),
4621 .tcu_clk_stop(1'b0),
4622 /*AUTOINST*/
4623 // Outputs
4624 .l2t_dbg_xbar_vcid (l2t_dbg_xbar_vcid_transfer[5:0]),
4625 .arbdec_arbdp_inst_c8 (arbdp_inst_c8[`L2_POISON:`L2_SZ_LO]),
4626 .arbdec_arbdp_inst_bufidhi_c8(arbdec_arbdp_inst_bufidhi_c8),
4627 .arbdec_arbdp_inst_way_c1(arbdec_arbdp_inst_way_c1[3:0]),
4628 .arbdec_arbdp_tecc_c1 (arbdec_arbdp_tecc_c1),
4629 .arbdec_arbdp_poison_c1(arbdec_arbdp_poison_c1),
4630 .arbdec_arbdp_inst_mb_entry_c1(arbdec_arbdp_inst_mb_entry_c1[4:0]),
4631 .arbdec_arbdp_inst_fb_c1(arbdec_arbdp_inst_fb_c1),
4632 .arbdec_arbdp_inst_mb_c1(arbdec_arbdp_inst_mb_c1),
4633 .arbdec_arbdp_evict_c1(arbdec_arbdp_evict_c1),
4634 .arbdec_arbdp_inst_rqtyp_c1(arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO]),
4635 // .arbdec_arbdp_inst_rsvd_c1(arbdec_arbdp_inst_rsvd_c1),
4636 .arbdec_arbdp_inst_nc_c1(arbdec_arbdp_inst_nc_c1),
4637 .arbdec_arbdp_inst_size_c1(arbdec_arbdp_inst_size_c1[`L2_SZ_HI:`L2_SZ_LO]),
4638 .arbdec_arbdp_inst_bufidhi_c1(arbdec_arbdp_inst_bufidhi_c1),
4639 .arbdec_arbdp_inst_bufid1_c1(arbdec_arbdp_inst_bufid1_c1),
4640 .arbdec_arbdp_inst_ctrue_c1(arbdec_arbdp_inst_ctrue_c1),
4641 .arbdec_arbdp_inst_fb_c2(arbdec_arbdp_inst_fb_c2),
4642 .arbdec_arbdp_inst_mb_c2(arbdec_arbdp_inst_mb_c2),
4643 .arbdec_arbdp_rdma_entry_c3(arbdec_arbdp_rdma_entry_c3[1:0]),
4644 .arbdec_arbdp_rdma_inst_c1(arbdec_arbdp_rdma_inst_c1),
4645 .arbdec_arbdp_inst_rsvd_c1_1(arbdec_arbdp_inst_rsvd_c1_1),
4646 .arbdec_arbdp_rdma_inst_c2(arbdec_arbdp_rdma_inst_c2),
4647 .arbdec_arbdp_inst_dep_c2(arbdec_arbdp_inst_dep_c2),
4648 .arbdec_arbdp_inst_way_c2(arbdec_arbdp_inst_way_c2[3:0]),
4649 .arbdec_arbdp_inst_rqtyp_c2(arbdec_arbdp_inst_rqtyp_c2[`L2_RQTYP_HI:`L2_RQTYP_LO]),
4650 .arbdec_arbdp_inst_bufidlo_c2(arbdec_arbdp_inst_bufidlo_c2),
4651 .arbdec_arbdp_inst_rqtyp_c6(arbdec_arbdp_inst_rqtyp_c6[`L2_RQTYP_HI:`L2_RQTYP_LO]),
4652 .arbdec_arbdp_inst_way_c3(arbdec_arbdp_inst_way_c3[3:0]),
4653 .arbdec_arbdp_inst_mb_c3(arbdec_arbdp_inst_mb_c3),
4654 .arbdec_arbdp_inst_tecc_c3(arbdec_arbdp_inst_tecc_c3),
4655 .arbdec_arbdp_inst_nc_c3(arbdec_arbdp_inst_nc_c3),
4656 .arbdec_arbdp_l1way_c3(arbdec_arbdp_l1way_c3[1:0]),
4657 .arbdec_arbdp_cpuid_c5(arbdec_arbdp_cpuid_c5[2:0]),
4658 .arbdec_arbdp_cpuid_c2(arbdec_arbdp_cpuid_c2[2:0]),
4659 .arbdec_arbdp_int_bcast_c5(arbdec_arbdp_int_bcast_c5),
4660 .arbdec_arbdp_inst_l1way_c7(arbdec_arbdp_inst_l1way_c7[1:0]),
4661 .arbdec_arbdp_inst_size_c7(arbdec_arbdp_inst_size_c7[7:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
4662 .st_ack_bmask(st_ack_bmask[7:0]), // BS and SR 1/30/04 Bmask for store ack including Diagnostic store ack
4663 .arbdec_arbdp_inst_tid_c7(arbdec_arbdp_inst_tid_c7[2:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
4664 .arbdec_arbdp_inst_cpuid_c7(arbdec_arbdp_inst_cpuid_c7[2:0]),
4665 .arbdec_arbdp_inst_nc_c7(arbdec_arbdp_inst_nc_c7),
4666 .arbdec_ctag_c6(arbdec_ctag_c6[31:0]),
4667 .arbdec_size_field_c8 (arbdec_size_field_c8[1:0]),
4668 // Inputs
4669 .sel_diag_store_data_c7 (sel_diag_store_data_c7), // BS and SR 12/22/03, store ack generation for diagnostic store
4670 .snpd_snpq_arbdp_inst_px2(snpd_snpq_arbdp_inst_px2[`JBI_HDR_SZ_LESS1:0]),
4671 .ique_iq_arbdp_inst_px2(ique_iq_arbdp_inst_px2[24:0]), // BS and SR 11/12/03 N2 Xbar Packet format
4672 // BS & SR 11/04/03, MB grows to 32
4673 // .mb_data_read_data_low(mb_data_read_data[`MBD_POISON:`MBD_SZ_LO]),
4674 // .mb_data_read_data_mid(mb_data_read_data[`MBD_EVICT:`MBD_TECC]),
4675 // .mb_data_read_data_hi(mb_data_read_data[`MBD_ECC_HI_PLUS5:`MBD_ECC_HI_PLUS1]),
4676 //.mbdata_snp_ecc(mb_data_read_data[117:111]),
4677 .misbuf_arbdp_ctrue_px2(misbuf_arbdp_ctrue_px2),
4678 .misbuf_arb_l2rd_en(misbuf_arb_l2rd_en),
4679 .filbuf_arbdp_entry_px2(filbuf_arbdp_entry_px2[2:0]),
4680 .filbuf_arbdp_tecc_px2(filbuf_arbdp_tecc_px2),
4681 .csr_l2_steering_tid(csr_l2_steering_tid[5:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
4682 .filbuf_arbdp_way_px2(filbuf_arbdp_way_px2[3:0]),
4683 .arb_mux1_mbsel_px2(arb_mux1_mbsel_px2),
4684 .arb_mux2_snpsel_px2(arb_arbdec_mux2_snpsel_px2),
4685 .arb_mux3_bufsel_px2(arb_arbdec_mux3_bufsel_px2),
4686 .arb_mux4_c1sel_px2(arb_arbdec_mux4_c1sel_px2),
4687 .scan_in(arbdec_scanin),
4688 .scan_out(arbdec_scanout_1),
4689 .l2clk (l2clk),
4690 .arbadr_arbdp_byte_addr_c6(arbadr_arbdp_byte_addr_c6[2:0]),
4691 .misbuf_buf_rd_en(misbuf_buf_rd_en),
4692 .mbdata_cmp_sel(mbdata_cmp_sel[3:2]),
4693 .l2t_mb2_wdata(l2t_mb2_wdata[7:0]),
4694 .mbdata_fail(mbdata_fail),
4695 .mbdata_fail_bot(mbdata_fail_bot),
4696 .mb_data_read_data(mb_data_read_data[127:64]),
4697 .snpd_ecc_px2(snpd_ecc_px2[6:0]),
4698 .arbdec_snpd_ecc_c8(arbdec_snpd_ecc_c8[6:0]),
4699 .arbdec_pf_ice_inst_c1(arbdec_pf_ice_inst_c1),
4700 .arbdec_csr_ttype_c6(arbdec_csr_ttype_c6[4:0]),
4701 .arbdec_csr_vcid_c6(arbdec_csr_vcid_c6[5:0])); // Phase 2 : SIU inteface and packet format change 2/7/04
4702
4703
4704l2t_wbufrpt_dp wbufrpt (
4705 .scan_in(arbdec_scanout_1),
4706 .scan_out(arbdec_scanout),
4707 .tcu_clk_stop(1'b0),
4708 .wbuf_wb_read_en(wb_read_en),
4709 .wbuf_rdmat_read_en(rdmat_read_en),
4710 .l2clk(l2clk),
4711 .tcu_pce_ov(tcu_pce_ov),
4712 .tcu_aclk(tcu_aclk),
4713 .tcu_bclk(tcu_bclk),
4714 .tcu_scan_en(tcu_scan_en),
4715 .l2t_l2b_wbrd_en_r0(l2t_l2b_wbrd_en_r0),
4716 .l2t_l2b_rdma_rden_r0(l2t_l2b_rdma_rden_r0),
4717 .wbuf_wbufrpt_leave_state0(wbuf_wbufrpt_leave_state0),
4718 .wbuf_wbufrpt_next_state_1(wbuf_wbufrpt_next_state_1),
4719 .cycle_count_less_than_7_din(cycle_count_less_than_7_din),
4720 .mcu_l2t_wr_ack_d1(mcu_l2t_wr_ack_d1)
4721 );
4722
4723l2t_wbuf_ctl wbuf(
4724 .tcu_pce_ov(ce_ovrd),
4725 .tcu_aclk(aclk),
4726 .tcu_bclk(bclk),
4727 .tcu_scan_en(tcu_scan_en),
4728
4729 .l2t_mb2_rdmatag_rd_en (l2t_mb2_rdmatag_rd_en),
4730 .l2t_mb2_wbtag_wr_en (l2t_mb2_wbtag_wr_en),
4731 .l2t_mb2_wbtag_rd_en (l2t_mb2_wbtag_rd_en),
4732 .l2t_mb2_addr (l2t_mb2_addr[2:0]),
4733 .wb_cam_match_c2 (wb_cam_match_c2[7:0]),
4734 .wb_mbist_cam_hit (wb_mbist_cam_hit),
4735 .wb_mbist_cam_sel(mbist_cam_sel[2]),
4736 .wbuf_wbtag_write_wl_c4 (wbtag_write_wl_c4[7:0]),
4737 .wbuf_wbtag_write_en_c4 (wbtag_write_en_c4),
4738 .wbuf_wb_read_wl (wb_read_wl[7:0]),
4739 .wbuf_wb_read_en (wb_read_en),
4740 .wbuf_rdmat_read_wl (rdmat_read_wl[3:0]),
4741 .wbuf_rdmat_read_en (rdmat_read_en),
4742 .wmr_l (wmr_l),
4743 // Outputs
4744 .l2t_dbg_sii_wib_dequeue (l2t_dbg_sii_wib_dequeue),
4745 .l2t_l2b_wbwr_wl_c6(l2t_l2b_wbwr_wl_c6[2:0]),
4746 .l2t_l2b_wbwr_wen_c6(l2t_l2b_wbwr_wen_c6[3:0]),
4747 .l2t_l2b_wbrd_wl_r0(l2t_l2b_wbrd_wl_r0[2:0]),
4748 // .l2t_l2b_wbrd_en_r0(l2t_l2b_wbrd_en_r0),
4749 .l2t_l2b_ev_dword_r0(l2t_l2b_ev_dword_r0[2:0]),
4750 .l2t_l2b_evict_en_r0(l2t_l2b_evict_en_r0),
4751 .l2t_mcu_wr_req (l2t_mcu_wr_req),
4752 .wbuf_hit_unqual_c2 (wbuf_hit_unqual_c2),
4753 .wbuf_misbuf_dep_rdy_en(wbuf_misbuf_dep_rdy_en),
4754 .wbuf_misbuf_dep_mbid (wbuf_misbuf_dep_mbid[4:0]),
4755 .wbuf_arb_full_px1(wbuf_arb_full_px1),
4756 .wbuf_wr_addr_sel (wbuf_wr_addr_sel),
4757 .wbuf_wb_or_rdma_wr_req_en (wbuf_wb_or_rdma_wr_req_en),
4758 .l2t_l2b_rdma_rdwl_r0(l2t_l2b_rdma_rdwl_r0[1:0]),
4759 // .l2t_l2b_rdma_rden_r0(l2t_l2b_rdma_rden_r0),
4760 .wbuf_reset_rdmat_vld (wbuf_reset_rdmat_vld[3:0]),
4761 .wbuf_set_rdmat_acked (wbuf_set_rdmat_acked[3:0]),
4762 .l2t_sii_wib_dequeue(l2t_sii_wib_dequeue),
4763 // Inputs
4764 .l2t_siu_delay (l2t_siu_delay),
4765 .scan_in(wbuf_scanin),
4766 .scan_out(wbuf_scanout),
4767 .l2clk (l2clk),
4768 .vlddir_dirty_evict_c3 (vlddir_dirty_evict_c3),
4769 .arbdec_arbdp_inst_fb_c2 (arbdec_arbdp_inst_fb_c2),
4770 .misbuf_wbuf_mbid_c4 (misbuf_wbuf_mbid_c4[4:0]),
4771 .misbuf_hit_c4 (misbuf_hit_c4),
4772 .misbuf_filbuf_mcu_pick(misbuf_filbuf_mcu_pick),
4773 .csr_l2_bypass_mode_on (csr_wbuf_l2off), // Templated
4774 .arbadr_c1_addr_eq_wb_c4 (arbadr_c1_addr_eq_wb_c4),
4775 .arb_wbuf_hit_off_c1(arb_wbuf_hit_off_c1),
4776 .arb_wbuf_inst_vld_c2(arb_wbuf_inst_vld_c2),
4777 .mcu_l2t_wr_ack (mcu_l2t_wr_ack),
4778 .rdmat_pick_vec (rdmat_pick_vec[3:0]),
4779 .rdmat_or_rdmat_valid (rdmat_or_rdmat_valid),
4780 .wbuf_wbufrpt_leave_state0(wbuf_wbufrpt_leave_state0),
4781 .l2t_mb2_run(l2t_mb2_run),
4782 .wbuf_wbufrpt_next_state_1(wbuf_wbufrpt_next_state_1),
4783 .cycle_count_less_than_7_din(cycle_count_less_than_7_din),
4784 .mcu_l2t_wr_ack_d1(mcu_l2t_wr_ack_d1));
4785
4786n2_com_cm_8x40_cust wbtag
4787 (
4788 .dout(wb_read_data[39:0]), // BS and SR 8 deep change 3/3/04
4789 .match(wb_cam_match_c2[7:0]),
4790 .match_idx(wb_match_idx_unused[7:0]),
4791 .adr_w(wbtag_write_wl_c4[7:0]),
4792 .din(wb_write_addr[39:0]), // generated in arbadr
4793 .write_en(wbtag_write_en_c4),
4794 .adr_r(wb_read_wl[7:0]),
4795 .lookup_en(arb_inst_vld_c1_v2),
4796 .key(lkup_addr_c1[39:7]),
4797 .tcu_se_scancollar_out(tcu_se_scancollar_out),
4798 .tcu_array_wr_inhibit(array_wr_inhibit),
4799 .scan_in(wbtag_scanin),
4800 .scan_out(wbtag_scanout),
4801 .l2clk(l2clk),
4802 .pce(1'b1),
4803 .read_en(wb_read_en),
4804 .tcu_aclk(aclk),
4805 .tcu_bclk(bclk),
4806 .tcu_scan_en(tcu_scan_en),
4807 .tcu_pce_ov(ce_ovrd),
4808 .tcu_clk_stop(1'b0),
4809 .tcu_array_bypass (tcu_array_bypass),
4810 .tcu_se_scancollar_in(tcu_se_scancollar_in));
4811
4812
4813l2t_ique_dp ique(
4814 .tcu_pce_ov(ce_ovrd),
4815 .tcu_aclk(aclk),
4816 .tcu_bclk(bclk),
4817 .tcu_scan_en(tcu_scan_en),
4818 .tcu_clk_stop(1'b0),
4819 .iqu_fail_reg(iqu_fail_reg),
4820 .tcu_dectest(tcu_dectest),
4821 .iq_array_rd_data_c1 (iq_array_rd_data_c1[130:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
4822 .ique_arb_pf_ice_px2 (ique_arb_pf_ice_px2),
4823 /*AUTOINST*/
4824 // Outputs
4825 .ique_pcx_l2t_data_103_px2 (ique_pcx_l2t_data_103_px2),
4826 .ique_iq_arbdp_data_px2 (ique_iq_arbdp_data_px2[63:0]),
4827 .ique_iq_arbdp_addr_px2 (ique_iq_arbdp_addr_px2[39:0]),
4828 .ique_iq_arbdp_inst_px2 (ique_iq_arbdp_inst_px2[24:0]), // BS and SR 11/12/03 N2 Xbar Packet format
4829 .ique_iq_arb_atm_px2 (ique_iq_arb_atm_px2),
4830 .ique_iq_arb_csr_px2 (ique_iq_arb_csr_px2),
4831 .ique_iq_arb_st_px2 (ique_iq_arb_st_px2),
4832 .ique_iq_arb_vbit_px2 (ique_iq_arb_vbit_px2),
4833 // Inputs
4834 .scan_in(ique_scanin),
4835 .scan_out(ique_scanout),
4836 .l2clk (l2clk),
4837 .pcx_l2t_data_px2 (pcx_l2t_data_px2[`PCX_WIDTH_LESS1:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
4838 .iqu_pcx_l2t_atm_px2_p (iqu_pcx_l2t_atm_px2_p),
4839 .iqu_sel_pcx (iqu_sel_pcx),
4840 .iqu_sel_c1 (iqu_sel_c1),
4841 .iqu_hold_rd_n (iqu_hold_rd_n),
4842 .iqu_sel_c1reg_over_iqarray(iqu_sel_c1reg_over_iqarray),
4843 .tcu_muxtest(tcu_muxtest),
4844 .l2t_mb2_wdata(l2t_mb2_wdata[7:0]),
4845 .mbdata_cmp_sel(mbdata_cmp_sel[3:0]),
4846 .iq_array_rd_en(iq_array_rd_en),
4847 .pcx_l2t_data_px2_fnl(pcx_l2t_data_px2_fnl[129:0]));
4848
4849l2t_iqu_ctl iqu(
4850 .tcu_pce_ov(ce_ovrd),
4851 .tcu_aclk(aclk),
4852 .tcu_bclk(bclk),
4853 .tcu_scan_en(tcu_scan_en),
4854 .l2t_mb2_iqarray_wr_en (l2t_mb2_iqarray_wr_en),
4855 .l2t_mb2_iqarray_rd_en (l2t_mb2_iqarray_rd_en),
4856 .l2t_mb2_run (l2t_mb2_run),
4857 .l2t_mb2_addr (l2t_mb2_addr[3:0]),
4858 .iqu_iq_array_wr_en (iq_array_wr_en),
4859 .iqu_iq_array_wr_wl (iq_array_wr_wl[3:0]),
4860 .iqu_iq_array_rd_en (iq_array_rd_en),
4861 .iqu_iq_array_rd_wl (iq_array_rd_wl[3:0]),
4862 .wmr_l (wmr_l),
4863 // Outputs
4864 .l2t_pcx_stall_pq (l2t_pcx_stall_pq),
4865 .iqu_iq_arb_vld_px2 (iqu_iq_arb_vld_px2),
4866 .iqu_pcx_l2t_atm_px2_p (iqu_pcx_l2t_atm_px2_p),
4867 .iqu_sel_pcx (iqu_sel_pcx),
4868 .iqu_sel_c1 (iqu_sel_c1),
4869 .iqu_hold_rd_n (iqu_hold_rd_n),
4870 .iqu_sel_c1reg_over_iqarray(iqu_sel_c1reg_over_iqarray),
4871 // Inputs
4872 .scan_in(iqu_scanin),
4873 .scan_out(iqu_scanout),
4874 .l2clk (l2clk),
4875 .pcx_l2t_data_rdy_px1(pcx_l2t_data_rdy_px1),
4876 .pcx_l2t_atm_px1 (pcx_l2t_atm_px1),
4877 .arb_iqsel_px2 (arb_iqsel_px2),
4878 .arb_iqsel_px2_v1(arb_iqsel_px2_v1),
4879 .iqu_iq_arb_vld_px2_v1(iqu_iq_arb_vld_px2_v1));
4880
4881
4882
4883// x0in fifo -enq iq_array_wr_wl -deq iq_array_rd_wl -depth 16
4884
4885n2_l2t_dp_16x160_cust iqarray(
4886 // Outputs
4887 .dout (iq_array_rd_data_c1[159:0]),
4888 // Inputs
4889 .din ({29'b0,iqu_pcx_l2t_atm_px2_p,pcx_l2t_data_px2_fnl[`PCX_WIDTH_LESS1:104],
4890 ique_pcx_l2t_data_103_px2, pcx_l2t_data_px2_fnl[102:0]}),
4891 // BS and SR 11/12/03 N2 Xbar Packet format change
4892// .din ({29'b0,iqu_pcx_l2t_atm_px2_p,pcx_l2t_data_px2[`PCX_WIDTH_LESS1:0]}),
4893 .tcu_pce_ov(ce_ovrd),
4894 .pce(1'b1),
4895 .tcu_aclk(aclk),
4896 .tcu_bclk(bclk),
4897 .tcu_scan_en(tcu_scan_en),
4898 .rd_adr (iq_array_rd_wl[3:0]),
4899 .wr_adr (iq_array_wr_wl[3:0]),
4900 .read_en (iq_array_rd_en),
4901 .wr_en (iq_array_wr_en),
4902 .word_wen (4'b1111),
4903 .byte_wen (20'b11111111111111111111),
4904 .scan_in(iqarray_scanin),
4905 .scan_out(iqarray_scanout),
4906 .l2clk (l2clk),
4907 .tcu_array_wr_inhibit(array_wr_inhibit),
4908 .mbist_wdata (l2t_mb2_wdata[7:0]),
4909 .mbist_run (l2t_mb2_run),
4910 .tcu_se_scancollar_in (tcu_se_scancollar_in));
4911
4912
4913
4914
4915l2t_oqu_ctl oqu(
4916 .tcu_pce_ov(ce_ovrd),
4917 .tcu_aclk(aclk),
4918 .tcu_bclk(bclk),
4919 .tcu_scan_en(tcu_scan_en),
4920 .oqu_oqarray_wr_en (oqarray_wr_en),
4921 .oqu_oqarray_rd_en (oqarray_rd_en),
4922 .oqu_oqarray_wr_ptr (oqarray_wr_ptr[3:0]),
4923 .oqu_oqarray_rd_ptr (oqarray_rd_ptr[3:0]),
4924 .lkup_bank_ena_dcd_c4(dirrep_dc_lkup_row_dec_c4[3:0]),
4925 .lkup_bank_ena_icd_c4(dirrep_ic_lkup_row_dec_c4[3:0]),
4926 .wmr_l (wmr_l),
4927 /*AUTOINST*/
4928 // Outputs
4929 .sel_st_ack_c7 (sel_st_ack_c7), // BS and SR 11/12/03 N2 Xbar Packet format change
4930 .oqu_mmu_ld_hit_c7(oqu_mmu_ld_hit_c7), // BS and SR 11/12/03 N2 Xbar Packet format change
4931 .l2t_cpx_req_cq (l2t_cpx_req_cq[7:0]),
4932 .l2t_cpx_atom_cq (l2t_cpx_atom_cq),
4933 .oqu_diag_acc_c8 (oqu_diag_acc_c8),
4934 .oqu_rqtyp_rtn_c7 (oqu_rqtyp_rtn_c7[3:0]),
4935 .oqu_cerr_ack_c7 (oqu_cerr_ack_c7),
4936 .oqu_uerr_ack_c7 (oqu_uerr_ack_c7),
4937 .oqu_str_ld_hit_c7 (oqu_str_ld_hit_c7),
4938 .oqu_fwd_req_ret_c7 (oqu_fwd_req_ret_c7),
4939 .oqu_atm_inst_ack_c7 (oqu_atm_inst_ack_c7),
4940 .oqu_strst_ack_c7 (oqu_strst_ack_c7),
4941 .oqu_int_ack_c7 (oqu_int_ack_c7),
4942 .oqu_imiss_hit_c8 (oqu_imiss_hit_c8),
4943 .oqu_pf_ack_c7 (oqu_pf_ack_c7),
4944 .oqu_rmo_st_c7 (oqu_rmo_st_c7),
4945 .oqu_l2_miss_c7 (oqu_l2_miss_c7),
4946 .oqu_mux1_sel_data_c7 (oqu_mux1_sel_data_c7[3:0]),
4947 .oqu_mux_csr_sel_c7 (oqu_mux_csr_sel_c7),
4948 .oqu_sel_inval_c7 (oqu_sel_inval_c7),
4949 .oqu_out_mux1_sel_c7 (oqu_out_mux1_sel_c7[2:0]),
4950 .oqu_out_mux2_sel_c7 (oqu_out_mux2_sel_c7[2:0]),
4951 .oqu_sel_array_out_l (oqu_sel_array_out_l),
4952 .oqu_sel_mux1_c6 (oqu_sel_mux1_c6[3:0]),
4953 .oqu_sel_mux2_c6 (oqu_sel_mux2_c6[3:0]),
4954 .oqu_sel_mux3_c6 (oqu_sel_mux3_c6),
4955 .oqu_mux_vec_sel_c6 (oqu_mux_vec_sel_c6[3:0]),
4956 .oqu_arb_full_px2(oqu_arb_full_px2),
4957 .oqu_st_complete_c7(oqu_st_complete_c7),
4958 .misbuf_vuad_ce_err_c6(misbuf_vuad_ce_err_c6), // vuad ecc change
4959 // Inputs
4960 .arb_cpuid_c5 (arb_cpuid_c5[2:0]),
4961 .arbdec_arbdp_cpuid_c5 (arbdec_arbdp_cpuid_c5[2:0]),
4962 .arbdec_arbdp_int_bcast_c5 (arbdec_arbdp_int_bcast_c5),
4963 .arb_oqu_swap_cas2_req_c2 (arb_oqu_swap_cas2_req_c2),
4964 .arb_decdp_strld_inst_c6(arb_decdp_strld_inst_c6),
4965 .arb_decdp_atm_inst_c6 (arb_decdp_atm_inst_c6),
4966 .arb_decdp_pf_inst_c5 (arb_decdp_pf_inst_c5),
4967 .arb_evict_c5 (arb_evict_c5),
4968 .dirvec_dirdp_req_vec_c6 (dirvec_dirdp_req_vec_c6[7:0]),
4969 .l2t_mb0_addr (l2t_mb0_addr[3:0]),
4970 .tag_imiss_hit_c5(tag_imiss_hit_c5),
4971 .tag_ld_hit_c5 (tag_ld_hit_c5),
4972 .tag_nonmem_comp_c6(tag_nonmem_comp_c6),
4973 .tag_st_ack_c5 (tag_st_ack_c5),
4974 .tag_strst_ack_c5(tag_strst_ack_c5),
4975 .tag_uerr_ack_c5 (tag_uerr_ack_c5),
4976 .tag_cerr_ack_c5 (tag_cerr_ack_c5),
4977 .tag_int_ack_c5 (tag_int_ack_c5),
4978 .tag_st_req_c5 (tag_st_req_c5),
4979 .tag_inval_req_c5(tag_inval_req_c5), // BS and SR 11/12/03 N2 Xbar Packet format change
4980 .arb_decdp_mmuld_inst_c6(arb_decdp_mmuld_inst_c6), // BS and SR 11/12/03 N2 Xbar Packet format change
4981 .tag_fwd_req_ret_c5(tag_fwd_req_ret_c5),
4982 .tag_sel_rdma_inval_vec_c5(tag_sel_rdma_inval_vec_c5),
4983 .tag_rdma_wr_comp_c4(tag_rdma_wr_comp_c4),
4984 .tag_store_inst_c5(tag_store_inst_c5),
4985 .tag_fwd_req_ld_c6(tag_fwd_req_ld_c6),
4986 .tag_rmo_st_ack_c5(tag_rmo_st_ack_c5),
4987 .tag_inst_mb_c5 (tag_inst_mb_c5),
4988 .tag_hit_c5 (tag_hit_c5),
4989 .arb_inst_l2data_vld_c6(arb_inst_l2data_vld_c6),
4990 .arb_inst_l2tag_vld_c6(arb_inst_l2tag_vld_c6),
4991 .arb_inst_l2vuad_vld_c6(arb_inst_l2vuad_vld_c6),
4992 .arb_csr_rd_en_c7(arb_csr_rd_en_c7),
4993 .cpx_l2t_grant_cx (cpx_l2t_grant_cx[7:0]),
4994 .scan_in(oqu_scanin),
4995 .scan_out(oqu_scanout),
4996 .l2clk (l2clk),
4997 .l2t_mb0_run(l2t_mb0_run),
4998 .l2t_mb0_oqarray_rd_en(l2t_mb0_oqarray_rd_en),
4999 .l2t_mb0_oqarray_wr_en(l2t_mb0_oqarray_wr_en));
5000
5001
5002
5003
5004
5005n2_l2t_dp_16x160_cust oqarray(
5006 // Outputs
5007 .dout (oq_array_data_out[159:0]),
5008 // Inputs
5009 .din ({14'b0,oq_array_data_in[`CPX_WIDTH_LESS1:0]}), // BS and SR 11/12/03 N2 Xbar Packet format change
5010 .tcu_pce_ov(ce_ovrd),
5011 .pce(1'b1),
5012 .tcu_aclk(aclk),
5013 .tcu_bclk(bclk),
5014 .tcu_scan_en(tcu_scan_en),
5015 .rd_adr (oqarray_rd_ptr[3:0]),
5016 .tcu_array_wr_inhibit(array_wr_inhibit),
5017 .wr_adr (oqarray_wr_ptr[3:0]),
5018 .read_en (oqarray_rd_en),
5019 .wr_en (oqarray_wr_en),
5020 .word_wen (4'b1111),
5021 .byte_wen (20'b11111111111111111111),
5022 .scan_in(oqarray_scanin),
5023 .scan_out(oqarray_scanout),
5024 .l2clk (l2clk),
5025 .mbist_wdata (mb0_l2t_mbist_write_data[7:0]),
5026 .mbist_run (l2t_mb0_run),
5027 .tcu_se_scancollar_in (tcu_se_scancollar_in));
5028
5029
5030l2t_oque_dp oque(
5031 .tcu_pce_ov(ce_ovrd),
5032 .tcu_aclk(aclk),
5033 .tcu_bclk(bclk),
5034 .tcu_scan_en(tcu_scan_en),
5035 .tcu_clk_stop(1'b0),
5036 .tcu_muxtest(tcu_muxtest),
5037 .tcu_dectest(tcu_dectest),
5038 .oq_array_data_out (oq_array_data_out[159:0]),
5039 .oque_oq_array_data_in (oq_array_data_in[`CPX_WIDTH_LESS1:0]),
5040 .vuadpm_vuad_diag_data_c7(tagdp_vuad_dp_diag_data_c7_buf[38:0]),
5041 .oqarray_rw_fail (oqarray_rw_fail),
5042 // Outputs
5043 .l2t_cpx_data_ca (l2t_cpx_data_ca[`CPX_WIDTH_LESS1:0]),
5044 .oque_tid_c8 (oque_tid_c8[5:0]),
5045 .mbist_oqarray_sel (mbist_oqarray_sel[3:0]),
5046 // Inputs
5047 .arbdec_arbdp_inst_l1way_c7 (arbdec_arbdp_inst_l1way_c7[1:0]),
5048 .arbdec_arbdp_inst_tid_c7 (arbdec_arbdp_inst_tid_c7[2:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
5049 .arbdec_arbdp_l1way_c3 (arbdec_arbdp_l1way_c3[1:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
5050 .oqu_mmu_ld_hit_c7 (oqu_mmu_ld_hit_c7), // BS and SR 11/12/03 N2 Xbar Packet format change
5051 .arbdec_arbdp_inst_nc_c7 (arbdec_arbdp_inst_nc_c7),
5052 .arbdec_arbdp_inst_cpuid_c7 (arbdec_arbdp_inst_cpuid_c7[2:0]),
5053 .oqu_rqtyp_rtn_c7 (oqu_rqtyp_rtn_c7[3:0]),
5054 .dirvec_dirdp_way_info_c7 (dirvec_dirdp_way_info_c7[3:0]), // BS and SR 11/18/03 Support for 8 way I$
5055 .oqu_strst_ack_c7 (oqu_strst_ack_c7),
5056 .arbdat_arbdp_oque_int_ret_c7(arbdat_arbdp_oque_int_ret_c7[17:0]),
5057 .csr_report_ldrc (csr_report_ldrc),
5058 .oqu_fwd_req_ret_c7 (oqu_fwd_req_ret_c7),
5059 .oqu_int_ack_c7 (oqu_int_ack_c7),
5060 .arbadr_arbdp_oque_l1_index_c7(arbadr_arbdp_oque_l1_index_c7[11:6]),
5061 .oqu_imiss_hit_c8 (oqu_imiss_hit_c8),
5062 .mb0_l2t_mbist_write_data(mb0_l2t_mbist_write_data[7:0]),
5063 .decc_ret_data_c7 (decc_ret_data_c7[127:0]),
5064// TIMING .deccck_ret_err_c7 (deccck_ret_err_c7[2:0]),
5065 .dirvec_dirdp_inval_pckt_c7 (dirvec_dirdp_inval_pckt_c7[111:0]),
5066 .decc_ret_diag_data_c7 (decc_ret_diag_data_c7[38:0]),
5067 .tagd_diag_data_c7 (tagd_diag_data_c7[27:0]),
5068 .oqu_pf_ack_c7 (oqu_pf_ack_c7),
5069 .oqu_rmo_st_c7 (oqu_rmo_st_c7),
5070 .oqu_atm_inst_ack_c7 (oqu_atm_inst_ack_c7),
5071 .oqu_diag_acc_c8 (oqu_diag_acc_c8),
5072// TIMING .oqu_cerr_ack_c7 (oqu_cerr_ack_c7),
5073// TIMING .oqu_uerr_ack_c7 (oqu_uerr_ack_c7),
5074 .oqu_mux1_sel_data_c7 (oqu_mux1_sel_data_c7[3:0]),
5075 .oqu_sel_array_out_l (oqu_sel_array_out_l),
5076 .oqu_mux_csr_sel_c7 (oqu_mux_csr_sel_c7),
5077 .oqu_sel_inval_c7 (oqu_sel_inval_c7),
5078 .oqu_out_mux1_sel_c7 (oqu_out_mux1_sel_c7[2:0]),
5079 .oqu_out_mux2_sel_c7 (oqu_out_mux2_sel_c7[2:0]),
5080 .arbadr_arbdp_line_addr_c7 (arbadr_arbdp_line_addr_c7[5:4]),
5081 .arb_dc_inval_vld_c7 (dc_inval_vld_c7),
5082 .arb_ic_inval_vld_c7 (ic_inval_vld_c7),
5083 .csr_rd_data_c8 (csr_rd_data_c8[63:0]),
5084// TIMING .oqu_l2_miss_c7 (oqu_l2_miss_c7),
5085 .scan_in(oque_scanin),
5086 .scan_out(oque_scanout),
5087 .l2clk (l2clk),
5088 .rtn_err_field_c7(rtn_err_field_c7[2:0]),
5089 .st_ack_data(st_ack_data[63:0]),
5090 .sel_st_ack_c7(sel_st_ack_c7),
5091 .oqarray_rd_en(oqarray_rd_en));
5092
5093
5094l2t_dirvec_ctl dirvec(
5095 .tcu_pce_ov(ce_ovrd),
5096 .tcu_aclk(aclk),
5097 .tcu_bclk(bclk),
5098 .tcu_scan_en(tcu_scan_en),
5099 .tcu_clk_stop(1'b0),
5100 // Outputs
5101 .dirvec_dirdp_req_vec_c6(dirvec_dirdp_req_vec_c6[7:0]),
5102 .dirvec_dirdp_way_info_c7(dirvec_dirdp_way_info_c7[3:0]), // BS and SR 11/18/03 Support for 8 way I$
5103 .dirvec_dirdp_inval_pckt_c7(dirvec_dirdp_inval_pckt_c7[111:0]),
5104 // Inputs
5105 .arbadr_2bnk_true_enbld_dist (arbadr_dirvec_2bnk_true_enbld_dist),
5106 .arbadr_4bnk_true_enbld_dist (arbadr_dirvec_4bnk_true_enbld_dist),
5107 .arbadr_ncu_l2t_pm_n_dist (arbadr_dirvec_ncu_l2t_pm_n_dist),
5108 .sel_st_ack_c7(sel_st_ack_c7), // BS and SR 11/12/03 N2 Xbar Packet format change
5109 .arbadr_arbdp_line_addr_c7(arbadr_arbdp_line_addr_c7[5:4]), // BS and SR 1/29/04
5110 .st_ack_bmask(st_ack_bmask[7:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
5111 // Bmask for store ack including Diagnostic store ack
5112 .arbadr_dirvec_addr3_c7(arbadr_dirvec_addr3_c7), // BS and SR 11/12/03 N2 Xbar Packet format change
5113 .ic_cam_hit (ic_cam_hit[127:0]),
5114 .dc_cam_hit (dc_cam_hit[127:0]),
5115 .oqu_sel_mux1_c6(oqu_sel_mux1_c6[3:0]),
5116 .oqu_sel_mux2_c6(oqu_sel_mux2_c6[3:0]),
5117 .oqu_sel_mux3_c6(oqu_sel_mux3_c6),
5118 .oqu_mux_vec_sel_c6(oqu_mux_vec_sel_c6[3:0]),
5119 .ic_cam_fail(ic_cam_fail[1:0]),
5120 .dc_cam_fail(dc_cam_fail[1:0]),
5121 .mb0_l2t_cambist(mb0_l2t_cambist),
5122 .scan_in(dirvec_scanin),
5123 .scan_out(dirvec_scanout),
5124 .l2clk (l2clk),
5125 .io_cmp_sync_en(io_cmp_sync_en),
5126 .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status),
5127 .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status),
5128 .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status),
5129 .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status),
5130 .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status),
5131 .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status),
5132 .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status),
5133 .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status));
5134
5135l2t_deccck_ctl deccck(
5136 .tcu_pce_ov(ce_ovrd),
5137 .tcu_aclk(aclk),
5138 .tcu_bclk(bclk),
5139 .tcu_scan_en(tcu_scan_en),
5140 // Outputs
5141 .deccck_muxsel_diag_out_c7(deccck_muxsel_diag_out_c7[3:0]),
5142 .deccck_bscd_corr_err_c8(deccck_bscd_corr_err_c8),
5143 .deccck_bscd_uncorr_err_c8(deccck_bscd_uncorr_err_c8),
5144 .deccck_bscd_notdata_err_c8(deccck_bscd_notdata_err_c8),
5145 .deccck_spcd_corr_err_c8(deccck_spcd_corr_err_c8),
5146 .deccck_spcd_uncorr_err_c8(deccck_spcd_uncorr_err_c8),
5147 .deccck_spcd_notdata_err_c8(deccck_spcd_notdata_err_c8),
5148 .deccck_scrd_corr_err_c8(deccck_scrd_corr_err_c8),
5149 .deccck_scrd_uncorr_err_c8(deccck_scrd_uncorr_err_c8),
5150 .deccck_spcfb_corr_err_c8(deccck_spcfb_corr_err_c8),
5151 .deccck_spcfb_uncorr_err_c8(deccck_spcfb_uncorr_err_c8),
5152 .deccck_uncorr_err_c8(deccck_uncorr_err_c8),
5153 .deccck_corr_err_c8 (deccck_corr_err_c8),
5154 .deccck_notdata_err_c8(deccck_notdata_err_c8),
5155 .deccck_dword_sel_c7 (deccck_dword_sel_c7),
5156 // Inputs
5157 .tag_deccck_addr3_c7(tag_deccck_addr3_c7),
5158 .arb_inst_l2data_vld_c6(arb_inst_l2data_vld_c6),
5159 .tag_data_ecc_active_c3(tag_data_ecc_active_c3),
5160 .bist_data_enable_c1(mbist_l2d_en), // Templated
5161 .bist_data_waddr_c1(mbist_l2d_word_sel[1:0]), // Templated
5162 .arbadr_arbdp_addr22_c7(arbadr_arbdp_addr22_c7),
5163 .arbadr_arbdp_waddr_c6(arbadr_arbdp_waddr_c6[1:0]),
5164 .tag_bsc_rd_vld_c7(tag_bsc_rd_vld_c7),
5165 .tag_scrub_rd_vld_c7(tag_scrub_rd_vld_c7),
5166 .scan_in(deccck_scanin),
5167 .scan_out(deccck_scanout),
5168 .l2clk (l2clk),
5169 .deccdp_decck_uncorr_err_c7(deccdp_decck_uncorr_err_c7[3:0]),
5170 .deccdp_decck_corr_err_c7(deccdp_decck_corr_err_c7[3:0]),
5171 .tag_spc_rd_vld_c6(tag_spc_rd_vld_c6),
5172 .filbuf_spc_corr_err_c6(filbuf_spc_corr_err_c6),
5173 .filbuf_spc_uncorr_err_c6(filbuf_spc_uncorr_err_c6),
5174 .filbuf_spc_rd_vld_c6(filbuf_spc_rd_vld_c6),
5175 .arbadr_arbdp_line_addr_c7(arbadr_arbdp_line_addr_c7[5:4]),
5176 .arbadr_arbdp_line_addr_c6(arbadr_arbdp_line_addr_c6[5:4])
5177 );
5178
5179
5180l2t_decc_dp decc
5181 (
5182 .tcu_pce_ov(ce_ovrd),
5183 .tcu_aclk(aclk),
5184 .tcu_bclk(bclk),
5185 .tcu_scan_en(tcu_scan_en),
5186 .tcu_clk_stop(1'b0),
5187 .tcu_dectest(tcu_dectest),
5188 // Outputs
5189 .decc_ret_data_c7 (decc_ret_data_c7[127:0]),
5190 .decc_arbdp_data_c8(decc_arbdp_data_c8[63:0]),
5191 .decc_lda_syndrome_c9 (decc_lda_syndrome_c9[27:0]),
5192 .deccck_uncorr_err_c8 (deccck_uncorr_err_c8),
5193 .deccck_corr_err_c8 (deccck_corr_err_c8),
5194 .deccck_notdata_err_c8 (deccck_notdata_err_c8),
5195 .csr_error_ceen (csr_error_ceen),
5196 .csr_error_nceen (csr_error_nceen),
5197 .tag_spc_rd_vld_c6(tag_spc_rd_vld_c6),
5198 // Inputs
5199 .filbuf_spc_rd_vld_c6 (filbuf_spc_rd_vld_c6),
5200 .filbuf_spc_uncorr_err_c6(filbuf_spc_uncorr_err_c6),
5201 .filbuf_spc_corr_err_c6(filbuf_spc_corr_err_c6),
5202 .tcu_l2t_tag_or_data_sel(tcu_l2t_tag_or_data_sel),
5203 .decc_ret_diag_data_c7 (decc_ret_diag_data_c7[38:0]),
5204 .tagd_evict_tag_c3 (tagd_dmo_evict_tag_c4[27:0]),
5205 .deccck_muxsel_diag_out_c7(deccck_muxsel_diag_out_c7[3:0]),
5206 .mbist_write_data (mbist_write_data_decck[7:0]),
5207 .deccck_dword_sel_c7 (deccck_dword_sel_c7),
5208 //.retbuf_ret_data_c7 (retbuf_ret_data_c7[127:0]),
5209 //.retbuf_ret_ecc_c7 (retbuf_ret_ecc_c7[27:0]),
5210 .l2d_l2t_decc_c6 (l2d_l2t_decc_c6[155:0]),
5211 .scan_in(decc_scanin),
5212 .scan_out(decc_scanout),
5213 .l2clk (l2clk),
5214 .oqu_l2_miss_c7(oqu_l2_miss_c7),
5215 .oqu_uerr_ack_c7(oqu_uerr_ack_c7),
5216 .oqu_cerr_ack_c7(oqu_cerr_ack_c7),
5217 .oqu_imiss_hit_c8(oqu_imiss_hit_c8),
5218 .rtn_err_field_c7(rtn_err_field_c7[2:0]),
5219 .mbist_dmo_data_out(mbist_dmo_data_out[38:0]),
5220 .deccdp_decck_uncorr_err_c7(deccdp_decck_uncorr_err_c7[3:0]),
5221 .deccdp_decck_corr_err_c7(deccdp_decck_corr_err_c7[3:0]),
5222 .tcu_muxtest(tcu_muxtest),
5223 .mbist_l2data_fail(mbist_l2data_fail),
5224 .mbist_l2d_write(mbist_l2d_write)
5225 );
5226
5227
5228//
5229// l2t_shdwscn_dp block should not be hooked up to the main scan chain
5230//
5231l2t_shdwscn_dp shadow_scan
5232 (
5233 .tcu_l2t_shscan_scan_in (tcu_l2t_shscan_scan_in ),
5234 .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ),
5235 .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ),
5236 .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ),
5237 .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ),
5238 .tcu_l2t_shscan_clk_stop_d2 (tcu_l2t_shscan_clk_stop_d2),
5239 .l2t_tcu_shscan_scan_out (l2t_tcu_shscan_scan_out),
5240 .rd_errstate_reg (shadow_error_status_reg[63:0] ),
5241 .rd_notdata_reg (shadow_notdata_reg[`ERR_MEND:`ERR_NDADR_LO]),
5242 .csr_l2_erraddr_reg (shadow_l2erraddr_reg[39:4]),
5243 .l2clk (l2clk)
5244 );
5245
5246/////////////////////////////////////////////////////////////////////////
5247l2t_csr_ctl csr (
5248 .tcu_pce_ov(ce_ovrd),
5249 .tcu_aclk(aclk),
5250 .tcu_bclk(bclk),
5251 .tcu_scan_en(tcu_scan_en),
5252 .aclk_wmr(aclk_wmr),
5253 .wmr_protect(wmr_protect),
5254 // Outputs
5255 .arbadr_csr_debug_addr (arbadr_csr_debug_addr[33:2]),
5256 .l2t_dbg_err_event (l2t_dbg_err_event),
5257 .csr_report_ldrc (csr_report_ldrc),
5258 .l2t_dbg_pa_match (l2t_dbg_pa_match),
5259 .csreg_l2_cmpr_reg_wr_en_c8 (csreg_l2_cmpr_reg_wr_en_c8),
5260 .csreg_l2_mask_reg_wr_en_c8 (csreg_l2_mask_reg_wr_en_c8),
5261 .csr_filbuf_scrub_ready (csr_filbuf_scrub_ready),
5262 .csr_l2_bypass_mode_on (csr_l2_bypass_mode_on),
5263 .csr_filbuf_l2off (csr_filbuf_l2off),
5264 .csr_tag_l2off (csr_tag_l2off),
5265 .csr_wbuf_l2off (csr_wbuf_l2off),
5266 .csr_misbuf_l2off (csr_misbuf_l2off),
5267 .csr_vuad_l2off (csr_vuad_l2off),
5268 .csr_l2_dir_map_on (csr_l2_dir_map_on),
5269 // .csr_l2_dbg_en (csr_l2_dbg_en),
5270 .csr_l2_steering_tid (csr_l2_steering_tid[5:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
5271 .csr_error_nceen (csr_error_nceen),
5272 .csr_error_ceen (csr_error_ceen),
5273 .csr_wr_dirpinj_en (csr_wr_dirpinj_en),
5274 .csr_oneshot_dir_clear_c3 (csr_oneshot_dir_clear_c3),
5275 .csr_rd_data_c8 (csr_rd_data_c8[63:0]),
5276 .csr_error_status_veu (csr_error_status_veu),
5277 .csr_error_status_vec (csr_error_status_vec),
5278// .l2t_clk_tr (1'b0),
5279 .shadow_error_status_reg(shadow_error_status_reg[63:0] ),
5280 .shadow_notdata_reg (shadow_notdata_reg[`ERR_MEND:`ERR_NDADR_LO]),
5281 .shadow_l2erraddr_reg (shadow_l2erraddr_reg[39:4]),
5282 // Inputs
5283 .csreg_csr_bist_wr_en_c8(csreg_csr_bist_wr_en_c8),
5284 .csr_error_status_notdata(csr_error_status_notdata),
5285 .csreg_notdata_error_rw_en(csreg_notdata_error_rw_en),
5286 .csreg_csr_notdata_wr_en_c8(csreg_csr_notdata_wr_en_c8),
5287 .csreg_wr_enable_notdata_vcid_c9(csreg_wr_enable_notdata_vcid_c9),
5288 .csreg_csr_notdata_vcid_wr_en(csreg_csr_notdata_vcid_wr_en),
5289 .csreg_notdata_err_state_in_rw(csreg_notdata_err_state_in_rw),
5290 .csreg_notdata_err_state_in_mend(csreg_notdata_err_state_in_mend),
5291 .csreg_notdata_err_state_in(csreg_notdata_err_state_in[`ERR_NDSP:`ERR_NDDM]),
5292 .csreg_notdata_diag_wr_en(csreg_notdata_diag_wr_en),
5293 .csreg_csr_notdata_addr_wr_en(csreg_csr_notdata_addr_wr_en),
5294 .csreg_notdata_addr_mux_sel(csreg_notdata_addr_mux_sel[2:0]),
5295 .arbdat_csr_inst_wr_data_c8(arbdat_csr_inst_wr_data_c8[63:0]),
5296 .arb_inst_vld_c2 (arb_inst_vld_c2),
5297 .scan_in(csr_scanin),
5298 .scan_out(csr_scanout),
5299 .l2clk (l2clk),
5300 .csreg_csr_rd_mux4_sel_c7 (csreg_csr_rd_mux4_sel_c7[1:0]),
5301 .csreg_csr_rd_mux_fnl_c7 (csreg_csr_rd_mux_fnl_c7[1:0]),
5302 .csreg_csr_erren_wr_en_c8 (csreg_csr_erren_wr_en_c8),
5303 .csreg_csr_wr_en_c8 (csreg_csr_wr_en_c8),
5304 .csreg_csr_errstate_wr_en_c8 (csreg_csr_errstate_wr_en_c8),
5305 .csreg_csr_errinj_wr_en_c8 (csreg_csr_errinj_wr_en_c8),
5306 .csreg_csr_rd_mux1_sel_c7 (csreg_csr_rd_mux1_sel_c7[3:0]),
5307 .csreg_csr_rd_mux2_sel_c7 (csreg_csr_rd_mux2_sel_c7),
5308 .csreg_csr_rd_mux3_sel_c7 (csreg_csr_rd_mux3_sel_c7[1:0]),
5309 .arbadr_arbdp_csr_addr_c9 (arbdp_csr_addr_c9[39:4]),
5310 .evctag_evict_addr (evctag_evict_addr[39:6]),
5311 .arbadr_rdmard_addr_c12 (arbadr_rdmard_addr_c12[39:6]),
5312 .arb_dir_addr_c9 (arb_dir_addr_c9[10:0]),
5313 .tag_scrub_addr_way (tag_scrub_addr_way[3:0]),
5314 .arbadr_data_ecc_idx (arbadr_data_ecc_idx[8:0]),
5315 .csreg_err_state_in_rw (csreg_err_state_in_rw),
5316 .csreg_err_state_in_mec (csreg_err_state_in_mec),
5317 .csreg_err_state_in_meu (csreg_err_state_in_meu),
5318 .csreg_err_state_in (csreg_err_state_in[`ERR_LDAC:`ERR_LVC]),
5319 .csreg_mux1_synd_sel (csreg_mux1_synd_sel[1:0]),
5320 .csreg_mux2_synd_sel (csreg_mux2_synd_sel[1:0]),
5321 .csreg_csr_synd_wr_en (csreg_csr_synd_wr_en),
5322 .usaloc_ua_synd_c9 (usaloc_ua_synd_c9[6:0]),
5323 .vlddir_vd_synd_c9 (vlddir_vd_synd_c9[6:0]),
5324 .decc_lda_syndrome_c9 (decc_lda_syndrome_c9[27:0]),
5325 .csreg_wr_enable_tid_c9 (csreg_wr_enable_tid_c9),
5326 .csreg_csr_tid_wr_en (csreg_csr_tid_wr_en),
5327 .csreg_csr_async_wr_en (csreg_csr_async_wr_en),
5328 .csreg_mux1_addr_sel (csreg_mux1_addr_sel[3:0]),
5329 .csreg_mux2_addr_sel (csreg_mux2_addr_sel[2:0]),
5330 .csreg_csr_addr_wr_en (csreg_csr_addr_wr_en),
5331 .arb_dir_wr_en_c4 (arb_dir_wr_en_c4),
5332 .oque_tid_c8 (oque_tid_c8[5:0]),
5333 .csreg_report_ldrc_inpkt(csreg_report_ldrc_inpkt),
5334 .notdata_higher_priority_err(notdata_higher_priority_err),
5335 .arbdec_csr_ttype_c6(arbdec_csr_ttype_c6[4:0]),
5336 .arbdec_csr_vcid_c6(arbdec_csr_vcid_c6[5:0]),
5337 .csreg_wr_enable_notdata_nddm_vcid_c9(csreg_wr_enable_notdata_nddm_vcid_c9),
5338 .set_async_c9(set_async_c9),
5339 .error_rw_en(error_rw_en),
5340 .diag_wr_en(diag_wr_en));
5341
5342l2t_csreg_ctl csreg (
5343 .tcu_pce_ov(ce_ovrd),
5344 .tcu_aclk(aclk),
5345 .tcu_bclk(bclk),
5346 .tcu_scan_en(tcu_scan_en),
5347 // Outputs
5348 .csreg_notdata_error_rw_en(csreg_notdata_error_rw_en),
5349 .csreg_csr_notdata_wr_en_c8(csreg_csr_notdata_wr_en_c8),
5350 .csreg_wr_enable_notdata_vcid_c9(csreg_wr_enable_notdata_vcid_c9),
5351 .csreg_csr_notdata_vcid_wr_en(csreg_csr_notdata_vcid_wr_en),
5352 .csreg_notdata_err_state_in_rw(csreg_notdata_err_state_in_rw),
5353 .csreg_notdata_err_state_in_mend(csreg_notdata_err_state_in_mend),
5354 .csreg_notdata_err_state_in(csreg_notdata_err_state_in[`ERR_NDSP:`ERR_NDDM]),
5355 .csreg_notdata_diag_wr_en(csreg_notdata_diag_wr_en),
5356 .csreg_csr_notdata_addr_wr_en(csreg_csr_notdata_addr_wr_en),
5357 .csreg_notdata_addr_mux_sel(csreg_notdata_addr_mux_sel[2:0]),
5358 .csreg_csr_rd_mux4_sel_c7 (csreg_csr_rd_mux4_sel_c7[1:0]),
5359 .csreg_csr_rd_mux_fnl_c7 (csreg_csr_rd_mux_fnl_c7[1:0]),
5360 .csreg_tagdp_l2_dir_map_on(csreg_tagdp_l2_dir_map_on),
5361 .csreg_misbuf_l2_dir_map_on(csreg_misbuf_l2_dir_map_on),
5362 .csreg_filbuf_l2_dir_map_on(csreg_filbuf_l2_dir_map_on),
5363 .csreg_csr_wr_en_c8(csreg_csr_wr_en_c8),
5364 .csreg_csr_erren_wr_en_c8(csreg_csr_erren_wr_en_c8),
5365 .csreg_csr_errstate_wr_en_c8(csreg_csr_errstate_wr_en_c8),
5366 .csreg_csr_errinj_wr_en_c8(csreg_csr_errinj_wr_en_c8),
5367 .csreg_err_state_in_rw (csreg_err_state_in_rw),
5368 .csreg_err_state_in_mec(csreg_err_state_in_mec),
5369 .csreg_err_state_in_meu(csreg_err_state_in_meu),
5370 .csreg_err_state_in (csreg_err_state_in[`ERR_LDAC:`ERR_LVC]),
5371 .csreg_csr_synd_wr_en (csreg_csr_synd_wr_en),
5372 .csreg_mux1_synd_sel (csreg_mux1_synd_sel[1:0]),
5373 .csreg_mux2_synd_sel (csreg_mux2_synd_sel[1:0]),
5374 .csreg_wr_enable_tid_c9(csreg_wr_enable_tid_c9),
5375 .csreg_csr_tid_wr_en (csreg_csr_tid_wr_en),
5376 .csreg_csr_async_wr_en (csreg_csr_async_wr_en),
5377 .csreg_mux1_addr_sel (csreg_mux1_addr_sel[3:0]),
5378 .csreg_mux2_addr_sel (csreg_mux2_addr_sel[2:0]),
5379 .csreg_csr_addr_wr_en (csreg_csr_addr_wr_en),
5380 .csreg_csr_rd_mux1_sel_c7(csreg_csr_rd_mux1_sel_c7[3:0]),
5381 .csreg_csr_rd_mux2_sel_c7(csreg_csr_rd_mux2_sel_c7),
5382 .csreg_csr_rd_mux3_sel_c7(csreg_csr_rd_mux3_sel_c7[1:0]),
5383 .csreg_csr_bist_wr_en_c8(csreg_csr_bist_wr_en_c8),
5384 .l2t_rst_fatal_error(l2t_rst_fatal_error),
5385 // Inputs
5386 .csreg_l2_cmpr_reg_wr_en_c8 (csreg_l2_cmpr_reg_wr_en_c8),
5387 .csreg_l2_mask_reg_wr_en_c8 (csreg_l2_mask_reg_wr_en_c8),
5388 .misbuf_vuad_ce_err_c8(misbuf_vuad_ce_err_c8),
5389 .csr_error_status_notdata(csr_error_status_notdata),
5390 .rdmat_rdmard_notdata_c12(rdmat_rdmard_notdata_c12),
5391 .deccck_spcd_notdata_err_c8(deccck_spcd_notdata_err_c8),
5392 .deccck_bscd_notdata_err_c8(deccck_bscd_notdata_err_c8),
5393 .csr_l2_dir_map_on(csr_l2_dir_map_on),
5394 .arb_csr_wr_en_c7(arb_csr_wr_en_c7),
5395 .arbadr_arbdp_word_addr_c6(arbadr_arbdp_word_addr_c6[4:0]),
5396 .scan_in(csreg_scanin),
5397 .scan_out(csreg_scanout),
5398 .l2clk (l2clk),
5399 .vuaddp_vuad_error_c8 (vuaddp_vuad_error_c8),
5400 .dirrep_dir_error_c8 (dirrep_dir_error_c8),
5401 .deccck_spcd_corr_err_c8(deccck_spcd_corr_err_c8),
5402 .deccck_spcd_uncorr_err_c8(deccck_spcd_uncorr_err_c8),
5403 .deccck_scrd_corr_err_c8(deccck_scrd_corr_err_c8),
5404 .deccck_scrd_uncorr_err_c8(deccck_scrd_uncorr_err_c8),
5405 .deccck_spcfb_corr_err_c8(deccck_spcfb_corr_err_c8),
5406 .deccck_spcfb_uncorr_err_c8(deccck_spcfb_uncorr_err_c8),
5407 .deccck_bscd_corr_err_c8(deccck_bscd_corr_err_c8),
5408 .deccck_bscd_uncorr_err_c8(deccck_bscd_uncorr_err_c8),
5409 .tagdp_tag_error_c8 (tagdp_tag_error_c8),
5410 .filbuf_mcu_scb_secc_err_d1(filbuf_mcu_scb_secc_err_d1),
5411 .filbuf_mcu_scb_mecc_err_d1(filbuf_mcu_scb_mecc_err_d1),
5412 .filbuf_uncorr_err_c8(filbuf_uncorr_err_c8),
5413 .filbuf_corr_err_c8(filbuf_corr_err_c8),
5414 .filbuf_bsc_corr_err_c12(filbuf_bsc_corr_err_c12),
5415 .filbuf_ld64_fb_hit_c12(filbuf_ld64_fb_hit_c12),
5416 .rdmat_ev_uerr_r6 (rdmat_ev_uerr_r6),
5417 .rdmat_ev_cerr_r6 (rdmat_ev_cerr_r6),
5418 .rdmat_rdmard_uerr_c12 (rdmat_rdmard_uerr_c12),
5419 .rdmat_rdmard_cerr_c12 (rdmat_rdmard_cerr_c12),
5420 .csr_error_status_vec(csr_error_status_vec),
5421 .csr_error_status_veu(csr_error_status_veu),
5422 .arb_store_err_c8 (arb_store_err_c8),
5423 .oqu_str_ld_hit_c7 (oqu_str_ld_hit_c7),
5424 .cmp_io_sync_en(cmp_io_sync_en),
5425 .csreg_wr_enable_notdata_nddm_vcid_c9(csreg_wr_enable_notdata_nddm_vcid_c9),
5426 .notdata_higher_priority_err(notdata_higher_priority_err),
5427 .csr_l2_bypass_mode_on(csr_l2_bypass_mode_on),
5428 .set_async_c9(set_async_c9),
5429 .error_rw_en(error_rw_en),
5430 .diag_wr_en(diag_wr_en),
5431 .csreg_report_ldrc_inpkt(csreg_report_ldrc_inpkt),
5432 .arb_fill_vld_c2(arb_fill_vld_c2));
5433
5434
5435l2t_snp_ctl snp(
5436 // Outputs
5437 .l2t_sii_iq_dequeue (l2t_sii_iq_dequeue),
5438 .snp_snpq_arb_vld_px1 (snp_snpq_arb_vld_px1),
5439 .l2t_dbg_sii_iq_dequeue (l2t_dbg_sii_iq_dequeue_unreg),
5440 .snp_hdr1_wen0_s0 (snp_hdr1_wen0_s0),
5441 .snp_hdr2_wen0_s1 (snp_hdr2_wen0_s1),
5442 .snp_snp_data1_wen0_s2 (snp_data1_wen0_s2),
5443 .snp_snp_data2_wen0_s3 (snp_data2_wen0_s3),
5444 .snp_hdr1_wen1_s0 (snp_hdr1_wen1_s0),
5445 .snp_hdr2_wen1_s1 (snp_hdr2_wen1_s1),
5446 .snp_snp_data1_wen1_s2 (snp_data1_wen1_s2),
5447 .snp_snp_data2_wen1_s3 (snp_data2_wen1_s3),
5448 .snp_wr_ptr (snp_wr_ptr),
5449 .snp_rd_ptr (snp_rd_ptr),
5450 .snp_rdmad_wr_entry_s2 (snp_rdmad_wr_entry_s2[1:0]),
5451 .l2t_l2b_rdma_wren_s2 (l2t_l2b_rdma_wren_s2[15:0]),
5452 .l2t_l2b_rdma_wrwl_s2 (l2t_l2b_rdma_wrwl_s2[1:0]),
5453 // Inputs
5454 .l2t_siu_delay (l2t_siu_delay),
5455 .tcu_pce_ov (ce_ovrd),
5456 .tcu_aclk (aclk),
5457 .tcu_bclk (bclk),
5458 .tcu_scan_en (tcu_scan_en),
5459 .snp_rdmatag_wr_en_s2 (rdmatag_wr_en_s2),
5460 .wmr_l (wmr_l),
5461 .rdmat_sii_req_vld_buf (sii_l2t_req_vld),
5462 .snpd_rq_winv_s1 (snpd_rq_winv_s1),
5463 .rdmat_wr_entry_s1 (rdmat_wr_entry_s1[1:0]),
5464 .scan_in(snp_scanin),
5465 .scan_out(snp_scanout),
5466 .l2clk (l2clk),
5467 .arb_snp_snpsel_px2(arb_snp_snpsel_px2),
5468 .l2t_mb2_run(l2t_mb2_run),
5469 .l2t_mb2_rdmatag_wr_en(l2t_mb2_rdmatag_wr_en));
5470
5471
5472l2t_snpd_dp snpd(
5473 // Outputs
5474 .snpd_snpq_arbdp_addr_px2 (snpd_snpq_arbdp_addr_px2[39:0]),
5475 .snpd_snpq_arbdp_inst_px2 (snpd_snpq_arbdp_inst_px2[`JBI_HDR_SZ_LESS1:0]),
5476 .snpd_snpq_arbdp_data_px2 (snpd_snpq_arbdp_data_px2[63:0]),
5477 .snpd_ecc_px2 (snpd_ecc_px2[6:0]),
5478 .snpd_rq_winv_s1 (snpd_rq_winv_s1),
5479 // Inputs
5480 .l2t_siu_delay (l2t_siu_delay),
5481 .tcu_pce_ov (ce_ovrd),
5482 .tcu_aclk (aclk),
5483 .tcu_bclk (bclk),
5484 .tcu_scan_en (tcu_scan_en),
5485 .tcu_clk_stop (1'b0),
5486 .snpd_rdmatag_wr_addr_s2 (rdmatag_wr_addr_s2[39:6]),
5487 .scan_in(snpd_scanin),
5488 .scan_out(snpd_scanout),
5489 .l2clk (l2clk),
5490 .sii_l2t_req (sii_l2t_req[31:0]),
5491 .sii_l2b_ecc (sii_l2b_ecc[6:0]),
5492 .snp_hdr1_wen0_s0 (snp_hdr1_wen0_s0),
5493 .snp_hdr2_wen0_s1 (snp_hdr2_wen0_s1),
5494 .snp_snp_data1_wen0_s2 (snp_data1_wen0_s2),
5495 .snp_snp_data2_wen0_s3 (snp_data2_wen0_s3),
5496 .snp_hdr1_wen1_s0 (snp_hdr1_wen1_s0),
5497 .snp_hdr2_wen1_s1 (snp_hdr2_wen1_s1),
5498 .snp_snp_data1_wen1_s2 (snp_data1_wen1_s2),
5499 .snp_snp_data2_wen1_s3 (snp_data2_wen1_s3),
5500 .snp_wr_ptr (snp_wr_ptr),
5501 .snp_rd_ptr (snp_rd_ptr),
5502 .snp_rdmad_wr_entry_s2 (snp_rdmad_wr_entry_s2[1:0]),
5503 .l2t_mb2_wdata(l2t_mb2_wdata[7:0]),
5504 .l2t_mb2_run(l2t_mb2_run));
5505
5506
5507l2t_evctag_dp evctag(
5508 .tcu_pce_ov(ce_ovrd),
5509 .tcu_aclk(aclk),
5510 .tcu_bclk(bclk),
5511 .tcu_scan_en(tcu_scan_en),
5512 .tcu_clk_stop(1'b0),
5513 .wb_read_data(wb_read_data[39:0]),
5514 .rdma_read_data(rdma_read_data[39:0]),
5515 .evctag_lkup_addr_c1(lkup_addr_c1[39:7]),
5516 .evctag_mb_write_addr(mb_write_addr[41:0]),
5517 .evctag_wb_write_addr(wb_write_addr[39:0]),
5518 .mbdata_din (mbdata_din[127:64]),
5519 .fbtag_din (fbtag_din[39:0]),
5520 // Outputs
5521 // .mbist_cam_read_data(mbist_cam_read_data[41:0]),
5522 .arbadr_2bnk_true_enbld_dist (arbadr_evctag_2bnk_true_enbld_dist),
5523 .arbadr_4bnk_true_enbld_dist (arbadr_evctag_4bnk_true_enbld_dist),
5524 .arbadr_ncu_l2t_pm_n_dist (arbadr_evctag_ncu_l2t_pm_n_dist),
5525 .fbtag_din_unbuff({evctag_mb_read_data[39:6],mb_data_read_data[`MBD_ECC_HI:`MBD_ECC_LO]}),
5526 .mbdata_din_unbuf ({10'b0,arbdec_snpd_ecc_c8[6:0],misbuf_mbentry_c8[4:0],mbdata_inst_tecc_c8[5:0],misbuf_evict_c8,misbuf_dep_c8,misbuf_tecc_c8,4'b0,arbdp_inst_c8[`L2_POISON:`L2_SZ_LO]}),
5527 .cam_mb2_rw_fail (cam_mb2_rw_fail),
5528 .evctag_addr_px2(evctag_addr_px2[39:0]),
5529 .evctag_evict_addr (evctag_evict_addr[39:6]),
5530 .l2t_mcu_addr(l2t_mcu_addr[39:7]),
5531 .l2t_mcu_addr_5(l2t_mcu_addr_5),
5532 .evctag_vuad_idx_c3 (evctag_vuad_idx_c3[8:0]),
5533 .evctag_mb_read_data(evctag_mb_read_data[39:0]),
5534 .arbadr_mbcam_addr_px2(arbadr_mbcam_addr_px2[41:7]),
5535 .arbadr_mbcam_addr_px2_buff(arbadr_mbcam_addr_px2_buff[41:7]),
5536 // Inputs
5537 .mb_read_data(mb_read_data[41:0]),
5538 .fb_read_data(fb_read_data[39:0]),
5539 .arbadr_arbdp_cam_addr_px2(arbdp_cam_addr_px2[39:0]),
5540 .tagd_evict_tag_c4(tagd_evict_tag_c4[`TAG_WIDTH_LESS1:6]), // Templated
5541 .wbuf_wr_addr_sel(wbuf_wr_addr_sel),
5542 .wbuf_wb_or_rdma_wr_req_en(wbuf_wb_or_rdma_wr_req_en),
5543 .misbuf_arb_l2rd_en(misbuf_arb_l2rd_en),
5544 .misbuf_arb_mcurd_en(misbuf_arb_mcurd_en),
5545 .filbuf_arb_l2rd_en(filbuf_arb_l2rd_en),
5546 .arb_mux1_mbsel_px1(arb_mux1_mbsel_px1),
5547 .arb_evict_c4(arb_evict_c4),
5548 .scan_in(evctag_scanin),
5549 .scan_out(evctag_scanout),
5550 .l2clk (l2clk),
5551 .misbuf_buf_rd_en(misbuf_buf_rd_en),
5552 .filbuf_buf_rd_en(filbuf_buf_rd_en),
5553 .wb_read_en(wb_read_en),
5554 .rdmat_read_en(rdmat_read_en),
5555 .l2t_mb2_run(l2t_mb2_run),
5556 .mbist_cam_sel(mbist_cam_sel[3:0]),
5557 .l2t_mb2_wdata(l2t_mb2_wdata[7:0]));
5558
5559n2_com_cm_8x40_cust rdmatag
5560 (
5561 .dout(rdma_read_data[39:0]), // BS and SR 8 deep change 3/3/04
5562 .match(rdmat_cam_match_c2[7:0]),
5563 .match_idx(rd_match_idx_unused[7:0]),
5564 .adr_w({4'b0, rdmat_wr_wl_s2[3:0]}),
5565 .din({rdmatag_wr_addr_s2[39:6],6'b0}),
5566 .write_en(rdmatag_wr_en_s2),
5567 .adr_r({4'b0,rdmat_read_wl[3:0]}),
5568 .lookup_en(arb_inst_vld_c1_v3),
5569 .key(lkup_addr_c1[39:7]),
5570 .tcu_array_wr_inhibit(array_wr_inhibit),
5571 .scan_in(rdmatag_scanin),
5572 .scan_out(rdmatag_scanout),
5573 .l2clk(l2clk),
5574 .pce(1'b1),
5575 .read_en(rdmat_read_en),
5576 .tcu_aclk(aclk),
5577 .tcu_bclk(bclk),
5578 .tcu_scan_en(tcu_scan_en),
5579 .tcu_pce_ov(ce_ovrd),
5580 .tcu_clk_stop(1'b0),
5581 .tcu_array_bypass (tcu_array_bypass),
5582 .tcu_se_scancollar_out(tcu_se_scancollar_out),
5583 .tcu_se_scancollar_in(tcu_se_scancollar_in));
5584
5585
5586l2t_rdmarpt_dp rdmarpt
5587 (
5588 .scan_in (rdmatag_scanout),
5589 .tcu_clk_stop(1'b0),
5590 .scan_out (rdmarpt_scanout),
5591 .l2t_l2b_fbrd_en_c3(l2t_l2b_fbrd_en_c3),
5592 .l2t_l2b_fbrd_wl_c3(l2t_l2b_fbrd_wl_c3[2:0]),
5593 .l2t_l2b_fbwr_wl_r2(l2t_l2b_fbwr_wl_r2[2:0]),
5594 .filbuf_fbd_rd_en_c2(filbuf_fbd_rd_en_c2),
5595 .filbuf_fbd_rd_entry_c2(filbuf_fbd_rd_entry_c2[2:0]),
5596 .filbuf_fbd_wr_entry_r1(filbuf_fbd_wr_entry_r1[2:0]),
5597 .l2clk(l2clk),
5598 .tcu_pce_ov(tcu_pce_ov),
5599 .tcu_aclk(tcu_aclk),
5600 .tcu_bclk(tcu_bclk),
5601 .tcu_scan_en(tcu_scan_en)
5602 );
5603
5604l2t_rdmat_ctl rdmat(
5605 .tcu_pce_ov(ce_ovrd),
5606 .tcu_aclk(aclk),
5607 .tcu_bclk(bclk),
5608 .tcu_scan_en(tcu_scan_en),
5609 .snp_rdmatag_wr_en_s2(rdmatag_wr_en_s2),
5610 .rdma_mbist_cam_hit(rdma_mbist_cam_hit),
5611 .rdma_mbist_cam_sel(mbist_cam_sel[3]),
5612 .rdmat_cam_match_c2(rdmat_cam_match_c2[3:0]),
5613 .rdmat_wr_wl_s2(rdmat_wr_wl_s2[3:0]),
5614 .wmr_l (wmr_l),
5615 .l2t_mb2_addr (l2t_mb2_addr[3:0]),
5616 .l2t_mb2_run (l2t_mb2_run),
5617 // Outputs
5618 .rdmat_rdmard_notdata_c12(rdmat_rdmard_notdata_c12),
5619 .rdmat_wr_entry_s1(rdmat_wr_entry_s1[1:0]),
5620 .rdmat_or_rdmat_valid(rdmat_or_rdmat_valid),
5621 .rdmat_pick_vec(rdmat_pick_vec[3:0]),
5622 .rdmat_rdma_hit_unqual_c2(rdmat_hit_unqual_c2),
5623 .rdmat_rdma_misbuf_dep_rdy_en(rdmat_misbuf_dep_rdy_en),
5624 .rdmat_rdma_misbuf_dep_mbid(rdmat_misbuf_dep_mbid[4:0]),
5625 //.l2t_l2b_fbwr_wl_r2(l2t_l2b_fbwr_wl_r2[2:0]),
5626 //.l2t_l2b_fbrd_en_c3(l2t_l2b_fbrd_en_c3),
5627 //.l2t_l2b_fbrd_wl_c3(l2t_l2b_fbrd_wl_c3[2:0]),
5628 .l2t_l2b_word_vld_c7(l2t_l2b_word_vld_c7),
5629 .l2t_l2b_ctag_en_c7(l2t_l2b_ctag_en_c7),
5630 .l2t_l2b_req_en_c7(l2t_l2b_req_en_c7),
5631 .l2t_l2b_word_c7(l2t_l2b_word_c7[3:0]),
5632 .rdmat_rdmard_cerr_c12(rdmat_rdmard_cerr_c12),
5633 .rdmat_rdmard_uerr_c12(rdmat_rdmard_uerr_c12),
5634 .rdmat_ev_uerr_r6 (rdmat_ev_uerr_r6),
5635 .rdmat_ev_cerr_r6 (rdmat_ev_cerr_r6),
5636 //.l2t_l2b_fbwr_wen_r2(l2t_l2b_fbwr_wen_r2[15:0]),
5637 //.l2t_l2b_fbd_stdatasel_c3(l2t_l2b_fbd_stdatasel_c3),
5638 .l2t_l2b_ctag_c7(l2t_l2b_ctag_c7[31:0]), // Phase 2 : SIU inteface and packet format change 2/7/04
5639
5640 // Inputs
5641 .wbuf_reset_rdmat_vld(wbuf_reset_rdmat_vld[3:0]),
5642 .l2t_dbg_xbar_vcid_unreg (l2t_dbg_xbar_vcid_transfer[5:0]),
5643 .l2t_dbg_xbar_vcid(l2t_dbg_xbar_vcid[5:0]),
5644 .l2t_dbg_sii_iq_dequeue_unreg(l2t_dbg_sii_iq_dequeue_unreg),
5645 .l2t_dbg_sii_iq_dequeue(l2t_dbg_sii_iq_dequeue),
5646 .wbuf_set_rdmat_acked(wbuf_set_rdmat_acked[3:0]),
5647 .arb_wbuf_inst_vld_c2(arb_wbuf_inst_vld_c2),
5648 .arb_wbuf_hit_off_c1(arb_wbuf_hit_off_c1),
5649 .arbdec_arbdp_rdma_entry_c3(arbdec_arbdp_rdma_entry_c3[1:0]),
5650 .misbuf_wbuf_mbid_c4(misbuf_wbuf_mbid_c4[4:0]),
5651 .misbuf_hit_c4 (misbuf_hit_c4),
5652 .tag_rdma_ev_en_c4(tag_rdma_ev_en_c4),
5653 .scan_in(rdmarpt_scanout),
5654 .scan_out(rdmat_scanout),
5655 .l2clk (l2clk),
5656 .l2b_l2t_rdma_cerr_c10(l2b_l2t_rdma_cerr_c10),
5657 .l2b_l2t_rdma_uerr_c10(l2b_l2t_rdma_uerr_c10),
5658 .l2b_l2t_rdma_notdata_c10(l2b_l2t_rdma_notdata_c10),
5659 .l2b_l2t_ev_uerr_r5(l2b_l2t_ev_uerr_r5),
5660 .l2b_l2t_ev_cerr_r5(l2b_l2t_ev_cerr_r5),
5661 .arbdec_ctag_c6(arbdec_ctag_c6[31:0]),
5662 .tag_inc_rdma_cnt_c4(tag_inc_rdma_cnt_c4),
5663 .tag_set_rdma_reg_vld_c4(tag_set_rdma_reg_vld_c4),
5664 .tag_siu_req_en_c52(tag_siu_req_en_c52),
5665 .arbdp_rdma_addr_c6(arbadr_arbdp_rdmat_addr_c6[5:2])
5666 //.filbuf_fbd_rd_en_c2(filbuf_fbd_rd_en_c2),
5667 //.filbuf_fbd_rd_entry_c2(filbuf_fbd_rd_entry_c2[2:0]),
5668 //.filbuf_fbd_wr_entry_r1(filbuf_fbd_wr_entry_r1[2:0])
5669 );
5670
5671
5672//l2t_dbg_dp dbg(
5673// .tcu_pce_ov(ce_ovrd),
5674// .tcu_aclk(aclk),
5675// .tcu_bclk(bclk),
5676// .tcu_scan_en(tcu_scan_en),
5677// .tcu_clk_stop(tcu_clk_stop),
5678// .arbadr_arbdp_dbg_addr_c3 ({arbadr_dir_cam_addr_c3[33:8], arbdp_dbg_addr_c3[5:2]}),
5679// // Outputs
5680// .l2t_dbgbus_out (l2t_dbgbus_out[41:0]), // BS and SR 11/12/03 N2 Xbar Packet format change
5681// // Inputs
5682// .csr_l2_dbg_en (csr_l2_dbg_en),
5683// .scan_in(dbg_scanin),
5684// .scan_out(dbg_scanout),
5685// .l2clk (l2clk));
5686//
5687//l2t_ret_dp ret(
5688// .tcu_pce_ov(ce_ovrd),
5689// .tcu_aclk(aclk),
5690// .tcu_bclk(bclk),
5691// .tcu_scan_en(tcu_scan_en),
5692// .tcu_clk_stop(1'b0),
5693// /*AUTOINST*/
5694// // Outputs
5695// .ret_data_c7_buf (retbuf_ret_data_c7[127:0]),
5696// .ret_ecc_c7_buf (retbuf_ret_ecc_c7[27:0]),
5697// // Inputs
5698// .l2d_l2t_decc_c6(l2d_l2t_decc_c6[155:0]),
5699// .scan_in(ret_scanin),
5700// .scan_out(ret_scanout),
5701// .l2clk (l2clk));
5702
5703l2t_dirrep_ctl dirrep(
5704 .tcu_pce_ov(ce_ovrd),
5705 .tcu_aclk(aclk),
5706 .tcu_bclk(bclk),
5707 .tcu_scan_en(tcu_scan_en),
5708 /*AUTOINST*/
5709 // Outputs
5710 .dirrep_dir_vld_c4_l (dirrep_dir_vld_c4_l),
5711 .dirrep_dir_wr_par_c4 (dirrep_dir_wr_par_c4),
5712 .dirrep_dc_rd_en_c4 (dirrep_dc_rd_en_c4),
5713 .dirrep_dc_wr_en_c4 (dirrep_dc_wr_en_c4),
5714 .dirrep_inval_mask_dcd_c4(dirrep_inval_mask_dcd_c4[7:0]),
5715 .dirrep_dc_rdwr_row_en_c4(dirrep_dc_rdwr_row_en_c4[3:0]),
5716 .dirrep_dc_rdwr_panel_dec_c4(dirrep_dc_rdwr_panel_dec_c4[3:0]),
5717 .dirrep_dc_lkup_row_dec_c4(dirrep_dc_lkup_row_dec_c4[3:0]),
5718 .dirrep_dc_lkup_panel_dec_c4(dirrep_dc_lkup_panel_dec_c4[3:0]),
5719 .dirrep_wr_dc_dir_entry_c4(dirrep_wr_dc_dir_entry_c4[4:0]), // BS and SR 11/18/03 Reverse Directory change
5720 .dirrep_dc_dir_clear_c4 (dirrep_dc_dir_clear_c4),
5721 .dirrep_ic_rd_en_c4 (dirrep_ic_rd_en_c4),
5722 .dirrep_ic_wr_en_c4 (dirrep_ic_wr_en_c4),
5723 .dirrep_inval_mask_icd_c4(dirrep_inval_mask_icd_c4[7:0]),
5724 .dirrep_ic_rdwr_row_en_c4(dirrep_ic_rdwr_row_en_c4[3:0]),
5725 .dirrep_ic_rdwr_panel_dec_c4(dirrep_ic_rdwr_panel_dec_c4[3:0]),
5726 .dirrep_ic_lkup_row_dec_c4(dirrep_ic_lkup_row_dec_c4[3:0]),
5727 .dirrep_ic_lkup_panel_dec_c4(dirrep_ic_lkup_panel_dec_c4[3:0]),
5728 .dirrep_wr_ic_dir_entry_c4(dirrep_wr_ic_dir_entry_c4[4:0]),// BS and SR 11/18/03 Reverse Directory change
5729 .dirrep_ic_dir_clear_c4 (dirrep_ic_dir_clear_c4),
5730 .dirrep_dir_error_c8 (dirrep_dir_error_c8),
5731 .arbadr_arbdp_addr4_c4 (arbadr_arbdp_addr4_c4),
5732 .arbadr_arbdp_dc_addr4_c4 (arbadr_arbdp_dc_addr4_c4),
5733 .arbadr_arbdp_ic_addr4_c4 (arbadr_arbdp_ic_addr4_c4),
5734 .arbadr_arbdp_index_ic_addr4_c4(arbadr_arbdp_index_ic_addr4_c4),
5735 .arbadr_arbdp_index_dc_addr4_c4(arbadr_arbdp_index_dc_addr4_c4),
5736 // Inputs
5737 .arb_ic_inval_vld_c7 (ic_inval_vld_c7),
5738 .ic_parity_out (ic_parity_out[3:0]),
5739 .dc_parity_out (dc_parity_out[3:0]),
5740 .arb_dc_ic_rd_bit_4(arb_dc_ic_rd_bit_4),
5741 .arb_inval_inst_vld_c3 (arb_inval_inst_vld_c3),
5742 .arbadr_arbdp_dir_wr_par_c3(csr_wr_dirpinj_en),
5743 .arbadr_arbdp_addr5to4_c3(arbadr_arbdp_addr5to4_c3[1:0]),
5744 .arb_dir_vld_c3_l(arb_dir_vld_c3_l),
5745 .arb_ic_rd_en_c3(arb_ic_rd_en_c3),
5746 .arb_dc_rd_en_c3(arb_dc_rd_en_c3),
5747 .arb_ic_wr_en_c3(arb_ic_wr_en_c3),
5748 .arb_dc_wr_en_c3(arb_dc_wr_en_c3),
5749 .arb_dir_panel_dcd_c3(arb_dir_panel_dcd_c3[4:0]),
5750 .arb_dir_panel_icd_c3(arb_dir_panel_icd_c3[4:0]),
5751 .arb_lkup_bank_ena_dcd_c3(arb_lkup_bank_ena_dcd_c3[3:0]),
5752 .arb_lkup_bank_ena_icd_c3(arb_lkup_bank_ena_icd_c3[3:0]),
5753 .arb_inval_mask_dcd_c3(arb_inval_mask_dcd_c3[7:0]),
5754 .arb_inval_mask_icd_c3(arb_inval_mask_icd_c3[7:0]),
5755 .arb_wr_dc_dir_entry_c3(arb_wr_dc_dir_entry_c3[4:0]),
5756 .arb_wr_ic_dir_entry_c3(arb_wr_ic_dir_entry_c3[4:0]),
5757 .tagd_lkup_row_addr_dcd_c3(lkup_row_addr_dcd_c3[2:0]),
5758 .tagd_lkup_row_addr_icd_c3(lkup_row_addr_icd_c3[2:0]),
5759 .csr_oneshot_dir_clear_c3(csr_oneshot_dir_clear_c3),
5760 .scan_in(dirrep_scanin),
5761 .scan_out(dirrep_scanout),
5762 .l2clk (l2clk),
5763 .por_l(por_l),
5764 .l2t_mb0_run(l2t_mb0_run));
5765
5766
5767///////////////////////////
5768// VUAD array coded here
5769///////////////////////////
5770
5771
5772
5773// ROW 0
5774
5775n2_l2t_dp_32x160_cust subarray_0(
5776 // Outputs
5777 .dout ({subarray_0_unused[3:0],data_in_h_r0[155:0]}),
5778 // Inputs
5779 .tcu_pce_ov(ce_ovrd),
5780 .pce(1'b1),
5781 .tcu_aclk(aclk),
5782 .tcu_bclk(bclk),
5783 .tcu_scan_en(tcu_scan_en),
5784 .din ( {
5785 1'b0, 1'b0, 1'b0, 1'b0,
5786 write_data[77], write_data[77], write_data[77], write_data[77],
5787 write_data[76], write_data[76], write_data[76], write_data[76],
5788 write_data[75], write_data[75], write_data[75], write_data[75],
5789 write_data[74], write_data[74], write_data[74], write_data[74],
5790 write_data[73], write_data[73], write_data[73], write_data[73],
5791 write_data[72], write_data[72], write_data[72], write_data[72],
5792 write_data[71], write_data[71], write_data[71], write_data[71],
5793 write_data[70], write_data[70], write_data[70], write_data[70],
5794 write_data[69], write_data[69], write_data[69], write_data[69],
5795 write_data[68], write_data[68], write_data[68], write_data[68],
5796 write_data[67], write_data[67], write_data[67], write_data[67],
5797 write_data[66], write_data[66], write_data[66], write_data[66],
5798 write_data[65], write_data[65], write_data[65], write_data[65],
5799 write_data[64], write_data[64], write_data[64], write_data[64],
5800 write_data[63], write_data[63], write_data[63], write_data[63],
5801 write_data[62], write_data[62], write_data[62], write_data[62],
5802 write_data[61], write_data[61], write_data[61], write_data[61],
5803 write_data[60], write_data[60], write_data[60], write_data[60],
5804 write_data[59], write_data[59], write_data[59], write_data[59],
5805 write_data[58], write_data[58], write_data[58], write_data[58],
5806 write_data[57], write_data[57], write_data[57], write_data[57],
5807 write_data[56], write_data[56], write_data[56], write_data[56],
5808 write_data[55], write_data[55], write_data[55], write_data[55],
5809 write_data[54], write_data[54], write_data[54], write_data[54],
5810 write_data[53], write_data[53], write_data[53], write_data[53],
5811 write_data[52], write_data[52], write_data[52], write_data[52],
5812 write_data[51], write_data[51], write_data[51], write_data[51],
5813 write_data[50], write_data[50], write_data[50], write_data[50],
5814 write_data[49], write_data[49], write_data[49], write_data[49],
5815 write_data[48], write_data[48], write_data[48], write_data[48],
5816 write_data[47], write_data[47], write_data[47], write_data[47],
5817 write_data[46], write_data[46], write_data[46], write_data[46],
5818 write_data[45], write_data[45], write_data[45], write_data[45],
5819 write_data[44], write_data[44], write_data[44], write_data[44],
5820 write_data[43], write_data[43], write_data[43], write_data[43],
5821 write_data[42], write_data[42], write_data[42], write_data[42],
5822 write_data[41], write_data[41], write_data[41], write_data[41],
5823 write_data[40], write_data[40], write_data[40], write_data[40],
5824 write_data[39], write_data[39], write_data[39], write_data[39] }),
5825 .rd_adr1 (vuad_rd_addr1_r0[4:0]), // Templated
5826 .rd_adr2 (vuad_rd_addr2_r0[4:0]), // Templated
5827 .sel_rdaddr1(vuad_rd_addr_sel_r0), // Templated
5828 .wr_adr (vuad_wr_addr_r0[4:0]), // Templated
5829 .read_en (vuad_rd_en_r0), // Templated
5830 .wr_en (vuad_wr_en_r0c0), // Templated
5831 .word_wen (vuad_word_en_r0[3:0]), // Templated
5832 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
5833 .scan_in(subarray_0_scanin),
5834 .scan_out(subarray_0_scanout),
5835 .l2clk (l2clk), // Templated
5836 .tcu_se_scancollar_in (tcu_se_scancollar_in)); // Templated
5837
5838l2t_vuadcl_dp vuadcl_0(
5839 // Outputs
5840 .vuadcl_data_out_col(data_out_col_r0[38:0]), // Templated
5841 // Inputs
5842 .tcu_muxtest(tcu_muxtest),
5843 .data_in_l(data_in_h_r1[155:0]), // Templated
5844 .data_in_h(data_in_h_r0[155:0]), // Templated
5845 .mux1_h_sel(mux1_h_sel_r0[3:0]), // Templated
5846 .mux1_l_sel(mux1_l_sel_r0[3:0]), // Templated
5847 .mux2_sel (vuad_mux2_sel_r0)); // Templated
5848
5849n2_l2t_dp_32x160_cust subarray_1(
5850 // Outputs
5851 .dout ({subarray_1_unused[3:0],data_in_h_r1[155:0]}), // Templated
5852 // Inputs
5853 .tcu_pce_ov(ce_ovrd),
5854 .pce(1'b1),
5855 .tcu_aclk(aclk),
5856 .tcu_bclk(bclk),
5857 .tcu_scan_en(tcu_scan_en),
5858
5859 .din ( {
5860 1'b0, 1'b0, 1'b0, 1'b0,
5861 write_data[77], write_data[77], write_data[77], write_data[77],
5862 write_data[76], write_data[76], write_data[76], write_data[76],
5863 write_data[75], write_data[75], write_data[75], write_data[75],
5864 write_data[74], write_data[74], write_data[74], write_data[74],
5865 write_data[73], write_data[73], write_data[73], write_data[73],
5866 write_data[72], write_data[72], write_data[72], write_data[72],
5867 write_data[71], write_data[71], write_data[71], write_data[71],
5868 write_data[70], write_data[70], write_data[70], write_data[70],
5869 write_data[69], write_data[69], write_data[69], write_data[69],
5870 write_data[68], write_data[68], write_data[68], write_data[68],
5871 write_data[67], write_data[67], write_data[67], write_data[67],
5872 write_data[66], write_data[66], write_data[66], write_data[66],
5873 write_data[65], write_data[65], write_data[65], write_data[65],
5874 write_data[64], write_data[64], write_data[64], write_data[64],
5875 write_data[63], write_data[63], write_data[63], write_data[63],
5876 write_data[62], write_data[62], write_data[62], write_data[62],
5877 write_data[61], write_data[61], write_data[61], write_data[61],
5878 write_data[60], write_data[60], write_data[60], write_data[60],
5879 write_data[59], write_data[59], write_data[59], write_data[59],
5880 write_data[58], write_data[58], write_data[58], write_data[58],
5881 write_data[57], write_data[57], write_data[57], write_data[57],
5882 write_data[56], write_data[56], write_data[56], write_data[56],
5883 write_data[55], write_data[55], write_data[55], write_data[55],
5884 write_data[54], write_data[54], write_data[54], write_data[54],
5885 write_data[53], write_data[53], write_data[53], write_data[53],
5886 write_data[52], write_data[52], write_data[52], write_data[52],
5887 write_data[51], write_data[51], write_data[51], write_data[51],
5888 write_data[50], write_data[50], write_data[50], write_data[50],
5889 write_data[49], write_data[49], write_data[49], write_data[49],
5890 write_data[48], write_data[48], write_data[48], write_data[48],
5891 write_data[47], write_data[47], write_data[47], write_data[47],
5892 write_data[46], write_data[46], write_data[46], write_data[46],
5893 write_data[45], write_data[45], write_data[45], write_data[45],
5894 write_data[44], write_data[44], write_data[44], write_data[44],
5895 write_data[43], write_data[43], write_data[43], write_data[43],
5896 write_data[42], write_data[42], write_data[42], write_data[42],
5897 write_data[41], write_data[41], write_data[41], write_data[41],
5898 write_data[40], write_data[40], write_data[40], write_data[40],
5899 write_data[39], write_data[39], write_data[39], write_data[39] }),
5900 .rd_adr1 (vuad_rd_addr1_r1[4:0]), // Templated
5901 .rd_adr2 (vuad_rd_addr2_r1[4:0]), // Templated
5902 .sel_rdaddr1(vuad_rd_addr_sel_r1), // Templated
5903 .wr_adr (vuad_wr_addr_r1[4:0]), // Templated
5904 .read_en (vuad_rd_en_r1), // Templated
5905 .wr_en (vuad_wr_en_r1c0), // Templated
5906 .word_wen (vuad_word_en_r1[3:0]), // Templated
5907 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
5908 .scan_in(subarray_1_scanin),
5909 .scan_out(subarray_1_scanout),
5910 .l2clk (l2clk), // Templated
5911 .tcu_se_scancollar_in (tcu_se_scancollar_in)); // Templated
5912
5913
5914
5915// ROW 2
5916
5917n2_l2t_dp_32x160_cust subarray_2(/*AUTOINST*/
5918 // Outputs
5919 .dout ({subarray_2_unused[3:0],data_in_h_r2[155:0]}), // Templated
5920 // Inputs
5921 .tcu_pce_ov(ce_ovrd),
5922 .pce(1'b1),
5923 .tcu_aclk(aclk),
5924 .tcu_bclk(bclk),
5925 .tcu_scan_en(tcu_scan_en),
5926 .din ( {
5927 1'b0, 1'b0, 1'b0, 1'b0,
5928 write_data[77], write_data[77], write_data[77], write_data[77],
5929 write_data[76], write_data[76], write_data[76], write_data[76],
5930 write_data[75], write_data[75], write_data[75], write_data[75],
5931 write_data[74], write_data[74], write_data[74], write_data[74],
5932 write_data[73], write_data[73], write_data[73], write_data[73],
5933 write_data[72], write_data[72], write_data[72], write_data[72],
5934 write_data[71], write_data[71], write_data[71], write_data[71],
5935 write_data[70], write_data[70], write_data[70], write_data[70],
5936 write_data[69], write_data[69], write_data[69], write_data[69],
5937 write_data[68], write_data[68], write_data[68], write_data[68],
5938 write_data[67], write_data[67], write_data[67], write_data[67],
5939 write_data[66], write_data[66], write_data[66], write_data[66],
5940 write_data[65], write_data[65], write_data[65], write_data[65],
5941 write_data[64], write_data[64], write_data[64], write_data[64],
5942 write_data[63], write_data[63], write_data[63], write_data[63],
5943 write_data[62], write_data[62], write_data[62], write_data[62],
5944 write_data[61], write_data[61], write_data[61], write_data[61],
5945 write_data[60], write_data[60], write_data[60], write_data[60],
5946 write_data[59], write_data[59], write_data[59], write_data[59],
5947 write_data[58], write_data[58], write_data[58], write_data[58],
5948 write_data[57], write_data[57], write_data[57], write_data[57],
5949 write_data[56], write_data[56], write_data[56], write_data[56],
5950 write_data[55], write_data[55], write_data[55], write_data[55],
5951 write_data[54], write_data[54], write_data[54], write_data[54],
5952 write_data[53], write_data[53], write_data[53], write_data[53],
5953 write_data[52], write_data[52], write_data[52], write_data[52],
5954 write_data[51], write_data[51], write_data[51], write_data[51],
5955 write_data[50], write_data[50], write_data[50], write_data[50],
5956 write_data[49], write_data[49], write_data[49], write_data[49],
5957 write_data[48], write_data[48], write_data[48], write_data[48],
5958 write_data[47], write_data[47], write_data[47], write_data[47],
5959 write_data[46], write_data[46], write_data[46], write_data[46],
5960 write_data[45], write_data[45], write_data[45], write_data[45],
5961 write_data[44], write_data[44], write_data[44], write_data[44],
5962 write_data[43], write_data[43], write_data[43], write_data[43],
5963 write_data[42], write_data[42], write_data[42], write_data[42],
5964 write_data[41], write_data[41], write_data[41], write_data[41],
5965 write_data[40], write_data[40], write_data[40], write_data[40],
5966 write_data[39], write_data[39], write_data[39], write_data[39] }),
5967 .rd_adr1 (vuad_rd_addr1_r2[4:0]), // Templated
5968 .rd_adr2 (vuad_rd_addr2_r2[4:0]), // Templated
5969 .sel_rdaddr1(vuad_rd_addr_sel_r2), // Templated
5970 .wr_adr (vuad_wr_addr_r2[4:0]), // Templated
5971 .read_en (vuad_rd_en_r2), // Templated
5972 .wr_en (vuad_wr_en_r2c0), // Templated
5973 .word_wen (vuad_word_en_r2[3:0]), // Templated
5974 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
5975 .scan_in(subarray_2_scanin),
5976 .scan_out(subarray_2_scanout),
5977 .l2clk (l2clk), // Templated
5978 .tcu_se_scancollar_in (tcu_se_scancollar_in)); // Templated
5979
5980
5981l2t_vuadcl_dp vuadcl_2(
5982 // Outputs
5983 .vuadcl_data_out_col(data_out_col_r2[38:0]), // Templated
5984 // Inputs
5985 .tcu_muxtest(tcu_muxtest),
5986 .data_in_l(data_in_h_r3[155:0]), // Templated
5987 .data_in_h(data_in_h_r2[155:0]), // Templated
5988 .mux1_h_sel(mux1_h_sel_r2[3:0]), // Templated
5989 .mux1_l_sel(mux1_l_sel_r2[3:0]), // Templated
5990 .mux2_sel (vuad_mux2_sel_r2)); // Templated
5991
5992
5993n2_l2t_dp_32x160_cust subarray_3(/*AUTOINST*/
5994 // Outputs
5995 .dout ({subarray_3_unused[3:0],data_in_h_r3[155:0]}), // Templated
5996 // Inputs
5997 .tcu_pce_ov(ce_ovrd),
5998 .pce(1'b1),
5999 .tcu_aclk(aclk),
6000 .tcu_bclk(bclk),
6001 .tcu_scan_en(tcu_scan_en),
6002 .din ( {
6003 1'b0, 1'b0, 1'b0, 1'b0,
6004 write_data[77], write_data[77], write_data[77], write_data[77],
6005 write_data[76], write_data[76], write_data[76], write_data[76],
6006 write_data[75], write_data[75], write_data[75], write_data[75],
6007 write_data[74], write_data[74], write_data[74], write_data[74],
6008 write_data[73], write_data[73], write_data[73], write_data[73],
6009 write_data[72], write_data[72], write_data[72], write_data[72],
6010 write_data[71], write_data[71], write_data[71], write_data[71],
6011 write_data[70], write_data[70], write_data[70], write_data[70],
6012 write_data[69], write_data[69], write_data[69], write_data[69],
6013 write_data[68], write_data[68], write_data[68], write_data[68],
6014 write_data[67], write_data[67], write_data[67], write_data[67],
6015 write_data[66], write_data[66], write_data[66], write_data[66],
6016 write_data[65], write_data[65], write_data[65], write_data[65],
6017 write_data[64], write_data[64], write_data[64], write_data[64],
6018 write_data[63], write_data[63], write_data[63], write_data[63],
6019 write_data[62], write_data[62], write_data[62], write_data[62],
6020 write_data[61], write_data[61], write_data[61], write_data[61],
6021 write_data[60], write_data[60], write_data[60], write_data[60],
6022 write_data[59], write_data[59], write_data[59], write_data[59],
6023 write_data[58], write_data[58], write_data[58], write_data[58],
6024 write_data[57], write_data[57], write_data[57], write_data[57],
6025 write_data[56], write_data[56], write_data[56], write_data[56],
6026 write_data[55], write_data[55], write_data[55], write_data[55],
6027 write_data[54], write_data[54], write_data[54], write_data[54],
6028 write_data[53], write_data[53], write_data[53], write_data[53],
6029 write_data[52], write_data[52], write_data[52], write_data[52],
6030 write_data[51], write_data[51], write_data[51], write_data[51],
6031 write_data[50], write_data[50], write_data[50], write_data[50],
6032 write_data[49], write_data[49], write_data[49], write_data[49],
6033 write_data[48], write_data[48], write_data[48], write_data[48],
6034 write_data[47], write_data[47], write_data[47], write_data[47],
6035 write_data[46], write_data[46], write_data[46], write_data[46],
6036 write_data[45], write_data[45], write_data[45], write_data[45],
6037 write_data[44], write_data[44], write_data[44], write_data[44],
6038 write_data[43], write_data[43], write_data[43], write_data[43],
6039 write_data[42], write_data[42], write_data[42], write_data[42],
6040 write_data[41], write_data[41], write_data[41], write_data[41],
6041 write_data[40], write_data[40], write_data[40], write_data[40],
6042 write_data[39], write_data[39], write_data[39], write_data[39] }),
6043 .rd_adr1 (vuad_rd_addr1_r3[4:0]), // Templated
6044 .rd_adr2 (vuad_rd_addr2_r3[4:0]), // Templated
6045 .sel_rdaddr1(vuad_rd_addr_sel_r3), // Templated
6046 .wr_adr (vuad_wr_addr_r3[4:0]), // Templated
6047 .read_en (vuad_rd_en_r3), // Templated
6048 .wr_en (vuad_wr_en_r3c0), // Templated
6049 .word_wen (vuad_word_en_r3[3:0]), // Templated
6050 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
6051 .scan_in(subarray_3_scanin),
6052 .scan_out(subarray_3_scanout),
6053 .l2clk (l2clk), // Templated
6054 .tcu_se_scancollar_in (tcu_se_scancollar_in)); // Templated
6055
6056l2t_vuadio_dp io_left(
6057 // Outputs
6058 .vuadio_array_data_in_buf(write_data[77:39]),
6059 .vuadio_data_out_io (vuad_array_rd_data_c1[77:39]), // Templated
6060 // Inputs
6061 .data_out_col1(data_out_col_r0[38:0]), // Templated
6062 .data_out_col2(data_out_col_r2[38:0]), // Templated
6063 .array_data_in(vlddir_vuad_array_wr_data_c4[77:39]), // Templated
6064 .vuad_mux_sel (vuad_mux_sel[1:0]));
6065
6066// ROW 0 col1
6067
6068n2_l2t_dp_32x160_cust subarray_8(/*AUTOINST*/
6069 // Outputs
6070 .dout({subarray_8_unused[3:0],data_in_h_r8[155:0]}), // Templated
6071 // Inputs
6072 .tcu_pce_ov(ce_ovrd),
6073 .pce(1'b1),
6074 .tcu_aclk(aclk),
6075 .tcu_bclk(bclk),
6076 .tcu_scan_en(tcu_scan_en),
6077 .din ( {
6078 1'b0, 1'b0, 1'b0, 1'b0,
6079 write_data[38], write_data[38], write_data[38], write_data[38],
6080 write_data[37], write_data[37], write_data[37], write_data[37],
6081 write_data[36], write_data[36], write_data[36], write_data[36],
6082 write_data[35], write_data[35], write_data[35], write_data[35],
6083 write_data[34], write_data[34], write_data[34], write_data[34],
6084 write_data[33], write_data[33], write_data[33], write_data[33],
6085 write_data[32], write_data[32],write_data[32], write_data[32],
6086 write_data[31], write_data[31],write_data[31], write_data[31],
6087 write_data[30], write_data[30],write_data[30], write_data[30],
6088 write_data[29], write_data[29],write_data[29], write_data[29],
6089 write_data[28], write_data[28],write_data[28], write_data[28],
6090 write_data[27], write_data[27],write_data[27], write_data[27],
6091 write_data[26], write_data[26],write_data[26], write_data[26],
6092 write_data[25], write_data[25],write_data[25], write_data[25],
6093 write_data[24], write_data[24],write_data[24], write_data[24],
6094 write_data[23], write_data[23],write_data[23], write_data[23],
6095 write_data[22], write_data[22],write_data[22], write_data[22],
6096 write_data[21], write_data[21],write_data[21], write_data[21],
6097 write_data[20], write_data[20],write_data[20], write_data[20],
6098 write_data[19], write_data[19],write_data[19], write_data[19],
6099 write_data[18], write_data[18],write_data[18], write_data[18],
6100 write_data[17], write_data[17],write_data[17], write_data[17],
6101 write_data[16], write_data[16],write_data[16], write_data[16],
6102 write_data[15], write_data[15],write_data[15], write_data[15],
6103 write_data[14], write_data[14],write_data[14], write_data[14],
6104 write_data[13], write_data[13],write_data[13], write_data[13],
6105 write_data[12], write_data[12],write_data[12], write_data[12],
6106 write_data[11], write_data[11],write_data[11], write_data[11],
6107 write_data[10], write_data[10],write_data[10], write_data[10],
6108 write_data[9], write_data[9], write_data[9], write_data[9],
6109 write_data[8], write_data[8], write_data[8], write_data[8],
6110 write_data[7], write_data[7], write_data[7], write_data[7],
6111 write_data[6], write_data[6], write_data[6], write_data[6],
6112 write_data[5], write_data[5], write_data[5], write_data[5],
6113 write_data[4], write_data[4], write_data[4], write_data[4],
6114 write_data[3], write_data[3], write_data[3], write_data[3],
6115 write_data[2], write_data[2], write_data[2], write_data[2],
6116 write_data[1], write_data[1], write_data[1], write_data[1],
6117 write_data[0], write_data[0], write_data[0], write_data[0]}),
6118 .rd_adr1(vuad_rd_addr1_r0[4:0]), // Templated
6119 .rd_adr2(vuad_rd_addr2_r0[4:0]), // Templated
6120 .sel_rdaddr1(vuad_rd_addr_sel_r0), // Templated
6121 .wr_adr(vuad_wr_addr_r0[4:0]), // Templated
6122 .read_en(vuad_rd_en_r0), // Templated
6123 .wr_en(vuad_wr_en_r0c1), // Templated
6124 .word_wen(vuad_word_en_r0[3:0]), // Templated
6125 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
6126 .scan_in(subarray_8_scanin),
6127 .scan_out(subarray_8_scanout),
6128 .l2clk(l2clk), // Templated
6129 .tcu_se_scancollar_in(tcu_se_scancollar_in)); // Templated
6130
6131l2t_vuadcl_dp vuadcl_8(/*AUTOINST*/
6132 // Outputs
6133 .vuadcl_data_out_col(data_out_col_r8[38:0]), // Templated
6134 // Inputs
6135 .tcu_muxtest(tcu_muxtest),
6136 .data_in_l(data_in_h_r9[155:0]), // Templated
6137 .data_in_h(data_in_h_r8[155:0]), // Templated
6138 .mux1_h_sel(mux1_h_sel_r0[3:0]), // Templated
6139 .mux1_l_sel(mux1_l_sel_r0[3:0]), // Templated
6140 .mux2_sel(vuad_mux2_sel_r0)); // Templated
6141
6142
6143n2_l2t_dp_32x160_cust subarray_9(/*AUTOINST*/
6144 // Outputs
6145 .dout({subarray_9_unused[3:0],data_in_h_r9[155:0]}), // Templated
6146 // Inputs
6147 .tcu_pce_ov(ce_ovrd),
6148 .pce(1'b1),
6149 .tcu_aclk(aclk),
6150 .tcu_bclk(bclk),
6151 .tcu_scan_en(tcu_scan_en),
6152 .din ( {
6153 1'b0, 1'b0, 1'b0, 1'b0,
6154 write_data[38], write_data[38], write_data[38], write_data[38],
6155 write_data[37], write_data[37], write_data[37], write_data[37],
6156 write_data[36], write_data[36], write_data[36], write_data[36],
6157 write_data[35], write_data[35], write_data[35], write_data[35],
6158 write_data[34], write_data[34], write_data[34], write_data[34],
6159 write_data[33], write_data[33], write_data[33], write_data[33],
6160 write_data[32], write_data[32],write_data[32], write_data[32],
6161 write_data[31], write_data[31],write_data[31], write_data[31],
6162 write_data[30], write_data[30],write_data[30], write_data[30],
6163 write_data[29], write_data[29],write_data[29], write_data[29],
6164 write_data[28], write_data[28],write_data[28], write_data[28],
6165 write_data[27], write_data[27],write_data[27], write_data[27],
6166 write_data[26], write_data[26],write_data[26], write_data[26],
6167 write_data[25], write_data[25],write_data[25], write_data[25],
6168 write_data[24], write_data[24],write_data[24], write_data[24],
6169 write_data[23], write_data[23],write_data[23], write_data[23],
6170 write_data[22], write_data[22],write_data[22], write_data[22],
6171 write_data[21], write_data[21],write_data[21], write_data[21],
6172 write_data[20], write_data[20],write_data[20], write_data[20],
6173 write_data[19], write_data[19],write_data[19], write_data[19],
6174 write_data[18], write_data[18],write_data[18], write_data[18],
6175 write_data[17], write_data[17],write_data[17], write_data[17],
6176 write_data[16], write_data[16],write_data[16], write_data[16],
6177 write_data[15], write_data[15],write_data[15], write_data[15],
6178 write_data[14], write_data[14],write_data[14], write_data[14],
6179 write_data[13], write_data[13],write_data[13], write_data[13],
6180 write_data[12], write_data[12],write_data[12], write_data[12],
6181 write_data[11], write_data[11],write_data[11], write_data[11],
6182 write_data[10], write_data[10],write_data[10], write_data[10],
6183 write_data[9], write_data[9], write_data[9], write_data[9],
6184 write_data[8], write_data[8], write_data[8], write_data[8],
6185 write_data[7], write_data[7], write_data[7], write_data[7],
6186 write_data[6], write_data[6], write_data[6], write_data[6],
6187 write_data[5], write_data[5], write_data[5], write_data[5],
6188 write_data[4], write_data[4], write_data[4], write_data[4],
6189 write_data[3], write_data[3], write_data[3], write_data[3],
6190 write_data[2], write_data[2], write_data[2], write_data[2],
6191 write_data[1], write_data[1], write_data[1], write_data[1],
6192 write_data[0], write_data[0], write_data[0], write_data[0]}),
6193 .rd_adr1(vuad_rd_addr1_r1[4:0]), // Templated
6194 .rd_adr2(vuad_rd_addr2_r1[4:0]), // Templated
6195 .sel_rdaddr1(vuad_rd_addr_sel_r1), // Templated
6196 .wr_adr(vuad_wr_addr_r1[4:0]), // Templated
6197 .read_en(vuad_rd_en_r1), // Templated
6198 .wr_en(vuad_wr_en_r1c1), // Templated
6199 .word_wen(vuad_word_en_r1[3:0]), // Templated
6200 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
6201 .scan_in(subarray_9_scanin),
6202 .scan_out(subarray_9_scanout),
6203 .l2clk(l2clk), // Templated
6204 .tcu_se_scancollar_in(tcu_se_scancollar_in)); // Templated
6205
6206
6207// ROW 2 col1
6208
6209n2_l2t_dp_32x160_cust subarray_10(/*AUTOINST*/
6210 // Outputs
6211 .dout({subarray_10_unused[3:0],data_in_h_r10[155:0]}), // Templated
6212 // Inputs
6213 .tcu_pce_ov(ce_ovrd),
6214 .pce(1'b1),
6215 .tcu_aclk(aclk),
6216 .tcu_bclk(bclk),
6217 .tcu_scan_en(tcu_scan_en),
6218 .din ( {
6219 1'b0, 1'b0, 1'b0, 1'b0,
6220 write_data[38], write_data[38], write_data[38], write_data[38],
6221 write_data[37], write_data[37], write_data[37], write_data[37],
6222 write_data[36], write_data[36], write_data[36], write_data[36],
6223 write_data[35], write_data[35], write_data[35], write_data[35],
6224 write_data[34], write_data[34], write_data[34], write_data[34],
6225 write_data[33], write_data[33], write_data[33], write_data[33],
6226 write_data[32], write_data[32],write_data[32], write_data[32],
6227 write_data[31], write_data[31],write_data[31], write_data[31],
6228 write_data[30], write_data[30],write_data[30], write_data[30],
6229 write_data[29], write_data[29],write_data[29], write_data[29],
6230 write_data[28], write_data[28],write_data[28], write_data[28],
6231 write_data[27], write_data[27],write_data[27], write_data[27],
6232 write_data[26], write_data[26],write_data[26], write_data[26],
6233 write_data[25], write_data[25],write_data[25], write_data[25],
6234 write_data[24], write_data[24],write_data[24], write_data[24],
6235 write_data[23], write_data[23],write_data[23], write_data[23],
6236 write_data[22], write_data[22],write_data[22], write_data[22],
6237 write_data[21], write_data[21],write_data[21], write_data[21],
6238 write_data[20], write_data[20],write_data[20], write_data[20],
6239 write_data[19], write_data[19],write_data[19], write_data[19],
6240 write_data[18], write_data[18],write_data[18], write_data[18],
6241 write_data[17], write_data[17],write_data[17], write_data[17],
6242 write_data[16], write_data[16],write_data[16], write_data[16],
6243 write_data[15], write_data[15],write_data[15], write_data[15],
6244 write_data[14], write_data[14],write_data[14], write_data[14],
6245 write_data[13], write_data[13],write_data[13], write_data[13],
6246 write_data[12], write_data[12],write_data[12], write_data[12],
6247 write_data[11], write_data[11],write_data[11], write_data[11],
6248 write_data[10], write_data[10],write_data[10], write_data[10],
6249 write_data[9], write_data[9], write_data[9], write_data[9],
6250 write_data[8], write_data[8], write_data[8], write_data[8],
6251 write_data[7], write_data[7], write_data[7], write_data[7],
6252 write_data[6], write_data[6], write_data[6], write_data[6],
6253 write_data[5], write_data[5], write_data[5], write_data[5],
6254 write_data[4], write_data[4], write_data[4], write_data[4],
6255 write_data[3], write_data[3], write_data[3], write_data[3],
6256 write_data[2], write_data[2], write_data[2], write_data[2],
6257 write_data[1], write_data[1], write_data[1], write_data[1],
6258 write_data[0], write_data[0], write_data[0], write_data[0]}),
6259 .rd_adr1(vuad_rd_addr1_r2[4:0]), // Templated
6260 .rd_adr2(vuad_rd_addr2_r2[4:0]), // Templated
6261 .sel_rdaddr1(vuad_rd_addr_sel_r2), // Templated
6262 .wr_adr(vuad_wr_addr_r2[4:0]), // Templated
6263 .read_en(vuad_rd_en_r2), // Templated
6264 .wr_en(vuad_wr_en_r2c1), // Templated
6265 .word_wen(vuad_word_en_r2[3:0]), // Templated
6266 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
6267 .scan_in(subarray_10_scanin),
6268 .scan_out(subarray_10_scanout),
6269 .l2clk(l2clk), // Templated
6270 .tcu_se_scancollar_in(tcu_se_scancollar_in)); // Templated
6271l2t_vuadcl_dp vuadcl_10(/*AUTOINST*/
6272 // Outputs
6273 .vuadcl_data_out_col(data_out_col_r10[38:0]), // Templated
6274 // Inputs
6275 .tcu_muxtest(tcu_muxtest),
6276 .data_in_l(data_in_h_r11[155:0]), // Templated
6277 .data_in_h(data_in_h_r10[155:0]), // Templated
6278 .mux1_h_sel(mux1_h_sel_r2[3:0]), // Templated
6279 .mux1_l_sel(mux1_l_sel_r2[3:0]), // Templated
6280 .mux2_sel(vuad_mux2_sel_r2)); // Templated
6281
6282
6283n2_l2t_dp_32x160_cust subarray_11(/*AUTOINST*/
6284 // Outputs
6285 .dout({subarray_11_unused[3:0],data_in_h_r11[155:0]}), // Templated
6286 // Inputs
6287 .tcu_pce_ov(ce_ovrd),
6288 .pce(1'b1),
6289 .tcu_aclk(aclk),
6290 .tcu_bclk(bclk),
6291 .tcu_scan_en(tcu_scan_en),
6292 .din ( {
6293 1'b0, 1'b0, 1'b0, 1'b0,
6294 write_data[38], write_data[38], write_data[38], write_data[38],
6295 write_data[37], write_data[37], write_data[37], write_data[37],
6296 write_data[36], write_data[36], write_data[36], write_data[36],
6297 write_data[35], write_data[35], write_data[35], write_data[35],
6298 write_data[34], write_data[34], write_data[34], write_data[34],
6299 write_data[33], write_data[33], write_data[33], write_data[33],
6300 write_data[32], write_data[32],write_data[32], write_data[32],
6301 write_data[31], write_data[31],write_data[31], write_data[31],
6302 write_data[30], write_data[30],write_data[30], write_data[30],
6303 write_data[29], write_data[29],write_data[29], write_data[29],
6304 write_data[28], write_data[28],write_data[28], write_data[28],
6305 write_data[27], write_data[27],write_data[27], write_data[27],
6306 write_data[26], write_data[26],write_data[26], write_data[26],
6307 write_data[25], write_data[25],write_data[25], write_data[25],
6308 write_data[24], write_data[24],write_data[24], write_data[24],
6309 write_data[23], write_data[23],write_data[23], write_data[23],
6310 write_data[22], write_data[22],write_data[22], write_data[22],
6311 write_data[21], write_data[21],write_data[21], write_data[21],
6312 write_data[20], write_data[20],write_data[20], write_data[20],
6313 write_data[19], write_data[19],write_data[19], write_data[19],
6314 write_data[18], write_data[18],write_data[18], write_data[18],
6315 write_data[17], write_data[17],write_data[17], write_data[17],
6316 write_data[16], write_data[16],write_data[16], write_data[16],
6317 write_data[15], write_data[15],write_data[15], write_data[15],
6318 write_data[14], write_data[14],write_data[14], write_data[14],
6319 write_data[13], write_data[13],write_data[13], write_data[13],
6320 write_data[12], write_data[12],write_data[12], write_data[12],
6321 write_data[11], write_data[11],write_data[11], write_data[11],
6322 write_data[10], write_data[10],write_data[10], write_data[10],
6323 write_data[9], write_data[9], write_data[9], write_data[9],
6324 write_data[8], write_data[8], write_data[8], write_data[8],
6325 write_data[7], write_data[7], write_data[7], write_data[7],
6326 write_data[6], write_data[6], write_data[6], write_data[6],
6327 write_data[5], write_data[5], write_data[5], write_data[5],
6328 write_data[4], write_data[4], write_data[4], write_data[4],
6329 write_data[3], write_data[3], write_data[3], write_data[3],
6330 write_data[2], write_data[2], write_data[2], write_data[2],
6331 write_data[1], write_data[1], write_data[1], write_data[1],
6332 write_data[0], write_data[0], write_data[0], write_data[0]}),
6333 .rd_adr1(vuad_rd_addr1_r3[4:0]), // Templated
6334 .rd_adr2(vuad_rd_addr2_r3[4:0]), // Templated
6335 .sel_rdaddr1(vuad_rd_addr_sel_r3), // Templated
6336 .wr_adr(vuad_wr_addr_r3[4:0]), // Templated
6337 .read_en(vuad_rd_en_r3), // Templated
6338 .wr_en(vuad_wr_en_r3c1), // Templated
6339 .word_wen(vuad_word_en_r3[3:0]), // Templated
6340 .tcu_array_wr_inhibit(array_wr_inhibit), // Templated
6341 .scan_in(subarray_11_scanin),
6342 .scan_out(subarray_11_scanout),
6343 .l2clk(l2clk), // Templated
6344 .tcu_se_scancollar_in(tcu_se_scancollar_in)); // Templated
6345
6346l2t_vuadio_dp io_right(
6347 // Outputs
6348 .vuadio_array_data_in_buf(write_data[38:0]),
6349 .vuadio_data_out_io (vuad_array_rd_data_c1[38:0]), // Templated
6350 // Inputs
6351 .data_out_col1(data_out_col_r8[38:0]), // Templated
6352 .data_out_col2(data_out_col_r10[38:0]), // Templated
6353 .array_data_in(vlddir_vuad_array_wr_data_c4[38:0]), // Templated
6354 .vuad_mux_sel (vuad_mux_sel[1:0]));
6355//l2t_vuad_dp vuad(
6356// .tcu_pce_ov(ce_ovrd),
6357// .tcu_aclk(aclk),
6358// .tcu_bclk(bclk),
6359// .tcu_scan_en(tcu_scan_en),
6360// .tcu_clk_stop(clk_stop),
6361// /*AUTOINST*/
6362// // Outputs
6363// .vuad_rd_addr1_r0(vuad_rd_addr1_r0[4:0]),
6364// .vuad_rd_addr2_r0(vuad_rd_addr2_r0[4:0]),
6365// .vuad_rd_addr_sel_r0(vuad_rd_addr_sel_r0),
6366// .vuad_wr_addr_r0(vuad_wr_addr_r0[4:0]),
6367// .vuad_word_en_r0(vuad_word_en_r0[3:0]),
6368// .vuad_wr_en_r0c0(vuad_wr_en_r0c0),
6369// .vuad_wr_en_r0c1(vuad_wr_en_r0c1),
6370// .vuad_mux1_h_sel_r0(mux1_h_sel_r0[3:0]),
6371// .vuad_mux1_l_sel_r0(mux1_l_sel_r0[3:0]),
6372// .vuad_mux2_sel_r0(vuad_mux2_sel_r0),
6373// .vuad_rd_en_r0 (vuad_rd_en_r0),
6374// .vuad_rd_addr1_r1(vuad_rd_addr1_r1[4:0]),
6375// .vuad_rd_addr2_r1(vuad_rd_addr2_r1[4:0]),
6376// .vuad_rd_addr_sel_r1(vuad_rd_addr_sel_r1),
6377// .vuad_wr_addr_r1(vuad_wr_addr_r1[4:0]),
6378// .vuad_word_en_r1(vuad_word_en_r1[3:0]),
6379// .vuad_wr_en_r1c0(vuad_wr_en_r1c0),
6380// .vuad_wr_en_r1c1(vuad_wr_en_r1c1),
6381// .vuad_rd_en_r1 (vuad_rd_en_r1),
6382// .vuad_rd_addr1_r2(vuad_rd_addr1_r2[4:0]),
6383// .vuad_rd_addr2_r2(vuad_rd_addr2_r2[4:0]),
6384// .vuad_rd_addr_sel_r2(vuad_rd_addr_sel_r2),
6385// .vuad_wr_addr_r2(vuad_wr_addr_r2[4:0]),
6386// .vuad_word_en_r2(vuad_word_en_r2[3:0]),
6387// .vuad_wr_en_r2c0(vuad_wr_en_r2c0),
6388// .vuad_wr_en_r2c1(vuad_wr_en_r2c1),
6389// .vuad_mux1_h_sel_r2(mux1_h_sel_r2[3:0]),
6390// .vuad_mux1_l_sel_r2(mux1_l_sel_r2[3:0]),
6391// .vuad_mux2_sel_r2(vuad_mux2_sel_r2),
6392// .vuad_rd_en_r2 (vuad_rd_en_r2),
6393// .vuad_rd_addr1_r3(vuad_rd_addr1_r3[4:0]),
6394// .vuad_rd_addr2_r3(vuad_rd_addr2_r3[4:0]),
6395// .vuad_rd_addr_sel_r3(vuad_rd_addr_sel_r3),
6396// .vuad_wr_addr_r3(vuad_wr_addr_r3[4:0]),
6397// .vuad_word_en_r3(vuad_word_en_r3[3:0]),
6398// .vuad_wr_en_r3c0(vuad_wr_en_r3c0),
6399// .vuad_wr_en_r3c1(vuad_wr_en_r3c1),
6400// .vuad_rd_en_r3 (vuad_rd_en_r3),
6401// .vuad_mux_sel (vuad_mux_sel[1:0]),
6402// // Inputs
6403// .rd_addr1 (arbadr_arbdp_vuad_idx1_px2[8:0]), // Templated
6404// .rd_addr2 (arbadr_arbdp_vuad_idx2_px2[8:0]), // Templated
6405// .rd_addr_sel(arb_vuad_idx2_sel_px2_n), // Templated
6406// .wr_addr (vuaddp_vuad_idx_c4[8:0]), // Templated
6407// .wr_en0 (vuaddp_vuad_array_wr_en0_c4), // Templated
6408// .wr_en1 (vuaddp_vuad_array_wr_en1_c4), // Templated
6409// .array_rd_en(arb_vuad_acc_px2), // Templated
6410// .scan_in(vuad_scanin),
6411// .scan_out(vuad_scanout),
6412// .l2clk (l2clk));
6413
6414////////////////////////////////////////
6415// DIRECTORY
6416////////////////////////////////////////
6417
6418n2_com_cm_64x64_cust ic_row0 (
6419 .scan_in(ic_row0_scanin),
6420 .scan_out(ic_row0_scanout),
6421 .l2clk (l2clk),
6422 // Outputs
6423 .row_hit (ic_cam_hit[63:0]),
6424 .rd_data0 (ic_rd_data04_row0[15:0]), // BS and SR 11/18/03 Reverse Directory change
6425 .rd_data1 (ic_rd_data15_row0[15:0]), // BS and SR 11/18/03 Reverse Directory change
6426 .rd_data2 (ic_rd_data26_row0[15:0]), // BS and SR 11/18/03 Reverse Directory change
6427 .rd_data3 (ic_rd_data37_row0[15:0]), // BS and SR 11/18/03 Reverse Directory change
6428 // Inputs
6429 .tcu_pce_ov (ce_ovrd),
6430 .pce (1'b1),
6431 .tcu_aclk (aclk),
6432 .tcu_bclk (bclk),
6433 .tcu_scan_en (tcu_scan_en),
6434 .tcu_array_bypass (tcu_array_bypass),
6435 .force_hit ({4{ic_force_hit_row0_c4}}),
6436 .cam_en (ic_cam_en_row0[3:0]), // Templated
6437 .inv_mask0 (ic_inv_mask_0145[7:0]), // Templated
6438 .inv_mask1 (ic_inv_mask_0145[7:0]), // Templated
6439 .inv_mask2 (ic_inv_mask_0145[7:0]), // Templated
6440 .inv_mask3 (ic_inv_mask_0145[7:0]), // Templated
6441 .tcu_se_scancollar_in (tcu_se_scancollar_in), // Templated
6442 .rd_en (ic_rd_en_row0[3:0]), // Templated
6443 .rw_addr0 (ic_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6444 .rw_addr1 (ic_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6445 .rw_addr2 (ic_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6446 .rw_addr3 (ic_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6447 .rst_warm_0 (ic_warm_rst_0145), // Templated
6448 .rst_warm_1 (ic_warm_rst_0145), // Templated
6449 .wr_en (ic_wr_en_row0[3:0]), // Templated
6450 .tcu_array_wr_inhibit (array_wr_inhibit), // Templated
6451 .wr_data0 (ic_lkup_wr_data_c4_row0[15:0]), // Templated
6452 .wr_data1 (ic_lkup_wr_data_c4_row0[15:0]), // Templated
6453 .wr_data2 (ic_lkup_wr_data_c4_row0[15:0]), // Templated
6454 .wr_data3 (ic_lkup_wr_data_c4_row0[15:0])); // Templated
6455
6456
6457l2t_dirout_dp out_col0 (
6458 // Inputs
6459 .tcu_pce_ov(ce_ovrd),
6460 .tcu_aclk(aclk),
6461 .tcu_bclk(bclk),
6462 .tcu_scan_en(tcu_scan_en),
6463 .tcu_clk_stop(1'b0),
6464 .scan_in(out_col0_scanin),
6465 .scan_out(out_col0_scanout),
6466 .l2clk (l2clk),
6467 // Outputs
6468 .dirout_parity_vld_out(out_col0_dirout_parity_vld_out_unused[2:0]),
6469 .dirout_parity_vld(ic_parity_in[0]),
6470 .mbist_read_data_pick_top (l2t_mb0_icrow_row_en[0]),
6471 .mbist_read_data_pick_bottom (l2t_mb0_icrow_row_en[1]),
6472 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6473 .l2t_mb0_run (l2t_mb0_run),
6474 .cam_read_fail (ic_cam_read_fail[0]),
6475 .mbist_dc_ic_read_en ({ic_rd_en_row0[0],ic_rd_en_row2[0]}),
6476 .rddata_out_c52_top(ic_rd_data04_row0[15:0]), // BS and SR 11/18/03 Reverse Directory change
6477 .rddata_out_c52_bottom(ic_rd_data8c_row1[15:0]), // BS and SR 11/18/03 Reverse Directory change
6478 .rd_data_sel_c52_top(ic_row0_select_panel0), //
6479 .rd_data_sel_c52_bottom(ic_row1_select_panel0), //
6480 .parity_vld_in(3'b0)); //
6481
6482
6483l2t_dirout_dp out_col1 (
6484 .tcu_pce_ov(ce_ovrd),
6485 .tcu_aclk(aclk),
6486 .tcu_bclk(bclk),
6487 .tcu_scan_en(tcu_scan_en),
6488 .tcu_clk_stop(1'b0),
6489 .scan_in(out_col1_scanin),
6490 .scan_out(out_col1_scanout),
6491 .l2clk (l2clk),
6492 .dirout_parity_vld_out(out_col1_dirout_parity_vld_out_unused[2:0]),
6493 .dirout_parity_vld(ic_parity_in[1]), //
6494 // Inputs
6495 .mbist_read_data_pick_top (l2t_mb0_icrow_row_en[0]),
6496 .mbist_read_data_pick_bottom (l2t_mb0_icrow_row_en[1]),
6497 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6498 .l2t_mb0_run (l2t_mb0_run),
6499 .cam_read_fail (ic_cam_read_fail[1]),
6500 .mbist_dc_ic_read_en ({ic_rd_en_row0[1],ic_rd_en_row2[1]}),
6501 .rddata_out_c52_top(ic_rd_data15_row0[15:0]), // ,BS and SR 11/18/03 Reverse Directory change
6502 .rddata_out_c52_bottom(ic_rd_data9d_row1[15:0]), // BS and SR 11/18/03 Reverse Directory change
6503 .rd_data_sel_c52_top(ic_row0_select_panel1), //
6504 .rd_data_sel_c52_bottom(ic_row1_select_panel1), //
6505 .parity_vld_in(3'b0)); //
6506
6507l2t_dirout_dp out_col2 (
6508 .tcu_pce_ov(ce_ovrd),
6509 .tcu_aclk(aclk),
6510 .tcu_bclk(bclk),
6511 .tcu_scan_en(tcu_scan_en),
6512 .tcu_clk_stop(1'b0),
6513 .scan_in(out_col2_scanin),
6514 .scan_out(out_col2_scanout),
6515 .l2clk (l2clk),
6516 // Outputs
6517 .dirout_parity_vld_out(out_col2_dirout_parity_vld_out_unused[2:0]),
6518 .dirout_parity_vld(ic_parity_in[2]), // Templated
6519 // Inputs
6520 .mbist_read_data_pick_top (l2t_mb0_icrow_row_en[0]),
6521 .mbist_read_data_pick_bottom (l2t_mb0_icrow_row_en[1]),
6522 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6523 .l2t_mb0_run (l2t_mb0_run),
6524 .cam_read_fail (ic_cam_read_fail[2]),
6525 .mbist_dc_ic_read_en ({ic_rd_en_row0[2],ic_rd_en_row2[2]}),
6526 .rddata_out_c52_top(ic_rd_data26_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6527 .rddata_out_c52_bottom(ic_rd_dataae_row1[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6528 .rd_data_sel_c52_top(ic_row0_select_panel2), // Templated
6529 .rd_data_sel_c52_bottom(ic_row1_select_panel2), // Templated
6530 .parity_vld_in(3'b0)); // Templated
6531
6532l2t_dirout_dp out_col3 (
6533 .tcu_pce_ov(ce_ovrd),
6534 .tcu_aclk(aclk),
6535 .tcu_bclk(bclk),
6536 .tcu_scan_en(tcu_scan_en),
6537 .tcu_clk_stop(1'b0),
6538 .scan_in(out_col3_scanin),
6539 .scan_out(out_col3_scanout),
6540 .l2clk (l2clk),
6541 // Outputs
6542 .dirout_parity_vld_out(ic_parity_out[3:1]), // Templated
6543 .dirout_parity_vld(ic_parity_out[0]), // Templated
6544 // Inputs
6545 .mbist_read_data_pick_top (l2t_mb0_icrow_row_en[0]),
6546 .mbist_read_data_pick_bottom (l2t_mb0_icrow_row_en[1]),
6547 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6548 .l2t_mb0_run (l2t_mb0_run),
6549 .cam_read_fail (ic_cam_read_fail[3]),
6550 .mbist_dc_ic_read_en ({ic_rd_en_row0[3],ic_rd_en_row2[3]}),
6551 .rddata_out_c52_top(ic_rd_data37_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6552 .rddata_out_c52_bottom(ic_rd_databf_row1[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6553 .rd_data_sel_c52_top(ic_row0_select_panel3), // Templated
6554 .rd_data_sel_c52_bottom(ic_row1_select_panel3), // Templated
6555 .parity_vld_in(ic_parity_in[2:0])); // Templated
6556
6557
6558
6559// Second half
6560n2_com_cm_64x64_cust ic_row2 (
6561 .scan_in(ic_row2_scanin),
6562 .scan_out(ic_row2_scanout),
6563 .l2clk (l2clk),
6564 // Outputs
6565 .row_hit (ic_cam_hit[127:64]), // Templated
6566 .rd_data0 (ic_rd_data8c_row1[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6567 .rd_data1 (ic_rd_data9d_row1[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6568 .rd_data2 (ic_rd_dataae_row1[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6569 .rd_data3 (ic_rd_databf_row1[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6570 // Inputs
6571 .tcu_pce_ov(ce_ovrd),
6572 .pce (1'b1),
6573 .tcu_aclk(aclk),
6574 .tcu_bclk(bclk),
6575 .tcu_scan_en(tcu_scan_en),
6576 .tcu_array_bypass (tcu_array_bypass),
6577 .force_hit ({4{ic_force_hit_row2_c4}}),
6578 .cam_en (ic_cam_en_row2[3:0]), // Templated
6579 .inv_mask0 (ic_inv_mask_89cd[7:0]), // Templated
6580 .inv_mask1 (ic_inv_mask_89cd[7:0]), // Templated
6581 .inv_mask2 (ic_inv_mask_89cd[7:0]), // Templated
6582 .inv_mask3 (ic_inv_mask_89cd[7:0]), // Templated
6583 .tcu_se_scancollar_in (tcu_se_scancollar_in), // Templated
6584 .rd_en (ic_rd_en_row2[3:0]), // Templated
6585 .rw_addr0 (ic_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6586 .rw_addr1 (ic_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6587 .rw_addr2 (ic_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6588 .rw_addr3 (ic_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6589 .rst_warm_0 (ic_warm_rst_89cd), // Templated
6590 .rst_warm_1 (ic_warm_rst_89cd), // Templated
6591 .wr_en (ic_wr_en_row2[3:0]), // Templated
6592 .tcu_array_wr_inhibit (array_wr_inhibit), // Templated
6593 .wr_data0 (ic_lkup_wr_data_c4_row2[15:0]), // Templated
6594 .wr_data1 (ic_lkup_wr_data_c4_row2[15:0]), // Templated
6595 .wr_data2 (ic_lkup_wr_data_c4_row2[15:0]), // Templated
6596 .wr_data3 (ic_lkup_wr_data_c4_row2[15:0])); // Templated
6597
6598
6599
6600///////////////////////////////////////////
6601// D$ directory starts here.
6602///////////////////////////////////////////
6603
6604// panels 0,1,2,3
6605n2_com_cm_64x64_cust dc_row0 (
6606 .scan_in(dc_row0_scanin),
6607 .scan_out(dc_row0_scanout),
6608 .l2clk (l2clk),
6609
6610 /*AUTOINST*/
6611 // Outputs
6612 .row_hit (dc_cam_hit[63:0]), // Templated
6613 .rd_data0 (dc_rd_data04_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6614 .rd_data1 (dc_rd_data15_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6615 .rd_data2 (dc_rd_data26_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6616 .rd_data3 (dc_rd_data37_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6617 // Inputs
6618 .tcu_pce_ov (ce_ovrd),
6619 .pce (1'b1),
6620 .tcu_aclk (aclk),
6621 .tcu_bclk (bclk),
6622 .tcu_scan_en (tcu_scan_en),
6623 .tcu_array_bypass (tcu_array_bypass),
6624 .force_hit ({4{dc_force_hit_row0_c4}}),
6625 .cam_en (dc_cam_en_row0[3:0]), // Templated
6626 .inv_mask0 (dc_inv_mask_0145[7:0]), // Templated
6627 .inv_mask1 (dc_inv_mask_0145[7:0]), // Templated
6628 .inv_mask2 (dc_inv_mask_0145[7:0]), // Templated
6629 .inv_mask3 (dc_inv_mask_0145[7:0]), // Templated
6630 .tcu_se_scancollar_in (tcu_se_scancollar_in), // Templated
6631 .rd_en (dc_rd_en_row0[3:0]), // Templated
6632 .rw_addr0 (dc_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6633 .rw_addr1 (dc_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6634 .rw_addr2 (dc_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6635 .rw_addr3 (dc_rw_addr_0145[5:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6636 .rst_warm_0 (dc_warm_rst_0145), // Templated
6637 .rst_warm_1 (dc_warm_rst_0145), // Templated
6638 .wr_en (dc_wr_en_row0[3:0]), // Templated
6639 .tcu_array_wr_inhibit (array_wr_inhibit), // Templated
6640 .wr_data0 (dc_lkup_wr_data_c4_row0[15:0]), // Templated
6641 .wr_data1 (dc_lkup_wr_data_c4_row0[15:0]), // Templated
6642 .wr_data2 (dc_lkup_wr_data_c4_row0[15:0]), // Templated
6643 .wr_data3 (dc_lkup_wr_data_c4_row0[15:0])); // Templated
6644
6645
6646
6647
6648l2t_dirout_dp dc_out_col0 (
6649 .tcu_pce_ov(ce_ovrd),
6650 .tcu_aclk(aclk),
6651 .tcu_bclk(bclk),
6652 .tcu_scan_en(tcu_scan_en),
6653 .tcu_clk_stop(1'b0),
6654 .scan_in(dc_out_col0_scanin),
6655 .scan_out(dc_out_col0_scanout),
6656 .l2clk (l2clk),
6657 // Outputs
6658 .dirout_parity_vld_out(dc_out_col0parity_vld_out_unused[2:0]), // Templated
6659 .dirout_parity_vld(dc_parity_in[0]), // Templated
6660 // Inputs
6661 .mbist_read_data_pick_top (l2t_mb0_dcrow_row_en[0]),
6662 .mbist_read_data_pick_bottom (l2t_mb0_dcrow_row_en[1]),
6663 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6664 .l2t_mb0_run (l2t_mb0_run),
6665 .cam_read_fail (dc_cam_read_fail[0]),
6666 .mbist_dc_ic_read_en ({dc_rd_en_row0[0],dc_rd_en_row2[0]}),
6667 .rddata_out_c52_top(dc_rd_data04_row0[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6668 .rddata_out_c52_bottom(dc_rd_data8c_row2[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6669 .rd_data_sel_c52_top(dc_row0_select_panel0), // Templated
6670 .rd_data_sel_c52_bottom(dc_row1_select_panel0), // Templated
6671 .parity_vld_in(3'b0)); // Templated
6672
6673l2t_dirout_dp dc_out_col1 (
6674 .tcu_pce_ov(ce_ovrd),
6675 .tcu_aclk(aclk),
6676 .tcu_bclk(bclk),
6677 .tcu_scan_en(tcu_scan_en),
6678 .tcu_clk_stop(1'b0),
6679 .scan_in(dc_out_col1_scanin),
6680 .scan_out(dc_out_col1_scanout),
6681 .l2clk (l2clk),
6682 // Outputs
6683 .dirout_parity_vld_out(dc_out_col1parity_vld_out_unused[2:0]), // Templated
6684 .dirout_parity_vld(dc_parity_in[1]), // Templated
6685 // Inputs
6686 .mbist_read_data_pick_top (l2t_mb0_dcrow_row_en[0]),
6687 .mbist_read_data_pick_bottom (l2t_mb0_dcrow_row_en[1]),
6688 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6689 .l2t_mb0_run (l2t_mb0_run),
6690 .cam_read_fail (dc_cam_read_fail[1]),
6691 .mbist_dc_ic_read_en ({dc_rd_en_row0[1],dc_rd_en_row2[1]}),
6692 .rddata_out_c52_top(dc_rd_data15_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6693 .rddata_out_c52_bottom(dc_rd_data9d_row2[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6694 .rd_data_sel_c52_top(dc_row0_select_panel1), // Templated
6695 .rd_data_sel_c52_bottom(dc_row1_select_panel1), // Templated
6696 .parity_vld_in(3'b0)); // Templated
6697
6698l2t_dirout_dp dc_out_col2 (
6699 .tcu_pce_ov(ce_ovrd),
6700 .tcu_aclk(aclk),
6701 .tcu_bclk(bclk),
6702 .tcu_scan_en(tcu_scan_en),
6703 .tcu_clk_stop(1'b0),
6704 .scan_in(dc_out_col2_scanin),
6705 .scan_out(dc_out_col2_scanout),
6706 .l2clk (l2clk),
6707 // Outputs
6708 .dirout_parity_vld_out(dc_out_col2parity_vld_out_unused[2:0]), // Templated
6709 .dirout_parity_vld(dc_parity_in[2]), // Templated
6710 // Inputs
6711 .mbist_read_data_pick_top (l2t_mb0_dcrow_row_en[0]),
6712 .mbist_read_data_pick_bottom (l2t_mb0_dcrow_row_en[1]),
6713 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6714 .l2t_mb0_run (l2t_mb0_run),
6715 .cam_read_fail (dc_cam_read_fail[2]),
6716 .mbist_dc_ic_read_en ({dc_rd_en_row0[2],dc_rd_en_row2[2]}),
6717 .rddata_out_c52_top(dc_rd_data26_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6718 .rddata_out_c52_bottom(dc_rd_dataae_row2[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6719 .rd_data_sel_c52_top(dc_row0_select_panel2), // Templated
6720 .rd_data_sel_c52_bottom(dc_row1_select_panel2), // Templated
6721 .parity_vld_in(3'b0)); // Templated
6722
6723l2t_dirout_dp dc_out_col3 (
6724 .tcu_pce_ov(ce_ovrd),
6725 .tcu_aclk(aclk),
6726 .tcu_bclk(bclk),
6727 .tcu_scan_en(tcu_scan_en),
6728 .tcu_clk_stop(1'b0),
6729 .scan_in(dc_out_col3_scanin),
6730 .scan_out(dc_out_col3_scanout),
6731 .l2clk (l2clk),
6732
6733 // Outputs
6734 .dirout_parity_vld_out(dc_parity_out[3:1]), // Templated
6735 .dirout_parity_vld(dc_parity_out[0]), // Templated
6736 // Inputs
6737 .mbist_read_data_pick_top (l2t_mb0_dcrow_row_en[0]),
6738 .mbist_read_data_pick_bottom (l2t_mb0_dcrow_row_en[1]),
6739 .mbist_lkup_wrdata (l2t_mb0_lookup_wdata[15:0]),
6740 .l2t_mb0_run (l2t_mb0_run),
6741 .cam_read_fail (dc_cam_read_fail[3]),
6742 .mbist_dc_ic_read_en ({dc_rd_en_row0[3],dc_rd_en_row2[3]}),
6743 .rddata_out_c52_top(dc_rd_data37_row0[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6744 .rddata_out_c52_bottom(dc_rd_databf_row2[15:0]), // Templated,BS and SR 11/18/03 Reverse Directory change
6745 .rd_data_sel_c52_top(dc_row0_select_panel3), // Templated
6746 .rd_data_sel_c52_bottom(dc_row1_select_panel3), // Templated
6747 .parity_vld_in(dc_parity_in[2:0])); // Templated
6748
6749
6750
6751
6752l2t_dirtop_ctl ic_row0_ctl
6753 (
6754 .scan_in(ic_row0_ctl_scanin),
6755 .scan_out(ic_row0_ctl_scanout),
6756 .l2clk (l2clk),
6757 .tcu_pce_ov (tcu_pce_ov),
6758 .tcu_aclk (tcu_aclk),
6759 .tcu_bclk (tcu_bclk),
6760 .tcu_scan_en (tcu_scan_en),
6761 .l2t_mb0_run (l2t_mb0_run),
6762 .l2t_mb0_mask (l2t_mb0_mask[7:0]),
6763 .l2t_mb0_addr (l2t_mb0_addr[5:0]),
6764 .l2t_mb0_row_panel_en (l2t_mb0_icrow_panel_en[3:0]),
6765 .l2t_mb0_row_row_en (l2t_mb0_icrow_row_en[0]),
6766 .l2t_mb0_row_lookup_en (l2t_mb0_icrow_lookup_en[3:0]),
6767 .l2t_mb0_lookup_wdata (l2t_mb0_lookup_wdata[15:0]),
6768 .l2t_mb0_row_wr_en (l2t_mb0_icrow_wr_en),
6769 .l2t_mb0_row_rd_en (l2t_mb0_icrow_rd_en),
6770 .ic_dc_dir (1'b1),
6771 .arb_force_hit_c4 (arb_ic_evict_c4),
6772 .arbadr_arbdp_addr4_c4 (arbadr_arbdp_addr4_c4),
6773 .dirrep_rd_en_c4 (dirrep_ic_rd_en_c4),
6774 .dirrep_wr_en_c4 (dirrep_ic_wr_en_c4),
6775 .addr_index_bit5 (arbadr_arbdp_index_ic_addr4_c4),
6776 .dirrep_inval_mask_c4 (dirrep_inval_mask_icd_c4[7:0]),
6777 .dirrep_rdwr_row_en_c4 (dirrep_ic_rdwr_row_en_c4[1:0]),
6778 .dirrep_lkup_row_dec_c4 (dirrep_ic_lkup_row_dec_c4[1:0]),
6779 .dirrep_lkup_panel_dec_c4 (dirrep_ic_lkup_panel_dec_c4[3:0]),
6780 .dirrep_rdwr_panel_dec_c4 (dirrep_ic_rdwr_panel_dec_c4[3:0]),
6781 .dirrep_rw_entry_c4 ({arbadr_arbdp_ic_addr4_c4,
6782 dirrep_wr_ic_dir_entry_c4[4:0]}),
6783 .lkup_wr_data_c4 ({dirrep_dir_vld_c4_l,
6784 dirrep_dir_wr_par_c4,
6785 tagd_lkup_ic_addr_c4[17:9],
6786 tag_dir_l2way_sel_c4[3:0]}),
6787 .dir_clear_c4 (dirrep_ic_dir_clear_c4),
6788 .dir_rd_data_en_c4 (ic_rd_en_row0[3:0]),
6789 .dir_wr_data_en_c4 (ic_wr_en_row0[3:0]),
6790 .dir_cam_en_c4 (ic_cam_en_row0[3:0]),
6791 .dir_rw_entry_c4 (ic_rw_addr_0145[5:0]),
6792 .dir_inval_mask_c4 (ic_inv_mask_0145[7:0]),
6793 .dir_warm_rst_c4 (ic_warm_rst_0145),
6794 .dirlbf_lkup_wr_data_c4_buf (ic_lkup_wr_data_c4_row0[15:0]),
6795 .dirlbf_force_hit_c4 (ic_force_hit_row0_c4),
6796 .select_panel0 (ic_row0_select_panel0),
6797 .select_panel1 (ic_row0_select_panel1),
6798 .select_panel2 (ic_row0_select_panel2),
6799 .select_panel3 (ic_row0_select_panel3)
6800 );
6801
6802l2t_dirtop_ctl ic_row2_ctl
6803 (
6804 .scan_in(ic_row2_ctl_scanin),
6805 .scan_out(ic_row2_ctl_scanout),
6806 .l2clk (l2clk),
6807 .tcu_pce_ov (tcu_pce_ov),
6808 .tcu_aclk (tcu_aclk),
6809 .tcu_bclk (tcu_bclk),
6810 .tcu_scan_en (tcu_scan_en),
6811 .l2t_mb0_run (l2t_mb0_run),
6812 .l2t_mb0_mask (l2t_mb0_mask[7:0]),
6813 .l2t_mb0_addr (l2t_mb0_addr[5:0]),
6814 .l2t_mb0_row_panel_en (l2t_mb0_icrow_panel_en[3:0]),
6815 .l2t_mb0_row_row_en (l2t_mb0_icrow_row_en[1]),
6816 .l2t_mb0_row_lookup_en (l2t_mb0_icrow_lookup_en[3:0]),
6817 .l2t_mb0_lookup_wdata (l2t_mb0_lookup_wdata[15:0]),
6818 .l2t_mb0_row_wr_en (l2t_mb0_icrow_wr_en),
6819 .l2t_mb0_row_rd_en (l2t_mb0_icrow_rd_en),
6820 .ic_dc_dir (1'b1),
6821 .arb_force_hit_c4 (arb_ic_evict_c4),
6822 .arbadr_arbdp_addr4_c4 (arbadr_arbdp_addr4_c4),
6823 .dirrep_rd_en_c4 (dirrep_ic_rd_en_c4),
6824 .dirrep_wr_en_c4 (dirrep_ic_wr_en_c4),
6825 .addr_index_bit5 (arbadr_arbdp_index_ic_addr4_c4),
6826 .dirrep_inval_mask_c4 (dirrep_inval_mask_icd_c4[7:0]),
6827 .dirrep_rdwr_row_en_c4 (dirrep_ic_rdwr_row_en_c4[3:2]),
6828 .dirrep_lkup_row_dec_c4 (dirrep_ic_lkup_row_dec_c4[3:2]),
6829 .dirrep_lkup_panel_dec_c4 (dirrep_ic_lkup_panel_dec_c4[3:0]),
6830 .dirrep_rdwr_panel_dec_c4 (dirrep_ic_rdwr_panel_dec_c4[3:0]),
6831 .dirrep_rw_entry_c4 ({arbadr_arbdp_ic_addr4_c4,
6832 dirrep_wr_ic_dir_entry_c4[4:0]}),
6833 .lkup_wr_data_c4 ({dirrep_dir_vld_c4_l,
6834 dirrep_dir_wr_par_c4,
6835 tagd_lkup_ic_addr_c4[17:9],
6836 tag_dir_l2way_sel_c4[3:0]}),
6837 .dir_clear_c4 (dirrep_ic_dir_clear_c4),
6838 .dir_rd_data_en_c4 (ic_rd_en_row2[3:0]),
6839 .dir_wr_data_en_c4 (ic_wr_en_row2[3:0]),
6840 .dir_cam_en_c4 (ic_cam_en_row2[3:0]),
6841 .dir_rw_entry_c4 (ic_rw_addr_89cd[5:0]),
6842 .dir_inval_mask_c4 (ic_inv_mask_89cd[7:0]),
6843 .dir_warm_rst_c4 (ic_warm_rst_89cd),
6844 .dirlbf_lkup_wr_data_c4_buf (ic_lkup_wr_data_c4_row2[15:0]),
6845 .dirlbf_force_hit_c4 (ic_force_hit_row2_c4),
6846 .select_panel0 (ic_row1_select_panel0),
6847 .select_panel1 (ic_row1_select_panel1),
6848 .select_panel2 (ic_row1_select_panel2),
6849 .select_panel3 (ic_row1_select_panel3)
6850 );
6851
6852
6853l2t_dirtop_ctl dc_row0_ctl
6854 (
6855 .scan_in(dc_row0_ctl_scanin),
6856 .scan_out(dc_row0_ctl_scanout),
6857 .l2clk (l2clk),
6858 .tcu_pce_ov (tcu_pce_ov),
6859 .tcu_aclk (tcu_aclk),
6860 .tcu_bclk (tcu_bclk),
6861 .tcu_scan_en (tcu_scan_en),
6862 .l2t_mb0_run (l2t_mb0_run),
6863 .l2t_mb0_mask (l2t_mb0_mask[7:0]),
6864 .l2t_mb0_addr (l2t_mb0_addr[5:0]),
6865 .l2t_mb0_row_panel_en (l2t_mb0_dcrow_panel_en[3:0]),
6866 .l2t_mb0_row_row_en (l2t_mb0_dcrow_row_en[0]),
6867 .l2t_mb0_row_lookup_en (l2t_mb0_dcrow_lookup_en[3:0]),
6868 .l2t_mb0_lookup_wdata (l2t_mb0_lookup_wdata[15:0]),
6869 .l2t_mb0_row_wr_en (l2t_mb0_dcrow_wr_en),
6870 .l2t_mb0_row_rd_en (l2t_mb0_dcrow_rd_en),
6871 .ic_dc_dir (1'b0),
6872 .arb_force_hit_c4 (arb_dc_evict_c4),
6873 .arbadr_arbdp_addr4_c4 (arbadr_arbdp_addr4_c4),
6874 .dirrep_rd_en_c4 (dirrep_dc_rd_en_c4),
6875 .dirrep_wr_en_c4 (dirrep_dc_wr_en_c4),
6876 .addr_index_bit5 (arbadr_arbdp_index_dc_addr4_c4),
6877 .dirrep_inval_mask_c4 (dirrep_inval_mask_dcd_c4[7:0]),
6878 .dirrep_rdwr_row_en_c4 (dirrep_dc_rdwr_row_en_c4[1:0]),
6879 .dirrep_lkup_row_dec_c4 (dirrep_dc_lkup_row_dec_c4[1:0]),
6880 .dirrep_lkup_panel_dec_c4 (dirrep_dc_lkup_panel_dec_c4[3:0]),
6881 .dirrep_rdwr_panel_dec_c4 (dirrep_dc_rdwr_panel_dec_c4[3:0]),
6882 .dirrep_rw_entry_c4 ({arbadr_arbdp_dc_addr4_c4,dirrep_wr_dc_dir_entry_c4[4:0]}),
6883 .lkup_wr_data_c4 ({dirrep_dir_vld_c4_l,dirrep_dir_wr_par_c4,
6884 tagd_lkup_dc_addr_c4[17:9],tag_dir_l2way_sel_c4[3:0]}),
6885 .dir_clear_c4 (dirrep_dc_dir_clear_c4),
6886 .dir_rd_data_en_c4 (dc_rd_en_row0[3:0]),
6887 .dir_wr_data_en_c4 (dc_wr_en_row0[3:0]),
6888 .dir_cam_en_c4 (dc_cam_en_row0[3:0]),
6889 .dir_rw_entry_c4 (dc_rw_addr_0145[5:0]),
6890 .dir_inval_mask_c4 (dc_inv_mask_0145[7:0]),
6891 .dir_warm_rst_c4 (dc_warm_rst_0145),
6892 .dirlbf_lkup_wr_data_c4_buf (dc_lkup_wr_data_c4_row0[15:0]),
6893 .dirlbf_force_hit_c4 (dc_force_hit_row0_c4),
6894 .select_panel0 (dc_row0_select_panel0),
6895 .select_panel1 (dc_row0_select_panel1),
6896 .select_panel2 (dc_row0_select_panel2),
6897 .select_panel3 (dc_row0_select_panel3)
6898 );
6899
6900
6901l2t_dirtop_ctl dc_row2_ctl
6902 (
6903 .scan_in(dc_row2_ctl_scanin),
6904 .scan_out(dc_row2_ctl_scanout),
6905 .l2clk (l2clk),
6906 .tcu_pce_ov (tcu_pce_ov),
6907 .tcu_aclk (tcu_aclk),
6908 .tcu_bclk (tcu_bclk),
6909 .tcu_scan_en (tcu_scan_en),
6910 .l2t_mb0_run (l2t_mb0_run),
6911 .l2t_mb0_mask (l2t_mb0_mask[7:0]),
6912 .l2t_mb0_addr (l2t_mb0_addr[5:0]),
6913 .l2t_mb0_row_panel_en (l2t_mb0_dcrow_panel_en[3:0]),
6914 .l2t_mb0_row_row_en (l2t_mb0_dcrow_row_en[1]),
6915 .l2t_mb0_row_lookup_en (l2t_mb0_dcrow_lookup_en[3:0]),
6916 .l2t_mb0_lookup_wdata (l2t_mb0_lookup_wdata[15:0]),
6917 .l2t_mb0_row_wr_en (l2t_mb0_dcrow_wr_en),
6918 .l2t_mb0_row_rd_en (l2t_mb0_dcrow_rd_en),
6919 .ic_dc_dir (1'b0),
6920 .arb_force_hit_c4 (arb_dc_evict_c4),
6921 .arbadr_arbdp_addr4_c4 (arbadr_arbdp_addr4_c4),
6922 .dirrep_rd_en_c4 (dirrep_dc_rd_en_c4),
6923 .dirrep_wr_en_c4 (dirrep_dc_wr_en_c4),
6924 .addr_index_bit5 (arbadr_arbdp_index_dc_addr4_c4),
6925 .dirrep_inval_mask_c4 (dirrep_inval_mask_dcd_c4[7:0]),
6926 .dirrep_rdwr_row_en_c4 (dirrep_dc_rdwr_row_en_c4[3:2]),
6927 .dirrep_lkup_row_dec_c4 (dirrep_dc_lkup_row_dec_c4[3:2]),
6928 .dirrep_lkup_panel_dec_c4 (dirrep_dc_lkup_panel_dec_c4[3:0]),
6929 .dirrep_rdwr_panel_dec_c4 (dirrep_dc_rdwr_panel_dec_c4[3:0]),
6930 .dirrep_rw_entry_c4 ({arbadr_arbdp_dc_addr4_c4,
6931 dirrep_wr_dc_dir_entry_c4[4:0]}),
6932 .lkup_wr_data_c4 ({dirrep_dir_vld_c4_l,dirrep_dir_wr_par_c4,
6933 tagd_lkup_dc_addr_c4[17:9],
6934 tag_dir_l2way_sel_c4[3:0]}),
6935 .dir_clear_c4 (dirrep_dc_dir_clear_c4),
6936 .dir_rd_data_en_c4 (dc_rd_en_row2[3:0]),
6937 .dir_wr_data_en_c4 (dc_wr_en_row2[3:0]),
6938 .dir_cam_en_c4 (dc_cam_en_row2[3:0]),
6939 .dir_rw_entry_c4 (dc_rw_addr_89cd[5:0]),
6940 .dir_inval_mask_c4 (dc_inv_mask_89cd[7:0]),
6941 .dir_warm_rst_c4 (dc_warm_rst_89cd),
6942 .dirlbf_lkup_wr_data_c4_buf (dc_lkup_wr_data_c4_row2[15:0]),
6943 .dirlbf_force_hit_c4 (dc_force_hit_row2_c4),
6944 .select_panel0 (dc_row1_select_panel0),
6945 .select_panel1 (dc_row1_select_panel1),
6946 .select_panel2 (dc_row1_select_panel2),
6947 .select_panel3 (dc_row1_select_panel3)
6948 );
6949
6950// Second half
6951n2_com_cm_64x64_cust dc_row2 (
6952 .scan_in(dc_row2_scanin),
6953 .scan_out(dc_row2_scanout),
6954 .l2clk (l2clk),
6955
6956 /*AUTOINST*/
6957 // Outputs
6958 .row_hit (dc_cam_hit[127:64]), // Templated
6959 .rd_data0 (dc_rd_data8c_row2[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6960 .rd_data1 (dc_rd_data9d_row2[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6961 .rd_data2 (dc_rd_dataae_row2[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6962 .rd_data3 (dc_rd_databf_row2[15:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6963 // Inputs
6964 .tcu_pce_ov(ce_ovrd),
6965 .pce (1'b1),
6966 .tcu_aclk(aclk),
6967 .tcu_bclk(bclk),
6968 .tcu_scan_en(tcu_scan_en),
6969 .tcu_array_bypass (tcu_array_bypass),
6970 .force_hit ({4{dc_force_hit_row2_c4}}),
6971 .cam_en (dc_cam_en_row2[3:0]), // Templated
6972 .inv_mask0 (dc_inv_mask_89cd[7:0]), // Templated
6973 .inv_mask1 (dc_inv_mask_89cd[7:0]), // Templated
6974 .inv_mask2 (dc_inv_mask_89cd[7:0]), // Templated
6975 .inv_mask3 (dc_inv_mask_89cd[7:0]), // Templated
6976 .tcu_se_scancollar_in (tcu_se_scancollar_in), // Templated
6977 .rd_en (dc_rd_en_row2[3:0]), // Templated
6978 .rw_addr0 (dc_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6979 .rw_addr1 (dc_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6980 .rw_addr2 (dc_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6981 .rw_addr3 (dc_rw_addr_89cd[5:0]), // Templated, BS and SR 11/18/03 Reverse Directory change
6982 .rst_warm_0 (dc_warm_rst_89cd), // Templated
6983 .rst_warm_1 (dc_warm_rst_89cd), // Templated
6984 .wr_en (dc_wr_en_row2[3:0]), // Templated
6985 .tcu_array_wr_inhibit (array_wr_inhibit), // Templated
6986 .wr_data0 (dc_lkup_wr_data_c4_row2[15:0]), // Templated
6987 .wr_data1 (dc_lkup_wr_data_c4_row2[15:0]), // Templated
6988 .wr_data2 (dc_lkup_wr_data_c4_row2[15:0]), // Templated
6989 .wr_data3 (dc_lkup_wr_data_c4_row2[15:0])); // Templated
6990
6991
6992
6993//////////////////////////////////////////////////////////////////////////////
6994//
6995// REPEATERS
6996//
6997////////////////////////////////////////////////////////////////////////////
6998l2t_rep_dp repeater
6999 (
7000 .rep_in0 (l2t_rep_in0[23:0]),
7001 .rep_in1 (l2t_rep_in1[23:0]),
7002 .rep_in2 (l2t_rep_in2[23:0]),
7003 .rep_in3 (l2t_rep_in3[23:0]),
7004 .rep_in4 (l2t_rep_in4[23:0]),
7005 .rep_in5 (l2t_rep_in5[23:0]),
7006 .rep_in6 (l2t_rep_in6[23:0]),
7007 .rep_in7 (l2t_rep_in7[23:0]),
7008 .rep_in8 (l2t_rep_in8[23:0]),
7009 .rep_in9 (l2t_rep_in9[23:0]),
7010 .rep_in10 (l2t_rep_in10[23:0]),
7011 .rep_in11 (l2t_rep_in11[23:0]),
7012 .rep_in12 (l2t_rep_in12[23:0]),
7013 .rep_in13 (l2t_rep_in13[23:0]),
7014 .rep_in14 (l2t_rep_in14[23:0]),
7015 .rep_in15 (l2t_rep_in15[23:0]),
7016 .rep_in16 (l2t_rep_in16[23:0]),
7017 .rep_in17 (l2t_rep_in17[23:0]),
7018 .rep_in18 (l2t_rep_in18[23:0]),
7019 .rep_in19 (l2t_rep_in19[23:0]),
7020 .rep_out0 (l2t_rep_out0[23:0]),
7021 .rep_out1 (l2t_rep_out1[23:0]),
7022 .rep_out2 (l2t_rep_out2[23:0]),
7023 .rep_out3 (l2t_rep_out3[23:0]),
7024 .rep_out4 (l2t_rep_out4[23:0]),
7025 .rep_out5 (l2t_rep_out5[23:0]),
7026 .rep_out6 (l2t_rep_out6[23:0]),
7027 .rep_out7 (l2t_rep_out7[23:0]),
7028 .rep_out8 (l2t_rep_out8[23:0]),
7029 .rep_out9 (l2t_rep_out9[23:0]),
7030 .rep_out10 (l2t_rep_out10[23:0]),
7031 .rep_out11 (l2t_rep_out11[23:0]),
7032 .rep_out12 (l2t_rep_out12[23:0]),
7033 .rep_out13 (l2t_rep_out13[23:0]),
7034 .rep_out14 (l2t_rep_out14[23:0]),
7035 .rep_out15 (l2t_rep_out15[23:0]),
7036 .rep_out16 (l2t_rep_out16[23:0]),
7037 .rep_out17 (l2t_rep_out17[23:0]),
7038 .rep_out18 (l2t_rep_out18[23:0]),
7039 .rep_out19 (l2t_rep_out19[23:0])
7040 );
7041
7042l2t_ffrpt_dp left_ffrptr
7043 (
7044 .data_in (l2t_lstg_in[191:0]),
7045 .tcu_clk_stop (1'b0),
7046 .tcu_pce_ov (tcu_pce_ov),
7047 .tcu_scan_en (tcu_scan_en),
7048 .tcu_aclk (tcu_aclk),
7049 .tcu_bclk (tcu_bclk),
7050 .scan_in(left_ffrptr_scanin),
7051 .scan_out(left_ffrptr_scanout),
7052 .l2clk (l2clk),
7053 .data_out (l2t_lstg_out[191:0])
7054 );
7055
7056l2t_ffrpt_dp right_ffrptr
7057 (
7058 .data_in (l2t_rstg_in[191:0]),
7059 .tcu_clk_stop (1'b0),
7060 .tcu_pce_ov (tcu_pce_ov),
7061 .tcu_scan_en (tcu_scan_en),
7062 .tcu_aclk (tcu_aclk),
7063 .tcu_bclk (tcu_bclk),
7064 .scan_in(right_ffrptr_scanin),
7065 .scan_out(right_ffrptr_scanout),
7066 .l2clk (l2clk),
7067 .data_out (l2t_rstg_out[191:0])
7068 );
7069
7070/////////////////////////////////////////////////////////////////////////////////
7071// Manual repeaters for internal timing fixes
7072/////////////////////////////////////////////////////////////////////////////////
7073
7074
7075l2t_mrep16x8_dp mrep_besides_tagl
7076 (
7077 .rep_out0 (vlddir_vuad_valid_c2_rep1[15:0]),
7078 .rep_out1 ({tag_st_to_data_array_c3_rep1,tagdp_evict_c3_2_rep1,
7079 tagdp_evict_c3_1_rep1,mrep_besides_tagl0_unused[12:0]}),
7080 .rep_out2 (mrep_besides_tagl1_unused[15:0]),
7081 .rep_out3 (mrep_besides_tagl2_unused[15:0]),
7082 .rep_out4 (mrep_besides_tagl3_unused[15:0]),
7083 .rep_out5 (mrep_besides_tagl4_unused[15:0]),
7084 .rep_out6 (mrep_besides_tagl5_unused[15:0]),
7085 .rep_out7 (mrep_besides_tagl6_unused[15:0]),
7086 .rep_in0 (vlddir_vuad_valid_c2[15:0]),
7087 .rep_in1 ({tag_st_to_data_array_c3,tagdp_evict_c3_2,
7088 tagdp_evict_c3_1,13'b0}),
7089 .rep_in2 (16'b0),
7090 .rep_in3 (16'b0),
7091 .rep_in4 (16'b0),
7092 .rep_in5 (16'b0),
7093 .rep_in6 (16'b0),
7094 .rep_in7 (16'b0)
7095 );
7096
7097l2t_mrep8x16_dp mrep_besides_mbdata
7098 (
7099 .rep_out0 (mrep_besides_mbdata1_unused[7:0]),
7100 .rep_out1 (mrep_besides_mbdata2_unused[7:0]),
7101 .rep_out2 (mrep_besides_mbdata3_unused[7:0]),
7102 .rep_out3 (mrep_besides_mbdata4_unused[7:0]),
7103 .rep_out4 (mrep_besides_mbdata5_unused[7:0]),
7104 .rep_out5 (mrep_besides_mbdata6_unused[7:0]),
7105 .rep_out6 (mrep_besides_mbdata7_unused[7:0]),
7106 .rep_out7 (tagdp_lru_way_sel_c3_rep20[7:0]),
7107 .rep_out8 (tagdp_lru_way_sel_c3_rep20[15:8]),
7108 .rep_out9 (tag_hit_way_vld_c3_rep20[7:0]),
7109 .rep_out10 (tag_hit_way_vld_c3_rep20[15:8]),
7110 .rep_out11 (tag_hit_way_vld_c3_rep2[7:0]),
7111 .rep_out12 (tag_hit_way_vld_c3_rep2[15:8]),
7112 .rep_out13 (tagdp_lru_way_sel_c3_rep2[7:0]),
7113 .rep_out14 (tagdp_lru_way_sel_c3_rep2[15:8]),
7114 .rep_out15 ({usaloc_vlddir_arb_vuad_ce_err_c3_rep1_v1,usaloc_vlddir_arb_vuad_ce_err_c3_rep1_v2,
7115 mrep_besides_mbdata15_unused[5:0]}),
7116 .rep_in0 (8'b0),
7117 .rep_in1 (8'b0),
7118 .rep_in2 (8'b0),
7119 .rep_in3 (8'b0),
7120 .rep_in4 (8'b0),
7121 .rep_in5 (8'b0),
7122 .rep_in6 (8'b0),
7123 .rep_in7 (tagdp_lru_way_sel_c3_rep1[7:0]),
7124 .rep_in8 (tagdp_lru_way_sel_c3_rep1[15:8]),
7125 .rep_in9 (tag_hit_way_vld_c3_rep1[7:0]),
7126 .rep_in10 (tag_hit_way_vld_c3_rep1[15:8]),
7127 .rep_in11 (tag_hit_way_vld_c3_rep1[7:0]),
7128 .rep_in12 (tag_hit_way_vld_c3_rep1[15:8]),
7129 .rep_in13 (tagdp_lru_way_sel_c3_rep1[7:0]),
7130 .rep_in14 (tagdp_lru_way_sel_c3_rep1[15:8]),
7131 .rep_in15 ({usaloc_vlddir_arb_vuad_ce_err_c3,usaloc_vlddir_arb_vuad_ce_err_c3,6'b0})
7132 );
7133
7134l2t_mrep32x3_dp mrep_arbdat_top
7135 (
7136 .rep_out0 (mrep_arbdat_top1_unused[31:0]),
7137 .rep_out1 (mrep_arbdat_top2_unused[31:0]),
7138 .rep_out2 (mrep_arbdat_top3_unused[31:0]),
7139 .rep_in0 (32'b0),
7140 .rep_in1 (32'b0),
7141 .rep_in2 (32'b0)
7142 );
7143
7144l2t_mrep32x3_dp mrep_arbdat_bot //1
7145 (
7146 .rep_out0 (mrep_arbdat_bot0_unused[31:0]),
7147 .rep_out1 (mrep_arbdat_bot1_unused[31:0]),
7148 .rep_out2 ({tagdp_lru_way_sel_c3_rep1[15:0],tag_hit_way_vld_c3_rep1[15:0]}),
7149 .rep_in0 (32'b0),
7150 .rep_in1 (32'b0),
7151 .rep_in2 ({tagdp_lru_way_sel_c3[15:0],tag_hit_way_vld_c3[15:0]})
7152 );
7153
7154
7155l2t_mrep32x3_dp mrep_arbdec_top //1
7156 (
7157 .rep_out0 ({arb_fill_vld_c2_rep1,mb_data_read_data_rep[`MBD_ECC_HI_PLUS5:`MBD_ECC_HI_PLUS1],
7158 mb_data_read_data_rep[`MBD_RQ_HI:`MBD_RQ_LO], mb_data_read_data_rep[`MBD_RSVD],
7159 mrep_arbdec_top_1_unused[19:0]}),
7160 .rep_out1 (mrep_arbdec_top1_unused[31:0]),
7161 .rep_out2 (mrep_arbdec_top2_unused[31:0]),
7162 .rep_in0 ({arb_fill_vld_c2,mb_data_read_data[`MBD_ECC_HI_PLUS5:`MBD_ECC_HI_PLUS1],
7163 mb_data_read_data[`MBD_RQ_HI:`MBD_RQ_LO], mb_data_read_data[`MBD_RSVD],20'b0}),
7164 .rep_in1 (32'b0),
7165 .rep_in2 (32'b0)
7166 );
7167
7168l2t_mrep2x64_dp mrep_besides_arbadr //1
7169 (
7170 .rep_out0 ({tag_rdma_gate_off_c2_rep1,mrep_besides_arbadr_out0_unused}),
7171 .rep_out1 ({filbuf_arb_tag_hit_frm_mb_c2_rep,filbuf_tag_tag_hit_frm_mb_c2_rep}),
7172 .rep_out2 (filbuf_tag_evict_way_c3_rep1[1:0]),
7173 .rep_out3 (filbuf_tag_evict_way_c3_rep1[3:2]),
7174 .rep_out4 ({tag_misbuf_rdma_reg_vld_c2_rep1a,tag_misbuf_rdma_reg_vld_c2_rep1b}),
7175 .rep_out5 ({arb_inst_vld_c1_v1,arb_inst_vld_c1_v2}),
7176 .rep_out6 ({mrep_besides_arbadr_unused,arb_inst_vld_c1_v3}),
7177 .rep_out7 ({filbuf_dis_cerr_c3_rep1,filbuf_dis_uerr_c3_rep1}),
7178 .rep_out8 (mrep_besides_arbadr11_unused[1:0]),
7179 .rep_out9 (mrep_besides_arbadr12_unused[1:0]),
7180 .rep_out10 (mrep_besides_arbadr13_unused[1:0]),
7181 .rep_out11 (mrep_besides_arbadr14_unused[1:0]),
7182 .rep_out12 (mrep_besides_arbadr15_unused[1:0]),
7183 .rep_out13 (mrep_besides_arbadr16_unused[1:0]),
7184 .rep_out14 (mrep_besides_arbadr17_unused[1:0]),
7185 .rep_out15 (mrep_besides_arbadr18_unused[1:0]),
7186 .rep_out16 (mrep_besides_arbadr19_unused[1:0]),
7187 .rep_out17 (mrep_besides_arbadr20_unused[1:0]),
7188 .rep_out18 (mrep_besides_arbadr21_unused[1:0]),
7189 .rep_out19 (mrep_besides_arbadr22_unused[1:0]),
7190 .rep_out20 (mrep_besides_arbadr23_unused[1:0]),
7191 .rep_out21 (mrep_besides_arbadr24_unused[1:0]),
7192 .rep_out22 (mrep_besides_arbadr25_unused[1:0]),
7193 .rep_out23 (mrep_besides_arbadr26_unused[1:0]),
7194 .rep_out24 (mrep_besides_arbadr27_unused[1:0]),
7195 .rep_out25 (mrep_besides_arbadr28_unused[1:0]),
7196 .rep_out26 (mrep_besides_arbadr29_unused[1:0]),
7197 .rep_out27 (mrep_besides_arbadr30_unused[1:0]),
7198 .rep_out28 (mrep_besides_arbadr31_unused[1:0]),
7199 .rep_out29 (mrep_besides_arbadr32_unused[1:0]),
7200 .rep_out30 (mrep_besides_arbadr33_unused[1:0]),
7201 .rep_out31 (mrep_besides_arbadr34_unused[1:0]),
7202 .rep_out32 (mrep_besides_arbadr35_unused[1:0]),
7203 .rep_out33 (mrep_besides_arbadr36_unused[1:0]),
7204 .rep_out34 (mrep_besides_arbadr37_unused[1:0]),
7205 .rep_out35 (mrep_besides_arbadr38_unused[1:0]),
7206 .rep_out36 (mrep_besides_arbadr39_unused[1:0]),
7207 .rep_out37 (mrep_besides_arbadr40_unused[1:0]),
7208 .rep_out38 (mrep_besides_arbadr41_unused[1:0]),
7209 .rep_out39 (mrep_besides_arbadr42_unused[1:0]),
7210 .rep_out40 (mrep_besides_arbadr43_unused[1:0]),
7211 .rep_out41 (mrep_besides_arbadr44_unused[1:0]),
7212 .rep_out42 (mrep_besides_arbadr45_unused[1:0]),
7213 .rep_out43 (mrep_besides_arbadr46_unused[1:0]),
7214 .rep_out44 (mrep_besides_arbadr47_unused[1:0]),
7215 .rep_out45 (mrep_besides_arbadr48_unused[1:0]),
7216 .rep_out46 (mrep_besides_arbadr49_unused[1:0]),
7217 .rep_out47 (mrep_besides_arbadr50_unused[1:0]),
7218 .rep_out48 (mrep_besides_arbadr51_unused[1:0]),
7219 .rep_out49 (mrep_besides_arbadr52_unused[1:0]),
7220 .rep_out50 (mrep_besides_arbadr53_unused[1:0]),
7221 .rep_out51 (mrep_besides_arbadr54_unused[1:0]),
7222 .rep_out52 (mrep_besides_arbadr55_unused[1:0]),
7223 .rep_out53 (mrep_besides_arbadr56_unused[1:0]),
7224 .rep_out54 (mrep_besides_arbadr57_unused[1:0]),
7225 .rep_out55 (mrep_besides_arbadr58_unused[1:0]),
7226 .rep_out56 (mrep_besides_arbadr59_unused[1:0]),
7227 .rep_out57 (mrep_besides_arbadr60_unused[1:0]),
7228 .rep_out58 (mrep_besides_arbadr61_unused[1:0]),
7229 .rep_out59 (mrep_besides_arbadr62_unused[1:0]),
7230 .rep_out60 (mrep_besides_arbadr63_unused[1:0]),
7231 .rep_out61 (mrep_besides_arbadr64_unused[1:0]),
7232 .rep_out62 ({misbuf_tag_hit_unqual_c2_rep2,misbuf_notdata_err_c2_rep1}),
7233 .rep_out63 ({tag_miss_unqual_c2_rep1,misbuf_tag_hit_unqual_c2_rep1}),
7234 .rep_in0 ({tag_rdma_gate_off_c2,1'b0}),
7235 .rep_in1 ({filbuf_arb_tag_hit_frm_mb_c2,filbuf_arb_tag_hit_frm_mb_c2}),
7236 .rep_in2 (filbuf_tag_evict_way_c3[1:0]),
7237 .rep_in3 (filbuf_tag_evict_way_c3[3:2]),
7238 .rep_in4 ({tag_misbuf_rdma_reg_vld_c2,tag_misbuf_rdma_reg_vld_c2}),
7239 .rep_in5 ({arb_inst_vld_c1,arb_inst_vld_c1}),
7240 .rep_in6 ({1'b0,arb_inst_vld_c1}),
7241 .rep_in7 ({filbuf_dis_cerr_c3,filbuf_dis_uerr_c3}),
7242 .rep_in8 (2'b0),
7243 .rep_in9 (2'b0),
7244 .rep_in10 (2'b0),
7245 .rep_in11 (2'b0),
7246 .rep_in12 (2'b0),
7247 .rep_in13 (2'b0),
7248 .rep_in14 (2'b0),
7249 .rep_in15 (2'b0),
7250 .rep_in16 (2'b0),
7251 .rep_in17 (2'b0),
7252 .rep_in18 (2'b0),
7253 .rep_in19 (2'b0),
7254 .rep_in20 (2'b0),
7255 .rep_in21 (2'b0),
7256 .rep_in22 (2'b0),
7257 .rep_in23 (2'b0),
7258 .rep_in24 (2'b0),
7259 .rep_in25 (2'b0),
7260 .rep_in26 (2'b0),
7261 .rep_in27 (2'b0),
7262 .rep_in28 (2'b0),
7263 .rep_in29 (2'b0),
7264 .rep_in30 (2'b0),
7265 .rep_in31 (2'b0),
7266 .rep_in32 (2'b0),
7267 .rep_in33 (2'b0),
7268 .rep_in34 (2'b0),
7269 .rep_in35 (2'b0),
7270 .rep_in36 (2'b0),
7271 .rep_in37 (2'b0),
7272 .rep_in38 (2'b0),
7273 .rep_in39 (2'b0),
7274 .rep_in40 (2'b0),
7275 .rep_in41 (2'b0),
7276 .rep_in42 (2'b0),
7277 .rep_in43 (2'b0),
7278 .rep_in44 (2'b0),
7279 .rep_in45 (2'b0),
7280 .rep_in46 (2'b0),
7281 .rep_in47 (2'b0),
7282 .rep_in48 (2'b0),
7283 .rep_in49 (2'b0),
7284 .rep_in50 (2'b0),
7285 .rep_in51 (2'b0),
7286 .rep_in52 (2'b0),
7287 .rep_in53 (2'b0),
7288 .rep_in54 (2'b0),
7289 .rep_in55 (2'b0),
7290 .rep_in56 (2'b0),
7291 .rep_in57 (2'b0),
7292 .rep_in58 (2'b0),
7293 .rep_in59 (2'b0),
7294 .rep_in60 (2'b0),
7295 .rep_in61 (2'b0),
7296 .rep_in62 ({misbuf_tag_hit_unqual_c2,misbuf_notdata_err_c2}),
7297 .rep_in63 ({tag_miss_unqual_c2,misbuf_tag_hit_unqual_c2})
7298 );
7299
7300
7301l2t_mrep4x6_dp mrep_for_dir
7302 (
7303 .rep_out0 ({mrep_for_dir0_unused[2:0],tagd_lkup_ic_addr_c4[17]}),
7304 .rep_out1 (tagd_lkup_ic_addr_c4[16:13]),
7305 .rep_out2 (tagd_lkup_ic_addr_c4[12:9]),
7306 .rep_out3 ({mrep_for_dir3_unused[2:0],tagd_lkup_dc_addr_c4[17]}),
7307 .rep_out4 (tagd_lkup_dc_addr_c4[16:13]),
7308 .rep_out5 (tagd_lkup_dc_addr_c4[12:9]),
7309 .rep_in0 ({3'b0,tagd_lkup_addr_c4[17]}),
7310 .rep_in1 (tagd_lkup_addr_c4[16:13]),
7311 .rep_in2 (tagd_lkup_addr_c4[12:9]),
7312 .rep_in3 ({3'b0,tagd_lkup_addr_c4[17]}),
7313 .rep_in4 (tagd_lkup_addr_c4[16:13]),
7314 .rep_in5 (tagd_lkup_addr_c4[12:9])
7315 );
7316
7317////////////////////////////////////////////////////////////////////////////
7318//
7319// MBIST CONTROLLERS
7320//
7321////////////////////////////////////////////////////////////////////////////
7322
7323l2t_mb2_ctl mb2_control
7324 (
7325 .mb2_l2t_run (l2t_mb2_run),
7326// .mb2_l2t_cambist (mb2_l2t_cambist),
7327 .mb2_l2t_addr (l2t_mb2_addr[4:0]),
7328 .mb2_l2t_wdata (l2t_mb2_wdata[7:0]),
7329 .mb2_l2t_mbtag_wr_en (l2t_mb2_mbtag_wr_en),
7330 .mb2_l2t_mbtag_rd_en (l2t_mb2_mbtag_rd_en),
7331 .mb2_l2t_mbtag_lookup_en (l2t_mb2_mbtag_lookup_en),
7332 .mb2_l2t_wk1_cam_init (mb2_l2t_wk1_cam_init),
7333 .mb2_l2t_wk1_cam_shift (mb2_l2t_wk1_cam_shift),
7334 .cam_mb2_cam_fail ({rdma_mbist_cam_hit,wb_mbist_cam_hit,
7335 fb_mbist_cam_hit,mb_mbist_cam_hit}),
7336 .mb2_l2t_fbtag_wr_en (l2t_mb2_fbtag_wr_en),
7337 .mb2_l2t_fbtag_rd_en (l2t_mb2_fbtag_rd_en),
7338 .mb2_l2t_fbtag_lookup_en (l2t_mb2_fbtag_lookup_en),
7339 .mb2_l2t_wbtag_wr_en (l2t_mb2_wbtag_wr_en),
7340 .mb2_l2t_wbtag_rd_en (l2t_mb2_wbtag_rd_en),
7341 .mb2_l2t_wbtag_lookup_en (l2t_mb2_wbtag_lookup_en),
7342 .mb2_l2t_rdmatag_wr_en (l2t_mb2_rdmatag_wr_en),
7343 .mb2_l2t_rdmatag_rd_en (l2t_mb2_rdmatag_rd_en),
7344 .mb2_l2t_rdmatag_lookup_en (l2t_mb2_rdmatag_lookup_en),
7345 .mb2_l2t_mbdata_wr_en (l2t_mb2_mbdata_wr_en),
7346 .mb2_l2t_mbdata_rd_en (l2t_mb2_mbdata_rd_en),
7347 .cam_mb2_rw_fail (cam_mb2_rw_fail),
7348 .mb2_cmp_sel (mbdata_cmp_sel[3:0]),
7349 .mbdata_mb2_rw_fail (mbdata_fail),
7350 .mb2_l2t_iqarray_wr_en (l2t_mb2_iqarray_wr_en),
7351 .mb2_l2t_iqarray_rd_en (l2t_mb2_iqarray_rd_en),
7352 .iqarray_mb2_rw_fail (iqu_fail_reg),
7353 .l2t_mb2_done (l2t_tcu_mbist2_done),
7354 .l2t_mb2_fail (l2t_tcu_mbist2_fail),
7355 .mbist_cam_sel (mbist_cam_sel[3:0]),
7356 .scan_in(tcu_l2t_mbist_scan_in1),
7357 .scan_out(tcu_l2t_mbist_scan_in2),
7358 .l2clk (l2clk),
7359 .tcu_pce_ov (tcu_pce_ov),
7360 .tcu_aclk (tcu_aclk),
7361 .tcu_bclk (tcu_bclk),
7362 .tcu_scan_en (tcu_scan_en),
7363 .tcu_clk_stop (1'b0),
7364 .mbist_start (mbist_start_mb2),
7365 .mbist_user_mode (tcu_mbist_user_mode),
7366 .mbist_bisi_mode (tcu_mbist_bisi_en)
7367 );
7368
7369
7370l2t_mb0_ctl mb0 (
7371 .mb0_l2t_run (l2t_mb0_run),
7372 .mb0_l2t_cambist (mb0_l2t_cambist),
7373 .mb0_l2t_addr (l2t_mb0_addr[5:0]),
7374 .mb0_l2t_lookup_wdata (l2t_mb0_lookup_wdata[15:0]),
7375 .mb0_l2t_icrow_wr_en (l2t_mb0_icrow_wr_en),
7376 .mb0_l2t_icrow_rd_en (l2t_mb0_icrow_rd_en),
7377 .mb0_l2t_icrow_lookup_en (l2t_mb0_icrow_lookup_en[3:0]),
7378 .mb0_l2t_icrow_row_en (l2t_mb0_icrow_row_en[1:0]),
7379 .mb0_l2t_icrow_panel_en (l2t_mb0_icrow_panel_en[3:0]),
7380 .mb0_l2t_mask (l2t_mb0_mask[7:0]),
7381 .mb0_l2t_dcrow_wr_en (l2t_mb0_dcrow_wr_en),
7382 .mb0_l2t_dcrow_rd_en (l2t_mb0_dcrow_rd_en),
7383 .mb0_l2t_dcrow_lookup_en (l2t_mb0_dcrow_lookup_en[3:0]),
7384 .mb0_l2t_dcrow_row_en (l2t_mb0_dcrow_row_en[1:0]),
7385 .mb0_l2t_dcrow_panel_en (l2t_mb0_dcrow_panel_en[3:0]),
7386 .mb0_l2t_oqarray_wr_en (l2t_mb0_oqarray_wr_en),
7387 .mb0_l2t_oqarray_rd_en (l2t_mb0_oqarray_rd_en),
7388 .mb0_l2t_done (l2t_tcu_mbist0_done),
7389 .mb0_l2t_fail (l2t_tcu_mbist0_fail),
7390 .mb0_l2t_cmpsel (mbist_oqarray_sel[3:0]),
7391 .mb0_l2t_mbist_write_data (mb0_l2t_mbist_write_data[7:0]),
7392 .ic_cam_fail (ic_cam_fail[1:0]),
7393 .dc_cam_fail (dc_cam_fail[1:0]),
7394 .dir_dc_rw_fail (dc_cam_read_fail[3:0]),
7395 .dir_ic_rw_fail (ic_cam_read_fail[3:0]),
7396 .oqarray_rw_fail (oqarray_rw_fail),
7397 .scan_in(tcu_l2t_mbist_scan_in2),
7398 .scan_out(l2t_tcu_mbist_scan_out),
7399 .l2clk (l2clk),
7400 .tcu_pce_ov (tcu_pce_ov),
7401 .tcu_clk_stop (1'b0),
7402 .tcu_aclk (tcu_aclk),
7403 .tcu_bclk (tcu_bclk),
7404 .tcu_scan_en (tcu_scan_en),
7405 .mbist_start (mbist_start_mb0),
7406 .mbist_user_mode (tcu_mbist_user_mode),
7407 .mbist_bisi_mode (tcu_mbist_bisi_en)
7408 );
7409
7410
7411//////////////////////////////////////////////////////////////////////////
7412// EFU tag array related header logic
7413//////////////////////////////////////////////////////////////////////////
7414
7415l2t_taghdr_ctl l2tag_sram_hdr
7416 (
7417 .efu_hdr_write_data (efu_l2t_fuse_data),
7418 .efu_hdr_xfer_en (efu_l2t_fuse_xfer_en),
7419 .efu_hdr_clr (efu_l2t_fuse_clr),
7420 .cmp_io_sync_en (cmp_io_sync_en),
7421 .io_cmp_sync_en (io_cmp_sync_en),
7422 .sram_hdr_read_data ({1'b0,tag_fuse_read_data[5:0]}),
7423 .scan_in(l2tag_sram_hdr_scanin),
7424 .scan_out(l2tag_sram_hdr_scanout),
7425 .l2clk (l2clk),
7426 .tcu_pce_ov (tcu_pce_ov),
7427 .tcu_aclk (tcu_aclk),
7428 .tcu_bclk (tcu_bclk),
7429 .tcu_scan_en (tcu_scan_en),
7430 .tcu_clk_stop (1'b0),
7431 .hdr_efu_read_data (l2t_efu_fuse_data),
7432 .hdr_efu_xfer_en (l2t_efu_fuse_xfer_en),
7433 .hdr_sram_rvalue (l2t_tag_rvalue[6:0]),
7434 .hdr_sram_rid (l2t_tag_rid[3:0]),
7435 .hdr_sram_wr_en (l2t_tag_wr_en),
7436 .hdr_sram_red_clr (l2t_tag_fuse_clr)
7437 );
7438
7439
7440// fixscan start:
7441assign l2t_clk_header_scanin = scan_in ;
7442assign vuad_scanin = l2t_clk_header_scanout ;
7443assign vuadpm_scanin = vuad_scanout ;
7444assign vlddir_scanin = vuadpm_scanout ;
7445assign usaloc_scanin = vlddir_scanout ;
7446assign tag_scanin = usaloc_scanout ;
7447assign tagl_1_scanin = tag_scanout ;
7448assign tagl_2_scanin = tagl_1_scanout ;
7449assign tagdp_scanin = tagl_2_scanout ;
7450assign tagd_scanin = tagdp_scanout ;
7451assign dmologic_scanin = tagd_scanout ;
7452assign tagctl_scanin = dmologic_scanout ;
7453assign misbuf_scanin = tagctl_scanout ;
7454assign mbdata_scanin = misbuf_scanout ;
7455assign mbtag_scanin = mbdata_scanout ;
7456assign filbuf_scanin = mbtag_scanout ;
7457assign fbtag_scanin = filbuf_scanout ;
7458assign arbdat_scanin = fbtag_scanout ;
7459assign arbadr_scanin = arbdat_scanout ;
7460assign arb_scanin = arbadr_scanout ;
7461assign arbdec_scanin = arb_scanout ;
7462assign wbuf_scanin = arbdec_scanout ;
7463assign wbtag_scanin = wbuf_scanout ;
7464assign ique_scanin = wbtag_scanout ;
7465assign iqu_scanin = ique_scanout ;
7466assign iqarray_scanin = iqu_scanout ;
7467assign oqu_scanin = iqarray_scanout ;
7468assign oqarray_scanin = oqu_scanout ;
7469assign oque_scanin = oqarray_scanout ;
7470assign dirvec_scanin = oque_scanout ;
7471assign deccck_scanin = dirvec_scanout ;
7472assign decc_scanin = deccck_scanout ;
7473assign csr_scanin = decc_scanout ;
7474assign csreg_scanin = csr_scanout ;
7475assign snp_scanin = csreg_scanout ;
7476assign snpd_scanin = snp_scanout ;
7477assign evctag_scanin = snpd_scanout ;
7478assign rdmatag_scanin = evctag_scanout ;
7479assign rdmat_scanin = rdmatag_scanout ;
7480assign dirrep_scanin = rdmat_scanout ;
7481assign subarray_0_scanin = dirrep_scanout ;
7482assign subarray_1_scanin = subarray_0_scanout ;
7483assign subarray_2_scanin = subarray_1_scanout ;
7484assign subarray_3_scanin = subarray_2_scanout ;
7485assign subarray_8_scanin = subarray_3_scanout ;
7486assign subarray_9_scanin = subarray_8_scanout ;
7487assign subarray_10_scanin = subarray_9_scanout ;
7488assign subarray_11_scanin = subarray_10_scanout ;
7489assign ic_row0_scanin = subarray_11_scanout ;
7490assign out_col0_scanin = ic_row0_scanout ;
7491assign out_col1_scanin = out_col0_scanout ;
7492assign out_col2_scanin = out_col1_scanout ;
7493assign out_col3_scanin = out_col2_scanout ;
7494assign ic_row2_scanin = out_col3_scanout ;
7495assign dc_row0_scanin = ic_row2_scanout ;
7496assign dc_out_col0_scanin = dc_row0_scanout ;
7497assign dc_out_col1_scanin = dc_out_col0_scanout ;
7498assign dc_out_col2_scanin = dc_out_col1_scanout ;
7499assign dc_out_col3_scanin = dc_out_col2_scanout ;
7500assign ic_row0_ctl_scanin = dc_out_col3_scanout ;
7501assign ic_row2_ctl_scanin = ic_row0_ctl_scanout ;
7502assign dc_row0_ctl_scanin = ic_row2_ctl_scanout ;
7503assign dc_row2_ctl_scanin = dc_row0_ctl_scanout ;
7504assign dc_row2_scanin = dc_row2_ctl_scanout ;
7505assign left_ffrptr_scanin = dc_row2_scanout ;
7506assign right_ffrptr_scanin = left_ffrptr_scanout ;
7507assign l2tag_sram_hdr_scanin = right_ffrptr_scanout ;
7508assign scan_out = l2tag_sram_hdr_scanout ;
7509// fixscan end:
7510endmodule
7511
Full OpenSPARC design & verification tarball including full HDL.