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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_arb_ctl.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_arb_ctl.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
1017// Description:
1018// This module contains the following
1019// // Mux sel logic for arbitration.
1020// // select logic for advancing IQ/SNP/MB/FB pointers.
1021// // mux selects for the dir CAM address muxes in arbadr.
1022// // Mux selects for the error addresses
1023// // Instruction valid C1 and C2
1024//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
1025
1026////////////////////////////////////////////////////////////////////////
1027// Local header file includes / local define
1028////////////////////////////////////////////////////////////////////////
1029
1030module l2t_arb_ctl (
1031 tcu_pce_ov,
1032 tcu_aclk,
1033 tcu_bclk,
1034 tcu_scan_en,
1035 arbadr_ncu_l2t_pm_n_dist,
1036 arbadr_2bnk_true_enbld_dist,
1037 arbadr_4bnk_true_enbld_dist,
1038 arbadr_arbdp_addr87_c2,
1039 ncu_spc0_core_enable_status,
1040 ncu_spc1_core_enable_status,
1041 ncu_spc2_core_enable_status,
1042 ncu_spc3_core_enable_status,
1043 ncu_spc4_core_enable_status,
1044 ncu_spc5_core_enable_status,
1045 ncu_spc6_core_enable_status,
1046 ncu_spc7_core_enable_status,
1047 oqu_arb_full_px2,
1048 misbuf_arb_vld_px1,
1049 misbuf_arb_cnt28_px2_prev,
1050 misbuf_arb_snp_cnt8_px1,
1051 wbuf_arb_full_px1,
1052 misbuf_arb_hit_c3,
1053 arb_misbuf_inval_inst_c2,
1054 filbuf_arb_vld_px1,
1055 iqu_iq_arb_vld_px2,
1056 iqu_iq_arb_vld_px2_v1,
1057 ique_iq_arb_vbit_px2,
1058 ique_iq_arb_atm_px2,
1059 ique_iq_arb_csr_px2,
1060 ique_iq_arb_st_px2,
1061 ique_arb_pf_ice_px2,
1062 snp_snpq_arb_vld_px1,
1063 arb_l2drpt_waysel_gate_c1,
1064 tag_deccck_data_sel_c8,
1065 tag_rdma_vld_px1,
1066 tag_data_ecc_active_c3,
1067 tag_decc_tag_acc_en_px2,
1068 misbuf_nondep_fbhit_c3,
1069 misbuf_hit_st_dep_zero,
1070 tag_hit_unqual_c3,
1071 mbist_arb_l2d_en,
1072 bist_vuad_rd_en_px1,
1073 mbist_run,
1074 arbdec_arbdp_inst_fb_c2,
1075 arbadr_arbdp_ioaddr_c1_39to37,
1076 arbadr_arbdp_ioaddr_c1_35to33,
1077 arbdec_size_field_c8,
1078 arbdat_word_lower_cmp_c8,
1079 arbdat_word_upper_cmp_c8,
1080 arbadr_addr2_c8,
1081 arbdec_arbdp_inst_size_c7,
1082 arbadr_arbdp_diag_wr_way_c2,
1083 arbdec_arbdp_inst_way_c1,
1084 arbdec_arbdp_tecc_c1,
1085 filbuf_arbdp_way_px2,
1086 filbuf_tag_hit_frm_mb_c2,
1087 arbdec_arbdp_inst_mb_c2,
1088 arbdec_arbdp_inst_fb_c1,
1089 arbdec_arbdp_inst_dep_c2,
1090 tag_hit_l2orfb_c3,
1091 tagdp_arb_par_err_c3,
1092 tagdp_invalid_evict_c3,
1093 arbdec_arbdp_inst_nc_c3,
1094 arbdec_arbdp_cpuid_c2,
1095 arbdec_arbdp_l1way_c3,
1096 arbadr_arbdp_addr11to4_c3,
1097 arbadr_arbdp_new_addr5to4_px2,
1098 arbadr_arbdp_addr5to4_c1,
1099 arbadr_arbdp_addr5to4_c3,
1100 arbdec_arbdp_inst_mb_c3,
1101 arbdec_arbdp_inst_tecc_c3,
1102 arbdec_arbdp_inst_bufidhi_c1,
1103 arbdec_arbdp_inst_bufid1_c1,
1104 arbdec_arbdp_inst_mb_c1,
1105 arbdec_arbdp_evict_c1,
1106 arbdec_arbdp_inst_rqtyp_c1,
1107 arbdec_arbdp_inst_rsvd_c1,
1108 arbdec_arbdp_inst_nc_c1,
1109 arbdec_arbdp_inst_ctrue_c1,
1110 arbdec_arbdp_inst_size_c1,
1111 arbadr_arbdp_addr_start_c2,
1112 arbdec_arbdp_rdma_inst_c2,
1113 arbdec_arbdp_inst_bufidlo_c2,
1114 arbdec_arbdp_inst_rqtyp_c2,
1115 arbdec_arbdp_inst_rqtyp_c6,
1116 arbadr_arbaddr_addr22_c2,
1117 bist_acc_vd_px1,
1118 l2t_mb2_mbtag_lookup_en,
1119 l2t_mb2_fbtag_lookup_en,
1120 l2t_mb2_wbtag_lookup_en,
1121 l2t_mb2_rdmatag_lookup_en,
1122 l2t_mb2_run,
1123 mbist_lookupen,
1124 mbist_arb_l2t_write,
1125 arb_decdp_mmuld_inst_c6,
1126 arb_acc_vd_c2,
1127 arb_acc_ua_c2,
1128 csr_l2_bypass_mode_on,
1129 l2clk,
1130 io_cmp_sync_en,
1131 wmr_l,
1132 scan_in,
1133 usaloc_ua_ce_c2,
1134 vlddir_vd_ce_c2,
1135 misbuf_vuad_ce_instr_c2,
1136 arb_cpuid_c5,
1137 scan_out,
1138 arb_bs_or_bis_inst_c2,
1139 arb_mux1_mbsel_px2,
1140 arb_arbdat_mux2_snpsel_px2,
1141 arb_arbadr_mux2_snpsel_px2,
1142 arb_arbdec_mux2_snpsel_px2,
1143 arb_arbdat_mux3_bufsel_px2,
1144 arb_arbdec_mux3_bufsel_px2,
1145 arb_mux3_bufsel_px1,
1146 arb_arbadr_mux4_c1sel_px2,
1147 arb_arbdat_mux4_c1sel_px2,
1148 arb_arbdec_mux4_c1sel_px2,
1149 arb_data_ecc_idx_en,
1150 arb_data_ecc_idx_reset,
1151 arb_sel_tecc_addr_px2,
1152 arb_sel_deccck_addr_px2,
1153 arb_sel_diag_addr_px2,
1154 arb_sel_diag_tag_addr_px2,
1155 arb_inc_tag_ecc_cnt_c3_n,
1156 arb_sel_lkup_stalled_tag_px2,
1157 arb_bist_or_diag_acc_c1,
1158 arb_sel_deccck_or_bist_idx,
1159 arb_sel_vuad_bist_px2,
1160 arb_misbuf_inst_vld_c2,
1161 arb_inst_vld_c2,
1162 arb_tag_inst_vld_c2,
1163 arb_wbuf_inst_vld_c2,
1164 arb_imiss_hit_c10,
1165 arb_imiss_hit_c4,
1166 arb_evict_c3,
1167 arb_evict_c4,
1168 arb_sel_c2_stall_idx_c1,
1169 arb_vuad_acc_px2,
1170 arb_upper_four_byte_access_c1,
1171 arb_lower_four_byte_access_c1,
1172 arb_tag_wr_px2,
1173 arb_vuad_idx2_sel_px2_n,
1174 arb_mb_camen_px2,
1175 arb_filbuf_fbsel_c1,
1176 arb_misbuf_mbsel_c1,
1177 arb_iqsel_px2,
1178 arb_iqsel_px2_v1,
1179 arb_evict_vld_c2,
1180 arb_ic_evict_c4,
1181 arb_dc_evict_c4,
1182 arb_inst_diag_c1,
1183 arb_inst_vld_c1,
1184 arb_inval_inst_vld_c3,
1185 arb_l2d_fbrd_c3,
1186 arb_misbuf_ctrue_c9,
1187 arb_misbuf_cas1_hit_c8,
1188 arb_decc_data_sel_c9,
1189 arb_tecc_way_c2,
1190 arb_l2tag_vld_c4,
1191 arb_dword_mask_c8,
1192 arb_fill_vld_c2,
1193 arb_imiss_vld_c2,
1194 arb_pf_ice_inst_c2,
1195 arb_pf_ice_inst_c7,
1196 arb_normal_tagacc_c2,
1197 arb_tagd_tecc_c2,
1198 arb_dir_vld_c3_l,
1199 arb_dc_rd_en_c3,
1200 arb_ic_rd_en_c3,
1201 arb_dc_wr_en_c3,
1202 arb_ic_wr_en_c3,
1203 arb_dir_panel_dcd_c3,
1204 arb_dir_panel_icd_c3,
1205 arb_lkup_bank_ena_dcd_c3,
1206 arb_lkup_bank_ena_icd_c3,
1207 arb_inval_mask_dcd_c3,
1208 arb_inval_mask_icd_c3,
1209 arb_wr_dc_dir_entry_c3,
1210 arb_wr_ic_dir_entry_c3,
1211 arb_dc_ic_rd_bit_4,
1212 arb_dir_addr_c9,
1213 arb_dir_wr_en_c4,
1214 arb_csr_wr_en_c7,
1215 arb_csr_rd_en_c7,
1216 arb_evict_c5,
1217 arb_waysel_gate_c2,
1218 arb_data_diag_st_c2,
1219 arb_inval_inst_c2,
1220 arb_decdp_ld64_inst_c1,
1221 arb_waysel_inst_vld_c2,
1222 arb_inst_vld_c2_prev,
1223 arb_rdwr_inst_vld_c2,
1224 arb_ic_inval_vld_c7,
1225 arb_dc_inval_vld_c7,
1226 arb_inst_l2data_vld_c6,
1227 arb_csr_wr_en_c3,
1228 arb_csr_rd_en_c3,
1229 arb_diag_complete_c3,
1230 arb_tag_pst_with_ctrue_c1,
1231 arb_csr_st_c2,
1232 arb_misbuf_hit_off_c1,
1233 arb_pst_ctrue_en_c8,
1234 arb_evict_tecc_vld_c2,
1235 arb_filbuf_hit_off_c1,
1236 arb_wbuf_hit_off_c1,
1237 arb_inst_l2vuad_vld_c6,
1238 arb_inst_l2tag_vld_c6,
1239 arb_snp_snpsel_px2,
1240 arb_decdp_tag_wr_c1,
1241 arb_decdp_pst_inst_c2,
1242 arb_decdp_fwd_req_c2,
1243 arb_decdp_swap_inst_c2,
1244 arb_decdp_imiss_inst_c2,
1245 arb_decdp_inst_int_c2,
1246 arb_decdp_inst_int_c1,
1247 arb_decdp_ld64_inst_c2,
1248 arb_decdp_bis_inst_c3,
1249 arb_decdp_rmo_st_c3,
1250 arb_decdp_strst_inst_c2,
1251 arb_decdp_wr8_inst_c2,
1252 arb_decdp_wr64_inst_c2,
1253 arb_decdp_st_inst_c2,
1254 arb_decdp_st_inst_c3,
1255 arb_decdp_st_with_ctrue_c2,
1256 arb_decdp_ld_inst_c2,
1257 arb_arbdp_dword_st_c1,
1258 arb_arbdp_pst_with_ctrue_c2,
1259 arb_decdp_cas1_inst_c2,
1260 arb_decdp_cas2_inst_c2,
1261 arb_decdp_cas2_from_mb_c2,
1262 decdp_cas2_from_mb_ctrue_c1,
1263 arb_inst_l2vuad_vld_c3,
1264 arb_decdp_pf_inst_c5,
1265 arb_decdp_strld_inst_c6,
1266 arb_decdp_atm_inst_c6,
1267 arb_store_err_c8,
1268 arb_arbdp_tecc_inst_mb_c8,
1269 arb_tagd_perr_vld_c2,
1270 arb_arbdp_tag_pst_no_ctrue_c2,
1271 arb_arbdp_misbuf_pst_no_ctrue_c2,
1272 arb_arbdp_vuadctl_pst_no_ctrue_c2,
1273 arb_tecc_c2,
1274 arb_vuadctl_no_bypass_px2,
1275 arb_sel_way_px2,
1276 arb_diag_or_tecc_write_px2,
1277 arb_tag_rd_px2,
1278 arb_tag_way_px2,
1279 arb_mux1_mbsel_px1,
1280 arb_wr8_inst_no_ctrue_c1,
1281 arb_vuad_ce_err_c2,
1282 usaloc_vlddir_arb_vuad_ce_err_c3,
1283 tagctl_arb_vuad_ce_err_c3,
1284 arb_oqu_swap_cas2_req_c2);
1285wire pce_ov;
1286wire stop;
1287wire siclk;
1288wire soclk;
1289wire se;
1290wire spares_scanin;
1291wire spares_scanout;
1292wire l1clk;
1293wire dbginit_l;
1294wire dbb_rst_l;
1295wire reset_flop_scanin;
1296wire reset_flop_scanout;
1297wire ff_gate_off_prim_req_c1_scanin;
1298wire ff_gate_off_prim_req_c1_scanout;
1299wire reset_for_pf_ice_c8;
1300wire reset_for_pf_ice_c3;
1301wire decdp_pf_ice_inst_c3;
1302wire ff_reset_for_pf_ice_staging_scanin;
1303wire ff_reset_for_pf_ice_staging_scanout;
1304wire reset_for_pf_ice_c4;
1305wire reset_for_pf_ice_c5;
1306wire reset_for_pf_ice_c52;
1307wire reset_for_pf_ice_c6;
1308wire reset_for_pf_ice_c7;
1309wire ff_gate_off_prim_req_state_scanin;
1310wire ff_gate_off_prim_req_state_scanout;
1311wire l2_bypass_mode_on_d1;
1312wire ff_l2_bypass_mode_on_d1_scanin;
1313wire ff_l2_bypass_mode_on_d1_scanout;
1314wire ff_mbf_valid_px2_scanin;
1315wire ff_mbf_valid_px2_scanout;
1316wire ff_mbf_valid_px2_1_scanin;
1317wire ff_mbf_valid_px2_1_scanout;
1318wire ff_fbf_valid_px2_1_scanin;
1319wire ff_fbf_valid_px2_1_scanout;
1320wire ff_snp_valid_px2_scanin;
1321wire ff_snp_valid_px2_scanout;
1322wire ff_snp_valid_px2_1_scanin;
1323wire ff_snp_valid_px2_1_scanout;
1324wire ff_mux3_bufsel_px2_scanin;
1325wire ff_mux3_bufsel_px2_scanout;
1326wire arb_mux3_bufsel_px2_unbuff;
1327wire ff_atm_instr_c1_scanin;
1328wire ff_atm_instr_c1_scanout;
1329wire arb_stall_c2_clone_1;
1330wire arb_stall_unqual_c2_clone_1;
1331wire arb_inst_vld_c1_1_cloned;
1332wire ff_arb_stall_c1_cloned_scanin;
1333wire ff_arb_stall_c1_cloned_scanout;
1334wire ff_arb_inst_vld_c1_1_clone_scanin;
1335wire ff_arb_inst_vld_c1_1_clone_scanout;
1336wire tag_data_ecc_active_c3_inverted;
1337wire tcu_scan_en_inv;
1338wire data_ecc_active_c4_n;
1339wire arb_sel_deccck_addr_px2_n;
1340wire ff_data_ecc_active_c4_dup_scanin;
1341wire ff_data_ecc_active_c4_dup_scanout;
1342wire data_ecc_active_c4_noninv;
1343wire ff_inc_tag_ecc_cnt_c3_dup_scanin;
1344wire ff_inc_tag_ecc_cnt_c3_dup_scanout;
1345wire inc_tag_ecc_cnt_c3_1_n;
1346wire inc_tag_ecc_cnt_c3_1_v2;
1347wire ff_tecc_c2_scanin;
1348wire ff_tecc_c2_scanout;
1349wire tecc_c2;
1350wire ff_arb_tecc_c2_c3_scanin;
1351wire ff_arb_tecc_c2_c3_scanout;
1352wire ff_data_ecc_active_c4_scanin;
1353wire ff_data_ecc_active_c4_scanout;
1354wire ff_bist_vuad_rd_en_px1_scanin;
1355wire ff_bist_vuad_rd_en_px1_scanout;
1356wire mbist_run_r1;
1357wire ff_bist_enable_c1_scanin;
1358wire ff_bist_enable_c1_scanout;
1359wire ff_bist_enable_c2_scanin;
1360wire ff_bist_enable_c2_scanout;
1361wire ff_bist_acc_vd_px2_scanin;
1362wire ff_bist_acc_vd_px2_scanout;
1363wire ff_bist_acc_vd_c1_scanin;
1364wire ff_bist_acc_vd_c1_scanout;
1365wire ff_bist_acc_vd_c2_scanin;
1366wire ff_bist_acc_vd_c2_scanout;
1367wire ff_mbist_arb_l2d_en_d1_scanin;
1368wire ff_mbist_arb_l2d_en_d1_scanout;
1369wire mbist_arb_l2d_en_d1;
1370wire ff_arb_tag_acc_c1_scanin;
1371wire ff_arb_tag_acc_c1_scanout;
1372wire ff_sp_tag_access_c1_scanin;
1373wire ff_sp_tag_access_c1_scanout;
1374wire ff_normal_tagacc_c2_scanin;
1375wire ff_normal_tagacc_c2_scanout;
1376wire ff_l2t_mb2_run_r1_scanin;
1377wire ff_l2t_mb2_run_r1_scanout;
1378wire l2t_mb2_run_r1;
1379wire l2t_mb2_mbtag_lookup_en_r1;
1380wire l2t_mb2_mbtag_lookup_en_r2;
1381wire ff_mbfull_px2_scanin;
1382wire ff_mbfull_px2_scanout;
1383wire arb_iqsel_px2_phase1;
1384wire arb_iqsel_px2_v1_n;
1385wire ff_mbsel_c1_scanin;
1386wire ff_mbsel_c1_scanout;
1387wire ff_fbsel_c1_scanin;
1388wire ff_fbsel_c1_scanout;
1389wire ff_snpsel_c1_scanin;
1390wire ff_snpsel_c1_scanout;
1391wire ff_snpsel_c2_scanin;
1392wire ff_snpsel_c2_scanout;
1393wire ff_snpsel_c3_scanin;
1394wire ff_snpsel_c3_scanout;
1395wire ff_arb_evict_c3_scanin;
1396wire ff_arb_evict_c3_scanout;
1397wire arb_vuad_ce_err_c3;
1398wire ff_arb_evict_c4_scanin;
1399wire ff_arb_evict_c4_scanout;
1400wire ff_arb_evict_c5_scanin;
1401wire ff_arb_evict_c5_scanout;
1402wire ff_imiss_inst_c3_scanin;
1403wire ff_imiss_inst_c3_scanout;
1404wire ff_arb_imiss_hit_c4_scanin;
1405wire ff_arb_imiss_hit_c4_scanout;
1406wire ff_arb_imiss_hit_c5_scanin;
1407wire ff_arb_imiss_hit_c5_scanout;
1408wire ff_arb_imiss_hit_c52_scanin;
1409wire ff_arb_imiss_hit_c52_scanout;
1410wire arb_imiss_hit_c52;
1411wire ff_arb_imiss_hit_c6_scanin;
1412wire ff_arb_imiss_hit_c6_scanout;
1413wire ff_arb_imiss_hit_c7_scanin;
1414wire ff_arb_imiss_hit_c7_scanout;
1415wire ff_arb_imiss_hit_c8_scanin;
1416wire ff_arb_imiss_hit_c8_scanout;
1417wire ff_arb_imiss_hit_c9_scanin;
1418wire ff_arb_imiss_hit_c9_scanout;
1419wire ff_arb_imiss_hit_c10_scanin;
1420wire ff_arb_imiss_hit_c10_scanout;
1421wire ff_arb_inst_diag_c2_scanin;
1422wire ff_arb_inst_diag_c2_scanout;
1423wire arb_inst_diag_c2;
1424wire decdp_inst_int_or_inval_c2;
1425wire ff_arb_inst_csr_c1_scanin;
1426wire ff_arb_inst_csr_c1_scanout;
1427wire ff_arb_inst_l2data_c2_scanin;
1428wire ff_arb_inst_l2data_c2_scanout;
1429wire ff_inst_l2data_vld_c3_scanin;
1430wire ff_inst_l2data_vld_c3_scanout;
1431wire ff_inst_l2data_vld_c4_scanin;
1432wire ff_inst_l2data_vld_c4_scanout;
1433wire ff_inst_l2data_vld_c5_scanin;
1434wire ff_inst_l2data_vld_c5_scanout;
1435wire ff_inst_l2data_vld_c52_scanin;
1436wire ff_inst_l2data_vld_c52_scanout;
1437wire ff_inst_l2data_vld_c6_scanin;
1438wire ff_inst_l2data_vld_c6_scanout;
1439wire ff_arb_csr_wr_en_c3_scanin;
1440wire ff_arb_csr_wr_en_c3_scanout;
1441wire ff_arb_csr_wr_en_c3_1_scanin;
1442wire ff_arb_csr_wr_en_c3_1_scanout;
1443wire ff_arb_csr_wr_en_c4_scanin;
1444wire ff_arb_csr_wr_en_c4_scanout;
1445wire ff_arb_csr_wr_en_c5_scanin;
1446wire ff_arb_csr_wr_en_c5_scanout;
1447wire ff_arb_csr_wr_en_c52_scanin;
1448wire ff_arb_csr_wr_en_c52_scanout;
1449wire ff_arb_csr_wr_en_c6_scanin;
1450wire ff_arb_csr_wr_en_c6_scanout;
1451wire ff_arb_csr_wr_en_c7_scanin;
1452wire ff_arb_csr_wr_en_c7_scanout;
1453wire ff_arb_csr_wr_en_c8_scanin;
1454wire ff_arb_csr_wr_en_c8_scanout;
1455wire ff_arb_csr_rd_en_c3_scanin;
1456wire ff_arb_csr_rd_en_c3_scanout;
1457wire ff_arb_csr_rd_en_c4_scanin;
1458wire ff_arb_csr_rd_en_c4_scanout;
1459wire ff_arb_csr_rd_en_c5_scanin;
1460wire ff_arb_csr_rd_en_c5_scanout;
1461wire ff_arb_csr_rd_en_c52_scanin;
1462wire ff_arb_csr_rd_en_c52_scanout;
1463wire ff_arb_csr_rd_en_c6_scanin;
1464wire ff_arb_csr_rd_en_c6_scanout;
1465wire ff_arb_csr_rd_en_c7_scanin;
1466wire ff_arb_csr_rd_en_c7_scanout;
1467wire ff_arb_inst_l2tag_c2_scanin;
1468wire ff_arb_inst_l2tag_c2_scanout;
1469wire ff_arb_inst_l2tag_c2_1_scanin;
1470wire ff_arb_inst_l2tag_c2_1_scanout;
1471wire ff_inst_l2tag_vld_c3_scanin;
1472wire ff_inst_l2tag_vld_c3_scanout;
1473wire ff_inst_l2tag_vld_c4_scanin;
1474wire ff_inst_l2tag_vld_c4_scanout;
1475wire ff_inst_l2tag_vld_c5_scanin;
1476wire ff_inst_l2tag_vld_c5_scanout;
1477wire ff_inst_l2tag_vld_c52_scanin;
1478wire ff_inst_l2tag_vld_c52_scanout;
1479wire ff_inst_l2tag_vld_c6_scanin;
1480wire ff_inst_l2tag_vld_c6_scanout;
1481wire ff_arb_inst_l2vuad_c2_scanin;
1482wire ff_arb_inst_l2vuad_c2_scanout;
1483wire ff_inst_l2vuad_vld_c3_scanin;
1484wire ff_inst_l2vuad_vld_c3_scanout;
1485wire ff_inst_l2vuad_vld_c4_scanin;
1486wire ff_inst_l2vuad_vld_c4_scanout;
1487wire ff_inst_l2vuad_vld_c5_scanin;
1488wire ff_inst_l2vuad_vld_c5_scanout;
1489wire ff_inst_l2vuad_vld_c52_scanin;
1490wire ff_inst_l2vuad_vld_c52_scanout;
1491wire ff_inst_l2vuad_vld_c6_scanin;
1492wire ff_inst_l2vuad_vld_c6_scanout;
1493wire ff_deccck_data_sel_c9_scanin;
1494wire ff_deccck_data_sel_c9_scanout;
1495wire ff_lower_cas_c9_scanin;
1496wire ff_lower_cas_c9_scanout;
1497wire ff_upper_cas_c9_scanin;
1498wire ff_upper_cas_c9_scanout;
1499wire ff_word_lower_cmp_c9_scanin;
1500wire ff_word_lower_cmp_c9_scanout;
1501wire ff_word_upper_cmp_c9_scanin;
1502wire ff_word_upper_cmp_c9_scanout;
1503wire ff_tecc_inst_c2_scanin;
1504wire ff_tecc_inst_c2_scanout;
1505wire ff_inc_tag_ecc_cnt_c3_scanin;
1506wire ff_inc_tag_ecc_cnt_c3_scanout;
1507wire ff_tag_ecc_fsm_count_scanin;
1508wire ff_tag_ecc_fsm_count_scanout;
1509wire ff_scrub_fsm_count_eq_6_px2_scanin;
1510wire ff_scrub_fsm_count_eq_6_px2_scanout;
1511wire ff_scrub_fsm_count_eq_1_px2_scanin;
1512wire ff_scrub_fsm_count_eq_1_px2_scanout;
1513wire ff_tecc_tag_acc_en_px2_scanin;
1514wire ff_tecc_tag_acc_en_px2_scanout;
1515wire ff_arb_tagd_tecc_c2_scanin;
1516wire ff_arb_tagd_tecc_c2_scanout;
1517wire ff_diag_or_tecc_acc_c1_scanin;
1518wire ff_diag_or_tecc_acc_c1_scanout;
1519wire arbdec_arbdp_inst_fb_c1_qual;
1520wire ff_hit_l2orfb_c4_scanin;
1521wire ff_hit_l2orfb_c4_scanout;
1522wire ff_hit_l2orfb_c5_scanin;
1523wire ff_hit_l2orfb_c5_scanout;
1524wire ff_hit_l2orfb_c52_scanin;
1525wire ff_hit_l2orfb_c52_scanout;
1526wire ff_hit_l2orfb_c6_scanin;
1527wire ff_hit_l2orfb_c6_scanout;
1528wire ff_hit_l2orfb_c7_scanin;
1529wire ff_hit_l2orfb_c7_scanout;
1530wire ff_hit_l2orfb_c8_scanin;
1531wire ff_hit_l2orfb_c8_scanout;
1532wire vuad_ce_err_c7;
1533wire ff_dword_mask_c8_scanin;
1534wire ff_dword_mask_c8_scanout;
1535wire ff_fbrd_c3_scanin;
1536wire ff_fbrd_c3_scanout;
1537wire ff_st_cam_en_c3_scanin;
1538wire ff_st_cam_en_c3_scanout;
1539wire arb_decdp_cas2_from_mb_ctrue_c2;
1540wire ff_sp_cam_en_c3_scanin;
1541wire ff_sp_cam_en_c3_scanout;
1542wire ff_arb_decdp_cas1_inst_c3_scanin;
1543wire ff_arb_decdp_cas1_inst_c3_scanout;
1544wire arb_decdp_cas1_inst_c3;
1545wire arb_decdp_swap_inst_c3;
1546wire arbdec_arbdp_rdma_inst_c3;
1547wire arb_decdp_ld_inst_c3;
1548wire arb_decdp_wr8_inst_c3;
1549wire arb_decdp_ld64_inst_c3;
1550wire arb_decdp_cas2_inst_c3;
1551wire enable_dc_cam;
1552wire misbuf_vuad_ce_instr_c3;
1553wire disable_dc_cam;
1554wire ff_enc_cam_addr_c4_scanin;
1555wire ff_enc_cam_addr_c4_scanout;
1556wire ff_vuad_ce_scanin;
1557wire ff_vuad_ce_scanout;
1558wire vuad_ce_err_c2_unqual;
1559wire vuad_ce_err_c3;
1560wire vuad_ce_err_c2;
1561wire ff_vuad_ce_err_c3_scanin;
1562wire ff_vuad_ce_err_c3_scanout;
1563wire vuad_ce_err_c4;
1564wire vuad_ce_err_c5;
1565wire vuad_ce_err_c52;
1566wire vuad_ce_err_c6;
1567wire ff_arbctl_inst_nc_c2_scanin;
1568wire ff_arbctl_inst_nc_c2_scanout;
1569wire arb_inst_nc_c2;
1570wire ff_ic_hitqual_cam_en_c3_scanin;
1571wire ff_ic_hitqual_cam_en_c3_scanout;
1572wire ff_ld_inst_c3_scanin;
1573wire ff_ld_inst_c3_scanout;
1574wire decdp_rmo_st_or_strst_c3;
1575wire ff_dc_inval_c3_scanin;
1576wire ff_dc_inval_c3_scanout;
1577wire ff_ic_inval_c3_scanin;
1578wire ff_ic_inval_c3_scanout;
1579wire ff_dc_inval_vld_c4_scanin;
1580wire ff_dc_inval_vld_c4_scanout;
1581wire ff_dc_inval_vld_c5_scanin;
1582wire ff_dc_inval_vld_c5_scanout;
1583wire ff_dc_inval_vld_c52_scanin;
1584wire ff_dc_inval_vld_c52_scanout;
1585wire ff_dc_inval_vld_c6_scanin;
1586wire ff_dc_inval_vld_c6_scanout;
1587wire ff_dc_inval_vld_c7_scanin;
1588wire ff_dc_inval_vld_c7_scanout;
1589wire ff_ic_inval_vld_c4_scanin;
1590wire ff_ic_inval_vld_c4_scanout;
1591wire ff_ic_inval_vld_c5_scanin;
1592wire ff_ic_inval_vld_c5_scanout;
1593wire ff_ic_inval_vld_c52_scanin;
1594wire ff_ic_inval_vld_c52_scanout;
1595wire ff_ic_inval_vld_c6_scanin;
1596wire ff_ic_inval_vld_c6_scanout;
1597wire ff_ic_inval_vld_c7_scanin;
1598wire ff_ic_inval_vld_c7_scanout;
1599wire ff_ic_inval_vld_c8_scanin;
1600wire ff_ic_inval_vld_c8_scanout;
1601wire arb_ic_inval_vld_c8;
1602wire ff_ic_inval_vld_c9_scanin;
1603wire ff_ic_inval_vld_c9_scanout;
1604wire arb_ic_inval_vld_c9;
1605wire ff_arb_dir_wr_en_c4_scanin;
1606wire ff_arb_dir_wr_en_c4_scanout;
1607wire dir_store_inst_vld_c3;
1608wire ff_dir_addr_cnt_scanin;
1609wire ff_dir_addr_cnt_scanout;
1610wire ff_dir_addr_cnt_c4_scanin;
1611wire ff_dir_addr_cnt_c4_scanout;
1612wire ff_dir_addr_cnt_c5_scanin;
1613wire ff_dir_addr_cnt_c5_scanout;
1614wire ff_dir_addr_cnt_c52_scanin;
1615wire ff_dir_addr_cnt_c52_scanout;
1616wire ff_dir_addr_cnt_c6_scanin;
1617wire ff_dir_addr_cnt_c6_scanout;
1618wire ff_dir_addr_cnt_c7_scanin;
1619wire ff_dir_addr_cnt_c7_scanout;
1620wire ff_dir_addr_c8_scanin;
1621wire ff_dir_addr_c8_scanout;
1622wire ff_dir_addr_c9_scanin;
1623wire ff_dir_addr_c9_scanout;
1624wire ff_sync_en_scanin;
1625wire ff_sync_en_scanout;
1626wire io_cmp_sync_en_r1;
1627wire ff_ncu_signals_scanin;
1628wire ff_ncu_signals_scanout;
1629wire spc0_avl;
1630wire spc1_avl;
1631wire spc2_avl;
1632wire spc3_avl;
1633wire spc4_avl;
1634wire spc5_avl;
1635wire spc6_avl;
1636wire spc7_avl_unused;
1637wire ff_staged_part_bank_scanin;
1638wire ff_staged_part_bank_scanout;
1639wire arbadr_ncu_l2t_pm_n;
1640wire arbadr_2bnk_true_enbld;
1641wire arbadr_4bnk_true_enbld;
1642wire ff_arb_cpuid_c3_scanin;
1643wire ff_arb_cpuid_c3_scanout;
1644wire ff_arb_cpuid_c4_scanin;
1645wire ff_arb_cpuid_c4_scanout;
1646wire ff_arb_cpuid_c5_scanin;
1647wire ff_arb_cpuid_c5_scanout;
1648wire ff_arb_cpuid_c52_scanin;
1649wire ff_arb_cpuid_c52_scanout;
1650wire ff_arb_ic_dir_wrentry_c4_scanin;
1651wire ff_arb_ic_dir_wrentry_c4_scanout;
1652wire [4:0] arb_ic_dir_wrentry_c4;
1653wire ff_arb_ic_dir_wrentry_c5_scanin;
1654wire ff_arb_ic_dir_wrentry_c5_scanout;
1655wire [4:0] arb_ic_dir_wrentry_c5;
1656wire ff_arb_ic_dir_wrentry_c6_scanin;
1657wire ff_arb_ic_dir_wrentry_c6_scanout;
1658wire [4:0] arb_ic_dir_wrentry_c6;
1659wire ff_arb_ic_dir_wrentry_c7_scanin;
1660wire ff_arb_ic_dir_wrentry_c7_scanout;
1661wire [4:0] arb_ic_dir_wrentry_c7;
1662wire inval_foric_vld;
1663wire ff_dc_wr_panel_c4_scanin;
1664wire ff_dc_wr_panel_c4_scanout;
1665wire ff_dc_wr_panel_c5_scanin;
1666wire ff_dc_wr_panel_c5_scanout;
1667wire ff_dc_wr_panel_c52_scanin;
1668wire ff_dc_wr_panel_c52_scanout;
1669wire ff_arbdec_arbdp_inst_bufidlo_c3_scanin;
1670wire ff_arbdec_arbdp_inst_bufidlo_c3_scanout;
1671wire arbdec_arbdp_inst_bufidlo_c3;
1672wire ff_ic_wr_panel_c4_scanin;
1673wire ff_ic_wr_panel_c4_scanout;
1674wire ff_ic_wr_panel_c5_scanin;
1675wire ff_ic_wr_panel_c5_scanout;
1676wire ff_ic_wr_panel_c52_scanin;
1677wire ff_ic_wr_panel_c52_scanout;
1678wire ff_ic_wr_panel_c6_scanin;
1679wire ff_ic_wr_panel_c6_scanout;
1680wire [4:0] ic_wr_panel_c6;
1681wire ff_ic_wr_panel_c7_scanin;
1682wire ff_ic_wr_panel_c7_scanout;
1683wire [4:0] ic_wr_panel_c7;
1684wire ff_ic_wr_panel_c8_scanin;
1685wire ff_ic_wr_panel_c8_scanout;
1686wire [4:0] ic_wr_panel_c8;
1687wire ff_ic_wr_panel_c9_scanin;
1688wire ff_ic_wr_panel_c9_scanout;
1689wire [4:0] ic_wr_panel_c9;
1690wire mux_sel_ic_inval_678_n;
1691wire [4:0] tmp_ic_wr_panel_c3_1;
1692wire mux_sel_ic_inval_6789;
1693wire fnl_sel_inval;
1694wire fnl_sel_default;
1695wire ff_wr64_inst_c3_scanin;
1696wire ff_wr64_inst_c3_scanout;
1697wire decdp_pf_ice_inst_c1;
1698wire ff_waysel_gate_c2_scanin;
1699wire ff_waysel_gate_c2_scanout;
1700wire ff_parerr_gate_c1_scanin;
1701wire ff_parerr_gate_c1_scanout;
1702wire ff_arb_stall_c1_scanin;
1703wire ff_arb_stall_c1_scanout;
1704wire ff_arb_inst_vld_c1_scanin;
1705wire ff_arb_inst_vld_c1_scanout;
1706wire arb_inst_vld_c1_fnl;
1707wire mbist_any_tag_lookup;
1708wire ff_mbist_lookup_r1_scanin;
1709wire ff_mbist_lookup_r1_scanout;
1710wire mbist_any_tag_lookup_reg;
1711wire mbist_any_tag_lookup_reg1;
1712wire l2t_mb2_fbtag_lookup_en_r1;
1713wire l2t_mb2_wbtag_lookup_en_r1;
1714wire l2t_mb2_rdmatag_lookup_en_r1;
1715wire mbist_any_tag_lookup_reg2;
1716wire ff_arb_inst_vld_c1_1_scanin;
1717wire ff_arb_inst_vld_c1_1_scanout;
1718wire ff_arb_inst_vld_c2_scanin;
1719wire ff_arb_inst_vld_c2_scanout;
1720wire ff_arb_inst_vld_c2_1_scanin;
1721wire ff_arb_inst_vld_c2_1_scanout;
1722wire ff_arb_inst_vld_c2_2_scanin;
1723wire ff_arb_inst_vld_c2_2_scanout;
1724wire ff_arb_inst_vld_c2_3_scanin;
1725wire ff_arb_inst_vld_c2_3_scanout;
1726wire ff_arb_inst_vld_c2_4_scanin;
1727wire ff_arb_inst_vld_c2_4_scanout;
1728wire ff_arb_inst_vld_c2_5_scanin;
1729wire ff_arb_inst_vld_c2_5_scanout;
1730wire ff_arb_inst_vld_c2_6_scanin;
1731wire ff_arb_inst_vld_c2_6_scanout;
1732wire ff_arb_inst_vld_c2_7_scanin;
1733wire ff_arb_inst_vld_c2_7_scanout;
1734wire ff_arb_inst_vld_c2_8_scanin;
1735wire ff_arb_inst_vld_c2_8_scanout;
1736wire ff_arb_inst_vld_c2_10_scanin;
1737wire ff_arb_inst_vld_c2_10_scanout;
1738wire ff_arb_inst_vld_c3_scanin;
1739wire ff_arb_inst_vld_c3_scanout;
1740wire ff_arb_inst_vld_c3_1_scanin;
1741wire ff_arb_inst_vld_c3_1_scanout;
1742wire ff_arb_inst_vld_c3_2_scanin;
1743wire ff_arb_inst_vld_c3_2_scanout;
1744wire ff_dec_evict_c2_scanin;
1745wire ff_dec_evict_c2_scanout;
1746wire ff_dec_evict_tecc_c2_scanin;
1747wire ff_dec_evict_tecc_c2_scanout;
1748wire ff_decdp_st_inst_c2_scanin;
1749wire ff_decdp_st_inst_c2_scanout;
1750wire ff_decdp_st_inst_c2_1_scanin;
1751wire ff_decdp_st_inst_c2_1_scanout;
1752wire ff_decdp_st_inst_c3_scanin;
1753wire ff_decdp_st_inst_c3_scanout;
1754wire ff_decdp_st_inst_c3_1_scanin;
1755wire ff_decdp_st_inst_c3_1_scanout;
1756wire ff_decdp_st_inst_c3_2_scanin;
1757wire ff_decdp_st_inst_c3_2_scanout;
1758wire ff_arbdp_inst_bufid1_c2_scanin;
1759wire ff_arbdp_inst_bufid1_c2_scanout;
1760wire decdp_bs_inst_c2;
1761wire ff_decdp_bis_inst_c2_scanin;
1762wire ff_decdp_bis_inst_c2_scanout;
1763wire decdp_strst_maid1_c2;
1764wire decdp_rmo_st_or_strst_maid1_c2;
1765wire ff_decdp_rmo_st_c3_scanin;
1766wire ff_decdp_rmo_st_c3_scanout;
1767wire decdp_rmo_st_or_strst_c2;
1768wire ff_decdp_rmo_or_strst_c3_scanin;
1769wire ff_decdp_rmo_or_strst_c3_scanout;
1770wire ff_decdp_strst_inst_c2_scanin;
1771wire ff_decdp_strst_inst_c2_scanout;
1772wire ff_decdp_strst_inst_c2_1_scanin;
1773wire ff_decdp_strst_inst_c2_1_scanout;
1774wire ff_decdp_wr8_inst_c2_scanin;
1775wire ff_decdp_wr8_inst_c2_scanout;
1776wire ff_decdp_wr64_inst_c2_scanin;
1777wire ff_decdp_wr64_inst_c2_scanout;
1778wire ff_decdp_wr64_inst_c2_1_scanin;
1779wire ff_decdp_wr64_inst_c2_1_scanout;
1780wire ff_arb_decdp_ld64_inst_c1_scanin;
1781wire ff_arb_decdp_ld64_inst_c1_scanout;
1782wire ff_decdp_inst_int_c2_scanin;
1783wire ff_decdp_inst_int_c2_scanout;
1784wire four_or_eight_byte_access_c1;
1785wire eight_byte_access_c1;
1786wire ff_decdp_pst_inst_c2_scanin;
1787wire ff_decdp_pst_inst_c2_scanout;
1788wire ff_decdp_pst_inst_c3_scanin;
1789wire ff_decdp_pst_inst_c3_scanout;
1790wire ff_decdp_pst_inst_c4_scanin;
1791wire ff_decdp_pst_inst_c4_scanout;
1792wire ff_decdp_pst_inst_c5_scanin;
1793wire ff_decdp_pst_inst_c5_scanout;
1794wire ff_decdp_pst_inst_c52_scanin;
1795wire ff_decdp_pst_inst_c52_scanout;
1796wire ff_decdp_pst_inst_c6_scanin;
1797wire ff_decdp_pst_inst_c6_scanout;
1798wire ff_decdp_pst_inst_c7_scanin;
1799wire ff_decdp_pst_inst_c7_scanout;
1800wire ff_st_no_ctrue_c1_scanin;
1801wire ff_st_no_ctrue_c1_scanout;
1802wire ff_arbdp_pst_no_ctrue_c2_1_scanin;
1803wire ff_arbdp_pst_no_ctrue_c2_1_scanout;
1804wire ff_arbdp_pst_with_ctrue_c2_scanin;
1805wire ff_arbdp_pst_with_ctrue_c2_scanout;
1806wire ff_arbdp_tag_pst_no_ctrue_c2_scanin;
1807wire ff_arbdp_tag_pst_no_ctrue_c2_scanout;
1808wire ff_arbdp_misbuf_pst_no_ctrue_c2_scanin;
1809wire ff_arbdp_misbuf_pst_no_ctrue_c2_scanout;
1810wire ff_arbdp_vuadctl_pst_no_ctrue_c2_scanin;
1811wire ff_arbdp_vuadctl_pst_no_ctrue_c2_scanout;
1812wire ff_decdp_cas1_inst_c2_scanin;
1813wire ff_decdp_cas1_inst_c2_scanout;
1814wire ff_decdp_cas1_inst_c2_1_scanin;
1815wire ff_decdp_cas1_inst_c2_1_scanout;
1816wire ff_decdp_cas2_inst_c2_scanin;
1817wire ff_decdp_cas2_inst_c2_scanout;
1818wire ff_decdp_cas2_from_mb_c2_scanin;
1819wire ff_decdp_cas2_from_mb_c2_scanout;
1820wire ff_decdp_cas2_from_mb_ctrue_c2_scanin;
1821wire ff_decdp_cas2_from_mb_ctrue_c2_scanout;
1822wire ff_store_err_c3_scanin;
1823wire ff_store_err_c3_scanout;
1824wire ff_store_err_c4_scanin;
1825wire ff_store_err_c4_scanout;
1826wire ff_store_err_c5_scanin;
1827wire ff_store_err_c5_scanout;
1828wire ff_store_err_c52_scanin;
1829wire ff_store_err_c52_scanout;
1830wire ff_store_err_c6_scanin;
1831wire ff_store_err_c6_scanout;
1832wire ff_store_err_c7_scanin;
1833wire ff_store_err_c7_scanout;
1834wire ff_store_err_c8_scanin;
1835wire ff_store_err_c8_scanout;
1836wire ff_decdp_fwd_req_c2_scanin;
1837wire ff_decdp_fwd_req_c2_scanout;
1838wire ff_decdp_swap_inst_c2_scanin;
1839wire ff_decdp_swap_inst_c2_scanout;
1840wire ff_decdp_imiss_inst_c2_scanin;
1841wire ff_decdp_imiss_inst_c2_scanout;
1842wire ff_decdp_camld_inst_c2_scanin;
1843wire ff_decdp_camld_inst_c2_scanout;
1844wire ff_decdp_ld_inst_c2_scanin;
1845wire ff_decdp_ld_inst_c2_scanout;
1846wire ff_decdp_pf_inst_c2_scanin;
1847wire ff_decdp_pf_inst_c2_scanout;
1848wire ff_decdp_pf_inst_c3_scanin;
1849wire ff_decdp_pf_inst_c3_scanout;
1850wire ff_decdp_pf_inst_c4_scanin;
1851wire ff_decdp_pf_inst_c4_scanout;
1852wire ff_decdp_pf_inst_c5_scanin;
1853wire ff_decdp_pf_inst_c5_scanout;
1854wire ff_decdp_pf_ice_inst_c2_scanin;
1855wire ff_decdp_pf_ice_inst_c2_scanout;
1856wire ff_decdp_pf_ice_inst_c3_scanin;
1857wire ff_decdp_pf_ice_inst_c3_scanout;
1858wire ff_decdp_pf_ice_inst_c4_scanin;
1859wire ff_decdp_pf_ice_inst_c4_scanout;
1860wire decdp_pf_ice_inst_c4;
1861wire ff_decdp_pf_ice_inst_c5_scanin;
1862wire ff_decdp_pf_ice_inst_c5_scanout;
1863wire decdp_pf_ice_inst_c5;
1864wire ff_decdp_pf_ice_inst_c52_scanin;
1865wire ff_decdp_pf_ice_inst_c52_scanout;
1866wire decdp_pf_ice_inst_c52;
1867wire ff_decdp_pf_ice_inst_c6_scanin;
1868wire ff_decdp_pf_ice_inst_c6_scanout;
1869wire decdp_pf_ice_inst_c6;
1870wire ff_decdp_pf_ice_inst_c7_scanin;
1871wire ff_decdp_pf_ice_inst_c7_scanout;
1872wire ff_decdp_dc_inval_c2_scanin;
1873wire ff_decdp_dc_inval_c2_scanout;
1874wire ff_decdp_ic_inval_c2_scanin;
1875wire ff_decdp_ic_inval_c2_scanout;
1876wire ff_pst_no_ctrue_c3_scanin;
1877wire ff_pst_no_ctrue_c3_scanout;
1878wire ff_pst_no_ctrue_c4_scanin;
1879wire ff_pst_no_ctrue_c4_scanout;
1880wire ff_pst_no_ctrue_c5_scanin;
1881wire ff_pst_no_ctrue_c5_scanout;
1882wire ff_pst_no_ctrue_c52_scanin;
1883wire ff_pst_no_ctrue_c52_scanout;
1884wire ff_pst_no_ctrue_c6_scanin;
1885wire ff_pst_no_ctrue_c6_scanout;
1886wire ff_pst_no_ctrue_c7_scanin;
1887wire ff_pst_no_ctrue_c7_scanout;
1888wire ff_pst_no_ctrue_c8_scanin;
1889wire ff_pst_no_ctrue_c8_scanout;
1890wire ff_decdp_cas1_inst_c3_scanin;
1891wire ff_decdp_cas1_inst_c3_scanout;
1892wire ff_decdp_cas1_inst_c4_scanin;
1893wire ff_decdp_cas1_inst_c4_scanout;
1894wire ff_decdp_cas1_inst_c5_scanin;
1895wire ff_decdp_cas1_inst_c5_scanout;
1896wire ff_decdp_cas1_inst_c52_scanin;
1897wire ff_decdp_cas1_inst_c52_scanout;
1898wire ff_decdp_cas1_inst_c6_scanin;
1899wire ff_decdp_cas1_inst_c6_scanout;
1900wire ff_decdp_cas1_inst_c7_scanin;
1901wire ff_decdp_cas1_inst_c7_scanout;
1902wire ff_decdp_cas1_inst_c8_scanin;
1903wire ff_decdp_cas1_inst_c8_scanout;
1904wire ff_arbdp_evict_c2_scanin;
1905wire ff_arbdp_evict_c2_scanout;
1906wire ff_arbdp_evict_c3_scanin;
1907wire ff_arbdp_evict_c3_scanout;
1908wire arb_ic_evict_c3;
1909wire arb_dc_evict_c3;
1910wire ff_arbdp_evict_c4_scanin;
1911wire ff_arbdp_evict_c4_scanout;
1912wire ff_arbdp_tecc_inst_mb_c4_scanin;
1913wire ff_arbdp_tecc_inst_mb_c4_scanout;
1914wire ff_arbdp_tecc_inst_mb_c5_scanin;
1915wire ff_arbdp_tecc_inst_mb_c5_scanout;
1916wire ff_arbdp_tecc_inst_mb_c52_scanin;
1917wire ff_arbdp_tecc_inst_mb_c52_scanout;
1918wire ff_arbdp_tecc_inst_mb_c6_scanin;
1919wire ff_arbdp_tecc_inst_mb_c6_scanout;
1920wire ff_arbdp_tecc_inst_mb_c7_scanin;
1921wire ff_arbdp_tecc_inst_mb_c7_scanout;
1922wire ff_arbdp_tecc_inst_mb_c8_scanin;
1923wire ff_arbdp_tecc_inst_mb_c8_scanout;
1924
1925
1926 input tcu_pce_ov;
1927 input tcu_aclk;
1928 input tcu_bclk;
1929 input tcu_scan_en;
1930
1931
1932 input arbadr_ncu_l2t_pm_n_dist; // BS 03/25/04 for partial bank/core modes support
1933 input arbadr_2bnk_true_enbld_dist; // BS 03/25/04 for partial bank/core modes support
1934 input arbadr_4bnk_true_enbld_dist; // BS 03/25/04 for partial bank/core modes support
1935 input [1:0] arbadr_arbdp_addr87_c2; // BS 03/25/04 for partial bank/core modes support
1936 input ncu_spc0_core_enable_status; // 0 : spc0 unavailable, 1 : available
1937 input ncu_spc1_core_enable_status; // 0 : spc1 unavailable, 1 : available
1938 input ncu_spc2_core_enable_status; // 0 : spc2 unavailable, 1 : available
1939 input ncu_spc3_core_enable_status; // 0 : spc3 unavailable, 1 : available
1940 input ncu_spc4_core_enable_status; // 0 : spc4 unavailable, 1 : available
1941 input ncu_spc5_core_enable_status; // 0 : spc5 unavailable, 1 : available
1942 input ncu_spc6_core_enable_status; // 0 : spc6 unavailable, 1 : available
1943 input ncu_spc7_core_enable_status; // 0 : spc7 unavailable, 1 : available
1944
1945
1946 input oqu_arb_full_px2; // oq is full. Comes from a flop in oqu. oq=6 or greater
1947
1948 input misbuf_arb_vld_px1; // valid Miss Buffer instruction.
1949 input misbuf_arb_cnt28_px2_prev; // NEW_PIN
1950 //input misbuf_arb_cnt12_px2; // OLD_PIN
1951 //input misbuf_arb_cnt11_px1; // OLD_PIN
1952 input misbuf_arb_snp_cnt8_px1; // 8 or more snoop entries in the mbf.
1953
1954 input wbuf_arb_full_px1; // wb is full. Comes from a flop in wbuf
1955 // has to accomodate the instruction in PX2 and C1
1956
1957// start int 5.0 changes
1958 input misbuf_arb_hit_c3 ; // POST_4.2 pin ( place on the right towards the bottom )
1959 output arb_misbuf_inval_inst_c2 ; // POST_4.2 pin ( place on the right towards the bottom )
1960// output decdp_ic_dc_inval_inst_c1 ; // POST_4.2 pin ( place on the right towards the bottom )
1961// end
1962
1963 input filbuf_arb_vld_px1; // valid fill in the Fill Buffer.
1964
1965 input iqu_iq_arb_vld_px2; // valid iq instruction
1966 input iqu_iq_arb_vld_px2_v1; // valid iq instruction
1967 input ique_iq_arb_vbit_px2; // vbit in the payload.
1968 input ique_iq_arb_atm_px2; // Px2 packet is atomic with the following packet.
1969 input ique_iq_arb_csr_px2; // may be critical.
1970 input ique_iq_arb_st_px2; // predecode from ique.
1971 input ique_arb_pf_ice_px2; // predecode from ique pf ice
1972 input snp_snpq_arb_vld_px1; // valid instruction at the head of the snoop q.
1973
1974 output arb_l2drpt_waysel_gate_c1;
1975
1976
1977 input tag_deccck_data_sel_c8; // decc state machine store data state.
1978 input tag_rdma_vld_px1;
1979 input tag_data_ecc_active_c3; // deccck state machine active.
1980 input tag_decc_tag_acc_en_px2; // decc FSM tag access state.
1981 input misbuf_nondep_fbhit_c3;
1982 input misbuf_hit_st_dep_zero;
1983 input tag_hit_unqual_c3;
1984
1985
1986
1987
1988 input mbist_arb_l2d_en; // from databist POST_3.2
1989 input bist_vuad_rd_en_px1;
1990
1991 input mbist_run;
1992
1993
1994 input arbdec_arbdp_inst_fb_c2; // fill instruction
1995
1996// int 5.0 changes
1997
1998 input [39:37] arbadr_arbdp_ioaddr_c1_39to37 ; // bits 39-32 are used to determine if the
1999 // address space is DRAM or diagnostic.
2000 input [35:33] arbadr_arbdp_ioaddr_c1_35to33 ; // bits 39-32 are used to determine if the
2001 // address space is DRAM or diagnostic.
2002
2003
2004
2005 // CAS compare related inputs
2006 input [1:0] arbdec_size_field_c8; // from arbdec for cas compare.
2007 input arbdat_word_lower_cmp_c8; // from arbdata for cas compare.
2008 input arbdat_word_upper_cmp_c8; // from arbdec for cas compare.
2009 input arbadr_addr2_c8; // from arbdec for cas compare.
2010
2011 // dwod mask generation inputs
2012 input [7:0] arbdec_arbdp_inst_size_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
2013
2014 input [3:0] arbadr_arbdp_diag_wr_way_c2; // from the addr of a tag write instruction
2015// input [2:0] arbadr_arbdp_inst_byte_addr_c7; // from arbaddr.
2016
2017 input [3:0] arbdec_arbdp_inst_way_c1 ; // from bits of a C1 instruction
2018 input arbdec_arbdp_tecc_c1 ;
2019
2020 input [3:0] filbuf_arbdp_way_px2; // new instruction way.
2021 input filbuf_tag_hit_frm_mb_c2;// instruction from MB hits in Fill Buffer , need to turn off
2022 // VUAD CE detection and reporting
2023
2024
2025
2026 input arbdec_arbdp_inst_mb_c2;
2027 input arbdec_arbdp_inst_fb_c1;
2028 input arbdec_arbdp_inst_dep_c2;
2029
2030 input tag_hit_l2orfb_c3 ;
2031 input tagdp_arb_par_err_c3; // used to gate off evicts in C3
2032 input tagdp_invalid_evict_c3 ; // from vuad dp.
2033 input arbdec_arbdp_inst_nc_c3 ;
2034 input [2:0] arbdec_arbdp_cpuid_c2; // from arbdec ,BS 03/25/04 for partial bank/core modes support
2035
2036 // BS 03/11/04 extra cycle for mem access
2037 input [1:0] arbdec_arbdp_l1way_c3;
2038
2039 input [7:0] arbadr_arbdp_addr11to4_c3 ; // from arbaddr
2040
2041
2042 input [1:0] arbadr_arbdp_new_addr5to4_px2; // from arbaddr not including stall mux results
2043 input [1:0] arbadr_arbdp_addr5to4_c1; // from arbaddr not including stall mux results
2044// int 5.0 change
2045 //input arbadr_arbdp_addr5_c2; // from arbaddr not including stall mux results
2046 input [1:0] arbadr_arbdp_addr5to4_c3; // from arbaddr not including stall mux results
2047
2048input arbdec_arbdp_inst_mb_c3;
2049input arbdec_arbdp_inst_tecc_c3;
2050
2051input arbdec_arbdp_inst_bufidhi_c1 ; // NEW_PIN decode
2052input arbdec_arbdp_inst_bufid1_c1;
2053input arbdec_arbdp_inst_mb_c1 ; // NEW_PIN decode
2054input arbdec_arbdp_evict_c1; // NEW_PIN decode.
2055input [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdec_arbdp_inst_rqtyp_c1 ; // NEW_PIN decode
2056input arbdec_arbdp_inst_rsvd_c1; // NEW_PIN decode
2057input arbdec_arbdp_inst_nc_c1 ; // NEW_PIN decode
2058//input [1:0] arbadr_arbdp_word_addr_c1;
2059input arbdec_arbdp_inst_ctrue_c1;
2060input [`L2_SZ_HI:`L2_SZ_LO] arbdec_arbdp_inst_size_c1;
2061
2062input arbadr_arbdp_addr_start_c2; // NEW_PIN decode
2063input arbdec_arbdp_rdma_inst_c2; // NEW_PIN decode
2064input arbdec_arbdp_inst_bufidlo_c2 ; // NEW_PIN decode
2065input [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdec_arbdp_inst_rqtyp_c2 ; // NEW_PIN decode
2066input [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdec_arbdp_inst_rqtyp_c6 ; // NEW_PIN decode
2067
2068
2069 input arbadr_arbaddr_addr22_c2 ; // NEW_PIN
2070 input bist_acc_vd_px1 ; // NEW_PIN from l2t_mbist_ctl.sv
2071
2072// MBIST hookup's
2073input l2t_mb2_mbtag_lookup_en;
2074input l2t_mb2_fbtag_lookup_en;
2075input l2t_mb2_wbtag_lookup_en;
2076input l2t_mb2_rdmatag_lookup_en;
2077input l2t_mb2_run;
2078output mbist_lookupen;
2079
2080
2081// int 5.0 changes
2082input mbist_arb_l2t_write ; // POST_4.0
2083
2084 output arb_decdp_mmuld_inst_c6; // BS and SR 11/12/03 N2 Xbar Packet format change
2085 output arb_acc_vd_c2 ; // NEW_PIN
2086 output arb_acc_ua_c2 ; // NEW_PIN
2087
2088 // csr inputs
2089 input csr_l2_bypass_mode_on;
2090
2091 // new pin POST_2.0
2092 // new pin POST_2.0
2093
2094 input l2clk;
2095 input io_cmp_sync_en;
2096 input wmr_l;
2097 input scan_in;
2098
2099// int 5.0 changes
2100input usaloc_ua_ce_c2; // VUAD ecc changes
2101input vlddir_vd_ce_c2; // VUAD ecc changes
2102input misbuf_vuad_ce_instr_c2; // VUAD ecc changes
2103
2104output [2:0] arb_cpuid_c5;
2105
2106output scan_out;
2107
2108output arb_bs_or_bis_inst_c2; // BS 04/20/04 , taking out arb_bs_or_bis_inst_c2 to l2t_usaloc_dp.sv
2109 // to clear Use bit on a BST or BIST to mitigate pollution effect in L2 cache
2110 // for Copy routines
2111
2112//output arb_dirvec_cpu0_sel00 ;// BS 03/25/04 for partial bank/core modes support
2113//output arb_dirvec_cpu0_selbot ;// BS 03/25/04 for partial bank/core modes support
2114//
2115//output arb_dirvec_cpu1_sel00 ;// BS 03/25/04 for partial bank/core modes support
2116//output arb_dirvec_cpu1_sel01 ;// BS 03/25/04 for partial bank/core modes support
2117//output arb_dirvec_cpu1_selbot ;// BS 03/25/04 for partial bank/core modes support
2118//output arb_dirvec_cpu1_seltop ;// BS 03/25/04 for partial bank/core modes support
2119//
2120//output arb_dirvec_cpu2_sel00 ;// BS 03/25/04 for partial bank/core modes support
2121//output arb_dirvec_cpu2_sel01 ;// BS 03/25/04 for partial bank/core modes support
2122//output arb_dirvec_cpu2_sel10 ;// BS 03/25/04 for partial bank/core modes support
2123//output arb_dirvec_cpu2_selbot ;// BS 03/25/04 for partial bank/core modes support
2124//output arb_dirvec_cpu2_seltop ;// BS 03/25/04 for partial bank/core modes support
2125//
2126//output arb_dirvec_cpu3_sel00 ;// BS 03/25/04 for partial bank/core modes support
2127//output arb_dirvec_cpu3_sel01 ;// BS 03/25/04 for partial bank/core modes support
2128//output arb_dirvec_cpu3_sel10 ;// BS 03/25/04 for partial bank/core modes support
2129//output arb_dirvec_cpu3_sel11 ;// BS 03/25/04 for partial bank/core modes support
2130//output arb_dirvec_cpu3_selbot ;// BS 03/25/04 for partial bank/core modes support
2131//output arb_dirvec_cpu3_seltop ;// BS 03/25/04 for partial bank/core modes support
2132//
2133//output arb_dirvec_cpu4_sel00 ;// BS 03/25/04 for partial bank/core modes support
2134//output arb_dirvec_cpu4_sel01 ;// BS 03/25/04 for partial bank/core modes support
2135//output arb_dirvec_cpu4_sel10 ;// BS 03/25/04 for partial bank/core modes support
2136//output arb_dirvec_cpu4_sel11 ;// BS 03/25/04 for partial bank/core modes support
2137//output arb_dirvec_cpu4_selbot ;// BS 03/25/04 for partial bank/core modes support
2138//output arb_dirvec_cpu4_seltop ;// BS 03/25/04 for partial bank/core modes support
2139//
2140//output arb_dirvec_cpu5_sel00 ;// BS 03/25/04 for partial bank/core modes support
2141//output arb_dirvec_cpu5_sel01 ;// BS 03/25/04 for partial bank/core modes support
2142//output arb_dirvec_cpu5_sel10 ;// BS 03/25/04 for partial bank/core modes support
2143//output arb_dirvec_cpu5_sel11 ;// BS 03/25/04 for partial bank/core modes support
2144//output arb_dirvec_cpu5_selbot ;// BS 03/25/04 for partial bank/core modes support
2145//output arb_dirvec_cpu5_seltop ;// BS 03/25/04 for partial bank/core modes support
2146//
2147//output arb_dirvec_cpu6_sel00 ;// BS 03/25/04 for partial bank/core modes support
2148//output arb_dirvec_cpu6_sel01 ;// BS 03/25/04 for partial bank/core modes support
2149//output arb_dirvec_cpu6_sel10 ;// BS 03/25/04 for partial bank/core modes support
2150//output arb_dirvec_cpu6_sel11 ;// BS 03/25/04 for partial bank/core modes support
2151//output arb_dirvec_cpu6_selbot ;// BS 03/25/04 for partial bank/core modes support
2152//output arb_dirvec_cpu6_seltop ;// BS 03/25/04 for partial bank/core modes support
2153//
2154//output arb_dirvec_cpu7_sel00 ;// BS 03/25/04 for partial bank/core modes support
2155//output arb_dirvec_cpu7_sel01 ;// BS 03/25/04 for partial bank/core modes support
2156//output arb_dirvec_cpu7_sel10 ;// BS 03/25/04 for partial bank/core modes support
2157//output arb_dirvec_cpu7_sel11 ;// BS 03/25/04 for partial bank/core modes support
2158//output arb_dirvec_cpu7_selbot ;// BS 03/25/04 for partial bank/core modes support
2159//output arb_dirvec_cpu7_seltop ;// BS 03/25/04 for partial bank/core modes support
2160//
2161 // BS 2/1/04 : Brought out IC inval signal to separate from IC fill
2162 // because IC fill will load only one panel in 1 row (only one 1 cache waY) while IC inval will write
2163 // to two panels in two rows (2 icache ways) every cycle. This IC dir write enable logic is in
2164 // l2t_dir_ctl.sv.
2165
2166// output arb_ic_inval_wr_en_c3; // to l2t_dirrep_ctl
2167
2168 output arb_mux1_mbsel_px2; // to all arbdps.
2169// output arb_mux2_snpsel_px2; // to all arbdps.
2170// cloned for timing
2171output arb_arbdat_mux2_snpsel_px2;
2172output arb_arbadr_mux2_snpsel_px2;
2173output arb_arbdec_mux2_snpsel_px2;
2174
2175
2176//output arb_arbadr_mux3_bufsel_px2;
2177output arb_arbdat_mux3_bufsel_px2;
2178output arb_arbdec_mux3_bufsel_px2;
2179
2180output arb_mux3_bufsel_px1;
2181
2182// output arb_mux4_c1sel_px2; // to all arbdps.
2183output arb_arbadr_mux4_c1sel_px2;
2184output arb_arbdat_mux4_c1sel_px2;
2185output arb_arbdec_mux4_c1sel_px2;
2186
2187 output arb_data_ecc_idx_en ; // to arbaddr
2188 output arb_data_ecc_idx_reset ; // to arbaddr.
2189
2190 output arb_sel_tecc_addr_px2; // sel for tecc,deccck,diagtag mux in px2.
2191 output arb_sel_deccck_addr_px2; // sel for tecc,decc,diagtag mux in px2.
2192 output arb_sel_diag_addr_px2; // sel for tecc,deccck,diagtag mux in px2.
2193 output arb_sel_diag_tag_addr_px2; // sel between C1 address and address from diag/tecc/deccck accesses.
2194 output arb_inc_tag_ecc_cnt_c3_n; // tecc instruction in C3.
2195 output arb_sel_lkup_stalled_tag_px2; // sel tecc/diagtag/c1 tag address.
2196
2197 output arb_bist_or_diag_acc_c1; // sel bist/diag data in arbaddr.
2198 // used for bist vs diagnostic way selection
2199 // in tag.
2200
2201// output arb_bist_or_diag_acc_qual_c1;
2202
2203 output arb_sel_deccck_or_bist_idx; // NEW_PIN
2204 output arb_sel_vuad_bist_px2 ; // NEW_PIN
2205 // output sel_stall_vuad_idx; // to arbadr. NEW_PIN
2206
2207 output arb_misbuf_inst_vld_c2; // instruction valid to misbuf
2208// output arb_filbuf_inst_vld_c2; // instruction valid to filbuf.
2209 output arb_inst_vld_c2; // valid instruction in C2.to arbaddr
2210
2211 output arb_tag_inst_vld_c2; // same as arb_inst_vld_c2
2212
2213 output arb_wbuf_inst_vld_c2;
2214
2215 output arb_imiss_hit_c10; // mux select for err reporting for imisses
2216 output arb_imiss_hit_c4; // mux select for dir cam address
2217
2218 output arb_evict_c3; // mux select for dir cam address
2219 output arb_evict_c4; // mux select for writing the approp
2220 // address into the directory
2221
2222 output arb_sel_c2_stall_idx_c1; // this signal goes to the set logic in
2223 // arbaddr
2224 output arb_vuad_acc_px2; // is an enable for vuad access.
2225
2226 output arb_upper_four_byte_access_c1;// BS 05/04/04 : taking out upper_four_byte_access info to word_en_c2[15:0] gen logic in tag_ctl
2227 output arb_lower_four_byte_access_c1;// BS 05/04/04 : taking out lower_four_byte_access info to word_en_c2[15:0] gen logic in tag_ctl
2228
2229 output arb_tag_wr_px2; // to tag for writes.
2230 output arb_vuad_idx2_sel_px2_n; // sel adr2 ( stalled addr ) for vuad access.
2231
2232 output arb_mb_camen_px2; // mbcam en.
2233
2234 output arb_filbuf_fbsel_c1 ; // indicates that an fb instruction got picked
2235 output arb_misbuf_mbsel_c1; // indicates that an fb instruction got picked.
2236 output arb_iqsel_px2; // indicates that the iq instruction got picked.
2237 output arb_iqsel_px2_v1; // indicates that the iq instruction got picked.
2238
2239 output arb_evict_vld_c2; // output to vuad dp.
2240
2241 output arb_ic_evict_c4; // output to vuad dp.
2242 output arb_dc_evict_c4; // output to vuad dp.
2243
2244 output arb_inst_diag_c1; // output to vuad dp.
2245
2246
2247 output arb_inst_vld_c1; // valid instruction in C1
2248 output arb_inval_inst_vld_c3; // valid invalid instruction in C3
2249
2250 // to l2d
2251 output arb_l2d_fbrd_c3; // mux select for wr data in l2d.
2252
2253 // to misbuf
2254 output arb_misbuf_ctrue_c9 ; // compare true.
2255 output arb_misbuf_cas1_hit_c8; // cas1 hit qualifier for the above inst.
2256
2257 output arb_decc_data_sel_c9; // scrub data write select to arbdat ;
2258 output [3:0] arb_tecc_way_c2; // to tagd for tagecc related reads.
2259 output arb_l2tag_vld_c4; // to tagd for diagnostic read
2260 // output arb_int_or_diag_acc_c1; // to tagd POST_2.0
2261
2262 output [7:0] arb_dword_mask_c8; // used in arbdata for pst merging.
2263
2264 output arb_fill_vld_c2; // to tag.
2265 output arb_imiss_vld_c2; // to tag for way select mux
2266
2267 output arb_pf_ice_inst_c2;
2268 output arb_pf_ice_inst_c7;
2269
2270
2271/////////////////////
2272// TAG DP outputs
2273/////////////////////
2274 output arb_normal_tagacc_c2; // to tagd
2275 output arb_tagd_tecc_c2; // NEW_PIN indicates that a tecc op is
2276 // reading the tags.
2277
2278/////////////////////
2279// Directory or Dir rep outputs
2280/////////////////////
2281output arb_dir_vld_c3_l;
2282output arb_dc_rd_en_c3; // NEW_PIN
2283output arb_ic_rd_en_c3;
2284output arb_dc_wr_en_c3; // NEW_PIN
2285output arb_ic_wr_en_c3;
2286output [4:0] arb_dir_panel_dcd_c3; // NEW_PIN
2287output [4:0] arb_dir_panel_icd_c3;
2288output [3:0] arb_lkup_bank_ena_dcd_c3 ; // NEW_PIN
2289output [3:0] arb_lkup_bank_ena_icd_c3 ; // NEW_PIN
2290output [7:0] arb_inval_mask_dcd_c3; // NEW_PIN
2291output [7:0] arb_inval_mask_icd_c3;
2292output [4:0] arb_wr_dc_dir_entry_c3; // NEW_PIN
2293output [4:0] arb_wr_ic_dir_entry_c3;
2294output arb_dc_ic_rd_bit_4;
2295
2296
2297 output [10:0] arb_dir_addr_c9; // NEW_PIN
2298
2299 output arb_dir_wr_en_c4; // NEW_PIN to the csrblock
2300
2301
2302output arb_csr_wr_en_c7; // to the csr block
2303output arb_csr_rd_en_c7; // to oq_dctl.
2304
2305
2306 output arb_evict_c5; // to oqu.
2307
2308///////////////////////
2309// tag outputs
2310///////////////////////
2311 output arb_waysel_gate_c2;
2312 output arb_data_diag_st_c2;
2313 output arb_inval_inst_c2;
2314// output arb_inst_diag_c2;
2315output arb_decdp_ld64_inst_c1; // POST_3.4 constrain it properly.
2316
2317 output arb_waysel_inst_vld_c2; // POST_2.0
2318// output arb_coloff_inst_vld_c2; // POST_2.0
2319 output arb_inst_vld_c2_prev;
2320 output arb_rdwr_inst_vld_c2; // POST_2.0
2321
2322// int 5.0 changes
2323// output arb_wen_inst_vld_c2; // POST_2.0
2324
2325 output arb_ic_inval_vld_c7; // outputs to oque to send a st ack
2326 output arb_dc_inval_vld_c7;
2327
2328
2329 output arb_inst_l2data_vld_c6; // diagnostic data access to decc.
2330
2331
2332output arb_csr_wr_en_c3; // to tag for st ack generation
2333output arb_csr_rd_en_c3; // to tag.
2334output arb_diag_complete_c3;
2335output arb_tag_pst_with_ctrue_c1 ; // POST_3.4 pin Bottom.
2336///////////////////////
2337// misbuf outputs
2338///////////////////////
2339output arb_csr_st_c2; // to misbuf for insert and delete logic.
2340output arb_misbuf_hit_off_c1 ; // turn off mb tag hit if this signal is high.
2341output arb_pst_ctrue_en_c8;
2342output arb_evict_tecc_vld_c2 ; // POST_2.0 pin
2343
2344///////////////////////
2345// filbuf outputs
2346///////////////////////
2347 output arb_filbuf_hit_off_c1 ; // turn off fb tag hit if this signal is high.
2348
2349///////////////////////
2350// wbuf outputs
2351///////////////////////
2352 output arb_wbuf_hit_off_c1 ; // turn off wb tag hit if this signal is high.
2353
2354///////////////////////
2355// oq_dctl outputs
2356///////////////////////
2357 output arb_inst_l2vuad_vld_c6;
2358 output arb_inst_l2tag_vld_c6;
2359
2360///////////////////////
2361// to snp
2362///////////////////////
2363// output arb_snpsel_c1;
2364output arb_snp_snpsel_px2;
2365
2366//output arb_dbg_inst_vld_c3; // to dbg.
2367
2368output arb_decdp_tag_wr_c1;
2369
2370output arb_decdp_pst_inst_c2 ;
2371output arb_decdp_fwd_req_c2;
2372output arb_decdp_swap_inst_c2;
2373output arb_decdp_imiss_inst_c2;
2374// int 5.0 changes
2375output arb_decdp_inst_int_c2;
2376output arb_decdp_inst_int_c1;
2377
2378
2379output arb_decdp_ld64_inst_c2; // NEW_PIN decod
2380output arb_decdp_bis_inst_c3; // NEW_PIN decode
2381output arb_decdp_rmo_st_c3;
2382output arb_decdp_strst_inst_c2; // NEW_PIN decode
2383output arb_decdp_wr8_inst_c2; // NEW_PIN decode
2384output arb_decdp_wr64_inst_c2;
2385output arb_decdp_st_inst_c2; // NEW_PIN decode.
2386output arb_decdp_st_inst_c3;
2387output arb_decdp_st_with_ctrue_c2;
2388output arb_decdp_ld_inst_c2;
2389output arb_arbdp_dword_st_c1 ;
2390output arb_arbdp_pst_with_ctrue_c2;
2391output arb_decdp_cas1_inst_c2;
2392output arb_decdp_cas2_inst_c2;
2393output arb_decdp_cas2_from_mb_c2;
2394//output arb_decdp_cas2_from_mb_ctrue_c2;
2395output decdp_cas2_from_mb_ctrue_c1;
2396
2397output arb_inst_l2vuad_vld_c3; // to vuaddp
2398
2399//output arb_write_req_c3; // to arbdec
2400//output arb_prim_req_c3;
2401
2402output arb_decdp_pf_inst_c5;
2403output arb_decdp_strld_inst_c6 ;
2404output arb_decdp_atm_inst_c6;
2405
2406output arb_store_err_c8;
2407output arb_arbdp_tecc_inst_mb_c8;
2408output arb_tagd_perr_vld_c2; // POST_2.0 pin
2409
2410output arb_arbdp_tag_pst_no_ctrue_c2; // POST 3.0 pin
2411output arb_arbdp_misbuf_pst_no_ctrue_c2; // POST 3.0 pin
2412output arb_arbdp_vuadctl_pst_no_ctrue_c2; // POST 3.0 pin
2413
2414output arb_tecc_c2; // POST_3.0 PIN
2415
2416 output arb_vuadctl_no_bypass_px2; // POST_3.1 pin
2417
2418 output arb_sel_way_px2; // selects go to arbaddr to wr data muxes
2419 output arb_diag_or_tecc_write_px2 ; // selects go to arbaddr to wr data muxes
2420 output arb_tag_rd_px2; // to tag for reads.
2421 output [15:0] arb_tag_way_px2; // tag write way. // BS & SR 10/28/03
2422 output arb_mux1_mbsel_px1;
2423 output arb_wr8_inst_no_ctrue_c1; // POST_3.4
2424
2425output arb_vuad_ce_err_c2; // VUAD ecc changes
2426output usaloc_vlddir_arb_vuad_ce_err_c3; // VUAD ecc changes
2427output tagctl_arb_vuad_ce_err_c3; // VUAD ecc changes
2428
2429// BS & SR 12/07/04 : taking out arb_swap_cas2_req_c2 to l2t_oqu_ctl.sv to disable ERROR
2430// Indication packet on a CE,UE, or Notdata on the store part of the swap or CAS2.
2431// Instead , regular store ack packet will get sent.
2432
2433output arb_oqu_swap_cas2_req_c2;
2434
2435
2436//////////////////////////////////////////////////
2437// L1 clk header
2438//////////////////////////////////////////////////
2439assign pce_ov = tcu_pce_ov;
2440assign stop = 1'b0;
2441assign siclk = tcu_aclk;
2442assign soclk = tcu_bclk;
2443assign se = tcu_scan_en;
2444
2445//////////////////////////////////////////
2446// Spare gate insertion
2447//////////////////////////////////////////
2448l2t_arb_ctl_spare_ctl_macro__num_4 spares (
2449 .scan_in(spares_scanin),
2450 .scan_out(spares_scanout),
2451 .l1clk (l1clk),
2452 .siclk(siclk),
2453 .soclk(soclk)
2454);
2455//////////////////////////////////////////
2456
2457
2458l2t_arb_ctl_l1clkhdr_ctl_macro clkgen (
2459 .l2clk(l2clk),
2460 .l1en(1'b1 ),
2461 .l1clk(l1clk),
2462 .pce_ov(pce_ov),
2463 .stop(stop),
2464 .se(se));
2465
2466//////////////////////////////////////////////////
2467
2468assign dbginit_l = 1'b1;
2469
2470wire [7:0] arb_cpuid_dec_c2;
2471wire sel_bot_seg;
2472wire sel_00;
2473wire sel_01;
2474wire sel_10;
2475wire sel_11;
2476wire sum0;
2477wire [1:0] sum01;
2478wire [1:0] sum012;
2479wire [2:0] sum0123,sum01234,sum012345,sum0123456;
2480wire [1:0] seg;
2481wire [2:0] arb_cpuid_c3,arb_cpuid_c4,arb_cpuid_c52;
2482
2483 wire [2:0] arb_cpuid_fnl_c2;
2484 wire decdp_strpst_inst_c1;
2485 wire arb_tag_acc_px2 ; // indicates that the tag array is accessed.
2486 wire sel_delayed_fill_wr_c1, sel_fill_wr_px2;
2487
2488 wire set_gate_off_prim_req_px2;
2489 wire gate_off_prim_req_c1;
2490 wire gate_off_prim_req_state;
2491 wire gate_off_prim_req_state_in;
2492
2493 wire arb_inst_l2vuad_c2 ;
2494 wire inst_l2vuad_vld_c2, inst_l2vuad_vld_c3, inst_l2vuad_vld_c4 ;
2495 wire inst_l2tag_vld_c3, inst_l2tag_vld_c4;
2496
2497 wire arb_multi_cyc_c1;
2498 wire arb_stall_c2 ;
2499 wire same_col_stall_c1, arb_prev_stall_c1, arb_stall_c1 ;
2500
2501// int 5.0 changes
2502
2503 wire decdp_st_inst_c3_1;
2504
2505
2506 wire mbf_valid_px1,mbf_valid_px2;
2507 wire snp_valid_px2;
2508 wire fbf_valid_px1; // int 5.0 changes ,fbf_valid_px2;
2509
2510 wire mbsel_px2,mbsel_c1;
2511 wire snpsel_px2,snpsel_c1,snpsel_c2, snpsel_c3;
2512 wire fbsel_px2,fbsel_c1;
2513 wire iqsel_px2;
2514 wire mbfull_px2;
2515 wire arb_inst_vld_px2;
2516 wire inst_vld_c2_prev;
2517
2518 wire atm_instr_c1, atm_instr_px2;
2519 wire inc_tag_ecc_cnt_c3;
2520
2521
2522// int 5.0 changes
2523// wire imiss_hit_c7;
2524
2525 wire arb_inst_l2tag_c2;
2526 wire inst_l2tag_vld_c2; // needed in muxsel generation for arbaddr
2527 wire arb_inst_l2data_c2;
2528 wire inst_l2data_vld_c2; // used in muxsel generation for arbdata
2529 wire inst_l2data_vld_c3, inst_l2data_vld_c4;
2530 wire inst_l2data_vld_c5, inst_l2data_vld_c52, inst_l2data_vld_c6; // BS 03/11/04 extra cycle for mem access
2531 wire cmp_lower_c9, cmp_upper_c9, cmp_dword_c9;
2532
2533 wire [7:0] tecc_st_cnt_plus1, tecc_st_cnt ;
2534
2535 wire [3:0] tag_diag_or_tecc_way_c2;
2536 wire [3:0] stalled_tag;
2537
2538 wire [7:0] dword_mask_c7;
2539 wire hit_l2orfb_c4, hit_l2orfb_c5, hit_l2orfb_c52, hit_l2orfb_c6, hit_l2orfb_c7, hit_l2orfb_c8 ;
2540 // BS 03/11/04 extra cycle for mem access
2541 wire arb_inst_vld_c3; // used to qualify address compares
2542 wire arb_inst_vld_c3_1; // used to qualify address compares
2543
2544
2545 wire [10:0] dir_addr_cnt_plus1,dir_addr_cnt_c3;
2546 wire [10:0] dir_addr_cnt_c4,dir_addr_cnt_c5, dir_addr_cnt_c52; // BS 03/11/04 extra cycle for mem access
2547 wire [10:0] dir_addr_cnt_c6,dir_addr_cnt_c7, dir_addr_cnt_c8;
2548 wire [4:0] dir_entry_c3, dir_entry_c4, dir_entry_c5, dir_entry_c52, dir_entry_c6 ; // BS 03/11/04 extra cycle for mem access
2549 wire [4:0] tmp_wr_dir_entry_c3, wr_dir_entry_c3 ;
2550 wire def_inval_entry;
2551 wire [4:0] dc_wr_panel_c3, dc_wr_panel_c4;
2552 wire [4:0] dc_wr_panel_c5, dc_wr_panel_c52; // BS 03/11/04 extra cycle for mem access
2553 wire [4:0] tmp_dc_wr_panel_c3;
2554 wire [4:0] ic_wr_panel_c3, ic_wr_panel_c4;
2555 wire [4:0] ic_wr_panel_c5, ic_wr_panel_c52; // BS 03/11/04 extra cycle for mem access
2556 wire [4:0] tmp_ic_wr_panel_c3;
2557 wire [7:0] self_inval_mask_c3, others_inval_mask_c3, tmp_inval_mask_c3 ;
2558 wire [2:0] cpuid_c3;
2559 wire ld_inst_c3, ld_hit_c3, sel_stld_mask;
2560 wire inval_inst_vld_c2 ;
2561 wire dc_inval_vld_c3, ic_inval_vld_c3, inval_inst_vld_c3;
2562 wire dc_inval_vld_c4, ic_inval_vld_c4, inval_inst_vld_c4;
2563 wire dc_inval_vld_c5, ic_inval_vld_c5, inval_inst_vld_c5;
2564// BS 03/11/04 extra cycle for mem access
2565 wire dc_inval_vld_c52, ic_inval_vld_c52, inval_inst_vld_c52;
2566 wire dc_inval_vld_c6, ic_inval_vld_c6;
2567 wire dc_inval_c3, ic_inval_c3;
2568
2569 wire [3:0] dc_cam_addr_c3, ic_cam_addr_c3 ;
2570// int 5.0 changes
2571 wire enc_cam_addr_c4 ;
2572
2573
2574 wire dc_hitqual_cam_en0_c3, dc_hitqual_cam_en1_c3, ic_hitqual_cam_en_c2 ;
2575
2576 wire tmp_bank_icd_c3 ;
2577
2578 wire st_cam_en_c2 ;
2579 wire waysel_gate_c1;
2580
2581 wire arb_imiss_hit_c5, arb_imiss_hit_c7 ;
2582 wire arb_imiss_hit_c8, arb_imiss_hit_c9 ;
2583 wire tecc_inst_c2;
2584 wire tecc_tag_acc_en_px2;
2585 wire inc_tag_ecc_cnt_c2;
2586 wire data_ecc_active_c4 ; // used for stall.
2587 wire arb_inst_csr_c2;
2588
2589 wire imiss_inst_c3;
2590 wire st_cam_en_c3_tmp; // BS and SR 11/07/03, store pipelining support
2591 wire st_cam_en_c3;
2592 wire sp_cam_en_c2, sp_cam_en_c3; // special instruction cam en
2593 wire ic_hitqual_cam_en_c3;
2594wire imiss_hit_c3;
2595
2596wire arb_evict_unqual_c3;
2597wire arb_csr_wr_en_c2, arb_csr_wr_en_c4;
2598wire arb_csr_wr_en_c5, arb_csr_wr_en_c52, arb_csr_wr_en_c6, arb_csr_wr_en_c8; // BS 03/11/04 extra cycle for mem access
2599wire arb_csr_rd_en_c2, arb_csr_rd_en_c4;
2600wire arb_csr_rd_en_c5, arb_csr_rd_en_c52, arb_csr_rd_en_c6; // BS 03/11/04 extra cycle for mem access
2601 wire inst_l2vuad_vld_c5, inst_l2vuad_vld_c52, inst_l2vuad_vld_c6; // BS 03/11/04 extra cycle for mem access
2602 wire inst_l2tag_vld_c5, inst_l2tag_vld_c52, inst_l2tag_vld_c6; // BS 03/11/04 extra cycle for mem access
2603
2604 wire arb_inst_csr_c1;
2605 wire arb_inst_l2data_c1;
2606 wire arb_inst_l2tag_c1;
2607 wire arb_inst_l2vuad_c1;
2608 wire store_inst_en_c3 ;
2609
2610 wire sp_tag_access_c1, sp_tag_access_px2 ;
2611 wire arb_tag_acc_c1;
2612 wire normal_tagacc_c1, normal_tagacc_c2;
2613 wire arb_stall_unqual_c2;
2614
2615 wire wr64_inst_c3;
2616 wire rdma_64B_stall;
2617 wire arb_fill_vld_c3;
2618 wire arb_imiss_hit_c6;
2619
2620 wire gate_off_buf_req_px2;
2621 wire snp_muxsel_px1 ;
2622 wire arb_dir_wr_en_c3;
2623
2624 wire bist_enable_c1, bist_enable_c2 ;
2625 wire bist_acc_vd_c1, bist_acc_vd_c2 ;
2626
2627 // Decode
2628
2629
2630// int 5.0 changes
2631// wire decdp_inst_int_c1;
2632
2633
2634wire decdp_inst_int_or_inval_c1;
2635wire arbdp_inst_mb_or_fb_c1 ;
2636
2637wire decdp_rmo_st_c2, decdp_bis_inst_c2 ;
2638wire decdp_strst_inst_c1;
2639wire decdp_wr8_inst_c1, decdp_wr64_inst_c1 ;
2640wire decdp_st_inst_c1;
2641wire dec_evict_c1, dec_evict_c2;
2642
2643wire decdp_rdmapst_inst_c1;
2644wire decdp_pst_inst_c1_internal;
2645wire pst_with_ctrue_c1, decdp_cas1_inst_c1;
2646wire decdp_cas2_inst_c1, decdp_cas2_from_mb_c1;
2647wire decdp_cas2_from_mb_ctrue_c1;
2648wire decdp_cas2_from_xbar_c1;
2649wire decdp_pst_st_c1, pst_no_ctrue_c1;
2650wire st_with_ctrue_c1;
2651wire arbdp_tecc_inst_c1;
2652wire store_err_c2, store_err_c3, store_err_c4 ;
2653wire store_err_c5, store_err_c52, store_err_c6, store_err_c7 ; // BS 03/11/04 extra cycle for mem access
2654wire decdp_fwd_req_c1;
2655wire decdp_swap_inst_c1;
2656wire decdp_camld_inst_c1, decdp_camld_inst_c2;
2657wire decdp_imiss_inst_c1;
2658wire decdp_ld_inst_c1;
2659wire decdp_pf_inst_c1, decdp_pf_inst_c2;
2660wire decdp_pf_inst_c3, decdp_pf_inst_c4;
2661wire dword_st_c1;
2662wire decdp_dc_inval_c1, decdp_dc_inval_c2;
2663wire decdp_ic_inval_c1, decdp_ic_inval_c2;
2664wire multi_cyc_op_c1;
2665wire decdp_pst_inst_c3, decdp_pst_inst_c4, decdp_pst_inst_c5, decdp_pst_inst_c52; // BS 03/11/04 extra cycle for mem access
2666wire decdp_pst_inst_c6, decdp_pst_inst_c7 ;
2667wire pst_no_ctrue_c3, pst_no_ctrue_c4, pst_no_ctrue_c5, pst_no_ctrue_c52 ; // BS 03/11/04 extra cycle for mem access
2668wire pst_no_ctrue_c6, pst_no_ctrue_c7 ;
2669wire arbdp_pst_no_ctrue_c8;
2670wire decdp_cas1_inst_c3, decdp_cas1_inst_c4, decdp_cas1_inst_c5, decdp_cas1_inst_c52 ; // BS 03/11/04 extra cycle for mem access
2671wire decdp_cas1_inst_c6, decdp_cas1_inst_c7, decdp_cas1_inst_c8 ;
2672//wire sp_pst_inst_c2, sp_pst_inst_c3, sp_pst_inst_c4 ;
2673//wire sp_pst_inst_c5, sp_pst_inst_c52, sp_pst_inst_c6;// sp_pst_inst_c7 ; // BS 03/11/04 extra cycle for mem access
2674wire decdp_strpst_inst_c2, decdp_rdmapst_inst_c2;
2675wire arbdp_tecc_inst_mb_c3, arbdp_tecc_inst_mb_c4;
2676wire arbdp_tecc_inst_mb_c5, arbdp_tecc_inst_mb_c52, arbdp_tecc_inst_mb_c6; // BS 03/11/04 extra cycle for mem access
2677wire arbdp_tecc_inst_mb_c7;
2678wire tecc_st_cnt_reset;
2679
2680 wire arb_inst_vld_c2_1, arb_inst_vld_c2_2;
2681 wire arb_inst_vld_c2_3, arb_inst_vld_c2_4;
2682 wire arb_inst_vld_c2_5, arb_inst_vld_c2_6;
2683 wire arb_inst_vld_c2_7;
2684
2685
2686wire imiss_stall_op_c1inc1;
2687wire decdp_cas1_inst_c1_1, decdp_cas1_inst_c2_1;
2688wire arb_stall_tmp_c1;
2689wire mbf_valid_px2_1;
2690wire fbf_valid_px2_1;
2691wire snp_valid_px2_1;
2692wire arb_inst_vld_c1_1;
2693wire decdp_st_inst_c2_1;
2694wire decdp_strst_inst_c2_1;
2695wire tecc_tag_acc_en_px1;
2696wire arb_tagd_tecc_c1;
2697wire arb_csr_wr_en_c3_1;
2698wire decdp_wr64_inst_c2_1;
2699wire arbdp_pst_no_ctrue_c2_1;
2700wire parerr_gate_c1, parerr_gate_c2;
2701wire dec_evict_tecc_c1, dec_evict_tecc_c2;
2702wire arbdp_evict_c2, arbdp_evict_c3;
2703 wire arb_inst_vld_c2_8;
2704 wire arb_inst_vld_c2_10; // int 5.0 changes, arb_inst_vld_c2_11;
2705 wire bist_vuad_rd_en_px2;
2706 wire bist_acc_vd_px2;
2707
2708 wire store_inst_vld_c3;
2709 wire store_inst_vld_c3_1;
2710 wire lower_cas_c8, lower_cas_c9;
2711 wire upper_cas_c8, upper_cas_c9;
2712 wire arbdat_word_lower_cmp_c8, word_lower_cmp_c9;
2713 wire arbdat_word_upper_cmp_c8, word_upper_cmp_c9;
2714wire [3:0] enc_tag_way_px2;
2715
2716wire [3:0] dec_lo_way_sel_c1;
2717// int 5.0 changes
2718wire [3:0] dec_hi_way_sel_c1 ; // left as is since way = 16
2719
2720wire decdp_st_inst_c3_2, arb_inst_vld_c3_2 ;
2721wire store_inst_vld_c3_2;
2722wire arb_inst_l2tag_c2_1;
2723 wire scrub_fsm_count_eq_5_px1, scrub_fsm_count_eq_6_px2;
2724 wire diag_or_tecc_acc_px2, diag_or_tecc_acc_c1;
2725 wire diag_or_scr_way_sel;
2726wire inst_l2tag_vld_c2_1;
2727 wire scrub_fsm_count_eq_0_px1, scrub_fsm_count_eq_1_px2 ;
2728wire inst_bufid1_c2;
2729 wire mux3_bufsel_px1;
2730 wire snp_valid_px1;
2731
2732 wire wr8_inst_pst_c1; // int 5.0 changes
2733
2734
2735 ///////////////////////////////////////////////////////////////////
2736 //
2737 // L2 $ OFF mode exceptions in arb:
2738 // IN the L2 $ off mode, a fill can only be issued if the
2739 // wbb is not full. This is factored into the fbsel logic in PX1
2740 //
2741 ///////////////////////////////////////////////////////////////////
2742
2743
2744 ///////////////////////////////////////////////////////////////////
2745 // Reset flop
2746 ///////////////////////////////////////////////////////////////////
2747
2748l2t_arb_ctl_msff_ctl_macro__width_1 reset_flop
2749 (.dout(dbb_rst_l),
2750 .scan_in(reset_flop_scanin),
2751 .scan_out(reset_flop_scanout),
2752 .l1clk(l1clk),
2753 .din(wmr_l),
2754 .siclk(siclk),
2755 .soclk(soclk)
2756
2757);
2758
2759
2760 ///////////////////////////////////////////////////////////////////
2761 // Sel for picking ctu data over sparc data for a BIST control reg
2762 // CSR write.
2763 ///////////////////////////////////////////////////////////////////
2764
2765
2766 ///////////////////////////////////////////////////////////////////
2767 //pipeline for gating off instructions due to CSR stores.
2768 //--------------------------------------------------------------------
2769 // PX2 C1
2770 //--------------------------------------------------------------------
2771 // csr store
2772 // selected
2773 // from IQ
2774 // assert
2775 // primary
2776 // request
2777 // blackout.
2778 //
2779 //--------------------------------------------------------------------
2780 // PX2
2781 //--------------------------------------------------------------------
2782 //
2783 // gate off
2784 // issue from
2785 // all srcs except
2786 // C1
2787 //
2788 //
2789 //--------------------------------------------------------------------
2790 // PX1 PX2
2791 //--------------------------------------------------------------------
2792 // gate off
2793 // issue from
2794 // snpQ
2795 //
2796 // gate
2797 // off issue
2798 // from IQ
2799 //
2800 // continue
2801 // fb/mb reqs.
2802 //
2803 ////////////////////////////////////////////////////////////////
2804
2805
2806//
2807// assign set_gate_off_prim_req_px2 = ( ique_iq_arb_csr_px2 & // csr address
2808// ique_iq_arb_st_px2 & // store
2809// ique_iq_arb_vbit_px2 &
2810// iqsel_px2 ) ; // select an IQ instruction.
2811//
2812
2813
2814
2815assign set_gate_off_prim_req_px2 = (( ique_iq_arb_csr_px2 & // csr address
2816 ique_iq_arb_st_px2 & // store
2817 ique_iq_arb_vbit_px2 & iqsel_px2 ) | // select an IQ instruction.
2818 (ique_arb_pf_ice_px2 & ique_iq_arb_vbit_px2 & iqsel_px2)); //select pf ice inst
2819
2820l2t_arb_ctl_msff_ctl_macro__width_1 ff_gate_off_prim_req_c1
2821 (.dout(gate_off_prim_req_c1), .l1clk(l1clk),
2822 .scan_in(ff_gate_off_prim_req_c1_scanin),
2823 .scan_out(ff_gate_off_prim_req_c1_scanout),
2824 .din(set_gate_off_prim_req_px2),
2825 .siclk(siclk),
2826 .soclk(soclk)
2827 );
2828
2829assign gate_off_prim_req_state_in = ( gate_off_prim_req_state | // gate off state==1
2830 gate_off_prim_req_c1 ) & // PX2 req is a csr store.
2831 ~( arb_csr_wr_en_c8 | reset_for_pf_ice_c8) ;
2832
2833
2834
2835assign reset_for_pf_ice_c3 = arbdec_arbdp_inst_mb_c3 & decdp_pf_ice_inst_c3 & arb_inst_vld_c3 & ~arbdec_arbdp_inst_tecc_c3 &
2836 ~tagdp_arb_par_err_c3; // on a tag parity error in the eviction pass of
2837 // prefetch ice or the tecc pass that comes after that
2838 // ,do not remove the IQ dequeue blocking
2839
2840l2t_arb_ctl_msff_ctl_macro__width_6 ff_reset_for_pf_ice_staging
2841 (
2842 .scan_in(ff_reset_for_pf_ice_staging_scanin),
2843 .scan_out(ff_reset_for_pf_ice_staging_scanout),
2844 .din({reset_for_pf_ice_c3,reset_for_pf_ice_c4,reset_for_pf_ice_c5,
2845 reset_for_pf_ice_c52,reset_for_pf_ice_c6,reset_for_pf_ice_c7}),
2846 .l1clk(l1clk),
2847 .dout({reset_for_pf_ice_c4,reset_for_pf_ice_c5,
2848 reset_for_pf_ice_c52,reset_for_pf_ice_c6,reset_for_pf_ice_c7,reset_for_pf_ice_c8}),
2849 .siclk(siclk),
2850 .soclk(soclk)
2851 );
2852
2853
2854l2t_arb_ctl_msff_ctl_macro__clr_1__width_1 ff_gate_off_prim_req_state // sync reset active low
2855 (.dout(gate_off_prim_req_state), .l1clk(l1clk),
2856 .scan_in(ff_gate_off_prim_req_state_scanin),
2857 .scan_out(ff_gate_off_prim_req_state_scanout),
2858 .clr(~dbb_rst_l),
2859 .din(gate_off_prim_req_state_in),
2860 .siclk(siclk),
2861 .soclk(soclk)
2862);
2863
2864
2865 // miss buffer instructions are blacked out for 2 cycles after issue.
2866 assign mbf_valid_px1 = ( misbuf_arb_vld_px1 & ~mbsel_px2 & ~mbsel_c1 ) & // 2 cycle blackout.
2867 ~wbuf_arb_full_px1; // wb can accept only 2 more reqs
2868
2869 // snpq instructions are blacked out for 4 cycles after issue.
2870 // A snoop/rdma instruction is issued one every 4 cycles at best.
2871 // In the C3 cycle of a snoop, the rdma register vld signal
2872 // will go high ( if the rdma instruction can complete ) and
2873 // prevent an instruction from issuing until the register goes low.
2874
2875 // A snoop is blacked out until, the previous snoop has had
2876 // an opportunity to set rdma_reg_vld in C4.
2877
2878
2879 assign snp_muxsel_px1 = ( snp_snpq_arb_vld_px1 &
2880 ~snpsel_px2 & ~snpsel_c1 & ~snpsel_c2 & ~snpsel_c3) // blacked out for 4 cycles.
2881 & ~misbuf_arb_snp_cnt8_px1 // no more than 8 snp entries in the mbf
2882 //& ~misbuf_arb_cnt11_px1 // no more than 11 entries in the mbf
2883 & ~tag_rdma_vld_px1 // reg_vld for stores is ~ 6 cycles and for loads is ~17 cycles
2884 & ~gate_off_prim_req_state & // csr instruction in the pipe c2 or beyond.
2885 ~gate_off_prim_req_c1; // csr instruction in C1
2886
2887l2t_arb_ctl_msff_ctl_macro__width_1 ff_l2_bypass_mode_on_d1
2888 (.dout(l2_bypass_mode_on_d1), .l1clk(l1clk),
2889 .scan_in(ff_l2_bypass_mode_on_d1_scanin),
2890 .scan_out(ff_l2_bypass_mode_on_d1_scanout),
2891 .din(csr_l2_bypass_mode_on),
2892 .siclk(siclk),
2893 .soclk(soclk)
2894);
2895
2896 // fill buffer instructions. are blacked out for 2 cycles after issue.
2897 assign fbf_valid_px1 = ( filbuf_arb_vld_px1 & ~fbsel_px2 & ~fbsel_c1 ) // 2 cycle blackout
2898 & ~(wbuf_arb_full_px1 & l2_bypass_mode_on_d1 ) ; // wb is inserted by
2899 // a fill in OFF mode.
2900
2901 assign arb_mux1_mbsel_px1 = mbf_valid_px1 ; // introduced for evctagd.
2902
2903
2904l2t_arb_ctl_msff_ctl_macro__width_1 ff_mbf_valid_px2
2905 (.dout(mbf_valid_px2), .l1clk(l1clk),
2906 .scan_in(ff_mbf_valid_px2_scanin),
2907 .scan_out(ff_mbf_valid_px2_scanout),
2908 .din(mbf_valid_px1),
2909 .siclk(siclk),
2910 .soclk(soclk)
2911);
2912
2913l2t_arb_ctl_msff_ctl_macro__width_1 ff_mbf_valid_px2_1
2914 (.dout(mbf_valid_px2_1), .l1clk(l1clk),
2915 .scan_in(ff_mbf_valid_px2_1_scanin),
2916 .scan_out(ff_mbf_valid_px2_1_scanout),
2917 .din(mbf_valid_px1),
2918 .siclk(siclk),
2919 .soclk(soclk)
2920);
2921
2922// int 5.0 changes
2923//msff_ctl_macro ff_fbf_valid_px2 (width=1)
2924// (.dout(fbf_valid_px2), .l1clk(l1clk),
2925// .din(fbf_valid_px1),
2926// .scan_in(),
2927// .scan_out()
2928//);
2929
2930l2t_arb_ctl_msff_ctl_macro__width_1 ff_fbf_valid_px2_1
2931 (.dout(fbf_valid_px2_1), .l1clk(l1clk),
2932 .scan_in(ff_fbf_valid_px2_1_scanin),
2933 .scan_out(ff_fbf_valid_px2_1_scanout),
2934 .din(fbf_valid_px1),
2935 .siclk(siclk),
2936 .soclk(soclk)
2937);
2938
2939 assign snp_valid_px1 = snp_muxsel_px1 & ~misbuf_arb_cnt28_px2_prev ;
2940
2941l2t_arb_ctl_msff_ctl_macro__width_1 ff_snp_valid_px2
2942 (.din(snp_valid_px1), .l1clk(l1clk),
2943 .scan_in(ff_snp_valid_px2_scanin),
2944 .scan_out(ff_snp_valid_px2_scanout),
2945 .dout(snp_valid_px2),
2946 .siclk(siclk),
2947 .soclk(soclk)
2948);
2949
2950l2t_arb_ctl_msff_ctl_macro__width_1 ff_snp_valid_px2_1
2951 (.din(snp_valid_px1), .l1clk(l1clk),
2952 .scan_in(ff_snp_valid_px2_1_scanin),
2953 .scan_out(ff_snp_valid_px2_1_scanout),
2954 .dout(snp_valid_px2_1),
2955 .siclk(siclk),
2956 .soclk(soclk)
2957);
2958
2959 assign mux3_bufsel_px1 = ( mbf_valid_px1 | fbf_valid_px1 | snp_valid_px1 ) &
2960 ~atm_instr_px2 ;
2961assign arb_mux3_bufsel_px1 = mux3_bufsel_px1;
2962
2963l2t_arb_ctl_msff_ctl_macro__width_1 ff_mux3_bufsel_px2
2964 (.din(mux3_bufsel_px1), .l1clk(l1clk),
2965 .scan_in(ff_mux3_bufsel_px2_scanin),
2966 .scan_out(ff_mux3_bufsel_px2_scanout),
2967 .dout(arb_mux3_bufsel_px2_unbuff),
2968 .siclk(siclk),
2969 .soclk(soclk)
2970);
2971
2972
2973//assign arb_arbadr_mux3_bufsel_px2 = arb_mux3_bufsel_px2_unbuff;
2974assign arb_arbdec_mux3_bufsel_px2 = arb_mux3_bufsel_px2_unbuff;
2975assign arb_arbdat_mux3_bufsel_px2 = arb_mux3_bufsel_px2_unbuff;
2976
2977
2978
2979
2980 // mux3 selects between the BUffer/snp instructions and the instruction from the IQ,
2981 // IQ instructions have priority only if the instruction currently in C1 is atomic with
2982 // the instruction in PX2.
2983
2984 //assign arb_mux3_bufsel_px2 = ( mbf_valid_px2_1 | fbf_valid_px2 | snp_valid_px2 ) &
2985 //~atm_instr_c1;
2986
2987
2988////////////////////////////////////////////////////////
2989// mux select for addresses
2990//////////////////////////////////////////////////////
2991
2992 // Mux1 in the arbiter selects between a Miss Buffer instruction and
2993 // a Fill. The Miss Buffer instruction has higher priority
2994
2995 assign arb_mux1_mbsel_px2 = mbf_valid_px2 ;
2996
2997 // mux2 selects between the MB/FB instruction or an external snoop
2998 // snoop has a higher priority.
2999
3000 assign arb_arbadr_mux2_snpsel_px2 = snp_valid_px2 ;
3001 assign arb_arbdat_mux2_snpsel_px2 = snp_valid_px2 ;
3002 assign arb_arbdec_mux2_snpsel_px2 = snp_valid_px2 ;
3003
3004 /////////////////////////////////////////////////////////////////////////////////////////////////
3005 // atomic instruction logic
3006 // an atomic instruction in PX2 stage of the IQ pipe will cause the PX1 instruction to be issued
3007 // immediately following it. However, if there is a stall asserted for the atomic instruction in C1,
3008 // the selection of the following instruction from the IQ is postponed until after the stall.
3009 // IQ pipeline
3010 //--------------------------------------------------------------------
3011 // PX1 PX2 C1
3012 //--------------------------------------------------------------------
3013 // atomic
3014 // attribute
3015 // bit from
3016 // IQ.
3017 //--------------------------------------------------------------------
3018 // PX2 C1 C2
3019 //--------------------------------------------------------------------
3020 // atomic
3021 // attribute
3022 // of C1 instr.
3023 // in case of
3024 // a C1 stall.
3025 //--------------------------------------------------------------------
3026 // PX1 PX2
3027 //--------------------------------------------------------------------
3028 // choose
3029 // IQ
3030 // instr.
3031 // if stall
3032 // is 0.
3033 ////////////////////////////////////////////////////////////////////////////////////////////////
3034
3035 assign atm_instr_px2 = ( ique_iq_arb_atm_px2 & iqsel_px2 ) // atomic instruction from IQ
3036 | ( atm_instr_c1 & arb_stall_c2 ) ; // C1 instruction is an atomic that is stalled.
3037
3038l2t_arb_ctl_msff_ctl_macro__width_1 ff_atm_instr_c1
3039 (.dout(atm_instr_c1), .l1clk(l1clk),
3040 .scan_in(ff_atm_instr_c1_scanin),
3041 .scan_out(ff_atm_instr_c1_scanout),
3042 .din(atm_instr_px2),
3043 .siclk(siclk),
3044 .soclk(soclk)
3045);
3046
3047 // mux3 selects between the BUffer/snp instructions and the instruction from the IQ,
3048 // IQ instructions have priority only if the instruction currently in C1 is atomic with
3049 // the instruction in PX2.
3050
3051 //assign arb_mux3_bufsel_px2 = ( mbf_valid_px2_1 | fbf_valid_px2 | snp_valid_px2 ) &
3052 //~atm_instr_c1;
3053
3054// Timing fix cloning
3055assign arb_stall_c2_clone_1 = arb_stall_unqual_c2_clone_1 & arb_inst_vld_c1_1_cloned ;
3056
3057l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_stall_c1_cloned
3058 (
3059 .scan_in(ff_arb_stall_c1_cloned_scanin),
3060 .scan_out(ff_arb_stall_c1_cloned_scanout),
3061 .din(arb_stall_c1),
3062 .l1clk(l1clk),
3063 .dout(arb_stall_unqual_c2_clone_1),
3064 .siclk(siclk),
3065 .soclk(soclk)
3066 );
3067
3068l2t_arb_ctl_msff_ctl_macro__clr_1__width_1 ff_arb_inst_vld_c1_1_clone // sync reset active low
3069 (
3070 .scan_in(ff_arb_inst_vld_c1_1_clone_scanin),
3071 .scan_out(ff_arb_inst_vld_c1_1_clone_scanout),
3072 .din(arb_inst_vld_px2),
3073 .l1clk(l1clk),
3074 .clr(~dbb_rst_l),
3075 .dout(arb_inst_vld_c1_1_cloned),
3076 .siclk(siclk),
3077 .soclk(soclk)
3078 );
3079
3080
3081
3082// assign arb_arbadr_mux4_c1sel_px2 = arb_stall_c2 & dbb_rst_l;
3083// assign arb_arbdat_mux4_c1sel_px2 = arb_stall_c2 & dbb_rst_l;
3084// assign arb_arbdec_mux4_c1sel_px2 = arb_stall_c2 & dbb_rst_l;
3085
3086assign arb_arbadr_mux4_c1sel_px2 = arb_stall_c2_clone_1 & dbb_rst_l;
3087assign arb_arbdat_mux4_c1sel_px2 = arb_stall_c2_clone_1 & dbb_rst_l;
3088assign arb_arbdec_mux4_c1sel_px2 = arb_stall_c2_clone_1 & dbb_rst_l;
3089
3090
3091 //mux selects
3092
3093
3094//////////////////////////////////////////////////////////////////////////////
3095// For ATPG : ECO ID 106991
3096//////////////////////////////////////////////////////////////////////////////
3097//assign arb_sel_tecc_addr_px2 = inc_tag_ecc_cnt_c3;
3098
3099assign arb_sel_tecc_addr_px2 = (inc_tag_ecc_cnt_c3 | tcu_scan_en);
3100
3101
3102
3103//////////////////////////////////////////////////////////////////////////////
3104
3105
3106
3107// timing fix
3108// assign arb_sel_deccck_addr_px2 = ~inc_tag_ecc_cnt_c3 & data_ecc_active_c4 ;
3109
3110// Cloning logic due for timing
3111//assign arb_sel_diag_addr_px2 = ~inc_tag_ecc_cnt_c3 & ~data_ecc_active_c4;
3112
3113assign tag_data_ecc_active_c3_inverted = ~tag_data_ecc_active_c3;
3114
3115// ECO for Atpg : 106991
3116//
3117//
3118
3119cl_u1_inv_16x arb__inv_eco_106991 (.in(tcu_scan_en), .out(
3120 tcu_scan_en_inv));
3121
3122
3123cl_u1_nand3_16x nand_arb_sel_deccck_addr_px2
3124 (
3125 .in0(~inc_tag_ecc_cnt_c3), // Fix for bug 111495
3126 .in1(~data_ecc_active_c4_n), // Fix for bug 111495
3127 .in2(tcu_scan_en_inv),
3128 .out(arb_sel_deccck_addr_px2_n)
3129 );
3130
3131cl_u1_inv_32x inv_arb_sel_deccck_addr_px2
3132 (
3133 .out (arb_sel_deccck_addr_px2),
3134 .in (arb_sel_deccck_addr_px2_n)
3135 );
3136
3137l2t_arb_ctl_msffi_ctl_macro__dmsff_16x__width_2 ff_data_ecc_active_c4_dup
3138 (
3139 .scan_in(ff_data_ecc_active_c4_dup_scanin),
3140 .scan_out(ff_data_ecc_active_c4_dup_scanout),
3141 .din({tag_data_ecc_active_c3_inverted,tag_data_ecc_active_c3}),
3142 .l1clk(l1clk),
3143 .q_l({data_ecc_active_c4_noninv,data_ecc_active_c4_n}),
3144 .siclk(siclk),
3145 .soclk(soclk)
3146 );
3147
3148l2t_arb_ctl_msffi_ctl_macro__dmsff_16x__width_2 ff_inc_tag_ecc_cnt_c3_dup
3149 (
3150 .scan_in(ff_inc_tag_ecc_cnt_c3_dup_scanin),
3151 .scan_out(ff_inc_tag_ecc_cnt_c3_dup_scanout),
3152 .din({2{inc_tag_ecc_cnt_c2}}),
3153 .l1clk(l1clk),
3154 .q_l({inc_tag_ecc_cnt_c3_1_n,inc_tag_ecc_cnt_c3_1_v2}),
3155 .siclk(siclk),
3156 .soclk(soclk)
3157 );
3158
3159// FLIP TO NOR 16x
3160
3161// ECO for Atpg : 106991
3162
3163assign arb_sel_diag_addr_px2 = (~inc_tag_ecc_cnt_c3 & tcu_scan_en_inv) & data_ecc_active_c4_n ;
3164 // Fix for bug 111495
3165
3166
3167assign arb_inc_tag_ecc_cnt_c3_n = ~inc_tag_ecc_cnt_c3 ;
3168
3169
3170
3171//////////////////////////////////////////////////////////////////////
3172// Scrub index enable :
3173// When a tecc fill is active in C2.
3174//////////////////////////////////////////////////////////////////////
3175
3176l2t_arb_ctl_msff_ctl_macro__width_1 ff_tecc_c2
3177 (.din(arbdec_arbdp_tecc_c1), .l1clk(l1clk),
3178 .scan_in(ff_tecc_c2_scanin),
3179 .scan_out(ff_tecc_c2_scanout),
3180 .dout(tecc_c2),
3181 .siclk(siclk),
3182 .soclk(soclk)
3183);
3184
3185//
3186//msff_ctl_macro ff_arb_tecc_c2_c3 (width=2) // VUAD ecc changes
3187// (.din({arbdec_arbdp_tecc_c1,arb_tecc_c2}), .l1clk(l1clk),
3188// .scan_in(ff_arb_tecc_c2_c3_scanin),
3189// .scan_out(ff_arb_tecc_c2_c3_scanout),
3190// .dout({arb_tecc_c2,arb_tecc_c3}),
3191//);
3192
3193l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_tecc_c2_c3 // VUAD ecc changes
3194 (
3195 .scan_in(ff_arb_tecc_c2_c3_scanin),
3196 .scan_out(ff_arb_tecc_c2_c3_scanout),
3197 .din(arbdec_arbdp_tecc_c1), .l1clk(l1clk),
3198 .dout(arb_tecc_c2),
3199 .siclk(siclk),
3200 .soclk(soclk)
3201 );
3202
3203
3204l2t_arb_ctl_msff_ctl_macro__width_1 ff_data_ecc_active_c4
3205 (.din(tag_data_ecc_active_c3), .l1clk(l1clk),
3206 .scan_in(ff_data_ecc_active_c4_scanin),
3207 .scan_out(ff_data_ecc_active_c4_scanout),
3208 .dout(data_ecc_active_c4),
3209 .siclk(siclk),
3210 .soclk(soclk)
3211 );
3212
3213 assign arb_data_ecc_idx_en = ( arb_fill_vld_c2 & tecc_c2 ) ;
3214 assign arb_data_ecc_idx_reset = ( ~dbb_rst_l | ~dbginit_l );
3215
3216
3217
3218 // The following mux select is used in selecting the C2 address(stalled)
3219 // over the c1 address.
3220 // The set to be scrubbed for data ecc is part of the C1 address and not
3221 // part of the stalled C2 address.
3222 assign arb_sel_c2_stall_idx_c1 = ( arb_stall_unqual_c2 & ~data_ecc_active_c4 );
3223
3224 //////////////////////////////////////////////////////////
3225 // The 3 addresses making up the stalled vuad address
3226 // are
3227 // - C1 instruction address
3228 // - DECC scrub address
3229 // - Bist address.
3230 //////////////////////////////////////////////////////////
3231
3232 //assign arb_sel_vuad_bist_px2 = ( bist_vuad_rd_en_px2 |
3233 // bist_vuad_wr_en_px2 ) ;
3234
3235
3236l2t_arb_ctl_msff_ctl_macro__width_1 ff_bist_vuad_rd_en_px1
3237 (.din(bist_vuad_rd_en_px1), .l1clk(l1clk),
3238 .scan_in(ff_bist_vuad_rd_en_px1_scanin),
3239 .scan_out(ff_bist_vuad_rd_en_px1_scanout),
3240 .dout(bist_vuad_rd_en_px2),
3241 .siclk(siclk),
3242 .soclk(soclk)
3243);
3244
3245 assign arb_sel_vuad_bist_px2 = bist_vuad_rd_en_px2 & mbist_run_r1;
3246
3247 assign arb_sel_deccck_or_bist_idx = ( data_ecc_active_c4 & ~mbist_run_r1 )|
3248 (bist_vuad_rd_en_px2 & mbist_run_r1) ;
3249
3250 // The following signal is a copy of arb_sel_deccck_or_bist_idx
3251 // and is used to disable bypassing of vuad data from the
3252 // other stages of the pipe so as to read the array output
3253
3254 assign arb_vuadctl_no_bypass_px2 = ( data_ecc_active_c4 & ~mbist_run_r1) |
3255 (bist_vuad_rd_en_px2 & mbist_run_r1 ) ;
3256
3257
3258 assign arb_vuad_idx2_sel_px2_n = ~( arb_stall_c2 | bist_vuad_rd_en_px2 |
3259 data_ecc_active_c4) ;
3260
3261 //assign sel_stall_vuad_idx = ( arb_stall_c2 |
3262 //bist_vuad_rd_en_px2 |
3263 //data_ecc_active_c4 ) ;
3264
3265
3266 ////////////////////////////////////////////////////////////////////////////////////////////
3267 // VUAD bist related signals.
3268 ////////////////////////////////////////////////////////////////////////////////////////////
3269
3270
3271l2t_arb_ctl_msff_ctl_macro__width_1 ff_bist_enable_c1
3272 (.din(bist_vuad_rd_en_px2), .l1clk(l1clk),
3273 .scan_in(ff_bist_enable_c1_scanin),
3274 .scan_out(ff_bist_enable_c1_scanout),
3275 .dout(bist_enable_c1),
3276 .siclk(siclk),
3277 .soclk(soclk)
3278);
3279
3280l2t_arb_ctl_msff_ctl_macro__width_1 ff_bist_enable_c2
3281 (.din(bist_enable_c1), .l1clk(l1clk),
3282 .scan_in(ff_bist_enable_c2_scanin),
3283 .scan_out(ff_bist_enable_c2_scanout),
3284 .dout(bist_enable_c2),
3285 .siclk(siclk),
3286 .soclk(soclk)
3287);
3288
3289
3290l2t_arb_ctl_msff_ctl_macro__width_1 ff_bist_acc_vd_px2
3291 (.din(bist_acc_vd_px1), .l1clk(l1clk),
3292 .scan_in(ff_bist_acc_vd_px2_scanin),
3293 .scan_out(ff_bist_acc_vd_px2_scanout),
3294 .dout(bist_acc_vd_px2),
3295 .siclk(siclk),
3296 .soclk(soclk)
3297);
3298
3299l2t_arb_ctl_msff_ctl_macro__width_1 ff_bist_acc_vd_c1
3300 (.din(bist_acc_vd_px2), .l1clk(l1clk),
3301 .scan_in(ff_bist_acc_vd_c1_scanin),
3302 .scan_out(ff_bist_acc_vd_c1_scanout),
3303 .dout(bist_acc_vd_c1),
3304 .siclk(siclk),
3305 .soclk(soclk)
3306);
3307
3308l2t_arb_ctl_msff_ctl_macro__width_1 ff_bist_acc_vd_c2
3309 (.din(bist_acc_vd_c1), .l1clk(l1clk),
3310 .scan_in(ff_bist_acc_vd_c2_scanin),
3311 .scan_out(ff_bist_acc_vd_c2_scanout),
3312 .dout(bist_acc_vd_c2),
3313 .siclk(siclk),
3314 .soclk(soclk)
3315);
3316
3317
3318//
3319// assign arb_acc_vd_c2 = ( arbadr_arbaddr_addr22_c2 & inst_l2vuad_vld_c2 ) |
3320// ( bist_acc_vd_c2 & bist_enable_c2 ) ;
3321//
3322// assign arb_acc_ua_c2 = ( ~arbadr_arbaddr_addr22_c2 & inst_l2vuad_vld_c2 ) |
3323// ( ~bist_acc_vd_c2 & bist_enable_c2 ) ;
3324//
3325
3326
3327assign arb_acc_ua_c2 = bist_enable_c2 ? ~bist_acc_vd_c2 :
3328 ( ~arbadr_arbaddr_addr22_c2 & inst_l2vuad_vld_c2 );
3329
3330assign arb_acc_vd_c2 = bist_enable_c2 ? bist_acc_vd_c2 :
3331 ( arbadr_arbaddr_addr22_c2 & inst_l2vuad_vld_c2 );
3332
3333
3334
3335
3336 ////////////////////////////////////////////////////////////////////////////////////////////
3337 // Mux selects for arbdata muxes
3338 ////////////////////////////////////////////////////////////////////////////////////////////
3339
3340l2t_arb_ctl_msff_ctl_macro__width_1 ff_mbist_arb_l2d_en_d1
3341 (
3342 .scan_in(ff_mbist_arb_l2d_en_d1_scanin),
3343 .scan_out(ff_mbist_arb_l2d_en_d1_scanout),
3344 .din(mbist_arb_l2d_en),
3345 .l1clk(l1clk),
3346 .dout(mbist_arb_l2d_en_d1),
3347 .siclk(siclk),
3348 .soclk(soclk)
3349 );
3350
3351
3352
3353
3354 assign arb_bist_or_diag_acc_c1 = ( inst_l2data_vld_c2 | mbist_arb_l2d_en_d1 );
3355
3356//assign arb_bist_or_diag_acc_qual_c1 = arb_bist_or_diag_acc_c1 & arb_stall_c1;
3357
3358
3359 ////////////////////////////////////////////////////////////////////////
3360 // the following signal indicates that the tag array is accessed.
3361 // It is asserted aggressively when
3362 // // mbf,fbf,snp or iq instructions are valid OR
3363 // // when there is a stalled instruction in C1 OR
3364 // // when there is a tecc, deccck or diagnostic tag access OR
3365 // // when a BIST access is performed.
3366 ////////////////////////////////////////////////////////////////////////
3367
3368 assign arb_tag_acc_px2 = ( arb_stall_c2|
3369 tecc_tag_acc_en_px2 |
3370 inst_l2tag_vld_c2 |
3371 tag_decc_tag_acc_en_px2 | // may not be reqd??????
3372 mbf_valid_px2_1 | fbf_valid_px2_1 | snp_valid_px2_1 |
3373 iqu_iq_arb_vld_px2 ) ;
3374
3375 ////////////////////////////////////////////////////////////////////////
3376 // arb_normal_tagacc_c2 is used by tagd to either select the dec
3377 // way or lru_way
3378 // Dec way is used by the following instructions
3379 // tecc, tag diagnostic access, data ecc, fill
3380 ////////////////////////////////////////////////////////////////////////
3381
3382l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_tag_acc_c1
3383 (.din(arb_tag_acc_px2), .l1clk(l1clk),
3384 .scan_in(ff_arb_tag_acc_c1_scanin),
3385 .scan_out(ff_arb_tag_acc_c1_scanout),
3386 .dout(arb_tag_acc_c1),
3387 .siclk(siclk),
3388 .soclk(soclk)
3389);
3390
3391 assign sp_tag_access_px2 = tecc_tag_acc_en_px2 | // tecc tag access
3392 inst_l2tag_vld_c2 | // diagnostic tag access
3393 tag_decc_tag_acc_en_px2 ; // decc tag access.
3394
3395l2t_arb_ctl_msff_ctl_macro__width_1 ff_sp_tag_access_c1
3396 (.din(sp_tag_access_px2), .l1clk(l1clk),
3397 .scan_in(ff_sp_tag_access_c1_scanin),
3398 .scan_out(ff_sp_tag_access_c1_scanout),
3399 .dout(sp_tag_access_c1),
3400 .siclk(siclk),
3401 .soclk(soclk)
3402);
3403
3404 assign normal_tagacc_c1= arb_tag_acc_c1
3405 & ~sp_tag_access_c1 ;
3406
3407l2t_arb_ctl_msff_ctl_macro__width_1 ff_normal_tagacc_c2
3408 (.din(normal_tagacc_c1), .l1clk(l1clk),
3409 .scan_in(ff_normal_tagacc_c2_scanin),
3410 .scan_out(ff_normal_tagacc_c2_scanout),
3411 .dout(normal_tagacc_c2),
3412 .siclk(siclk),
3413 .soclk(soclk)
3414);
3415
3416 assign arb_normal_tagacc_c2 = normal_tagacc_c2 & ~arb_fill_vld_c2 ;
3417
3418
3419 ////////////////////////////////////////////////////////////////////////
3420 // vuad rd access en
3421 // Similar to tag access expression minus
3422 // tag diagnostic access.
3423 ////////////////////////////////////////////////////////////////////////
3424
3425 assign arb_vuad_acc_px2 = ((arb_stall_c2 | tag_decc_tag_acc_en_px2 | tecc_tag_acc_en_px2 |
3426 mbf_valid_px2_1 | fbf_valid_px2_1 | snp_valid_px2_1 | iqu_iq_arb_vld_px2 ) & ~mbist_run_r1) |
3427 (bist_vuad_rd_en_px2 & mbist_run_r1) ;
3428
3429
3430
3431// assign arb_vuad_acc_px2 = ((arb_stall_c2 | tag_decc_tag_acc_en_px2 |
3432// tecc_tag_acc_en_px2 |
3433// mbf_valid_px2_1 | fbf_valid_px2_1 | snp_valid_px2_1 |
3434// iqu_iq_arb_vld_px2 | arb_vuad_acc_px2) & ~mbist_run_r1) |
3435// ( mbist_run_r1 &( bist_vuad_rd_en_px2 | arb_vuad_acc_px2));
3436
3437 ////////////////////////////////////////////////////////////////////////
3438 // mbcam is asserted for the following conditions
3439 // * PX2 instruction from the IQ is valid
3440 // * PX2 instruction from the snoop Q is valid.
3441 // * C1 instruction is stalled
3442 // In case 1 and 2 it is possible that the instruction never got issued
3443 // because of a mbf full condition or a copyback Q full condition.
3444 // However, the miss buffer cam is still asserted speculatively for
3445 // timing reasons.
3446 //
3447 // The Hit vector generated by the cam operation is appropriately
3448 // qualified in misbuf to gate off any false hits due to speculative
3449 // camming.
3450 ////////////////////////////////////////////////////////////////////////
3451
3452
3453
3454l2t_arb_ctl_msff_ctl_macro__width_3 ff_l2t_mb2_run_r1
3455 (.din({l2t_mb2_run,mbist_run,l2t_mb2_mbtag_lookup_en}), .l1clk(l1clk),
3456 .scan_in(ff_l2t_mb2_run_r1_scanin),
3457 .scan_out(ff_l2t_mb2_run_r1_scanout),
3458 .dout({l2t_mb2_run_r1,mbist_run_r1,l2t_mb2_mbtag_lookup_en_r1}),
3459 .siclk(siclk),
3460 .soclk(soclk)
3461 );
3462
3463
3464
3465 assign arb_mb_camen_px2 = l2t_mb2_run_r1 ? l2t_mb2_mbtag_lookup_en_r2 :
3466 (iqu_iq_arb_vld_px2 | snp_valid_px2_1 | arb_stall_c2);
3467
3468
3469 // Miss buffer count is a C4 flop.
3470 // Instructions in C1,C2,C3 are inflight ops that can be inserted.
3471 // //The instruction in PX2 is picked if atleast 4 entries are available in the MBF. ( mbcount <= 12)
3472 // //If PX2 is a block store atleast 11 entries should be availabe in the MBF. ( mb_count <= 5 )
3473
3474l2t_arb_ctl_msff_ctl_macro__width_1 ff_mbfull_px2
3475 (.dout(mbfull_px2), .l1clk(l1clk),
3476 .scan_in(ff_mbfull_px2_scanin),
3477 .scan_out(ff_mbfull_px2_scanout),
3478 .din(misbuf_arb_cnt28_px2_prev),
3479 .siclk(siclk),
3480 .soclk(soclk)
3481);
3482
3483
3484 assign gate_off_buf_req_px2 = ( iqu_iq_arb_vld_px2 & atm_instr_c1 ) | // iq atomic instr.
3485 gate_off_prim_req_c1 | // csr instruction in C1.
3486 oqu_arb_full_px2 | // OQ full
3487 arb_stall_c2 ; // stall
3488
3489
3490 assign mbsel_px2 = mbf_valid_px2_1 & ~snp_valid_px2_1 & dbb_rst_l &
3491 ~gate_off_buf_req_px2;
3492
3493 assign fbsel_px2 = fbf_valid_px2_1 & ~mbf_valid_px2_1 & ~snp_valid_px2_1 & dbb_rst_l &
3494 ~gate_off_buf_req_px2 ;
3495
3496
3497 assign snpsel_px2 = snp_valid_px2_1 & dbb_rst_l & ~gate_off_buf_req_px2 ;
3498 assign arb_snp_snpsel_px2 = snp_valid_px2_1 & dbb_rst_l & ~gate_off_buf_req_px2 ;
3499
3500// ////// most critical signal in this block
3501 assign iqsel_px2 = iqu_iq_arb_vld_px2 & dbb_rst_l & (
3502 ( ~( mbf_valid_px2_1 |
3503 fbf_valid_px2_1 |
3504 snp_valid_px2_1 ) // no buffer instructions.
3505 & ~mbfull_px2 & // mbf is not full
3506 ~gate_off_prim_req_c1 &
3507 ~gate_off_prim_req_state & // csr store in the pipe
3508 ~oqu_arb_full_px2 ) // oqfull in PX2
3509 | atm_instr_c1 ) & // if c1 is atomic IQ has lower priority than only stall_c1.
3510 ~arb_stall_c2 ; // stall
3511
3512// Cloning logic for timing fix
3513//assign arb_iqsel_px2 = iqsel_px2 ;
3514
3515assign arb_iqsel_px2 = iqu_iq_arb_vld_px2 & dbb_rst_l & (
3516 ( ~( mbf_valid_px2_1 | fbf_valid_px2_1 | snp_valid_px2_1 ) // no buffer instructions.
3517 & ~mbfull_px2 & // mbf is not full
3518 ~gate_off_prim_req_c1 & ~gate_off_prim_req_state & // csr store in the pipe
3519 ~oqu_arb_full_px2 ) // oqfull in PX2
3520 | atm_instr_c1 ) & // if c1 is atomic IQ has lower priority than only stall_c1.
3521 ~arb_stall_c2 ; // stall
3522
3523
3524
3525
3526assign arb_iqsel_px2_phase1 = dbb_rst_l & (
3527 ( ~( mbf_valid_px2_1 | fbf_valid_px2_1 | snp_valid_px2_1 ) // no buffer instructions.
3528 & ~mbfull_px2 & // mbf is not full
3529 ~gate_off_prim_req_c1 & ~gate_off_prim_req_state & // csr store in the pipe
3530 ~oqu_arb_full_px2 ) // oqfull in PX2
3531 | atm_instr_c1 ) & // if c1 is atomic IQ has lower priority than only stall_c1.
3532 ~arb_stall_c2 ; // stall
3533
3534// assign arb_iqsel_px2_v1 = iqu_iq_arb_vld_px2 & arb_iqsel_px2_phase1;
3535
3536cl_u1_nand2_16x nand_arb_iqsel_px2_v1_n
3537 (
3538 .out (arb_iqsel_px2_v1_n),
3539 .in0 (iqu_iq_arb_vld_px2_v1),
3540 .in1 (arb_iqsel_px2_phase1)
3541 );
3542
3543cl_u1_inv_48x inv_arb_iqsel_px2_v1
3544 (
3545 .out (arb_iqsel_px2_v1),
3546 .in (arb_iqsel_px2_v1_n)
3547 );
3548
3549l2t_arb_ctl_msff_ctl_macro__width_1 ff_mbsel_c1
3550 (.dout(mbsel_c1), .l1clk(l1clk),
3551 .scan_in(ff_mbsel_c1_scanin),
3552 .scan_out(ff_mbsel_c1_scanout),
3553 .din(mbsel_px2),
3554 .siclk(siclk),
3555 .soclk(soclk)
3556);
3557
3558 assign arb_misbuf_mbsel_c1 = mbsel_c1 ;
3559
3560// int 5.0 changes
3561//msff_ctl_macro ff_mbsel_c2 (width=1)
3562// (.dout(mbsel_c2), .l1clk(l1clk),
3563// .din(mbsel_c1),
3564// .scan_in(),
3565// .scan_out()
3566//);
3567//
3568
3569l2t_arb_ctl_msff_ctl_macro__width_1 ff_fbsel_c1
3570 (.dout(fbsel_c1), .l1clk(l1clk),
3571 .scan_in(ff_fbsel_c1_scanin),
3572 .scan_out(ff_fbsel_c1_scanout),
3573 .din(fbsel_px2),
3574 .siclk(siclk),
3575 .soclk(soclk)
3576);
3577
3578assign arb_filbuf_fbsel_c1 = fbsel_c1 ;
3579
3580// int 5.0 changes
3581//msff_ctl_macro ff_fbsel_c2 (width=1)
3582// (.dout(fbsel_c2), .l1clk(l1clk),
3583// .din(fbsel_c1),
3584// .scan_in(),
3585// .scan_out()
3586//);
3587
3588
3589l2t_arb_ctl_msff_ctl_macro__width_1 ff_snpsel_c1
3590 (.dout(snpsel_c1), .l1clk(l1clk),
3591 .scan_in(ff_snpsel_c1_scanin),
3592 .scan_out(ff_snpsel_c1_scanout),
3593 .din(snpsel_px2),
3594 .siclk(siclk),
3595 .soclk(soclk)
3596);
3597l2t_arb_ctl_msff_ctl_macro__width_1 ff_snpsel_c2
3598 (.dout(snpsel_c2), .l1clk(l1clk),
3599 .scan_in(ff_snpsel_c2_scanin),
3600 .scan_out(ff_snpsel_c2_scanout),
3601 .din(snpsel_c1),
3602 .siclk(siclk),
3603 .soclk(soclk)
3604);
3605l2t_arb_ctl_msff_ctl_macro__width_1 ff_snpsel_c3
3606 (.dout(snpsel_c3), .l1clk(l1clk),
3607 .scan_in(ff_snpsel_c3_scanin),
3608 .scan_out(ff_snpsel_c3_scanout),
3609 .din(snpsel_c2),
3610 .siclk(siclk),
3611 .soclk(soclk)
3612);
3613
3614
3615// assign arb_snpsel_c1 = snpsel_c1 ;
3616
3617////////////////////////////////////////////////////////////////
3618// mux selects for dir cam address
3619// An eviction is turned off in C3 if a
3620// parity error is detected during the eviction operation.
3621////////////////////////////////////////////////////////////////
3622
3623 assign arb_evict_vld_c2 = mbist_run_r1 ? 1'b0 : (dec_evict_c2 & arb_inst_vld_c2_6);
3624
3625 // eviction address vs normal addresses
3626l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_evict_c3
3627 (.din(arb_evict_vld_c2), .l1clk(l1clk),
3628 .scan_in(ff_arb_evict_c3_scanin),
3629 .scan_out(ff_arb_evict_c3_scanout),
3630 .dout(arb_evict_unqual_c3),
3631 .siclk(siclk),
3632 .soclk(soclk)
3633);
3634
3635 assign arb_evict_c3 = arb_evict_unqual_c3 & ~tagdp_arb_par_err_c3 & ~arb_vuad_ce_err_c3;
3636
3637l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_evict_c4
3638 (.din(arb_evict_c3), .l1clk(l1clk),
3639 .scan_in(ff_arb_evict_c4_scanin),
3640 .scan_out(ff_arb_evict_c4_scanout),
3641 .dout(arb_evict_c4),
3642 .siclk(siclk),
3643 .soclk(soclk)
3644);
3645
3646l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_evict_c5
3647 (.din(arb_evict_c4), .l1clk(l1clk),
3648 .scan_in(ff_arb_evict_c5_scanin),
3649 .scan_out(ff_arb_evict_c5_scanout),
3650 .dout(arb_evict_c5),
3651 .siclk(siclk),
3652 .soclk(soclk)
3653);
3654
3655
3656
3657 assign arb_imiss_vld_c2 = mbist_run_r1 ? 1'b0 : arb_decdp_imiss_inst_c2 & arb_inst_vld_c2_6 ;
3658
3659
3660l2t_arb_ctl_msff_ctl_macro__width_1 ff_imiss_inst_c3
3661 (.din(arb_decdp_imiss_inst_c2), .l1clk(l1clk),
3662 .scan_in(ff_imiss_inst_c3_scanin),
3663 .scan_out(ff_imiss_inst_c3_scanout),
3664 .dout(imiss_inst_c3),
3665 .siclk(siclk),
3666 .soclk(soclk)
3667);
3668
3669 assign imiss_hit_c3 = imiss_inst_c3 & tag_hit_l2orfb_c3 ;
3670
3671 // c4 vs c3 addresses.
3672l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c4
3673 (.din(imiss_hit_c3), .l1clk(l1clk),
3674 .scan_in(ff_arb_imiss_hit_c4_scanin),
3675 .scan_out(ff_arb_imiss_hit_c4_scanout),
3676 .dout(arb_imiss_hit_c4),
3677 .siclk(siclk),
3678 .soclk(soclk)
3679);
3680
3681
3682////////////////////////////////////////////////////////////////
3683// mux selects for imiss address for err
3684// reporting.
3685// Used to determine if the C7 or C8 address should be chosen for error logging.
3686////////////////////////////////////////////////////////////////
3687
3688l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c5
3689 (.din(arb_imiss_hit_c4), .l1clk(l1clk),
3690 .scan_in(ff_arb_imiss_hit_c5_scanin),
3691 .scan_out(ff_arb_imiss_hit_c5_scanout),
3692 .dout(arb_imiss_hit_c5),
3693 .siclk(siclk),
3694 .soclk(soclk)
3695);
3696
3697// BS 03/11/04 extra cycle for mem access
3698
3699l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c52
3700 (.din(arb_imiss_hit_c5), .l1clk(l1clk),
3701 .scan_in(ff_arb_imiss_hit_c52_scanin),
3702 .scan_out(ff_arb_imiss_hit_c52_scanout),
3703 .dout(arb_imiss_hit_c52),
3704 .siclk(siclk),
3705 .soclk(soclk)
3706);
3707
3708l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c6
3709 (.din(arb_imiss_hit_c52), .l1clk(l1clk),
3710 .scan_in(ff_arb_imiss_hit_c6_scanin),
3711 .scan_out(ff_arb_imiss_hit_c6_scanout),
3712 .dout(arb_imiss_hit_c6),
3713 .siclk(siclk),
3714 .soclk(soclk)
3715);
3716
3717l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c7
3718 (.din(arb_imiss_hit_c6), .l1clk(l1clk),
3719 .scan_in(ff_arb_imiss_hit_c7_scanin),
3720 .scan_out(ff_arb_imiss_hit_c7_scanout),
3721 .dout(arb_imiss_hit_c7),
3722 .siclk(siclk),
3723 .soclk(soclk)
3724);
3725
3726l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c8
3727 (.din(arb_imiss_hit_c7), .l1clk(l1clk),
3728 .scan_in(ff_arb_imiss_hit_c8_scanin),
3729 .scan_out(ff_arb_imiss_hit_c8_scanout),
3730 .dout(arb_imiss_hit_c8),
3731 .siclk(siclk),
3732 .soclk(soclk)
3733);
3734
3735l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c9
3736 (.din(arb_imiss_hit_c8), .l1clk(l1clk),
3737 .scan_in(ff_arb_imiss_hit_c9_scanin),
3738 .scan_out(ff_arb_imiss_hit_c9_scanout),
3739 .dout(arb_imiss_hit_c9),
3740 .siclk(siclk),
3741 .soclk(soclk)
3742);
3743
3744l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_imiss_hit_c10
3745 (.din(arb_imiss_hit_c9), .l1clk(l1clk),
3746 .scan_in(ff_arb_imiss_hit_c10_scanin),
3747 .scan_out(ff_arb_imiss_hit_c10_scanout),
3748 .dout(arb_imiss_hit_c10),
3749 .siclk(siclk),
3750 .soclk(soclk)
3751);
3752
3753 ////////////////////////////////////////////////////////////////////
3754 // Decode based on address.
3755 ////////////////////////////////////////////////////////////////////
3756
3757 // Fix for bug#3789
3758 // an interrupt issued with a diagnostic address is not
3759 // marked as a diagnostic instruction.
3760
3761 assign arb_inst_diag_c1 = arb_inst_vld_c1_1 &
3762 ~( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `INT_RQ ) &
3763 // int 5.0 changes
3764 // ( arbadr_arbdp_ioaddr_c1[39:37] == 3'h5 ); // A0-BF
3765 ( arbadr_arbdp_ioaddr_c1_39to37[39:37] == 3'h5 ); // A0-BF
3766
3767
3768l2t_arb_ctl_msff_ctl_macro__width_2 ff_arb_inst_diag_c2 // VUAD ecc changes
3769 (.din({arb_inst_diag_c1,decdp_inst_int_or_inval_c1}), .l1clk(l1clk),
3770 .scan_in(ff_arb_inst_diag_c2_scanin),
3771 .scan_out(ff_arb_inst_diag_c2_scanout),
3772 .dout({arb_inst_diag_c2,decdp_inst_int_or_inval_c2}),
3773 .siclk(siclk),
3774 .soclk(soclk)
3775);
3776
3777 //assign arb_int_or_diag_acc_c1 = ( arb_inst_diag_c1 |
3778 //decdp_inst_int_or_inval_c1 ) ; // all instructions that do not insert in mbf
3779
3780 //A8 and above.
3781 assign arb_inst_csr_c1 = arb_inst_diag_c1 &
3782 // int 5.0 changes arbadr_arbdp_ioaddr_c1[35] ;
3783 arbadr_arbdp_ioaddr_c1_35to33[35];
3784
3785l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_csr_c1
3786 (.din(arb_inst_csr_c1), .l1clk(l1clk),
3787 .scan_in(ff_arb_inst_csr_c1_scanin),
3788 .scan_out(ff_arb_inst_csr_c1_scanout),
3789 .dout(arb_inst_csr_c2),
3790 .siclk(siclk),
3791 .soclk(soclk)
3792);
3793
3794 // A0, A1, A2, A3
3795 assign arb_inst_l2data_c1 = arb_inst_diag_c1 &
3796 // int 5.0 changes ~arbadr_arbdp_ioaddr_c1[35] & ~arbadr_arbdp_ioaddr_c1[34] ;
3797 ~arbadr_arbdp_ioaddr_c1_35to33[35] & ~arbadr_arbdp_ioaddr_c1_35to33[34] ;
3798
3799l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_l2data_c2
3800 (.din(arb_inst_l2data_c1), .l1clk(l1clk),
3801 .scan_in(ff_arb_inst_l2data_c2_scanin),
3802 .scan_out(ff_arb_inst_l2data_c2_scanout),
3803 .dout(arb_inst_l2data_c2),
3804 .siclk(siclk),
3805 .soclk(soclk)
3806);
3807
3808 assign inst_l2data_vld_c2 = arb_inst_l2data_c2 & arb_inst_vld_c2_6;
3809
3810l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2data_vld_c3
3811 (.din(inst_l2data_vld_c2), .l1clk(l1clk),
3812 .scan_in(ff_inst_l2data_vld_c3_scanin),
3813 .scan_out(ff_inst_l2data_vld_c3_scanout),
3814 .dout(inst_l2data_vld_c3),
3815 .siclk(siclk),
3816 .soclk(soclk)
3817);
3818l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2data_vld_c4
3819 (.din(inst_l2data_vld_c3), .l1clk(l1clk),
3820 .scan_in(ff_inst_l2data_vld_c4_scanin),
3821 .scan_out(ff_inst_l2data_vld_c4_scanout),
3822 .dout(inst_l2data_vld_c4),
3823 .siclk(siclk),
3824 .soclk(soclk)
3825);
3826l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2data_vld_c5
3827 (.din(inst_l2data_vld_c4), .l1clk(l1clk),
3828 .scan_in(ff_inst_l2data_vld_c5_scanin),
3829 .scan_out(ff_inst_l2data_vld_c5_scanout),
3830 .dout(inst_l2data_vld_c5),
3831 .siclk(siclk),
3832 .soclk(soclk)
3833);
3834
3835// BS 03/11/04 extra cycle for mem access
3836
3837l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2data_vld_c52
3838 (.din(inst_l2data_vld_c5), .l1clk(l1clk),
3839 .scan_in(ff_inst_l2data_vld_c52_scanin),
3840 .scan_out(ff_inst_l2data_vld_c52_scanout),
3841 .dout(inst_l2data_vld_c52),
3842 .siclk(siclk),
3843 .soclk(soclk)
3844);
3845
3846l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2data_vld_c6
3847 (.din(inst_l2data_vld_c52), .l1clk(l1clk),
3848 .scan_in(ff_inst_l2data_vld_c6_scanin),
3849 .scan_out(ff_inst_l2data_vld_c6_scanout),
3850 .dout(inst_l2data_vld_c6),
3851 .siclk(siclk),
3852 .soclk(soclk)
3853);
3854
3855 assign arb_inst_l2data_vld_c6 = inst_l2data_vld_c6 ;
3856
3857 //////////////////////////////////////////
3858 // csr store signal is used to
3859 // enqueue or dequeue an instruction from
3860 // the miss buffer.
3861 //////////////////////////////////////////
3862
3863
3864 assign arb_csr_st_c2 = arb_inst_csr_c2 & decdp_st_inst_c2_1 ;
3865
3866
3867
3868 assign arb_csr_wr_en_c2 = arb_csr_st_c2 &
3869 arbdec_arbdp_inst_mb_c2 &
3870 arb_inst_vld_c2_6 ;
3871
3872l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c3
3873 (.din(arb_csr_wr_en_c2), .l1clk(l1clk),
3874 .scan_in(ff_arb_csr_wr_en_c3_scanin),
3875 .scan_out(ff_arb_csr_wr_en_c3_scanout),
3876 .dout(arb_csr_wr_en_c3),
3877 .siclk(siclk),
3878 .soclk(soclk)
3879);
3880
3881l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c3_1
3882 (.din(arb_csr_wr_en_c2), .l1clk(l1clk),
3883 .scan_in(ff_arb_csr_wr_en_c3_1_scanin),
3884 .scan_out(ff_arb_csr_wr_en_c3_1_scanout),
3885 .dout(arb_csr_wr_en_c3_1),
3886 .siclk(siclk),
3887 .soclk(soclk)
3888);
3889
3890
3891l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c4
3892 (.din(arb_csr_wr_en_c3_1), .l1clk(l1clk),
3893 .scan_in(ff_arb_csr_wr_en_c4_scanin),
3894 .scan_out(ff_arb_csr_wr_en_c4_scanout),
3895 .dout(arb_csr_wr_en_c4),
3896 .siclk(siclk),
3897 .soclk(soclk)
3898);
3899l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c5
3900 (.din(arb_csr_wr_en_c4), .l1clk(l1clk),
3901 .scan_in(ff_arb_csr_wr_en_c5_scanin),
3902 .scan_out(ff_arb_csr_wr_en_c5_scanout),
3903 .dout(arb_csr_wr_en_c5),
3904 .siclk(siclk),
3905 .soclk(soclk)
3906);
3907
3908// BS 03/11/04 extra cycle for mem access
3909
3910l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c52
3911 (.din(arb_csr_wr_en_c5), .l1clk(l1clk),
3912 .scan_in(ff_arb_csr_wr_en_c52_scanin),
3913 .scan_out(ff_arb_csr_wr_en_c52_scanout),
3914 .dout(arb_csr_wr_en_c52),
3915 .siclk(siclk),
3916 .soclk(soclk)
3917);
3918
3919l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c6
3920 (.din(arb_csr_wr_en_c52), .l1clk(l1clk),
3921 .scan_in(ff_arb_csr_wr_en_c6_scanin),
3922 .scan_out(ff_arb_csr_wr_en_c6_scanout),
3923 .dout(arb_csr_wr_en_c6),
3924 .siclk(siclk),
3925 .soclk(soclk)
3926);
3927l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c7
3928 (.din(arb_csr_wr_en_c6), .l1clk(l1clk),
3929 .scan_in(ff_arb_csr_wr_en_c7_scanin),
3930 .scan_out(ff_arb_csr_wr_en_c7_scanout),
3931 .dout(arb_csr_wr_en_c7),
3932 .siclk(siclk),
3933 .soclk(soclk)
3934);
3935l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_wr_en_c8
3936 (.din(arb_csr_wr_en_c7), .l1clk(l1clk),
3937 .scan_in(ff_arb_csr_wr_en_c8_scanin),
3938 .scan_out(ff_arb_csr_wr_en_c8_scanout),
3939 .dout(arb_csr_wr_en_c8),
3940 .siclk(siclk),
3941 .soclk(soclk)
3942);
3943
3944
3945 assign arb_csr_rd_en_c2 = arb_inst_csr_c2 & arb_decdp_ld_inst_c2 &
3946 arb_inst_vld_c2_6;
3947
3948l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_rd_en_c3
3949 (.din(arb_csr_rd_en_c2), .l1clk(l1clk),
3950 .scan_in(ff_arb_csr_rd_en_c3_scanin),
3951 .scan_out(ff_arb_csr_rd_en_c3_scanout),
3952 .dout(arb_csr_rd_en_c3),
3953 .siclk(siclk),
3954 .soclk(soclk)
3955);
3956l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_rd_en_c4
3957 (.din(arb_csr_rd_en_c3), .l1clk(l1clk),
3958 .scan_in(ff_arb_csr_rd_en_c4_scanin),
3959 .scan_out(ff_arb_csr_rd_en_c4_scanout),
3960 .dout(arb_csr_rd_en_c4),
3961 .siclk(siclk),
3962 .soclk(soclk)
3963);
3964l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_rd_en_c5
3965 (.din(arb_csr_rd_en_c4), .l1clk(l1clk),
3966 .scan_in(ff_arb_csr_rd_en_c5_scanin),
3967 .scan_out(ff_arb_csr_rd_en_c5_scanout),
3968 .dout(arb_csr_rd_en_c5),
3969 .siclk(siclk),
3970 .soclk(soclk)
3971);
3972
3973// BS 03/11/04 extra cycle for mem access
3974l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_rd_en_c52
3975 (.din(arb_csr_rd_en_c5), .l1clk(l1clk),
3976 .scan_in(ff_arb_csr_rd_en_c52_scanin),
3977 .scan_out(ff_arb_csr_rd_en_c52_scanout),
3978 .dout(arb_csr_rd_en_c52),
3979 .siclk(siclk),
3980 .soclk(soclk)
3981);
3982
3983l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_rd_en_c6
3984 (.din(arb_csr_rd_en_c52), .l1clk(l1clk),
3985 .scan_in(ff_arb_csr_rd_en_c6_scanin),
3986 .scan_out(ff_arb_csr_rd_en_c6_scanout),
3987 .dout(arb_csr_rd_en_c6),
3988 .siclk(siclk),
3989 .soclk(soclk)
3990);
3991l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_csr_rd_en_c7
3992 (.din(arb_csr_rd_en_c6), .l1clk(l1clk),
3993 .scan_in(ff_arb_csr_rd_en_c7_scanin),
3994 .scan_out(ff_arb_csr_rd_en_c7_scanout),
3995 .dout(arb_csr_rd_en_c7),
3996 .siclk(siclk),
3997 .soclk(soclk)
3998);
3999
4000 ////////////////////////
4001 // data diagnostic store for R/W calculation
4002 ////////////////////////
4003 assign arb_data_diag_st_c2 = inst_l2data_vld_c2 & decdp_st_inst_c2_1 ;
4004
4005
4006 // A4 or A5
4007 assign arb_inst_l2tag_c1 = arb_inst_diag_c1 &
4008// int 5.0 changes ~arbadr_arbdp_ioaddr_c1[35] & arbadr_arbdp_ioaddr_c1[34] &
4009// ~arbadr_arbdp_ioaddr_c1[33] ;
4010 ~arbadr_arbdp_ioaddr_c1_35to33[35] & arbadr_arbdp_ioaddr_c1_35to33[34] &
4011 ~arbadr_arbdp_ioaddr_c1_35to33[33];
4012
4013
4014l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_l2tag_c2
4015 (.din(arb_inst_l2tag_c1), .l1clk(l1clk),
4016 .scan_in(ff_arb_inst_l2tag_c2_scanin),
4017 .scan_out(ff_arb_inst_l2tag_c2_scanout),
4018 .dout(arb_inst_l2tag_c2),
4019 .siclk(siclk),
4020 .soclk(soclk)
4021);
4022
4023 assign inst_l2tag_vld_c2 = arb_inst_l2tag_c2 & arb_inst_vld_c2_6 ;
4024
4025l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_l2tag_c2_1
4026 (.din(arb_inst_l2tag_c1), .l1clk(l1clk),
4027 .scan_in(ff_arb_inst_l2tag_c2_1_scanin),
4028 .scan_out(ff_arb_inst_l2tag_c2_1_scanout),
4029 .dout(arb_inst_l2tag_c2_1),
4030 .siclk(siclk),
4031 .soclk(soclk)
4032);
4033
4034 assign inst_l2tag_vld_c2_1 = arb_inst_l2tag_c2_1 & arb_inst_vld_c2_6 ;
4035
4036l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2tag_vld_c3
4037 (.din(inst_l2tag_vld_c2), .l1clk(l1clk),
4038 .scan_in(ff_inst_l2tag_vld_c3_scanin),
4039 .scan_out(ff_inst_l2tag_vld_c3_scanout),
4040 .dout(inst_l2tag_vld_c3),
4041 .siclk(siclk),
4042 .soclk(soclk)
4043);
4044
4045l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2tag_vld_c4
4046 (.din(inst_l2tag_vld_c3), .l1clk(l1clk),
4047 .scan_in(ff_inst_l2tag_vld_c4_scanin),
4048 .scan_out(ff_inst_l2tag_vld_c4_scanout),
4049 .dout(inst_l2tag_vld_c4),
4050 .siclk(siclk),
4051 .soclk(soclk)
4052);
4053
4054 assign arb_l2tag_vld_c4 = inst_l2tag_vld_c4 ; // to tagd.
4055
4056l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2tag_vld_c5
4057 (.din(inst_l2tag_vld_c4), .l1clk(l1clk),
4058 .scan_in(ff_inst_l2tag_vld_c5_scanin),
4059 .scan_out(ff_inst_l2tag_vld_c5_scanout),
4060 .dout(inst_l2tag_vld_c5),
4061 .siclk(siclk),
4062 .soclk(soclk)
4063);
4064
4065// BS 03/11/04 extra cycle for mem access
4066
4067l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2tag_vld_c52
4068 (.din(inst_l2tag_vld_c5), .l1clk(l1clk),
4069 .scan_in(ff_inst_l2tag_vld_c52_scanin),
4070 .scan_out(ff_inst_l2tag_vld_c52_scanout),
4071 .dout(inst_l2tag_vld_c52),
4072 .siclk(siclk),
4073 .soclk(soclk)
4074);
4075
4076
4077l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2tag_vld_c6
4078 (.din(inst_l2tag_vld_c52), .l1clk(l1clk),
4079 .scan_in(ff_inst_l2tag_vld_c6_scanin),
4080 .scan_out(ff_inst_l2tag_vld_c6_scanout),
4081 .dout(inst_l2tag_vld_c6),
4082 .siclk(siclk),
4083 .soclk(soclk)
4084);
4085
4086
4087 assign arb_inst_l2tag_vld_c6 = inst_l2tag_vld_c6 ;
4088
4089
4090
4091 // A6 or A7
4092 assign arb_inst_l2vuad_c1 = arb_inst_diag_c1 &
4093
4094// int 5.0 changes ~arbadr_arbdp_ioaddr_c1[35] & arbadr_arbdp_ioaddr_c1[34] &
4095// arbadr_arbdp_ioaddr_c1[33];
4096 ~arbadr_arbdp_ioaddr_c1_35to33[35] & arbadr_arbdp_ioaddr_c1_35to33[34] &
4097 arbadr_arbdp_ioaddr_c1_35to33[33];
4098
4099l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_l2vuad_c2
4100 (.din(arb_inst_l2vuad_c1), .l1clk(l1clk),
4101 .scan_in(ff_arb_inst_l2vuad_c2_scanin),
4102 .scan_out(ff_arb_inst_l2vuad_c2_scanout),
4103 .dout(arb_inst_l2vuad_c2),
4104 .siclk(siclk),
4105 .soclk(soclk)
4106 );
4107
4108assign inst_l2vuad_vld_c2 = arb_inst_l2vuad_c2 & arb_inst_vld_c2_7 & ~mbist_run_r1;
4109
4110l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2vuad_vld_c3
4111 (.din(inst_l2vuad_vld_c2), .l1clk(l1clk),
4112 .scan_in(ff_inst_l2vuad_vld_c3_scanin),
4113 .scan_out(ff_inst_l2vuad_vld_c3_scanout),
4114 .dout(inst_l2vuad_vld_c3),
4115 .siclk(siclk),
4116 .soclk(soclk)
4117);
4118
4119 assign arb_inst_l2vuad_vld_c3 = inst_l2vuad_vld_c3 ;
4120
4121l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2vuad_vld_c4
4122 (.din(inst_l2vuad_vld_c3), .l1clk(l1clk),
4123 .scan_in(ff_inst_l2vuad_vld_c4_scanin),
4124 .scan_out(ff_inst_l2vuad_vld_c4_scanout),
4125 .dout(inst_l2vuad_vld_c4),
4126 .siclk(siclk),
4127 .soclk(soclk)
4128);
4129
4130l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2vuad_vld_c5
4131 (.din(inst_l2vuad_vld_c4), .l1clk(l1clk),
4132 .scan_in(ff_inst_l2vuad_vld_c5_scanin),
4133 .scan_out(ff_inst_l2vuad_vld_c5_scanout),
4134 .dout(inst_l2vuad_vld_c5),
4135 .siclk(siclk),
4136 .soclk(soclk)
4137);
4138
4139// BS 03/11/04 extra cycle for mem access
4140
4141l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2vuad_vld_c52
4142 (.din(inst_l2vuad_vld_c5), .l1clk(l1clk),
4143 .scan_in(ff_inst_l2vuad_vld_c52_scanin),
4144 .scan_out(ff_inst_l2vuad_vld_c52_scanout),
4145 .dout(inst_l2vuad_vld_c52),
4146 .siclk(siclk),
4147 .soclk(soclk)
4148);
4149
4150
4151l2t_arb_ctl_msff_ctl_macro__width_1 ff_inst_l2vuad_vld_c6
4152 (.din(inst_l2vuad_vld_c52), .l1clk(l1clk),
4153 .scan_in(ff_inst_l2vuad_vld_c6_scanin),
4154 .scan_out(ff_inst_l2vuad_vld_c6_scanout),
4155 .dout(inst_l2vuad_vld_c6),
4156 .siclk(siclk),
4157 .soclk(soclk)
4158);
4159
4160
4161 assign arb_inst_l2vuad_vld_c6 = inst_l2vuad_vld_c6 ;
4162
4163 assign arb_diag_complete_c3 = inst_l2vuad_vld_c3 |
4164 inst_l2tag_vld_c3 |
4165 inst_l2data_vld_c3;
4166
4167
4168
4169
4170////////////////////////////////////////////////////////////
4171// refer to scrub pipeline
4172// The following signal tag_deccck_data_sel_c8 is used to
4173// select between store data and deccck scrub data.
4174/////////////////////////////////////////////////////////////
4175l2t_arb_ctl_msff_ctl_macro__width_1 ff_deccck_data_sel_c9
4176 (.din(tag_deccck_data_sel_c8), .l1clk(l1clk),
4177 .scan_in(ff_deccck_data_sel_c9_scanin),
4178 .scan_out(ff_deccck_data_sel_c9_scanout),
4179 .dout(arb_decc_data_sel_c9),
4180 .siclk(siclk),
4181 .soclk(soclk)
4182);
4183
4184
4185
4186
4187 ////////////////////////////////////////////////////////////////////////////
4188 // CAs compare results and control signal
4189 // to misbuf.
4190 // arb_misbuf_ctrue_c9 is the compare result.
4191 // arb_misbuf_cas1_hit_c8 is the qualifier.
4192 ////////////////////////////////////////////////////////////////////////////
4193
4194 assign lower_cas_c8 = arbdec_size_field_c8[1] & ~arbdec_size_field_c8[0] & arbadr_addr2_c8 ;
4195
4196l2t_arb_ctl_msff_ctl_macro__width_1 ff_lower_cas_c9
4197 (.din(lower_cas_c8), .l1clk(l1clk),
4198 .scan_in(ff_lower_cas_c9_scanin),
4199 .scan_out(ff_lower_cas_c9_scanout),
4200 .dout(lower_cas_c9),
4201 .siclk(siclk),
4202 .soclk(soclk)
4203);
4204
4205 assign upper_cas_c8 = ~arbdec_size_field_c8[1] & arbdec_size_field_c8[0] & ~arbadr_addr2_c8 ;
4206 // BS and SR 11/12/03 N2 Xbar Packet format change
4207
4208l2t_arb_ctl_msff_ctl_macro__width_1 ff_upper_cas_c9
4209 (.din(upper_cas_c8), .l1clk(l1clk),
4210 .scan_in(ff_upper_cas_c9_scanin),
4211 .scan_out(ff_upper_cas_c9_scanout),
4212 .dout(upper_cas_c9),
4213 .siclk(siclk),
4214 .soclk(soclk)
4215);
4216
4217
4218l2t_arb_ctl_msff_ctl_macro__width_1 ff_word_lower_cmp_c9
4219 (.din(arbdat_word_lower_cmp_c8), .l1clk(l1clk),
4220 .scan_in(ff_word_lower_cmp_c9_scanin),
4221 .scan_out(ff_word_lower_cmp_c9_scanout),
4222 .dout(word_lower_cmp_c9),
4223 .siclk(siclk),
4224 .soclk(soclk)
4225);
4226
4227l2t_arb_ctl_msff_ctl_macro__width_1 ff_word_upper_cmp_c9
4228 (.din(arbdat_word_upper_cmp_c8), .l1clk(l1clk),
4229 .scan_in(ff_word_upper_cmp_c9_scanin),
4230 .scan_out(ff_word_upper_cmp_c9_scanout),
4231 .dout(word_upper_cmp_c9),
4232 .siclk(siclk),
4233 .soclk(soclk)
4234);
4235
4236
4237 assign cmp_lower_c9 = word_lower_cmp_c9 & lower_cas_c9;
4238
4239 assign cmp_upper_c9 = word_upper_cmp_c9 & upper_cas_c9;
4240
4241 assign cmp_dword_c9 = word_lower_cmp_c9 & word_upper_cmp_c9 ;
4242
4243 assign arb_misbuf_ctrue_c9 = ( cmp_dword_c9 | cmp_lower_c9 | cmp_upper_c9 ) ;
4244
4245 assign arb_misbuf_cas1_hit_c8 = decdp_cas1_inst_c8 & hit_l2orfb_c8 ;
4246
4247
4248 ////////////////////////////////////////////////////////////////////////////////////
4249 // tecc count is maintained
4250 // here. The tag ecc pipeline is as follows.
4251 //
4252 //--------------------------------------------------------
4253 // C1(tecc inst C2(setup tag read
4254 // from mb or of corrupted
4255 // snpiQ) idx
4256 //
4257 // store affected
4258 // idx in arbaddr
4259 //
4260 // start
4261 // counting.
4262 //--------------------------------------------------------
4263 //
4264 //
4265 //-------------------------------------------------------------------------------
4266 // count<2:0> 1(px2) 2(c1) 3(c2) 4(c3) 5(c4) 6(px2) 7(c1) 8
4267 //-------------------------------------------------------------------------------
4268 // action setup tagrd setup mux corre setup tagwr do nothing
4269 // idx muxsel tag tag wr
4270 // idx
4271 //-------------------------------------------------------------------------------
4272 // STALL lasts for 128 cycles.
4273 // When the counter is 1 or 6, the tag_acc_px2 needs to be enabled
4274 // for a tagecc operation. If an instruction is present in C1, the
4275 // tag will be enabled for the entire duration of the tag ecc operation.
4276 ////////////////////////////////////////////////////////////////////////////////////
4277
4278
4279
4280
4281l2t_arb_ctl_msff_ctl_macro__width_1 ff_tecc_inst_c2
4282 (.din(arbdp_tecc_inst_c1), .l1clk(l1clk),
4283 .scan_in(ff_tecc_inst_c2_scanin),
4284 .scan_out(ff_tecc_inst_c2_scanout),
4285 .dout(tecc_inst_c2),
4286 .siclk(siclk),
4287 .soclk(soclk)
4288);
4289
4290// int 5.0 changes
4291
4292 assign inc_tag_ecc_cnt_c2 = ( tecc_inst_c2 & arb_inst_vld_c2_7 ) |
4293 (|( tecc_st_cnt )) ;
4294
4295
4296l2t_arb_ctl_msff_ctl_macro__width_1 ff_inc_tag_ecc_cnt_c3
4297 (.din(inc_tag_ecc_cnt_c2), .l1clk(l1clk),
4298 .scan_in(ff_inc_tag_ecc_cnt_c3_scanin),
4299 .scan_out(ff_inc_tag_ecc_cnt_c3_scanout),
4300 .dout(inc_tag_ecc_cnt_c3),
4301 .siclk(siclk),
4302 .soclk(soclk)
4303);
4304
4305 assign tecc_st_cnt_plus1 = tecc_st_cnt + 8'b1 ;
4306
4307 assign tecc_st_cnt_reset = ~dbb_rst_l |
4308 ~dbginit_l |
4309 (tecc_st_cnt == 8'b1111111 );
4310
4311l2t_arb_ctl_msff_ctl_macro__clr_1__en_1__width_8 ff_tag_ecc_fsm_count // sync reset active high
4312 (.din(tecc_st_cnt_plus1[7:0]),
4313 .scan_in(ff_tag_ecc_fsm_count_scanin),
4314 .scan_out(ff_tag_ecc_fsm_count_scanout),
4315 .en(inc_tag_ecc_cnt_c2), .l1clk(l1clk), .clr(tecc_st_cnt_reset),
4316 .dout(tecc_st_cnt[7:0]),
4317 .siclk(siclk),
4318 .soclk(soclk)
4319);
4320
4321
4322// int 5.0 changes
4323// msff_ctl_macro ff_arb_tecc_way_c2 (width=4,en=1,clr=1) // sync reset active high
4324// (.din(tecc_st_cnt_plus1[6:3]),
4325// .en(inc_tag_ecc_cnt_c2), .l1clk(l1clk), .clr(tecc_st_cnt_reset),
4326// .dout(arb_tecc_way_c2[3:0]),
4327// .scan_in(),
4328// .scan_out()
4329//);
4330
4331assign arb_tecc_way_c2 = tecc_st_cnt[6:3] ; // tecc way // int 5.0 changes
4332
4333assign scrub_fsm_count_eq_5_px1 = (tecc_st_cnt[2:0] == 3'd5) ;
4334
4335l2t_arb_ctl_msff_ctl_macro__width_1 ff_scrub_fsm_count_eq_6_px2
4336 (.din(scrub_fsm_count_eq_5_px1),
4337 .scan_in(ff_scrub_fsm_count_eq_6_px2_scanin),
4338 .scan_out(ff_scrub_fsm_count_eq_6_px2_scanout),
4339 .l1clk(l1clk),
4340 .dout(scrub_fsm_count_eq_6_px2),
4341 .siclk(siclk),
4342 .soclk(soclk)
4343);
4344
4345 assign scrub_fsm_count_eq_0_px1 = (tecc_st_cnt[2:0] == 3'd0) &
4346 inc_tag_ecc_cnt_c2 ;
4347
4348l2t_arb_ctl_msff_ctl_macro__width_1 ff_scrub_fsm_count_eq_1_px2
4349 (.din(scrub_fsm_count_eq_0_px1),
4350 .scan_in(ff_scrub_fsm_count_eq_1_px2_scanin),
4351 .scan_out(ff_scrub_fsm_count_eq_1_px2_scanout),
4352 .l1clk(l1clk),
4353 .dout(scrub_fsm_count_eq_1_px2),
4354 .siclk(siclk),
4355 .soclk(soclk)
4356);
4357
4358
4359
4360 assign tecc_tag_acc_en_px1 = (( tecc_st_cnt[2:0] == 3'd0 ) & inc_tag_ecc_cnt_c2 ) |
4361 ( tecc_st_cnt[2:0] == 3'd5 );
4362
4363l2t_arb_ctl_msff_ctl_macro__width_1 ff_tecc_tag_acc_en_px2
4364 (.din(tecc_tag_acc_en_px1), .l1clk(l1clk),
4365 .scan_in(ff_tecc_tag_acc_en_px2_scanin),
4366 .scan_out(ff_tecc_tag_acc_en_px2_scanout),
4367 .dout(tecc_tag_acc_en_px2),
4368 .siclk(siclk),
4369 .soclk(soclk)
4370);
4371
4372 assign arb_tagd_tecc_c1 = ( tecc_st_cnt[2:0] == 3'd2 );
4373
4374
4375l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_tagd_tecc_c2
4376 (.din(arb_tagd_tecc_c1), .l1clk(l1clk),
4377 .scan_in(ff_arb_tagd_tecc_c2_scanin),
4378 .scan_out(ff_arb_tagd_tecc_c2_scanout),
4379 .dout(arb_tagd_tecc_c2),
4380 .siclk(siclk),
4381 .soclk(soclk)
4382);
4383
4384
4385// int 5.0 changes
4386// assign arb_tecc_way_c2 = tecc_st_cnt[6:3] ; // tecc way.
4387
4388
4389 ///////////////////////////////////////////////////////////////////////
4390 // tag is written if
4391 // - a Fill instruction is allowed to issue in PX2 and is not superceded
4392 // by a stall condition or diag/tecc/deccck active.
4393 // - A diagnostic tag write in C2
4394 // _ Tecc tag write state.
4395 // - Fill stalled in C1 but not superceded by diag/tecc/deccck active.
4396 ////////////////////////////////////////////////////////////////////////
4397
4398
4399
4400 // Used to select between the way and wrdata of a C1 instruction vs
4401 // a tecc or diagnostic instruction.
4402 assign arb_diag_or_tecc_write_px2 = (decdp_st_inst_c2_1 & inst_l2tag_vld_c2_1 ) |
4403 scrub_fsm_count_eq_6_px2 ;
4404
4405 assign diag_or_scr_way_sel = inst_l2tag_vld_c2_1 | scrub_fsm_count_eq_6_px2 ;
4406
4407 assign diag_or_tecc_acc_px2 = (inst_l2tag_vld_c2_1 ) |
4408 scrub_fsm_count_eq_6_px2 |
4409 scrub_fsm_count_eq_1_px2 |
4410 data_ecc_active_c4 ;
4411
4412 assign arb_sel_diag_tag_addr_px2 = diag_or_tecc_acc_px2 ;
4413
4414//////////////////////////////////////////////////////////////////////////////
4415// Fix for atpg : ECO ID 106991
4416//////////////////////////////////////////////////////////////////////////////
4417// assign arb_sel_lkup_stalled_tag_px2 = ( arb_stall_c2 |
4418// (inst_l2tag_vld_c2_1 | scrub_fsm_count_eq_6_px2 | scrub_fsm_count_eq_1_px2 | data_ecc_active_c4)) ;
4419//
4420
4421
4422assign arb_sel_lkup_stalled_tag_px2 = (( arb_stall_c2 |
4423 (inst_l2tag_vld_c2_1 | scrub_fsm_count_eq_6_px2 | scrub_fsm_count_eq_1_px2 | data_ecc_active_c4)) | tcu_scan_en ) ;
4424
4425
4426l2t_arb_ctl_msff_ctl_macro__width_1 ff_diag_or_tecc_acc_c1
4427 (.din(diag_or_tecc_acc_px2), .l1clk(l1clk),
4428 .scan_in(ff_diag_or_tecc_acc_c1_scanin),
4429 .scan_out(ff_diag_or_tecc_acc_c1_scanout),
4430 .dout(diag_or_tecc_acc_c1),
4431 .siclk(siclk),
4432 .soclk(soclk)
4433);
4434
4435// int 5.0 changes
4436// assign sel_fill_wr_px2 = fbsel_px2 & ~diag_or_tecc_acc_px2 ;
4437 assign sel_fill_wr_px2 = fbsel_px2 & ~diag_or_tecc_acc_px2 & ~l2_bypass_mode_on_d1;
4438
4439 // BS 04/28/04 sync up with N1 TO 1.0
4440 assign arbdec_arbdp_inst_fb_c1_qual = arbdec_arbdp_inst_fb_c1 & arb_inst_vld_c1_1;
4441
4442 // A fill will write into the tag in C1 instead of in PX2 if
4443 // the fill is stalled in C1 due to a deccck, tecc or tag diagnostic access.
4444 // This means that one cycle after the tecc, deccck or diagnostic operation
4445 // finishes accessing the tag, the fill in C1 will access the tag.
4446
4447// int 5.0 changes
4448// assign sel_delayed_fill_wr_c1 = arbdec_arbdp_inst_fb_c1 & diag_or_tecc_acc_c1 &
4449// ~diag_or_tecc_acc_px2 ;
4450
4451 assign sel_delayed_fill_wr_c1 = arbdec_arbdp_inst_fb_c1_qual & diag_or_tecc_acc_c1 &
4452 ~diag_or_tecc_acc_px2 & ~l2_bypass_mode_on_d1 ;
4453
4454
4455 assign arb_tag_wr_px2 = sel_fill_wr_px2 |
4456 arb_diag_or_tecc_write_px2 | // diagnostic or tecc write.
4457 sel_delayed_fill_wr_c1 ;
4458 // cyc after.
4459
4460// int 5.0 changes
4461 // added POST_4.0 for bug #3897. If mbist is ON when a diagnostic
4462 // write is issued to turn it off, the Mbist write should take precedence over
4463 // the diagnostic access.
4464
4465 assign arb_tag_rd_px2 = ~arb_tag_wr_px2
4466 & arb_tag_acc_px2
4467 & ~mbist_arb_l2t_write ;
4468
4469
4470
4471 assign arb_sel_way_px2 = ~sel_delayed_fill_wr_c1 & ~diag_or_tecc_acc_px2 ;
4472
4473
4474 //////////////////////////////////////////////////////////
4475 // way for tag writes is determined here.
4476 //////////////////////////////////////////////////////////
4477
4478l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux1_tag_way_px
4479 (.dout ( tag_diag_or_tecc_way_c2[3:0] ) , // diag or tag write way
4480 .din0(tecc_st_cnt[6:3]), // tecc way counter
4481 .din1(arbadr_arbdp_diag_wr_way_c2[3:0] ), // diagnostic way
4482 .sel0(inc_tag_ecc_cnt_c3), // tecc under process
4483 .sel1(~inc_tag_ecc_cnt_c3)); // default
4484
4485l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux2_tag_way_px
4486 (.dout (stalled_tag[3:0]) , // stalled or diag or tag write way
4487 .din0(tag_diag_or_tecc_way_c2[3:0]), // diag or tag tecc way counter
4488 .din1(arbdec_arbdp_inst_way_c1[3:0] ), // stalled instr way
4489 .sel0(diag_or_scr_way_sel), // diag or tecc under process
4490 .sel1(~diag_or_scr_way_sel)); // default
4491
4492l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux3_tag_way_px
4493 (.dout (enc_tag_way_px2[3:0]) , // stalled or diag or tag write way
4494 .din0(stalled_tag[3:0]), // diag or tag tecc way counter or stalled way
4495 .din1(filbuf_arbdp_way_px2[3:0] ), // fbtag
4496 .sel0(~arb_sel_way_px2),
4497 .sel1(arb_sel_way_px2));
4498
4499////////////////////////////////////////////////////////////////////////////////
4500// Decode the tag way here
4501////////////////////////////////////////////////////////////////////////////////
4502
4503assign dec_lo_way_sel_c1[0] = ( enc_tag_way_px2[1:0]==2'd0 ) ;
4504assign dec_lo_way_sel_c1[1] = ( enc_tag_way_px2[1:0]==2'd1 ) ;
4505assign dec_lo_way_sel_c1[2] = ( enc_tag_way_px2[1:0]==2'd2 ) ;
4506assign dec_lo_way_sel_c1[3] = ( enc_tag_way_px2[1:0]==2'd3 ) ;
4507
4508assign dec_hi_way_sel_c1[0] = ( enc_tag_way_px2[3:2]==2'd0 ) ;
4509assign dec_hi_way_sel_c1[1] = ( enc_tag_way_px2[3:2]==2'd1 ) ;
4510assign dec_hi_way_sel_c1[2] = ( enc_tag_way_px2[3:2]==2'd2 ) ;
4511assign dec_hi_way_sel_c1[3] = ( enc_tag_way_px2[3:2]==2'd3 ) ;
4512
4513
4514assign arb_tag_way_px2[0] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[0] ; // 0000
4515assign arb_tag_way_px2[1] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[1] ; // 0001
4516assign arb_tag_way_px2[2] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[2] ; // 0010
4517assign arb_tag_way_px2[3] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[3] ; // 0011
4518
4519assign arb_tag_way_px2[4] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[0] ;
4520assign arb_tag_way_px2[5] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[1] ;
4521assign arb_tag_way_px2[6] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[2] ;
4522assign arb_tag_way_px2[7] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[3] ;
4523
4524assign arb_tag_way_px2[8] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[0] ; // 1000
4525assign arb_tag_way_px2[9] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[1] ; // 1001
4526assign arb_tag_way_px2[10] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[2] ; // 1010
4527assign arb_tag_way_px2[11] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[3] ; // 1011
4528
4529
4530assign arb_tag_way_px2[12] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[0] ; // 1100, BS & SR 10/28/03
4531assign arb_tag_way_px2[13] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[1] ; // 1101, BS & SR 10/28/03
4532assign arb_tag_way_px2[14] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[2] ; // 1110, BS & SR 10/28/03
4533assign arb_tag_way_px2[15] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[3] ; // 1111, BS & SR 10/28/03
4534
4535
4536////////////////////////////////////////////////////////////////////////////////
4537// dword mask generation logic for pst data merging.
4538////////////////////////////////////////////////////////////////////////////////
4539l2t_arb_ctl_msff_ctl_macro__width_1 ff_hit_l2orfb_c4
4540 (.din(tag_hit_l2orfb_c3), .l1clk(l1clk),
4541 .scan_in(ff_hit_l2orfb_c4_scanin),
4542 .scan_out(ff_hit_l2orfb_c4_scanout),
4543 .dout(hit_l2orfb_c4),
4544 .siclk(siclk),
4545 .soclk(soclk)
4546
4547);
4548l2t_arb_ctl_msff_ctl_macro__width_1 ff_hit_l2orfb_c5
4549 (.din(hit_l2orfb_c4), .l1clk(l1clk),
4550 .scan_in(ff_hit_l2orfb_c5_scanin),
4551 .scan_out(ff_hit_l2orfb_c5_scanout),
4552 .dout(hit_l2orfb_c5),
4553 .siclk(siclk),
4554 .soclk(soclk)
4555
4556);
4557
4558// BS 03/11/04 extra cycle for mem access
4559
4560l2t_arb_ctl_msff_ctl_macro__width_1 ff_hit_l2orfb_c52
4561 (.din(hit_l2orfb_c5), .l1clk(l1clk),
4562 .scan_in(ff_hit_l2orfb_c52_scanin),
4563 .scan_out(ff_hit_l2orfb_c52_scanout),
4564 .dout(hit_l2orfb_c52),
4565 .siclk(siclk),
4566 .soclk(soclk)
4567
4568);
4569
4570l2t_arb_ctl_msff_ctl_macro__width_1 ff_hit_l2orfb_c6
4571 (.din(hit_l2orfb_c52), .l1clk(l1clk),
4572 .scan_in(ff_hit_l2orfb_c6_scanin),
4573 .scan_out(ff_hit_l2orfb_c6_scanout),
4574 .dout(hit_l2orfb_c6),
4575 .siclk(siclk),
4576 .soclk(soclk)
4577
4578);
4579l2t_arb_ctl_msff_ctl_macro__width_1 ff_hit_l2orfb_c7
4580 (.din(hit_l2orfb_c6), .l1clk(l1clk),
4581 .scan_in(ff_hit_l2orfb_c7_scanin),
4582 .scan_out(ff_hit_l2orfb_c7_scanout),
4583 .dout(hit_l2orfb_c7),
4584 .siclk(siclk),
4585 .soclk(soclk)
4586
4587);
4588l2t_arb_ctl_msff_ctl_macro__width_1 ff_hit_l2orfb_c8
4589 (.din(hit_l2orfb_c7), .l1clk(l1clk),
4590 .scan_in(ff_hit_l2orfb_c8_scanin),
4591 .scan_out(ff_hit_l2orfb_c8_scanout),
4592 .dout(hit_l2orfb_c8),
4593 .siclk(siclk),
4594 .soclk(soclk)
4595
4596);
4597
4598
4599// BS and SR 11/12/03 N2 Xbar Packet format change :
4600
4601// bug id 95620
4602// Upon encountering vuad array for a partial store,
4603// Care should be taken to diable the mask bits since the first pass is to detect and correct
4604// VUAD error
4605
4606assign dword_mask_c7 = (arbdec_arbdp_inst_size_c7[7:0]) | {8{~decdp_pst_inst_c7|~hit_l2orfb_c7 | vuad_ce_err_c7}};
4607
4608
4609l2t_arb_ctl_msff_ctl_macro__width_8 ff_dword_mask_c8
4610 (.din(dword_mask_c7[7:0]), .l1clk(l1clk),
4611 .scan_in(ff_dword_mask_c8_scanin),
4612 .scan_out(ff_dword_mask_c8_scanout),
4613 .dout(arb_dword_mask_c8[7:0]),
4614 .siclk(siclk),
4615 .soclk(soclk)
4616
4617);
4618
4619
4620 // ////////////////////////////////////////////////////////////////////////////////////
4621 // PST CTRUE WR EN
4622 // Write ctrue for a PST if its pass hits the cache or FB so that the next
4623 // pass will perform a store to the $
4624 // ////////////////////////////////////////////////////////////////////////////////////
4625
4626
4627 assign arb_pst_ctrue_en_c8 = arbdp_pst_no_ctrue_c8 & hit_l2orfb_c8 ;
4628
4629
4630
4631 // ////////////////////////////////////////////////////////////////////////////////////
4632 // Select for the mux in data array between store data and fill data.
4633 // ///////////////////////////////////////////////////////////////////////////////////
4634
4635 assign arb_fill_vld_c2 = mbist_run_r1 ? 1'b0 : ( arbdec_arbdp_inst_fb_c2 & arb_inst_vld_c2_7) ;
4636
4637l2t_arb_ctl_msff_ctl_macro__width_1 ff_fbrd_c3
4638 (.din(arb_fill_vld_c2), .l1clk(l1clk),
4639 .scan_in(ff_fbrd_c3_scanin),
4640 .scan_out(ff_fbrd_c3_scanout),
4641 .dout(arb_fill_vld_c3),
4642 .siclk(siclk),
4643 .soclk(soclk)
4644);
4645
4646 assign arb_l2d_fbrd_c3 = arb_fill_vld_c3 ;
4647
4648
4649
4650
4651 //////////////////////////////////////////////////////////////////////
4652 // DIrectory access Signals are generated here
4653 /////////////////////////////////////////////////////////////////////
4654
4655 ////////////////////////////////////////////////////////////////////////
4656 // 1. Bank enable for the D$ directories.
4657 // C2 C3
4658 //================================
4659 // store imiss2 hit
4660 // hit
4661 //
4662 // atm hit eviction
4663 // of valid line
4664 //
4665 // imiss1 hit xmit to dir
4666 //
4667 // bst hit
4668 // snp hit
4669 ////////////////////////////////////////////////////////////////////////
4670
4671
4672 assign st_cam_en_c2 = ( decdp_st_inst_c2_1 | decdp_strst_inst_c2_1 ) &
4673 ~( arb_decdp_fwd_req_c2 | arb_inst_diag_c2 ) &
4674 ( ~arbdec_arbdp_inst_mb_c2 | arbdec_arbdp_inst_dep_c2 ) ;
4675
4676l2t_arb_ctl_msff_ctl_macro__width_1 ff_st_cam_en_c3
4677 (.din(st_cam_en_c2), .l1clk(l1clk),
4678 .scan_in(ff_st_cam_en_c3_scanin),
4679 .scan_out(ff_st_cam_en_c3_scanout),
4680 .dout(st_cam_en_c3),
4681 .siclk(siclk),
4682 .soclk(soclk)
4683);
4684
4685
4686// special instructions cam en.
4687// 2/20/2003 Changed arb_decdp_cas2_from_mb_c2 to
4688// arb_decdp_cas2_from_mb_ctrue_c2 in the following expressions.
4689// A CAS instruction will not cam the D$ directory unless
4690// the compare results are true.
4691// Remember: THe I$ directory WILL BE CAMMED irrespective
4692// of the compare results.
4693
4694 assign sp_cam_en_c2 = ( ~arbdp_pst_no_ctrue_c2_1 & arb_decdp_swap_inst_c2 ) |
4695 ( ~arbdp_pst_no_ctrue_c2_1 & arb_decdp_wr8_inst_c2 ) |
4696 arb_decdp_cas2_from_mb_ctrue_c2 ;
4697
4698
4699l2t_arb_ctl_msff_ctl_macro__width_1 ff_sp_cam_en_c3
4700 (.din(sp_cam_en_c2), .l1clk(l1clk),
4701 .scan_in(ff_sp_cam_en_c3_scanin),
4702 .scan_out(ff_sp_cam_en_c3_scanout),
4703 .dout(sp_cam_en_c3),
4704 .siclk(siclk),
4705 .soclk(soclk)
4706);
4707
4708 assign dc_cam_addr_c3[0] = ( arbadr_arbdp_addr5to4_c3 == 2'd0 ) ;
4709 assign dc_cam_addr_c3[1] = ( arbadr_arbdp_addr5to4_c3 == 2'd1 ) ;
4710 assign dc_cam_addr_c3[2] = ( arbadr_arbdp_addr5to4_c3 == 2'd2 ) ;
4711 assign dc_cam_addr_c3[3] = ( arbadr_arbdp_addr5to4_c3 == 2'd3 ) ;
4712
4713
4714
4715// int 5.0 changes
4716 //---------\/ POST_4.2 change required for timing \/------
4717 // misbuf_nondep_fbhit_c3 is an unqualified signal from mbctl
4718 //---------\/ POST_4.2 change required for timing \/------
4719
4720
4721 assign store_inst_en_c3 = ( tag_hit_l2orfb_c3 |
4722 ( misbuf_nondep_fbhit_c3 & ~tagdp_arb_par_err_c3 & arb_inst_vld_c3_2 & ~arb_vuad_ce_err_c3));
4723
4724// assign store_inst_en_c3 = ( tag_hit_l2orfb_c3 | misbuf_nondep_fbhit_c3 ) ;
4725
4726 // cam entries with addr<5>==0 for the 1st imiss packet.
4727
4728l2t_arb_ctl_msff_ctl_macro__width_7 ff_arb_decdp_cas1_inst_c3
4729 (
4730 .scan_in(ff_arb_decdp_cas1_inst_c3_scanin),
4731 .scan_out(ff_arb_decdp_cas1_inst_c3_scanout),
4732 .din({arb_decdp_cas1_inst_c2,arb_decdp_swap_inst_c2,arbdec_arbdp_rdma_inst_c2,arb_decdp_ld_inst_c2
4733 ,arb_decdp_wr8_inst_c2,arb_decdp_ld64_inst_c2,arb_decdp_cas2_inst_c2}),
4734 .l1clk(l1clk),
4735 .dout({arb_decdp_cas1_inst_c3,arb_decdp_swap_inst_c3,arbdec_arbdp_rdma_inst_c3,arb_decdp_ld_inst_c3
4736 ,arb_decdp_wr8_inst_c3,arb_decdp_ld64_inst_c3,arb_decdp_cas2_inst_c3}),
4737 .siclk(siclk),
4738 .soclk(soclk)
4739 );
4740
4741// Bug fix 87037
4742assign enable_dc_cam = ((~arb_decdp_cas1_inst_c3 & ~arb_decdp_swap_inst_c3 & ~arb_decdp_ld_inst_c3)
4743 | arbdec_arbdp_rdma_inst_c3 ) & misbuf_vuad_ce_instr_c3 &
4744 ~arb_decdp_ld64_inst_c3 & ~arb_decdp_wr8_inst_c3 & ~arb_decdp_cas2_inst_c3;
4745
4746
4747
4748// for swap and wr8, sp_cam_en_c2 will enable D$ directory CAMing only
4749
4750assign disable_dc_cam = (arb_decdp_swap_inst_c3 & arb_vuad_ce_err_c3) |
4751 (imiss_inst_c3 & tag_hit_l2orfb_c3 & arb_vuad_ce_err_c3) |
4752 (store_inst_en_c3 & arb_vuad_ce_err_c3) ;
4753
4754
4755
4756// Bug id 87014
4757 assign dc_hitqual_cam_en0_c3 = (( st_cam_en_c3 & (store_inst_en_c3 |
4758 (tag_hit_unqual_c3 & misbuf_hit_st_dep_zero)))
4759 | ( tag_hit_l2orfb_c3 & (sp_cam_en_c3 | enable_dc_cam))
4760 | ( ~tag_hit_l2orfb_c3 & misbuf_vuad_ce_instr_c3 & store_inst_en_c3)
4761 | imiss_hit_c3 ) & ~disable_dc_cam;
4762
4763// Bug id 87014
4764assign dc_hitqual_cam_en1_c3 = (( st_cam_en_c3 & (store_inst_en_c3 |
4765 (tag_hit_unqual_c3 & misbuf_hit_st_dep_zero)))
4766 | ( (enable_dc_cam | sp_cam_en_c3) & tag_hit_l2orfb_c3 )
4767 | ( ~tag_hit_l2orfb_c3 & misbuf_vuad_ce_instr_c3 & store_inst_en_c3))
4768 & ~disable_dc_cam ;
4769
4770l2t_arb_ctl_msff_ctl_macro__width_1 ff_enc_cam_addr_c4 // int 5.0 changes
4771 (.din(arbadr_arbdp_addr5to4_c3[1]), .l1clk(l1clk),
4772 .scan_in(ff_enc_cam_addr_c4_scanin),
4773 .scan_out(ff_enc_cam_addr_c4_scanout),
4774 .dout(enc_cam_addr_c4),
4775 .siclk(siclk),
4776 .soclk(soclk)
4777);
4778
4779
4780l2t_arb_ctl_msff_ctl_macro__width_1 ff_vuad_ce
4781 (.dout ({misbuf_vuad_ce_instr_c3}),
4782 .scan_in(ff_vuad_ce_scanin),
4783 .scan_out(ff_vuad_ce_scanout),
4784 .din ({misbuf_vuad_ce_instr_c2}),
4785 .l1clk (l1clk),
4786 .siclk(siclk),
4787 .soclk(soclk)
4788 ) ;
4789
4790
4791// VUAD ECC pipeline :
4792// On detecting a CE on VUAD in L2 the following happen
4793// 0. We detect VUAD CE on any valid instruction from Core or SIU other than Tecc, I$ Invalidate,
4794// D$ Invalidates,Prefetch ICE and Diagnostics . (However the data gets silently corrected for
4795// Tecc, I$ Invalidate,D$ Invalidates,Prefetch ICE and Diagnostics in C2 stage of pipe before it
4796// gets written to VUAD array in C5). For Prefetch ICE, even if the error happens in the
4797// Eviction pass of the Prefetch ICE, since it gets corrected in C2 phase itself , any
4798// error in Valid,Dirty bits will not be visible, and the Prefetch ICE will do the
4799// right thing w.r.t Dirty/Clean
4800// 1. On detecting CE, Instruction gets moved into the MB (logic in l2t_misbuf_ctl)
4801// 2. Correction happens in C2 stage in l2t_usaloc_dp and l2t_vlddir_dp
4802// 3. CAMS to I$ and D$ directories are gated off (logic in l2t_arb_ctl)
4803// 4. Updates of I$ and D$ directories are gated off (logic in l2t_arb_ctl)
4804// 5. requests to crossbar gated off in C7 (first pass) (logic in l2t_oqu_ctl)
4805// 6. Updates of VUAD array happens in C5 (first pass) (logic in l2t_vuaddp_ctl)
4806// This is corrected data.
4807// 7. DRAM ready is not set (logic in l2t_misbuf_ctl)
4808// 8. Instruction would be readied for replay from MB in C9 ((logic in l2t_misbuf_ctl)
4809
4810//assign vuad_ce_err_c3 = (usaloc_ua_ce_c3 | vlddir_vd_ce_c3) & arb_inst_vld_c3 &
4811// ~(arb_tecc_c3 | inst_diag_c3 | decdp_pf_ice_inst_c3 | decdp_inst_int_or_inval_c3) ;
4812//
4813//
4814//assign arb_vuad_ce_err_c3 = vuad_ce_err_c3;
4815
4816// changed from c3 to c2
4817
4818/*
4819// VUAD CE is not detected for the following :
48201.TECC instruction
48212.Fill
48223.Diagnostic instruction
48234.Prefetch ICE
48245.Invalidation Instructions
48256.Replayed instructions from Miss Buffer that hit in the Fill Buffer
4826*/
4827
4828//
4829//the following equation will have filbuf_tag_hit_frm_mb_c2 qualified in misbuf
4830//since this signal goes to misbuf.
4831//
4832//assign vuad_ce_err_c2_unqual = arb_inst_vld_c2 & ~(arb_tecc_c2 |
4833// filbuf_tag_hit_frm_mb_c2 | arb_fill_vld_c2 | arb_inst_diag_c2
4834// | arb_pf_ice_inst_c2 | decdp_inst_int_or_inval_c2) ;
4835//
4836
4837
4838assign vuad_ce_err_c2_unqual = arb_inst_vld_c2 & ~(arb_tecc_c2 |
4839 filbuf_tag_hit_frm_mb_c2 | arb_fill_vld_c2 | arb_inst_diag_c2 | l2_bypass_mode_on_d1 |
4840 arb_pf_ice_inst_c2 | decdp_inst_int_or_inval_c2) ;
4841
4842// assign arb_vuad_ce_err_c2 = vuad_ce_err_c2_unqual;
4843
4844assign arb_vuad_ce_err_c2 = arb_inst_vld_c2_4 & ~(arb_tecc_c2 | l2_bypass_mode_on_d1 |
4845 arb_fill_vld_c2 | arb_inst_diag_c2 | arb_pf_ice_inst_c2 | decdp_inst_int_or_inval_c2) ;
4846
4847
4848assign arb_vuad_ce_err_c3 = vuad_ce_err_c3;
4849
4850assign vuad_ce_err_c2 = (usaloc_ua_ce_c2 | vlddir_vd_ce_c2) & vuad_ce_err_c2_unqual;
4851
4852
4853l2t_arb_ctl_msff_ctl_macro__width_8 ff_vuad_ce_err_c3 // int 5.0 changes
4854 (
4855 .scan_in(ff_vuad_ce_err_c3_scanin),
4856 .scan_out(ff_vuad_ce_err_c3_scanout),
4857 .din({vuad_ce_err_c2,vuad_ce_err_c2,vuad_ce_err_c2,vuad_ce_err_c3,vuad_ce_err_c4,vuad_ce_err_c5,
4858 vuad_ce_err_c52,vuad_ce_err_c6}),
4859 .l1clk(l1clk),
4860 .dout({vuad_ce_err_c3,usaloc_vlddir_arb_vuad_ce_err_c3,tagctl_arb_vuad_ce_err_c3,
4861 vuad_ce_err_c4,vuad_ce_err_c5, vuad_ce_err_c52,vuad_ce_err_c6,vuad_ce_err_c7}),
4862 .siclk(siclk),
4863 .soclk(soclk)
4864 );
4865
4866
4867 // snoops and block stores need to be included in this expression.
4868// In case of VUAD CE turn off CAM enable for D$ directory
4869//
4870//
4871// assign arb_lkup_bank_ena_dcd_c3[0] = ( dc_cam_addr_c3[0] & // cam for store,atomic, imiss packet1
4872// dc_hitqual_cam_en0_c3 ) |
4873// ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) | // eviction CAM
4874// ( wr64_inst_c3 & tag_hit_l2orfb_c3 );
4875//
4876// assign arb_lkup_bank_ena_dcd_c3[1] = ( dc_cam_addr_c3[1] & // cam for store,atomic, imiss packet2
4877// dc_hitqual_cam_en1_c3) |
4878// ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) |
4879//// int 5.0 changes
4880//// ( ~enc_cam_addr_c4[1] & arb_imiss_hit_c4 )|// addr<5>=0 cam for 2nd imiss packet
4881// ( ~enc_cam_addr_c4 & arb_imiss_hit_c4 )|// addr<5>=0 cam for 2nd imiss packet
4882// ( wr64_inst_c3 & tag_hit_l2orfb_c3 );
4883//
4884//
4885//
4886//
4887//
4888// assign arb_lkup_bank_ena_dcd_c3[2] = ( dc_cam_addr_c3[2] & // cam for store,atomic, imiss packet1
4889// dc_hitqual_cam_en0_c3) |
4890// ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) |
4891// (wr64_inst_c3 & tag_hit_l2orfb_c3 );
4892//
4893// assign arb_lkup_bank_ena_dcd_c3[3] = ( dc_cam_addr_c3[3] & // cam for store,atomic, imiss packet2
4894// dc_hitqual_cam_en1_c3 ) |
4895// ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) |
4896//// int 5.0 changes
4897//// ( enc_cam_addr_c4[1] & arb_imiss_hit_c4 )| // addr<5>=1 cam for 2nd imiss packet
4898// ( enc_cam_addr_c4 & arb_imiss_hit_c4 )| // addr<5>=1 cam for 2nd imiss packet
4899//
4900// ( wr64_inst_c3 & tag_hit_l2orfb_c3 );
4901//
4902
4903// VUAD ecc changes
4904 assign arb_lkup_bank_ena_dcd_c3[0] = (( dc_cam_addr_c3[0] & // cam for store,atomic, imiss packet1
4905 dc_hitqual_cam_en0_c3 ) |
4906 ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) | // eviction CAM
4907 ( wr64_inst_c3 & tag_hit_l2orfb_c3 )) & ~vuad_ce_err_c3; // VUAD ecc change
4908
4909 assign arb_lkup_bank_ena_dcd_c3[1] = ((( dc_cam_addr_c3[1] & // cam for store,atomic, imiss packet2
4910 dc_hitqual_cam_en1_c3) |
4911 ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) |
4912 ( wr64_inst_c3 & tag_hit_l2orfb_c3 )) & ~vuad_ce_err_c3)
4913 |
4914 (( ~enc_cam_addr_c4 & arb_imiss_hit_c4 ) // addr<5>=0 cam for 2nd imiss packet
4915 & ~vuad_ce_err_c4); // VUAD ecc change
4916
4917 assign arb_lkup_bank_ena_dcd_c3[2] = (( dc_cam_addr_c3[2] & // cam for store,atomic, imiss packet1
4918 dc_hitqual_cam_en0_c3) |
4919 ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) |
4920 (wr64_inst_c3 & tag_hit_l2orfb_c3 )) & ~vuad_ce_err_c3; // VUAD ecc change
4921
4922 assign arb_lkup_bank_ena_dcd_c3[3] = ((( dc_cam_addr_c3[3] & // cam for store,atomic, imiss packet2
4923 dc_hitqual_cam_en1_c3 ) |
4924 ( arb_evict_c3 & ~tagdp_invalid_evict_c3 ) |
4925 ( wr64_inst_c3 & tag_hit_l2orfb_c3 )) & ~vuad_ce_err_c3)
4926 |
4927 (( enc_cam_addr_c4 & arb_imiss_hit_c4 ) // addr<5>=1 cam for 2nd imiss packet
4928 & ~vuad_ce_err_c4); // VUAD ecc change
4929
4930
4931
4932 ////////////////////////////////////////////////////////////////////////
4933 // 2. Bank enable for the I$ directories.
4934 // C2 C3
4935 //==================================
4936 // store
4937 // hit
4938 //
4939 // atm hit eviction
4940 // of valid line
4941 //
4942 // ld hit xmit to
4943 // dir
4944 // bst hit
4945 // snp hit
4946 ////////////////////////////////////////////////////////////////////////
4947
4948
4949 // int 5.0 change
4950 //-------\/ Added this logic POST_4.2 \/----------
4951 // For a BLD, NC=1. The D$ is not filled with BLD data returned by
4952 // the L2. In this case, it will be incorrect to invalidate the i$
4953 // because the i$ logic cannot handle more than one invalidate per
4954 // outstanding load whereas a BLD will invalidate 2 lines in the I$( potentially)
4955
4956l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbctl_inst_nc_c2
4957 (.din(arbdec_arbdp_inst_nc_c1), .l1clk(l1clk),
4958 .scan_in(ff_arbctl_inst_nc_c2_scanin),
4959 .scan_out(ff_arbctl_inst_nc_c2_scanout),
4960 .dout(arb_inst_nc_c2),
4961 .siclk(siclk),
4962 .soclk(soclk)
4963);
4964
4965
4966 assign ic_hitqual_cam_en_c2 = (( ~arbdp_pst_no_ctrue_c2_1 & arb_decdp_swap_inst_c2 ) |
4967 ( ~arbdp_pst_no_ctrue_c2_1 & arb_decdp_wr8_inst_c2 ) |
4968 arb_decdp_cas2_from_mb_c2 |
4969 (decdp_camld_inst_c2 & ~arb_inst_nc_c2 )) ; // int 5.0 change
4970
4971l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_hitqual_cam_en_c3
4972 (.din(ic_hitqual_cam_en_c2), .l1clk(l1clk),
4973 .scan_in(ff_ic_hitqual_cam_en_c3_scanin),
4974 .scan_out(ff_ic_hitqual_cam_en_c3_scanout),
4975 .dout(ic_hitqual_cam_en_c3),
4976 .siclk(siclk),
4977 .soclk(soclk)
4978);
4979
4980 // instructions that cam only one directory panel are included here.
4981
4982 assign tmp_bank_icd_c3 = ( st_cam_en_c3 & (store_inst_en_c3 |
4983 (tag_hit_unqual_c3 & misbuf_hit_st_dep_zero))) |
4984 ( ic_hitqual_cam_en_c3 & tag_hit_l2orfb_c3 ) ;
4985
4986
4987// BS and SR 11/18/03 Support for 8 way I$
4988// Support for 8 way I$. Two rows need to be cammed out of 4 for every
4989// Load hit or Store hit. All four rows need to be cammed for an Eviction
4990// Each row holds I$ ways 0 through 3 or I$ ways 4 through 7.
4991// Row select = {addr[5],I$ L1 way[2]}
4992//
4993// assign arb_lkup_bank_ena_icd_c3[0] = ( tmp_bank_icd_c3 & ~arbadr_arbdp_addr5to4_c3[1] ) |
4994// ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
4995// (wr64_inst_c3 & tag_hit_l2orfb_c3 ) ) ;
4996//
4997// assign arb_lkup_bank_ena_icd_c3[1] = ( tmp_bank_icd_c3 & ~arbadr_arbdp_addr5to4_c3[1] ) |
4998// ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
4999// (wr64_inst_c3 & tag_hit_l2orfb_c3 ) ) ;
5000//
5001//
5002// assign arb_lkup_bank_ena_icd_c3[2] = ( tmp_bank_icd_c3 & arbadr_arbdp_addr5to4_c3[1] ) |
5003// ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
5004// (wr64_inst_c3 & tag_hit_l2orfb_c3 ) ) ;
5005//
5006//
5007// assign arb_lkup_bank_ena_icd_c3[3] = ( tmp_bank_icd_c3 & arbadr_arbdp_addr5to4_c3[1] ) |
5008// ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
5009// (wr64_inst_c3 & tag_hit_l2orfb_c3 ) ) ;
5010//
5011
5012
5013// In case of VUAD CE turn off CAM enable for I$ directory
5014 assign arb_lkup_bank_ena_icd_c3[0] = (( tmp_bank_icd_c3 & ~arbadr_arbdp_addr5to4_c3[1] ) |
5015 ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
5016 (wr64_inst_c3 & tag_hit_l2orfb_c3 ))) & ~vuad_ce_err_c3;
5017
5018 assign arb_lkup_bank_ena_icd_c3[1] = (( tmp_bank_icd_c3 & ~arbadr_arbdp_addr5to4_c3[1] ) |
5019 ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
5020 (wr64_inst_c3 & tag_hit_l2orfb_c3 ))) & ~vuad_ce_err_c3;
5021
5022
5023 assign arb_lkup_bank_ena_icd_c3[2] = (( tmp_bank_icd_c3 & arbadr_arbdp_addr5to4_c3[1] ) |
5024 ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
5025 (wr64_inst_c3 & tag_hit_l2orfb_c3 ))) & ~vuad_ce_err_c3 ;
5026
5027
5028 assign arb_lkup_bank_ena_icd_c3[3] = (( tmp_bank_icd_c3 & arbadr_arbdp_addr5to4_c3[1] ) |
5029 ((arb_evict_c3 & ~tagdp_invalid_evict_c3) |
5030 (wr64_inst_c3 & tag_hit_l2orfb_c3 ))) & ~vuad_ce_err_c3 ;
5031
5032
5033
5034 ////////////////////////////////////////////////////////////////////////
5035 // 3 & 4. Row address for the D$ directories. ( This logic is in arbadr.)
5036 ////////////////////////////////////////////////////////////////////////
5037
5038
5039
5040 ////////////////////////////////////////////////////////////////////////
5041 // 5. INvalidate mask for the d$ directories.
5042 // // For a normal store in C3 invalidate all other cpus
5043 // // For an imiss ld in C3 or C4 invalidate the decoded cpu
5044 // // invalidate all cpus as the default case.
5045 ////////////////////////////////////////////////////////////////////////
5046
5047l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_3 mux_cpuid_c3
5048 (.dout (cpuid_c3[2:0]) , // c3 invalidation cpu
5049 .din0(arb_cpuid_c4[2:0]), // c4 instruction cpuid
5050 .din1(arb_cpuid_c3[2:0] ), // c3 instruction cpuid
5051 .sel0(arb_imiss_hit_c4), // sel c4 cpuid
5052 .sel1(~arb_imiss_hit_c4)); // sel default.
5053
5054 assign self_inval_mask_c3[0] = ( cpuid_c3 == 3'd0 ) ;
5055 assign self_inval_mask_c3[1] = ( cpuid_c3 == 3'd1 ) ;
5056 assign self_inval_mask_c3[2] = ( cpuid_c3 == 3'd2 ) ;
5057 assign self_inval_mask_c3[3] = ( cpuid_c3 == 3'd3 ) ;
5058 assign self_inval_mask_c3[4] = ( cpuid_c3 == 3'd4 ) ;
5059 assign self_inval_mask_c3[5] = ( cpuid_c3 == 3'd5 ) ;
5060 assign self_inval_mask_c3[6] = ( cpuid_c3 == 3'd6 ) ;
5061 assign self_inval_mask_c3[7] = ( cpuid_c3 == 3'd7 ) ;
5062
5063 assign others_inval_mask_c3 = ~self_inval_mask_c3 ;
5064
5065l2t_arb_ctl_msff_ctl_macro__width_1 ff_ld_inst_c3
5066 (.din(decdp_camld_inst_c2), .l1clk(l1clk),
5067 .scan_in(ff_ld_inst_c3_scanin),
5068 .scan_out(ff_ld_inst_c3_scanout),
5069 .dout(ld_inst_c3),
5070 .siclk(siclk),
5071 .soclk(soclk)
5072);
5073
5074
5075 // store hit includes that case where the store hits the Fill Buffer
5076 // and not the Miss Buffer.
5077 //assign st_inst_hit_c3 = arb_decdp_st_inst_c3 & store_inst_en_c3 ;
5078
5079 // Store inst vld c3 can be used in place of st_inst_hit_c3 in
5080 // * inval mask logic.
5081 // * dir rd entry logic
5082 // * dir error logic
5083 // * dir rd panel logic.
5084
5085
5086
5087 assign store_inst_vld_c3 = arb_decdp_st_inst_c3 & arb_inst_vld_c3 ;
5088 assign store_inst_vld_c3_1 = decdp_st_inst_c3_1 & arb_inst_vld_c3_1 ;
5089 assign store_inst_vld_c3_2 = decdp_st_inst_c3_2 & arb_inst_vld_c3_2 ;
5090
5091
5092 assign ld_hit_c3 = ld_inst_c3 & tag_hit_l2orfb_c3;
5093
5094 assign sel_stld_mask = ( ( store_inst_vld_c3_2 &
5095 ~decdp_rmo_st_or_strst_c3 & // Inval every cpu on an eviction or a rmo store
5096 ~arb_evict_unqual_c3 ) // or a stream store
5097 | imiss_hit_c3 |
5098 arb_imiss_hit_c4 | ld_hit_c3 );
5099
5100l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux1_inval_mask_c3
5101 (.dout (tmp_inval_mask_c3[7:0]) , // lds and stores mask
5102 .din0(others_inval_mask_c3[7:0]), // stores mask
5103 .din1(self_inval_mask_c3[7:0] ), // loads mask
5104 .sel0(store_inst_vld_c3_1), // sel stores mask
5105 .sel1(~store_inst_vld_c3_1)); // sel default.
5106
5107l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux2_inval_mask_c3
5108 (.dout (arb_inval_mask_dcd_c3[7:0]) , // inval_mask_dcd
5109 .din0(tmp_inval_mask_c3[7:0]), // stores/lds mask
5110 .din1(8'hFF), // default mask
5111 .sel0(sel_stld_mask), // sel stldimiss mask
5112 .sel1(~sel_stld_mask)); // sel default.
5113
5114
5115
5116 ////////////////////////////////////////////////////////////////////////
5117 // 6. INvalidate mask for the i$ directories.
5118 // // For an ld in C3 invalidate the decoded cpu
5119 // // invalidate all cpus in the default case.
5120 ////////////////////////////////////////////////////////////////////////
5121
5122l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux1_ic_inval_mask_c3
5123 (.dout(arb_inval_mask_icd_c3[7:0]) , // inval_mask_icd
5124 .din0(self_inval_mask_c3[7:0]), // lds mask
5125 .din1(8'hFF), // default mask
5126 .sel0(ld_hit_c3), // sel lds mask
5127 .sel1(~ld_hit_c3)); // sel default.
5128
5129
5130
5131 ////////////////////////////////////////////////////////////////////////
5132 // 7. Wr enable into the D$ & I$ directory
5133 ////////////////////////////////////////////////////////////////////////
5134
5135l2t_arb_ctl_msff_ctl_macro__width_1 ff_dc_inval_c3
5136 (.din(decdp_dc_inval_c2), .l1clk(l1clk),
5137 .scan_in(ff_dc_inval_c3_scanin),
5138 .scan_out(ff_dc_inval_c3_scanout),
5139 .dout(dc_inval_c3),
5140 .siclk(siclk),
5141 .soclk(soclk)
5142);
5143
5144l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_c3
5145 (.din(decdp_ic_inval_c2), .l1clk(l1clk),
5146 .scan_in(ff_ic_inval_c3_scanin),
5147 .scan_out(ff_ic_inval_c3_scanout),
5148 .dout(ic_inval_c3),
5149 .siclk(siclk),
5150 .soclk(soclk)
5151);
5152
5153 assign inval_inst_vld_c2 = ( decdp_dc_inval_c2 |
5154 decdp_ic_inval_c2 ) &
5155 arb_inst_vld_c2_7 ;
5156
5157 assign arb_inval_inst_c2 = inval_inst_vld_c2 ;
5158
5159
5160//----\/ FIX for bug#4619 \/--------------------------------------
5161 assign arb_misbuf_inval_inst_c2 = ( decdp_dc_inval_c2 |
5162 decdp_ic_inval_c2 ) ;
5163
5164
5165 assign dc_inval_vld_c3 = dc_inval_c3 & arb_inst_vld_c3 & ~misbuf_arb_hit_c3 ;
5166 assign ic_inval_vld_c3 = ic_inval_c3 & arb_inst_vld_c3 & ~misbuf_arb_hit_c3 ;
5167
5168// assign dc_inval_vld_c3 = dc_inval_c3 & arb_inst_vld_c3 ;
5169// assign ic_inval_vld_c3 = ic_inval_c3 & arb_inst_vld_c3 ;
5170
5171
5172l2t_arb_ctl_msff_ctl_macro__width_1 ff_dc_inval_vld_c4
5173 (.din(dc_inval_vld_c3), .l1clk(l1clk),
5174 .scan_in(ff_dc_inval_vld_c4_scanin),
5175 .scan_out(ff_dc_inval_vld_c4_scanout),
5176 .dout(dc_inval_vld_c4),
5177 .siclk(siclk),
5178 .soclk(soclk)
5179);
5180l2t_arb_ctl_msff_ctl_macro__width_1 ff_dc_inval_vld_c5
5181 (.din(dc_inval_vld_c4), .l1clk(l1clk),
5182 .scan_in(ff_dc_inval_vld_c5_scanin),
5183 .scan_out(ff_dc_inval_vld_c5_scanout),
5184 .dout(dc_inval_vld_c5),
5185 .siclk(siclk),
5186 .soclk(soclk)
5187);
5188
5189// BS 03/11/04 extra cycle for mem access
5190
5191l2t_arb_ctl_msff_ctl_macro__width_1 ff_dc_inval_vld_c52
5192 (.din(dc_inval_vld_c5), .l1clk(l1clk),
5193 .scan_in(ff_dc_inval_vld_c52_scanin),
5194 .scan_out(ff_dc_inval_vld_c52_scanout),
5195 .dout(dc_inval_vld_c52),
5196 .siclk(siclk),
5197 .soclk(soclk)
5198);
5199
5200l2t_arb_ctl_msff_ctl_macro__width_1 ff_dc_inval_vld_c6
5201 (.din(dc_inval_vld_c52), .l1clk(l1clk),
5202 .scan_in(ff_dc_inval_vld_c6_scanin),
5203 .scan_out(ff_dc_inval_vld_c6_scanout),
5204 .dout(dc_inval_vld_c6),
5205 .siclk(siclk),
5206 .soclk(soclk)
5207);
5208l2t_arb_ctl_msff_ctl_macro__width_1 ff_dc_inval_vld_c7
5209 (.din(dc_inval_vld_c6), .l1clk(l1clk),
5210 .scan_in(ff_dc_inval_vld_c7_scanin),
5211 .scan_out(ff_dc_inval_vld_c7_scanout),
5212 .dout(arb_dc_inval_vld_c7),
5213 .siclk(siclk),
5214 .soclk(soclk)
5215);
5216
5217
5218l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_vld_c4
5219 (.din(ic_inval_vld_c3), .l1clk(l1clk),
5220 .scan_in(ff_ic_inval_vld_c4_scanin),
5221 .scan_out(ff_ic_inval_vld_c4_scanout),
5222 .dout(ic_inval_vld_c4),
5223 .siclk(siclk),
5224 .soclk(soclk)
5225);
5226l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_vld_c5
5227 (.din(ic_inval_vld_c4), .l1clk(l1clk),
5228 .scan_in(ff_ic_inval_vld_c5_scanin),
5229 .scan_out(ff_ic_inval_vld_c5_scanout),
5230 .dout(ic_inval_vld_c5),
5231 .siclk(siclk),
5232 .soclk(soclk)
5233);
5234
5235// BS 03/11/04 extra cycle for mem access
5236
5237l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_vld_c52
5238 (.din(ic_inval_vld_c5), .l1clk(l1clk),
5239 .scan_in(ff_ic_inval_vld_c52_scanin),
5240 .scan_out(ff_ic_inval_vld_c52_scanout),
5241 .dout(ic_inval_vld_c52),
5242 .siclk(siclk),
5243 .soclk(soclk)
5244);
5245
5246l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_vld_c6
5247 (.din(ic_inval_vld_c52), .l1clk(l1clk),
5248 .scan_in(ff_ic_inval_vld_c6_scanin),
5249 .scan_out(ff_ic_inval_vld_c6_scanout),
5250 .dout(ic_inval_vld_c6),
5251 .siclk(siclk),
5252 .soclk(soclk)
5253);
5254l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_vld_c7
5255 (.din(ic_inval_vld_c6), .l1clk(l1clk),
5256 .scan_in(ff_ic_inval_vld_c7_scanin),
5257 .scan_out(ff_ic_inval_vld_c7_scanout),
5258 .dout(arb_ic_inval_vld_c7),
5259 .siclk(siclk),
5260 .soclk(soclk)
5261);
5262
5263// SR 12/6/04 :: Dir changes following 2 flops
5264
5265l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_vld_c8
5266 (.din(arb_ic_inval_vld_c7),
5267 .scan_in(ff_ic_inval_vld_c8_scanin),
5268 .scan_out(ff_ic_inval_vld_c8_scanout),
5269 .l1clk(l1clk),
5270 .dout(arb_ic_inval_vld_c8),
5271 .siclk(siclk),
5272 .soclk(soclk));
5273
5274l2t_arb_ctl_msff_ctl_macro__width_1 ff_ic_inval_vld_c9
5275 (.din(arb_ic_inval_vld_c8),
5276 .scan_in(ff_ic_inval_vld_c9_scanin),
5277 .scan_out(ff_ic_inval_vld_c9_scanout),
5278 .l1clk(l1clk),
5279 .dout(arb_ic_inval_vld_c9),
5280 .siclk(siclk),
5281 .soclk(soclk));
5282
5283
5284//msff_ctl_macro ff_ic_inval_vld_c10 (width=1)
5285// (.din(arb_ic_inval_vld_c9),
5286// .scan_in(ff_ic_inval_vld_c10_scanin),
5287// .scan_out(ff_ic_inval_vld_c10_scanout),
5288// .l1clk(l1clk),
5289// .dout(arb_ic_inval_vld_c10));
5290
5291
5292
5293
5294 assign inval_inst_vld_c3 = dc_inval_vld_c3 | ic_inval_vld_c3 ;
5295 assign inval_inst_vld_c4 = dc_inval_vld_c4 | ic_inval_vld_c4 ;
5296 assign inval_inst_vld_c5 = dc_inval_vld_c5 | ic_inval_vld_c5 ;
5297 assign inval_inst_vld_c52 = dc_inval_vld_c52 | ic_inval_vld_c52 ; // BS 03/11/04 extra cycle for mem access
5298
5299
5300
5301 // Date : 2/2/2002:
5302 // In L2 bypass mode, the directory write for Fb hits is
5303 // disabled
5304
5305//
5306// assign arb_dc_wr_en_c3 = ( ld_hit_c3 & ~arbdec_arbdp_inst_nc_c3
5307// & ~l2_bypass_mode_on_d1 ) |
5308// dc_inval_vld_c3 | // l1_way 00
5309// dc_inval_vld_c4 | // l1_way 01
5310// dc_inval_vld_c5 | // l1_way 10
5311//// dc_inval_vld_c6 ; // l1_way 11
5312// dc_inval_vld_c52 ; // l1_way 11 BS 03/11/04 extra cycle for mem access
5313//
5314//
5315// assign arb_ic_wr_en_c3 = ( imiss_hit_c3 & ~arbdec_arbdp_inst_nc_c3
5316// & ~l2_bypass_mode_on_d1 ) |
5317// ic_inval_vld_c3 | // l1_way 00
5318// ic_inval_vld_c4 | // l1_way 01
5319// ic_inval_vld_c5 | // l1_way 10
5320// // ic_inval_vld_c6 ; // l1_way 11
5321// ic_inval_vld_c52 ; // l1_way 11 BS 03/11/04 extra cycle for mem access
5322//
5323// // BS 2/1/04 : Brought out IC inval signal to separate from IC fill
5324// // because IC fill will load only one panel in 1 row (only one 1 cache waY) while IC inval will write
5325// // to two panels in two rows (2 icache ways) every cycle. This IC dir write enable logic is in
5326// // l2t_dir_ctl.sv.
5327//
5328// assign arb_ic_inval_wr_en_c3 = ic_inval_vld_c3 | // l1_way 00
5329// ic_inval_vld_c4 | // l1_way 01
5330// ic_inval_vld_c5 | // l1_way 10
5331// // ic_inval_vld_c6 ; // l1_way 11
5332// ic_inval_vld_c52 ; // l1_way 11 BS 03/11/04 extra cycle for mem access
5333//
5334//
5335// VUAD ecc changes
5336// vuad ce will disable the D$ dir writes only for instructions other than D$ invalidates.
5337// for D$ invalidates, vuad ce will be masked and hence the dir writes will go through
5338
5339 assign arb_dc_wr_en_c3 = (( ~vuad_ce_err_c3 & ld_hit_c3 & ~arbdec_arbdp_inst_nc_c3 // VUAD ecc change
5340 & ~l2_bypass_mode_on_d1 ) |
5341 dc_inval_vld_c3 | // l1_way 00
5342 dc_inval_vld_c4 | // l1_way 01
5343 dc_inval_vld_c5 | // l1_way 10
5344 dc_inval_vld_c52 ); // l1_way 11 BS 03/11/04 extra cycle for mem access
5345
5346
5347//// vuad ce will disable the I$ dir writes only for instructions other than I$ invalidates.
5348//// for I$ invalidates, vuad ce will be masked and hence the dir writes will go through
5349//
5350// assign arb_ic_wr_en_c3 = (( ~vuad_ce_err_c3 & imiss_hit_c3 & ~arbdec_arbdp_inst_nc_c3 // VUAD ecc change
5351// & ~l2_bypass_mode_on_d1 ) |
5352// ic_inval_vld_c3 | // l1_way 00
5353// ic_inval_vld_c4 | // l1_way 01
5354// ic_inval_vld_c5 | // l1_way 10
5355// ic_inval_vld_c52 ); // l1_way 11 BS 03/11/04 extra cycle for mem access
5356//
5357// // BS 2/1/04 : Brought out IC inval signal to separate from IC fill
5358// // because IC fill will load only one panel in 1 row (only one 1 cache waY) while IC inval will write
5359// // to two panels in two rows (2 icache ways) every cycle. This IC dir write enable logic is in
5360// // l2t_dir_ctl.sv.
5361//
5362//// In case of VUAD CE turn off write enable for I$ directory
5363// assign arb_ic_inval_wr_en_c3 = (ic_inval_vld_c3 | // l1_way 00
5364// ic_inval_vld_c4 | // l1_way 01
5365// ic_inval_vld_c5 | // l1_way 10
5366// ic_inval_vld_c52); // l1_way 11 BS 03/11/04 extra cycle for mem access
5367//
5368
5369// SR 12/6/04 :: Dir changes
5370
5371assign arb_ic_wr_en_c3 = (( ~vuad_ce_err_c3 & imiss_hit_c3 &
5372 ~arbdec_arbdp_inst_nc_c3 & ~l2_bypass_mode_on_d1 ) |
5373 ic_inval_vld_c3 | // l1_way 000
5374 ic_inval_vld_c4 | // l1_way 001
5375 ic_inval_vld_c5 | // l1_way 010
5376 ic_inval_vld_c52 | // l1_way 011
5377 ic_inval_vld_c6 | // l1_way 100
5378 arb_ic_inval_vld_c7 | // l1_way 101
5379 arb_ic_inval_vld_c8 | // l1_way 110
5380 arb_ic_inval_vld_c9 ); // l1_way 111
5381
5382//assign arb_ic_inval_wr_en_c3 =
5383// (ic_inval_vld_c3 | // l1_way 000
5384// ic_inval_vld_c4 | // l1_way 001
5385// ic_inval_vld_c5 | // l1_way 010
5386// ic_inval_vld_c52 | // l1_way 011
5387// ic_inval_vld_c6 | // l1_way 100
5388// arb_ic_inval_vld_c7 | // l1_way 101
5389// arb_ic_inval_vld_c8 | // l1_way 110
5390// arb_ic_inval_vld_c9 ); // l1_way 111
5391
5392 ////////////////////////////////////////////////////////////////////////
5393 // The Error injection register in csr needs this signal.
5394 ////////////////////////////////////////////////////////////////////////
5395 assign arb_dir_wr_en_c3 = ( arb_dc_wr_en_c3 |
5396 arb_ic_wr_en_c3 ) ;
5397
5398l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_dir_wr_en_c4
5399 (.din(arb_dir_wr_en_c3), .l1clk(l1clk),
5400 .scan_in(ff_arb_dir_wr_en_c4_scanin),
5401 .scan_out(ff_arb_dir_wr_en_c4_scanout),
5402 .dout(arb_dir_wr_en_c4),
5403 .siclk(siclk),
5404 .soclk(soclk)
5405);
5406
5407
5408 ////////////////////////////////////////////////////////////////////////
5409 // 8. Rd enable into the d$ and I$ directories
5410 // A read is performed when a store hit is in C3.
5411 // dir_addr_cnt<10:6> = panel #
5412 // dir_addr_cnt<5:1> = entry #
5413 // dir_addr_cnt<0> = I$ , 0= d$
5414 // Pipeline for reads.
5415 //--------------------------------------------------------------------------------
5416 // C3 C4 C5 C6 C7
5417 //--------------------------------------------------------------------------------
5418 // setup xmit Dir Parity Error
5419 // dir inside Rd Calc. Xmit
5420 // rd access the dir to arb
5421 // I$/d$
5422 ////////////////////////////////////////////////////////////////////////
5423
5424 assign dir_addr_cnt_plus1 = dir_addr_cnt_c3 + 11'b1 ;
5425
5426assign dir_store_inst_vld_c3 = store_inst_vld_c3 & ~arb_vuad_ce_err_c3; // do nothing on vuad ce error
5427
5428
5429l2t_arb_ctl_msff_ctl_macro__clr_1__en_1__width_11 ff_dir_addr_cnt // sync reset active high
5430 (.dout(dir_addr_cnt_c3[10:0]),
5431 .scan_in(ff_dir_addr_cnt_scanin),
5432 .scan_out(ff_dir_addr_cnt_scanout),
5433 .en(dir_store_inst_vld_c3), .l1clk(l1clk), .clr(arb_data_ecc_idx_reset),
5434 .din(dir_addr_cnt_plus1[10:0]),
5435 .siclk(siclk),
5436 .soclk(soclk)
5437);
5438
5439 assign arb_dc_rd_en_c3 = (~dir_addr_cnt_c3[0] & store_inst_vld_c3_1) & ~arb_vuad_ce_err_c3;
5440 assign arb_ic_rd_en_c3 = (dir_addr_cnt_c3[0] & store_inst_vld_c3_1 ) & ~arb_vuad_ce_err_c3;
5441 assign arb_dc_ic_rd_bit_4 = dir_addr_cnt_c3[6];
5442
5443
5444l2t_arb_ctl_msff_ctl_macro__width_11 ff_dir_addr_cnt_c4
5445 (.din(dir_addr_cnt_c3[10:0]), .l1clk(l1clk),
5446 .scan_in(ff_dir_addr_cnt_c4_scanin),
5447 .scan_out(ff_dir_addr_cnt_c4_scanout),
5448 .dout(dir_addr_cnt_c4[10:0]),
5449 .siclk(siclk),
5450 .soclk(soclk)
5451);
5452l2t_arb_ctl_msff_ctl_macro__width_11 ff_dir_addr_cnt_c5
5453 (.din(dir_addr_cnt_c4[10:0]), .l1clk(l1clk),
5454 .scan_in(ff_dir_addr_cnt_c5_scanin),
5455 .scan_out(ff_dir_addr_cnt_c5_scanout),
5456 .dout(dir_addr_cnt_c5[10:0]),
5457 .siclk(siclk),
5458 .soclk(soclk)
5459);
5460
5461// BS 03/11/04 extra cycle for mem access
5462
5463l2t_arb_ctl_msff_ctl_macro__width_11 ff_dir_addr_cnt_c52
5464 (.din(dir_addr_cnt_c5[10:0]), .l1clk(l1clk),
5465 .scan_in(ff_dir_addr_cnt_c52_scanin),
5466 .scan_out(ff_dir_addr_cnt_c52_scanout),
5467 .dout(dir_addr_cnt_c52[10:0]),
5468 .siclk(siclk),
5469 .soclk(soclk)
5470);
5471
5472
5473
5474l2t_arb_ctl_msff_ctl_macro__width_11 ff_dir_addr_cnt_c6
5475 (.din(dir_addr_cnt_c52[10:0]), .l1clk(l1clk),
5476 .scan_in(ff_dir_addr_cnt_c6_scanin),
5477 .scan_out(ff_dir_addr_cnt_c6_scanout),
5478 .dout(dir_addr_cnt_c6[10:0]),
5479 .siclk(siclk),
5480 .soclk(soclk)
5481);
5482l2t_arb_ctl_msff_ctl_macro__width_11 ff_dir_addr_cnt_c7
5483 (.din(dir_addr_cnt_c6[10:0]), .l1clk(l1clk),
5484 .scan_in(ff_dir_addr_cnt_c7_scanin),
5485 .scan_out(ff_dir_addr_cnt_c7_scanout),
5486 .dout(dir_addr_cnt_c7[10:0]),
5487 .siclk(siclk),
5488 .soclk(soclk)
5489);
5490
5491
5492
5493 /////////////////
5494 // sent to the CSR
5495 // block for ERR
5496 // reporting.
5497 /////////////////
5498
5499l2t_arb_ctl_msff_ctl_macro__width_11 ff_dir_addr_c8
5500 (.din(dir_addr_cnt_c7[10:0]), .l1clk(l1clk),
5501 .scan_in(ff_dir_addr_c8_scanin),
5502 .scan_out(ff_dir_addr_c8_scanout),
5503 .dout(dir_addr_cnt_c8[10:0]),
5504 .siclk(siclk),
5505 .soclk(soclk)
5506);
5507
5508l2t_arb_ctl_msff_ctl_macro__width_11 ff_dir_addr_c9
5509 (.din(dir_addr_cnt_c8[10:0]), .l1clk(l1clk),
5510 .scan_in(ff_dir_addr_c9_scanin),
5511 .scan_out(ff_dir_addr_c9_scanout),
5512 .dout(arb_dir_addr_c9[10:0]),
5513 .siclk(siclk),
5514 .soclk(soclk)
5515);
5516
5517
5518
5519////////////////////////////////////////////////////////////////////////
5520// 9. Rd/Wr entry number
5521////////////////////////////////////////////////////////////////////////
5522
5523// BS 03/25/04 for partial bank/core modes support
5524
5525//assign spc0_avl = ncu_spc0_core_enable_status;
5526//assign spc1_avl = ncu_spc1_core_enable_status;
5527//assign spc2_avl = ncu_spc2_core_enable_status;
5528//assign spc3_avl = ncu_spc3_core_enable_status;
5529//assign spc4_avl = ncu_spc4_core_enable_status;
5530//assign spc5_avl = ncu_spc5_core_enable_status;
5531//assign spc6_avl = ncu_spc6_core_enable_status;
5532//assign spc7_avl = ncu_spc7_core_enable_status;
5533
5534l2t_arb_ctl_msff_ctl_macro__width_1 ff_sync_en
5535 (
5536 .scan_in(ff_sync_en_scanin),
5537 .scan_out(ff_sync_en_scanout),
5538 .dout (io_cmp_sync_en_r1),
5539 .din (io_cmp_sync_en),
5540 .l1clk (l1clk),
5541 .siclk(siclk),
5542 .soclk(soclk)
5543 );
5544
5545l2t_arb_ctl_msff_ctl_macro__en_1__width_8 ff_ncu_signals
5546 (
5547 .scan_in(ff_ncu_signals_scanin),
5548 .scan_out(ff_ncu_signals_scanout),
5549 .dout ({spc0_avl,
5550 spc1_avl,
5551 spc2_avl,
5552 spc3_avl,
5553 spc4_avl,
5554 spc5_avl,
5555 spc6_avl,
5556 spc7_avl_unused}),
5557 .din ({ ncu_spc0_core_enable_status,
5558 ncu_spc1_core_enable_status,
5559 ncu_spc2_core_enable_status,
5560 ncu_spc3_core_enable_status,
5561 ncu_spc4_core_enable_status,
5562 ncu_spc5_core_enable_status,
5563 ncu_spc6_core_enable_status,
5564 ncu_spc7_core_enable_status}),
5565 .l1clk (l1clk),
5566 .en (io_cmp_sync_en_r1),
5567 .siclk(siclk),
5568 .soclk(soclk)
5569 );
5570
5571
5572
5573l2t_arb_ctl_msff_ctl_macro__width_3 ff_staged_part_bank
5574 (
5575 .scan_in(ff_staged_part_bank_scanin),
5576 .scan_out(ff_staged_part_bank_scanout),
5577 .dout ({arbadr_ncu_l2t_pm_n,
5578 arbadr_2bnk_true_enbld,
5579 arbadr_4bnk_true_enbld}),
5580 .din ({arbadr_ncu_l2t_pm_n_dist,
5581 arbadr_2bnk_true_enbld_dist,
5582 arbadr_4bnk_true_enbld_dist}),
5583 .l1clk (l1clk),
5584 .siclk(siclk),
5585 .soclk(soclk)
5586 );
5587
5588
5589assign arb_cpuid_dec_c2[0] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b000);
5590assign arb_cpuid_dec_c2[1] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b001);
5591assign arb_cpuid_dec_c2[2] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b010);
5592assign arb_cpuid_dec_c2[3] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b011);
5593assign arb_cpuid_dec_c2[4] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b100);
5594assign arb_cpuid_dec_c2[5] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b101);
5595assign arb_cpuid_dec_c2[6] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b110);
5596assign arb_cpuid_dec_c2[7] = (arbdec_arbdp_cpuid_c2[2:0] == 3'b111);
5597
5598
5599
5600
5601
5602assign sum01 = {1'b0,spc0_avl} + {1'b0,spc1_avl};
5603assign sum012 = {1'b0,spc0_avl} + {1'b0,spc1_avl} + {1'b0,spc2_avl};
5604assign sum0123 = {2'b00,spc0_avl} + {2'b00,spc1_avl} + {2'b00,spc2_avl} + {2'b00,spc3_avl};
5605assign sum01234 = {2'b00,spc0_avl} + {2'b00,spc1_avl} + {2'b00,spc2_avl} + {2'b00,spc3_avl} + {2'b00,spc4_avl};
5606assign sum012345 = {2'b00,spc0_avl} + {2'b00,spc1_avl} + {2'b00,spc2_avl} + {2'b00,spc3_avl} + {2'b00,spc4_avl} + {2'b00,spc5_avl};
5607assign sum0123456 = {2'b00,spc0_avl} + {2'b00,spc1_avl} + {2'b00,spc2_avl} + {2'b00,spc3_avl} + {2'b00,spc4_avl} + {2'b00,spc5_avl}
5608 + {2'b00,spc6_avl};
5609
5610assign sum0 = spc0_avl;
5611
5612assign sel_bot_seg = (arb_cpuid_dec_c2[0]) |
5613 (arb_cpuid_dec_c2[1] & (sum0 == 1'b0)) |
5614 (arb_cpuid_dec_c2[2] & (sum01 == 2'b00)) |
5615 (arb_cpuid_dec_c2[3] & (sum012 == 2'b00)) |
5616 (arb_cpuid_dec_c2[4] & (sum0123 == 3'b000)) |
5617 (arb_cpuid_dec_c2[5] & (sum01234 == 3'b000)) |
5618 (arb_cpuid_dec_c2[6] & (sum012345 == 3'b000)) |
5619 (arb_cpuid_dec_c2[7] & (sum0123456 == 3'b000));
5620
5621assign sel_00 = sel_bot_seg;
5622assign sel_01 = (arb_cpuid_dec_c2[1] & (sum0 == 1'b1)) |
5623 (arb_cpuid_dec_c2[2] & (sum01 == 2'b01)) |
5624 (arb_cpuid_dec_c2[3] & (sum012 == 2'b01)) |
5625 (arb_cpuid_dec_c2[4] & (sum0123 == 3'b001)) |
5626 (arb_cpuid_dec_c2[5] & (sum01234 == 3'b001)) |
5627 (arb_cpuid_dec_c2[6] & (sum012345 == 3'b001)) |
5628 (arb_cpuid_dec_c2[7] & (sum0123456 == 3'b001));
5629
5630assign sel_10 = (arb_cpuid_dec_c2[2] & (sum01 == 2'b10)) |
5631 (arb_cpuid_dec_c2[3] & (sum012 == 2'b10)) |
5632 (arb_cpuid_dec_c2[4] & (sum0123 == 3'b010)) |
5633 (arb_cpuid_dec_c2[5] & (sum01234 == 3'b010)) |
5634 (arb_cpuid_dec_c2[6] & (sum012345 == 3'b010)) |
5635 (arb_cpuid_dec_c2[7] & (sum0123456 == 3'b010));
5636
5637assign sel_11 = (arb_cpuid_dec_c2[3] & (sum012 == 2'b11)) |
5638 (arb_cpuid_dec_c2[4] & (sum0123 == 3'b011)) |
5639 (arb_cpuid_dec_c2[5] & (sum01234 == 3'b011)) |
5640 (arb_cpuid_dec_c2[6] & (sum012345 == 3'b011)) |
5641 (arb_cpuid_dec_c2[7] & (sum0123456 == 3'b011));
5642
5643//assign arb_dirvec_cpu0_sel00 = arbadr_4bnk_true_enbld & sum0;
5644//assign arb_dirvec_cpu0_selbot = arbadr_2bnk_true_enbld & sum0; // fix for bug 93049, had a typo here.
5645// // should have been arbadr_2bnk_true_enbld
5646// // instead of "arbadr_4bnk_true_enbld"
5647//
5648//assign arb_dirvec_cpu1_sel00 = arbadr_4bnk_true_enbld & ~sum0 & (sum01==2'b01);
5649//assign arb_dirvec_cpu1_sel01 = arbadr_4bnk_true_enbld & (sum01==2'b10);
5650//assign arb_dirvec_cpu1_selbot = arbadr_2bnk_true_enbld & ~sum0 & (sum01==2'b01);
5651//assign arb_dirvec_cpu1_seltop = arbadr_2bnk_true_enbld & (sum01==2'b10);
5652//
5653//assign arb_dirvec_cpu2_sel00 = arbadr_4bnk_true_enbld & (sum01==2'b00) & (sum012 == 2'b01);
5654//assign arb_dirvec_cpu2_sel01 = arbadr_4bnk_true_enbld & (sum01==2'b01) & (sum012 == 2'b10);
5655//assign arb_dirvec_cpu2_sel10 = arbadr_4bnk_true_enbld & (sum01==2'b10) & (sum012 == 2'b11);
5656//assign arb_dirvec_cpu2_selbot = arbadr_2bnk_true_enbld & (sum01==2'b00) & (sum012 == 2'b01);
5657//assign arb_dirvec_cpu2_seltop = arbadr_2bnk_true_enbld & (sum01==2'b01) & (sum012 == 2'b10);
5658//
5659//assign arb_dirvec_cpu3_sel00 = arbadr_4bnk_true_enbld & (sum012 == 2'b00) & (sum0123 == 3'b001);
5660//assign arb_dirvec_cpu3_sel01 = arbadr_4bnk_true_enbld & (sum012 == 2'b01) & (sum0123 == 3'b010);
5661//assign arb_dirvec_cpu3_sel10 = arbadr_4bnk_true_enbld & (sum012 == 2'b10) & (sum0123 == 3'b011);
5662//assign arb_dirvec_cpu3_sel11 = arbadr_4bnk_true_enbld & (sum012 == 2'b11) & (sum0123 == 3'b100);
5663//assign arb_dirvec_cpu3_selbot = arbadr_2bnk_true_enbld & (sum012 == 2'b00) & (sum0123 == 3'b001);
5664//assign arb_dirvec_cpu3_seltop = arbadr_2bnk_true_enbld & (sum012 == 2'b01) & (sum0123 == 3'b010);
5665//
5666//assign arb_dirvec_cpu4_sel00 = arbadr_4bnk_true_enbld & (sum0123 == 3'b000) & (sum01234 == 3'b001);
5667//assign arb_dirvec_cpu4_sel01 = arbadr_4bnk_true_enbld & (sum0123 == 3'b001) & (sum01234 == 3'b010);
5668//assign arb_dirvec_cpu4_sel10 = arbadr_4bnk_true_enbld & (sum0123 == 3'b010) & (sum01234 == 3'b011);
5669//assign arb_dirvec_cpu4_sel11 = arbadr_4bnk_true_enbld & (sum0123 == 3'b011) & (sum01234 == 3'b100);
5670//assign arb_dirvec_cpu4_selbot = arbadr_2bnk_true_enbld & (sum0123 == 3'b000) & (sum01234 == 3'b001);
5671//assign arb_dirvec_cpu4_seltop = arbadr_2bnk_true_enbld & (sum0123 == 3'b001) & (sum01234 == 3'b010);
5672//
5673//assign arb_dirvec_cpu5_sel00 = arbadr_4bnk_true_enbld & (sum01234 == 3'b000) & (sum012345== 3'b001);
5674//assign arb_dirvec_cpu5_sel01 = arbadr_4bnk_true_enbld & (sum01234 == 3'b001) & (sum012345== 3'b010);
5675//assign arb_dirvec_cpu5_sel10 = arbadr_4bnk_true_enbld & (sum01234 == 3'b010) & (sum012345== 3'b011);
5676//assign arb_dirvec_cpu5_sel11 = arbadr_4bnk_true_enbld & (sum01234 == 3'b011) & (sum012345== 3'b100);
5677//assign arb_dirvec_cpu5_selbot = arbadr_2bnk_true_enbld & (sum01234 == 3'b000) & (sum012345 == 3'b001);
5678//assign arb_dirvec_cpu5_seltop = arbadr_2bnk_true_enbld & (sum01234 == 3'b001) & (sum012345 == 3'b010);
5679//
5680//assign arb_dirvec_cpu6_sel00 = arbadr_4bnk_true_enbld & (sum012345 == 3'b000) & (sum0123456 == 3'b001);
5681//assign arb_dirvec_cpu6_sel01 = arbadr_4bnk_true_enbld & (sum012345 == 3'b001) & (sum0123456 == 3'b010);
5682//assign arb_dirvec_cpu6_sel10 = arbadr_4bnk_true_enbld & (sum012345 == 3'b010) & (sum0123456 == 3'b011);
5683//assign arb_dirvec_cpu6_sel11 = arbadr_4bnk_true_enbld & (sum012345 == 3'b011) & (sum0123456 == 3'b100);
5684//assign arb_dirvec_cpu6_selbot = arbadr_2bnk_true_enbld & (sum012345 == 3'b000) & (sum0123456 == 3'b001);
5685//assign arb_dirvec_cpu6_seltop = arbadr_2bnk_true_enbld & (sum012345 == 3'b001) & (sum0123456 == 3'b010);
5686//
5687//assign arb_dirvec_cpu7_sel00 = arbadr_4bnk_true_enbld & (sum0123456 == 3'b000) & spc7_avl;
5688//assign arb_dirvec_cpu7_sel01 = arbadr_4bnk_true_enbld & (sum0123456 == 3'b001) & spc7_avl;
5689//assign arb_dirvec_cpu7_sel10 = arbadr_4bnk_true_enbld & (sum0123456 == 3'b010) & spc7_avl;
5690//assign arb_dirvec_cpu7_sel11 = arbadr_4bnk_true_enbld & (sum0123456 == 3'b011) & spc7_avl;
5691//assign arb_dirvec_cpu7_selbot = arbadr_2bnk_true_enbld & (sum0123456 == 3'b000) & spc7_avl;
5692//assign arb_dirvec_cpu7_seltop = arbadr_2bnk_true_enbld & (sum0123456 == 3'b001) & spc7_avl;
5693//
5694
5695l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_2 sel_segment
5696 (.dout (seg[1:0]),
5697 .din0 (2'b00),
5698 .din1 (2'b01),
5699 .din2 (2'b10),
5700 .din3 (2'b11),
5701 .sel0 (sel_00),
5702 .sel1 (sel_01),
5703 .sel2 (sel_10),
5704 .sel3 (sel_11)
5705 );
5706
5707
5708
5709l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_3 mux_arb_cpuid_fnl_c2
5710 (.dout (arb_cpuid_fnl_c2[2:0]) ,
5711 .din0(arbdec_arbdp_cpuid_c2[2:0]), // original cpuid , all banks enabled
5712 .din1({seg[1:0],arbadr_arbdp_addr87_c2[1]}), // bit[8] in case of 4 banks enabled
5713 .din2({~sel_bot_seg,arbadr_arbdp_addr87_c2[1:0]}), // bits 8:7 in case of 2 banks enabled
5714 // fix for bug 93607, msb should be 1'b0 when sel_bot_seg = 1
5715 .sel0(arbadr_ncu_l2t_pm_n),
5716 .sel1(arbadr_4bnk_true_enbld),
5717 .sel2(arbadr_2bnk_true_enbld)
5718 );
5719
5720
5721
5722l2t_arb_ctl_msff_ctl_macro__width_3 ff_arb_cpuid_c3
5723 ( .din(arb_cpuid_fnl_c2), .l1clk(l1clk),
5724 .scan_in(ff_arb_cpuid_c3_scanin),
5725 .scan_out(ff_arb_cpuid_c3_scanout),
5726 .dout(arb_cpuid_c3),
5727 .siclk(siclk),
5728 .soclk(soclk)
5729 );
5730
5731l2t_arb_ctl_msff_ctl_macro__width_3 ff_arb_cpuid_c4
5732 ( .din(arb_cpuid_c3), .l1clk(l1clk),
5733 .scan_in(ff_arb_cpuid_c4_scanin),
5734 .scan_out(ff_arb_cpuid_c4_scanout),
5735 .dout(arb_cpuid_c4),
5736 .siclk(siclk),
5737 .soclk(soclk)
5738 );
5739
5740l2t_arb_ctl_msff_ctl_macro__width_3 ff_arb_cpuid_c5
5741 ( .din(arb_cpuid_c4), .l1clk(l1clk),
5742 .scan_in(ff_arb_cpuid_c5_scanin),
5743 .scan_out(ff_arb_cpuid_c5_scanout),
5744 .dout(arb_cpuid_c5),
5745 .siclk(siclk),
5746 .soclk(soclk)
5747 );
5748
5749l2t_arb_ctl_msff_ctl_macro__width_3 ff_arb_cpuid_c52
5750 ( .din(arb_cpuid_c5), .l1clk(l1clk),
5751 .scan_in(ff_arb_cpuid_c52_scanin),
5752 .scan_out(ff_arb_cpuid_c52_scanout),
5753 .dout(arb_cpuid_c52),
5754 .siclk(siclk),
5755 .soclk(soclk)
5756 );
5757
5758
5759 assign dir_entry_c3 = { arb_cpuid_c3, arbdec_arbdp_l1way_c3 } ;
5760 assign dir_entry_c4 = { arb_cpuid_c4, 2'b01 } ;
5761 assign dir_entry_c5 = { arb_cpuid_c5, 2'b10 } ;
5762 assign dir_entry_c52 = { arb_cpuid_c52, 2'b11 } ; // BS 03/11/04 extra cycle for mem access
5763
5764 assign def_inval_entry = ~( inval_inst_vld_c4 |
5765 inval_inst_vld_c5 |
5766 inval_inst_vld_c52 ) ; // BS 03/11/04 extra cycle for mem access
5767
5768l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_inval_dir_entry_c3
5769 (.dout (tmp_wr_dir_entry_c3[4:0]),
5770 .din0(dir_entry_c3[4:0]), .din1(dir_entry_c4[4:0]),
5771 .din2(dir_entry_c5[4:0]), .din3(dir_entry_c52[4:0]),
5772 .sel0(def_inval_entry), .sel1(inval_inst_vld_c4),
5773 .sel2(inval_inst_vld_c5), .sel3(inval_inst_vld_c52)); // BS 03/11/04 extra cycle for mem access
5774
5775
5776 assign wr_dir_entry_c3[1:0] = tmp_wr_dir_entry_c3[1:0] & ~{2{inval_inst_vld_c3}} ;
5777 assign wr_dir_entry_c3[4:2] = tmp_wr_dir_entry_c3[4:2] ;
5778
5779
5780
5781l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 mux_dir_entry_c3
5782 (.dout (arb_wr_dc_dir_entry_c3[4:0]),
5783 .din0(dir_addr_cnt_c3[5:1]), .din1(wr_dir_entry_c3[4:0]),
5784 .sel0(store_inst_vld_c3_1), .sel1(~store_inst_vld_c3_1));
5785
5786// SR 12/6/04 : Dir changes toggle ic dir entry for 8 clocks instead of 4
5787
5788l2t_arb_ctl_msff_ctl_macro__width_5 ff_arb_ic_dir_wrentry_c4
5789 (
5790 .scan_in(ff_arb_ic_dir_wrentry_c4_scanin),
5791 .scan_out(ff_arb_ic_dir_wrentry_c4_scanout),
5792 .din(arb_wr_dc_dir_entry_c3[4:0]),
5793 .l1clk(l1clk),
5794 .dout(arb_ic_dir_wrentry_c4[4:0]),
5795 .siclk(siclk),
5796 .soclk(soclk)
5797 );
5798l2t_arb_ctl_msff_ctl_macro__width_5 ff_arb_ic_dir_wrentry_c5
5799 (
5800 .scan_in(ff_arb_ic_dir_wrentry_c5_scanin),
5801 .scan_out(ff_arb_ic_dir_wrentry_c5_scanout),
5802 .din(arb_ic_dir_wrentry_c4[4:0]),
5803 .l1clk(l1clk),
5804 .dout(arb_ic_dir_wrentry_c5[4:0]),
5805 .siclk(siclk),
5806 .soclk(soclk)
5807 );
5808l2t_arb_ctl_msff_ctl_macro__width_5 ff_arb_ic_dir_wrentry_c6
5809 (
5810 .scan_in(ff_arb_ic_dir_wrentry_c6_scanin),
5811 .scan_out(ff_arb_ic_dir_wrentry_c6_scanout),
5812 .din(arb_ic_dir_wrentry_c5[4:0]),
5813 .l1clk(l1clk),
5814 .dout(arb_ic_dir_wrentry_c6[4:0]),
5815 .siclk(siclk),
5816 .soclk(soclk)
5817 );
5818
5819l2t_arb_ctl_msff_ctl_macro__width_5 ff_arb_ic_dir_wrentry_c7
5820 (
5821 .scan_in(ff_arb_ic_dir_wrentry_c7_scanin),
5822 .scan_out(ff_arb_ic_dir_wrentry_c7_scanout),
5823 .din(arb_ic_dir_wrentry_c6[4:0]),
5824 .l1clk(l1clk),
5825 .dout(arb_ic_dir_wrentry_c7[4:0]),
5826 .siclk(siclk),
5827 .soclk(soclk)
5828 );
5829
5830
5831assign inval_foric_vld = ic_inval_vld_c6 | arb_ic_inval_vld_c7 | arb_ic_inval_vld_c8 |
5832 arb_ic_inval_vld_c9;
5833
5834l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 mux_arb_wr_ic_dir_entry_c3
5835 (
5836 .dout(arb_wr_ic_dir_entry_c3[4:0]),
5837 .din0(arb_wr_dc_dir_entry_c3[4:0]),
5838 .din1(arb_ic_dir_wrentry_c7[4:0]),
5839 .sel0(~inval_foric_vld),
5840 .sel1(inval_foric_vld));
5841
5842// Not anymore since it is now 8 clocks
5843// assign arb_wr_ic_dir_entry_c3 = arb_wr_dc_dir_entry_c3 ;
5844//
5845
5846 assign arb_inval_inst_vld_c3 = inval_inst_vld_c3;
5847
5848////////////////////////////////////////////////////////////////////////
5849// 10. Rd/Wr Panel number
5850// BS and SR 11/18/03 Support for 8 way I$
5851// d$ panel number = X<10-9>, Y<5-4>
5852// i$ panel number = X<10-9>, Y<5,I$ l1 way[2]>
5853////////////////////////////////////////////////////////////////////////
5854
5855
5856 assign dc_wr_panel_c3 = { arbadr_arbdp_addr11to4_c3[6:4], arbadr_arbdp_addr11to4_c3[1:0]};
5857
5858l2t_arb_ctl_msff_ctl_macro__width_5 ff_dc_wr_panel_c4
5859 (.din(dc_wr_panel_c3[4:0]), .l1clk(l1clk),
5860 .scan_in(ff_dc_wr_panel_c4_scanin),
5861 .scan_out(ff_dc_wr_panel_c4_scanout),
5862 .dout(dc_wr_panel_c4[4:0]),
5863 .siclk(siclk),
5864 .soclk(soclk)
5865);
5866l2t_arb_ctl_msff_ctl_macro__width_5 ff_dc_wr_panel_c5
5867 (.din(dc_wr_panel_c4[4:0]), .l1clk(l1clk),
5868 .scan_in(ff_dc_wr_panel_c5_scanin),
5869 .scan_out(ff_dc_wr_panel_c5_scanout),
5870 .dout(dc_wr_panel_c5[4:0]),
5871 .siclk(siclk),
5872 .soclk(soclk)
5873);
5874
5875// BS 03/11/04 extra cycle for mem access
5876
5877l2t_arb_ctl_msff_ctl_macro__width_5 ff_dc_wr_panel_c52
5878 (.din(dc_wr_panel_c5[4:0]), .l1clk(l1clk),
5879 .scan_in(ff_dc_wr_panel_c52_scanin),
5880 .scan_out(ff_dc_wr_panel_c52_scanout),
5881 .dout(dc_wr_panel_c52[4:0]),
5882 .siclk(siclk),
5883 .soclk(soclk)
5884);
5885
5886l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_inval_dc_panel_c3
5887 (.dout (tmp_dc_wr_panel_c3[4:0]),
5888 .din0(dc_wr_panel_c3[4:0]), .din1(dc_wr_panel_c4[4:0]),
5889 .din2(dc_wr_panel_c5[4:0]), .din3(dc_wr_panel_c52[4:0]),
5890 .sel0(def_inval_entry), .sel1(inval_inst_vld_c4),
5891 .sel2(inval_inst_vld_c5), .sel3(inval_inst_vld_c52)); // BS 03/11/04 extra cycle for mem access
5892
5893l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 mux_dc_dir_panel_c3
5894 (.dout (arb_dir_panel_dcd_c3[4:0]),
5895 .din0(dir_addr_cnt_c3[10:6]), .din1(tmp_dc_wr_panel_c3[4:0]),
5896 .sel0(store_inst_vld_c3_2), .sel1(~store_inst_vld_c3_2));
5897
5898
5899// BS and SR 11/18/03 Support for 8 way I$
5900// Row Select for I$ panel
5901// Support for 8 way I$. Two rows need to be cammed out of 4 for every
5902// Load hit or Store hit. All four rows need to be cammed for an Eviction
5903// Each row holds I$ ways 0 through 3 or I$ ways 4 through 7.
5904// Row select = {addr[5],I$ L1 way[2]}
5905
5906l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdec_arbdp_inst_bufidlo_c3
5907 (.din(arbdec_arbdp_inst_bufidlo_c2), .l1clk(l1clk),
5908 .scan_in(ff_arbdec_arbdp_inst_bufidlo_c3_scanin),
5909 .scan_out(ff_arbdec_arbdp_inst_bufidlo_c3_scanout),
5910 .dout(arbdec_arbdp_inst_bufidlo_c3),
5911 .siclk(siclk),
5912 .soclk(soclk)
5913);
5914
5915assign ic_wr_panel_c3 = { arbadr_arbdp_addr11to4_c3[6:4], arbadr_arbdp_addr11to4_c3[1], arbdec_arbdp_inst_bufidlo_c3};
5916
5917
5918
5919l2t_arb_ctl_msff_ctl_macro__width_5 ff_ic_wr_panel_c4
5920 (.din(ic_wr_panel_c3[4:0]), .l1clk(l1clk),
5921 .scan_in(ff_ic_wr_panel_c4_scanin),
5922 .scan_out(ff_ic_wr_panel_c4_scanout),
5923 .dout(ic_wr_panel_c4[4:0]),
5924 .siclk(siclk),
5925 .soclk(soclk)
5926);
5927l2t_arb_ctl_msff_ctl_macro__width_5 ff_ic_wr_panel_c5
5928 (.din(ic_wr_panel_c4[4:0]), .l1clk(l1clk),
5929 .scan_in(ff_ic_wr_panel_c5_scanin),
5930 .scan_out(ff_ic_wr_panel_c5_scanout),
5931 .dout(ic_wr_panel_c5[4:0]),
5932 .siclk(siclk),
5933 .soclk(soclk)
5934);
5935
5936// BS 03/11/04 extra cycle for mem access
5937
5938l2t_arb_ctl_msff_ctl_macro__width_5 ff_ic_wr_panel_c52
5939 (.din(ic_wr_panel_c5[4:0]), .l1clk(l1clk),
5940 .scan_in(ff_ic_wr_panel_c52_scanin),
5941 .scan_out(ff_ic_wr_panel_c52_scanout),
5942 .dout(ic_wr_panel_c52[4:0]),
5943 .siclk(siclk),
5944 .soclk(soclk)
5945);
5946
5947
5948// SR 12/6/04 :: DIR changes
5949
5950
5951l2t_arb_ctl_msff_ctl_macro__width_5 ff_ic_wr_panel_c6
5952 (
5953 .scan_in(ff_ic_wr_panel_c6_scanin),
5954 .scan_out(ff_ic_wr_panel_c6_scanout),
5955 .din(ic_wr_panel_c52[4:0]),
5956 .l1clk(l1clk),
5957 .dout(ic_wr_panel_c6[4:0]),
5958 .siclk(siclk),
5959 .soclk(soclk)
5960 );
5961
5962l2t_arb_ctl_msff_ctl_macro__width_5 ff_ic_wr_panel_c7
5963 (
5964 .scan_in(ff_ic_wr_panel_c7_scanin),
5965 .scan_out(ff_ic_wr_panel_c7_scanout),
5966 .din(ic_wr_panel_c6[4:0]),
5967 .l1clk(l1clk),
5968 .dout(ic_wr_panel_c7[4:0]),
5969 .siclk(siclk),
5970 .soclk(soclk)
5971 );
5972l2t_arb_ctl_msff_ctl_macro__width_5 ff_ic_wr_panel_c8
5973 (
5974 .scan_in(ff_ic_wr_panel_c8_scanin),
5975 .scan_out(ff_ic_wr_panel_c8_scanout),
5976 .din(ic_wr_panel_c7[4:0]),
5977 .l1clk(l1clk),
5978 .dout(ic_wr_panel_c8[4:0]),
5979 .siclk(siclk),
5980 .soclk(soclk)
5981 );
5982l2t_arb_ctl_msff_ctl_macro__width_5 ff_ic_wr_panel_c9
5983 (
5984 .scan_in(ff_ic_wr_panel_c9_scanin),
5985 .scan_out(ff_ic_wr_panel_c9_scanout),
5986 .din(ic_wr_panel_c8[4:0]),
5987 .l1clk(l1clk),
5988 .dout(ic_wr_panel_c9[4:0]),
5989 .siclk(siclk),
5990 .soclk(soclk)
5991 );
5992
5993
5994assign mux_sel_ic_inval_678_n = ~(ic_inval_vld_c6 | arb_ic_inval_vld_c7 | arb_ic_inval_vld_c8);
5995
5996l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_inval_ic_panel_second_half
5997 (
5998 .dout (tmp_ic_wr_panel_c3_1[4:0]),
5999 .din0(ic_wr_panel_c6[4:0]), .din1(ic_wr_panel_c7[4:0]),
6000 .din2(ic_wr_panel_c8[4:0]), .din3(ic_wr_panel_c9[4:0]),
6001 .sel0(ic_inval_vld_c6), .sel1(arb_ic_inval_vld_c7),
6002 .sel2(arb_ic_inval_vld_c8), .sel3(mux_sel_ic_inval_678_n)
6003 );
6004
6005
6006assign mux_sel_ic_inval_6789 = ~mux_sel_ic_inval_678_n | arb_ic_inval_vld_c9;
6007
6008
6009l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_inval_ic_panel_c3
6010 (
6011 .dout (tmp_ic_wr_panel_c3[4:0]),
6012 .din0(ic_wr_panel_c3[4:0]), .din1(ic_wr_panel_c4[4:0]),
6013 .din2(ic_wr_panel_c5[4:0]), .din3(ic_wr_panel_c52[4:0]),
6014 .sel0(def_inval_entry), .sel1(inval_inst_vld_c4),
6015 .sel2(inval_inst_vld_c5), .sel3(inval_inst_vld_c52)
6016 );
6017
6018
6019assign fnl_sel_inval = ~store_inst_vld_c3_2 & mux_sel_ic_inval_6789;
6020assign fnl_sel_default = ~store_inst_vld_c3_2 & ~mux_sel_ic_inval_6789;
6021
6022
6023l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_5 mux_ic_dir_panel_c3
6024 (
6025 .dout (arb_dir_panel_icd_c3[4:0]),
6026 .din0(dir_addr_cnt_c3[10:6]),
6027 .din1(tmp_ic_wr_panel_c3[4:0]),
6028 .din2(tmp_ic_wr_panel_c3_1[4:0]),
6029 .sel0(store_inst_vld_c3_2), //.sel1(~store_inst_vld_c3_2)
6030 .sel1(fnl_sel_default),
6031 .sel2(fnl_sel_inval)
6032 );
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042 //////////////////////////////////////////////////////////////////////////
6043 // Valid bit written into the directory entries is
6044 // * 0 when an invalidation instruction is active
6045 // * 1 by default.
6046 //////////////////////////////////////////////////////////////////////////
6047
6048 assign arb_dir_vld_c3_l = ~( inval_inst_vld_c3 |
6049 inval_inst_vld_c4 |
6050 inval_inst_vld_c5 |
6051 inval_inst_vld_c52 |
6052 ic_inval_vld_c6 |
6053 arb_ic_inval_vld_c7 |
6054 arb_ic_inval_vld_c8 |
6055 arb_ic_inval_vld_c9) ;
6056
6057 //////////////////////////////////////////////////////////////////////////
6058 // 2nd cycle stall condition for WR64 and RD64
6059 //////////////////////////////////////////////////////////////////////////
6060 assign rdma_64B_stall = ( decdp_wr64_inst_c2_1 | arb_decdp_ld64_inst_c2 ) &
6061 arb_inst_vld_c2_7 ;
6062
6063l2t_arb_ctl_msff_ctl_macro__width_1 ff_wr64_inst_c3
6064 (.din(decdp_wr64_inst_c2_1), .l1clk(l1clk),
6065 .scan_in(ff_wr64_inst_c3_scanin),
6066 .scan_out(ff_wr64_inst_c3_scanout),
6067 .dout(wr64_inst_c3),
6068 .siclk(siclk),
6069 .soclk(soclk)
6070);
6071
6072 //////////////////////////////////////////////////////////////////////////
6073 // Way select gate
6074 // Way selects are turned off for the following types of operations.
6075 // * INterrupts
6076 // * L1 $ inval instructions.
6077 // * Prefetch ICE
6078 // * Fills.
6079 // * Diagnostic instructions.
6080 // * cas2 from the xbar.
6081 // * Tecc instructions.
6082 // * eviction instructions.
6083 //////////////////////////////////////////////////////////////////////////
6084
6085
6086 assign waysel_gate_c1 = ~( decdp_inst_int_or_inval_c1 | // int or inval instr.
6087 arbdec_arbdp_inst_fb_c1_qual | // Fills.
6088 arb_inst_diag_c1 | // diagnostic instruction
6089 decdp_cas2_from_xbar_c1 | // cas2 from xbar
6090 decdp_pf_ice_inst_c1 | // Prefetch Ice
6091 dec_evict_c1 | // eviction instruction.
6092 arbdec_arbdp_tecc_c1 ); // tecc instruction
6093
6094assign arb_l2drpt_waysel_gate_c1 = waysel_gate_c1;
6095
6096
6097
6098
6099l2t_arb_ctl_msff_ctl_macro__width_1 ff_waysel_gate_c2
6100 (.din(waysel_gate_c1), .l1clk(l1clk),
6101 .scan_in(ff_waysel_gate_c2_scanin),
6102 .scan_out(ff_waysel_gate_c2_scanout),
6103 .dout(arb_waysel_gate_c2),
6104 .siclk(siclk),
6105 .soclk(soclk)
6106);
6107
6108 //////////////////////////////////////////////////////////////////////////
6109 // Par err gate C1
6110 // Parity error is gated off for the tag under the following conditions:
6111 // - INterrupts
6112 // L1 $ inval instructions
6113 // Prefetch ICE
6114 // Fills
6115 // Diagnostic instructions
6116 // Tecc instructions
6117 //////////////////////////////////////////////////////////////////////////
6118
6119 assign parerr_gate_c1 = ~( decdp_inst_int_or_inval_c1 | // int or inval instr.
6120 (decdp_pf_ice_inst_c1 & ~arbdec_arbdp_evict_c1) | // Prefetch Ice 1st pass
6121 arbdec_arbdp_inst_fb_c1_qual | // Fills.
6122 arb_inst_diag_c1 |
6123 arbdec_arbdp_tecc_c1 );
6124
6125l2t_arb_ctl_msff_ctl_macro__width_1 ff_parerr_gate_c1
6126 (.din(parerr_gate_c1), .l1clk(l1clk),
6127 .scan_in(ff_parerr_gate_c1_scanin),
6128 .scan_out(ff_parerr_gate_c1_scanout),
6129 .dout(parerr_gate_c2),
6130 .siclk(siclk),
6131 .soclk(soclk)
6132);
6133
6134 assign arb_tagd_perr_vld_c2 = arb_inst_vld_c2
6135 & ~l2_bypass_mode_on_d1
6136 & parerr_gate_c2 ;
6137
6138
6139
6140 //////////////////////////////////////////////////////////////////////////
6141 // Stall logic.
6142 // The following instructions/events cause the C1 instruction in
6143 // the pipe to be stalled.
6144 // * evictions. (2 cycle stall )
6145 // * Fills. (2 cycle stall )
6146 // * Imiss. (1 cycle stall )
6147 // * tecc. (n cycle stall )
6148 // * diagnostic access. (data=2, tag=3, vuad=4)
6149 // * snoop access ( n cycle stall )
6150 // * SAme col stall
6151 //
6152 // The above multicycle stall conditions are detected in C1
6153 // and so is the same col stall. This is qualfied with
6154 // arb_unstalled_inst_c1.
6155 // WHen a multicycle instruction is in C2 or beyond, inst_vld_cn is
6156 // used for qualifying that instruction.
6157 //
6158 //////////////////////////////////////////////////////////////////////////
6159
6160 assign arb_multi_cyc_c1 = ( multi_cyc_op_c1 | // all mutlcyc ops except diagnostics.
6161 arb_inst_diag_c1 )
6162 & ~arb_stall_c2 & arb_inst_vld_c1_1 ; // unstalled valid instruction in C1.
6163
6164 //////////////////////////////////////////////////////////////////////////
6165 // imiss_col_stall_c1:
6166 //--------------------------------------------------------------------
6167 // instA C1 C2 C3
6168 // instB C1 stall C1 stall
6169 // OR
6170 // instB PX2 nostall C1 stall
6171 //--------------------------------------------------------------------
6172 // when an imiss packet is in C2, stall is high due to arb_multi_cyc_c1.
6173 // when the imiss packet is in C3, stall is high if the instruction stalled
6174 // in C1 or in PX2 accesses the same column as the second imiss packet .
6175 // ** arbadr_arbdp_new_addr5to4_px2 ** is the output of the address muxes in arbadr
6176 // not including the final stall mux.
6177 //////////////////////////////////////////////////////////////////////////
6178// px2 c1 c2 c3 C4
6179///////////////////////////////////////////////////////////////////////////////////////////////
6180// inst A imiss1
6181// stall_c1
6182// inst A imiss2 imiss1
6183// no_c1 Stall noc2stall
6184// same col inst B imiss Stall imiss2 imiss1
6185// ~same col inst B NoStall imiss2 imiss1
6186//
6187///////////////////////////////////////////////////////////////////////////////////////////////
6188
6189assign imiss_stall_op_c1inc1 = (arbadr_arbdp_addr5to4_c1[0] & arb_stall_c2 & arb_imiss_vld_c2 ) ;
6190
6191
6192//
6193//assign same_col_stall_c1 = ~arb_stall_c2 & (
6194// ( arb_inst_vld_c1_1 & (
6195// (~arbadr_arbdp_addr5to4_c1[1] & ~arbadr_arbdp_addr5to4_c1[0] & ~arbadr_arbdp_new_addr5to4_px2[0]) |
6196// (~arbadr_arbdp_addr5to4_c1[1] & arbadr_arbdp_addr5to4_c1[0] & arbadr_arbdp_new_addr5to4_px2[0]) |
6197// ( arbadr_arbdp_addr5to4_c1[1] & ~arbadr_arbdp_addr5to4_c1[0] & ~arbadr_arbdp_new_addr5to4_px2[0]) |
6198// ( arbadr_arbdp_addr5to4_c1[1] & arbadr_arbdp_addr5to4_c1[0] & arbadr_arbdp_new_addr5to4_px2[0]))) |
6199// ( arb_imiss_vld_c2 & arbadr_arbdp_new_addr5to4_px2[0] ));
6200//
6201
6202assign same_col_stall_c1 = ~arb_stall_c2 & (
6203 ( arb_inst_vld_c1_1 & (
6204 ( ~arbadr_arbdp_addr5to4_c1[0] & ~arbadr_arbdp_new_addr5to4_px2[0]) |
6205 ( arbadr_arbdp_addr5to4_c1[0] & arbadr_arbdp_new_addr5to4_px2[0]))) |
6206 ( arb_imiss_vld_c2 & arbadr_arbdp_new_addr5to4_px2[0] ));
6207
6208
6209
6210 //////////////////////////////////////////////////////////////////////////
6211 // same_col_stall_c1:
6212 //--------------------------------------------------------------------
6213 // instA C1 nostall C2
6214 // instB PX2 C1 stall
6215 //--------------------------------------------------------------------
6216 // If a packet in PX2 has the same address as a packet in C1 that is not
6217 // currently stalling in C1.
6218 //////////////////////////////////////////////////////////////////////////
6219
6220
6221 //////////////
6222 // The following component of stall does not require any qualification
6223 // since it already is qualified with inst vld in the appropriate stages.
6224// Notice that in the case of tecc or deccck stalls, the stall is asserted for
6225 // one more cycle than the operation itself so that the instruction stalled in
6226 // C1 can again access the tags and VUAD array.
6227 //////////////
6228
6229
6230 assign arb_prev_stall_c1 = arb_evict_vld_c2 | // evict last cyc
6231 (arb_fill_vld_c2 | arb_fill_vld_c3) | // fill last 2 cycles
6232 rdma_64B_stall | // 64B rdma access
6233 ( inval_inst_vld_c2 | inval_inst_vld_c3 | inval_inst_vld_c4 )| // inval cyc2-4
6234// SR 12/6/04 : Dir changes stall for 4 more clocks from c4
6235( ic_inval_vld_c5 | ic_inval_vld_c52 | ic_inval_vld_c6 | arb_ic_inval_vld_c7) |
6236 ( inst_l2data_vld_c2 ) | // data diag. last cyc
6237 ( inst_l2tag_vld_c2 | inst_l2tag_vld_c3 ) | // tag last 2 cycles
6238 ( inst_l2vuad_vld_c2 | inst_l2vuad_vld_c3 | inst_l2vuad_vld_c4 ) | // vuad last 3 cycles.
6239 ( inc_tag_ecc_cnt_c2 | inc_tag_ecc_cnt_c3 ) | // tecc stall
6240 ( data_ecc_active_c4 ) ; // deccck stall from tag.
6241
6242assign arb_stall_tmp_c1 = ( imiss_stall_op_c1inc1 ) |
6243 ( arb_multi_cyc_c1 ) |
6244 ( arb_prev_stall_c1 ) ;
6245
6246assign arb_stall_c1 = (arb_stall_tmp_c1 | same_col_stall_c1) ;
6247
6248l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_stall_c1
6249 (.din(arb_stall_c1), .l1clk(l1clk),
6250 .scan_in(ff_arb_stall_c1_scanin),
6251 .scan_out(ff_arb_stall_c1_scanout),
6252 .dout(arb_stall_unqual_c2),
6253 .siclk(siclk),
6254 .soclk(soclk)
6255);
6256
6257
6258assign arb_stall_c2 = arb_stall_unqual_c2 & arb_inst_vld_c1_1 ;
6259
6260//////////////////////////////////////////////////////////
6261//// instruction valid logic
6262// An instruction from the IQ/PCX without V=1 is considered
6263// to be an invalid instruction.
6264// Since the V bit is part of the payload, it is late arriving
6265// compared to the rdy bit.
6266//
6267// THe rdy bit is used to enable tag vuad and cam access.
6268// However, the V bit of the packet needs to be high
6269// for the instruction to be considered valid.
6270//////////////////////////////////////////////////////////
6271
6272 assign arb_inst_vld_px2 = ( arb_stall_c2 |
6273 mbsel_px2 |
6274 fbsel_px2 |
6275 snpsel_px2 |
6276 ( iqsel_px2 & ique_iq_arb_vbit_px2 )
6277 ) ;
6278
6279// int 5.0 change
6280// arbctl_inst_vld_c1 is used only for
6281// enabling the lkup in bw_r_cm16x40b i.e. fb,wb and rdma tags.
6282// This flop is disabled by the assertion of sehold.
6283
6284l2t_arb_ctl_msff_ctl_macro__clr_1__width_1 ff_arb_inst_vld_c1 // sync reset active low
6285 (.din(arb_inst_vld_px2), .l1clk(l1clk),
6286 .scan_in(ff_arb_inst_vld_c1_scanin),
6287 .scan_out(ff_arb_inst_vld_c1_scanout),
6288 .clr(~dbb_rst_l),
6289 .dout(arb_inst_vld_c1_fnl),
6290 .siclk(siclk),
6291 .soclk(soclk)
6292);
6293
6294assign mbist_any_tag_lookup = l2t_mb2_rdmatag_lookup_en | l2t_mb2_fbtag_lookup_en
6295 | l2t_mb2_wbtag_lookup_en;
6296
6297l2t_arb_ctl_msff_ctl_macro__width_7 ff_mbist_lookup_r1
6298 (
6299 .scan_in(ff_mbist_lookup_r1_scanin),
6300 .scan_out(ff_mbist_lookup_r1_scanout),
6301 .din({l2t_mb2_fbtag_lookup_en, l2t_mb2_wbtag_lookup_en,
6302 l2t_mb2_mbtag_lookup_en_r1, l2t_mb2_rdmatag_lookup_en,mbist_any_tag_lookup,mbist_any_tag_lookup_reg,mbist_any_tag_lookup_reg1}),
6303 .l1clk(l1clk),
6304 .dout({l2t_mb2_fbtag_lookup_en_r1, l2t_mb2_wbtag_lookup_en_r1,
6305 l2t_mb2_mbtag_lookup_en_r2, l2t_mb2_rdmatag_lookup_en_r1,mbist_any_tag_lookup_reg,mbist_any_tag_lookup_reg1,mbist_any_tag_lookup_reg2}),
6306 .siclk(siclk),
6307 .soclk(soclk)
6308 );
6309
6310
6311assign mbist_lookupen = (l2t_mb2_fbtag_lookup_en_r1 | l2t_mb2_wbtag_lookup_en_r1 |
6312 l2t_mb2_mbtag_lookup_en_r1 | l2t_mb2_rdmatag_lookup_en_r1);
6313
6314//assign arb_inst_vld_c1 = l2t_mb2_run_r1 ? (l2t_mb2_fbtag_lookup_en_r1 |
6315// l2t_mb2_wbtag_lookup_en_r1 | l2t_mb2_rdmatag_lookup_en_r1) : arb_inst_vld_c1_fnl;
6316
6317assign arb_inst_vld_c1 = l2t_mb2_run_r1 ? mbist_any_tag_lookup_reg2 : arb_inst_vld_c1_fnl;
6318
6319l2t_arb_ctl_msff_ctl_macro__clr_1__width_1 ff_arb_inst_vld_c1_1 // sync reset active low
6320 (.din(arb_inst_vld_px2), .l1clk(l1clk),
6321 .scan_in(ff_arb_inst_vld_c1_1_scanin),
6322 .scan_out(ff_arb_inst_vld_c1_1_scanout),
6323 .clr(~dbb_rst_l),
6324 .dout(arb_inst_vld_c1_1),
6325 .siclk(siclk),
6326 .soclk(soclk)
6327);
6328
6329 // the following expression indicates if an instruction will be
6330 // valid in the next cycle in the C2 stage.
6331
6332 assign inst_vld_c2_prev = arb_inst_vld_c1_1 & ~arb_stall_unqual_c2 ;
6333
6334 assign arb_inst_vld_c2_prev = arb_inst_vld_c1_1 & ~arb_stall_unqual_c2 ;
6335
6336// make 8 copies of instruction valid
6337// since it is heavily loaded.
6338
6339l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2
6340 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6341 .scan_in(ff_arb_inst_vld_c2_scanin),
6342 .scan_out(ff_arb_inst_vld_c2_scanout),
6343 .dout(arb_inst_vld_c2),
6344 .siclk(siclk),
6345 .soclk(soclk)
6346);
6347
6348l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_1
6349 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6350 .scan_in(ff_arb_inst_vld_c2_1_scanin),
6351 .scan_out(ff_arb_inst_vld_c2_1_scanout),
6352 .dout(arb_inst_vld_c2_1),
6353 .siclk(siclk),
6354 .soclk(soclk)
6355);
6356
6357l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_2
6358 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6359 .scan_in(ff_arb_inst_vld_c2_2_scanin),
6360 .scan_out(ff_arb_inst_vld_c2_2_scanout),
6361 .dout(arb_inst_vld_c2_2),
6362 .siclk(siclk),
6363 .soclk(soclk)
6364);
6365
6366l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_3
6367 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6368 .scan_in(ff_arb_inst_vld_c2_3_scanin),
6369 .scan_out(ff_arb_inst_vld_c2_3_scanout),
6370 .dout(arb_inst_vld_c2_3),
6371 .siclk(siclk),
6372 .soclk(soclk)
6373);
6374
6375l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_4
6376 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6377 .scan_in(ff_arb_inst_vld_c2_4_scanin),
6378 .scan_out(ff_arb_inst_vld_c2_4_scanout),
6379 .dout(arb_inst_vld_c2_4),
6380 .siclk(siclk),
6381 .soclk(soclk)
6382);
6383
6384l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_5
6385 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6386 .scan_in(ff_arb_inst_vld_c2_5_scanin),
6387 .scan_out(ff_arb_inst_vld_c2_5_scanout),
6388 .dout(arb_inst_vld_c2_5),
6389 .siclk(siclk),
6390 .soclk(soclk)
6391);
6392
6393l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_6
6394 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6395 .scan_in(ff_arb_inst_vld_c2_6_scanin),
6396 .scan_out(ff_arb_inst_vld_c2_6_scanout),
6397 .dout(arb_inst_vld_c2_6),
6398 .siclk(siclk),
6399 .soclk(soclk)
6400);
6401
6402l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_7
6403 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6404 .scan_in(ff_arb_inst_vld_c2_7_scanin),
6405 .scan_out(ff_arb_inst_vld_c2_7_scanout),
6406 .dout(arb_inst_vld_c2_7),
6407 .siclk(siclk),
6408 .soclk(soclk)
6409);
6410
6411 assign arb_tag_inst_vld_c2 = arb_inst_vld_c2_2;
6412
6413l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_8
6414 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6415 .scan_in(ff_arb_inst_vld_c2_8_scanin),
6416 .scan_out(ff_arb_inst_vld_c2_8_scanout),
6417 .dout(arb_inst_vld_c2_8),
6418 .siclk(siclk),
6419 .soclk(soclk)
6420);
6421
6422 assign arb_waysel_inst_vld_c2 = arb_inst_vld_c2_8 ; // to tag waysel comp.
6423
6424
6425
6426
6427
6428l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c2_10
6429 (.din(inst_vld_c2_prev), .l1clk(l1clk),
6430 .scan_in(ff_arb_inst_vld_c2_10_scanin),
6431 .scan_out(ff_arb_inst_vld_c2_10_scanout),
6432 .dout(arb_inst_vld_c2_10),
6433 .siclk(siclk),
6434 .soclk(soclk)
6435);
6436
6437 assign arb_rdwr_inst_vld_c2 = arb_inst_vld_c2_10 ; // to tag rdwr comp.
6438
6439// int 5.0 change
6440//msff_ctl_macro ff_arb_inst_vld_c2_11 (width=1)
6441// (.din(inst_vld_c2_prev), .l1clk(l1clk),
6442// .dout(arb_inst_vld_c2_11),
6443// .scan_in(),
6444// .scan_out()
6445//);
6446//
6447//assign arb_wen_inst_vld_c2 = arb_inst_vld_c2_11 ; // to tag word_en comp.
6448
6449
6450 assign arb_misbuf_inst_vld_c2 = arb_inst_vld_c2_3 ;
6451
6452// the following signal is flopped in filbuf
6453// assign arb_filbuf_inst_vld_c2 = arb_inst_vld_c2_4 ;
6454 assign arb_wbuf_inst_vld_c2 = arb_inst_vld_c2_5 ;
6455
6456l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c3
6457 (.din(arb_inst_vld_c2), .l1clk(l1clk),
6458 .scan_in(ff_arb_inst_vld_c3_scanin),
6459 .scan_out(ff_arb_inst_vld_c3_scanout),
6460 .dout(arb_inst_vld_c3),
6461 .siclk(siclk),
6462 .soclk(soclk)
6463);
6464
6465l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c3_1
6466 (.din(arb_inst_vld_c2_1), .l1clk(l1clk),
6467 .scan_in(ff_arb_inst_vld_c3_1_scanin),
6468 .scan_out(ff_arb_inst_vld_c3_1_scanout),
6469 .dout(arb_inst_vld_c3_1),
6470 .siclk(siclk),
6471 .soclk(soclk)
6472);
6473
6474l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_inst_vld_c3_2
6475 (.din(arb_inst_vld_c2_1), .l1clk(l1clk),
6476 .scan_in(ff_arb_inst_vld_c3_2_scanin),
6477 .scan_out(ff_arb_inst_vld_c3_2_scanout),
6478 .dout(arb_inst_vld_c3_2),
6479 .siclk(siclk),
6480 .soclk(soclk)
6481);
6482
6483// assign arb_dbg_inst_vld_c3 = arb_inst_vld_c3 ;
6484
6485 ////////////////////////////////////////////////////////////////////////
6486 // MB CAM hit DISABLE : arb_misbuf_hit_off_c1
6487 // Miss Buffer hit is disabled in the following conditions:
6488 // * MB or FB instruction.
6489 // * invalid instruction.
6490 // * INVAL instruction
6491 // * Diagnostic
6492 // * INterrupt instruction
6493 ////////////////////////////////////////////////////////////////////////
6494
6495//-----------\/ FIX for BUG#4619. Mb is cammed on a INVAL instruction as well \/---------
6496
6497 assign arb_misbuf_hit_off_c1 = ~arb_inst_vld_c1_1 | // invalid instruction
6498 // decdp_inst_int_or_inval_c1 | // int or inval c1
6499 arb_decdp_inst_int_c1 | // int C1
6500 arbdp_inst_mb_or_fb_c1 | // mb or fb
6501 arb_inst_diag_c1 ; // diagnostic access
6502
6503//-----------\/ FIX for BUG#4619. Mb is cammed on a INVAL instruction as well \/---------
6504
6505
6506 ////////////////////////////////////////////////////////////////////////
6507 // FB CAM hit DISABLE : arb_filbuf_hit_off_c1
6508 // Fill Buffer hit is disabled in the following conditions:
6509 // * FB instruction.
6510 // * invalid instruction.
6511 // * INVAL instruction
6512 // * Diagnostic
6513 // * INterrupt instruction
6514 // * TECC instruction.
6515 // * EVICT instruction
6516 ////////////////////////////////////////////////////////////////////////
6517
6518
6519 assign arb_filbuf_hit_off_c1 = ~arb_inst_vld_c1_1 | // invalid instruction
6520 decdp_inst_int_or_inval_c1 | // int or inval c1
6521 arbdec_arbdp_inst_fb_c1_qual | // mb or fb
6522 arb_inst_diag_c1 | // diagnostic access
6523 arbdec_arbdp_tecc_c1 | // tecc instruction
6524 dec_evict_c1 ; // eviction pass
6525
6526 ////////////////////////////////////////////////////////////////////////
6527 // WB CAM hit DISABLE : arb_wbuf_hit_off_c1
6528 // WB Buffer hit is disabled in the following conditions:
6529 // * FB instruction.
6530 // * invalid instruction.
6531 // * INVAL instruction
6532 // * Diagnostic
6533 // * INterrupt instruction
6534 // * TECC instruction.
6535 ////////////////////////////////////////////////////////////////////////
6536
6537
6538 assign arb_wbuf_hit_off_c1 = ~arb_inst_vld_c1_1 | // invalid instruction
6539 decdp_inst_int_or_inval_c1 | // int or inval c1
6540 arbdec_arbdp_inst_fb_c1_qual | // mb or fb
6541 arb_inst_diag_c1 | // diagnostic access
6542 arbdec_arbdp_tecc_c1 ; // tecc instruction
6543
6544
6545
6546
6547
6548 // Decode logic.
6549
6550 //////////////////////////////////////////////////////
6551 // unqualled eviction packet.
6552 // If an instruction is a TECC instruction then eviction
6553 // is turned off.Why?
6554 // An instruction making an eviction pass could detect a
6555 // TECC error. In this case, we mark the TECC bit in the
6556 // miss Buffer and also keep the EVICT bit set. When the
6557 // instruction makes its next pass through the L2 pipeline
6558 // It will cause TECC repair and reset TECC_READY.
6559 // The following pass will cause an eviction and reset EVICT_READY.
6560// IN order for this to happen, we need to set the EVICT bit for
6561// an EVICTIOn instruction with tecc=1.
6562//
6563 //////////////////////////////////////////////////////
6564
6565 assign dec_evict_c1 = arbdec_arbdp_evict_c1 & ~arbdec_arbdp_tecc_c1 ;
6566
6567l2t_arb_ctl_msff_ctl_macro__width_1 ff_dec_evict_c2
6568 (.din(dec_evict_c1), .l1clk(l1clk),
6569 .scan_in(ff_dec_evict_c2_scanin),
6570 .scan_out(ff_dec_evict_c2_scanout),
6571 .dout(dec_evict_c2),
6572 .siclk(siclk),
6573 .soclk(soclk)
6574);
6575
6576 assign dec_evict_tecc_c1 = arbdec_arbdp_evict_c1 & arbdec_arbdp_tecc_c1 ;
6577
6578l2t_arb_ctl_msff_ctl_macro__width_1 ff_dec_evict_tecc_c2
6579 (.din(dec_evict_tecc_c1), .l1clk(l1clk),
6580 .scan_in(ff_dec_evict_tecc_c2_scanin),
6581 .scan_out(ff_dec_evict_tecc_c2_scanout),
6582 .dout(dec_evict_tecc_c2),
6583 .siclk(siclk),
6584 .soclk(soclk)
6585);
6586
6587 assign arb_evict_tecc_vld_c2 = dec_evict_tecc_c2 &
6588 arb_inst_vld_c2_6 ;
6589
6590 //////////////////////////////////////////////////////
6591// normal store instruction
6592//////////////////////////////////////////////////////
6593assign decdp_st_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 & (
6594 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ ) |
6595 (( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `FWD_RQ ) &
6596 ~arbdec_arbdp_inst_nc_c1 ) );
6597
6598l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_st_inst_c2
6599 (.din(decdp_st_inst_c1),
6600 .scan_in(ff_decdp_st_inst_c2_scanin),
6601 .scan_out(ff_decdp_st_inst_c2_scanout),
6602 .l1clk(l1clk), .dout(arb_decdp_st_inst_c2),
6603 .siclk(siclk),
6604 .soclk(soclk)
6605);
6606
6607l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_st_inst_c2_1
6608 (.din(decdp_st_inst_c1),
6609 .scan_in(ff_decdp_st_inst_c2_1_scanin),
6610 .scan_out(ff_decdp_st_inst_c2_1_scanout),
6611 .l1clk(l1clk), .dout(decdp_st_inst_c2_1),
6612 .siclk(siclk),
6613 .soclk(soclk)
6614);
6615
6616l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_st_inst_c3
6617 (.din(decdp_st_inst_c2_1),
6618 .scan_in(ff_decdp_st_inst_c3_scanin),
6619 .scan_out(ff_decdp_st_inst_c3_scanout),
6620 .l1clk(l1clk), .dout(arb_decdp_st_inst_c3),
6621 .siclk(siclk),
6622 .soclk(soclk)
6623);
6624
6625l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_st_inst_c3_1
6626 (.din(decdp_st_inst_c2_1),
6627 .scan_in(ff_decdp_st_inst_c3_1_scanin),
6628 .scan_out(ff_decdp_st_inst_c3_1_scanout),
6629 .l1clk(l1clk), .dout(decdp_st_inst_c3_1),
6630 .siclk(siclk),
6631 .soclk(soclk)
6632);
6633
6634l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_st_inst_c3_2
6635 (.din(decdp_st_inst_c2_1),
6636 .scan_in(ff_decdp_st_inst_c3_2_scanin),
6637 .scan_out(ff_decdp_st_inst_c3_2_scanout),
6638 .l1clk(l1clk), .dout(decdp_st_inst_c3_2),
6639 .siclk(siclk),
6640 .soclk(soclk)
6641);
6642
6643
6644//////////////////////////////////////////////////////
6645// 1) A normal store with bit[109] = 1 is treated like a
6646// Block init store if it is performed to
6647// address 0 within a cacheline.
6648// bug #3395
6649// PCX[109] is used to denote an RMO store ( BST or BIST ).
6650// PCX[110] is used to denote a BST.
6651//////////////////////////////////////////////////////
6652
6653
6654
6655l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_inst_bufid1_c2
6656 (.din(arbdec_arbdp_inst_bufid1_c1), .l1clk(l1clk),
6657 .scan_in(ff_arbdp_inst_bufid1_c2_scanin),
6658 .scan_out(ff_arbdp_inst_bufid1_c2_scanout),
6659 .dout(inst_bufid1_c2),
6660 .siclk(siclk),
6661 .soclk(soclk)
6662);
6663
6664
6665assign decdp_bis_inst_c2 = arbadr_arbdp_addr_start_c2 & // addr<5:0> = 0
6666 ~arbdec_arbdp_rdma_inst_c2 &
6667 ~inst_bufid1_c2 & // implies a BST and not BIST
6668 ( arbdec_arbdp_inst_rqtyp_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ ) &
6669 arbdec_arbdp_inst_bufidlo_c2 ;
6670
6671assign decdp_bs_inst_c2 = arbadr_arbdp_addr_start_c2 & // addr<5:0> = 0
6672 ~arbdec_arbdp_rdma_inst_c2 &
6673 ( arbdec_arbdp_inst_rqtyp_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ ) &
6674 inst_bufid1_c2; // implies a BST
6675
6676assign arb_bs_or_bis_inst_c2 = decdp_bis_inst_c2 | decdp_bs_inst_c2; // BST or BIST
6677
6678
6679
6680l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_bis_inst_c2
6681 (.din(decdp_bis_inst_c2),
6682 .scan_in(ff_decdp_bis_inst_c2_scanin),
6683 .scan_out(ff_decdp_bis_inst_c2_scanout),
6684 .l1clk(l1clk), .dout(arb_decdp_bis_inst_c3),
6685 .siclk(siclk),
6686 .soclk(soclk)
6687);
6688
6689
6690
6691
6692
6693
6694assign decdp_rmo_st_c2 = ~arbdec_arbdp_rdma_inst_c2 & // not a JBI inst
6695 ( arbdec_arbdp_inst_rqtyp_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ ) &
6696 arbdec_arbdp_inst_bufidlo_c2 ;
6697
6698// BS 03/10/04 fix for bug : 80000, MAiD is being propagated from SPU to L2
6699// needs to be played back to SPU on bit 125 of CPX packet
6700
6701assign decdp_strst_maid1_c2 = ( arbdec_arbdp_inst_rqtyp_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STRST_RQ) &
6702 arbdec_arbdp_inst_bufidlo_c2 ;
6703
6704assign decdp_rmo_st_or_strst_maid1_c2 = decdp_rmo_st_c2 | decdp_strst_maid1_c2;
6705
6706l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_rmo_st_c3
6707 (.din(decdp_rmo_st_or_strst_maid1_c2),
6708 .scan_in(ff_decdp_rmo_st_c3_scanin),
6709 .scan_out(ff_decdp_rmo_st_c3_scanout),
6710 .l1clk(l1clk), .dout(arb_decdp_rmo_st_c3),
6711 .siclk(siclk),
6712 .soclk(soclk)
6713);
6714
6715assign decdp_rmo_st_or_strst_c2 = decdp_rmo_st_c2 | arb_decdp_strst_inst_c2;
6716
6717// rmo st or stream store will inval dir entry on a hit, will set inval_mask = 8'hff
6718// for stream store,dir entry inval will not depend on status of maid bit
6719
6720l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_rmo_or_strst_c3
6721 (.din(decdp_rmo_st_or_strst_c2),
6722 .scan_in(ff_decdp_rmo_or_strst_c3_scanin),
6723 .scan_out(ff_decdp_rmo_or_strst_c3_scanout),
6724 .l1clk(l1clk), .dout(decdp_rmo_st_or_strst_c3),
6725 .siclk(siclk),
6726 .soclk(soclk)
6727);
6728
6729
6730
6731//////////////////////////////////////////////////////
6732// streaming store
6733//////////////////////////////////////////////////////
6734assign decdp_strst_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
6735 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STRST_RQ) ;
6736
6737l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_strst_inst_c2
6738 (.din(decdp_strst_inst_c1),
6739 .scan_in(ff_decdp_strst_inst_c2_scanin),
6740 .scan_out(ff_decdp_strst_inst_c2_scanout),
6741 .l1clk(l1clk), .dout(arb_decdp_strst_inst_c2),
6742 .siclk(siclk),
6743 .soclk(soclk)
6744);
6745
6746
6747l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_strst_inst_c2_1
6748 (.din(decdp_strst_inst_c1),
6749 .scan_in(ff_decdp_strst_inst_c2_1_scanin),
6750 .scan_out(ff_decdp_strst_inst_c2_1_scanout),
6751 .l1clk(l1clk), .dout(decdp_strst_inst_c2_1),
6752 .siclk(siclk),
6753 .soclk(soclk)
6754);
6755
6756//////////////////////////////////////////////////////
6757// rdma store instructions.
6758//////////////////////////////////////////////////////
6759
6760assign decdp_wr8_inst_c1 = arbdec_arbdp_inst_rsvd_c1 &
6761 arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_LO+1] ;
6762
6763assign decdp_wr64_inst_c1 = arbdec_arbdp_inst_rsvd_c1 &
6764 arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_LO+2] ;
6765
6766l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_wr8_inst_c2
6767 (.din(decdp_wr8_inst_c1),
6768 .scan_in(ff_decdp_wr8_inst_c2_scanin),
6769 .scan_out(ff_decdp_wr8_inst_c2_scanout),
6770 .l1clk(l1clk), .dout(arb_decdp_wr8_inst_c2),
6771 .siclk(siclk),
6772 .soclk(soclk)
6773);
6774
6775l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_wr64_inst_c2
6776 (.din(decdp_wr64_inst_c1),
6777 .scan_in(ff_decdp_wr64_inst_c2_scanin),
6778 .scan_out(ff_decdp_wr64_inst_c2_scanout),
6779 .l1clk(l1clk), .dout(arb_decdp_wr64_inst_c2),
6780 .siclk(siclk),
6781 .soclk(soclk)
6782);
6783
6784l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_wr64_inst_c2_1
6785 (.din(decdp_wr64_inst_c1),
6786 .scan_in(ff_decdp_wr64_inst_c2_1_scanin),
6787 .scan_out(ff_decdp_wr64_inst_c2_1_scanout),
6788 .l1clk(l1clk), .dout(decdp_wr64_inst_c2_1),
6789 .siclk(siclk),
6790 .soclk(soclk)
6791);
6792
6793
6794
6795 //////////////////////////////////////////////////////
6796 // rdma ld instruction
6797 //////////////////////////////////////////////////////
6798
6799assign arb_decdp_ld64_inst_c1 = arbdec_arbdp_inst_rsvd_c1 &
6800 arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_LO] ;
6801
6802l2t_arb_ctl_msff_ctl_macro__width_1 ff_arb_decdp_ld64_inst_c1
6803 (.din(arb_decdp_ld64_inst_c1),
6804 .scan_in(ff_arb_decdp_ld64_inst_c1_scanin),
6805 .scan_out(ff_arb_decdp_ld64_inst_c1_scanout),
6806 .l1clk(l1clk), .dout(arb_decdp_ld64_inst_c2),
6807 .siclk(siclk),
6808 .soclk(soclk)
6809);
6810
6811
6812
6813
6814//////////////////////////////////////////////////////
6815// interrupt access to tagd via arb for disabling tag parity errors.
6816//////////////////////////////////////////////////////
6817
6818assign arb_decdp_inst_int_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
6819 ~arbdec_arbdp_evict_c1 &
6820 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `INT_RQ ) ;
6821
6822l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_inst_int_c2
6823 (.din(arb_decdp_inst_int_c1),
6824 .scan_in(ff_decdp_inst_int_c2_scanin),
6825 .scan_out(ff_decdp_inst_int_c2_scanout),
6826 .l1clk(l1clk), .dout(arb_decdp_inst_int_c2),
6827 .siclk(siclk),
6828 .soclk(soclk)
6829);
6830
6831// int 5.0 change
6832//msff_ctl_macro ff_decdp_inst_int_c3 (width=1)
6833// (.din(arb_decdp_inst_int_c2),
6834// .l1clk(l1clk), .dout(arb_decdp_inst_int_c3),
6835// .scan_in(),
6836// .scan_out()
6837//);
6838
6839// Bug fix 87786
6840//
6841//assign decdp_inst_int_or_inval_c1 = arb_decdp_inst_int_c1 |
6842// ( arbdec_arbdp_inst_bufidhi_c1 &
6843// ~arbdec_arbdp_inst_bufid1_c1 &
6844// ~arbdec_arbdp_inst_fb_c1_qual &
6845// ~arbdec_arbdp_inst_rsvd_c1 ) ;
6846//
6847
6848assign decdp_inst_int_or_inval_c1 = arb_decdp_inst_int_c1 |
6849 ( (decdp_pf_inst_c1 | decdp_ic_inval_c1 | decdp_dc_inval_c1) &
6850 ~arbdec_arbdp_inst_bufid1_c1 &
6851 ~arbdec_arbdp_inst_fb_c1_qual &
6852 ~arbdec_arbdp_inst_rsvd_c1 ) ;
6853
6854
6855
6856assign arbdp_inst_mb_or_fb_c1 = arbdec_arbdp_inst_mb_c1 |
6857 arbdec_arbdp_inst_fb_c1_qual ;
6858
6859
6860//////////////////////////////////////////////////////
6861 // the following decoded signals are required in vuad dp.
6862 // *pst with and without ctrue logic
6863 // *cas1 instruction decode.
6864 // *cas2 instruction decode.
6865 //////////////////////////////////////////////////////
6866
6867
6868 assign decdp_strpst_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
6869 ~arbdec_arbdp_evict_c1 &
6870 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STRST_RQ) &
6871 ~four_or_eight_byte_access_c1;// BS and SR 11/12/03 N2 Xbar Packet format change
6872
6873 // new net created to relieve timing pressure from the
6874 // arb_tag_pst_no_ctrue_c2 signal that is used
6875 // in the way_sel expression inside tag.
6876 // This expr does not need a ~RSVD qualification as that is
6877 // done inside tag.
6878
6879 // int 5.0 change
6880 assign wr8_inst_pst_c1 = ~arbdec_arbdp_evict_c1 &
6881 arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_LO+1] & ~four_or_eight_byte_access_c1;
6882 // BS and SR 11/12/03 N2 Xbar Packet format change :
6883
6884 assign decdp_rdmapst_inst_c1 = arbdec_arbdp_inst_rsvd_c1 &
6885 wr8_inst_pst_c1 ; // int 5.0 change
6886
6887 assign arb_wr8_inst_no_ctrue_c1 = wr8_inst_pst_c1 & ~arbdec_arbdp_inst_ctrue_c1; // int 5.0 change
6888
6889
6890// BS and SR 11/12/03 N2 Xbar Packet format change :
6891
6892 assign four_or_eight_byte_access_c1 = ((arbdec_arbdp_inst_size_c1[`L2_SZ_LO] & arbdec_arbdp_inst_size_c1[`L2_SZ_LO+1] &
6893 arbdec_arbdp_inst_size_c1[`L2_SZ_LO+2] & arbdec_arbdp_inst_size_c1[`L2_SZ_LO+3]) &
6894 (~arbdec_arbdp_inst_size_c1[`L2_SZ_HI] & ~arbdec_arbdp_inst_size_c1[`L2_SZ_HI-1] &
6895 ~arbdec_arbdp_inst_size_c1[`L2_SZ_HI-2] & ~arbdec_arbdp_inst_size_c1[`L2_SZ_HI-3]))
6896 // size [7:0] == 00001111
6897 |
6898 ((~arbdec_arbdp_inst_size_c1[`L2_SZ_LO] & ~arbdec_arbdp_inst_size_c1[`L2_SZ_LO+1] &
6899 ~arbdec_arbdp_inst_size_c1[`L2_SZ_LO+2] & ~arbdec_arbdp_inst_size_c1[`L2_SZ_LO+3]) &
6900 (arbdec_arbdp_inst_size_c1[`L2_SZ_HI] & arbdec_arbdp_inst_size_c1[`L2_SZ_HI-1] &
6901 arbdec_arbdp_inst_size_c1[`L2_SZ_HI-2] & arbdec_arbdp_inst_size_c1[`L2_SZ_HI-3]))
6902 // size [7:0] == 11110000
6903 |
6904 ((arbdec_arbdp_inst_size_c1[`L2_SZ_LO] & arbdec_arbdp_inst_size_c1[`L2_SZ_LO+1] &
6905 arbdec_arbdp_inst_size_c1[`L2_SZ_LO+2] & arbdec_arbdp_inst_size_c1[`L2_SZ_LO+3]) &
6906 (arbdec_arbdp_inst_size_c1[`L2_SZ_HI] & arbdec_arbdp_inst_size_c1[`L2_SZ_HI-1] &
6907 arbdec_arbdp_inst_size_c1[`L2_SZ_HI-2] & arbdec_arbdp_inst_size_c1[`L2_SZ_HI-3]));
6908 // size [7:0] == 11111111
6909
6910 assign eight_byte_access_c1 = ((arbdec_arbdp_inst_size_c1[`L2_SZ_LO] & arbdec_arbdp_inst_size_c1[`L2_SZ_LO+1] &
6911 arbdec_arbdp_inst_size_c1[`L2_SZ_LO+2] & arbdec_arbdp_inst_size_c1[`L2_SZ_LO+3]) &
6912 (arbdec_arbdp_inst_size_c1[`L2_SZ_HI] & arbdec_arbdp_inst_size_c1[`L2_SZ_HI-1] &
6913 arbdec_arbdp_inst_size_c1[`L2_SZ_HI-2] & arbdec_arbdp_inst_size_c1[`L2_SZ_HI-3]));
6914 // size [7:0] == 11111111
6915
6916//
6917// SR bug id 84953
6918// for a diagnostic access to data array both upper and lower 4 bytes
6919// have to be enabled. hence oring regular store byte with arb_inst_diag_c1
6920//
6921
6922 assign arb_upper_four_byte_access_c1 = (|(arbdec_arbdp_inst_size_c1[`L2_SZ_LO+3:`L2_SZ_LO]) | // for st
6923 arb_inst_diag_c1 ) ; // for diag
6924 assign arb_lower_four_byte_access_c1 = (|(arbdec_arbdp_inst_size_c1[`L2_SZ_LO+7:`L2_SZ_LO+4]) | // for st
6925 arb_inst_diag_c1 ) ; // for diag
6926
6927//
6928// assign decdp_pst_inst_c1 = ( ~arbdec_arbdp_inst_rsvd_c1 & // BS and SR 11/12/03 N2 Xbar Packet format change
6929// ~( arbadr_arbdp_ioaddr_c1_39to37[39:37] == 3'h5 ) & // int 5.0 change
6930// ~arbdec_arbdp_evict_c1 & (
6931// ( ~four_or_eight_byte_access_c1 &
6932// (( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ ) |
6933// ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STRST_RQ ))) |
6934// ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `SWAP_RQ ) )) |
6935// decdp_rdmapst_inst_c1 ;
6936//
6937//
6938
6939//// The below logic is cloned for timing reasons
6940
6941 assign decdp_pst_inst_c1_internal = ( ~arbdec_arbdp_inst_rsvd_c1 & // BS and SR 11/12/03 N2 Xbar Packet format change
6942 ~( arbadr_arbdp_ioaddr_c1_39to37[39:37] == 3'h5 ) & // int 5.0 change
6943 ~arbdec_arbdp_evict_c1 & (
6944 ( ~four_or_eight_byte_access_c1 &
6945 (( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ ) |
6946 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STRST_RQ ))) |
6947 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `SWAP_RQ ) )) |
6948 decdp_rdmapst_inst_c1 ;
6949
6950
6951
6952
6953
6954
6955 assign decdp_pst_st_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
6956 ~arbdec_arbdp_evict_c1 &
6957 ( ~four_or_eight_byte_access_c1 & // BS and SR 11/12/03 N2 Xbar Packet format change
6958 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ )) ;
6959
6960
6961 assign pst_no_ctrue_c1 = ( decdp_pst_inst_c1_internal &
6962 ~arbdec_arbdp_inst_ctrue_c1);
6963
6964 //////////////////////////////////////////////////////////////
6965 // arb_decdp_st_with_ctrue_c2:
6966 // This signal is used for generating an ERR packet
6967 // for PST 2nd passes that encountered an error during
6968 // the first pass.
6969 // All partial stores ( including atomic stores )
6970 // are included in this signal.
6971 //////////////////////////////////////////////////////////////
6972
6973l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pst_inst_c2
6974 (.din(decdp_pst_inst_c1_internal),
6975 .scan_in(ff_decdp_pst_inst_c2_scanin),
6976 .scan_out(ff_decdp_pst_inst_c2_scanout),
6977 .l1clk(l1clk), .dout(arb_decdp_pst_inst_c2),
6978 .siclk(siclk),
6979 .soclk(soclk)
6980);
6981
6982l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pst_inst_c3
6983 (.din(arb_decdp_pst_inst_c2),
6984 .scan_in(ff_decdp_pst_inst_c3_scanin),
6985 .scan_out(ff_decdp_pst_inst_c3_scanout),
6986 .l1clk(l1clk), .dout(decdp_pst_inst_c3),
6987 .siclk(siclk),
6988 .soclk(soclk)
6989);
6990
6991l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pst_inst_c4
6992 (.din(decdp_pst_inst_c3),
6993 .scan_in(ff_decdp_pst_inst_c4_scanin),
6994 .scan_out(ff_decdp_pst_inst_c4_scanout),
6995 .l1clk(l1clk), .dout(decdp_pst_inst_c4),
6996 .siclk(siclk),
6997 .soclk(soclk)
6998);
6999
7000l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pst_inst_c5
7001 (.din(decdp_pst_inst_c4),
7002 .scan_in(ff_decdp_pst_inst_c5_scanin),
7003 .scan_out(ff_decdp_pst_inst_c5_scanout),
7004 .l1clk(l1clk), .dout(decdp_pst_inst_c5),
7005 .siclk(siclk),
7006 .soclk(soclk)
7007);
7008
7009// BS 03/11/04 extra cycle for mem access
7010
7011l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pst_inst_c52
7012 (.din(decdp_pst_inst_c5),
7013 .scan_in(ff_decdp_pst_inst_c52_scanin),
7014 .scan_out(ff_decdp_pst_inst_c52_scanout),
7015 .l1clk(l1clk), .dout(decdp_pst_inst_c52),
7016 .siclk(siclk),
7017 .soclk(soclk)
7018);
7019
7020
7021l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pst_inst_c6
7022 (.din(decdp_pst_inst_c52),
7023 .scan_in(ff_decdp_pst_inst_c6_scanin),
7024 .scan_out(ff_decdp_pst_inst_c6_scanout),
7025 .l1clk(l1clk), .dout(decdp_pst_inst_c6),
7026 .siclk(siclk),
7027 .soclk(soclk)
7028);
7029
7030l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pst_inst_c7
7031 (.din(decdp_pst_inst_c6),
7032 .scan_in(ff_decdp_pst_inst_c7_scanin),
7033 .scan_out(ff_decdp_pst_inst_c7_scanout),
7034 .l1clk(l1clk), .dout(decdp_pst_inst_c7),
7035 .siclk(siclk),
7036 .soclk(soclk)
7037);
7038
7039 assign st_with_ctrue_c1 = (( decdp_pst_st_c1 | decdp_strpst_inst_c1 |
7040 decdp_rdmapst_inst_c1 | decdp_swap_inst_c1) & arbdec_arbdp_inst_ctrue_c1)
7041 | decdp_cas2_inst_c1 ;
7042
7043 // BS 03/04/05 : on cas2 and swap that had errors in
7044 // cas1 and swap/ldstub return phases, need to
7045 // return error type in cas2 and swap/ldstub acks.
7046
7047 // Fix for bug 90935
7048 // cas1 with UE/ND would not set ctrue bit and store would get blocked in tag_ctl
7049 // cas1 with CE would still set Ctrue bit and store would happen.
7050 // In both of the above cases, cas2 would send err packet on cas ack packet
7051
7052 // swap/ldstub with UE/ND would still set ctrue bit , but store would get blocked in tag_ctl
7053 // through misbuf_uncorr_err_c2
7054 // swap/ldstub with CE would set ctrue bit and store would be allowed to happen
7055 // In both of the above cases, swap/ldstub ack would drive err field as valid
7056
7057l2t_arb_ctl_msff_ctl_macro__width_1 ff_st_no_ctrue_c1
7058 (.din(st_with_ctrue_c1),
7059 .scan_in(ff_st_no_ctrue_c1_scanin),
7060 .scan_out(ff_st_no_ctrue_c1_scanout),
7061 .l1clk(l1clk), .dout(arb_decdp_st_with_ctrue_c2),
7062 .siclk(siclk),
7063 .soclk(soclk)
7064);
7065
7066
7067 assign decdp_cas1_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7068 ~arbdec_arbdp_evict_c1 &
7069 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `CAS1_RQ ) ;
7070
7071 assign decdp_cas1_inst_c1_1 = decdp_cas1_inst_c1;
7072
7073 assign decdp_cas2_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7074 ~arbdec_arbdp_evict_c1 &
7075 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `CAS2_RQ ) ;
7076
7077 assign decdp_cas2_from_mb_c1 = decdp_cas2_inst_c1
7078 & arbdec_arbdp_inst_mb_c1 ;
7079
7080
7081 assign decdp_cas2_from_mb_ctrue_c1 = decdp_cas2_from_mb_c1 &
7082 arbdec_arbdp_inst_ctrue_c1 ;
7083
7084 assign decdp_cas2_from_xbar_c1 = decdp_cas2_inst_c1
7085 & ~arbdec_arbdp_inst_mb_c1 ;
7086
7087
7088
7089 //////////////////////////////////////////////////////
7090 // The following signal indicates that a tecc repair
7091 // sequence needs to be initiated in arb.
7092 // The appropriate counters need to be initialized.
7093 //////////////////////////////////////////////////////
7094
7095 assign arbdp_tecc_inst_c1 = arbdec_arbdp_tecc_c1 & arbdec_arbdp_inst_mb_c1;
7096
7097l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_pst_no_ctrue_c2_1
7098 (.din(pst_no_ctrue_c1),
7099 .scan_in(ff_arbdp_pst_no_ctrue_c2_1_scanin),
7100 .scan_out(ff_arbdp_pst_no_ctrue_c2_1_scanout),
7101 .l1clk(l1clk), .dout(arbdp_pst_no_ctrue_c2_1),
7102 .siclk(siclk),
7103 .soclk(soclk)
7104);
7105
7106 //assign pst_with_ctrue_c1 = decdp_pst_inst_c1_internal
7107 // & arbdec_arbdp_inst_ctrue_c1 ;
7108
7109 // It is not necessary to use decdp_pst_inst_c1
7110 // Any instruction issued from the miss buffer with ctrue=1 is either
7111 // a partial store or a CAS2.
7112 assign pst_with_ctrue_c1 = arbdec_arbdp_inst_mb_c1
7113 & arbdec_arbdp_inst_ctrue_c1 ;
7114
7115 assign arb_tag_pst_with_ctrue_c1 = pst_with_ctrue_c1 ;
7116
7117
7118l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_pst_with_ctrue_c2
7119 (.din(pst_with_ctrue_c1),
7120 .scan_in(ff_arbdp_pst_with_ctrue_c2_scanin),
7121 .scan_out(ff_arbdp_pst_with_ctrue_c2_scanout),
7122 .l1clk(l1clk), .dout(arb_arbdp_pst_with_ctrue_c2),
7123 .siclk(siclk),
7124 .soclk(soclk)
7125);
7126
7127
7128l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_tag_pst_no_ctrue_c2
7129 (.din(pst_no_ctrue_c1),
7130 .scan_in(ff_arbdp_tag_pst_no_ctrue_c2_scanin),
7131 .scan_out(ff_arbdp_tag_pst_no_ctrue_c2_scanout),
7132 .l1clk(l1clk), .dout(arb_arbdp_tag_pst_no_ctrue_c2),
7133 .siclk(siclk),
7134 .soclk(soclk)
7135);
7136
7137l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_misbuf_pst_no_ctrue_c2
7138 (.din(pst_no_ctrue_c1),
7139 .scan_in(ff_arbdp_misbuf_pst_no_ctrue_c2_scanin),
7140 .scan_out(ff_arbdp_misbuf_pst_no_ctrue_c2_scanout),
7141 .l1clk(l1clk), .dout(arb_arbdp_misbuf_pst_no_ctrue_c2),
7142 .siclk(siclk),
7143 .soclk(soclk)
7144);
7145
7146l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_vuadctl_pst_no_ctrue_c2
7147 (.din(pst_no_ctrue_c1),
7148 .scan_in(ff_arbdp_vuadctl_pst_no_ctrue_c2_scanin),
7149 .scan_out(ff_arbdp_vuadctl_pst_no_ctrue_c2_scanout),
7150 .l1clk(l1clk), .dout(arb_arbdp_vuadctl_pst_no_ctrue_c2),
7151 .siclk(siclk),
7152 .soclk(soclk)
7153);
7154
7155
7156
7157 // multiple copies needed due to the loading internally.
7158l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c2
7159 (.din(decdp_cas1_inst_c1), .l1clk(l1clk),
7160 .scan_in(ff_decdp_cas1_inst_c2_scanin),
7161 .scan_out(ff_decdp_cas1_inst_c2_scanout),
7162 .dout(arb_decdp_cas1_inst_c2),
7163 .siclk(siclk),
7164 .soclk(soclk)
7165);
7166
7167l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c2_1
7168 (.din(decdp_cas1_inst_c1_1), .l1clk(l1clk),
7169 .scan_in(ff_decdp_cas1_inst_c2_1_scanin),
7170 .scan_out(ff_decdp_cas1_inst_c2_1_scanout),
7171 .dout(decdp_cas1_inst_c2_1),
7172 .siclk(siclk),
7173 .soclk(soclk)
7174);
7175
7176
7177l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas2_inst_c2
7178 (.din(decdp_cas2_inst_c1), .l1clk(l1clk),
7179 .scan_in(ff_decdp_cas2_inst_c2_scanin),
7180 .scan_out(ff_decdp_cas2_inst_c2_scanout),
7181 .dout(arb_decdp_cas2_inst_c2),
7182 .siclk(siclk),
7183 .soclk(soclk)
7184);
7185
7186l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas2_from_mb_c2
7187 (.din(decdp_cas2_from_mb_c1), .l1clk(l1clk),
7188 .scan_in(ff_decdp_cas2_from_mb_c2_scanin),
7189 .scan_out(ff_decdp_cas2_from_mb_c2_scanout),
7190 .dout(arb_decdp_cas2_from_mb_c2),
7191 .siclk(siclk),
7192 .soclk(soclk)
7193);
7194
7195l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas2_from_mb_ctrue_c2
7196 (.din(decdp_cas2_from_mb_ctrue_c1), .l1clk(l1clk),
7197 .scan_in(ff_decdp_cas2_from_mb_ctrue_c2_scanin),
7198 .scan_out(ff_decdp_cas2_from_mb_ctrue_c2_scanout),
7199 .dout(arb_decdp_cas2_from_mb_ctrue_c2),
7200 .siclk(siclk),
7201 .soclk(soclk)
7202);
7203
7204
7205
7206//////////////////////////////////////////////////////
7207 // This signal is used for RW bit in the L2_ESR
7208 // The following Store/Atomic instructions can encounter
7209 // an error while performing a Read
7210 // - Partial stores.
7211 // - LDSTUB/SWAP.
7212 // - CAS
7213 // - Streaming Partial stores.
7214 //////////////////////////////////////////////////////
7215
7216
7217 assign store_err_c2 = ( arb_decdp_pst_inst_c2 | decdp_cas1_inst_c2_1 ) &
7218 arb_inst_vld_c2_5 ;
7219
7220l2t_arb_ctl_msff_ctl_macro__width_1 ff_store_err_c3
7221 (.din(store_err_c2), .l1clk(l1clk),
7222 .scan_in(ff_store_err_c3_scanin),
7223 .scan_out(ff_store_err_c3_scanout),
7224 .dout(store_err_c3),
7225 .siclk(siclk),
7226 .soclk(soclk)
7227);
7228
7229l2t_arb_ctl_msff_ctl_macro__width_1 ff_store_err_c4
7230 (.din(store_err_c3), .l1clk(l1clk),
7231 .scan_in(ff_store_err_c4_scanin),
7232 .scan_out(ff_store_err_c4_scanout),
7233 .dout(store_err_c4),
7234 .siclk(siclk),
7235 .soclk(soclk)
7236);
7237
7238l2t_arb_ctl_msff_ctl_macro__width_1 ff_store_err_c5
7239 (.din(store_err_c4), .l1clk(l1clk),
7240 .scan_in(ff_store_err_c5_scanin),
7241 .scan_out(ff_store_err_c5_scanout),
7242 .dout(store_err_c5),
7243 .siclk(siclk),
7244 .soclk(soclk)
7245);
7246
7247// BS 03/11/04 extra cycle for mem access
7248
7249l2t_arb_ctl_msff_ctl_macro__width_1 ff_store_err_c52
7250 (.din(store_err_c5), .l1clk(l1clk),
7251 .scan_in(ff_store_err_c52_scanin),
7252 .scan_out(ff_store_err_c52_scanout),
7253 .dout(store_err_c52),
7254 .siclk(siclk),
7255 .soclk(soclk)
7256);
7257
7258
7259l2t_arb_ctl_msff_ctl_macro__width_1 ff_store_err_c6
7260 (.din(store_err_c52), .l1clk(l1clk),
7261 .scan_in(ff_store_err_c6_scanin),
7262 .scan_out(ff_store_err_c6_scanout),
7263 .dout(store_err_c6),
7264 .siclk(siclk),
7265 .soclk(soclk)
7266);
7267
7268l2t_arb_ctl_msff_ctl_macro__width_1 ff_store_err_c7
7269 (.din(store_err_c6), .l1clk(l1clk),
7270 .scan_in(ff_store_err_c7_scanin),
7271 .scan_out(ff_store_err_c7_scanout),
7272 .dout(store_err_c7),
7273 .siclk(siclk),
7274 .soclk(soclk)
7275);
7276
7277l2t_arb_ctl_msff_ctl_macro__width_1 ff_store_err_c8
7278 (.din(store_err_c7), .l1clk(l1clk),
7279 .scan_in(ff_store_err_c8_scanin),
7280 .scan_out(ff_store_err_c8_scanout),
7281 .dout(arb_store_err_c8),
7282 .siclk(siclk),
7283 .soclk(soclk)
7284);
7285
7286//////////////////////////////////////////////////////
7287// The following is used in RD./Wr logic in tag.
7288//////////////////////////////////////////////////////
7289assign arb_decdp_tag_wr_c1 = ( decdp_strst_inst_c1
7290 | decdp_st_inst_c1
7291 | decdp_wr8_inst_c1 )
7292 & ~decdp_pst_inst_c1_internal ;
7293
7294//////////////////////////////////////////////////////
7295// forward req
7296// used in arb to enable store invals for all
7297// cpus.
7298//////////////////////////////////////////////////////
7299
7300assign decdp_fwd_req_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7301 ~arbdec_arbdp_evict_c1 &
7302 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == 5'b01101 ) ;
7303
7304l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_fwd_req_c2
7305 (.din(decdp_fwd_req_c1), .l1clk(l1clk),
7306 .scan_in(ff_decdp_fwd_req_c2_scanin),
7307 .scan_out(ff_decdp_fwd_req_c2_scanout),
7308 .dout(arb_decdp_fwd_req_c2),
7309 .siclk(siclk),
7310 .soclk(soclk)
7311);
7312
7313
7314//////////////////////////////////////////////////////
7315// SWAP/LDSTUB decode
7316//////////////////////////////////////////////////////
7317
7318 assign decdp_swap_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7319 ~arbdec_arbdp_evict_c1 &
7320 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `SWAP_RQ ) ;
7321
7322l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_swap_inst_c2
7323 (.din(decdp_swap_inst_c1), .l1clk(l1clk),
7324 .scan_in(ff_decdp_swap_inst_c2_scanin),
7325 .scan_out(ff_decdp_swap_inst_c2_scanout),
7326 .dout(arb_decdp_swap_inst_c2),
7327 .siclk(siclk),
7328 .soclk(soclk)
7329);
7330
7331 //////////////////////////////////////////////////////
7332 // IMISS decode
7333 // Remember to disqualify INVAL instructions.
7334 //////////////////////////////////////////////////////
7335
7336 assign decdp_imiss_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7337 ~arbdec_arbdp_evict_c1 &
7338 ~arbdec_arbdp_inst_bufidhi_c1 &
7339 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `IMISS_RQ ) ;
7340
7341l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_imiss_inst_c2
7342 (.din(decdp_imiss_inst_c1),
7343 .scan_in(ff_decdp_imiss_inst_c2_scanin),
7344 .scan_out(ff_decdp_imiss_inst_c2_scanout),
7345 .l1clk(l1clk), .dout(arb_decdp_imiss_inst_c2),
7346 .siclk(siclk),
7347 .soclk(soclk)
7348);
7349
7350 //////////////////////////////////////////////////////
7351 // LD that cams the I$ decode
7352 // Streaming loads and FWD req loads are not included.
7353 //////////////////////////////////////////////////////
7354
7355
7356 assign decdp_camld_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7357 ~arbdec_arbdp_evict_c1 &
7358 ~arbdec_arbdp_inst_bufidhi_c1 &
7359 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ ) ;
7360
7361l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_camld_inst_c2
7362 (.din(decdp_camld_inst_c1),
7363 .scan_in(ff_decdp_camld_inst_c2_scanin),
7364 .scan_out(ff_decdp_camld_inst_c2_scanout),
7365 .l1clk(l1clk), .dout(decdp_camld_inst_c2),
7366 .siclk(siclk),
7367 .soclk(soclk)
7368);
7369
7370
7371 /////////////////////////////////////////////////////
7372 // Ld instruction decode for sending a request back
7373 // with data.
7374 /////////////////////////////////////////////////////
7375
7376
7377 assign decdp_ld_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7378 ~arbdec_arbdp_evict_c1 &
7379 ~arbdec_arbdp_inst_bufidhi_c1 &
7380 (( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) |
7381 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `MMU_RQ) | // BS and SR 11/12/03 N2 Xbar Packet format change
7382 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STRLOAD_RQ) |
7383 (( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `FWD_RQ) &
7384 arbdec_arbdp_inst_nc_c1 )
7385 );
7386
7387l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_ld_inst_c2
7388 (.din(decdp_ld_inst_c1), .l1clk(l1clk),
7389 .scan_in(ff_decdp_ld_inst_c2_scanin),
7390 .scan_out(ff_decdp_ld_inst_c2_scanout),
7391 .dout(arb_decdp_ld_inst_c2),
7392 .siclk(siclk),
7393 .soclk(soclk)
7394);
7395
7396 /////////////////////////////////////////////////////
7397 // Prefetch instruction.
7398 // At this time, the instruction is not qualified
7399 // so it could be an eviction pass of a prefetch
7400 // instruction. THe qualification is done in oqu.
7401 /////////////////////////////////////////////////////
7402
7403
7404 assign decdp_pf_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7405 arbdec_arbdp_inst_bufid1_c1 &
7406 ~arbdec_arbdp_inst_bufidhi_c1 & // inv bit = 0, pf bit = 1
7407 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ ) ;
7408
7409l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_inst_c2
7410 (.din(decdp_pf_inst_c1), .l1clk(l1clk),
7411 .scan_in(ff_decdp_pf_inst_c2_scanin),
7412 .scan_out(ff_decdp_pf_inst_c2_scanout),
7413 .dout(decdp_pf_inst_c2),
7414 .siclk(siclk),
7415 .soclk(soclk)
7416);
7417
7418l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_inst_c3
7419 (.din(decdp_pf_inst_c2), .l1clk(l1clk),
7420 .scan_in(ff_decdp_pf_inst_c3_scanin),
7421 .scan_out(ff_decdp_pf_inst_c3_scanout),
7422 .dout(decdp_pf_inst_c3),
7423 .siclk(siclk),
7424 .soclk(soclk)
7425);
7426
7427l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_inst_c4
7428 (.din(decdp_pf_inst_c3), .l1clk(l1clk),
7429 .scan_in(ff_decdp_pf_inst_c4_scanin),
7430 .scan_out(ff_decdp_pf_inst_c4_scanout),
7431 .dout(decdp_pf_inst_c4),
7432 .siclk(siclk),
7433 .soclk(soclk)
7434);
7435
7436l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_inst_c5
7437 (.din(decdp_pf_inst_c4), .l1clk(l1clk),
7438 .scan_in(ff_decdp_pf_inst_c5_scanin),
7439 .scan_out(ff_decdp_pf_inst_c5_scanout),
7440 .dout(arb_decdp_pf_inst_c5),
7441 .siclk(siclk),
7442 .soclk(soclk)
7443);
7444
7445 /////////////////////////////////////////////////////
7446 // Prefetch ICE instruction.
7447 // BS 06/24/04
7448 // Have to squash the DRAM read on a Prefetch ICE. Prefetch ICE should
7449 // miss in L2 tags , and get inserted in the Miss Buffer , but should
7450 // not assert a DRAM read request. It should cause the eviction pass
7451 // to happen using the way from PA[21:18] of the instruction itself.
7452 // In the eviction pass, the miss buffer entry will get deleted .
7453 /////////////////////////////////////////////////////
7454
7455assign decdp_pf_ice_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1 &
7456 arbdec_arbdp_inst_bufid1_c1 &
7457 arbdec_arbdp_inst_bufidhi_c1 & // inv bit = 1, pf bit = 1
7458 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ ) ;
7459
7460
7461l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_ice_inst_c2
7462 (.din(decdp_pf_ice_inst_c1), .l1clk(l1clk),
7463 .scan_in(ff_decdp_pf_ice_inst_c2_scanin),
7464 .scan_out(ff_decdp_pf_ice_inst_c2_scanout),
7465 .dout(arb_pf_ice_inst_c2),
7466 .siclk(siclk),
7467 .soclk(soclk)
7468);
7469
7470l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_ice_inst_c3
7471 (.din(arb_pf_ice_inst_c2), .l1clk(l1clk),
7472 .scan_in(ff_decdp_pf_ice_inst_c3_scanin),
7473 .scan_out(ff_decdp_pf_ice_inst_c3_scanout),
7474 .dout(decdp_pf_ice_inst_c3),
7475 .siclk(siclk),
7476 .soclk(soclk)
7477);
7478
7479//assign arb_iqu_pf_ice_stall_set = decdp_pf_ice_inst_c1 & arb_inst_vld_c1_1;
7480//assign arb_iqu_pf_ice_stall_clr = decdp_pf_ice_inst_c3 & arbdec_arbdp_inst_mb_c3;
7481
7482l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_ice_inst_c4
7483 (.din(decdp_pf_ice_inst_c3), .l1clk(l1clk),
7484 .scan_in(ff_decdp_pf_ice_inst_c4_scanin),
7485 .scan_out(ff_decdp_pf_ice_inst_c4_scanout),
7486 .dout(decdp_pf_ice_inst_c4),
7487 .siclk(siclk),
7488 .soclk(soclk)
7489);
7490
7491l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_ice_inst_c5
7492 (.din(decdp_pf_ice_inst_c4), .l1clk(l1clk),
7493 .scan_in(ff_decdp_pf_ice_inst_c5_scanin),
7494 .scan_out(ff_decdp_pf_ice_inst_c5_scanout),
7495 .dout(decdp_pf_ice_inst_c5),
7496 .siclk(siclk),
7497 .soclk(soclk)
7498);
7499
7500l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_ice_inst_c52
7501 (.din(decdp_pf_ice_inst_c5), .l1clk(l1clk),
7502 .scan_in(ff_decdp_pf_ice_inst_c52_scanin),
7503 .scan_out(ff_decdp_pf_ice_inst_c52_scanout),
7504 .dout(decdp_pf_ice_inst_c52),
7505 .siclk(siclk),
7506 .soclk(soclk)
7507);
7508
7509l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_ice_inst_c6
7510 (.din(decdp_pf_ice_inst_c52), .l1clk(l1clk),
7511 .scan_in(ff_decdp_pf_ice_inst_c6_scanin),
7512 .scan_out(ff_decdp_pf_ice_inst_c6_scanout),
7513 .dout(decdp_pf_ice_inst_c6),
7514 .siclk(siclk),
7515 .soclk(soclk)
7516);
7517
7518l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_pf_ice_inst_c7
7519 (.din(decdp_pf_ice_inst_c6), .l1clk(l1clk),
7520 .scan_in(ff_decdp_pf_ice_inst_c7_scanin),
7521 .scan_out(ff_decdp_pf_ice_inst_c7_scanout),
7522 .dout(arb_pf_ice_inst_c7),
7523 .siclk(siclk),
7524 .soclk(soclk)
7525);
7526
7527
7528///////////////////////////////////////////////////////
7529 // Streaming load indication to oqu in C6
7530 // Used in rqtyp logic
7531 // Note: This is an unqualled instruction and has to
7532 // be qualified with load hit to be accurate.
7533 ///////////////////////////////////////////////////////
7534
7535 assign arb_decdp_strld_inst_c6 =
7536 ( arbdec_arbdp_inst_rqtyp_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STRLOAD_RQ) ;
7537
7538///////////////////////////////////////////////////////
7539// BS and SR 11/12/03 N2 Xbar Packet format change
7540 // MMU load return indication to oqu in C6
7541 // Used in rqtyp logic
7542 // Note: This is an unqualled instruction and has to
7543 // be qualified with load hit to be accurate.
7544 ///////////////////////////////////////////////////////
7545
7546 assign arb_decdp_mmuld_inst_c6 =
7547( arbdec_arbdp_inst_rqtyp_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] == `MMU_RQ);
7548
7549 assign arb_decdp_atm_inst_c6 = ( arbdec_arbdp_inst_rqtyp_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] == `SWAP_RQ ) |
7550 ( arbdec_arbdp_inst_rqtyp_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] == `CAS1_RQ ) |
7551 ( arbdec_arbdp_inst_rqtyp_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] == `CAS2_RQ ) ;
7552
7553
7554 //////////////////////////////////////////////////////
7555 // The following expression is used for word enable generation in
7556 // tag.
7557 // A store is considered to be a DWORD store under the following
7558 // conditions:
7559 // 1) strm store or rdma wr8 with size=0
7560 // 2) cas2 from mb or a regular store with sz=3
7561 //////////////////////////////////////////////////////
7562
7563 assign dword_st_c1 = (( decdp_strst_inst_c1 | decdp_wr8_inst_c1 ) & // strm or siu WR8
7564 eight_byte_access_c1) | // strm store 8 byte access, BS and SR 11/12/03 N2 Xbar Packet format change
7565 (( decdp_st_inst_c1 | decdp_cas2_from_mb_c1 ) &
7566 eight_byte_access_c1) | // BS and SR 11/12/03 N2 Xbar Packet format change
7567 ( decdp_pst_inst_c1_internal & arbdec_arbdp_inst_ctrue_c1) ; // pst write is always a dword write.
7568
7569assign arb_arbdp_dword_st_c1 = dword_st_c1;
7570
7571 /////////////////////////////////////////////////////
7572 // INVAL instruction decode to arb
7573 // ~arbdp_inst_c1[`L2_EVICT] qualification is not necessary
7574 // as these instructions can only come from the IQ and not
7575 // from the Miss Buffer.
7576 /////////////////////////////////////////////////////
7577
7578
7579// assign decdp_ic_dc_inval_inst_c1 = decdp_dc_inval_c1 | decdp_ic_inval_c1;
7580 assign decdp_dc_inval_c1 = arbdec_arbdp_inst_bufidhi_c1 & ~arbdec_arbdp_inst_bufid1_c1 &
7581 // inv bit = 1, pf bit = 0
7582 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ ) &
7583 ~arbdec_arbdp_inst_rsvd_c1 ;
7584
7585 assign decdp_ic_inval_c1 = arbdec_arbdp_inst_bufidhi_c1 &
7586 ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `IMISS_RQ ) &
7587 ~arbdec_arbdp_inst_rsvd_c1 ;
7588
7589l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_dc_inval_c2
7590 (.din(decdp_dc_inval_c1), .l1clk(l1clk),
7591 .scan_in(ff_decdp_dc_inval_c2_scanin),
7592 .scan_out(ff_decdp_dc_inval_c2_scanout),
7593 .dout(decdp_dc_inval_c2),
7594 .siclk(siclk),
7595 .soclk(soclk)
7596);
7597
7598l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_ic_inval_c2
7599 (.din(decdp_ic_inval_c1), .l1clk(l1clk),
7600 .scan_in(ff_decdp_ic_inval_c2_scanin),
7601 .scan_out(ff_decdp_ic_inval_c2_scanout),
7602 .dout(decdp_ic_inval_c2),
7603 .siclk(siclk),
7604 .soclk(soclk)
7605);
7606
7607
7608 //////////////////////////////////////////////////////////////////////////
7609 // Stall logic.( logic is in l2t_arb but some of the
7610 // components are calculated here ).
7611 // The following instructions/events cause the C1 instruction in
7612 // the pipe to be stalled.
7613 // * evictions. (2 cycle stall )
7614 // * Fills. (2 cycle stall )
7615 // * Imiss. (1 cycle stall )
7616 // * tecc. (n cycle stall )
7617 // * diagnostic access. (data=2, tag=3, vuad=4)
7618 // * snoop access ( n cycle stall )
7619 // * SAme col stall
7620 //
7621 // The above multicycle stall conditions are detected in C1
7622 // and so is the same col stall. This is qualfied with
7623 // arb_unstalled_inst_c1.
7624 // WHen a multicycle instruction is in C2 or beyond, inst_vld_cn is
7625 // used for qualifying that instruction.
7626 /////////////////////////////////////////////////////////////////////////////
7627
7628 assign multi_cyc_op_c1 = arbdec_arbdp_evict_c1 | // eviction
7629 arbdec_arbdp_inst_fb_c1_qual | // fill instruction
7630 decdp_imiss_inst_c1 | // imiss
7631 decdp_ic_inval_c1 | // i$ invalidate
7632 decdp_dc_inval_c1 | // d$ invalidate
7633 arbdec_arbdp_tecc_c1 | // tecc instruction.
7634 arbdec_arbdp_inst_rsvd_c1 ; // siu instruction
7635
7636
7637
7638/////////////////////////////////////////////////////
7639//PST no ctrue is staged till C8 and then
7640//qualified with a hit signal to generate the
7641// write enable for mb_ctrue.
7642// The write enable generation is mbist_done in arb.
7643// the Ctrue logic is performed in misbuf.
7644//////////////////////////////////////////////////////
7645
7646l2t_arb_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c3
7647 (.din(arbdp_pst_no_ctrue_c2_1),
7648 .scan_in(ff_pst_no_ctrue_c3_scanin),
7649 .scan_out(ff_pst_no_ctrue_c3_scanout),
7650 .l1clk(l1clk), .dout(pst_no_ctrue_c3),
7651 .siclk(siclk),
7652 .soclk(soclk)
7653);
7654
7655l2t_arb_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c4
7656 (.din(pst_no_ctrue_c3),
7657 .scan_in(ff_pst_no_ctrue_c4_scanin),
7658 .scan_out(ff_pst_no_ctrue_c4_scanout),
7659 .l1clk(l1clk), .dout(pst_no_ctrue_c4),
7660 .siclk(siclk),
7661 .soclk(soclk)
7662);
7663
7664l2t_arb_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c5
7665 (.din(pst_no_ctrue_c4),
7666 .scan_in(ff_pst_no_ctrue_c5_scanin),
7667 .scan_out(ff_pst_no_ctrue_c5_scanout),
7668 .l1clk(l1clk), .dout(pst_no_ctrue_c5),
7669 .siclk(siclk),
7670 .soclk(soclk)
7671);
7672
7673// BS 03/11/04 extra cycle for mem access
7674
7675l2t_arb_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c52
7676 (.din(pst_no_ctrue_c5),
7677 .scan_in(ff_pst_no_ctrue_c52_scanin),
7678 .scan_out(ff_pst_no_ctrue_c52_scanout),
7679 .l1clk(l1clk), .dout(pst_no_ctrue_c52),
7680 .siclk(siclk),
7681 .soclk(soclk)
7682);
7683
7684
7685l2t_arb_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c6
7686 (.din(pst_no_ctrue_c52),
7687 .scan_in(ff_pst_no_ctrue_c6_scanin),
7688 .scan_out(ff_pst_no_ctrue_c6_scanout),
7689 .l1clk(l1clk), .dout(pst_no_ctrue_c6),
7690 .siclk(siclk),
7691 .soclk(soclk)
7692);
7693
7694l2t_arb_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c7
7695 (.din(pst_no_ctrue_c6),
7696 .scan_in(ff_pst_no_ctrue_c7_scanin),
7697 .scan_out(ff_pst_no_ctrue_c7_scanout),
7698 .l1clk(l1clk), .dout(pst_no_ctrue_c7),
7699 .siclk(siclk),
7700 .soclk(soclk)
7701);
7702
7703l2t_arb_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c8
7704 (.din(pst_no_ctrue_c7),
7705 .scan_in(ff_pst_no_ctrue_c8_scanin),
7706 .scan_out(ff_pst_no_ctrue_c8_scanout),
7707 .l1clk(l1clk), .dout(arbdp_pst_no_ctrue_c8),
7708 .siclk(siclk),
7709 .soclk(soclk)
7710);
7711
7712
7713/////////////////////////////////////////////////////
7714// CAs1 instruction
7715/////////////////////////////////////////////////////
7716
7717l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c3
7718 (.din(decdp_cas1_inst_c2_1),
7719 .scan_in(ff_decdp_cas1_inst_c3_scanin),
7720 .scan_out(ff_decdp_cas1_inst_c3_scanout),
7721 .l1clk(l1clk), .dout(decdp_cas1_inst_c3),
7722 .siclk(siclk),
7723 .soclk(soclk)
7724);
7725
7726l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c4
7727 (.din(decdp_cas1_inst_c3),
7728 .scan_in(ff_decdp_cas1_inst_c4_scanin),
7729 .scan_out(ff_decdp_cas1_inst_c4_scanout),
7730 .l1clk(l1clk), .dout(decdp_cas1_inst_c4),
7731 .siclk(siclk),
7732 .soclk(soclk)
7733);
7734
7735l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c5
7736 (.din(decdp_cas1_inst_c4),
7737 .scan_in(ff_decdp_cas1_inst_c5_scanin),
7738 .scan_out(ff_decdp_cas1_inst_c5_scanout),
7739 .l1clk(l1clk), .dout(decdp_cas1_inst_c5),
7740 .siclk(siclk),
7741 .soclk(soclk)
7742);
7743
7744// BS 03/11/04 extra cycle for mem access
7745
7746l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c52
7747 (.din(decdp_cas1_inst_c5),
7748 .scan_in(ff_decdp_cas1_inst_c52_scanin),
7749 .scan_out(ff_decdp_cas1_inst_c52_scanout),
7750 .l1clk(l1clk), .dout(decdp_cas1_inst_c52),
7751 .siclk(siclk),
7752 .soclk(soclk)
7753);
7754
7755
7756l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c6
7757 (.din(decdp_cas1_inst_c52),
7758 .scan_in(ff_decdp_cas1_inst_c6_scanin),
7759 .scan_out(ff_decdp_cas1_inst_c6_scanout),
7760 .l1clk(l1clk), .dout(decdp_cas1_inst_c6),
7761 .siclk(siclk),
7762 .soclk(soclk)
7763);
7764
7765l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c7
7766 (.din(decdp_cas1_inst_c6),
7767 .scan_in(ff_decdp_cas1_inst_c7_scanin),
7768 .scan_out(ff_decdp_cas1_inst_c7_scanout),
7769 .l1clk(l1clk), .dout(decdp_cas1_inst_c7),
7770 .siclk(siclk),
7771 .soclk(soclk)
7772);
7773
7774l2t_arb_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c8
7775 (.din(decdp_cas1_inst_c7),
7776 .scan_in(ff_decdp_cas1_inst_c8_scanin),
7777 .scan_out(ff_decdp_cas1_inst_c8_scanout),
7778 .l1clk(l1clk), .dout(decdp_cas1_inst_c8),
7779 .siclk(siclk),
7780 .soclk(soclk)
7781);
7782
7783
7784
7785///////////////////////////////////////////////////
7786// Special store logic. Used to generate byte masks for
7787// streaming stores and wr8s
7788///////////////////////////////////////////////////
7789
7790//msff_ctl_macro ff_decdp_strpst_inst_c2 (width=1)
7791// (.din(decdp_strpst_inst_c1),
7792// .scan_in(ff_decdp_strpst_inst_c2_scanin),
7793// .scan_out(ff_decdp_strpst_inst_c2_scanout),
7794// .l1clk(l1clk), .dout(decdp_strpst_inst_c2),
7795//);
7796//
7797//msff_ctl_macro ff_decdp_rdmapst_inst_c2 (width=1)
7798// (.din(decdp_rdmapst_inst_c1),
7799// .scan_in(ff_decdp_rdmapst_inst_c2_scanin),
7800// .scan_out(ff_decdp_rdmapst_inst_c2_scanout),
7801// .l1clk(l1clk), .dout(decdp_rdmapst_inst_c2),
7802//);
7803//
7804// assign sp_pst_inst_c2 = ( decdp_strpst_inst_c2 |
7805// decdp_rdmapst_inst_c2 ) ;
7806//
7807//msff_ctl_macro ff_sp_pst_inst_c3 (width=1)
7808// (.din(sp_pst_inst_c2),
7809// .scan_in(ff_sp_pst_inst_c3_scanin),
7810// .scan_out(ff_sp_pst_inst_c3_scanout),
7811// .l1clk(l1clk), .dout(sp_pst_inst_c3),
7812//);
7813//
7814//msff_ctl_macro ff_sp_pst_inst_c4 (width=1)
7815// (.din(sp_pst_inst_c3),
7816// .scan_in(ff_sp_pst_inst_c4_scanin),
7817// .scan_out(ff_sp_pst_inst_c4_scanout),
7818// .l1clk(l1clk), .dout(sp_pst_inst_c4),
7819//);
7820//
7821//msff_ctl_macro ff_sp_pst_inst_c5 (width=1)
7822// (.din(sp_pst_inst_c4),
7823// .scan_in(ff_sp_pst_inst_c5_scanin),
7824// .scan_out(ff_sp_pst_inst_c5_scanout),
7825// .l1clk(l1clk), .dout(sp_pst_inst_c5),
7826//);
7827//
7828//// BS 03/11/04 extra cycle for mem access
7829//
7830//msff_ctl_macro ff_sp_pst_inst_c52 (width=1)
7831// (.din(sp_pst_inst_c5),
7832// .scan_in(ff_sp_pst_inst_c52_scanin),
7833// .scan_out(ff_sp_pst_inst_c52_scanout),
7834// .l1clk(l1clk), .dout(sp_pst_inst_c52),
7835//);
7836//
7837//
7838//msff_ctl_macro ff_sp_pst_inst_c6 (width=1)
7839// (.din(sp_pst_inst_c52),
7840// .scan_in(ff_sp_pst_inst_c6_scanin),
7841// .scan_out(ff_sp_pst_inst_c6_scanout),
7842// .l1clk(l1clk), .dout(sp_pst_inst_c6),
7843//);
7844//
7845//msff_ctl_macro ff_sp_pst_inst_c7 (width=1)
7846// (.din(sp_pst_inst_c6),
7847// .scan_in(ff_sp_pst_inst_c7_scanin),
7848// .scan_out(ff_sp_pst_inst_c7_scanout),
7849// .l1clk(l1clk), .dout(sp_pst_inst_c7),
7850//);
7851
7852// BS 12/07/04 : taking out arb_swap_cas2_req_c2 to l2t_oqu_ctl.sv to disable ERROR
7853// Indication packet on a CE,UE, or Notdata on the store part of the swap or CAS2.
7854// Instead , regular store ack packet will get sent.
7855
7856assign arb_oqu_swap_cas2_req_c2 = ( arb_decdp_swap_inst_c2 | arb_decdp_cas2_inst_c2);
7857
7858
7859/////////////////////////////////////////////////////
7860// TECC instruction in C8 is used by the misbuf
7861// READY Logic. HEnce, this bit should not be looking
7862// at only the TECC bit of an instruction but also
7863// the fact that it got issued out of the MBF
7864//
7865// If an eviction packet has tecc_c3==1, the L2 ready bit
7866// is not set but EVICT_READY is set.
7867/////////////////////////////////////////////////////
7868
7869l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_evict_c2
7870 (.din(arbdec_arbdp_evict_c1),
7871 .scan_in(ff_arbdp_evict_c2_scanin),
7872 .scan_out(ff_arbdp_evict_c2_scanout),
7873 .l1clk(l1clk), .dout(arbdp_evict_c2),
7874 .siclk(siclk),
7875 .soclk(soclk)
7876);
7877
7878l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_evict_c3
7879 (.din(arbdp_evict_c2),
7880 .scan_in(ff_arbdp_evict_c3_scanin),
7881 .scan_out(ff_arbdp_evict_c3_scanout),
7882 .l1clk(l1clk), .dout(arbdp_evict_c3),
7883 .siclk(siclk),
7884 .soclk(soclk)
7885);
7886
7887assign arb_ic_evict_c3 = wr64_inst_c3 | arbdp_evict_c3; // Set force hit for directories
7888assign arb_dc_evict_c3 = arbdp_evict_c3 | wr64_inst_c3; // Set force hit for directories
7889
7890l2t_arb_ctl_msff_ctl_macro__width_2 ff_arbdp_evict_c4
7891 (
7892 .scan_in(ff_arbdp_evict_c4_scanin),
7893 .scan_out(ff_arbdp_evict_c4_scanout),
7894 .din({arb_dc_evict_c3,arb_ic_evict_c3}),
7895 .l1clk(l1clk),
7896 .dout({arb_ic_evict_c4,arb_dc_evict_c4}),
7897 .siclk(siclk),
7898 .soclk(soclk)
7899 );
7900
7901
7902
7903
7904assign arbdp_tecc_inst_mb_c3 = arbdec_arbdp_inst_tecc_c3 &
7905 arbdec_arbdp_inst_mb_c3 &
7906 ~arbdp_evict_c3 ;
7907
7908l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_tecc_inst_mb_c4
7909 (.din(arbdp_tecc_inst_mb_c3),
7910 .scan_in(ff_arbdp_tecc_inst_mb_c4_scanin),
7911 .scan_out(ff_arbdp_tecc_inst_mb_c4_scanout),
7912 .l1clk(l1clk), .dout(arbdp_tecc_inst_mb_c4),
7913 .siclk(siclk),
7914 .soclk(soclk)
7915);
7916
7917l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_tecc_inst_mb_c5
7918 (.din(arbdp_tecc_inst_mb_c4),
7919 .scan_in(ff_arbdp_tecc_inst_mb_c5_scanin),
7920 .scan_out(ff_arbdp_tecc_inst_mb_c5_scanout),
7921 .l1clk(l1clk), .dout(arbdp_tecc_inst_mb_c5),
7922 .siclk(siclk),
7923 .soclk(soclk)
7924);
7925
7926// BS 03/11/04 extra cycle for mem access
7927
7928l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_tecc_inst_mb_c52
7929 (.din(arbdp_tecc_inst_mb_c5),
7930 .scan_in(ff_arbdp_tecc_inst_mb_c52_scanin),
7931 .scan_out(ff_arbdp_tecc_inst_mb_c52_scanout),
7932 .l1clk(l1clk), .dout(arbdp_tecc_inst_mb_c52),
7933 .siclk(siclk),
7934 .soclk(soclk)
7935);
7936
7937
7938l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_tecc_inst_mb_c6
7939 (.din(arbdp_tecc_inst_mb_c52),
7940 .scan_in(ff_arbdp_tecc_inst_mb_c6_scanin),
7941 .scan_out(ff_arbdp_tecc_inst_mb_c6_scanout),
7942 .l1clk(l1clk), .dout(arbdp_tecc_inst_mb_c6),
7943 .siclk(siclk),
7944 .soclk(soclk)
7945);
7946
7947l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_tecc_inst_mb_c7
7948 (.din(arbdp_tecc_inst_mb_c6),
7949 .scan_in(ff_arbdp_tecc_inst_mb_c7_scanin),
7950 .scan_out(ff_arbdp_tecc_inst_mb_c7_scanout),
7951 .l1clk(l1clk), .dout(arbdp_tecc_inst_mb_c7),
7952 .siclk(siclk),
7953 .soclk(soclk)
7954);
7955
7956l2t_arb_ctl_msff_ctl_macro__width_1 ff_arbdp_tecc_inst_mb_c8
7957 (.din(arbdp_tecc_inst_mb_c7),
7958 .scan_in(ff_arbdp_tecc_inst_mb_c8_scanin),
7959 .scan_out(ff_arbdp_tecc_inst_mb_c8_scanout),
7960 .l1clk(l1clk), .dout(arb_arbdp_tecc_inst_mb_c8),
7961 .siclk(siclk),
7962 .soclk(soclk)
7963);
7964
7965
7966// fixscan start:
7967assign spares_scanin = scan_in ;
7968assign reset_flop_scanin = spares_scanout ;
7969assign ff_gate_off_prim_req_c1_scanin = reset_flop_scanout ;
7970assign ff_reset_for_pf_ice_staging_scanin = ff_gate_off_prim_req_c1_scanout;
7971assign ff_gate_off_prim_req_state_scanin = ff_reset_for_pf_ice_staging_scanout;
7972assign ff_l2_bypass_mode_on_d1_scanin = ff_gate_off_prim_req_state_scanout;
7973assign ff_mbf_valid_px2_scanin = ff_l2_bypass_mode_on_d1_scanout;
7974assign ff_mbf_valid_px2_1_scanin = ff_mbf_valid_px2_scanout ;
7975assign ff_fbf_valid_px2_1_scanin = ff_mbf_valid_px2_1_scanout;
7976assign ff_snp_valid_px2_scanin = ff_fbf_valid_px2_1_scanout;
7977assign ff_snp_valid_px2_1_scanin = ff_snp_valid_px2_scanout ;
7978assign ff_mux3_bufsel_px2_scanin = ff_snp_valid_px2_1_scanout;
7979assign ff_atm_instr_c1_scanin = ff_mux3_bufsel_px2_scanout;
7980assign ff_arb_stall_c1_cloned_scanin = ff_atm_instr_c1_scanout ;
7981assign ff_arb_inst_vld_c1_1_clone_scanin = ff_arb_stall_c1_cloned_scanout;
7982assign ff_data_ecc_active_c4_dup_scanin = ff_arb_inst_vld_c1_1_clone_scanout;
7983assign ff_inc_tag_ecc_cnt_c3_dup_scanin = ff_data_ecc_active_c4_dup_scanout;
7984assign ff_tecc_c2_scanin = ff_inc_tag_ecc_cnt_c3_dup_scanout;
7985assign ff_arb_tecc_c2_c3_scanin = ff_tecc_c2_scanout ;
7986assign ff_data_ecc_active_c4_scanin = ff_arb_tecc_c2_c3_scanout;
7987assign ff_bist_vuad_rd_en_px1_scanin = ff_data_ecc_active_c4_scanout;
7988assign ff_bist_enable_c1_scanin = ff_bist_vuad_rd_en_px1_scanout;
7989assign ff_bist_enable_c2_scanin = ff_bist_enable_c1_scanout;
7990assign ff_bist_acc_vd_px2_scanin = ff_bist_enable_c2_scanout;
7991assign ff_bist_acc_vd_c1_scanin = ff_bist_acc_vd_px2_scanout;
7992assign ff_bist_acc_vd_c2_scanin = ff_bist_acc_vd_c1_scanout;
7993assign ff_mbist_arb_l2d_en_d1_scanin = ff_bist_acc_vd_c2_scanout;
7994assign ff_arb_tag_acc_c1_scanin = ff_mbist_arb_l2d_en_d1_scanout;
7995assign ff_sp_tag_access_c1_scanin = ff_arb_tag_acc_c1_scanout;
7996assign ff_normal_tagacc_c2_scanin = ff_sp_tag_access_c1_scanout;
7997assign ff_l2t_mb2_run_r1_scanin = ff_normal_tagacc_c2_scanout;
7998assign ff_mbfull_px2_scanin = ff_l2t_mb2_run_r1_scanout;
7999assign ff_mbsel_c1_scanin = ff_mbfull_px2_scanout ;
8000assign ff_fbsel_c1_scanin = ff_mbsel_c1_scanout ;
8001assign ff_snpsel_c1_scanin = ff_fbsel_c1_scanout ;
8002assign ff_snpsel_c2_scanin = ff_snpsel_c1_scanout ;
8003assign ff_snpsel_c3_scanin = ff_snpsel_c2_scanout ;
8004assign ff_arb_evict_c3_scanin = ff_snpsel_c3_scanout ;
8005assign ff_arb_evict_c4_scanin = ff_arb_evict_c3_scanout ;
8006assign ff_arb_evict_c5_scanin = ff_arb_evict_c4_scanout ;
8007assign ff_imiss_inst_c3_scanin = ff_arb_evict_c5_scanout ;
8008assign ff_arb_imiss_hit_c4_scanin = ff_imiss_inst_c3_scanout ;
8009assign ff_arb_imiss_hit_c5_scanin = ff_arb_imiss_hit_c4_scanout;
8010assign ff_arb_imiss_hit_c52_scanin = ff_arb_imiss_hit_c5_scanout;
8011assign ff_arb_imiss_hit_c6_scanin = ff_arb_imiss_hit_c52_scanout;
8012assign ff_arb_imiss_hit_c7_scanin = ff_arb_imiss_hit_c6_scanout;
8013assign ff_arb_imiss_hit_c8_scanin = ff_arb_imiss_hit_c7_scanout;
8014assign ff_arb_imiss_hit_c9_scanin = ff_arb_imiss_hit_c8_scanout;
8015assign ff_arb_imiss_hit_c10_scanin = ff_arb_imiss_hit_c9_scanout;
8016assign ff_arb_inst_diag_c2_scanin = ff_arb_imiss_hit_c10_scanout;
8017assign ff_arb_inst_csr_c1_scanin = ff_arb_inst_diag_c2_scanout;
8018assign ff_arb_inst_l2data_c2_scanin = ff_arb_inst_csr_c1_scanout;
8019assign ff_inst_l2data_vld_c3_scanin = ff_arb_inst_l2data_c2_scanout;
8020assign ff_inst_l2data_vld_c4_scanin = ff_inst_l2data_vld_c3_scanout;
8021assign ff_inst_l2data_vld_c5_scanin = ff_inst_l2data_vld_c4_scanout;
8022assign ff_inst_l2data_vld_c52_scanin = ff_inst_l2data_vld_c5_scanout;
8023assign ff_inst_l2data_vld_c6_scanin = ff_inst_l2data_vld_c52_scanout;
8024assign ff_arb_csr_wr_en_c3_scanin = ff_inst_l2data_vld_c6_scanout;
8025assign ff_arb_csr_wr_en_c3_1_scanin = ff_arb_csr_wr_en_c3_scanout;
8026assign ff_arb_csr_wr_en_c4_scanin = ff_arb_csr_wr_en_c3_1_scanout;
8027assign ff_arb_csr_wr_en_c5_scanin = ff_arb_csr_wr_en_c4_scanout;
8028assign ff_arb_csr_wr_en_c52_scanin = ff_arb_csr_wr_en_c5_scanout;
8029assign ff_arb_csr_wr_en_c6_scanin = ff_arb_csr_wr_en_c52_scanout;
8030assign ff_arb_csr_wr_en_c7_scanin = ff_arb_csr_wr_en_c6_scanout;
8031assign ff_arb_csr_wr_en_c8_scanin = ff_arb_csr_wr_en_c7_scanout;
8032assign ff_arb_csr_rd_en_c3_scanin = ff_arb_csr_wr_en_c8_scanout;
8033assign ff_arb_csr_rd_en_c4_scanin = ff_arb_csr_rd_en_c3_scanout;
8034assign ff_arb_csr_rd_en_c5_scanin = ff_arb_csr_rd_en_c4_scanout;
8035assign ff_arb_csr_rd_en_c52_scanin = ff_arb_csr_rd_en_c5_scanout;
8036assign ff_arb_csr_rd_en_c6_scanin = ff_arb_csr_rd_en_c52_scanout;
8037assign ff_arb_csr_rd_en_c7_scanin = ff_arb_csr_rd_en_c6_scanout;
8038assign ff_arb_inst_l2tag_c2_scanin = ff_arb_csr_rd_en_c7_scanout;
8039assign ff_arb_inst_l2tag_c2_1_scanin = ff_arb_inst_l2tag_c2_scanout;
8040assign ff_inst_l2tag_vld_c3_scanin = ff_arb_inst_l2tag_c2_1_scanout;
8041assign ff_inst_l2tag_vld_c4_scanin = ff_inst_l2tag_vld_c3_scanout;
8042assign ff_inst_l2tag_vld_c5_scanin = ff_inst_l2tag_vld_c4_scanout;
8043assign ff_inst_l2tag_vld_c52_scanin = ff_inst_l2tag_vld_c5_scanout;
8044assign ff_inst_l2tag_vld_c6_scanin = ff_inst_l2tag_vld_c52_scanout;
8045assign ff_arb_inst_l2vuad_c2_scanin = ff_inst_l2tag_vld_c6_scanout;
8046assign ff_inst_l2vuad_vld_c3_scanin = ff_arb_inst_l2vuad_c2_scanout;
8047assign ff_inst_l2vuad_vld_c4_scanin = ff_inst_l2vuad_vld_c3_scanout;
8048assign ff_inst_l2vuad_vld_c5_scanin = ff_inst_l2vuad_vld_c4_scanout;
8049assign ff_inst_l2vuad_vld_c52_scanin = ff_inst_l2vuad_vld_c5_scanout;
8050assign ff_inst_l2vuad_vld_c6_scanin = ff_inst_l2vuad_vld_c52_scanout;
8051assign ff_deccck_data_sel_c9_scanin = ff_inst_l2vuad_vld_c6_scanout;
8052assign ff_lower_cas_c9_scanin = ff_deccck_data_sel_c9_scanout;
8053assign ff_upper_cas_c9_scanin = ff_lower_cas_c9_scanout ;
8054assign ff_word_lower_cmp_c9_scanin = ff_upper_cas_c9_scanout ;
8055assign ff_word_upper_cmp_c9_scanin = ff_word_lower_cmp_c9_scanout;
8056assign ff_tecc_inst_c2_scanin = ff_word_upper_cmp_c9_scanout;
8057assign ff_inc_tag_ecc_cnt_c3_scanin = ff_tecc_inst_c2_scanout ;
8058assign ff_tag_ecc_fsm_count_scanin = ff_inc_tag_ecc_cnt_c3_scanout;
8059assign ff_scrub_fsm_count_eq_6_px2_scanin = ff_tag_ecc_fsm_count_scanout;
8060assign ff_scrub_fsm_count_eq_1_px2_scanin = ff_scrub_fsm_count_eq_6_px2_scanout;
8061assign ff_tecc_tag_acc_en_px2_scanin = ff_scrub_fsm_count_eq_1_px2_scanout;
8062assign ff_arb_tagd_tecc_c2_scanin = ff_tecc_tag_acc_en_px2_scanout;
8063assign ff_diag_or_tecc_acc_c1_scanin = ff_arb_tagd_tecc_c2_scanout;
8064assign ff_hit_l2orfb_c4_scanin = ff_diag_or_tecc_acc_c1_scanout;
8065assign ff_hit_l2orfb_c5_scanin = ff_hit_l2orfb_c4_scanout ;
8066assign ff_hit_l2orfb_c52_scanin = ff_hit_l2orfb_c5_scanout ;
8067assign ff_hit_l2orfb_c6_scanin = ff_hit_l2orfb_c52_scanout;
8068assign ff_hit_l2orfb_c7_scanin = ff_hit_l2orfb_c6_scanout ;
8069assign ff_hit_l2orfb_c8_scanin = ff_hit_l2orfb_c7_scanout ;
8070assign ff_dword_mask_c8_scanin = ff_hit_l2orfb_c8_scanout ;
8071assign ff_fbrd_c3_scanin = ff_dword_mask_c8_scanout ;
8072assign ff_st_cam_en_c3_scanin = ff_fbrd_c3_scanout ;
8073assign ff_sp_cam_en_c3_scanin = ff_st_cam_en_c3_scanout ;
8074assign ff_arb_decdp_cas1_inst_c3_scanin = ff_sp_cam_en_c3_scanout ;
8075assign ff_enc_cam_addr_c4_scanin = ff_arb_decdp_cas1_inst_c3_scanout;
8076assign ff_vuad_ce_scanin = ff_enc_cam_addr_c4_scanout;
8077assign ff_vuad_ce_err_c3_scanin = ff_vuad_ce_scanout ;
8078assign ff_arbctl_inst_nc_c2_scanin = ff_vuad_ce_err_c3_scanout;
8079assign ff_ic_hitqual_cam_en_c3_scanin = ff_arbctl_inst_nc_c2_scanout;
8080assign ff_ld_inst_c3_scanin = ff_ic_hitqual_cam_en_c3_scanout;
8081assign ff_dc_inval_c3_scanin = ff_ld_inst_c3_scanout ;
8082assign ff_ic_inval_c3_scanin = ff_dc_inval_c3_scanout ;
8083assign ff_dc_inval_vld_c4_scanin = ff_ic_inval_c3_scanout ;
8084assign ff_dc_inval_vld_c5_scanin = ff_dc_inval_vld_c4_scanout;
8085assign ff_dc_inval_vld_c52_scanin = ff_dc_inval_vld_c5_scanout;
8086assign ff_dc_inval_vld_c6_scanin = ff_dc_inval_vld_c52_scanout;
8087assign ff_dc_inval_vld_c7_scanin = ff_dc_inval_vld_c6_scanout;
8088assign ff_ic_inval_vld_c4_scanin = ff_dc_inval_vld_c7_scanout;
8089assign ff_ic_inval_vld_c5_scanin = ff_ic_inval_vld_c4_scanout;
8090assign ff_ic_inval_vld_c52_scanin = ff_ic_inval_vld_c5_scanout;
8091assign ff_ic_inval_vld_c6_scanin = ff_ic_inval_vld_c52_scanout;
8092assign ff_ic_inval_vld_c7_scanin = ff_ic_inval_vld_c6_scanout;
8093assign ff_ic_inval_vld_c8_scanin = ff_ic_inval_vld_c7_scanout;
8094assign ff_ic_inval_vld_c9_scanin = ff_ic_inval_vld_c8_scanout;
8095assign ff_arb_dir_wr_en_c4_scanin = ff_ic_inval_vld_c9_scanout;
8096assign ff_dir_addr_cnt_scanin = ff_arb_dir_wr_en_c4_scanout;
8097assign ff_dir_addr_cnt_c4_scanin = ff_dir_addr_cnt_scanout ;
8098assign ff_dir_addr_cnt_c5_scanin = ff_dir_addr_cnt_c4_scanout;
8099assign ff_dir_addr_cnt_c52_scanin = ff_dir_addr_cnt_c5_scanout;
8100assign ff_dir_addr_cnt_c6_scanin = ff_dir_addr_cnt_c52_scanout;
8101assign ff_dir_addr_cnt_c7_scanin = ff_dir_addr_cnt_c6_scanout;
8102assign ff_dir_addr_c8_scanin = ff_dir_addr_cnt_c7_scanout;
8103assign ff_dir_addr_c9_scanin = ff_dir_addr_c8_scanout ;
8104assign ff_sync_en_scanin = ff_dir_addr_c9_scanout ;
8105assign ff_ncu_signals_scanin = ff_sync_en_scanout ;
8106assign ff_staged_part_bank_scanin = ff_ncu_signals_scanout ;
8107assign ff_arb_cpuid_c3_scanin = ff_staged_part_bank_scanout;
8108assign ff_arb_cpuid_c4_scanin = ff_arb_cpuid_c3_scanout ;
8109assign ff_arb_cpuid_c5_scanin = ff_arb_cpuid_c4_scanout ;
8110assign ff_arb_cpuid_c52_scanin = ff_arb_cpuid_c5_scanout ;
8111assign ff_arb_ic_dir_wrentry_c4_scanin = ff_arb_cpuid_c52_scanout ;
8112assign ff_arb_ic_dir_wrentry_c5_scanin = ff_arb_ic_dir_wrentry_c4_scanout;
8113assign ff_arb_ic_dir_wrentry_c6_scanin = ff_arb_ic_dir_wrentry_c5_scanout;
8114assign ff_arb_ic_dir_wrentry_c7_scanin = ff_arb_ic_dir_wrentry_c6_scanout;
8115assign ff_dc_wr_panel_c4_scanin = ff_arb_ic_dir_wrentry_c7_scanout;
8116assign ff_dc_wr_panel_c5_scanin = ff_dc_wr_panel_c4_scanout;
8117assign ff_dc_wr_panel_c52_scanin = ff_dc_wr_panel_c5_scanout;
8118assign ff_arbdec_arbdp_inst_bufidlo_c3_scanin = ff_dc_wr_panel_c52_scanout;
8119assign ff_ic_wr_panel_c4_scanin = ff_arbdec_arbdp_inst_bufidlo_c3_scanout;
8120assign ff_ic_wr_panel_c5_scanin = ff_ic_wr_panel_c4_scanout;
8121assign ff_ic_wr_panel_c52_scanin = ff_ic_wr_panel_c5_scanout;
8122assign ff_ic_wr_panel_c6_scanin = ff_ic_wr_panel_c52_scanout;
8123assign ff_ic_wr_panel_c7_scanin = ff_ic_wr_panel_c6_scanout;
8124assign ff_ic_wr_panel_c8_scanin = ff_ic_wr_panel_c7_scanout;
8125assign ff_ic_wr_panel_c9_scanin = ff_ic_wr_panel_c8_scanout;
8126assign ff_wr64_inst_c3_scanin = ff_ic_wr_panel_c9_scanout;
8127assign ff_waysel_gate_c2_scanin = ff_wr64_inst_c3_scanout ;
8128assign ff_parerr_gate_c1_scanin = ff_waysel_gate_c2_scanout;
8129assign ff_arb_stall_c1_scanin = ff_parerr_gate_c1_scanout;
8130assign ff_arb_inst_vld_c1_scanin = ff_arb_stall_c1_scanout ;
8131assign ff_mbist_lookup_r1_scanin = ff_arb_inst_vld_c1_scanout;
8132assign ff_arb_inst_vld_c1_1_scanin = ff_mbist_lookup_r1_scanout;
8133assign ff_arb_inst_vld_c2_scanin = ff_arb_inst_vld_c1_1_scanout;
8134assign ff_arb_inst_vld_c2_1_scanin = ff_arb_inst_vld_c2_scanout;
8135assign ff_arb_inst_vld_c2_2_scanin = ff_arb_inst_vld_c2_1_scanout;
8136assign ff_arb_inst_vld_c2_3_scanin = ff_arb_inst_vld_c2_2_scanout;
8137assign ff_arb_inst_vld_c2_4_scanin = ff_arb_inst_vld_c2_3_scanout;
8138assign ff_arb_inst_vld_c2_5_scanin = ff_arb_inst_vld_c2_4_scanout;
8139assign ff_arb_inst_vld_c2_6_scanin = ff_arb_inst_vld_c2_5_scanout;
8140assign ff_arb_inst_vld_c2_7_scanin = ff_arb_inst_vld_c2_6_scanout;
8141assign ff_arb_inst_vld_c2_8_scanin = ff_arb_inst_vld_c2_7_scanout;
8142assign ff_arb_inst_vld_c2_10_scanin = ff_arb_inst_vld_c2_8_scanout;
8143assign ff_arb_inst_vld_c3_scanin = ff_arb_inst_vld_c2_10_scanout;
8144assign ff_arb_inst_vld_c3_1_scanin = ff_arb_inst_vld_c3_scanout;
8145assign ff_arb_inst_vld_c3_2_scanin = ff_arb_inst_vld_c3_1_scanout;
8146assign ff_dec_evict_c2_scanin = ff_arb_inst_vld_c3_2_scanout;
8147assign ff_dec_evict_tecc_c2_scanin = ff_dec_evict_c2_scanout ;
8148assign ff_decdp_st_inst_c2_scanin = ff_dec_evict_tecc_c2_scanout;
8149assign ff_decdp_st_inst_c2_1_scanin = ff_decdp_st_inst_c2_scanout;
8150assign ff_decdp_st_inst_c3_scanin = ff_decdp_st_inst_c2_1_scanout;
8151assign ff_decdp_st_inst_c3_1_scanin = ff_decdp_st_inst_c3_scanout;
8152assign ff_decdp_st_inst_c3_2_scanin = ff_decdp_st_inst_c3_1_scanout;
8153assign ff_arbdp_inst_bufid1_c2_scanin = ff_decdp_st_inst_c3_2_scanout;
8154assign ff_decdp_bis_inst_c2_scanin = ff_arbdp_inst_bufid1_c2_scanout;
8155assign ff_decdp_rmo_st_c3_scanin = ff_decdp_bis_inst_c2_scanout;
8156assign ff_decdp_rmo_or_strst_c3_scanin = ff_decdp_rmo_st_c3_scanout;
8157assign ff_decdp_strst_inst_c2_scanin = ff_decdp_rmo_or_strst_c3_scanout;
8158assign ff_decdp_strst_inst_c2_1_scanin = ff_decdp_strst_inst_c2_scanout;
8159assign ff_decdp_wr8_inst_c2_scanin = ff_decdp_strst_inst_c2_1_scanout;
8160assign ff_decdp_wr64_inst_c2_scanin = ff_decdp_wr8_inst_c2_scanout;
8161assign ff_decdp_wr64_inst_c2_1_scanin = ff_decdp_wr64_inst_c2_scanout;
8162assign ff_arb_decdp_ld64_inst_c1_scanin = ff_decdp_wr64_inst_c2_1_scanout;
8163assign ff_decdp_inst_int_c2_scanin = ff_arb_decdp_ld64_inst_c1_scanout;
8164assign ff_decdp_pst_inst_c2_scanin = ff_decdp_inst_int_c2_scanout;
8165assign ff_decdp_pst_inst_c3_scanin = ff_decdp_pst_inst_c2_scanout;
8166assign ff_decdp_pst_inst_c4_scanin = ff_decdp_pst_inst_c3_scanout;
8167assign ff_decdp_pst_inst_c5_scanin = ff_decdp_pst_inst_c4_scanout;
8168assign ff_decdp_pst_inst_c52_scanin = ff_decdp_pst_inst_c5_scanout;
8169assign ff_decdp_pst_inst_c6_scanin = ff_decdp_pst_inst_c52_scanout;
8170assign ff_decdp_pst_inst_c7_scanin = ff_decdp_pst_inst_c6_scanout;
8171assign ff_st_no_ctrue_c1_scanin = ff_decdp_pst_inst_c7_scanout;
8172assign ff_arbdp_pst_no_ctrue_c2_1_scanin = ff_st_no_ctrue_c1_scanout;
8173assign ff_arbdp_pst_with_ctrue_c2_scanin = ff_arbdp_pst_no_ctrue_c2_1_scanout;
8174assign ff_arbdp_tag_pst_no_ctrue_c2_scanin = ff_arbdp_pst_with_ctrue_c2_scanout;
8175assign ff_arbdp_misbuf_pst_no_ctrue_c2_scanin = ff_arbdp_tag_pst_no_ctrue_c2_scanout;
8176assign ff_arbdp_vuadctl_pst_no_ctrue_c2_scanin = ff_arbdp_misbuf_pst_no_ctrue_c2_scanout;
8177assign ff_decdp_cas1_inst_c2_scanin = ff_arbdp_vuadctl_pst_no_ctrue_c2_scanout;
8178assign ff_decdp_cas1_inst_c2_1_scanin = ff_decdp_cas1_inst_c2_scanout;
8179assign ff_decdp_cas2_inst_c2_scanin = ff_decdp_cas1_inst_c2_1_scanout;
8180assign ff_decdp_cas2_from_mb_c2_scanin = ff_decdp_cas2_inst_c2_scanout;
8181assign ff_decdp_cas2_from_mb_ctrue_c2_scanin = ff_decdp_cas2_from_mb_c2_scanout;
8182assign ff_store_err_c3_scanin = ff_decdp_cas2_from_mb_ctrue_c2_scanout;
8183assign ff_store_err_c4_scanin = ff_store_err_c3_scanout ;
8184assign ff_store_err_c5_scanin = ff_store_err_c4_scanout ;
8185assign ff_store_err_c52_scanin = ff_store_err_c5_scanout ;
8186assign ff_store_err_c6_scanin = ff_store_err_c52_scanout ;
8187assign ff_store_err_c7_scanin = ff_store_err_c6_scanout ;
8188assign ff_store_err_c8_scanin = ff_store_err_c7_scanout ;
8189assign ff_decdp_fwd_req_c2_scanin = ff_store_err_c8_scanout ;
8190assign ff_decdp_swap_inst_c2_scanin = ff_decdp_fwd_req_c2_scanout;
8191assign ff_decdp_imiss_inst_c2_scanin = ff_decdp_swap_inst_c2_scanout;
8192assign ff_decdp_camld_inst_c2_scanin = ff_decdp_imiss_inst_c2_scanout;
8193assign ff_decdp_ld_inst_c2_scanin = ff_decdp_camld_inst_c2_scanout;
8194assign ff_decdp_pf_inst_c2_scanin = ff_decdp_ld_inst_c2_scanout;
8195assign ff_decdp_pf_inst_c3_scanin = ff_decdp_pf_inst_c2_scanout;
8196assign ff_decdp_pf_inst_c4_scanin = ff_decdp_pf_inst_c3_scanout;
8197assign ff_decdp_pf_inst_c5_scanin = ff_decdp_pf_inst_c4_scanout;
8198assign ff_decdp_pf_ice_inst_c2_scanin = ff_decdp_pf_inst_c5_scanout;
8199assign ff_decdp_pf_ice_inst_c3_scanin = ff_decdp_pf_ice_inst_c2_scanout;
8200assign ff_decdp_pf_ice_inst_c4_scanin = ff_decdp_pf_ice_inst_c3_scanout;
8201assign ff_decdp_pf_ice_inst_c5_scanin = ff_decdp_pf_ice_inst_c4_scanout;
8202assign ff_decdp_pf_ice_inst_c52_scanin = ff_decdp_pf_ice_inst_c5_scanout;
8203assign ff_decdp_pf_ice_inst_c6_scanin = ff_decdp_pf_ice_inst_c52_scanout;
8204assign ff_decdp_pf_ice_inst_c7_scanin = ff_decdp_pf_ice_inst_c6_scanout;
8205assign ff_decdp_dc_inval_c2_scanin = ff_decdp_pf_ice_inst_c7_scanout;
8206assign ff_decdp_ic_inval_c2_scanin = ff_decdp_dc_inval_c2_scanout;
8207assign ff_pst_no_ctrue_c3_scanin = ff_decdp_ic_inval_c2_scanout;
8208assign ff_pst_no_ctrue_c4_scanin = ff_pst_no_ctrue_c3_scanout;
8209assign ff_pst_no_ctrue_c5_scanin = ff_pst_no_ctrue_c4_scanout;
8210assign ff_pst_no_ctrue_c52_scanin = ff_pst_no_ctrue_c5_scanout;
8211assign ff_pst_no_ctrue_c6_scanin = ff_pst_no_ctrue_c52_scanout;
8212assign ff_pst_no_ctrue_c7_scanin = ff_pst_no_ctrue_c6_scanout;
8213assign ff_pst_no_ctrue_c8_scanin = ff_pst_no_ctrue_c7_scanout;
8214assign ff_decdp_cas1_inst_c3_scanin = ff_pst_no_ctrue_c8_scanout;
8215assign ff_decdp_cas1_inst_c4_scanin = ff_decdp_cas1_inst_c3_scanout;
8216assign ff_decdp_cas1_inst_c5_scanin = ff_decdp_cas1_inst_c4_scanout;
8217assign ff_decdp_cas1_inst_c52_scanin = ff_decdp_cas1_inst_c5_scanout;
8218assign ff_decdp_cas1_inst_c6_scanin = ff_decdp_cas1_inst_c52_scanout;
8219assign ff_decdp_cas1_inst_c7_scanin = ff_decdp_cas1_inst_c6_scanout;
8220assign ff_decdp_cas1_inst_c8_scanin = ff_decdp_cas1_inst_c7_scanout;
8221assign ff_arbdp_evict_c2_scanin = ff_decdp_cas1_inst_c8_scanout;
8222assign ff_arbdp_evict_c3_scanin = ff_arbdp_evict_c2_scanout;
8223assign ff_arbdp_evict_c4_scanin = ff_arbdp_evict_c3_scanout;
8224assign ff_arbdp_tecc_inst_mb_c4_scanin = ff_arbdp_evict_c4_scanout;
8225assign ff_arbdp_tecc_inst_mb_c5_scanin = ff_arbdp_tecc_inst_mb_c4_scanout;
8226assign ff_arbdp_tecc_inst_mb_c52_scanin = ff_arbdp_tecc_inst_mb_c5_scanout;
8227assign ff_arbdp_tecc_inst_mb_c6_scanin = ff_arbdp_tecc_inst_mb_c52_scanout;
8228assign ff_arbdp_tecc_inst_mb_c7_scanin = ff_arbdp_tecc_inst_mb_c6_scanout;
8229assign ff_arbdp_tecc_inst_mb_c8_scanin = ff_arbdp_tecc_inst_mb_c7_scanout;
8230assign scan_out = ff_arbdp_tecc_inst_mb_c8_scanout;
8231// fixscan end:
8232endmodule
8233
8234
8235// Description: Spare gate macro for control blocks
8236//
8237// Param num controls the number of times the macro is added
8238// flops=0 can be used to use only combination spare logic
8239
8240
8241module l2t_arb_ctl_spare_ctl_macro__num_4 (
8242 l1clk,
8243 scan_in,
8244 siclk,
8245 soclk,
8246 scan_out);
8247wire si_0;
8248wire so_0;
8249wire spare0_flop_unused;
8250wire spare0_buf_32x_unused;
8251wire spare0_nand3_8x_unused;
8252wire spare0_inv_8x_unused;
8253wire spare0_aoi22_4x_unused;
8254wire spare0_buf_8x_unused;
8255wire spare0_oai22_4x_unused;
8256wire spare0_inv_16x_unused;
8257wire spare0_nand2_16x_unused;
8258wire spare0_nor3_4x_unused;
8259wire spare0_nand2_8x_unused;
8260wire spare0_buf_16x_unused;
8261wire spare0_nor2_16x_unused;
8262wire spare0_inv_32x_unused;
8263wire si_1;
8264wire so_1;
8265wire spare1_flop_unused;
8266wire spare1_buf_32x_unused;
8267wire spare1_nand3_8x_unused;
8268wire spare1_inv_8x_unused;
8269wire spare1_aoi22_4x_unused;
8270wire spare1_buf_8x_unused;
8271wire spare1_oai22_4x_unused;
8272wire spare1_inv_16x_unused;
8273wire spare1_nand2_16x_unused;
8274wire spare1_nor3_4x_unused;
8275wire spare1_nand2_8x_unused;
8276wire spare1_buf_16x_unused;
8277wire spare1_nor2_16x_unused;
8278wire spare1_inv_32x_unused;
8279wire si_2;
8280wire so_2;
8281wire spare2_flop_unused;
8282wire spare2_buf_32x_unused;
8283wire spare2_nand3_8x_unused;
8284wire spare2_inv_8x_unused;
8285wire spare2_aoi22_4x_unused;
8286wire spare2_buf_8x_unused;
8287wire spare2_oai22_4x_unused;
8288wire spare2_inv_16x_unused;
8289wire spare2_nand2_16x_unused;
8290wire spare2_nor3_4x_unused;
8291wire spare2_nand2_8x_unused;
8292wire spare2_buf_16x_unused;
8293wire spare2_nor2_16x_unused;
8294wire spare2_inv_32x_unused;
8295wire si_3;
8296wire so_3;
8297wire spare3_flop_unused;
8298wire spare3_buf_32x_unused;
8299wire spare3_nand3_8x_unused;
8300wire spare3_inv_8x_unused;
8301wire spare3_aoi22_4x_unused;
8302wire spare3_buf_8x_unused;
8303wire spare3_oai22_4x_unused;
8304wire spare3_inv_16x_unused;
8305wire spare3_nand2_16x_unused;
8306wire spare3_nor3_4x_unused;
8307wire spare3_nand2_8x_unused;
8308wire spare3_buf_16x_unused;
8309wire spare3_nor2_16x_unused;
8310wire spare3_inv_32x_unused;
8311
8312
8313input l1clk;
8314input scan_in;
8315input siclk;
8316input soclk;
8317output scan_out;
8318
8319cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
8320 .siclk(siclk),
8321 .soclk(soclk),
8322 .si(si_0),
8323 .so(so_0),
8324 .d(1'b0),
8325 .q(spare0_flop_unused));
8326assign si_0 = scan_in;
8327
8328cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
8329 .out(spare0_buf_32x_unused));
8330cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
8331 .in1(1'b1),
8332 .in2(1'b1),
8333 .out(spare0_nand3_8x_unused));
8334cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
8335 .out(spare0_inv_8x_unused));
8336cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
8337 .in01(1'b1),
8338 .in10(1'b1),
8339 .in11(1'b1),
8340 .out(spare0_aoi22_4x_unused));
8341cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
8342 .out(spare0_buf_8x_unused));
8343cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
8344 .in01(1'b1),
8345 .in10(1'b1),
8346 .in11(1'b1),
8347 .out(spare0_oai22_4x_unused));
8348cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
8349 .out(spare0_inv_16x_unused));
8350cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
8351 .in1(1'b1),
8352 .out(spare0_nand2_16x_unused));
8353cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
8354 .in1(1'b0),
8355 .in2(1'b0),
8356 .out(spare0_nor3_4x_unused));
8357cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
8358 .in1(1'b1),
8359 .out(spare0_nand2_8x_unused));
8360cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
8361 .out(spare0_buf_16x_unused));
8362cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
8363 .in1(1'b0),
8364 .out(spare0_nor2_16x_unused));
8365cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
8366 .out(spare0_inv_32x_unused));
8367
8368cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
8369 .siclk(siclk),
8370 .soclk(soclk),
8371 .si(si_1),
8372 .so(so_1),
8373 .d(1'b0),
8374 .q(spare1_flop_unused));
8375assign si_1 = so_0;
8376
8377cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
8378 .out(spare1_buf_32x_unused));
8379cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
8380 .in1(1'b1),
8381 .in2(1'b1),
8382 .out(spare1_nand3_8x_unused));
8383cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
8384 .out(spare1_inv_8x_unused));
8385cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
8386 .in01(1'b1),
8387 .in10(1'b1),
8388 .in11(1'b1),
8389 .out(spare1_aoi22_4x_unused));
8390cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
8391 .out(spare1_buf_8x_unused));
8392cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
8393 .in01(1'b1),
8394 .in10(1'b1),
8395 .in11(1'b1),
8396 .out(spare1_oai22_4x_unused));
8397cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
8398 .out(spare1_inv_16x_unused));
8399cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
8400 .in1(1'b1),
8401 .out(spare1_nand2_16x_unused));
8402cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
8403 .in1(1'b0),
8404 .in2(1'b0),
8405 .out(spare1_nor3_4x_unused));
8406cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
8407 .in1(1'b1),
8408 .out(spare1_nand2_8x_unused));
8409cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
8410 .out(spare1_buf_16x_unused));
8411cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
8412 .in1(1'b0),
8413 .out(spare1_nor2_16x_unused));
8414cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
8415 .out(spare1_inv_32x_unused));
8416
8417cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
8418 .siclk(siclk),
8419 .soclk(soclk),
8420 .si(si_2),
8421 .so(so_2),
8422 .d(1'b0),
8423 .q(spare2_flop_unused));
8424assign si_2 = so_1;
8425
8426cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
8427 .out(spare2_buf_32x_unused));
8428cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
8429 .in1(1'b1),
8430 .in2(1'b1),
8431 .out(spare2_nand3_8x_unused));
8432cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
8433 .out(spare2_inv_8x_unused));
8434cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
8435 .in01(1'b1),
8436 .in10(1'b1),
8437 .in11(1'b1),
8438 .out(spare2_aoi22_4x_unused));
8439cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
8440 .out(spare2_buf_8x_unused));
8441cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
8442 .in01(1'b1),
8443 .in10(1'b1),
8444 .in11(1'b1),
8445 .out(spare2_oai22_4x_unused));
8446cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
8447 .out(spare2_inv_16x_unused));
8448cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
8449 .in1(1'b1),
8450 .out(spare2_nand2_16x_unused));
8451cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
8452 .in1(1'b0),
8453 .in2(1'b0),
8454 .out(spare2_nor3_4x_unused));
8455cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
8456 .in1(1'b1),
8457 .out(spare2_nand2_8x_unused));
8458cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
8459 .out(spare2_buf_16x_unused));
8460cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
8461 .in1(1'b0),
8462 .out(spare2_nor2_16x_unused));
8463cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
8464 .out(spare2_inv_32x_unused));
8465
8466cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
8467 .siclk(siclk),
8468 .soclk(soclk),
8469 .si(si_3),
8470 .so(so_3),
8471 .d(1'b0),
8472 .q(spare3_flop_unused));
8473assign si_3 = so_2;
8474
8475cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
8476 .out(spare3_buf_32x_unused));
8477cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
8478 .in1(1'b1),
8479 .in2(1'b1),
8480 .out(spare3_nand3_8x_unused));
8481cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
8482 .out(spare3_inv_8x_unused));
8483cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
8484 .in01(1'b1),
8485 .in10(1'b1),
8486 .in11(1'b1),
8487 .out(spare3_aoi22_4x_unused));
8488cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
8489 .out(spare3_buf_8x_unused));
8490cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
8491 .in01(1'b1),
8492 .in10(1'b1),
8493 .in11(1'b1),
8494 .out(spare3_oai22_4x_unused));
8495cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
8496 .out(spare3_inv_16x_unused));
8497cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
8498 .in1(1'b1),
8499 .out(spare3_nand2_16x_unused));
8500cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
8501 .in1(1'b0),
8502 .in2(1'b0),
8503 .out(spare3_nor3_4x_unused));
8504cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
8505 .in1(1'b1),
8506 .out(spare3_nand2_8x_unused));
8507cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
8508 .out(spare3_buf_16x_unused));
8509cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
8510 .in1(1'b0),
8511 .out(spare3_nor2_16x_unused));
8512cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
8513 .out(spare3_inv_32x_unused));
8514assign scan_out = so_3;
8515
8516
8517
8518endmodule
8519
8520
8521
8522
8523
8524
8525// any PARAMS parms go into naming of macro
8526
8527module l2t_arb_ctl_l1clkhdr_ctl_macro (
8528 l2clk,
8529 l1en,
8530 pce_ov,
8531 stop,
8532 se,
8533 l1clk);
8534
8535
8536 input l2clk;
8537 input l1en;
8538 input pce_ov;
8539 input stop;
8540 input se;
8541 output l1clk;
8542
8543
8544
8545
8546
8547cl_sc1_l1hdr_8x c_0 (
8548
8549
8550 .l2clk(l2clk),
8551 .pce(l1en),
8552 .l1clk(l1clk),
8553 .se(se),
8554 .pce_ov(pce_ov),
8555 .stop(stop)
8556);
8557
8558
8559
8560endmodule
8561
8562
8563
8564
8565
8566
8567
8568
8569
8570
8571
8572
8573
8574// any PARAMS parms go into naming of macro
8575
8576module l2t_arb_ctl_msff_ctl_macro__width_1 (
8577 din,
8578 l1clk,
8579 scan_in,
8580 siclk,
8581 soclk,
8582 dout,
8583 scan_out);
8584wire [0:0] fdin;
8585
8586 input [0:0] din;
8587 input l1clk;
8588 input scan_in;
8589
8590
8591 input siclk;
8592 input soclk;
8593
8594 output [0:0] dout;
8595 output scan_out;
8596assign fdin[0:0] = din[0:0];
8597
8598
8599
8600
8601
8602
8603dff #(1) d0_0 (
8604.l1clk(l1clk),
8605.siclk(siclk),
8606.soclk(soclk),
8607.d(fdin[0:0]),
8608.si(scan_in),
8609.so(scan_out),
8610.q(dout[0:0])
8611);
8612
8613
8614
8615
8616
8617
8618
8619
8620
8621
8622
8623
8624endmodule
8625
8626
8627
8628
8629
8630
8631
8632
8633
8634
8635
8636
8637
8638// any PARAMS parms go into naming of macro
8639
8640module l2t_arb_ctl_msff_ctl_macro__width_6 (
8641 din,
8642 l1clk,
8643 scan_in,
8644 siclk,
8645 soclk,
8646 dout,
8647 scan_out);
8648wire [5:0] fdin;
8649wire [4:0] so;
8650
8651 input [5:0] din;
8652 input l1clk;
8653 input scan_in;
8654
8655
8656 input siclk;
8657 input soclk;
8658
8659 output [5:0] dout;
8660 output scan_out;
8661assign fdin[5:0] = din[5:0];
8662
8663
8664
8665
8666
8667
8668dff #(6) d0_0 (
8669.l1clk(l1clk),
8670.siclk(siclk),
8671.soclk(soclk),
8672.d(fdin[5:0]),
8673.si({scan_in,so[4:0]}),
8674.so({so[4:0],scan_out}),
8675.q(dout[5:0])
8676);
8677
8678
8679
8680
8681
8682
8683
8684
8685
8686
8687
8688
8689endmodule
8690
8691
8692
8693
8694
8695
8696
8697
8698
8699
8700
8701
8702
8703// any PARAMS parms go into naming of macro
8704
8705module l2t_arb_ctl_msff_ctl_macro__clr_1__width_1 (
8706 din,
8707 clr,
8708 l1clk,
8709 scan_in,
8710 siclk,
8711 soclk,
8712 dout,
8713 scan_out);
8714wire [0:0] fdin;
8715
8716 input [0:0] din;
8717 input clr;
8718 input l1clk;
8719 input scan_in;
8720
8721
8722 input siclk;
8723 input soclk;
8724
8725 output [0:0] dout;
8726 output scan_out;
8727assign fdin[0:0] = din[0:0] & ~{1{clr}};
8728
8729
8730
8731
8732
8733
8734dff #(1) d0_0 (
8735.l1clk(l1clk),
8736.siclk(siclk),
8737.soclk(soclk),
8738.d(fdin[0:0]),
8739.si(scan_in),
8740.so(scan_out),
8741.q(dout[0:0])
8742);
8743
8744
8745
8746
8747
8748
8749
8750
8751
8752
8753
8754
8755endmodule
8756
8757
8758
8759
8760
8761
8762
8763
8764
8765
8766
8767
8768
8769// any PARAMS parms go into naming of macro
8770
8771module l2t_arb_ctl_msffi_ctl_macro__dmsff_16x__width_2 (
8772 din,
8773 l1clk,
8774 scan_in,
8775 siclk,
8776 soclk,
8777 q_l,
8778 scan_out);
8779wire [0:0] so;
8780
8781 input [1:0] din;
8782 input l1clk;
8783 input scan_in;
8784
8785
8786 input siclk;
8787 input soclk;
8788
8789 output [1:0] q_l;
8790 output scan_out;
8791
8792
8793
8794
8795
8796
8797msffi #(2) d0_0 (
8798.l1clk(l1clk),
8799.siclk(siclk),
8800.soclk(soclk),
8801.d(din[1:0]),
8802.si({scan_in,so[0:0]}),
8803.so({so[0:0],scan_out}),
8804.q_l(q_l[1:0])
8805);
8806
8807
8808
8809
8810
8811
8812
8813
8814
8815
8816
8817
8818endmodule
8819
8820
8821
8822
8823
8824
8825
8826
8827
8828
8829
8830
8831
8832// any PARAMS parms go into naming of macro
8833
8834module l2t_arb_ctl_msff_ctl_macro__width_3 (
8835 din,
8836 l1clk,
8837 scan_in,
8838 siclk,
8839 soclk,
8840 dout,
8841 scan_out);
8842wire [2:0] fdin;
8843wire [1:0] so;
8844
8845 input [2:0] din;
8846 input l1clk;
8847 input scan_in;
8848
8849
8850 input siclk;
8851 input soclk;
8852
8853 output [2:0] dout;
8854 output scan_out;
8855assign fdin[2:0] = din[2:0];
8856
8857
8858
8859
8860
8861
8862dff #(3) d0_0 (
8863.l1clk(l1clk),
8864.siclk(siclk),
8865.soclk(soclk),
8866.d(fdin[2:0]),
8867.si({scan_in,so[1:0]}),
8868.so({so[1:0],scan_out}),
8869.q(dout[2:0])
8870);
8871
8872
8873
8874
8875
8876
8877
8878
8879
8880
8881
8882
8883endmodule
8884
8885
8886
8887
8888
8889
8890
8891
8892
8893
8894
8895
8896
8897// any PARAMS parms go into naming of macro
8898
8899module l2t_arb_ctl_msff_ctl_macro__width_2 (
8900 din,
8901 l1clk,
8902 scan_in,
8903 siclk,
8904 soclk,
8905 dout,
8906 scan_out);
8907wire [1:0] fdin;
8908wire [0:0] so;
8909
8910 input [1:0] din;
8911 input l1clk;
8912 input scan_in;
8913
8914
8915 input siclk;
8916 input soclk;
8917
8918 output [1:0] dout;
8919 output scan_out;
8920assign fdin[1:0] = din[1:0];
8921
8922
8923
8924
8925
8926
8927dff #(2) d0_0 (
8928.l1clk(l1clk),
8929.siclk(siclk),
8930.soclk(soclk),
8931.d(fdin[1:0]),
8932.si({scan_in,so[0:0]}),
8933.so({so[0:0],scan_out}),
8934.q(dout[1:0])
8935);
8936
8937
8938
8939
8940
8941
8942
8943
8944
8945
8946
8947
8948endmodule
8949
8950
8951
8952
8953
8954
8955
8956
8957
8958
8959
8960
8961
8962// any PARAMS parms go into naming of macro
8963
8964module l2t_arb_ctl_msff_ctl_macro__clr_1__en_1__width_8 (
8965 din,
8966 en,
8967 clr,
8968 l1clk,
8969 scan_in,
8970 siclk,
8971 soclk,
8972 dout,
8973 scan_out);
8974wire [7:0] fdin;
8975wire [6:0] so;
8976
8977 input [7:0] din;
8978 input en;
8979 input clr;
8980 input l1clk;
8981 input scan_in;
8982
8983
8984 input siclk;
8985 input soclk;
8986
8987 output [7:0] dout;
8988 output scan_out;
8989assign fdin[7:0] = (din[7:0] & {8{en}} & ~{8{clr}}) | (dout[7:0] & ~{8{en}} & ~{8{clr}});
8990
8991
8992
8993
8994
8995
8996dff #(8) d0_0 (
8997.l1clk(l1clk),
8998.siclk(siclk),
8999.soclk(soclk),
9000.d(fdin[7:0]),
9001.si({scan_in,so[6:0]}),
9002.so({so[6:0],scan_out}),
9003.q(dout[7:0])
9004);
9005
9006
9007
9008
9009
9010
9011
9012
9013
9014
9015
9016
9017endmodule
9018
9019
9020
9021
9022
9023
9024
9025
9026
9027// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9028// also for pass-gate with decoder
9029
9030
9031
9032
9033
9034// any PARAMS parms go into naming of macro
9035
9036module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 (
9037 din0,
9038 sel0,
9039 din1,
9040 sel1,
9041 dout);
9042 input [3:0] din0;
9043 input sel0;
9044 input [3:0] din1;
9045 input sel1;
9046 output [3:0] dout;
9047
9048
9049
9050
9051
9052assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
9053 ( {4{sel1}} & din1[3:0]);
9054
9055
9056
9057
9058
9059endmodule
9060
9061
9062
9063
9064
9065
9066// any PARAMS parms go into naming of macro
9067
9068module l2t_arb_ctl_msff_ctl_macro__width_8 (
9069 din,
9070 l1clk,
9071 scan_in,
9072 siclk,
9073 soclk,
9074 dout,
9075 scan_out);
9076wire [7:0] fdin;
9077wire [6:0] so;
9078
9079 input [7:0] din;
9080 input l1clk;
9081 input scan_in;
9082
9083
9084 input siclk;
9085 input soclk;
9086
9087 output [7:0] dout;
9088 output scan_out;
9089assign fdin[7:0] = din[7:0];
9090
9091
9092
9093
9094
9095
9096dff #(8) d0_0 (
9097.l1clk(l1clk),
9098.siclk(siclk),
9099.soclk(soclk),
9100.d(fdin[7:0]),
9101.si({scan_in,so[6:0]}),
9102.so({so[6:0],scan_out}),
9103.q(dout[7:0])
9104);
9105
9106
9107
9108
9109
9110
9111
9112
9113
9114
9115
9116
9117endmodule
9118
9119
9120
9121
9122
9123
9124
9125
9126
9127
9128
9129
9130
9131// any PARAMS parms go into naming of macro
9132
9133module l2t_arb_ctl_msff_ctl_macro__width_7 (
9134 din,
9135 l1clk,
9136 scan_in,
9137 siclk,
9138 soclk,
9139 dout,
9140 scan_out);
9141wire [6:0] fdin;
9142wire [5:0] so;
9143
9144 input [6:0] din;
9145 input l1clk;
9146 input scan_in;
9147
9148
9149 input siclk;
9150 input soclk;
9151
9152 output [6:0] dout;
9153 output scan_out;
9154assign fdin[6:0] = din[6:0];
9155
9156
9157
9158
9159
9160
9161dff #(7) d0_0 (
9162.l1clk(l1clk),
9163.siclk(siclk),
9164.soclk(soclk),
9165.d(fdin[6:0]),
9166.si({scan_in,so[5:0]}),
9167.so({so[5:0],scan_out}),
9168.q(dout[6:0])
9169);
9170
9171
9172
9173
9174
9175
9176
9177
9178
9179
9180
9181
9182endmodule
9183
9184
9185
9186
9187
9188
9189
9190
9191
9192// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9193// also for pass-gate with decoder
9194
9195
9196
9197
9198
9199// any PARAMS parms go into naming of macro
9200
9201module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_3 (
9202 din0,
9203 sel0,
9204 din1,
9205 sel1,
9206 dout);
9207 input [2:0] din0;
9208 input sel0;
9209 input [2:0] din1;
9210 input sel1;
9211 output [2:0] dout;
9212
9213
9214
9215
9216
9217assign dout[2:0] = ( {3{sel0}} & din0[2:0] ) |
9218 ( {3{sel1}} & din1[2:0]);
9219
9220
9221
9222
9223
9224endmodule
9225
9226
9227// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9228// also for pass-gate with decoder
9229
9230
9231
9232
9233
9234// any PARAMS parms go into naming of macro
9235
9236module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 (
9237 din0,
9238 sel0,
9239 din1,
9240 sel1,
9241 dout);
9242 input [7:0] din0;
9243 input sel0;
9244 input [7:0] din1;
9245 input sel1;
9246 output [7:0] dout;
9247
9248
9249
9250
9251
9252assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) |
9253 ( {8{sel1}} & din1[7:0]);
9254
9255
9256
9257
9258
9259endmodule
9260
9261
9262
9263
9264
9265
9266// any PARAMS parms go into naming of macro
9267
9268module l2t_arb_ctl_msff_ctl_macro__clr_1__en_1__width_11 (
9269 din,
9270 en,
9271 clr,
9272 l1clk,
9273 scan_in,
9274 siclk,
9275 soclk,
9276 dout,
9277 scan_out);
9278wire [10:0] fdin;
9279wire [9:0] so;
9280
9281 input [10:0] din;
9282 input en;
9283 input clr;
9284 input l1clk;
9285 input scan_in;
9286
9287
9288 input siclk;
9289 input soclk;
9290
9291 output [10:0] dout;
9292 output scan_out;
9293assign fdin[10:0] = (din[10:0] & {11{en}} & ~{11{clr}}) | (dout[10:0] & ~{11{en}} & ~{11{clr}});
9294
9295
9296
9297
9298
9299
9300dff #(11) d0_0 (
9301.l1clk(l1clk),
9302.siclk(siclk),
9303.soclk(soclk),
9304.d(fdin[10:0]),
9305.si({scan_in,so[9:0]}),
9306.so({so[9:0],scan_out}),
9307.q(dout[10:0])
9308);
9309
9310
9311
9312
9313
9314
9315
9316
9317
9318
9319
9320
9321endmodule
9322
9323
9324
9325
9326
9327
9328
9329
9330
9331
9332
9333
9334
9335// any PARAMS parms go into naming of macro
9336
9337module l2t_arb_ctl_msff_ctl_macro__width_11 (
9338 din,
9339 l1clk,
9340 scan_in,
9341 siclk,
9342 soclk,
9343 dout,
9344 scan_out);
9345wire [10:0] fdin;
9346wire [9:0] so;
9347
9348 input [10:0] din;
9349 input l1clk;
9350 input scan_in;
9351
9352
9353 input siclk;
9354 input soclk;
9355
9356 output [10:0] dout;
9357 output scan_out;
9358assign fdin[10:0] = din[10:0];
9359
9360
9361
9362
9363
9364
9365dff #(11) d0_0 (
9366.l1clk(l1clk),
9367.siclk(siclk),
9368.soclk(soclk),
9369.d(fdin[10:0]),
9370.si({scan_in,so[9:0]}),
9371.so({so[9:0],scan_out}),
9372.q(dout[10:0])
9373);
9374
9375
9376
9377
9378
9379
9380
9381
9382
9383
9384
9385
9386endmodule
9387
9388
9389
9390
9391
9392
9393
9394
9395
9396
9397
9398
9399
9400// any PARAMS parms go into naming of macro
9401
9402module l2t_arb_ctl_msff_ctl_macro__en_1__width_8 (
9403 din,
9404 en,
9405 l1clk,
9406 scan_in,
9407 siclk,
9408 soclk,
9409 dout,
9410 scan_out);
9411wire [7:0] fdin;
9412wire [6:0] so;
9413
9414 input [7:0] din;
9415 input en;
9416 input l1clk;
9417 input scan_in;
9418
9419
9420 input siclk;
9421 input soclk;
9422
9423 output [7:0] dout;
9424 output scan_out;
9425assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}});
9426
9427
9428
9429
9430
9431
9432dff #(8) d0_0 (
9433.l1clk(l1clk),
9434.siclk(siclk),
9435.soclk(soclk),
9436.d(fdin[7:0]),
9437.si({scan_in,so[6:0]}),
9438.so({so[6:0],scan_out}),
9439.q(dout[7:0])
9440);
9441
9442
9443
9444
9445
9446
9447
9448
9449
9450
9451
9452
9453endmodule
9454
9455
9456
9457
9458
9459
9460
9461
9462
9463// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9464// also for pass-gate with decoder
9465
9466
9467
9468
9469
9470// any PARAMS parms go into naming of macro
9471
9472module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_2 (
9473 din0,
9474 sel0,
9475 din1,
9476 sel1,
9477 din2,
9478 sel2,
9479 din3,
9480 sel3,
9481 dout);
9482 input [1:0] din0;
9483 input sel0;
9484 input [1:0] din1;
9485 input sel1;
9486 input [1:0] din2;
9487 input sel2;
9488 input [1:0] din3;
9489 input sel3;
9490 output [1:0] dout;
9491
9492
9493
9494
9495
9496assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) |
9497 ( {2{sel1}} & din1[1:0]) |
9498 ( {2{sel2}} & din2[1:0]) |
9499 ( {2{sel3}} & din3[1:0]);
9500
9501
9502
9503
9504
9505endmodule
9506
9507
9508// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9509// also for pass-gate with decoder
9510
9511
9512
9513
9514
9515// any PARAMS parms go into naming of macro
9516
9517module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_3 (
9518 din0,
9519 sel0,
9520 din1,
9521 sel1,
9522 din2,
9523 sel2,
9524 dout);
9525 input [2:0] din0;
9526 input sel0;
9527 input [2:0] din1;
9528 input sel1;
9529 input [2:0] din2;
9530 input sel2;
9531 output [2:0] dout;
9532
9533
9534
9535
9536
9537assign dout[2:0] = ( {3{sel0}} & din0[2:0] ) |
9538 ( {3{sel1}} & din1[2:0]) |
9539 ( {3{sel2}} & din2[2:0]);
9540
9541
9542
9543
9544
9545endmodule
9546
9547
9548// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9549// also for pass-gate with decoder
9550
9551
9552
9553
9554
9555// any PARAMS parms go into naming of macro
9556
9557module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 (
9558 din0,
9559 sel0,
9560 din1,
9561 sel1,
9562 din2,
9563 sel2,
9564 din3,
9565 sel3,
9566 dout);
9567 input [4:0] din0;
9568 input sel0;
9569 input [4:0] din1;
9570 input sel1;
9571 input [4:0] din2;
9572 input sel2;
9573 input [4:0] din3;
9574 input sel3;
9575 output [4:0] dout;
9576
9577
9578
9579
9580
9581assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) |
9582 ( {5{sel1}} & din1[4:0]) |
9583 ( {5{sel2}} & din2[4:0]) |
9584 ( {5{sel3}} & din3[4:0]);
9585
9586
9587
9588
9589
9590endmodule
9591
9592
9593// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9594// also for pass-gate with decoder
9595
9596
9597
9598
9599
9600// any PARAMS parms go into naming of macro
9601
9602module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 (
9603 din0,
9604 sel0,
9605 din1,
9606 sel1,
9607 dout);
9608 input [4:0] din0;
9609 input sel0;
9610 input [4:0] din1;
9611 input sel1;
9612 output [4:0] dout;
9613
9614
9615
9616
9617
9618assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) |
9619 ( {5{sel1}} & din1[4:0]);
9620
9621
9622
9623
9624
9625endmodule
9626
9627
9628
9629
9630
9631
9632// any PARAMS parms go into naming of macro
9633
9634module l2t_arb_ctl_msff_ctl_macro__width_5 (
9635 din,
9636 l1clk,
9637 scan_in,
9638 siclk,
9639 soclk,
9640 dout,
9641 scan_out);
9642wire [4:0] fdin;
9643wire [3:0] so;
9644
9645 input [4:0] din;
9646 input l1clk;
9647 input scan_in;
9648
9649
9650 input siclk;
9651 input soclk;
9652
9653 output [4:0] dout;
9654 output scan_out;
9655assign fdin[4:0] = din[4:0];
9656
9657
9658
9659
9660
9661
9662dff #(5) d0_0 (
9663.l1clk(l1clk),
9664.siclk(siclk),
9665.soclk(soclk),
9666.d(fdin[4:0]),
9667.si({scan_in,so[3:0]}),
9668.so({so[3:0],scan_out}),
9669.q(dout[4:0])
9670);
9671
9672
9673
9674
9675
9676
9677
9678
9679
9680
9681
9682
9683endmodule
9684
9685
9686
9687
9688
9689
9690
9691
9692
9693// general mux macro for pass-gate and and-or muxes with/wout priority encoders
9694// also for pass-gate with decoder
9695
9696
9697
9698
9699
9700// any PARAMS parms go into naming of macro
9701
9702module l2t_arb_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_5 (
9703 din0,
9704 sel0,
9705 din1,
9706 sel1,
9707 din2,
9708 sel2,
9709 dout);
9710 input [4:0] din0;
9711 input sel0;
9712 input [4:0] din1;
9713 input sel1;
9714 input [4:0] din2;
9715 input sel2;
9716 output [4:0] dout;
9717
9718
9719
9720
9721
9722assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) |
9723 ( {5{sel1}} & din1[4:0]) |
9724 ( {5{sel2}} & din2[4:0]);
9725
9726
9727
9728
9729
9730endmodule
9731
Full OpenSPARC design & verification tarball including full HDL.