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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_arbadr_dp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_arbadr_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016// comments. requires about 20 tracks per bit pitch in the
1017// vertical direction.
1018
1019////////////////////////////////////////////////////////////////////////
1020// Local header file includes / local define
1021////////////////////////////////////////////////////////////////////////
1022
1023module l2t_arbadr_dp (
1024 tcu_pce_ov,
1025 tcu_aclk,
1026 tcu_bclk,
1027 tcu_scan_en,
1028 tcu_clk_stop,
1029 tcu_muxtest,
1030 tcu_dectest,
1031 ncu_l2t_pm,
1032 ncu_l2t_ba01,
1033 ncu_l2t_ba23,
1034 ncu_l2t_ba45,
1035 ncu_l2t_ba67,
1036 arbadr_dirvec_2bnk_true_enbld_dist,
1037 arbadr_dirvec_4bnk_true_enbld_dist,
1038 arbadr_dirvec_ncu_l2t_pm_n_dist,
1039 arbadr_evctag_2bnk_true_enbld_dist,
1040 arbadr_evctag_4bnk_true_enbld_dist,
1041 arbadr_evctag_ncu_l2t_pm_n_dist,
1042 arbadr_tagd_2bnk_true_enbld_dist,
1043 arbadr_tagd_4bnk_true_enbld_dist,
1044 arbadr_tagd_ncu_l2t_pm_n_dist,
1045 arbadr_arbctl_2bnk_true_enbld_dist,
1046 arbadr_arbctl_4bnk_true_enbld_dist,
1047 arbadr_arbctl_ncu_l2t_pm_n_dist,
1048 arbadr_arbdp_addr87_c2,
1049 sel_diag_store_data_c7,
1050 ique_iq_arbdp_addr_px2,
1051 snpd_snpq_arbdp_addr_px2,
1052 evctag_addr_px2,
1053 arbdat_arbdata_wr_data_c2,
1054 tagd_evict_tag_c3,
1055 tagd_evict_tag_c4,
1056 arb_mux2_snpsel_px2,
1057 arb_mux3_bufsel_px1,
1058 arb_mux4_c1sel_px2,
1059 arb_inc_tag_ecc_cnt_c3_n,
1060 arb_data_ecc_idx_reset,
1061 arb_data_ecc_idx_en,
1062 arb_sel_vuad_bist_px2,
1063 arb_sel_deccck_or_bist_idx,
1064 arb_sel_diag_addr_px2,
1065 arb_sel_tecc_addr_px2,
1066 arb_sel_deccck_addr_px2,
1067 arb_sel_diag_tag_addr_px2,
1068 arb_sel_lkup_stalled_tag_px2,
1069 arb_imiss_hit_c10,
1070 tag_rd64_complete_c11,
1071 arb_imiss_hit_c4,
1072 arb_sel_c2_stall_idx_c1,
1073 bist_data_set_c1,
1074 bist_data_enable_c1,
1075 bist_vuad_idx_px1,
1076 l2clk,
1077 io_cmp_sync_en,
1078 scan_in,
1079 scan_out,
1080 arbadr_arbdp_tag_idx_px2,
1081 arbadr_arbdp_vuad_idx1_px2,
1082 arbadr_arbdp_vuad_idx2_px2,
1083 arbadr_arbdp_tagdata_px2,
1084 arbadr_arbdp_cam_addr_px2,
1085 arbadr_mbcam_addr_px2,
1086 arbadr_arbdp_new_addr5to4_px2,
1087 arbadr_arbdp_addr_c1c2comp_c1,
1088 arbadr_arbdp_addr_c1c3comp_c1,
1089 arbadr_idx_c1c2comp_c1_n,
1090 arbadr_idx_c1c3comp_c1_n,
1091 arbadr_idx_c1c4comp_c1_n,
1092 arbadr_idx_c1c5comp_c1_n,
1093 arbadr_misbuf_idx_c1c2comp_c1,
1094 arbadr_misbuf_idx_c1c3comp_c1,
1095 arbadr_arbdp_ioaddr_c1,
1096 arbadr_arbdp_addr5to4_c1,
1097 arbadr_arbdp_addr3to2_c1,
1098 arbadr_arbdp_diag_wr_way_c2,
1099 l2t_l2d_set_c2,
1100 arbadr_arbaddr_addr22_c2,
1101 arbadr_arbdp_addr_start_c2,
1102 arbadr_arbaddr_idx_c3,
1103 arbadr_dir_cam_addr_c3,
1104 arbadr_arbdp_addr11to4_c3,
1105 arbadr_arbdp_addr5to4_c3,
1106 arbadr_c1_addr_eq_wb_c4,
1107 arbadr_arbdp_rdmat_addr_c6,
1108 arbadr_arbdp_waddr_c6,
1109 arbadr_arbdp_word_addr_c6,
1110 arbadr_csr_debug_addr,
1111 arbadr_arbdp_byte_addr_c6,
1112 arbadr_arbdp_addr22_c7,
1113 arbadr_arbdp_csr_addr_c9,
1114 arbadr_rdmard_addr_c12,
1115 arbadr_arbdp_line_addr_c6,
1116 arbadr_arbdp_oque_l1_index_c7,
1117 arbadr_dirvec_addr3_c7,
1118 arbadr_addr2_c8,
1119 arbadr_data_ecc_idx,
1120 arb_diag_or_tecc_write_px2,
1121 arb_sel_way_px2,
1122 arbadr_tag_wrdata_px2,
1123 l2t_mb2_run,
1124 mbist_tag_lkup_addr,
1125 mbist_lookupen,
1126 mbist_run,
1127 l2t_mb2_wdata,
1128 mb2_l2t_wk1_cam_shift,
1129 mb2_l2t_wk1_cam_init);
1130wire stop;
1131wire pce_ov;
1132wire siclk;
1133wire soclk;
1134wire se;
1135wire muxtst;
1136wire test;
1137wire ff_tagd_evict_tag_c4_scanin;
1138wire ff_tagd_evict_tag_c4_scanout;
1139wire [29:6] tecc_corr_tag_c1_unbuff;
1140wire [4:0] corr_bit_unbuff;
1141wire check_corr_bit_16;
1142wire check_corr_bit_8;
1143wire check_corr_bit_4;
1144wire check_corr_bit_2;
1145wire check_corr_bit_1;
1146wire cbit_err_n;
1147wire par_err_tag_c4_and_cbit_err;
1148wire ff_tecc_corr_tag_c2_scanin;
1149wire ff_tecc_corr_tag_c2_scanout;
1150wire arb_mux2_snpsel_px2_n;
1151wire [39:0] arbdp_addr_c1_1;
1152wire sel_diag_store_data_c7_n;
1153wire ff_mux3_bufsel_px2_scanin;
1154wire ff_mux3_bufsel_px2_scanout;
1155wire io_cmp_sync_en_r1;
1156wire sel_diag_store_data_c8_n;
1157wire sel_diag_store_data_c8;
1158wire arb_mux3_bufsel_px2;
1159wire arb_mux3_bufsel_px2_n;
1160wire snoop_select;
1161wire evict_select;
1162wire [39:0] arbdp_addr_c1_2;
1163wire ff_stall_addr_idx_c1_unbuff_scanin;
1164wire ff_stall_addr_idx_c1_unbuff_scanout;
1165wire [8:0] stall_addr_idx_c1_1;
1166wire [8:0] stall_addr_idx_c1_2;
1167wire [8:0] stall_addr_idx_c1_3;
1168wire [8:0] stall_addr_idx_px2_unbuff;
1169wire fourbanks_true_enbld_ff1;
1170wire twobanks_true_enbld_ff1;
1171wire l2t_mb2_run_r1_n;
1172wire l2t_mb2_run_r1;
1173wire ff_l2t_mb2_wdata_scanin;
1174wire ff_l2t_mb2_wdata_scanout;
1175wire mbist_run_r1;
1176wire [7:0] l2t_mb2_wdata_r1;
1177wire l2t_mb2_wdata_r1_0_n;
1178wire mbist_run_r1_n;
1179wire walk1;
1180wire walk0;
1181wire lookupen_and_shift_init;
1182wire mb2_l2t_wk1_cam_init_r1;
1183wire shift_init;
1184wire mb2_l2t_wk1_cam_shift_r1;
1185wire [41:7] cam_lookup_data_w;
1186wire [41:7] cam_lookup_data_reg;
1187wire ff_cam_mbist_datain_reg_scanin;
1188wire ff_cam_mbist_datain_reg_scanout;
1189wire [41:7] mbist_mbcam_addr_input;
1190wire [41:7] arbadr_mbcam_addr_px2_unbuff;
1191wire [8:0] arbadr_data_ecc_idx_internal;
1192wire [12:9] arbadr_unused;
1193wire [8:0] arbadr_data_ecc_idx_plus1;
1194wire [8:0] arb_data_ecc_idx_reset10_n;
1195wire [8:0] ff_data_ecc_idx_din;
1196wire ff_data_ecc_idx_scanin;
1197wire ff_data_ecc_idx_scanout;
1198wire ff_bist_vuad_idx_px2_scanin;
1199wire ff_bist_vuad_idx_px2_scanout;
1200wire arbadr_dirvec_addr3_c7_tmp;
1201wire arbadr_dirvec_addr3_c8;
1202wire arb_sel_vuad_bist_px2_n;
1203wire arb_inc_tag_ecc_cnt_c3_n_n;
1204wire ff_idx_hold_c2_scanin;
1205wire ff_idx_hold_c2_scanout;
1206wire arb_sel_diag_tag_addr_px2_n;
1207wire arb_sel_lkup_stalled_tag_px2_n;
1208wire ff_stall_addr_idx_c2to5_scanin;
1209wire ff_stall_addr_idx_c2to5_scanout;
1210wire ncu_l2t_pm_sync_n_ff1_n;
1211wire fourbanks_true_enbld_ff1_n;
1212wire twobanks_true_enbld_ff1_n;
1213wire ncu_l2t_pm_sync_n_ff1;
1214wire mux_data_idx_px2_sel1;
1215wire mux_data_idx_px2_sel2;
1216wire mux_data_idx_px2_sel3;
1217wire ff_ncu_signals_scanin;
1218wire ff_ncu_signals_scanout;
1219wire ncu_l2t_pm_sync;
1220wire ncu_l2t_ba01_sync;
1221wire ncu_l2t_ba23_sync;
1222wire ncu_l2t_ba45_sync;
1223wire ncu_l2t_ba67_sync;
1224wire ncu_l2t_pm_sync_n;
1225wire ncu_l2t_pm_sync_n_ff8;
1226wire ncu_l2t_pm_sync_n_ff7;
1227wire ncu_l2t_pm_sync_n_ff6;
1228wire ncu_l2t_pm_sync_n_ff5;
1229wire ncu_l2t_ba01_sync_n;
1230wire ncu_l2t_ba23_sync_n;
1231wire ncu_l2t_ba45_sync_n;
1232wire ncu_l2t_ba67_sync_n;
1233wire ba01_only_enbld;
1234wire ba23_only_enbld;
1235wire ba45_only_enbld;
1236wire ba67_only_enbld;
1237wire twobanks_enbld_1;
1238wire twobanks_enbld;
1239wire ba0123_enbld;
1240wire ba2345_enbld;
1241wire ba4567_enbld;
1242wire ba6701_enbld;
1243wire ba2367_enbld;
1244wire ba0145_enbld;
1245wire fourbanks_enbld_1;
1246wire fourbanks_enbld_2;
1247wire fourbanks_enbld;
1248wire twobanks_true_enbld;
1249wire twobanks_true_enbld_ff8;
1250wire twobanks_true_enbld_ff7;
1251wire twobanks_true_enbld_ff6;
1252wire twobanks_true_enbld_ff5;
1253wire fourbanks_true_enbld;
1254wire fourbanks_true_enbld_ff8;
1255wire fourbanks_true_enbld_ff7;
1256wire fourbanks_true_enbld_ff6;
1257wire fourbanks_true_enbld_ff5;
1258wire mux_ncu_l2t_pm_sync_n;
1259wire mux_twobanks_true_enbld;
1260wire mux_fourbanks_true_enbld;
1261wire [7:0] ncu_l2t_pm_sync_n_8;
1262wire [7:0] twobanks_true_enbld_8;
1263wire [7:0] fourbanks_true_enbld_8;
1264wire ff_l2d_idx_c1_scanin;
1265wire ff_l2d_idx_c1_scanout;
1266wire ff_ncu_mux_sel_2_scanin;
1267wire ff_ncu_mux_sel_2_scanout;
1268wire ff_ncu_mux_sel_3_scanin;
1269wire ff_ncu_mux_sel_3_scanout;
1270wire ncu_l2t_pm_sync_n_ff2;
1271wire twobanks_true_enbld_ff2;
1272wire fourbanks_true_enbld_ff2;
1273wire ff_ncu_mux_sel_1_scanin;
1274wire ff_ncu_mux_sel_1_scanout;
1275wire arb_sel_c2_stall_idx_c1_n;
1276wire bist_data_enable_c1_n;
1277wire ff_l2d_idx_c2_scanin;
1278wire ff_l2d_idx_c2_scanout;
1279wire ff_l2d_idx_fnl_c2_scanin;
1280wire ff_l2d_idx_fnl_c2_scanout;
1281wire arb_diag_or_tecc_write_px2_n;
1282wire arb_sel_way_px2_n;
1283wire [27:0] arbadr_tag_wrdata_px2_unbuff;
1284wire [39:0] arbdp_addr_c1_unbuff;
1285wire [39:0] arbdp_addr_c1_3;
1286wire ff_inst_addr_c1_scanin;
1287wire ff_inst_addr_c1_scanout;
1288wire ff_addr_c2_scanin;
1289wire ff_addr_c2_scanout;
1290wire [39:32] arbadr_arbdp_ioaddr_c1_unused;
1291wire ff_addr_c3_scanin;
1292wire ff_addr_c3_scanout;
1293wire arbadr_arbdp_addr_c1c2comp_c1_unbuff;
1294wire arbadr_arbdp_addr_c1c3comp_c1_unbuff;
1295wire ff_addr_c4_scanin;
1296wire ff_addr_c4_scanout;
1297wire arb_imiss_hit_c4_n;
1298wire ff_addr_c5_scanin;
1299wire ff_addr_c5_scanout;
1300wire ff_addr_c52_scanin;
1301wire ff_addr_c52_scanout;
1302wire ff_addr_c6_scanin;
1303wire ff_addr_c6_scanout;
1304wire ff_addr_c7_scanin;
1305wire ff_addr_c7_scanout;
1306wire ff_addr_c8_scanin;
1307wire ff_addr_c8_scanout;
1308wire ff_addr_c9_scanin;
1309wire ff_addr_c9_scanout;
1310wire ff_addr_c10_scanin;
1311wire ff_addr_c10_scanout;
1312wire ff_addr_c11_scanin;
1313wire ff_addr_c11_scanout;
1314wire arb_imiss_hit_c10_n;
1315wire ff_arbdp_addr_c12_scanin;
1316wire ff_arbdp_addr_c12_scanout;
1317wire arbadr_idx_c1c2comp_c1_unbuff;
1318wire arbadr_idx_c1c3comp_c1_unbuff;
1319wire arbadr_idx_c1c4comp_c1_unbuff;
1320wire arbadr_idx_c1c5comp_c1_unbuff;
1321wire arbadr_c1_addr_eq_wb_c4_unbuff_1;
1322wire arbadr_c1_addr_eq_wb_c4_unbuff_2;
1323wire arbadr_c1_addr_eq_wb_c4_unbuff;
1324
1325
1326 input tcu_pce_ov;
1327 input tcu_aclk;
1328 input tcu_bclk;
1329 input tcu_scan_en;
1330 input tcu_clk_stop;
1331 input tcu_muxtest;
1332 input tcu_dectest;
1333
1334// data to the L2 arbiter
1335
1336// BS 03/25/04 for partial bank/core modes support
1337input ncu_l2t_pm; // 0:all 8 banks available, 1:partial mode and need to look at each *ba* signals)
1338input ncu_l2t_ba01; // 0:bank0 and bank1 unavailable, 1:both banks available
1339input ncu_l2t_ba23; // 0:bank2 and bank3 unavailable, 1:both banks available
1340input ncu_l2t_ba45; // 0:bank4 and bank5 unavailable, 1:both banks available
1341input ncu_l2t_ba67; // 0:bank6 and bank7 unavailable, 1:both banks available
1342
1343output arbadr_dirvec_2bnk_true_enbld_dist; // 2 banks enabled
1344output arbadr_dirvec_4bnk_true_enbld_dist; // 4 banks enabled
1345output arbadr_dirvec_ncu_l2t_pm_n_dist;
1346
1347output arbadr_evctag_2bnk_true_enbld_dist; // 2 banks enabled
1348output arbadr_evctag_4bnk_true_enbld_dist; // 4 banks enabled
1349output arbadr_evctag_ncu_l2t_pm_n_dist;
1350
1351output arbadr_tagd_2bnk_true_enbld_dist; // 2 banks enabled
1352output arbadr_tagd_4bnk_true_enbld_dist; // 4 banks enabled
1353output arbadr_tagd_ncu_l2t_pm_n_dist;
1354
1355output arbadr_arbctl_2bnk_true_enbld_dist; // 2 banks enabled
1356output arbadr_arbctl_4bnk_true_enbld_dist; // 4 banks enabled
1357output arbadr_arbctl_ncu_l2t_pm_n_dist;
1358
1359
1360
1361
1362
1363output [1:0] arbadr_arbdp_addr87_c2; // PA [8:7] for forming directory address , BS 03/25/04 for partial bank/core modes support
1364
1365
1366input sel_diag_store_data_c7; // from tag, for store ack generation for diagnostic store
1367input [39:0] ique_iq_arbdp_addr_px2; // IQ instruction
1368input [39:0] snpd_snpq_arbdp_addr_px2; // PX2 instruction.
1369input [39:0] evctag_addr_px2; // mb fb addr mux output.
1370input [27:0] arbdat_arbdata_wr_data_c2; // for diagnostic tag writes. from arbdata // pin on the left
1371input [(`TAG_WIDTH-1):0] tagd_evict_tag_c3 ; // read tag. TOP
1372output [(`TAG_WIDTH-1):0] tagd_evict_tag_c4 ; // read tag. TOP
1373
1374//input csr_wr_dirpinj_en ; // parity injection into directory is enabled.
1375//input [3:0] tag_dir_l2way_sel_c3; // L2 tag hit way for directory , BS and SR 11/18/03 Reverse Directory change
1376
1377
1378input arb_mux2_snpsel_px2; // snp,mb and fb
1379input arb_mux3_bufsel_px1; // snp,mb and fb
1380//input arb_mux3_bufsel_px2; // snp,mb,fb or IQ
1381input arb_mux4_c1sel_px2; // snp,mb,fb,iq or C1
1382
1383input arb_inc_tag_ecc_cnt_c3_n; // from arb.
1384input arb_data_ecc_idx_reset; // decc scrub idx = 0 from arb
1385input arb_data_ecc_idx_en; // decc scrub idx increment. from arb
1386
1387input arb_sel_vuad_bist_px2; // NEW_PIN
1388input arb_sel_deccck_or_bist_idx; // NEW_PIN
1389// input sel_stall_vuad_idx ; // NEW_PIN from arb
1390
1391input arb_sel_diag_addr_px2; // diag tag idx sel
1392input arb_sel_tecc_addr_px2; // tecc idx sel.
1393input arb_sel_deccck_addr_px2; // decc idx sel.
1394input arb_sel_diag_tag_addr_px2; // diag or tecc or deccck only
1395input arb_sel_lkup_stalled_tag_px2; // sel stalled address.
1396input arb_imiss_hit_c10; // select to pick address
1397 // for a csr write. NEW_PIN replaces OLD_PIN arb_imiss_hit_c8
1398
1399input tag_rd64_complete_c11; // NEW_PIN
1400input arb_imiss_hit_c4; // select to pick an address for camming the dir
1401input arb_sel_c2_stall_idx_c1; // sel from arb
1402input [8:0] bist_data_set_c1; // from data bist
1403input bist_data_enable_c1; // from databist
1404input [8:0] bist_vuad_idx_px1 ; // POST_3.0 pin , BS & SR 10/28/03
1405input l2clk;
1406input io_cmp_sync_en;
1407input scan_in;
1408
1409output scan_out;
1410// PX2 outputs
1411output [8:0] arbadr_arbdp_tag_idx_px2 ; // addr<17:9> going to tag, BS & SR 10/28/03
1412output [8:0] arbadr_arbdp_vuad_idx1_px2 ; // addr<17:9> going to vuad . BS & SR 10/28/03
1413output [8:0] arbadr_arbdp_vuad_idx2_px2 ; // addr<17:9> going to vuad . BS & SR 10/28/03
1414// wr data to tagd
1415output [27:6] arbadr_arbdp_tagdata_px2; // lkup data for the tag. // int 5.0 changes
1416output [39:0] arbadr_arbdp_cam_addr_px2 ; // Address to l2t_arbadr_dp.sv
1417output [41:7] arbadr_mbcam_addr_px2 ; // Address to cam MBF.
1418output [1:0] arbadr_arbdp_new_addr5to4_px2; // to arb for col offset stall calculation ( does not include
1419 // the output of the stall mux .
1420
1421
1422// C1 outputs
1423output arbadr_arbdp_addr_c1c2comp_c1; // to misbuf via arb
1424output arbadr_arbdp_addr_c1c3comp_c1; // to misbuf via arb
1425
1426//output arbadr_idx_c1c2comp_c1 ; // to vuad dp via arb
1427//output arbadr_idx_c1c3comp_c1 ; // to vuad dp via arb
1428
1429output arbadr_idx_c1c2comp_c1_n;
1430output arbadr_idx_c1c3comp_c1_n;
1431output arbadr_idx_c1c4comp_c1_n;
1432output arbadr_idx_c1c5comp_c1_n;
1433
1434
1435//output arbadr_vuad_idx_c1c2comp_c1;
1436//output arbadr_vuad_idx_c1c3comp_c1;
1437output arbadr_misbuf_idx_c1c2comp_c1;
1438output arbadr_misbuf_idx_c1c3comp_c1;
1439
1440//output arbadr_idx_c1c4comp_c1 ; // to vuad dp via arb
1441//output arbadr_idx_c1c5comp_c1; // to vuad dp via arb
1442
1443//output [1:0] arbadr_arbdp_word_addr_c1; // to arbdec for pst decode logic
1444output [39:32] arbadr_arbdp_ioaddr_c1; // bits 39-32 are used to determine if the
1445 // address space is DRAM or diagnostic.
1446output [1:0] arbadr_arbdp_addr5to4_c1; // to arb foroffset stall calculation
1447output [1:0] arbadr_arbdp_addr3to2_c1 ; // output to tag.
1448
1449// C2 outputs
1450output [3:0] arbadr_arbdp_diag_wr_way_c2; // bit of the diagnostic access address indicate way.
1451
1452output [8:0] l2t_l2d_set_c2; // 2X wire going to l2d. BS & SR 10/28/03
1453output arbadr_arbaddr_addr22_c2; // used by vuad dp for muxing diagnostic read data.
1454output arbadr_arbdp_addr_start_c2; // NEW_PIN to l2t_arbdec.
1455
1456
1457// C3 outputs
1458// output [8:0] evctag_vuad_idx_c3; // NEW_PIN to vuad array
1459output [10:0] arbadr_arbaddr_idx_c3; // sent to tagd. BS & SR 10/28/03
1460output [39:7] arbadr_dir_cam_addr_c3; // output to tagd.
1461//output arbadr_arbdp_dir_wr_par_c3 ; // wr data for i and d directories.
1462output [7:0] arbadr_arbdp_addr11to4_c3; // output to arb for dir cam logic
1463output [1:0] arbadr_arbdp_addr5to4_c3 ; // output to arb for dir cam logic
1464//output [5:2] arbadr_arbdp_dbg_addr_c3 ; // output to dbg.
1465
1466
1467output arbadr_c1_addr_eq_wb_c4; //output to wbuf.
1468
1469//output [5:2] arbdp_tag_addr_c6; // to tag
1470output [5:2] arbadr_arbdp_rdmat_addr_c6; // to l2b_rep NEW_PIN
1471output [1:0] arbadr_arbdp_waddr_c6; // word addr to decc
1472output [4:0] arbadr_arbdp_word_addr_c6 ; // address of a Byte to csr. NEW_PIN
1473output [33:2] arbadr_csr_debug_addr; // address to csr for debug related logic
1474
1475output [2:0] arbadr_arbdp_byte_addr_c6; // to arbdec for pst decode logic // // Phase 2 : SIU inteface and packet format change 2/7/04
1476output arbadr_arbdp_addr22_c7 ; // diagnostic data word addr
1477output [39:4] arbadr_arbdp_csr_addr_c9; // NEW _PIN replaces OLD_PIN arbdp_csr_addr_c7
1478output [39:6] arbadr_rdmard_addr_c12; // NEW_PIN
1479output [5:4] arbadr_arbdp_line_addr_c6 ; // to oque.
1480//output [2:0] arbadr_arbdp_inst_byte_addr_c7 ; // to arb for dword mask generation.
1481output [11:6] arbadr_arbdp_oque_l1_index_c7; // l1 index.
1482output arbadr_dirvec_addr3_c7; // Bit 3 of address, BS and SR 11/12/03 N2 Xbar Packet format change
1483
1484output arbadr_addr2_c8 ; // to arb for cas compare.
1485
1486
1487output [8:0] arbadr_data_ecc_idx; // output to the CSR block. BS & SR 10/28/03
1488
1489
1490input arb_diag_or_tecc_write_px2; // new input. Left
1491input arb_sel_way_px2; // Left
1492output [27:0] arbadr_tag_wrdata_px2 ; // interleave with pins arbadr_arbdp_tagdata_px2
1493 // at the bottom.
1494
1495input l2t_mb2_run;
1496input [27:0] mbist_tag_lkup_addr;
1497input mbist_lookupen;
1498input mbist_run;
1499
1500
1501input [7:0] l2t_mb2_wdata;
1502input mb2_l2t_wk1_cam_shift;
1503input mb2_l2t_wk1_cam_init;
1504
1505assign stop = tcu_clk_stop;
1506assign pce_ov = tcu_pce_ov;
1507assign siclk = tcu_aclk;
1508assign soclk = tcu_bclk;
1509assign se = tcu_scan_en;
1510assign muxtst = tcu_muxtest;
1511assign test = tcu_dectest;
1512
1513//////////////////////////////////////////////////////////////////////////////
1514wire [31:0] arbadr_addr_c1_pbnk,arbadr_addr_c2_pbnk,arbadr_addr_c3_pbnk;
1515wire [23:0] tagd_evct_addr_39_16_c4;
1516wire [17:9] arbadr_mbcam_idx_px2; // Index to MB CAM
1517wire [27:6] arbadr_arbdp_tagdata_tmp_px2; // BS 03/25/04 for partial bank/core modes support
1518wire [39:18] evctag_addr_fnl_px2,arbdp_addr_c1_1_fnl; // BS 03/25/04 for partial bank/core modes support
1519wire [8:0] stall_addr_idx_c1,stall_addr_idx_c2,stall_addr_idx_c3,stall_addr_idx_c4,stall_addr_idx_c5;
1520 // BS 03/25/04 for partial bank/core modes support
1521wire [8:0] mux3_tag_idx_px2; // BS 03/25/04 for partial bank/core modes support
1522
1523wire [39:0] tag_diag_wr_data_c2; // diagnostic wr data after processing.
1524wire [29:0] err_tag_c4 ; // read tag.
1525wire cbit_err;
1526wire [29:0] tecc_corr_tag_c1; // corrected tag in the tagecc pipeline.
1527wire [27:0] tecc_corr_tag_c2; // corrected tag in the tagecc pipeline. // int 5.0 changes
1528wire par_err_tag_c4; // par err.
1529wire [8:0] tag_ecc_idx; // BS & SR 10/28/03
1530
1531wire [39:0] mux2_addr_px2; // snoop/mbf and fbf address.
1532wire [39:0] mux3_addr_px2; // snoop/mbf/fbf and Iq address.
1533wire [39:0] mux4_addr_px2; // snoop/mbf/fbf Iq address.
1534
1535wire [8:0] data_ecc_idx_plus1; // BS & SR 10/28/03
1536
1537wire [8:0] tag_acc_idx_px2; // BS & SR 10/28/03
1538wire [8:0] mux_idx2_px2; // BS & SR 10/28/03
1539wire [27:0] tag_acc_data_px2;
1540wire [27:0] mux2_tagdata_px2;
1541
1542wire [4:0] corr_bit;
1543
1544
1545wire [39:0] arbdp_addr_c1;
1546wire [39:0] arbdp_addr_c2;
1547wire [39:0] arbdp_addr_c3;
1548wire [39:0] arbdp_addr_c4;
1549wire [39:0] arbdp_addr_c5;
1550wire [39:0] arbdp_addr_c52; // BS 03/11/04 extra cycle for mem access
1551wire [39:0] arbdp_addr_c6;
1552wire [39:0] arbdp_addr_c7;
1553wire [39:0] arbdp_addr_c8;
1554wire [39:0] arbdp_addr_c9;
1555wire [39:0] arbdp_addr_c10;
1556wire [39:0] arbdp_addr_c11;
1557
1558
1559wire [8:0] data_idx_px2; // BS & SR 10/28/03
1560wire [8:0] data_idx_c1, data_bist_idx_c2, data_bist_idx_c1;
1561wire [8:0] stall_idx_c1;
1562wire [39:7] evict_addr_c4 ;
1563
1564wire [8:0] vuad_acc_idx_px2; // BS & SR 10/28/03
1565wire [8:0] vuad_idx2_px2; // BS & SR 10/28/03
1566wire [8:0] bist_vuad_idx; // BS & SR 10/28/03
1567
1568//////////////////////////////////////////////////////////////////////////////
1569/////////////////////////////////////////////////////////////
1570// dp is 30 bits wide eventhough tag is only 28 bits wide.
1571// ECC Correction and Generation for writing into the tag array.
1572// 30 bit wide dp eventhough, the tag is only 28 bits wide.
1573/////////////////////////////////////////////////////////////
1574
1575//assign err_tag_c4 = {2'b0,tagd_evict_tag_c4[(`TAG_WIDTH-1):0]};
1576
1577l2t_arbadr_dp_msff_macro__dmsff_32x__stack_30r__width_28 ff_tagd_evict_tag_c4
1578 (
1579 .scan_in(ff_tagd_evict_tag_c4_scanin),
1580 .scan_out(ff_tagd_evict_tag_c4_scanout),
1581 .dout (tagd_evict_tag_c4[(`TAG_WIDTH-1):0]),
1582 .din (tagd_evict_tag_c3[(`TAG_WIDTH-1):0]),
1583 .clk (l2clk),
1584 .en (1'b1),
1585 .se(se),
1586 .siclk(siclk),
1587 .soclk(soclk),
1588 .pce_ov(pce_ov),
1589 .stop(stop)
1590 );
1591
1592
1593l2t_arbadr_dp_buff_macro__dbuff_16x__width_30 buff_err_tag_c4
1594 (
1595 .dout (err_tag_c4[29:0]),
1596 .din ({2'b0,tagd_evict_tag_c4[(`TAG_WIDTH-1):0]})
1597 );
1598
1599l2t_ecc30b_dp ecc_corr
1600 (
1601 .din ({err_tag_c4[29:6]}),
1602 .parity (err_tag_c4[5:1]),
1603 .dout (tecc_corr_tag_c1_unbuff[29:6]),
1604 .corrected_bit(corr_bit_unbuff[4:0])
1605 );
1606
1607l2t_arbadr_dp_buff_macro__dbuff_16x__width_29 buff_ecc_out_corr_bit
1608 (
1609 .dout ({tecc_corr_tag_c1[29:6],corr_bit[4:0]}),
1610 .din ({tecc_corr_tag_c1_unbuff[29:6],corr_bit_unbuff[4:0]})
1611 );
1612
1613
1614//assign tecc_corr_tag_c1[5] = err_tag_c4[5] ^ ( corr_bit[4:0] == 5'd16) ;
1615//assign tecc_corr_tag_c1[4] = err_tag_c4[4] ^ ( corr_bit[4:0] == 5'd8) ;
1616//assign tecc_corr_tag_c1[3] = err_tag_c4[3] ^ ( corr_bit[4:0] == 5'd4) ;
1617//assign tecc_corr_tag_c1[2] = err_tag_c4[2] ^ ( corr_bit[4:0] == 5'd2) ;
1618//assign tecc_corr_tag_c1[1] = err_tag_c4[1] ^ ( corr_bit[4:0] == 5'd1) ;
1619
1620l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 check_corr_bit_16_slice
1621 (
1622 .din0 ({3'b0,corr_bit[4:0]}),
1623 .din1 ({3'b0,5'd16}),
1624 .dout ( check_corr_bit_16)
1625 );
1626
1627l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 check_corr_bit_08_slice
1628 (
1629 .din0 ({3'b0,corr_bit[4:0]}),
1630 .din1 ({3'b0,5'd8}),
1631 .dout ( check_corr_bit_8)
1632 );
1633
1634l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 check_corr_bit_04_slice
1635 (
1636 .din0 ({3'b0,corr_bit[4:0]}),
1637 .din1 ({3'b0,5'd4}),
1638 .dout ( check_corr_bit_4)
1639 );
1640
1641l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 check_corr_bit_02_slice
1642 (
1643 .din0 ({3'b0,corr_bit[4:0]}),
1644 .din1 ({3'b0,5'd2}),
1645 .dout ( check_corr_bit_2)
1646 );
1647
1648l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 check_corr_bit_01_slice
1649 (
1650 .din0 ({3'b0,corr_bit[4:0]}),
1651 .din1 ({3'b0,5'd1}),
1652 .dout (check_corr_bit_1)
1653 );
1654
1655l2t_arbadr_dp_xor_macro__width_1 xor_err_tag_5_corr_bit16
1656 (
1657 .dout (tecc_corr_tag_c1[5]),
1658 .din0 (check_corr_bit_16),
1659 .din1 (err_tag_c4[5])
1660 );
1661
1662l2t_arbadr_dp_xor_macro__width_1 xor_err_tag_4_corr_bit8
1663 (
1664 .dout (tecc_corr_tag_c1[4]),
1665 .din0 (check_corr_bit_8),
1666 .din1 (err_tag_c4[4])
1667 );
1668l2t_arbadr_dp_xor_macro__width_1 xor_err_tag_3_corr_bit4
1669 (
1670 .dout (tecc_corr_tag_c1[3]),
1671 .din0 (check_corr_bit_4),
1672 .din1 (err_tag_c4[3])
1673 );
1674l2t_arbadr_dp_xor_macro__width_1 xor_err_tag_2_corr_bit2
1675 (
1676 .dout (tecc_corr_tag_c1[2]),
1677 .din0 (check_corr_bit_2),
1678 .din1 (err_tag_c4[2])
1679 );
1680l2t_arbadr_dp_xor_macro__width_1 xor_err_tag_1_corr_bit1
1681 (
1682 .dout (tecc_corr_tag_c1[1]),
1683 .din0 (check_corr_bit_1),
1684 .din1 (err_tag_c4[1])
1685 );
1686
1687// assign cbit_err = |(corr_bit[4:0]);
1688
1689
1690l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 cmp_cbit_err
1691 (
1692 .dout (cbit_err_n),
1693 .din0 ({3'b0,corr_bit[4:0]}),
1694 .din1 (8'b0)
1695 );
1696
1697//or_macro corr_bit_slice_0 (width=1)
1698// (
1699// .dout (corr_bit_0_or_1),
1700// .din0 (corr_bit[0]),
1701// .din1 (corr_bit[1])
1702// );
1703//
1704//or_macro corr_bit_slice_1 (width=1)
1705// (
1706// .dout (corr_bit_1_or_2),
1707// .din0 (corr_bit_0_or_1),
1708// .din1 (corr_bit[2])
1709// );
1710//
1711//or_macro corr_bit_slice_2 (width=1)
1712// (
1713// .dout (corr_bit_2_or_3),
1714// .din0 (corr_bit_1_or_2),
1715// .din1 (corr_bit[3])
1716// );
1717//
1718//or_macro corr_bit_slice_3 (width=1)
1719// (
1720// .dout (cbit_err),
1721// .din0 (corr_bit_2_or_3),
1722// .din1 (corr_bit[4])
1723// );
1724//
1725//zzpar32 par_bit (.z(par_err_tag_c4), .d({err_tag_c4[29:0],2'b0}));
1726
1727l2t_arbadr_dp_prty_macro__dprty_8x__width_32 par_bit
1728 (
1729 .din ({err_tag_c4[29:0],2'b0}),
1730 .dout (par_err_tag_c4)
1731 );
1732
1733// assign tecc_corr_tag_c1[0] = ( par_err_tag_c4 & ~cbit_err ) ^ err_tag_c4[0] ;
1734
1735
1736l2t_arbadr_dp_and_macro__width_1 par_err_tag_c4_and_cbit_err_slice
1737 (
1738 .din1 (par_err_tag_c4),
1739 .din0 (cbit_err_n),
1740 .dout (par_err_tag_c4_and_cbit_err)
1741 );
1742
1743l2t_arbadr_dp_xor_macro__width_1 tecc_corr_tag_c1_0_slice_xor
1744 (
1745 .din1 (par_err_tag_c4_and_cbit_err),
1746 .din0 (err_tag_c4[0]),
1747 .dout (tecc_corr_tag_c1[0])
1748 );
1749
1750l2t_arbadr_dp_msff_macro__stack_28r__width_28 ff_tecc_corr_tag_c2 // int 5.0 changes
1751 (
1752 .scan_in(ff_tecc_corr_tag_c2_scanin),
1753 .scan_out(ff_tecc_corr_tag_c2_scanout),
1754 .din (tecc_corr_tag_c1[27:0]),
1755 .clk (l2clk),
1756 .dout (tecc_corr_tag_c2[27:0]),
1757 .en (1'b1),
1758 .se(se),
1759 .siclk(siclk),
1760 .soclk(soclk),
1761 .pce_ov(pce_ov),
1762 .stop(stop)
1763 );
1764
1765
1766/////////////////////////////////////////////////////////////////////////
1767// 1st level of ARB muxes
1768// 1) Mux between Fb and MB addr (in evctag)
1769// 2) Mux between Mux1 and SNp data
1770// 3) Mux between Mux2 and IQ data
1771/////////////////////////////////////////////////////////////////////////
1772
1773l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_mux2_snpsel_px2_inv_slice (
1774 .dout (arb_mux2_snpsel_px2_n),
1775 .din (arb_mux2_snpsel_px2)
1776 );
1777
1778
1779l2t_arbadr_dp_msff_macro__dmsff_32x__stack_8c__width_8 ff_mux3_bufsel_px2
1780 (
1781 .din({arbdp_addr_c1_1[21:18],io_cmp_sync_en,sel_diag_store_data_c7_n,
1782 sel_diag_store_data_c7,arb_mux3_bufsel_px1}),
1783 .clk(l2clk), .en(1'b1),
1784 .scan_in(ff_mux3_bufsel_px2_scanin),
1785 .scan_out(ff_mux3_bufsel_px2_scanout),
1786 .dout({arbadr_arbdp_diag_wr_way_c2[3:0],io_cmp_sync_en_r1,sel_diag_store_data_c8_n,
1787 sel_diag_store_data_c8,arb_mux3_bufsel_px2}),
1788 .se(se),
1789 .siclk(siclk),
1790 .soclk(soclk),
1791 .pce_ov(pce_ov),
1792 .stop(stop)
1793 );
1794
1795
1796l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_mux3_bufsel_px2_invert_slice (
1797 .dout (arb_mux3_bufsel_px2_n),
1798 .din (arb_mux3_bufsel_px2)
1799 );
1800
1801l2t_arbadr_dp_and_macro__width_1 and_snp_select
1802 (
1803 .dout (snoop_select),
1804 .din0 (arb_mux2_snpsel_px2),
1805 .din1 (arb_mux3_bufsel_px2)
1806 );
1807
1808l2t_arbadr_dp_and_macro__width_1 and_evict_select
1809 (
1810 .dout (evict_select),
1811 .din0 (arb_mux2_snpsel_px2_n),
1812 .din1 (arb_mux3_bufsel_px2)
1813 );
1814
1815l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_40r__width_40 mux_mux3_instr_px2
1816 (
1817 .dout (mux3_addr_px2[39:0]) ,
1818 .din0 (snpd_snpq_arbdp_addr_px2[39:0]),
1819 .din1 (ique_iq_arbdp_addr_px2[39:0]),
1820 .din2 (evctag_addr_px2[39:0]),
1821 .sel0 (snoop_select),
1822 .sel1 (arb_mux3_bufsel_px2_n),
1823 .sel2 (evict_select)
1824 );
1825
1826
1827l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_40r__width_40 mux_mux4_instr_px2
1828 (
1829 .dout (mux4_addr_px2[39:0]) ,
1830 .din0 (arbdp_addr_c1_2[39:0]),
1831 .din1 (mux3_addr_px2[39:0]),
1832 .sel0 (arb_mux4_c1sel_px2)
1833 );
1834
1835
1836//assign arbadr_arbdp_new_addr5to4_px2 = mux3_addr_px2[5:4]; // column offset
1837//assign arbadr_arbdp_cam_addr_px2 = mux4_addr_px2[39:0] ; // miss buffer cam address.
1838
1839
1840l2t_arbadr_dp_buff_macro__dbuff_32x__stack_40r__width_40 buff_arbadr_arbdp_cam_addr_px2
1841 (
1842 .dout (arbadr_arbdp_cam_addr_px2[39:0]),
1843 .din (mux4_addr_px2[39:0])
1844 );
1845
1846//buff_macro buff_arbadr_arbdp_new_addr5to4_px2 (width=2,stack=2r,dbuff=32x)
1847// (
1848// .dout (arbadr_arbdp_new_addr5to4_px2[1:0]),
1849// .din (mux3_addr_px2[5:4])
1850// );
1851//
1852//buff_macro buff_stall_addr_idx_c1 (width=27,dbuff=32x)
1853// (
1854// .dout ({stall_addr_idx_c1_1[8:0],stall_addr_idx_c1_2[8:0],stall_addr_idx_c1_3[8:0]}),
1855// .din ({stall_addr_idx_c1_unbuff[8:0],stall_addr_idx_c1_unbuff[8:0],stall_addr_idx_c1_unbuff[8:0]})
1856// );
1857//
1858
1859
1860l2t_arbadr_dp_msff_macro__dmsff_32x__stack_36r__width_27 ff_stall_addr_idx_c1_unbuff
1861 (
1862 .scan_in(ff_stall_addr_idx_c1_unbuff_scanin),
1863 .scan_out(ff_stall_addr_idx_c1_unbuff_scanout),
1864 .dout ({stall_addr_idx_c1_1[8:0],stall_addr_idx_c1_2[8:0],stall_addr_idx_c1_3[8:0]}),
1865 .din ({stall_addr_idx_px2_unbuff[8:0],stall_addr_idx_px2_unbuff[8:0],stall_addr_idx_px2_unbuff[8:0]}),
1866 .clk (l2clk),
1867 .en (1'b1),
1868 .se(se),
1869 .siclk(siclk),
1870 .soclk(soclk),
1871 .pce_ov(pce_ov),
1872 .stop(stop)
1873 );
1874
1875
1876l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_36r__width_27 mux_arbadr_idx_px2
1877 (
1878 .dout({stall_addr_idx_px2_unbuff[8:0],arbadr_arbdp_vuad_idx1_px2[8:0], arbadr_mbcam_idx_px2[17:9]}),
1879 .din0({mux4_addr_px2[16:8] ,mux3_addr_px2[16:8], mux4_addr_px2[16:8]}),
1880 .din1({mux4_addr_px2[15:7] ,mux3_addr_px2[15:7], mux4_addr_px2[15:7]}),
1881 .din2({mux4_addr_px2[17:9] ,mux3_addr_px2[17:9], mux4_addr_px2[17:9]}),
1882 .sel0(fourbanks_true_enbld_ff1), // 1 bit shifted idx in case of 4 banks enabled
1883 .sel1(twobanks_true_enbld_ff1),
1884 .muxtst(muxtst),
1885 .test(test) // 2 bit shifted idx of 2 banks enabled
1886// .sel2(ncu_l2t_pm_sync_n_ff1), // original idx , all banks enabled
1887 );
1888
1889l2t_arbadr_dp_inv_macro__dinv_32x__width_1 inv_l2t_mb2_run
1890 (
1891 .dout (l2t_mb2_run_r1_n),
1892 .din (l2t_mb2_run_r1)
1893 );
1894
1895
1896l2t_arbadr_dp_msff_macro__stack_10r__width_9 ff_l2t_mb2_wdata
1897 (
1898 .scan_in(ff_l2t_mb2_wdata_scanin),
1899 .scan_out(ff_l2t_mb2_wdata_scanout),
1900 .dout ({mbist_run_r1,l2t_mb2_wdata_r1[7:0]}),
1901 .din ({mbist_run,l2t_mb2_wdata[7:0]}),
1902 .clk (l2clk),
1903 .en (1'b1),
1904 .se(se),
1905 .siclk(siclk),
1906 .soclk(soclk),
1907 .pce_ov(pce_ov),
1908 .stop(stop)
1909 );
1910
1911l2t_arbadr_dp_inv_macro__dinv_32x__width_2 inv_l2t_mb2_wdata_r1_0
1912 (
1913 .dout ({l2t_mb2_wdata_r1_0_n,mbist_run_r1_n}),
1914 .din ({l2t_mb2_wdata_r1[0],mbist_run_r1})
1915 );
1916
1917l2t_arbadr_dp_and_macro__width_3 and_mbist_gate1
1918 (
1919 .dout ({walk1,walk0,lookupen_and_shift_init}),
1920 .din0 ({mb2_l2t_wk1_cam_init_r1,mb2_l2t_wk1_cam_init_r1,mbist_lookupen}),
1921 .din1 ({l2t_mb2_wdata_r1[0],l2t_mb2_wdata_r1_0_n,shift_init})
1922 );
1923
1924l2t_arbadr_dp_nor_macro__width_1 nor_shift_init
1925 (
1926 .dout (shift_init),
1927 .din0 (mb2_l2t_wk1_cam_shift_r1),
1928 .din1 (mb2_l2t_wk1_cam_init_r1)
1929 );
1930
1931l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_5__stack_35r__width_35 mux_cam_lookup_data
1932 (
1933 .dout (cam_lookup_data_w[41:7]),
1934 .din0 ({34'b0,1'b1}), // initial loading 0 or 1
1935 .din1 ({{34{1'b1}},1'b0}), //walk 0 or 1
1936 .din2 ({cam_lookup_data_reg[40:7],l2t_mb2_wdata_r1_0_n}), //walk 0 or 1
1937 .din3 (35'h0), // initialize lookup
1938 .din4 ({l2t_mb2_wdata_r1[2:0],{4{l2t_mb2_wdata_r1[7:0]}}}), // camming data
1939 .sel0 (walk1),
1940 .sel1 (walk0),
1941 .sel2 (mb2_l2t_wk1_cam_shift_r1),
1942 .sel3 (l2t_mb2_run_r1_n),
1943 .sel4 (lookupen_and_shift_init)
1944 );
1945
1946
1947l2t_arbadr_dp_msff_macro__stack_35r__width_35 ff_cam_mbist_datain_reg
1948 (
1949 .scan_in(ff_cam_mbist_datain_reg_scanin),
1950 .scan_out(ff_cam_mbist_datain_reg_scanout),
1951 .dout (cam_lookup_data_reg[41:7]),
1952 .din (cam_lookup_data_w[41:7]),
1953 .clk (l2clk),
1954 .en (1'b1),
1955 .se(se),
1956 .siclk(siclk),
1957 .soclk(soclk),
1958 .pce_ov(pce_ov),
1959 .stop(stop)
1960 );
1961
1962//mux_macro mux_wlk_lookup_addr (width=35,ports=2,mux=aonpe,dmux=8x)
1963// (
1964// .dout (cam_lookup_data[41:7]),
1965// .din0 ({7'b0,cam_lookup_data_reg[27:7],7'b0}),
1966// .din1 (cam_lookup_data_reg[41:7]),
1967// .sel0 (l2t_mb2_run_r1),
1968// .sel1 (l2t_mb2_run_r1_n)
1969// );
1970
1971l2t_arbadr_dp_buff_macro__dbuff_8x__stack_35r__width_35 buff_mbist_mbcam_addr_input
1972 (
1973 .dout (mbist_mbcam_addr_input[41:7]),
1974// .din (cam_lookup_data_reg[41:7])
1975// .din (cam_lookup_data_w[41:7])
1976 .din (cam_lookup_data_reg[41:7])
1977 );
1978
1979l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_35r__width_35 mux_arbadr_mbcam_addr_px2
1980 (
1981 .dout (arbadr_mbcam_addr_px2_unbuff[41:7]),
1982 .din0 (mbist_mbcam_addr_input[41:7]),
1983 .din1 ({mux4_addr_px2[39:16],arbadr_mbcam_idx_px2[17:9],mux4_addr_px2[8:7]}),
1984 .sel0 (l2t_mb2_run_r1),
1985 .sel1 (l2t_mb2_run_r1_n)
1986 );
1987
1988l2t_arbadr_dp_buff_macro__dbuff_32x__stack_37r__width_37 buff_arbadr_mbcam_addr_px2
1989 (
1990 .dout ({arbadr_mbcam_addr_px2[41:7],arbadr_arbdp_new_addr5to4_px2[1:0]}),
1991 .din ({arbadr_mbcam_addr_px2_unbuff[41:7],mux3_addr_px2[5:4]})
1992 );
1993
1994
1995
1996////////////////////////////////////////////////////////////////////////
1997// INDEX BITS TO THE VUAD.
1998////////////////////////////////////////////////////////////////////////
1999
2000
2001// data ecc index manipulation.
2002//assign arbadr_data_ecc_idx_plus1 = arbadr_data_ecc_idx + 10'b1 ;
2003
2004l2t_arbadr_dp_increment_macro__dincr_8x__width_12 decc_incr // BS & SR 10/28/03
2005 (
2006// .din ( {3'b000,arbadr_data_ecc_idx[8:0]} ) ,
2007 .din ( {3'b000,arbadr_data_ecc_idx_internal[8:0]} ) ,
2008 .cin (1'b1 ) ,
2009 .dout ({arbadr_unused[11:9],arbadr_data_ecc_idx_plus1[8:0]}) ,
2010 .cout (arbadr_unused[12])
2011 );
2012
2013l2t_arbadr_dp_inv_macro__dinv_32x__stack_9r__width_9 arb_data_ecc_idx_reset_inv_slice
2014 (
2015 .dout (arb_data_ecc_idx_reset10_n[8:0]),
2016 .din ({9{arb_data_ecc_idx_reset}})
2017 );
2018
2019///assign arb_data_ecc_idx_reset10_n[8:0] = {9{arb_data_ecc_idx_reset_n}}; // BS & SR 10/28/03
2020
2021
2022l2t_arbadr_dp_and_macro__width_9 ff_data_ecc_idx_din_and_macro // BS & SR 10/28/03
2023 (
2024 .dout (ff_data_ecc_idx_din[8:0]),
2025 .din0 (arb_data_ecc_idx_reset10_n[8:0]),
2026 .din1 (arbadr_data_ecc_idx_plus1[8:0])
2027 );
2028
2029l2t_arbadr_dp_msff_macro__dmsff_32x__stack_20r__width_18 ff_data_ecc_idx // BS & SR 10/28/03
2030 (
2031 .scan_in(ff_data_ecc_idx_scanin),
2032 .scan_out(ff_data_ecc_idx_scanout),
2033 .clk (l2clk),
2034 .din ({ff_data_ecc_idx_din[8:0],ff_data_ecc_idx_din[8:0]}),
2035 .dout ({arbadr_data_ecc_idx_internal[8:0],arbadr_data_ecc_idx[8:0]}),
2036 .en (arb_data_ecc_idx_en),
2037 .se(se),
2038 .siclk(siclk),
2039 .soclk(soclk),
2040 .pce_ov(pce_ov),
2041 .stop(stop)
2042 );
2043
2044
2045l2t_arbadr_dp_msff_macro__stack_13r__width_13 ff_bist_vuad_idx_px2 // BS & SR 10/28/03
2046 (
2047 .scan_in(ff_bist_vuad_idx_px2_scanin),
2048 .scan_out(ff_bist_vuad_idx_px2_scanout),
2049 .din ({arbadr_dirvec_addr3_c7_tmp,l2t_mb2_run,bist_vuad_idx_px1[8:0],
2050 mb2_l2t_wk1_cam_init,mb2_l2t_wk1_cam_shift}),
2051 .clk (l2clk),
2052 .dout ({arbadr_dirvec_addr3_c8,l2t_mb2_run_r1,bist_vuad_idx[8:0],
2053 mb2_l2t_wk1_cam_init_r1,mb2_l2t_wk1_cam_shift_r1}),
2054 .en (1'b1),
2055 .se(se),
2056 .siclk(siclk),
2057 .soclk(soclk),
2058 .pce_ov(pce_ov),
2059 .stop(stop)
2060 );
2061
2062
2063l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_sel_vuad_bist_px2_inv_slice (
2064 .dout (arb_sel_vuad_bist_px2_n),
2065 .din (arb_sel_vuad_bist_px2)
2066 );
2067
2068l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_10r__width_9 mux_vuad_acc_idx_px2 // BS & SR 10/28/03
2069 (
2070 .dout ( vuad_acc_idx_px2[8:0] ) ,
2071// .din0 (arbadr_data_ecc_idx[8:0]), // deccck idx
2072 .din0 (arbadr_data_ecc_idx_internal[8:0]), // deccck idx
2073 .din1 (bist_vuad_idx[8:0]), // tecc idx
2074 .sel0 (arb_sel_vuad_bist_px2_n), // sel deccck
2075 .sel1 (arb_sel_vuad_bist_px2)
2076 ); // sel tecc
2077
2078//inv_macro arb_sel_deccck_or_bist_idx_inv_slice (width=1,dinv=32x)
2079// (
2080// .dout (arb_sel_deccck_or_bist_idx_n),
2081// .din (arb_sel_deccck_or_bist_idx)
2082// );
2083
2084
2085l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_10r__width_9 mux_vuad_idx2_px2 // BS & SR 10/28/03
2086 (
2087// .dout (vuad_idx2_px2[8:0] ) ,
2088 .dout (arbadr_arbdp_vuad_idx2_px2[8:0] ) ,
2089 .din0(vuad_acc_idx_px2[8:0]), // bist or deccck idx
2090 .din1(stall_addr_idx_c1_1[8:0]), // stalled addr, BS 03/25/04 for partial bank/core modes support
2091 .sel0(arb_sel_deccck_or_bist_idx) // select diag/bist addr
2092// .sel1(arb_sel_deccck_or_bist_idx_n) // ~select diag/bist addr
2093 );
2094
2095// BS 03/25/04 for partial bank/core modes support
2096// vuad index shift for unstalled operations
2097
2098//mux_macro mux_arbadr_arbdp_vuad_idx1_px2 (width=9,ports=3,mux=aonpe,stack=10r,dmux=8x)
2099// (.dout (arbadr_arbdp_vuad_idx1_px2_unbuff[8:0]) , // index for unstalled operations.
2100// .din0(mux3_addr_px2[17:9]), // original idx from core/siu/mbf/filbuf, all banks enabled
2101// .din1(mux3_addr_px2[16:8]), // 1 bit shifted idx in case of 4 banks enabled
2102// .din2(mux3_addr_px2[15:7]), // 2 bit shifted idx in case of 2 banks enabled
2103// .sel0(ncu_l2t_pm_sync_n),
2104// .sel1(fourbanks_true_enbld),
2105// .sel2(twobanks_true_enbld)
2106// );
2107
2108
2109//assign arbadr_arbdp_vuad_idx2_px2 = vuad_idx2_px2[8:0] ; // index for stalled operations.
2110
2111//buff_macro buff_arbadr_arbdp_vuad_idx1_px2 (width=18,stack=18r,dbuff=32x)
2112// (
2113// .dout ({arbadr_arbdp_vuad_idx2_px2[8:0],arbadr_arbdp_vuad_idx1_px2[8:0]}),
2114// .din ({vuad_idx2_px2[8:0],arbadr_arbdp_vuad_idx1_px2_unbuff[8:0]})
2115//// );
2116//
2117//buff_macro buff_arbadr_arbdp_vuad_idx1_px2 (width=9,stack=10r,dbuff=32x)
2118// (
2119// .dout (arbadr_arbdp_vuad_idx2_px2[8:0]),
2120// .din (vuad_idx2_px2[8:0])
2121// );
2122//
2123//
2124
2125
2126
2127//////////////////////////////////////////////////////////////////////////
2128// INDEX BITS TO THE TAG.
2129// The index of a C1 stalled instruction is muxed with the following
2130// components to generate the address for accessing tag/vuad arrays
2131// tag_ecc addr.
2132// data_ecc_addr.
2133// tag diagnostic addr.
2134// ( The tag BIST mux is located inside the tag array )
2135//
2136// two separate addresses are sent to the tag array/vuad array.
2137// these arrays select between the new address or the address of the
2138// stalled instruction. The select signal is generated in l2t_arb_ctl.sv
2139////////////////////////////////////////////////////////////////////////
2140
2141l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_inc_tag_ecc_cnt_c3_n_inv_slice (
2142 .dout (arb_inc_tag_ecc_cnt_c3_n_n),
2143 .din (arb_inc_tag_ecc_cnt_c3_n)
2144 );
2145
2146l2t_arbadr_dp_msff_macro__stack_10r__width_9 ff_idx_hold_c2 // BS & SR 10/28/03
2147// (.din(arbdp_addr_c2[17:9]), .clk(l2clk),
2148 (.din(arbadr_addr_c2_pbnk[8:0]), .clk(l2clk), // fix for bug 117807
2149 .scan_in(ff_idx_hold_c2_scanin),
2150 .scan_out(ff_idx_hold_c2_scanout),
2151 .dout(tag_ecc_idx[8:0]), .en(arb_inc_tag_ecc_cnt_c3_n),
2152 .se(se),
2153 .siclk(siclk),
2154 .soclk(soclk),
2155 .pce_ov(pce_ov),
2156 .stop(stop)
2157 );
2158
2159
2160l2t_arbadr_dp_mux_macro__dmux_8x__mux_pgnpe__ports_3__stack_10r__width_9 mux_tag_idx_px // BS & SR 10/28/03
2161 (.dout ( tag_acc_idx_px2[8:0] ) ,
2162// .din0(arbadr_data_ecc_idx[8:0]), // deccck idx
2163 .din0(arbadr_data_ecc_idx_internal[8:0]), // deccck idx
2164 .din1(tag_ecc_idx[8:0]), // tecc idx
2165 .din2(arbdp_addr_c2[17:9]), // diagnostic wr.
2166 .sel0(arb_sel_deccck_addr_px2), // sel decc
2167 .sel1(arb_sel_tecc_addr_px2), // sel tecc
2168 .sel2(arb_sel_diag_addr_px2),
2169 .muxtst(muxtst)); // sel diag wr.
2170
2171l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_sel_diag_tag_addr_px2_inv_slice (
2172 .dout (arb_sel_diag_tag_addr_px2_n),
2173 .din (arb_sel_diag_tag_addr_px2)
2174 );
2175
2176l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_10r__width_9 mux_mux_idx2_px2 // BS & SR 10/28/03
2177 (.dout (mux_idx2_px2[8:0] ) ,
2178 .din0(tag_acc_idx_px2[8:0]), // tecc, deccck and diag write.
2179 .din1(stall_addr_idx_c1_1[8:0]), // stalled addr, BS 03/25/04 for partial bank/core modes support
2180 .sel0(arb_sel_diag_tag_addr_px2), // select diag/tecc/deccck addr
2181 .sel1(arb_sel_diag_tag_addr_px2_n)); // sel stalled addr.
2182
2183l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_sel_lkup_stalled_tag_px2_inv_slice (
2184 .dout (arb_sel_lkup_stalled_tag_px2_n),
2185 .din (arb_sel_lkup_stalled_tag_px2)
2186 );
2187
2188
2189// BS 03/25/04 for partial bank/core modes support
2190// tag index shift , shift only indices from core/siu/mbf/fbf/stalled instructions
2191// no shift for tecc, scrub and diagnostic accesses
2192//mux_macro mux_stall_addr_idx_c1 (width=9,ports=3,mux=aonpe,stack=10r,dmux=8x)
2193// (.dout (stall_addr_idx_c1[8:0]) ,
2194// .din0 (arbdp_addr_c1[17:9] ), // original idx from core/siu/mbf/filbuf, all banks enabled
2195// .din1 (arbdp_addr_c1[16:8] ), // 1 bit shifted idx in case of 4 banks enabled
2196// .din2 (arbdp_addr_c1[15:7] ), // 2 bit shifted idx in case of 2 banks enabled
2197// .sel0(ncu_l2t_pm_sync_n),
2198// .sel1(fourbanks_true_enbld),
2199// .sel2(twobanks_true_enbld)
2200// );
2201// B.S : 03/26/05
2202// Flop stall_addr_idx_c1 till c5 , these will be used to detect index matches
2203// between wr and rd of vuad to trigger vuad bypass.
2204
2205l2t_arbadr_dp_msff_macro__stack_36r__width_36 ff_stall_addr_idx_c2to5 // BS & SR 10/28/03
2206 (
2207 .scan_in(ff_stall_addr_idx_c2to5_scanin),
2208 .scan_out(ff_stall_addr_idx_c2to5_scanout),
2209 .din({stall_addr_idx_c1_1[8:0],stall_addr_idx_c2[8:0],stall_addr_idx_c3[8:0],stall_addr_idx_c4[8:0]}),
2210 .clk(l2clk),
2211 .dout({stall_addr_idx_c2[8:0],stall_addr_idx_c3[8:0],stall_addr_idx_c4[8:0],stall_addr_idx_c5[8:0]}),
2212 .en(1'b1),
2213 .se(se),
2214 .siclk(siclk),
2215 .soclk(soclk),
2216 .pce_ov(pce_ov),
2217 .stop(stop)
2218 );
2219
2220//////////////////////////////
2221l2t_arbadr_dp_inv_macro__dinv_32x__width_3 inv_partial_core_signals
2222 (
2223 .dout ({ncu_l2t_pm_sync_n_ff1_n,fourbanks_true_enbld_ff1_n,twobanks_true_enbld_ff1_n}),
2224 .din ({ncu_l2t_pm_sync_n_ff1,fourbanks_true_enbld_ff1,twobanks_true_enbld_ff1})
2225 );
2226
2227l2t_arbadr_dp_nor_macro__dnor_16x__width_1 nor_mux_data_idx_px2_muxsel_1
2228 (
2229 .dout (mux_data_idx_px2_sel1),
2230 .din0 (arb_sel_lkup_stalled_tag_px2),
2231 .din1 (ncu_l2t_pm_sync_n_ff1_n)
2232 );
2233
2234l2t_arbadr_dp_nor_macro__dnor_16x__ports_3__width_2 nor_mux_data_idx_px2_muxsel_2_3 // fix for bug 111495
2235 (
2236 .dout ({mux_data_idx_px2_sel2,mux_data_idx_px2_sel3}),
2237 .din0 ({arb_sel_lkup_stalled_tag_px2,arb_sel_lkup_stalled_tag_px2}),
2238 .din1 ({fourbanks_true_enbld_ff1_n,fourbanks_true_enbld_ff1}),
2239 .din2 ({ncu_l2t_pm_sync_n_ff1,ncu_l2t_pm_sync_n_ff1})
2240 );
2241
2242
2243// ATPG fix not possible on this mux.. very critical timing
2244//
2245//mux_macro mux_data_idx_px2 (width=9,ports=4,mux=pgnpe,stack=10r,dmux=32x) // ATPG FLAGGED
2246// (
2247// .dout (data_idx_px2[8:0]) ,
2248// .din0 (mux3_addr_px2[17:9]), // instruction Px2 addr
2249// .din1 (mux3_addr_px2[16:8]),
2250// .din2 (mux3_addr_px2[15:7]),
2251// .din3 (mux_idx2_px2[8:0]), // C1 or modified index
2252// .sel0 (mux_data_idx_px2_sel1),
2253// .sel1 (mux_data_idx_px2_sel2),
2254// .sel2 (mux_data_idx_px2_sel3),
2255// );
2256
2257l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgnpe__ports_4__stack_10r__width_9 mux_data_idx_px2 // BS & SR 10/28/03
2258 (
2259 .dout (data_idx_px2[8:0]) ,
2260 .din0 (mux_idx2_px2[8:0]), // C1 or modified index
2261 .din1 (mux3_addr_px2[17:9]), // instruction Px2 addr
2262 .din2 (mux3_addr_px2[16:8]),
2263 .din3 (mux3_addr_px2[15:7]),
2264 .sel0 (arb_sel_lkup_stalled_tag_px2), // select diag/tecc/deccck addr
2265 .sel1 (mux_data_idx_px2_sel1),
2266 .sel2 (mux_data_idx_px2_sel2),
2267 .sel3 (mux_data_idx_px2_sel3),
2268 .muxtst(muxtst)
2269 );
2270
2271
2272
2273
2274l2t_arbadr_dp_msff_macro__stack_5r__width_5 ff_ncu_signals // BS & SR 10/28/03
2275 (
2276 .scan_in(ff_ncu_signals_scanin),
2277 .scan_out(ff_ncu_signals_scanout),
2278 .din({ncu_l2t_pm,ncu_l2t_ba01,ncu_l2t_ba23,ncu_l2t_ba45,ncu_l2t_ba67}),
2279 .dout({ncu_l2t_pm_sync,ncu_l2t_ba01_sync,ncu_l2t_ba23_sync,ncu_l2t_ba45_sync,ncu_l2t_ba67_sync}),
2280 .clk(l2clk),
2281 .en(io_cmp_sync_en_r1),
2282 .se(se),
2283 .siclk(siclk),
2284 .soclk(soclk),
2285 .pce_ov(pce_ov),
2286 .stop(stop)
2287 );
2288
2289
2290l2t_arbadr_dp_inv_macro__width_1 inv_ncu_l2t_pm (
2291 .dout (ncu_l2t_pm_sync_n),
2292 .din (ncu_l2t_pm_sync)
2293 );
2294
2295assign arbadr_dirvec_ncu_l2t_pm_n_dist = ncu_l2t_pm_sync_n_ff8;
2296assign arbadr_arbctl_ncu_l2t_pm_n_dist = ncu_l2t_pm_sync_n_ff7;
2297assign arbadr_tagd_ncu_l2t_pm_n_dist = ncu_l2t_pm_sync_n_ff6;
2298assign arbadr_evctag_ncu_l2t_pm_n_dist = ncu_l2t_pm_sync_n_ff5;
2299
2300l2t_arbadr_dp_inv_macro__width_1 inv_ncu_l2t_ba01 (
2301 .dout (ncu_l2t_ba01_sync_n),
2302 .din (ncu_l2t_ba01_sync)
2303 );
2304
2305l2t_arbadr_dp_inv_macro__width_1 inv_ncu_l2t_ba23 (
2306 .dout (ncu_l2t_ba23_sync_n),
2307 .din (ncu_l2t_ba23_sync)
2308 );
2309l2t_arbadr_dp_inv_macro__width_1 inv_ncu_l2t_ba45 (
2310 .dout (ncu_l2t_ba45_sync_n),
2311 .din (ncu_l2t_ba45_sync)
2312 );
2313l2t_arbadr_dp_inv_macro__width_1 inv_ncu_l2t_ba67 (
2314 .dout (ncu_l2t_ba67_sync_n),
2315 .din (ncu_l2t_ba67_sync)
2316 );
2317
2318l2t_arbadr_dp_and_macro__ports_4__width_1 ba01_only_enbld_slice
2319 (.dout (ba01_only_enbld),
2320 .din0 (ncu_l2t_ba01_sync),
2321 .din1 (ncu_l2t_ba23_sync_n),
2322 .din2 (ncu_l2t_ba45_sync_n),
2323 .din3 (ncu_l2t_ba67_sync_n)
2324 );
2325
2326l2t_arbadr_dp_and_macro__ports_4__width_1 ba23_only_enbld_slice
2327 (.dout (ba23_only_enbld),
2328 .din0 (ncu_l2t_ba23_sync),
2329 .din1 (ncu_l2t_ba01_sync_n),
2330 .din2 (ncu_l2t_ba45_sync_n),
2331 .din3 (ncu_l2t_ba67_sync_n)
2332 );
2333l2t_arbadr_dp_and_macro__ports_4__width_1 ba45_only_enbld_slice
2334 (.dout (ba45_only_enbld),
2335 .din0 (ncu_l2t_ba45_sync),
2336 .din1 (ncu_l2t_ba23_sync_n),
2337 .din2 (ncu_l2t_ba01_sync_n),
2338 .din3 (ncu_l2t_ba67_sync_n)
2339 );
2340l2t_arbadr_dp_and_macro__ports_4__width_1 ba67_only_enbld_slice
2341 (.dout (ba67_only_enbld),
2342 .din0 (ncu_l2t_ba67_sync),
2343 .din1 (ncu_l2t_ba23_sync_n),
2344 .din2 (ncu_l2t_ba45_sync_n),
2345 .din3 (ncu_l2t_ba01_sync_n)
2346 );
2347
2348l2t_arbadr_dp_or_macro__ports_3__width_1 or_2banks_enbld_1_slice
2349 (.dout (twobanks_enbld_1),
2350 .din0 (ba01_only_enbld),
2351 .din1 (ba23_only_enbld),
2352 .din2 (ba45_only_enbld)
2353 );
2354
2355l2t_arbadr_dp_or_macro__ports_2__width_1 or_2banks_enbld_slice
2356 (.dout (twobanks_enbld),
2357 .din0 (twobanks_enbld_1),
2358 .din1 (ba67_only_enbld)
2359 );
2360
2361
2362l2t_arbadr_dp_and_macro__ports_4__width_1 ba0123_enbld_slice
2363 (.dout (ba0123_enbld),
2364 .din0 (ncu_l2t_ba01_sync),
2365 .din1 (ncu_l2t_ba23_sync),
2366 .din2 (ncu_l2t_ba45_sync_n),
2367 .din3 (ncu_l2t_ba67_sync_n)
2368 );
2369
2370l2t_arbadr_dp_and_macro__ports_4__width_1 ba2345_enbld_slice
2371 (.dout (ba2345_enbld),
2372 .din0 (ncu_l2t_ba23_sync),
2373 .din1 (ncu_l2t_ba01_sync_n),
2374 .din2 (ncu_l2t_ba45_sync),
2375 .din3 (ncu_l2t_ba67_sync_n)
2376 );
2377l2t_arbadr_dp_and_macro__ports_4__width_1 ba4567_enbld_slice
2378 (.dout (ba4567_enbld),
2379 .din0 (ncu_l2t_ba45_sync),
2380 .din1 (ncu_l2t_ba23_sync_n),
2381 .din2 (ncu_l2t_ba01_sync_n),
2382 .din3 (ncu_l2t_ba67_sync)
2383 );
2384l2t_arbadr_dp_and_macro__ports_4__width_1 ba6701_enbld_slice
2385 (.dout (ba6701_enbld),
2386 .din0 (ncu_l2t_ba67_sync),
2387 .din1 (ncu_l2t_ba23_sync_n),
2388 .din2 (ncu_l2t_ba45_sync_n),
2389 .din3 (ncu_l2t_ba01_sync)
2390 );
2391
2392l2t_arbadr_dp_and_macro__ports_4__width_1 ba2367_enbld_slice
2393 (.dout (ba2367_enbld),
2394 .din0 (ncu_l2t_ba67_sync),
2395 .din1 (ncu_l2t_ba23_sync),
2396 .din2 (ncu_l2t_ba45_sync_n),
2397 .din3 (ncu_l2t_ba01_sync_n)
2398 );
2399l2t_arbadr_dp_and_macro__ports_4__width_1 ba0145_enbld_slice
2400 (.dout (ba0145_enbld),
2401 .din0 (ncu_l2t_ba67_sync_n),
2402 .din1 (ncu_l2t_ba23_sync_n),
2403 .din2 (ncu_l2t_ba45_sync),
2404 .din3 (ncu_l2t_ba01_sync)
2405 );
2406
2407l2t_arbadr_dp_or_macro__ports_3__width_1 or_4banks_enbld_1_slice
2408 (.dout (fourbanks_enbld_1),
2409 .din0 (ba0123_enbld),
2410 .din1 (ba2345_enbld),
2411 .din2 (ba4567_enbld)
2412 );
2413
2414l2t_arbadr_dp_or_macro__ports_3__width_1 or_4banks_enbld_2_slice
2415 (.dout (fourbanks_enbld_2),
2416 .din0 (ba6701_enbld),
2417 .din1 (ba0145_enbld),
2418 .din2 (ba2367_enbld)
2419 );
2420
2421l2t_arbadr_dp_or_macro__ports_2__width_1 or_4banks_enbld_slice
2422 (.dout (fourbanks_enbld),
2423 .din0 (fourbanks_enbld_1),
2424 .din1 (fourbanks_enbld_2)
2425 );
2426
2427l2t_arbadr_dp_and_macro__ports_2__width_1 and_twobanks_true_enbld_slice
2428 (.dout (twobanks_true_enbld),
2429 .din0 (ncu_l2t_pm_sync),
2430 .din1 (twobanks_enbld)
2431 );
2432
2433assign arbadr_dirvec_2bnk_true_enbld_dist = twobanks_true_enbld_ff8;
2434assign arbadr_evctag_2bnk_true_enbld_dist = twobanks_true_enbld_ff7;
2435assign arbadr_arbctl_2bnk_true_enbld_dist = twobanks_true_enbld_ff6;
2436assign arbadr_tagd_2bnk_true_enbld_dist = twobanks_true_enbld_ff5;
2437
2438l2t_arbadr_dp_and_macro__ports_2__width_1 and_fourbanks_true_enbld_slice
2439 (.dout (fourbanks_true_enbld),
2440 .din0 (ncu_l2t_pm_sync),
2441 .din1 (fourbanks_enbld)
2442 );
2443
2444assign arbadr_dirvec_4bnk_true_enbld_dist = fourbanks_true_enbld_ff8;
2445assign arbadr_evctag_4bnk_true_enbld_dist = fourbanks_true_enbld_ff7;
2446assign arbadr_arbctl_4bnk_true_enbld_dist = fourbanks_true_enbld_ff6;
2447assign arbadr_tagd_4bnk_true_enbld_dist = fourbanks_true_enbld_ff5;
2448
2449//assign arbadr_arbdp_tag_idx_px2[8:0] = data_idx_px2[8:0];
2450
2451//buff_macro buff_arbadr_arbdp_tag_idx_px2 (width=9,dbuff=16x)
2452// (
2453// .dout (arbadr_arbdp_tag_idx_px2[8:0]),
2454// .din (data_idx_px2[8:0])
2455// );
2456
2457
2458
2459
2460l2t_arbadr_dp_inv_macro__dinv_16x__width_9 inv_arbadr_arbdp_tag_idx_px2
2461 (
2462 .dout (arbadr_arbdp_tag_idx_px2[8:0]),
2463 .din (data_idx_px2[8:0])
2464 );
2465
2466
2467///////////////////////////////////////////////////////////////////////////
2468// l2t_l2d_set_c2
2469// If an operation is stalled in C1, the C1 and C2 indices are
2470// maintained until the stall is deasserted.
2471//
2472// The set calculation is done with 3 2:1 muxes as follows
2473// mux1: select between a stalled C1 addr ( from C1 op, deccck idx,
2474// tecc idx, diagnostic idx ) and a PX2 operation.
2475// mux2(c2 stall mux): select between the FLOPPED mux1 output C2 idx.
2476//
2477// mux3(bust mux flop): select between bist idx and the output of mux2
2478//
2479// Notice that the C1 and C2 indices are stalled.
2480///////////////////////////////////////////////////////////////////////////
2481l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_3 mux_ncu_partialbank_signals
2482 (
2483 .dout ({mux_ncu_l2t_pm_sync_n,mux_twobanks_true_enbld,mux_fourbanks_true_enbld}),
2484 .din0 ({ncu_l2t_pm_sync_n,twobanks_true_enbld,fourbanks_true_enbld}),
2485 .din1 (3'b0),
2486 .sel0 (mbist_run_r1_n),
2487 .sel1 (mbist_run_r1)
2488 );
2489
2490assign ncu_l2t_pm_sync_n_8[7:0] = {8{mux_ncu_l2t_pm_sync_n}};
2491assign twobanks_true_enbld_8[7:0] = {8{mux_twobanks_true_enbld}};
2492assign fourbanks_true_enbld_8[7:0] = {8{mux_fourbanks_true_enbld}};
2493
2494l2t_arbadr_dp_msff_macro__dmsff_32x__stack_10r__width_9 ff_l2d_idx_c1 // BS & SR 10/28/03
2495 (
2496 .scan_in(ff_l2d_idx_c1_scanin),
2497 .scan_out(ff_l2d_idx_c1_scanout),
2498 .din(data_idx_px2[8:0]),
2499 .clk(l2clk),
2500 .dout(data_idx_c1[8:0]),
2501 .en(1'b1),
2502 .se(se),
2503 .siclk(siclk),
2504 .soclk(soclk),
2505 .pce_ov(pce_ov),
2506 .stop(stop)
2507 );
2508
2509// use a mux flop here to reduce setup.
2510l2t_arbadr_dp_msff_macro__dmsff_32x__stack_4r__width_3 ff_ncu_mux_sel_2 // BS & SR 10/28/03
2511 (
2512 .scan_in(ff_ncu_mux_sel_2_scanin),
2513 .scan_out(ff_ncu_mux_sel_2_scanout),
2514 .din({ncu_l2t_pm_sync_n_8[0],twobanks_true_enbld_8[0],fourbanks_true_enbld_8[0]}),
2515 .clk(l2clk),
2516 .dout({ncu_l2t_pm_sync_n_ff1, twobanks_true_enbld_ff1, fourbanks_true_enbld_ff1}),
2517 .en(1'b1),
2518 .se(se),
2519 .siclk(siclk),
2520 .soclk(soclk),
2521 .pce_ov(pce_ov),
2522 .stop(stop)
2523 );
2524
2525l2t_arbadr_dp_msff_macro__dmsff_32x__stack_4r__width_3 ff_ncu_mux_sel_3 // BS & SR 10/28/03
2526 (
2527 .scan_in(ff_ncu_mux_sel_3_scanin),
2528 .scan_out(ff_ncu_mux_sel_3_scanout),
2529 .din({ncu_l2t_pm_sync_n_8[1],twobanks_true_enbld_8[1],fourbanks_true_enbld_8[1]}),
2530 .clk(l2clk),
2531 .dout({ncu_l2t_pm_sync_n_ff2, twobanks_true_enbld_ff2, fourbanks_true_enbld_ff2}),
2532 .en(1'b1),
2533 .se(se),
2534 .siclk(siclk),
2535 .soclk(soclk),
2536 .pce_ov(pce_ov),
2537 .stop(stop)
2538 );
2539
2540// Following flop needs to drive outside blocks
2541l2t_arbadr_dp_msff_macro__dmsff_32x__stack_12r__width_12 ff_ncu_mux_sel_1 // BS & SR 10/28/03
2542 (
2543 .scan_in(ff_ncu_mux_sel_1_scanin),
2544 .scan_out(ff_ncu_mux_sel_1_scanout),
2545 .din({ncu_l2t_pm_sync_n_8[7:4],twobanks_true_enbld_8[7:4],fourbanks_true_enbld_8[7:4]}),
2546 .clk(l2clk),
2547 .dout({ncu_l2t_pm_sync_n_ff5,ncu_l2t_pm_sync_n_ff6,ncu_l2t_pm_sync_n_ff7,ncu_l2t_pm_sync_n_ff8,
2548 twobanks_true_enbld_ff5,twobanks_true_enbld_ff6,twobanks_true_enbld_ff7,twobanks_true_enbld_ff8,
2549 fourbanks_true_enbld_ff5,fourbanks_true_enbld_ff6,fourbanks_true_enbld_ff7,fourbanks_true_enbld_ff8}),
2550 .en(1'b1),
2551 .se(se),
2552 .siclk(siclk),
2553 .soclk(soclk),
2554 .pce_ov(pce_ov),
2555 .stop(stop)
2556 );
2557
2558l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_sel_c2_stall_idx_c1_inv_slice (
2559 .dout (arb_sel_c2_stall_idx_c1_n),
2560 .din (arb_sel_c2_stall_idx_c1)
2561 );
2562
2563l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_10r__width_9 mux_c2stall // BS & SR 10/28/03
2564 (.dout (stall_idx_c1[8:0] ) ,
2565 .din0(data_idx_c1[8:0]), // idx of C1 instruction
2566 .din1(data_bist_idx_c2[8:0]), // BIST set
2567 .sel0(arb_sel_c2_stall_idx_c1_n), // stalled c2 address is NOT selected
2568 .sel1(arb_sel_c2_stall_idx_c1)); // stalled c2 address is selected
2569
2570// C2 address stall mux.
2571// If a stall is asserted, the C2 address needs to be
2572// retained. THis is
2573
2574l2t_arbadr_dp_inv_macro__dinv_32x__width_1 bist_data_enable_c1_inv_slice (
2575 .dout (bist_data_enable_c1_n),
2576 .din (bist_data_enable_c1)
2577 );
2578
2579
2580l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_10r__width_9 mux_data_idx_c1 // BS & SR 10/28/03
2581 (.dout (data_bist_idx_c1[8:0] ) ,
2582 .din0(stall_idx_c1[8:0]), // idx of C1 instruction
2583 .din1(bist_data_set_c1[8:0]), // BIST set
2584 .sel0(bist_data_enable_c1_n),
2585 .sel1(bist_data_enable_c1));
2586
2587// use a mux flop here to reduce setup.
2588l2t_arbadr_dp_msff_macro__stack_10r__width_9 ff_l2d_idx_c2 // BS & SR 10/28/03
2589 (.din(data_bist_idx_c1[8:0]), .clk(l2clk),
2590 .scan_in(ff_l2d_idx_c2_scanin),
2591 .scan_out(ff_l2d_idx_c2_scanout),
2592 .dout(data_bist_idx_c2[8:0]), .en(1'b1),
2593 .se(se),
2594 .siclk(siclk),
2595 .soclk(soclk),
2596 .pce_ov(pce_ov),
2597 .stop(stop)
2598);
2599
2600//assign l2t_l2d_set_c2 = data_bist_idx_c2 ;
2601//buff_macro buff_l2t_l2d_set_c2 (width=9,stack=9r,dbuff=32x)
2602// (
2603// .dout (l2t_l2d_set_c2[8:0]),
2604// .din (data_bist_idx_c2[8:0])
2605// );
2606
2607l2t_arbadr_dp_msff_macro__dmsff_32x__stack_10r__width_9 ff_l2d_idx_fnl_c2
2608 (
2609 .scan_in(ff_l2d_idx_fnl_c2_scanin),
2610 .scan_out(ff_l2d_idx_fnl_c2_scanout),
2611 .din(data_bist_idx_c1[8:0]),
2612 .clk(l2clk),
2613 .dout(l2t_l2d_set_c2[8:0]),
2614 .en(1'b1),
2615 .se(se),
2616 .siclk(siclk),
2617 .soclk(soclk),
2618 .pce_ov(pce_ov),
2619 .stop(stop)
2620 );
2621
2622
2623
2624///////////////////////////////////////////////////////////////////////
2625// other bits of the tag.
2626///////////////////////////////////////////////////////////////////////
2627
2628// diagnostic wr data
2629// assign tag_diag_wr_data_c2[39:18] = arbdat_arbdata_wr_data_c2[27:6] ; // c2 data.
2630// assign tag_diag_wr_data_c2[5:0] = arbdat_arbdata_wr_data_c2[5:0]; // tag ecc bits.
2631
2632l2t_arbadr_dp_buff_macro__dbuff_16x__stack_28r__width_28 buff_tag_diag_wr_data_c2
2633 (
2634 .dout ({tag_diag_wr_data_c2[39:18],tag_diag_wr_data_c2[5:0]}),
2635 .din (arbdat_arbdata_wr_data_c2[27:0])
2636 );
2637
2638
2639
2640l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_28r__width_28 mux_tag_acc_data_px2
2641 (.dout(tag_acc_data_px2[27:0]) ,
2642 .din0(tecc_corr_tag_c2[27:0]), // corr tecc tag.
2643 .din1({tag_diag_wr_data_c2[39:18],tag_diag_wr_data_c2[5:0]}), // diagnostic write tag.
2644 .sel0(arb_inc_tag_ecc_cnt_c3_n_n), // tecc active
2645 .sel1(arb_inc_tag_ecc_cnt_c3_n)); // tecc not active
2646
2647//*******************************************************************
2648// Changes start here.
2649// changed sel0 and sel1 ;
2650l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_diag_or_tecc_write_px2_inv_slice (
2651 .dout (arb_diag_or_tecc_write_px2_n),
2652 .din (arb_diag_or_tecc_write_px2)
2653 );
2654
2655l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_22r__width_22 mux_arbdp_addr_c1_1_fnl
2656 (.dout (arbdp_addr_c1_1_fnl[39:18]) ,
2657 .din0(arbdp_addr_c1_1[39:18]), // original tag from core/siu/mbf/filbuf, all banks enabled
2658 .din1(arbdp_addr_c1_1[38:17]), // 1 bit shifted tag in case of 4 banks enabled
2659 .din2(arbdp_addr_c1_1[37:16]), // 2 bit shifted tag in case of 2 banks enabled
2660 .sel0(ncu_l2t_pm_sync_n_ff2),
2661 .sel1(fourbanks_true_enbld_ff2),
2662 .sel2(twobanks_true_enbld_ff2)
2663 );
2664
2665
2666l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_28r__width_28 mux_tag_stalled_data
2667 (
2668 .dout (mux2_tagdata_px2[27:0]) ,
2669 .din0 (tag_acc_data_px2[27:0]), // corr tecc tag or diag data
2670 .din1 ({arbdp_addr_c1_1_fnl[39:18],arbdp_addr_c1_1[5:0]}), // c1 tag
2671 .sel0 (arb_diag_or_tecc_write_px2), // diag ortecc or deccck active
2672 .sel1 (arb_diag_or_tecc_write_px2_n)
2673 ); // no diag or tecc access.
2674
2675//Added this mux
2676l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_sel_way_px2_inv_slice (
2677 .dout (arb_sel_way_px2_n),
2678 .din (arb_sel_way_px2)
2679 );
2680
2681// BS 03/25/04 for partial bank/core modes support
2682// fill tag shift for update
2683// On a fill related tag update, the tag needs to be shifted also,
2684// however the ecc would be correct as it is gnerated off of the
2685// miss address in C1 which had been shifted properly already
2686// before tag lookup. hence we do not need to change evctag_addr_px2[5:0]
2687// also corr tecc tag or diag data should go through unmodified to the
2688// tag array.
2689
2690l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_22r__width_22 mux_evctag_addr_fnl_px2
2691 (.dout (evctag_addr_fnl_px2[39:18]) ,
2692 .din0(evctag_addr_px2[39:18]), // original tag from core/siu/mbf/filbuf, all banks enabled
2693 .din1(evctag_addr_px2[38:17]), // 1 bit shifted tag in case of 4 banks enabled
2694 .din2(evctag_addr_px2[37:16]), // 2 bit shifted tag in case of 2 banks enabled
2695 .sel0(ncu_l2t_pm_sync_n_ff2),
2696 .sel1(fourbanks_true_enbld_ff2),
2697 .sel2(twobanks_true_enbld_ff2)
2698 );
2699
2700
2701l2t_arbadr_dp_buff_macro__dbuff_8x__stack_28r__width_28 buff_arbadr_tag_wrdata_px2
2702 (
2703 .dout (arbadr_tag_wrdata_px2[27:0]),
2704 .din (arbadr_tag_wrdata_px2_unbuff[27:0])
2705 );
2706l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_28r__width_28 mux_tag_wrdata_px2
2707 (
2708 .dout (arbadr_tag_wrdata_px2_unbuff[27:0]) ,
2709 .din0 (mux2_tagdata_px2[27:0]), // corr tecc tag or diag data
2710 .din1 ({evctag_addr_fnl_px2[39:18],evctag_addr_px2[5:0]}), // px2 fill tag
2711 .sel0 (arb_sel_way_px2_n), // diag ortecc or deccck active
2712 .sel1 (arb_sel_way_px2) // no diag or tecc access.
2713 );
2714
2715// LKUP addr.
2716// changed in0
2717
2718l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_22r__width_22 mux_arbdp_tagdata_tmp_px2 // int 5.0 changes
2719 (
2720 .dout (arbadr_arbdp_tagdata_tmp_px2[27:6]) ,
2721 .din0 (arbdp_addr_c1_1[39:18]), // c1 tag
2722 .din1 (mux3_addr_px2[39:18]), // tag from other srcs
2723 .sel0 (arb_sel_lkup_stalled_tag_px2), // stalled tag sel.
2724 .sel1 (arb_sel_lkup_stalled_tag_px2_n) // new tag sel
2725 );
2726
2727// BS 03/25/04 for partial bank/core modes support
2728// tag shift for lookup
2729
2730l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_22r__width_22 mux_arbdp_tagdata_px2
2731 (
2732 .dout (arbadr_arbdp_tagdata_px2[27:6]) ,
2733 .din0(arbadr_arbdp_tagdata_tmp_px2[27:6]), // original tag from core/siu/mbf/filbuf, all banks enabled
2734 .din1({arbadr_arbdp_tagdata_tmp_px2[26:6],mux4_addr_px2[17]}), // 1 bit shifted tag in case of 4 banks enabled
2735 .din2({arbadr_arbdp_tagdata_tmp_px2[25:6],mux4_addr_px2[17:16]}), // 2 bit shifted tag in case of 2 banks enabled
2736 .din3(mbist_tag_lkup_addr[27:6]), // mbist lkup data
2737 .sel0(ncu_l2t_pm_sync_n_ff2),
2738 .sel1(fourbanks_true_enbld_ff2),
2739 .sel2(twobanks_true_enbld_ff2),
2740 .muxtst(muxtst),
2741 .test(test)
2742// .sel3(mbist_run_r1)
2743 );
2744
2745
2746// Changes end here.
2747//*******************************************************************
2748
2749// the whole tag for CAMMIng the miss buffer.
2750
2751l2t_arbadr_dp_buff_macro__dbuff_32x__width_40 buff_arbdp_addr_c1_1
2752 (
2753 .dout (arbdp_addr_c1_1[39:0]),
2754 .din (arbdp_addr_c1_unbuff[39:0])
2755 );
2756
2757l2t_arbadr_dp_buff_macro__dbuff_32x__width_40 buff_arbdp_addr_c1_2
2758 (
2759 .dout (arbdp_addr_c1_2[39:0]),
2760 .din (arbdp_addr_c1_unbuff[39:0])
2761 );
2762
2763
2764l2t_arbadr_dp_buff_macro__dbuff_32x__width_40 buff_arbdp_addr_c1_3
2765 (
2766 .dout (arbdp_addr_c1_3[39:0]),
2767 .din (arbdp_addr_c1_unbuff[39:0])
2768 );
2769
2770
2771
2772l2t_arbadr_dp_msff_macro__dmsff_32x__stack_40r__width_40 ff_inst_addr_c1
2773 (
2774 .scan_in(ff_inst_addr_c1_scanin),
2775 .scan_out(ff_inst_addr_c1_scanout),
2776 .din (mux4_addr_px2[39:0]),
2777 .clk (l2clk),
2778 .dout (arbdp_addr_c1_unbuff[39:0]),
2779 .en (1'b1),
2780 .se(se),
2781 .siclk(siclk),
2782 .soclk(soclk),
2783 .pce_ov(pce_ov),
2784 .stop(stop)
2785 );
2786
2787
2788// assign arbadr_arbdp_addr5to4_c1 = arbdp_addr_c1[5:4] ; // to arb for col offset stall calculation.
2789// assign arbadr_arbdp_addr3to2_c1 = arbdp_addr_c1[3:2] ;
2790// assign arbadr_arbdp_ioaddr_c1 = arbdp_addr_c1[39:32] ; // to arb for diag acc decode
2791// assign arbadr_arbdp_word_addr_c1 = arbdp_addr_c1[1:0] ; // pst decode in arbdec
2792
2793
2794l2t_arbadr_dp_msff_macro__dmsff_32x__minbuff_1__stack_40r__width_40 ff_addr_c2
2795 (.din(arbdp_addr_c1_1[39:0]), .clk(l2clk),
2796 .scan_in(ff_addr_c2_scanin),
2797 .scan_out(ff_addr_c2_scanout),
2798 .dout(arbdp_addr_c2[39:0]), .en(1'b1),
2799 .se(se),
2800 .siclk(siclk),
2801 .soclk(soclk),
2802 .pce_ov(pce_ov),
2803 .stop(stop)
2804 );
2805
2806
2807// assign arbadr_arbdp_addr87_c2 = arbdp_addr_c2[8:7]; // BS 03/25/04 for partial bank/core modes support
2808// assign arbadr_arbaddr_addr22_c2 = arbdp_addr_c2[22] ;
2809// assign arbadr_arbdp_addr5to4_c2 = arbdp_addr_c2[5:4] ;
2810// assign arbadr_arbdp_diag_wr_way_c2 = arbdp_addr_c2[21:18] ;// diag wr way
2811
2812assign arbadr_arbdp_ioaddr_c1[39:32] = arbdp_addr_c1_1[39:32];
2813
2814l2t_arbadr_dp_buff_macro__dbuff_32x__stack_23r__width_15 buff_arbadr_arbaddr_addr_c2
2815 (
2816 .dout ({arbadr_arbdp_addr5to4_c1[1:0],arbadr_arbdp_addr3to2_c1[1:0],
2817 arbadr_arbdp_ioaddr_c1_unused[39:32],
2818 arbadr_arbdp_addr87_c2,arbadr_arbaddr_addr22_c2}),
2819 .din ({arbdp_addr_c1_1[5:4],arbdp_addr_c1_1[3:2],arbdp_addr_c1_1[39:32],
2820 arbdp_addr_c2[8:7],arbdp_addr_c2[22]})
2821 );
2822
2823// The following signal indicates that the access is issued to
2824// addr0 of a cacheline.
2825
2826
2827// assign arbadr_arbdp_addr_start_c2 = ( arbdp_addr_c2[5:0] == 6'b0 ) ;
2828
2829l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 arbadr_arbdp_addr_start_c2_cmptr
2830 (
2831 .din0 ({2'b0,6'b0}),
2832 .din1 ({2'b0,arbdp_addr_c2[5:0]}),
2833 .dout (arbadr_arbdp_addr_start_c2)
2834 );
2835
2836l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c3
2837 (.din(arbdp_addr_c2[39:0]), .clk(l2clk),
2838 .scan_in(ff_addr_c3_scanin),
2839 .scan_out(ff_addr_c3_scanout),
2840 .dout(arbdp_addr_c3[39:0]), .en(1'b1),
2841 .se(se),
2842 .siclk(siclk),
2843 .soclk(soclk),
2844 .pce_ov(pce_ov),
2845 .stop(stop)
2846);
2847
2848//assign arbadr_arbdp_addr5to4_c3 = arbdp_addr_c3[5:4] ; // used in arb for dir cam
2849//assign arbadr_arbaddr_idx_c3 = arbdp_addr_c3[17:7] ; // for vuad array writes.
2850
2851l2t_arbadr_dp_buff_macro__dbuff_32x__stack_15r__width_15 buff_arbadr_arbdp_addr_c1c2comp_c1c3cmp_c1
2852 (
2853 .dout ({arbadr_arbdp_addr5to4_c3[1:0],arbadr_arbaddr_idx_c3[10:0],
2854 arbadr_arbdp_addr_c1c2comp_c1,arbadr_arbdp_addr_c1c3comp_c1}),
2855 .din ({arbdp_addr_c3[5:4],arbdp_addr_c3[17:7],
2856 arbadr_arbdp_addr_c1c2comp_c1_unbuff,arbadr_arbdp_addr_c1c3comp_c1_unbuff})
2857 );
2858
2859
2860
2861
2862
2863
2864////// POST_4.1
2865assign arbadr_arbdp_addr11to4_c3[7:0] = arbdp_addr_c3[11:4] ;
2866
2867//assign arbadr_arbdp_dbg_addr_c3 = {arbdp_addr_c3[5:2] };
2868
2869l2t_arbadr_dp_msff_macro__minbuff_1__stack_40r__width_40 ff_addr_c4
2870 (.din(arbdp_addr_c3[39:0]), .clk(l2clk),
2871 .scan_in(ff_addr_c4_scanin),
2872 .scan_out(ff_addr_c4_scanout),
2873 .dout(arbdp_addr_c4[39:0]), .en(1'b1),
2874 .se(se),
2875 .siclk(siclk),
2876 .soclk(soclk),
2877 .pce_ov(pce_ov),
2878 .stop(stop)
2879);
2880
2881// address for CAMMing the directory. i.e. lkup key
2882// wr data into the directory.
2883// The evict addr is muxed into this value in tagd.
2884
2885l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_imiss_hit_c4_inv_slice (
2886 .dout (arb_imiss_hit_c4_n),
2887 .din (arb_imiss_hit_c4)
2888 );
2889
2890l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_33r__width_33 mux_tmp_cam_addr_c3
2891 ( .dout (arbadr_dir_cam_addr_c3[39:7]),
2892 .din0(arbdp_addr_c3[39:7]), .din1(arbdp_addr_c4[39:7]),
2893 .sel0(arb_imiss_hit_c4_n), .sel1(arb_imiss_hit_c4));
2894
2895l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c5
2896 (
2897 .scan_in(ff_addr_c5_scanin),
2898 .scan_out(ff_addr_c5_scanout),
2899 .din(arbdp_addr_c4[39:0]), .clk(l2clk),
2900 .dout(arbdp_addr_c5[39:0]), .en(1'b1),
2901 .se(se),
2902 .siclk(siclk),
2903 .soclk(soclk),
2904 .pce_ov(pce_ov),
2905 .stop(stop)
2906);
2907
2908// BS 03/11/04 extra cycle for mem access
2909
2910l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c52
2911 (
2912 .scan_in(ff_addr_c52_scanin),
2913 .scan_out(ff_addr_c52_scanout),
2914 .din(arbdp_addr_c5[39:0]), .clk(l2clk),
2915 .dout(arbdp_addr_c52[39:0]), .en(1'b1),
2916 .se(se),
2917 .siclk(siclk),
2918 .soclk(soclk),
2919 .pce_ov(pce_ov),
2920 .stop(stop)
2921);
2922
2923l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c6
2924 (.din(arbdp_addr_c52[39:0]), .clk(l2clk),
2925 .scan_in(ff_addr_c6_scanin),
2926 .scan_out(ff_addr_c6_scanout),
2927 .dout(arbdp_addr_c6[39:0]), .en(1'b1),
2928 .se(se),
2929 .siclk(siclk),
2930 .soclk(soclk),
2931 .pce_ov(pce_ov),
2932 .stop(stop)
2933);
2934
2935// assign arbadr_arbdp_word_addr_c6 = arbdp_addr_c6[36:32] ;// word address to csr ctl.
2936// assign arbadr_arbdp_waddr_c6 = arbdp_addr_c6[3:2] ; // word address tpo
2937// assign arbadr_arbdp_rdmat_addr_c6 = arbdp_addr_c6[5:2] ; // requrired in rdma state logic.
2938// assign arbadr_arbdp_oque_l1_index_c7[11:6] = {1'b0,arbdp_addr_c7[10:6]} ; // idx bits to oque
2939// assign arbadr_dirvec_addr3_c7_tmp = arbdp_addr_c7[3] ; // Address bit 3, BS and SR 11/12/03 N2 Xbar Packet format change
2940
2941// debug related changes
2942// assign arbadr_csr_debug_addr[33:2] = arbdp_addr_c6[33:2];
2943
2944l2t_arbadr_dp_buff_macro__dbuff_32x__stack_32r__width_32 buff_arbadr_csr_debug_addr
2945 (
2946 .dout (arbadr_csr_debug_addr[33:2]),
2947 .din (arbdp_addr_c6[33:2])
2948 );
2949
2950l2t_arbadr_dp_buff_macro__dbuff_32x__stack_18r__width_18 buff_arbdp_addr_c6
2951 (
2952 .dout ({arbadr_arbdp_word_addr_c6[4:0],arbadr_arbdp_waddr_c6[1:0],
2953 arbadr_arbdp_rdmat_addr_c6[5:2], arbadr_arbdp_oque_l1_index_c7[11:6],
2954 arbadr_dirvec_addr3_c7_tmp}),
2955 .din ({arbdp_addr_c6[36:32],arbdp_addr_c6[3:2],arbdp_addr_c6[5:2],
2956 1'b0,arbdp_addr_c7[10:6],arbdp_addr_c7[3]})
2957 );
2958
2959// BS and SR 12/22/03, store ack generation for diagnostic store
2960
2961l2t_arbadr_dp_inv_macro__dinv_32x__width_1 inv_sel_diag_store_data_c8
2962 (
2963 .dout (sel_diag_store_data_c7_n ),
2964 .din (sel_diag_store_data_c7 )
2965 );
2966
2967l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_1r__width_1 mux_st_ack_addr3
2968 (
2969 .dout (arbadr_dirvec_addr3_c7),
2970 .din0 (arbadr_dirvec_addr3_c8),
2971 .din1 (arbadr_dirvec_addr3_c7_tmp),
2972 .sel0 (sel_diag_store_data_c8), // for diagnostic store ack cases
2973 .sel1 (sel_diag_store_data_c8_n) // for default cases
2974 );
2975
2976
2977assign arbadr_arbdp_byte_addr_c6 = arbdp_addr_c6[2:0] ; // to arbdec for ctag generation, Phase 2 : SIU inteface and packet format change 2/7/04
2978
2979
2980l2t_arbadr_dp_msff_macro__dmsff_32x__stack_40r__width_40 ff_addr_c7
2981 (.din(arbdp_addr_c6[39:0]), .clk(l2clk),
2982 .scan_in(ff_addr_c7_scanin),
2983 .scan_out(ff_addr_c7_scanout),
2984 .dout(arbdp_addr_c7[39:0]), .en(1'b1),
2985 .se(se),
2986 .siclk(siclk),
2987 .soclk(soclk),
2988 .pce_ov(pce_ov),
2989 .stop(stop)
2990);
2991
2992// assign arbadr_arbdp_inst_byte_addr_c7[2:0] = arbdp_addr_c7[2:0] ; // byte address to arb.
2993// assign arbadr_arbdp_addr22_c7 = arbdp_addr_c7[22] ; // diagnostic data word addr.
2994// assign arbadr_arbdp_line_addr_c7[5:4] = arbdp_addr_c7[5:4] ;// required by oque but pipe stage may change
2995// assign arbadr_addr2_c8 = arbdp_addr_c8[2] ; // for cas compare.
2996
2997l2t_arbadr_dp_buff_macro__dbuff_32x__stack_6r__width_2 buff_arbdp_addr_c7_misc
2998 (
2999 .dout ({arbadr_arbdp_addr22_c7,arbadr_addr2_c8}),
3000 .din ({arbdp_addr_c7[22],arbdp_addr_c8[2]})
3001 );
3002
3003//assign arbadr_arbdp_line_addr_c7[5:4] = arbdp_addr_c7[5:4];
3004assign arbadr_arbdp_line_addr_c6[5:4] = arbdp_addr_c6[5:4];
3005
3006
3007l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c8
3008 (.din(arbdp_addr_c7[39:0]), .clk(l2clk),
3009 .scan_in(ff_addr_c8_scanin),
3010 .scan_out(ff_addr_c8_scanout),
3011 .dout(arbdp_addr_c8[39:0]), .en(1'b1),
3012 .se(se),
3013 .siclk(siclk),
3014 .soclk(soclk),
3015 .pce_ov(pce_ov),
3016 .stop(stop)
3017);
3018
3019
3020l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c9
3021 (.din(arbdp_addr_c8[39:0]), .clk(l2clk),
3022 .scan_in(ff_addr_c9_scanin),
3023 .scan_out(ff_addr_c9_scanout),
3024 .dout(arbdp_addr_c9[39:0]), .en(1'b1),
3025 .se(se),
3026 .siclk(siclk),
3027 .soclk(soclk),
3028 .pce_ov(pce_ov),
3029 .stop(stop)
3030);
3031
3032l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c10
3033 (.din(arbdp_addr_c9[39:0]), .clk(l2clk),
3034 .scan_in(ff_addr_c10_scanin),
3035 .scan_out(ff_addr_c10_scanout),
3036 .dout(arbdp_addr_c10[39:0]), .en(1'b1),
3037 .se(se),
3038 .siclk(siclk),
3039 .soclk(soclk),
3040 .pce_ov(pce_ov),
3041 .stop(stop)
3042);
3043
3044l2t_arbadr_dp_msff_macro__stack_40r__width_40 ff_addr_c11
3045 (.din(arbdp_addr_c10[39:0]), .clk(l2clk),
3046 .scan_in(ff_addr_c11_scanin),
3047 .scan_out(ff_addr_c11_scanout),
3048 .dout(arbdp_addr_c11[39:0]), .en(1'b1),
3049 .se(se),
3050 .siclk(siclk),
3051 .soclk(soclk),
3052 .pce_ov(pce_ov),
3053 .stop(stop)
3054);
3055
3056///////////////////////////////////////////////////
3057// Addr to csr block is the address of a ld in C9
3058// or an imiss in C10
3059///////////////////////////////////////////////////
3060
3061l2t_arbadr_dp_inv_macro__dinv_32x__width_1 arb_imiss_hit_c10_inv_slice
3062 (
3063 .dout (arb_imiss_hit_c10_n),
3064 .din (arb_imiss_hit_c10)
3065 );
3066
3067
3068l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_36r__width_36 mux_arbadr_arbdp_csr_addr_c9
3069 ( .dout (arbadr_arbdp_csr_addr_c9[39:4]),
3070 .din0(arbdp_addr_c9[39:4]), .din1(arbdp_addr_c10[39:4]),
3071 .sel0(arb_imiss_hit_c10_n), .sel1(arb_imiss_hit_c10));
3072
3073
3074///////////////////////////////////////////////////
3075// Addr of an ld64 instruction is staged till C11
3076///////////////////////////////////////////////////
3077
3078l2t_arbadr_dp_msff_macro__stack_34r__width_34 ff_arbdp_addr_c12
3079 (.din(arbdp_addr_c11[39:6]), .clk(l2clk),
3080 .scan_in(ff_arbdp_addr_c12_scanin),
3081 .scan_out(ff_arbdp_addr_c12_scanout),
3082 .dout(arbadr_rdmard_addr_c12[39:6]), .en(tag_rd64_complete_c11),
3083 .se(se),
3084 .siclk(siclk),
3085 .soclk(soclk),
3086 .pce_ov(pce_ov),
3087 .stop(stop)
3088);
3089
3090// B.S 05/02/05 : fix for bug 93991 :
3091// c1c2 cmp and c1c3 cmp have to be generated taking partial core/bank mode into account
3092
3093
3094l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_32r__width_31 mux_arbdp_c1_pbnk
3095 (.dout (arbadr_addr_c1_pbnk[30:0]) ,
3096 .din0(arbdp_addr_c1_3[39:9]), // original PA from core/siu/mbf/filbuf, all banks enabled
3097 .din1(arbdp_addr_c1_3[38:8]), // 1 bit shifted PA in case of 4 banks enabled
3098 .din2(arbdp_addr_c1_3[37:7]), // 2 bit shifted PA in case of 2 banks enabled
3099 .sel0(ncu_l2t_pm_sync_n_ff1),
3100 .sel1(fourbanks_true_enbld_ff1),
3101 .sel2(twobanks_true_enbld_ff1)
3102 );
3103
3104
3105l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_32r__width_31 mux_arbdp_c2_pbnk
3106 (.dout (arbadr_addr_c2_pbnk[30:0]) ,
3107 .din0(arbdp_addr_c2[39:9]), // original PA from core/siu/mbf/filbuf, all banks enabled
3108 .din1(arbdp_addr_c2[38:8]), // 1 bit shifted PA in case of 4 banks enabled
3109 .din2(arbdp_addr_c2[37:7]), // 2 bit shifted PA in case of 2 banks enabled
3110 .sel0(ncu_l2t_pm_sync_n_ff1),
3111 .sel1(fourbanks_true_enbld_ff1),
3112 .sel2(twobanks_true_enbld_ff1)
3113 );
3114
3115
3116l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_32r__width_31 mux_arbdp_c3_pbnk
3117 (.dout (arbadr_addr_c3_pbnk[30:0]) ,
3118 .din0(arbdp_addr_c3[39:9]), // original PA from core/siu/mbf/filbuf, all banks enabled
3119 .din1(arbdp_addr_c3[38:8]), // 1 bit shifted PA in case of 4 banks enabled
3120 .din2(arbdp_addr_c3[37:7]), // 2 bit shifted PA in case of 2 banks enabled
3121 .sel0(ncu_l2t_pm_sync_n_ff1),
3122 .sel1(fourbanks_true_enbld_ff1),
3123 .sel2(twobanks_true_enbld_ff1)
3124 );
3125
3126
3127l2t_arbadr_dp_cmp_macro__dcmp_8x__width_32 mbf_bypass_cmp1
3128 ( .din0({1'b0,arbadr_addr_c2_pbnk[30:0]}),
3129 .din1({1'b0,arbadr_addr_c1_pbnk[30:0]}),
3130 .dout(arbadr_arbdp_addr_c1c2comp_c1_unbuff)
3131 );
3132
3133l2t_arbadr_dp_cmp_macro__dcmp_8x__width_32 mbf_bypass_cmp2
3134 ( .din0({1'b0,arbadr_addr_c3_pbnk[30:0]}),
3135 .din1({1'b0,arbadr_addr_c1_pbnk[30:0]}),
3136 .dout(arbadr_arbdp_addr_c1c3comp_c1_unbuff)
3137 );
3138
3139
3140
3141// INDEX COMPARATORS for VUAD bypass
3142
3143// B.S : 03/26/05
3144// Flop stall_addr_idx_c1 till c5 , these will be used to detect index matches
3145// between wr and rd of vuad to trigger vuad bypass.
3146//assign arbadr_idx_c1c2comp_c1 = ( stall_addr_idx_c2[8:0] == stall_addr_idx_c1[8:0] ) ;
3147//assign arbadr_idx_c1c3comp_c1 = ( stall_addr_idx_c3[8:0] == stall_addr_idx_c1[8:0] ) ;
3148//assign arbadr_idx_c1c4comp_c1 = ( stall_addr_idx_c4[8:0] == stall_addr_idx_c1[8:0] ) ;
3149//assign arbadr_idx_c1c5comp_c1 = ( stall_addr_idx_c5[8:0] == stall_addr_idx_c1[8:0] ) ;
3150
3151l2t_arbadr_dp_cmp_macro__dcmp_8x__width_12 vuad_bypass_cmp1
3152 ( .din0({3'b00,stall_addr_idx_c2[8:0]}),
3153 .din1({3'b00,stall_addr_idx_c1_2[8:0]}),
3154 .dout(arbadr_idx_c1c2comp_c1_unbuff)
3155 );
3156
3157
3158l2t_arbadr_dp_buff_macro__dbuff_48x__width_2 buff_c1c2andc1c3_slice
3159 (
3160 .dout ({arbadr_misbuf_idx_c1c2comp_c1,arbadr_misbuf_idx_c1c3comp_c1}),
3161 .din ({arbadr_idx_c1c2comp_c1_unbuff,arbadr_idx_c1c3comp_c1_unbuff})
3162 );
3163
3164
3165l2t_arbadr_dp_inv_macro__dinv_32x__width_4 inv_signals_to_vuad
3166 (
3167 .dout ({arbadr_idx_c1c2comp_c1_n,arbadr_idx_c1c3comp_c1_n,
3168 arbadr_idx_c1c4comp_c1_n,arbadr_idx_c1c5comp_c1_n}),
3169 .din ({arbadr_idx_c1c2comp_c1_unbuff,arbadr_idx_c1c3comp_c1_unbuff,
3170 arbadr_idx_c1c4comp_c1_unbuff,arbadr_idx_c1c5comp_c1_unbuff})
3171 );
3172
3173
3174
3175
3176
3177l2t_arbadr_dp_cmp_macro__dcmp_8x__width_12 vuad_bypass_cmp2
3178 ( .din0({3'b00,stall_addr_idx_c3[8:0]}),
3179 .din1({3'b00,stall_addr_idx_c1_2[8:0]}),
3180 .dout(arbadr_idx_c1c3comp_c1_unbuff)
3181 );
3182l2t_arbadr_dp_cmp_macro__dcmp_8x__width_12 vuad_bypass_cmp3
3183 ( .din0({3'b00,stall_addr_idx_c4[8:0]}),
3184 .din1({3'b00,stall_addr_idx_c1_3[8:0]}),
3185 .dout(arbadr_idx_c1c4comp_c1_unbuff)
3186 );
3187l2t_arbadr_dp_cmp_macro__dcmp_8x__width_12 vuad_bypass_cmp4
3188 ( .din0({3'b00,stall_addr_idx_c5[8:0]}),
3189 .din1({3'b00,stall_addr_idx_c1_3[8:0]}),
3190 .dout(arbadr_idx_c1c5comp_c1_unbuff)
3191 );
3192
3193
3194
3195///////////////////////////////////////////////
3196// bypassing of wb_write_data
3197// required for generation
3198// of wb hit.
3199// evicted tag is written into the WBB in C5.
3200// The operation in C2 in that cycle will have
3201// to see the effect of the wb write. Hence the
3202// C4 address being written into the tag is compared
3203// with the address of the instruction in C1.
3204//////////////////////////////////////////////
3205//
3206// assign evict_addr_c4[39:18] = tagd_evict_tag_orig_c4[21:0] ;
3207// assign evict_addr_c4[17:8] = arbdp_addr_c4[17:8] ;
3208//
3209
3210// fix for bug 93448 : tag read from tag array on evict needs to be shifted around to
3211// original address before being sent to MCU
3212
3213l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_24r__width_24 mux_tagd_evict_addr_39_16_c4
3214 (
3215 .dout (tagd_evct_addr_39_16_c4[23:0]),
3216 .din0({tagd_evict_tag_c4[`TAG_WIDTH-1:6],arbdp_addr_c4[17:16]}), // original idx , all banks enabled
3217 .din1({1'b0,tagd_evict_tag_c4[`TAG_WIDTH-1:6],arbdp_addr_c4[16]}), // 1 bit shifted idx for 4 banks enabled
3218 .din2({2'b0,tagd_evict_tag_c4[`TAG_WIDTH-1:6]}), //2 bit shifted idx for 2 banks enabled
3219 .sel0(ncu_l2t_pm_sync_n_ff2),
3220 .sel1(fourbanks_true_enbld_ff2),
3221 .sel2(twobanks_true_enbld_ff2)
3222 );
3223
3224
3225l2t_arbadr_dp_buff_macro__dbuff_16x__stack_33r__width_33 buff_evict_addr_c4
3226 (
3227 .dout (evict_addr_c4[39:7]),
3228 .din ({tagd_evct_addr_39_16_c4[23:0],arbdp_addr_c4[15:7]})
3229 );
3230
3231// assign arbadr_c1_addr_eq_wb_c4 = (evict_addr_c4[39:8] == arbdp_addr_c1[39:8]);
3232
3233// B.S 05/15/05 : Fix for bug 94724. Since in partial bank mode, we can have index starting
3234// from PA[7] , we need to compare PA[39:7] instead of PA[39:8].
3235
3236l2t_arbadr_dp_cmp_macro__dcmp_8x__dcmp_8x__width_32 cmpc4c1
3237 ( .din0(arbdp_addr_c1_3[39:8]),
3238 .din1(evict_addr_c4[39:8]),
3239 .dout(arbadr_c1_addr_eq_wb_c4_unbuff_1)
3240 );
3241
3242l2t_arbadr_dp_xnor_macro__dxnor_8x__ports_2__width_1 xnor_bit7 (
3243 .dout(arbadr_c1_addr_eq_wb_c4_unbuff_2),
3244 .din0(arbdp_addr_c1_3[7]),
3245 .din1(evict_addr_c4[7])
3246);
3247
3248l2t_arbadr_dp_and_macro__ports_2__width_1 arbadr_c1_addr_eq_wb_c4_unbuff_macro (
3249 .dout(arbadr_c1_addr_eq_wb_c4_unbuff),
3250 .din0(arbadr_c1_addr_eq_wb_c4_unbuff_1),
3251 .din1(arbadr_c1_addr_eq_wb_c4_unbuff_2)
3252);
3253
3254
3255
3256l2t_arbadr_dp_buff_macro__dbuff_32x__stack_1r__width_1 buff_arbadr_c1_addr_eq_wb_c4_buf
3257 (
3258 .dout (arbadr_c1_addr_eq_wb_c4),
3259 .din (arbadr_c1_addr_eq_wb_c4_unbuff)
3260 );
3261
3262
3263// fixscan start:
3264assign ff_tagd_evict_tag_c4_scanin = scan_in ;
3265assign ff_tecc_corr_tag_c2_scanin = ff_tagd_evict_tag_c4_scanout;
3266assign ff_mux3_bufsel_px2_scanin = ff_tecc_corr_tag_c2_scanout;
3267assign ff_stall_addr_idx_c1_unbuff_scanin = ff_mux3_bufsel_px2_scanout;
3268assign ff_l2t_mb2_wdata_scanin = ff_stall_addr_idx_c1_unbuff_scanout;
3269assign ff_cam_mbist_datain_reg_scanin = ff_l2t_mb2_wdata_scanout ;
3270assign ff_data_ecc_idx_scanin = ff_cam_mbist_datain_reg_scanout;
3271assign ff_bist_vuad_idx_px2_scanin = ff_data_ecc_idx_scanout ;
3272assign ff_idx_hold_c2_scanin = ff_bist_vuad_idx_px2_scanout;
3273assign ff_stall_addr_idx_c2to5_scanin = ff_idx_hold_c2_scanout ;
3274assign ff_ncu_signals_scanin = ff_stall_addr_idx_c2to5_scanout;
3275assign ff_l2d_idx_c1_scanin = ff_ncu_signals_scanout ;
3276assign ff_ncu_mux_sel_2_scanin = ff_l2d_idx_c1_scanout ;
3277assign ff_ncu_mux_sel_3_scanin = ff_ncu_mux_sel_2_scanout ;
3278assign ff_ncu_mux_sel_1_scanin = ff_ncu_mux_sel_3_scanout ;
3279assign ff_l2d_idx_c2_scanin = ff_ncu_mux_sel_1_scanout ;
3280assign ff_l2d_idx_fnl_c2_scanin = ff_l2d_idx_c2_scanout ;
3281assign ff_inst_addr_c1_scanin = ff_l2d_idx_fnl_c2_scanout;
3282assign ff_addr_c2_scanin = ff_inst_addr_c1_scanout ;
3283assign ff_addr_c3_scanin = ff_addr_c2_scanout ;
3284assign ff_addr_c4_scanin = ff_addr_c3_scanout ;
3285assign ff_addr_c5_scanin = ff_addr_c4_scanout ;
3286assign ff_addr_c52_scanin = ff_addr_c5_scanout ;
3287assign ff_addr_c6_scanin = ff_addr_c52_scanout ;
3288assign ff_addr_c7_scanin = ff_addr_c6_scanout ;
3289assign ff_addr_c8_scanin = ff_addr_c7_scanout ;
3290assign ff_addr_c9_scanin = ff_addr_c8_scanout ;
3291assign ff_addr_c10_scanin = ff_addr_c9_scanout ;
3292assign ff_addr_c11_scanin = ff_addr_c10_scanout ;
3293assign ff_arbdp_addr_c12_scanin = ff_addr_c11_scanout ;
3294assign scan_out = ff_arbdp_addr_c12_scanout;
3295// fixscan end:
3296endmodule
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306// any PARAMS parms go into naming of macro
3307
3308module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_30r__width_28 (
3309 din,
3310 clk,
3311 en,
3312 se,
3313 scan_in,
3314 siclk,
3315 soclk,
3316 pce_ov,
3317 stop,
3318 dout,
3319 scan_out);
3320wire l1clk;
3321wire siclk_out;
3322wire soclk_out;
3323wire [26:0] so;
3324
3325 input [27:0] din;
3326
3327
3328 input clk;
3329 input en;
3330 input se;
3331 input scan_in;
3332 input siclk;
3333 input soclk;
3334 input pce_ov;
3335 input stop;
3336
3337
3338
3339 output [27:0] dout;
3340
3341
3342 output scan_out;
3343
3344
3345
3346
3347cl_dp1_l1hdr_8x c0_0 (
3348.l2clk(clk),
3349.pce(en),
3350.aclk(siclk),
3351.bclk(soclk),
3352.l1clk(l1clk),
3353 .se(se),
3354 .pce_ov(pce_ov),
3355 .stop(stop),
3356 .siclk_out(siclk_out),
3357 .soclk_out(soclk_out)
3358);
3359dff #(28) d0_0 (
3360.l1clk(l1clk),
3361.siclk(siclk_out),
3362.soclk(soclk_out),
3363.d(din[27:0]),
3364.si({scan_in,so[26:0]}),
3365.so({so[26:0],scan_out}),
3366.q(dout[27:0])
3367);
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388endmodule
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398//
3399// buff macro
3400//
3401//
3402
3403
3404
3405
3406
3407module l2t_arbadr_dp_buff_macro__dbuff_16x__width_30 (
3408 din,
3409 dout);
3410 input [29:0] din;
3411 output [29:0] dout;
3412
3413
3414
3415
3416
3417
3418buff #(30) d0_0 (
3419.in(din[29:0]),
3420.out(dout[29:0])
3421);
3422
3423
3424
3425
3426
3427
3428
3429
3430endmodule
3431
3432
3433
3434
3435//
3436// xor macro for ports = 2,3
3437//
3438//
3439
3440
3441
3442
3443
3444module l2t_arbadr_dp_xor_macro__dxor_8x__ports_3__width_1 (
3445 din0,
3446 din1,
3447 din2,
3448 dout);
3449 input [0:0] din0;
3450 input [0:0] din1;
3451 input [0:0] din2;
3452 output [0:0] dout;
3453
3454
3455
3456
3457
3458xor3 #(1) d0_0 (
3459.in0(din0[0:0]),
3460.in1(din1[0:0]),
3461.in2(din2[0:0]),
3462.out(dout[0:0])
3463);
3464
3465
3466
3467
3468
3469
3470
3471
3472endmodule
3473
3474
3475
3476
3477
3478//
3479// xor macro for ports = 2,3
3480//
3481//
3482
3483
3484
3485
3486
3487module l2t_arbadr_dp_xor_macro__dxor_8x__ports_2__width_1 (
3488 din0,
3489 din1,
3490 dout);
3491 input [0:0] din0;
3492 input [0:0] din1;
3493 output [0:0] dout;
3494
3495
3496
3497
3498
3499xor2 #(1) d0_0 (
3500.in0(din0[0:0]),
3501.in1(din1[0:0]),
3502.out(dout[0:0])
3503);
3504
3505
3506
3507
3508
3509
3510
3511
3512endmodule
3513
3514
3515
3516
3517
3518//
3519// invert macro
3520//
3521//
3522
3523
3524
3525
3526
3527module l2t_arbadr_dp_inv_macro__stack_1r__width_1 (
3528 din,
3529 dout);
3530 input [0:0] din;
3531 output [0:0] dout;
3532
3533
3534
3535
3536
3537
3538inv #(1) d0_0 (
3539.in(din[0:0]),
3540.out(dout[0:0])
3541);
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551endmodule
3552
3553
3554
3555
3556
3557//
3558// and macro for ports = 2,3,4
3559//
3560//
3561
3562
3563
3564
3565
3566module l2t_arbadr_dp_and_macro__ports_2__width_1 (
3567 din0,
3568 din1,
3569 dout);
3570 input [0:0] din0;
3571 input [0:0] din1;
3572 output [0:0] dout;
3573
3574
3575
3576
3577
3578
3579and2 #(1) d0_0 (
3580.in0(din0[0:0]),
3581.in1(din1[0:0]),
3582.out(dout[0:0])
3583);
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593endmodule
3594
3595
3596
3597
3598
3599//
3600// xor macro for ports = 2,3
3601//
3602//
3603
3604
3605
3606
3607
3608module l2t_arbadr_dp_xor_macro__stack_24r__width_24 (
3609 din0,
3610 din1,
3611 dout);
3612 input [23:0] din0;
3613 input [23:0] din1;
3614 output [23:0] dout;
3615
3616
3617
3618
3619
3620xor2 #(24) d0_0 (
3621.in0(din0[23:0]),
3622.in1(din1[23:0]),
3623.out(dout[23:0])
3624);
3625
3626
3627
3628
3629
3630
3631
3632
3633endmodule
3634
3635
3636
3637
3638
3639//
3640// buff macro
3641//
3642//
3643
3644
3645
3646
3647
3648module l2t_arbadr_dp_buff_macro__stack_5r__width_5 (
3649 din,
3650 dout);
3651 input [4:0] din;
3652 output [4:0] dout;
3653
3654
3655
3656
3657
3658
3659buff #(5) d0_0 (
3660.in(din[4:0]),
3661.out(dout[4:0])
3662);
3663
3664
3665
3666
3667
3668
3669
3670
3671endmodule
3672
3673
3674
3675
3676
3677//
3678// buff macro
3679//
3680//
3681
3682
3683
3684
3685
3686module l2t_arbadr_dp_buff_macro__dbuff_16x__width_29 (
3687 din,
3688 dout);
3689 input [28:0] din;
3690 output [28:0] dout;
3691
3692
3693
3694
3695
3696
3697buff #(29) d0_0 (
3698.in(din[28:0]),
3699.out(dout[28:0])
3700);
3701
3702
3703
3704
3705
3706
3707
3708
3709endmodule
3710
3711
3712
3713
3714
3715//
3716// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
3717//
3718//
3719
3720
3721
3722
3723
3724module l2t_arbadr_dp_cmp_macro__dcmp_8x__width_8 (
3725 din0,
3726 din1,
3727 dout);
3728 input [7:0] din0;
3729 input [7:0] din1;
3730 output dout;
3731
3732
3733
3734
3735
3736
3737cmp #(8) m0_0 (
3738.in0(din0[7:0]),
3739.in1(din1[7:0]),
3740.out(dout)
3741);
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752endmodule
3753
3754
3755
3756
3757
3758//
3759// xor macro for ports = 2,3
3760//
3761//
3762
3763
3764
3765
3766
3767module l2t_arbadr_dp_xor_macro__width_1 (
3768 din0,
3769 din1,
3770 dout);
3771 input [0:0] din0;
3772 input [0:0] din1;
3773 output [0:0] dout;
3774
3775
3776
3777
3778
3779xor2 #(1) d0_0 (
3780.in0(din0[0:0]),
3781.in1(din1[0:0]),
3782.out(dout[0:0])
3783);
3784
3785
3786
3787
3788
3789
3790
3791
3792endmodule
3793
3794
3795
3796
3797
3798//
3799// parity macro (even parity)
3800//
3801//
3802
3803
3804
3805
3806
3807module l2t_arbadr_dp_prty_macro__dprty_8x__width_32 (
3808 din,
3809 dout);
3810 input [31:0] din;
3811 output dout;
3812
3813
3814
3815
3816
3817
3818
3819prty #(32) m0_0 (
3820.in(din[31:0]),
3821.out(dout)
3822);
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833endmodule
3834
3835
3836
3837
3838
3839//
3840// and macro for ports = 2,3,4
3841//
3842//
3843
3844
3845
3846
3847
3848module l2t_arbadr_dp_and_macro__width_1 (
3849 din0,
3850 din1,
3851 dout);
3852 input [0:0] din0;
3853 input [0:0] din1;
3854 output [0:0] dout;
3855
3856
3857
3858
3859
3860
3861and2 #(1) d0_0 (
3862.in0(din0[0:0]),
3863.in1(din1[0:0]),
3864.out(dout[0:0])
3865);
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875endmodule
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885// any PARAMS parms go into naming of macro
3886
3887module l2t_arbadr_dp_msff_macro__stack_28r__width_28 (
3888 din,
3889 clk,
3890 en,
3891 se,
3892 scan_in,
3893 siclk,
3894 soclk,
3895 pce_ov,
3896 stop,
3897 dout,
3898 scan_out);
3899wire l1clk;
3900wire siclk_out;
3901wire soclk_out;
3902wire [26:0] so;
3903
3904 input [27:0] din;
3905
3906
3907 input clk;
3908 input en;
3909 input se;
3910 input scan_in;
3911 input siclk;
3912 input soclk;
3913 input pce_ov;
3914 input stop;
3915
3916
3917
3918 output [27:0] dout;
3919
3920
3921 output scan_out;
3922
3923
3924
3925
3926cl_dp1_l1hdr_8x c0_0 (
3927.l2clk(clk),
3928.pce(en),
3929.aclk(siclk),
3930.bclk(soclk),
3931.l1clk(l1clk),
3932 .se(se),
3933 .pce_ov(pce_ov),
3934 .stop(stop),
3935 .siclk_out(siclk_out),
3936 .soclk_out(soclk_out)
3937);
3938dff #(28) d0_0 (
3939.l1clk(l1clk),
3940.siclk(siclk_out),
3941.soclk(soclk_out),
3942.d(din[27:0]),
3943.si({scan_in,so[26:0]}),
3944.so({so[26:0],scan_out}),
3945.q(dout[27:0])
3946);
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967endmodule
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977//
3978// invert macro
3979//
3980//
3981
3982
3983
3984
3985
3986module l2t_arbadr_dp_inv_macro__dinv_32x__width_1 (
3987 din,
3988 dout);
3989 input [0:0] din;
3990 output [0:0] dout;
3991
3992
3993
3994
3995
3996
3997inv #(1) d0_0 (
3998.in(din[0:0]),
3999.out(dout[0:0])
4000);
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010endmodule
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020// any PARAMS parms go into naming of macro
4021
4022module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_8c__width_8 (
4023 din,
4024 clk,
4025 en,
4026 se,
4027 scan_in,
4028 siclk,
4029 soclk,
4030 pce_ov,
4031 stop,
4032 dout,
4033 scan_out);
4034wire l1clk;
4035wire siclk_out;
4036wire soclk_out;
4037wire [6:0] so;
4038
4039 input [7:0] din;
4040
4041
4042 input clk;
4043 input en;
4044 input se;
4045 input scan_in;
4046 input siclk;
4047 input soclk;
4048 input pce_ov;
4049 input stop;
4050
4051
4052
4053 output [7:0] dout;
4054
4055
4056 output scan_out;
4057
4058
4059
4060
4061cl_dp1_l1hdr_8x c0_0 (
4062.l2clk(clk),
4063.pce(en),
4064.aclk(siclk),
4065.bclk(soclk),
4066.l1clk(l1clk),
4067 .se(se),
4068 .pce_ov(pce_ov),
4069 .stop(stop),
4070 .siclk_out(siclk_out),
4071 .soclk_out(soclk_out)
4072);
4073dff #(8) d0_0 (
4074.l1clk(l1clk),
4075.siclk(siclk_out),
4076.soclk(soclk_out),
4077.d(din[7:0]),
4078.si({scan_in,so[6:0]}),
4079.so({so[6:0],scan_out}),
4080.q(dout[7:0])
4081);
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102endmodule
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4113// also for pass-gate with decoder
4114
4115
4116
4117
4118
4119// any PARAMS parms go into naming of macro
4120
4121module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_40r__width_40 (
4122 din0,
4123 sel0,
4124 din1,
4125 sel1,
4126 din2,
4127 sel2,
4128 dout);
4129wire buffout0;
4130wire buffout1;
4131wire buffout2;
4132
4133 input [39:0] din0;
4134 input sel0;
4135 input [39:0] din1;
4136 input sel1;
4137 input [39:0] din2;
4138 input sel2;
4139 output [39:0] dout;
4140
4141
4142
4143
4144
4145cl_dp1_muxbuff3_8x c0_0 (
4146 .in0(sel0),
4147 .in1(sel1),
4148 .in2(sel2),
4149 .out0(buffout0),
4150 .out1(buffout1),
4151 .out2(buffout2)
4152);
4153mux3s #(40) d0_0 (
4154 .sel0(buffout0),
4155 .sel1(buffout1),
4156 .sel2(buffout2),
4157 .in0(din0[39:0]),
4158 .in1(din1[39:0]),
4159 .in2(din2[39:0]),
4160.dout(dout[39:0])
4161);
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175endmodule
4176
4177
4178// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4179// also for pass-gate with decoder
4180
4181
4182
4183
4184
4185// any PARAMS parms go into naming of macro
4186
4187module l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_40r__width_40 (
4188 din0,
4189 din1,
4190 sel0,
4191 dout);
4192wire psel0_unused;
4193wire psel1;
4194
4195 input [39:0] din0;
4196 input [39:0] din1;
4197 input sel0;
4198 output [39:0] dout;
4199
4200
4201
4202
4203
4204cl_dp1_penc2_8x c0_0 (
4205 .sel0(sel0),
4206 .psel0(psel0_unused),
4207 .psel1(psel1)
4208);
4209
4210mux2e #(40) d0_0 (
4211 .sel(psel1),
4212 .in0(din0[39:0]),
4213 .in1(din1[39:0]),
4214.dout(dout[39:0])
4215);
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229endmodule
4230
4231
4232//
4233// buff macro
4234//
4235//
4236
4237
4238
4239
4240
4241module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_40r__width_40 (
4242 din,
4243 dout);
4244 input [39:0] din;
4245 output [39:0] dout;
4246
4247
4248
4249
4250
4251
4252buff #(40) d0_0 (
4253.in(din[39:0]),
4254.out(dout[39:0])
4255);
4256
4257
4258
4259
4260
4261
4262
4263
4264endmodule
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274// any PARAMS parms go into naming of macro
4275
4276module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_36r__width_27 (
4277 din,
4278 clk,
4279 en,
4280 se,
4281 scan_in,
4282 siclk,
4283 soclk,
4284 pce_ov,
4285 stop,
4286 dout,
4287 scan_out);
4288wire l1clk;
4289wire siclk_out;
4290wire soclk_out;
4291wire [25:0] so;
4292
4293 input [26:0] din;
4294
4295
4296 input clk;
4297 input en;
4298 input se;
4299 input scan_in;
4300 input siclk;
4301 input soclk;
4302 input pce_ov;
4303 input stop;
4304
4305
4306
4307 output [26:0] dout;
4308
4309
4310 output scan_out;
4311
4312
4313
4314
4315cl_dp1_l1hdr_8x c0_0 (
4316.l2clk(clk),
4317.pce(en),
4318.aclk(siclk),
4319.bclk(soclk),
4320.l1clk(l1clk),
4321 .se(se),
4322 .pce_ov(pce_ov),
4323 .stop(stop),
4324 .siclk_out(siclk_out),
4325 .soclk_out(soclk_out)
4326);
4327dff #(27) d0_0 (
4328.l1clk(l1clk),
4329.siclk(siclk_out),
4330.soclk(soclk_out),
4331.d(din[26:0]),
4332.si({scan_in,so[25:0]}),
4333.so({so[25:0],scan_out}),
4334.q(dout[26:0])
4335);
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356endmodule
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4367// also for pass-gate with decoder
4368
4369
4370
4371
4372
4373// any PARAMS parms go into naming of macro
4374
4375module l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_36r__width_27 (
4376 din0,
4377 din1,
4378 din2,
4379 sel0,
4380 sel1,
4381 muxtst,
4382 test,
4383 dout);
4384wire psel0;
4385wire psel1;
4386wire psel2;
4387
4388 input [26:0] din0;
4389 input [26:0] din1;
4390 input [26:0] din2;
4391 input sel0;
4392 input sel1;
4393 input muxtst;
4394 input test;
4395 output [26:0] dout;
4396
4397
4398
4399
4400
4401cl_dp1_penc3_8x c0_0 (
4402 .sel0(sel0),
4403 .sel1(sel1),
4404 .psel0(psel0),
4405 .psel1(psel1),
4406 .psel2(psel2),
4407 .test(test)
4408);
4409
4410mux3 #(27) d0_0 (
4411 .sel0(psel0),
4412 .sel1(psel1),
4413 .sel2(psel2),
4414 .in0(din0[26:0]),
4415 .in1(din1[26:0]),
4416 .in2(din2[26:0]),
4417.dout(dout[26:0]),
4418 .muxtst(muxtst)
4419);
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433endmodule
4434
4435
4436
4437
4438
4439
4440// any PARAMS parms go into naming of macro
4441
4442module l2t_arbadr_dp_msff_macro__stack_10r__width_9 (
4443 din,
4444 clk,
4445 en,
4446 se,
4447 scan_in,
4448 siclk,
4449 soclk,
4450 pce_ov,
4451 stop,
4452 dout,
4453 scan_out);
4454wire l1clk;
4455wire siclk_out;
4456wire soclk_out;
4457wire [7:0] so;
4458
4459 input [8:0] din;
4460
4461
4462 input clk;
4463 input en;
4464 input se;
4465 input scan_in;
4466 input siclk;
4467 input soclk;
4468 input pce_ov;
4469 input stop;
4470
4471
4472
4473 output [8:0] dout;
4474
4475
4476 output scan_out;
4477
4478
4479
4480
4481cl_dp1_l1hdr_8x c0_0 (
4482.l2clk(clk),
4483.pce(en),
4484.aclk(siclk),
4485.bclk(soclk),
4486.l1clk(l1clk),
4487 .se(se),
4488 .pce_ov(pce_ov),
4489 .stop(stop),
4490 .siclk_out(siclk_out),
4491 .soclk_out(soclk_out)
4492);
4493dff #(9) d0_0 (
4494.l1clk(l1clk),
4495.siclk(siclk_out),
4496.soclk(soclk_out),
4497.d(din[8:0]),
4498.si({scan_in,so[7:0]}),
4499.so({so[7:0],scan_out}),
4500.q(dout[8:0])
4501);
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522endmodule
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532//
4533// invert macro
4534//
4535//
4536
4537
4538
4539
4540
4541module l2t_arbadr_dp_inv_macro__dinv_32x__width_2 (
4542 din,
4543 dout);
4544 input [1:0] din;
4545 output [1:0] dout;
4546
4547
4548
4549
4550
4551
4552inv #(2) d0_0 (
4553.in(din[1:0]),
4554.out(dout[1:0])
4555);
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565endmodule
4566
4567
4568
4569
4570
4571//
4572// and macro for ports = 2,3,4
4573//
4574//
4575
4576
4577
4578
4579
4580module l2t_arbadr_dp_and_macro__width_3 (
4581 din0,
4582 din1,
4583 dout);
4584 input [2:0] din0;
4585 input [2:0] din1;
4586 output [2:0] dout;
4587
4588
4589
4590
4591
4592
4593and2 #(3) d0_0 (
4594.in0(din0[2:0]),
4595.in1(din1[2:0]),
4596.out(dout[2:0])
4597);
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607endmodule
4608
4609
4610
4611
4612
4613//
4614// nor macro for ports = 2,3
4615//
4616//
4617
4618
4619
4620
4621
4622module l2t_arbadr_dp_nor_macro__width_1 (
4623 din0,
4624 din1,
4625 dout);
4626 input [0:0] din0;
4627 input [0:0] din1;
4628 output [0:0] dout;
4629
4630
4631
4632
4633
4634
4635nor2 #(1) d0_0 (
4636.in0(din0[0:0]),
4637.in1(din1[0:0]),
4638.out(dout[0:0])
4639);
4640
4641
4642
4643
4644
4645
4646
4647endmodule
4648
4649
4650
4651
4652
4653// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4654// also for pass-gate with decoder
4655
4656
4657
4658
4659
4660// any PARAMS parms go into naming of macro
4661
4662module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_5__stack_35r__width_35 (
4663 din0,
4664 sel0,
4665 din1,
4666 sel1,
4667 din2,
4668 sel2,
4669 din3,
4670 sel3,
4671 din4,
4672 sel4,
4673 dout);
4674wire buffout0;
4675wire buffout1;
4676wire buffout2;
4677wire buffout3;
4678wire buffout4;
4679
4680 input [34:0] din0;
4681 input sel0;
4682 input [34:0] din1;
4683 input sel1;
4684 input [34:0] din2;
4685 input sel2;
4686 input [34:0] din3;
4687 input sel3;
4688 input [34:0] din4;
4689 input sel4;
4690 output [34:0] dout;
4691
4692
4693
4694
4695
4696cl_dp1_muxbuff5_8x c0_0 (
4697 .in0(sel0),
4698 .in1(sel1),
4699 .in2(sel2),
4700 .in3(sel3),
4701 .in4(sel4),
4702 .out0(buffout0),
4703 .out1(buffout1),
4704 .out2(buffout2),
4705 .out3(buffout3),
4706 .out4(buffout4)
4707);
4708mux5s #(35) d0_0 (
4709 .sel0(buffout0),
4710 .sel1(buffout1),
4711 .sel2(buffout2),
4712 .sel3(buffout3),
4713 .sel4(buffout4),
4714 .in0(din0[34:0]),
4715 .in1(din1[34:0]),
4716 .in2(din2[34:0]),
4717 .in3(din3[34:0]),
4718 .in4(din4[34:0]),
4719.dout(dout[34:0])
4720);
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734endmodule
4735
4736
4737
4738
4739
4740
4741// any PARAMS parms go into naming of macro
4742
4743module l2t_arbadr_dp_msff_macro__stack_35r__width_35 (
4744 din,
4745 clk,
4746 en,
4747 se,
4748 scan_in,
4749 siclk,
4750 soclk,
4751 pce_ov,
4752 stop,
4753 dout,
4754 scan_out);
4755wire l1clk;
4756wire siclk_out;
4757wire soclk_out;
4758wire [33:0] so;
4759
4760 input [34:0] din;
4761
4762
4763 input clk;
4764 input en;
4765 input se;
4766 input scan_in;
4767 input siclk;
4768 input soclk;
4769 input pce_ov;
4770 input stop;
4771
4772
4773
4774 output [34:0] dout;
4775
4776
4777 output scan_out;
4778
4779
4780
4781
4782cl_dp1_l1hdr_8x c0_0 (
4783.l2clk(clk),
4784.pce(en),
4785.aclk(siclk),
4786.bclk(soclk),
4787.l1clk(l1clk),
4788 .se(se),
4789 .pce_ov(pce_ov),
4790 .stop(stop),
4791 .siclk_out(siclk_out),
4792 .soclk_out(soclk_out)
4793);
4794dff #(35) d0_0 (
4795.l1clk(l1clk),
4796.siclk(siclk_out),
4797.soclk(soclk_out),
4798.d(din[34:0]),
4799.si({scan_in,so[33:0]}),
4800.so({so[33:0],scan_out}),
4801.q(dout[34:0])
4802);
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823endmodule
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833//
4834// buff macro
4835//
4836//
4837
4838
4839
4840
4841
4842module l2t_arbadr_dp_buff_macro__dbuff_8x__stack_35r__width_35 (
4843 din,
4844 dout);
4845 input [34:0] din;
4846 output [34:0] dout;
4847
4848
4849
4850
4851
4852
4853buff #(35) d0_0 (
4854.in(din[34:0]),
4855.out(dout[34:0])
4856);
4857
4858
4859
4860
4861
4862
4863
4864
4865endmodule
4866
4867
4868
4869
4870
4871// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4872// also for pass-gate with decoder
4873
4874
4875
4876
4877
4878// any PARAMS parms go into naming of macro
4879
4880module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_35r__width_35 (
4881 din0,
4882 sel0,
4883 din1,
4884 sel1,
4885 dout);
4886wire buffout0;
4887wire buffout1;
4888
4889 input [34:0] din0;
4890 input sel0;
4891 input [34:0] din1;
4892 input sel1;
4893 output [34:0] dout;
4894
4895
4896
4897
4898
4899cl_dp1_muxbuff2_8x c0_0 (
4900 .in0(sel0),
4901 .in1(sel1),
4902 .out0(buffout0),
4903 .out1(buffout1)
4904);
4905mux2s #(35) d0_0 (
4906 .sel0(buffout0),
4907 .sel1(buffout1),
4908 .in0(din0[34:0]),
4909 .in1(din1[34:0]),
4910.dout(dout[34:0])
4911);
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925endmodule
4926
4927
4928//
4929// buff macro
4930//
4931//
4932
4933
4934
4935
4936
4937module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_37r__width_37 (
4938 din,
4939 dout);
4940 input [36:0] din;
4941 output [36:0] dout;
4942
4943
4944
4945
4946
4947
4948buff #(37) d0_0 (
4949.in(din[36:0]),
4950.out(dout[36:0])
4951);
4952
4953
4954
4955
4956
4957
4958
4959
4960endmodule
4961
4962
4963
4964
4965
4966//
4967// increment macro
4968//
4969//
4970
4971
4972
4973
4974
4975module l2t_arbadr_dp_increment_macro__dincr_8x__width_12 (
4976 din,
4977 cin,
4978 dout,
4979 cout);
4980 input [11:0] din;
4981 input cin;
4982 output [11:0] dout;
4983 output cout;
4984
4985
4986
4987
4988
4989
4990incr #(12) m0_0 (
4991.cin(cin),
4992.in(din[11:0]),
4993.out(dout[11:0]),
4994.cout(cout)
4995);
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007endmodule
5008
5009
5010
5011
5012
5013//
5014// invert macro
5015//
5016//
5017
5018
5019
5020
5021
5022module l2t_arbadr_dp_inv_macro__dinv_32x__stack_9r__width_9 (
5023 din,
5024 dout);
5025 input [8:0] din;
5026 output [8:0] dout;
5027
5028
5029
5030
5031
5032
5033inv #(9) d0_0 (
5034.in(din[8:0]),
5035.out(dout[8:0])
5036);
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046endmodule
5047
5048
5049
5050
5051
5052//
5053// and macro for ports = 2,3,4
5054//
5055//
5056
5057
5058
5059
5060
5061module l2t_arbadr_dp_and_macro__width_9 (
5062 din0,
5063 din1,
5064 dout);
5065 input [8:0] din0;
5066 input [8:0] din1;
5067 output [8:0] dout;
5068
5069
5070
5071
5072
5073
5074and2 #(9) d0_0 (
5075.in0(din0[8:0]),
5076.in1(din1[8:0]),
5077.out(dout[8:0])
5078);
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088endmodule
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098// any PARAMS parms go into naming of macro
5099
5100module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_20r__width_18 (
5101 din,
5102 clk,
5103 en,
5104 se,
5105 scan_in,
5106 siclk,
5107 soclk,
5108 pce_ov,
5109 stop,
5110 dout,
5111 scan_out);
5112wire l1clk;
5113wire siclk_out;
5114wire soclk_out;
5115wire [16:0] so;
5116
5117 input [17:0] din;
5118
5119
5120 input clk;
5121 input en;
5122 input se;
5123 input scan_in;
5124 input siclk;
5125 input soclk;
5126 input pce_ov;
5127 input stop;
5128
5129
5130
5131 output [17:0] dout;
5132
5133
5134 output scan_out;
5135
5136
5137
5138
5139cl_dp1_l1hdr_8x c0_0 (
5140.l2clk(clk),
5141.pce(en),
5142.aclk(siclk),
5143.bclk(soclk),
5144.l1clk(l1clk),
5145 .se(se),
5146 .pce_ov(pce_ov),
5147 .stop(stop),
5148 .siclk_out(siclk_out),
5149 .soclk_out(soclk_out)
5150);
5151dff #(18) d0_0 (
5152.l1clk(l1clk),
5153.siclk(siclk_out),
5154.soclk(soclk_out),
5155.d(din[17:0]),
5156.si({scan_in,so[16:0]}),
5157.so({so[16:0],scan_out}),
5158.q(dout[17:0])
5159);
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180endmodule
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194// any PARAMS parms go into naming of macro
5195
5196module l2t_arbadr_dp_msff_macro__stack_13r__width_13 (
5197 din,
5198 clk,
5199 en,
5200 se,
5201 scan_in,
5202 siclk,
5203 soclk,
5204 pce_ov,
5205 stop,
5206 dout,
5207 scan_out);
5208wire l1clk;
5209wire siclk_out;
5210wire soclk_out;
5211wire [11:0] so;
5212
5213 input [12:0] din;
5214
5215
5216 input clk;
5217 input en;
5218 input se;
5219 input scan_in;
5220 input siclk;
5221 input soclk;
5222 input pce_ov;
5223 input stop;
5224
5225
5226
5227 output [12:0] dout;
5228
5229
5230 output scan_out;
5231
5232
5233
5234
5235cl_dp1_l1hdr_8x c0_0 (
5236.l2clk(clk),
5237.pce(en),
5238.aclk(siclk),
5239.bclk(soclk),
5240.l1clk(l1clk),
5241 .se(se),
5242 .pce_ov(pce_ov),
5243 .stop(stop),
5244 .siclk_out(siclk_out),
5245 .soclk_out(soclk_out)
5246);
5247dff #(13) d0_0 (
5248.l1clk(l1clk),
5249.siclk(siclk_out),
5250.soclk(soclk_out),
5251.d(din[12:0]),
5252.si({scan_in,so[11:0]}),
5253.so({so[11:0],scan_out}),
5254.q(dout[12:0])
5255);
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276endmodule
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5287// also for pass-gate with decoder
5288
5289
5290
5291
5292
5293// any PARAMS parms go into naming of macro
5294
5295module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_10r__width_9 (
5296 din0,
5297 sel0,
5298 din1,
5299 sel1,
5300 dout);
5301wire buffout0;
5302wire buffout1;
5303
5304 input [8:0] din0;
5305 input sel0;
5306 input [8:0] din1;
5307 input sel1;
5308 output [8:0] dout;
5309
5310
5311
5312
5313
5314cl_dp1_muxbuff2_8x c0_0 (
5315 .in0(sel0),
5316 .in1(sel1),
5317 .out0(buffout0),
5318 .out1(buffout1)
5319);
5320mux2s #(9) d0_0 (
5321 .sel0(buffout0),
5322 .sel1(buffout1),
5323 .in0(din0[8:0]),
5324 .in1(din1[8:0]),
5325.dout(dout[8:0])
5326);
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340endmodule
5341
5342
5343// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5344// also for pass-gate with decoder
5345
5346
5347
5348
5349
5350// any PARAMS parms go into naming of macro
5351
5352module l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_10r__width_9 (
5353 din0,
5354 din1,
5355 sel0,
5356 dout);
5357wire psel0_unused;
5358wire psel1;
5359
5360 input [8:0] din0;
5361 input [8:0] din1;
5362 input sel0;
5363 output [8:0] dout;
5364
5365
5366
5367
5368
5369cl_dp1_penc2_8x c0_0 (
5370 .sel0(sel0),
5371 .psel0(psel0_unused),
5372 .psel1(psel1)
5373);
5374
5375mux2e #(9) d0_0 (
5376 .sel(psel1),
5377 .in0(din0[8:0]),
5378 .in1(din1[8:0]),
5379.dout(dout[8:0])
5380);
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394endmodule
5395
5396
5397// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5398// also for pass-gate with decoder
5399
5400
5401
5402
5403
5404// any PARAMS parms go into naming of macro
5405
5406module l2t_arbadr_dp_mux_macro__dmux_8x__mux_pgnpe__ports_3__stack_10r__width_9 (
5407 din0,
5408 sel0,
5409 din1,
5410 sel1,
5411 din2,
5412 sel2,
5413 muxtst,
5414 dout);
5415wire buffout0;
5416wire buffout1;
5417wire buffout2;
5418
5419 input [8:0] din0;
5420 input sel0;
5421 input [8:0] din1;
5422 input sel1;
5423 input [8:0] din2;
5424 input sel2;
5425 input muxtst;
5426 output [8:0] dout;
5427
5428
5429
5430
5431
5432cl_dp1_muxbuff3_8x c0_0 (
5433 .in0(sel0),
5434 .in1(sel1),
5435 .in2(sel2),
5436 .out0(buffout0),
5437 .out1(buffout1),
5438 .out2(buffout2)
5439);
5440mux3 #(9) d0_0 (
5441 .sel0(buffout0),
5442 .sel1(buffout1),
5443 .sel2(buffout2),
5444 .in0(din0[8:0]),
5445 .in1(din1[8:0]),
5446 .in2(din2[8:0]),
5447.dout(dout[8:0]),
5448 .muxtst(muxtst)
5449);
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463endmodule
5464
5465
5466
5467
5468
5469
5470// any PARAMS parms go into naming of macro
5471
5472module l2t_arbadr_dp_msff_macro__stack_36r__width_36 (
5473 din,
5474 clk,
5475 en,
5476 se,
5477 scan_in,
5478 siclk,
5479 soclk,
5480 pce_ov,
5481 stop,
5482 dout,
5483 scan_out);
5484wire l1clk;
5485wire siclk_out;
5486wire soclk_out;
5487wire [34:0] so;
5488
5489 input [35:0] din;
5490
5491
5492 input clk;
5493 input en;
5494 input se;
5495 input scan_in;
5496 input siclk;
5497 input soclk;
5498 input pce_ov;
5499 input stop;
5500
5501
5502
5503 output [35:0] dout;
5504
5505
5506 output scan_out;
5507
5508
5509
5510
5511cl_dp1_l1hdr_8x c0_0 (
5512.l2clk(clk),
5513.pce(en),
5514.aclk(siclk),
5515.bclk(soclk),
5516.l1clk(l1clk),
5517 .se(se),
5518 .pce_ov(pce_ov),
5519 .stop(stop),
5520 .siclk_out(siclk_out),
5521 .soclk_out(soclk_out)
5522);
5523dff #(36) d0_0 (
5524.l1clk(l1clk),
5525.siclk(siclk_out),
5526.soclk(soclk_out),
5527.d(din[35:0]),
5528.si({scan_in,so[34:0]}),
5529.so({so[34:0],scan_out}),
5530.q(dout[35:0])
5531);
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552endmodule
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562//
5563// invert macro
5564//
5565//
5566
5567
5568
5569
5570
5571module l2t_arbadr_dp_inv_macro__dinv_32x__width_3 (
5572 din,
5573 dout);
5574 input [2:0] din;
5575 output [2:0] dout;
5576
5577
5578
5579
5580
5581
5582inv #(3) d0_0 (
5583.in(din[2:0]),
5584.out(dout[2:0])
5585);
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595endmodule
5596
5597
5598
5599
5600
5601//
5602// nor macro for ports = 2,3
5603//
5604//
5605
5606
5607
5608
5609
5610module l2t_arbadr_dp_nor_macro__dnor_16x__width_1 (
5611 din0,
5612 din1,
5613 dout);
5614 input [0:0] din0;
5615 input [0:0] din1;
5616 output [0:0] dout;
5617
5618
5619
5620
5621
5622
5623nor2 #(1) d0_0 (
5624.in0(din0[0:0]),
5625.in1(din1[0:0]),
5626.out(dout[0:0])
5627);
5628
5629
5630
5631
5632
5633
5634
5635endmodule
5636
5637
5638
5639
5640
5641//
5642// nor macro for ports = 2,3
5643//
5644//
5645
5646
5647
5648
5649
5650module l2t_arbadr_dp_nor_macro__dnor_16x__ports_3__width_2 (
5651 din0,
5652 din1,
5653 din2,
5654 dout);
5655 input [1:0] din0;
5656 input [1:0] din1;
5657 input [1:0] din2;
5658 output [1:0] dout;
5659
5660
5661
5662
5663
5664
5665nor3 #(2) d0_0 (
5666.in0(din0[1:0]),
5667.in1(din1[1:0]),
5668.in2(din2[1:0]),
5669.out(dout[1:0])
5670);
5671
5672
5673
5674
5675
5676
5677
5678endmodule
5679
5680
5681
5682
5683
5684// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5685// also for pass-gate with decoder
5686
5687
5688
5689
5690
5691// any PARAMS parms go into naming of macro
5692
5693module l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgnpe__ports_4__stack_10r__width_9 (
5694 din0,
5695 sel0,
5696 din1,
5697 sel1,
5698 din2,
5699 sel2,
5700 din3,
5701 sel3,
5702 muxtst,
5703 dout);
5704wire buffout0;
5705wire buffout1;
5706wire buffout2;
5707wire buffout3;
5708
5709 input [8:0] din0;
5710 input sel0;
5711 input [8:0] din1;
5712 input sel1;
5713 input [8:0] din2;
5714 input sel2;
5715 input [8:0] din3;
5716 input sel3;
5717 input muxtst;
5718 output [8:0] dout;
5719
5720
5721
5722
5723
5724cl_dp1_muxbuff4_8x c0_0 (
5725 .in0(sel0),
5726 .in1(sel1),
5727 .in2(sel2),
5728 .in3(sel3),
5729 .out0(buffout0),
5730 .out1(buffout1),
5731 .out2(buffout2),
5732 .out3(buffout3)
5733);
5734mux4 #(9) d0_0 (
5735 .sel0(buffout0),
5736 .sel1(buffout1),
5737 .sel2(buffout2),
5738 .sel3(buffout3),
5739 .in0(din0[8:0]),
5740 .in1(din1[8:0]),
5741 .in2(din2[8:0]),
5742 .in3(din3[8:0]),
5743.dout(dout[8:0]),
5744 .muxtst(muxtst)
5745);
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759endmodule
5760
5761
5762
5763
5764
5765
5766// any PARAMS parms go into naming of macro
5767
5768module l2t_arbadr_dp_msff_macro__stack_5r__width_5 (
5769 din,
5770 clk,
5771 en,
5772 se,
5773 scan_in,
5774 siclk,
5775 soclk,
5776 pce_ov,
5777 stop,
5778 dout,
5779 scan_out);
5780wire l1clk;
5781wire siclk_out;
5782wire soclk_out;
5783wire [3:0] so;
5784
5785 input [4:0] din;
5786
5787
5788 input clk;
5789 input en;
5790 input se;
5791 input scan_in;
5792 input siclk;
5793 input soclk;
5794 input pce_ov;
5795 input stop;
5796
5797
5798
5799 output [4:0] dout;
5800
5801
5802 output scan_out;
5803
5804
5805
5806
5807cl_dp1_l1hdr_8x c0_0 (
5808.l2clk(clk),
5809.pce(en),
5810.aclk(siclk),
5811.bclk(soclk),
5812.l1clk(l1clk),
5813 .se(se),
5814 .pce_ov(pce_ov),
5815 .stop(stop),
5816 .siclk_out(siclk_out),
5817 .soclk_out(soclk_out)
5818);
5819dff #(5) d0_0 (
5820.l1clk(l1clk),
5821.siclk(siclk_out),
5822.soclk(soclk_out),
5823.d(din[4:0]),
5824.si({scan_in,so[3:0]}),
5825.so({so[3:0],scan_out}),
5826.q(dout[4:0])
5827);
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848endmodule
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858//
5859// invert macro
5860//
5861//
5862
5863
5864
5865
5866
5867module l2t_arbadr_dp_inv_macro__width_1 (
5868 din,
5869 dout);
5870 input [0:0] din;
5871 output [0:0] dout;
5872
5873
5874
5875
5876
5877
5878inv #(1) d0_0 (
5879.in(din[0:0]),
5880.out(dout[0:0])
5881);
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891endmodule
5892
5893
5894
5895
5896
5897//
5898// and macro for ports = 2,3,4
5899//
5900//
5901
5902
5903
5904
5905
5906module l2t_arbadr_dp_and_macro__ports_4__width_1 (
5907 din0,
5908 din1,
5909 din2,
5910 din3,
5911 dout);
5912 input [0:0] din0;
5913 input [0:0] din1;
5914 input [0:0] din2;
5915 input [0:0] din3;
5916 output [0:0] dout;
5917
5918
5919
5920
5921
5922
5923and4 #(1) d0_0 (
5924.in0(din0[0:0]),
5925.in1(din1[0:0]),
5926.in2(din2[0:0]),
5927.in3(din3[0:0]),
5928.out(dout[0:0])
5929);
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939endmodule
5940
5941
5942
5943
5944
5945//
5946// or macro for ports = 2,3
5947//
5948//
5949
5950
5951
5952
5953
5954module l2t_arbadr_dp_or_macro__ports_3__width_1 (
5955 din0,
5956 din1,
5957 din2,
5958 dout);
5959 input [0:0] din0;
5960 input [0:0] din1;
5961 input [0:0] din2;
5962 output [0:0] dout;
5963
5964
5965
5966
5967
5968
5969or3 #(1) d0_0 (
5970.in0(din0[0:0]),
5971.in1(din1[0:0]),
5972.in2(din2[0:0]),
5973.out(dout[0:0])
5974);
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984endmodule
5985
5986
5987
5988
5989
5990//
5991// or macro for ports = 2,3
5992//
5993//
5994
5995
5996
5997
5998
5999module l2t_arbadr_dp_or_macro__ports_2__width_1 (
6000 din0,
6001 din1,
6002 dout);
6003 input [0:0] din0;
6004 input [0:0] din1;
6005 output [0:0] dout;
6006
6007
6008
6009
6010
6011
6012or2 #(1) d0_0 (
6013.in0(din0[0:0]),
6014.in1(din1[0:0]),
6015.out(dout[0:0])
6016);
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026endmodule
6027
6028
6029
6030
6031
6032//
6033// invert macro
6034//
6035//
6036
6037
6038
6039
6040
6041module l2t_arbadr_dp_inv_macro__dinv_16x__width_9 (
6042 din,
6043 dout);
6044 input [8:0] din;
6045 output [8:0] dout;
6046
6047
6048
6049
6050
6051
6052inv #(9) d0_0 (
6053.in(din[8:0]),
6054.out(dout[8:0])
6055);
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065endmodule
6066
6067
6068
6069
6070
6071// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6072// also for pass-gate with decoder
6073
6074
6075
6076
6077
6078// any PARAMS parms go into naming of macro
6079
6080module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_3 (
6081 din0,
6082 sel0,
6083 din1,
6084 sel1,
6085 dout);
6086wire buffout0;
6087wire buffout1;
6088
6089 input [2:0] din0;
6090 input sel0;
6091 input [2:0] din1;
6092 input sel1;
6093 output [2:0] dout;
6094
6095
6096
6097
6098
6099cl_dp1_muxbuff2_8x c0_0 (
6100 .in0(sel0),
6101 .in1(sel1),
6102 .out0(buffout0),
6103 .out1(buffout1)
6104);
6105mux2s #(3) d0_0 (
6106 .sel0(buffout0),
6107 .sel1(buffout1),
6108 .in0(din0[2:0]),
6109 .in1(din1[2:0]),
6110.dout(dout[2:0])
6111);
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125endmodule
6126
6127
6128
6129
6130
6131
6132// any PARAMS parms go into naming of macro
6133
6134module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_10r__width_9 (
6135 din,
6136 clk,
6137 en,
6138 se,
6139 scan_in,
6140 siclk,
6141 soclk,
6142 pce_ov,
6143 stop,
6144 dout,
6145 scan_out);
6146wire l1clk;
6147wire siclk_out;
6148wire soclk_out;
6149wire [7:0] so;
6150
6151 input [8:0] din;
6152
6153
6154 input clk;
6155 input en;
6156 input se;
6157 input scan_in;
6158 input siclk;
6159 input soclk;
6160 input pce_ov;
6161 input stop;
6162
6163
6164
6165 output [8:0] dout;
6166
6167
6168 output scan_out;
6169
6170
6171
6172
6173cl_dp1_l1hdr_8x c0_0 (
6174.l2clk(clk),
6175.pce(en),
6176.aclk(siclk),
6177.bclk(soclk),
6178.l1clk(l1clk),
6179 .se(se),
6180 .pce_ov(pce_ov),
6181 .stop(stop),
6182 .siclk_out(siclk_out),
6183 .soclk_out(soclk_out)
6184);
6185dff #(9) d0_0 (
6186.l1clk(l1clk),
6187.siclk(siclk_out),
6188.soclk(soclk_out),
6189.d(din[8:0]),
6190.si({scan_in,so[7:0]}),
6191.so({so[7:0],scan_out}),
6192.q(dout[8:0])
6193);
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214endmodule
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228// any PARAMS parms go into naming of macro
6229
6230module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_4r__width_3 (
6231 din,
6232 clk,
6233 en,
6234 se,
6235 scan_in,
6236 siclk,
6237 soclk,
6238 pce_ov,
6239 stop,
6240 dout,
6241 scan_out);
6242wire l1clk;
6243wire siclk_out;
6244wire soclk_out;
6245wire [1:0] so;
6246
6247 input [2:0] din;
6248
6249
6250 input clk;
6251 input en;
6252 input se;
6253 input scan_in;
6254 input siclk;
6255 input soclk;
6256 input pce_ov;
6257 input stop;
6258
6259
6260
6261 output [2:0] dout;
6262
6263
6264 output scan_out;
6265
6266
6267
6268
6269cl_dp1_l1hdr_8x c0_0 (
6270.l2clk(clk),
6271.pce(en),
6272.aclk(siclk),
6273.bclk(soclk),
6274.l1clk(l1clk),
6275 .se(se),
6276 .pce_ov(pce_ov),
6277 .stop(stop),
6278 .siclk_out(siclk_out),
6279 .soclk_out(soclk_out)
6280);
6281dff #(3) d0_0 (
6282.l1clk(l1clk),
6283.siclk(siclk_out),
6284.soclk(soclk_out),
6285.d(din[2:0]),
6286.si({scan_in,so[1:0]}),
6287.so({so[1:0],scan_out}),
6288.q(dout[2:0])
6289);
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310endmodule
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324// any PARAMS parms go into naming of macro
6325
6326module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_12r__width_12 (
6327 din,
6328 clk,
6329 en,
6330 se,
6331 scan_in,
6332 siclk,
6333 soclk,
6334 pce_ov,
6335 stop,
6336 dout,
6337 scan_out);
6338wire l1clk;
6339wire siclk_out;
6340wire soclk_out;
6341wire [10:0] so;
6342
6343 input [11:0] din;
6344
6345
6346 input clk;
6347 input en;
6348 input se;
6349 input scan_in;
6350 input siclk;
6351 input soclk;
6352 input pce_ov;
6353 input stop;
6354
6355
6356
6357 output [11:0] dout;
6358
6359
6360 output scan_out;
6361
6362
6363
6364
6365cl_dp1_l1hdr_8x c0_0 (
6366.l2clk(clk),
6367.pce(en),
6368.aclk(siclk),
6369.bclk(soclk),
6370.l1clk(l1clk),
6371 .se(se),
6372 .pce_ov(pce_ov),
6373 .stop(stop),
6374 .siclk_out(siclk_out),
6375 .soclk_out(soclk_out)
6376);
6377dff #(12) d0_0 (
6378.l1clk(l1clk),
6379.siclk(siclk_out),
6380.soclk(soclk_out),
6381.d(din[11:0]),
6382.si({scan_in,so[10:0]}),
6383.so({so[10:0],scan_out}),
6384.q(dout[11:0])
6385);
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406endmodule
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416//
6417// buff macro
6418//
6419//
6420
6421
6422
6423
6424
6425module l2t_arbadr_dp_buff_macro__dbuff_16x__stack_28r__width_28 (
6426 din,
6427 dout);
6428 input [27:0] din;
6429 output [27:0] dout;
6430
6431
6432
6433
6434
6435
6436buff #(28) d0_0 (
6437.in(din[27:0]),
6438.out(dout[27:0])
6439);
6440
6441
6442
6443
6444
6445
6446
6447
6448endmodule
6449
6450
6451
6452
6453
6454// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6455// also for pass-gate with decoder
6456
6457
6458
6459
6460
6461// any PARAMS parms go into naming of macro
6462
6463module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_28r__width_28 (
6464 din0,
6465 sel0,
6466 din1,
6467 sel1,
6468 dout);
6469wire buffout0;
6470wire buffout1;
6471
6472 input [27:0] din0;
6473 input sel0;
6474 input [27:0] din1;
6475 input sel1;
6476 output [27:0] dout;
6477
6478
6479
6480
6481
6482cl_dp1_muxbuff2_8x c0_0 (
6483 .in0(sel0),
6484 .in1(sel1),
6485 .out0(buffout0),
6486 .out1(buffout1)
6487);
6488mux2s #(28) d0_0 (
6489 .sel0(buffout0),
6490 .sel1(buffout1),
6491 .in0(din0[27:0]),
6492 .in1(din1[27:0]),
6493.dout(dout[27:0])
6494);
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508endmodule
6509
6510
6511// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6512// also for pass-gate with decoder
6513
6514
6515
6516
6517
6518// any PARAMS parms go into naming of macro
6519
6520module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_22r__width_22 (
6521 din0,
6522 sel0,
6523 din1,
6524 sel1,
6525 din2,
6526 sel2,
6527 dout);
6528wire buffout0;
6529wire buffout1;
6530wire buffout2;
6531
6532 input [21:0] din0;
6533 input sel0;
6534 input [21:0] din1;
6535 input sel1;
6536 input [21:0] din2;
6537 input sel2;
6538 output [21:0] dout;
6539
6540
6541
6542
6543
6544cl_dp1_muxbuff3_8x c0_0 (
6545 .in0(sel0),
6546 .in1(sel1),
6547 .in2(sel2),
6548 .out0(buffout0),
6549 .out1(buffout1),
6550 .out2(buffout2)
6551);
6552mux3s #(22) d0_0 (
6553 .sel0(buffout0),
6554 .sel1(buffout1),
6555 .sel2(buffout2),
6556 .in0(din0[21:0]),
6557 .in1(din1[21:0]),
6558 .in2(din2[21:0]),
6559.dout(dout[21:0])
6560);
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574endmodule
6575
6576
6577//
6578// buff macro
6579//
6580//
6581
6582
6583
6584
6585
6586module l2t_arbadr_dp_buff_macro__dbuff_8x__stack_28r__width_28 (
6587 din,
6588 dout);
6589 input [27:0] din;
6590 output [27:0] dout;
6591
6592
6593
6594
6595
6596
6597buff #(28) d0_0 (
6598.in(din[27:0]),
6599.out(dout[27:0])
6600);
6601
6602
6603
6604
6605
6606
6607
6608
6609endmodule
6610
6611
6612
6613
6614
6615// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6616// also for pass-gate with decoder
6617
6618
6619
6620
6621
6622// any PARAMS parms go into naming of macro
6623
6624module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_22r__width_22 (
6625 din0,
6626 sel0,
6627 din1,
6628 sel1,
6629 dout);
6630wire buffout0;
6631wire buffout1;
6632
6633 input [21:0] din0;
6634 input sel0;
6635 input [21:0] din1;
6636 input sel1;
6637 output [21:0] dout;
6638
6639
6640
6641
6642
6643cl_dp1_muxbuff2_8x c0_0 (
6644 .in0(sel0),
6645 .in1(sel1),
6646 .out0(buffout0),
6647 .out1(buffout1)
6648);
6649mux2s #(22) d0_0 (
6650 .sel0(buffout0),
6651 .sel1(buffout1),
6652 .in0(din0[21:0]),
6653 .in1(din1[21:0]),
6654.dout(dout[21:0])
6655);
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669endmodule
6670
6671
6672// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6673// also for pass-gate with decoder
6674
6675
6676
6677
6678
6679// any PARAMS parms go into naming of macro
6680
6681module l2t_arbadr_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_22r__width_22 (
6682 din0,
6683 din1,
6684 din2,
6685 din3,
6686 sel0,
6687 sel1,
6688 sel2,
6689 muxtst,
6690 test,
6691 dout);
6692wire psel0;
6693wire psel1;
6694wire psel2;
6695wire psel3;
6696
6697 input [21:0] din0;
6698 input [21:0] din1;
6699 input [21:0] din2;
6700 input [21:0] din3;
6701 input sel0;
6702 input sel1;
6703 input sel2;
6704 input muxtst;
6705 input test;
6706 output [21:0] dout;
6707
6708
6709
6710
6711
6712cl_dp1_penc4_8x c0_0 (
6713 .sel0(sel0),
6714 .sel1(sel1),
6715 .sel2(sel2),
6716 .psel0(psel0),
6717 .psel1(psel1),
6718 .psel2(psel2),
6719 .psel3(psel3),
6720 .test(test)
6721);
6722
6723mux4 #(22) d0_0 (
6724 .sel0(psel0),
6725 .sel1(psel1),
6726 .sel2(psel2),
6727 .sel3(psel3),
6728 .in0(din0[21:0]),
6729 .in1(din1[21:0]),
6730 .in2(din2[21:0]),
6731 .in3(din3[21:0]),
6732.dout(dout[21:0]),
6733 .muxtst(muxtst)
6734);
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748endmodule
6749
6750
6751//
6752// buff macro
6753//
6754//
6755
6756
6757
6758
6759
6760module l2t_arbadr_dp_buff_macro__dbuff_32x__width_40 (
6761 din,
6762 dout);
6763 input [39:0] din;
6764 output [39:0] dout;
6765
6766
6767
6768
6769
6770
6771buff #(40) d0_0 (
6772.in(din[39:0]),
6773.out(dout[39:0])
6774);
6775
6776
6777
6778
6779
6780
6781
6782
6783endmodule
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793// any PARAMS parms go into naming of macro
6794
6795module l2t_arbadr_dp_msff_macro__dmsff_32x__stack_40r__width_40 (
6796 din,
6797 clk,
6798 en,
6799 se,
6800 scan_in,
6801 siclk,
6802 soclk,
6803 pce_ov,
6804 stop,
6805 dout,
6806 scan_out);
6807wire l1clk;
6808wire siclk_out;
6809wire soclk_out;
6810wire [38:0] so;
6811
6812 input [39:0] din;
6813
6814
6815 input clk;
6816 input en;
6817 input se;
6818 input scan_in;
6819 input siclk;
6820 input soclk;
6821 input pce_ov;
6822 input stop;
6823
6824
6825
6826 output [39:0] dout;
6827
6828
6829 output scan_out;
6830
6831
6832
6833
6834cl_dp1_l1hdr_8x c0_0 (
6835.l2clk(clk),
6836.pce(en),
6837.aclk(siclk),
6838.bclk(soclk),
6839.l1clk(l1clk),
6840 .se(se),
6841 .pce_ov(pce_ov),
6842 .stop(stop),
6843 .siclk_out(siclk_out),
6844 .soclk_out(soclk_out)
6845);
6846dff #(40) d0_0 (
6847.l1clk(l1clk),
6848.siclk(siclk_out),
6849.soclk(soclk_out),
6850.d(din[39:0]),
6851.si({scan_in,so[38:0]}),
6852.so({so[38:0],scan_out}),
6853.q(dout[39:0])
6854);
6855
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871
6872
6873
6874
6875endmodule
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888
6889// any PARAMS parms go into naming of macro
6890
6891module l2t_arbadr_dp_msff_macro__dmsff_32x__minbuff_1__stack_40r__width_40 (
6892 din,
6893 clk,
6894 en,
6895 se,
6896 scan_in,
6897 siclk,
6898 soclk,
6899 pce_ov,
6900 stop,
6901 dout,
6902 scan_out);
6903wire l1clk;
6904wire siclk_out;
6905wire soclk_out;
6906wire [38:0] so;
6907
6908 input [39:0] din;
6909
6910
6911 input clk;
6912 input en;
6913 input se;
6914 input scan_in;
6915 input siclk;
6916 input soclk;
6917 input pce_ov;
6918 input stop;
6919
6920
6921
6922 output [39:0] dout;
6923
6924
6925 output scan_out;
6926
6927
6928
6929
6930cl_dp1_l1hdr_8x c0_0 (
6931.l2clk(clk),
6932.pce(en),
6933.aclk(siclk),
6934.bclk(soclk),
6935.l1clk(l1clk),
6936 .se(se),
6937 .pce_ov(pce_ov),
6938 .stop(stop),
6939 .siclk_out(siclk_out),
6940 .soclk_out(soclk_out)
6941);
6942dff #(40) d0_0 (
6943.l1clk(l1clk),
6944.siclk(siclk_out),
6945.soclk(soclk_out),
6946.d(din[39:0]),
6947.si({scan_in,so[38:0]}),
6948.so({so[38:0],scan_out}),
6949.q(dout[39:0])
6950);
6951
6952
6953
6954
6955
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967
6968
6969
6970
6971endmodule
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981//
6982// buff macro
6983//
6984//
6985
6986
6987
6988
6989
6990module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_23r__width_15 (
6991 din,
6992 dout);
6993 input [14:0] din;
6994 output [14:0] dout;
6995
6996
6997
6998
6999
7000
7001buff #(15) d0_0 (
7002.in(din[14:0]),
7003.out(dout[14:0])
7004);
7005
7006
7007
7008
7009
7010
7011
7012
7013endmodule
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023// any PARAMS parms go into naming of macro
7024
7025module l2t_arbadr_dp_msff_macro__stack_40r__width_40 (
7026 din,
7027 clk,
7028 en,
7029 se,
7030 scan_in,
7031 siclk,
7032 soclk,
7033 pce_ov,
7034 stop,
7035 dout,
7036 scan_out);
7037wire l1clk;
7038wire siclk_out;
7039wire soclk_out;
7040wire [38:0] so;
7041
7042 input [39:0] din;
7043
7044
7045 input clk;
7046 input en;
7047 input se;
7048 input scan_in;
7049 input siclk;
7050 input soclk;
7051 input pce_ov;
7052 input stop;
7053
7054
7055
7056 output [39:0] dout;
7057
7058
7059 output scan_out;
7060
7061
7062
7063
7064cl_dp1_l1hdr_8x c0_0 (
7065.l2clk(clk),
7066.pce(en),
7067.aclk(siclk),
7068.bclk(soclk),
7069.l1clk(l1clk),
7070 .se(se),
7071 .pce_ov(pce_ov),
7072 .stop(stop),
7073 .siclk_out(siclk_out),
7074 .soclk_out(soclk_out)
7075);
7076dff #(40) d0_0 (
7077.l1clk(l1clk),
7078.siclk(siclk_out),
7079.soclk(soclk_out),
7080.d(din[39:0]),
7081.si({scan_in,so[38:0]}),
7082.so({so[38:0],scan_out}),
7083.q(dout[39:0])
7084);
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105endmodule
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115//
7116// buff macro
7117//
7118//
7119
7120
7121
7122
7123
7124module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_15r__width_15 (
7125 din,
7126 dout);
7127 input [14:0] din;
7128 output [14:0] dout;
7129
7130
7131
7132
7133
7134
7135buff #(15) d0_0 (
7136.in(din[14:0]),
7137.out(dout[14:0])
7138);
7139
7140
7141
7142
7143
7144
7145
7146
7147endmodule
7148
7149
7150
7151
7152
7153
7154
7155
7156
7157// any PARAMS parms go into naming of macro
7158
7159module l2t_arbadr_dp_msff_macro__minbuff_1__stack_40r__width_40 (
7160 din,
7161 clk,
7162 en,
7163 se,
7164 scan_in,
7165 siclk,
7166 soclk,
7167 pce_ov,
7168 stop,
7169 dout,
7170 scan_out);
7171wire l1clk;
7172wire siclk_out;
7173wire soclk_out;
7174wire [38:0] so;
7175
7176 input [39:0] din;
7177
7178
7179 input clk;
7180 input en;
7181 input se;
7182 input scan_in;
7183 input siclk;
7184 input soclk;
7185 input pce_ov;
7186 input stop;
7187
7188
7189
7190 output [39:0] dout;
7191
7192
7193 output scan_out;
7194
7195
7196
7197
7198cl_dp1_l1hdr_8x c0_0 (
7199.l2clk(clk),
7200.pce(en),
7201.aclk(siclk),
7202.bclk(soclk),
7203.l1clk(l1clk),
7204 .se(se),
7205 .pce_ov(pce_ov),
7206 .stop(stop),
7207 .siclk_out(siclk_out),
7208 .soclk_out(soclk_out)
7209);
7210dff #(40) d0_0 (
7211.l1clk(l1clk),
7212.siclk(siclk_out),
7213.soclk(soclk_out),
7214.d(din[39:0]),
7215.si({scan_in,so[38:0]}),
7216.so({so[38:0],scan_out}),
7217.q(dout[39:0])
7218);
7219
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239endmodule
7240
7241
7242
7243
7244
7245
7246
7247
7248
7249// general mux macro for pass-gate and and-or muxes with/wout priority encoders
7250// also for pass-gate with decoder
7251
7252
7253
7254
7255
7256// any PARAMS parms go into naming of macro
7257
7258module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_33r__width_33 (
7259 din0,
7260 sel0,
7261 din1,
7262 sel1,
7263 dout);
7264wire buffout0;
7265wire buffout1;
7266
7267 input [32:0] din0;
7268 input sel0;
7269 input [32:0] din1;
7270 input sel1;
7271 output [32:0] dout;
7272
7273
7274
7275
7276
7277cl_dp1_muxbuff2_8x c0_0 (
7278 .in0(sel0),
7279 .in1(sel1),
7280 .out0(buffout0),
7281 .out1(buffout1)
7282);
7283mux2s #(33) d0_0 (
7284 .sel0(buffout0),
7285 .sel1(buffout1),
7286 .in0(din0[32:0]),
7287 .in1(din1[32:0]),
7288.dout(dout[32:0])
7289);
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303endmodule
7304
7305
7306//
7307// buff macro
7308//
7309//
7310
7311
7312
7313
7314
7315module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_32r__width_32 (
7316 din,
7317 dout);
7318 input [31:0] din;
7319 output [31:0] dout;
7320
7321
7322
7323
7324
7325
7326buff #(32) d0_0 (
7327.in(din[31:0]),
7328.out(dout[31:0])
7329);
7330
7331
7332
7333
7334
7335
7336
7337
7338endmodule
7339
7340
7341
7342
7343
7344//
7345// buff macro
7346//
7347//
7348
7349
7350
7351
7352
7353module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_18r__width_18 (
7354 din,
7355 dout);
7356 input [17:0] din;
7357 output [17:0] dout;
7358
7359
7360
7361
7362
7363
7364buff #(18) d0_0 (
7365.in(din[17:0]),
7366.out(dout[17:0])
7367);
7368
7369
7370
7371
7372
7373
7374
7375
7376endmodule
7377
7378
7379
7380
7381
7382// general mux macro for pass-gate and and-or muxes with/wout priority encoders
7383// also for pass-gate with decoder
7384
7385
7386
7387
7388
7389// any PARAMS parms go into naming of macro
7390
7391module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_1r__width_1 (
7392 din0,
7393 sel0,
7394 din1,
7395 sel1,
7396 dout);
7397wire buffout0;
7398wire buffout1;
7399
7400 input [0:0] din0;
7401 input sel0;
7402 input [0:0] din1;
7403 input sel1;
7404 output [0:0] dout;
7405
7406
7407
7408
7409
7410cl_dp1_muxbuff2_8x c0_0 (
7411 .in0(sel0),
7412 .in1(sel1),
7413 .out0(buffout0),
7414 .out1(buffout1)
7415);
7416mux2s #(1) d0_0 (
7417 .sel0(buffout0),
7418 .sel1(buffout1),
7419 .in0(din0[0:0]),
7420 .in1(din1[0:0]),
7421.dout(dout[0:0])
7422);
7423
7424
7425
7426
7427
7428
7429
7430
7431
7432
7433
7434
7435
7436endmodule
7437
7438
7439//
7440// buff macro
7441//
7442//
7443
7444
7445
7446
7447
7448module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_6r__width_2 (
7449 din,
7450 dout);
7451 input [1:0] din;
7452 output [1:0] dout;
7453
7454
7455
7456
7457
7458
7459buff #(2) d0_0 (
7460.in(din[1:0]),
7461.out(dout[1:0])
7462);
7463
7464
7465
7466
7467
7468
7469
7470
7471endmodule
7472
7473
7474
7475
7476
7477// general mux macro for pass-gate and and-or muxes with/wout priority encoders
7478// also for pass-gate with decoder
7479
7480
7481
7482
7483
7484// any PARAMS parms go into naming of macro
7485
7486module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_36r__width_36 (
7487 din0,
7488 sel0,
7489 din1,
7490 sel1,
7491 dout);
7492wire buffout0;
7493wire buffout1;
7494
7495 input [35:0] din0;
7496 input sel0;
7497 input [35:0] din1;
7498 input sel1;
7499 output [35:0] dout;
7500
7501
7502
7503
7504
7505cl_dp1_muxbuff2_8x c0_0 (
7506 .in0(sel0),
7507 .in1(sel1),
7508 .out0(buffout0),
7509 .out1(buffout1)
7510);
7511mux2s #(36) d0_0 (
7512 .sel0(buffout0),
7513 .sel1(buffout1),
7514 .in0(din0[35:0]),
7515 .in1(din1[35:0]),
7516.dout(dout[35:0])
7517);
7518
7519
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529
7530
7531endmodule
7532
7533
7534
7535
7536
7537
7538// any PARAMS parms go into naming of macro
7539
7540module l2t_arbadr_dp_msff_macro__stack_34r__width_34 (
7541 din,
7542 clk,
7543 en,
7544 se,
7545 scan_in,
7546 siclk,
7547 soclk,
7548 pce_ov,
7549 stop,
7550 dout,
7551 scan_out);
7552wire l1clk;
7553wire siclk_out;
7554wire soclk_out;
7555wire [32:0] so;
7556
7557 input [33:0] din;
7558
7559
7560 input clk;
7561 input en;
7562 input se;
7563 input scan_in;
7564 input siclk;
7565 input soclk;
7566 input pce_ov;
7567 input stop;
7568
7569
7570
7571 output [33:0] dout;
7572
7573
7574 output scan_out;
7575
7576
7577
7578
7579cl_dp1_l1hdr_8x c0_0 (
7580.l2clk(clk),
7581.pce(en),
7582.aclk(siclk),
7583.bclk(soclk),
7584.l1clk(l1clk),
7585 .se(se),
7586 .pce_ov(pce_ov),
7587 .stop(stop),
7588 .siclk_out(siclk_out),
7589 .soclk_out(soclk_out)
7590);
7591dff #(34) d0_0 (
7592.l1clk(l1clk),
7593.siclk(siclk_out),
7594.soclk(soclk_out),
7595.d(din[33:0]),
7596.si({scan_in,so[32:0]}),
7597.so({so[32:0],scan_out}),
7598.q(dout[33:0])
7599);
7600
7601
7602
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619
7620endmodule
7621
7622
7623
7624
7625
7626
7627
7628
7629
7630// general mux macro for pass-gate and and-or muxes with/wout priority encoders
7631// also for pass-gate with decoder
7632
7633
7634
7635
7636
7637// any PARAMS parms go into naming of macro
7638
7639module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_32r__width_31 (
7640 din0,
7641 sel0,
7642 din1,
7643 sel1,
7644 din2,
7645 sel2,
7646 dout);
7647wire buffout0;
7648wire buffout1;
7649wire buffout2;
7650
7651 input [30:0] din0;
7652 input sel0;
7653 input [30:0] din1;
7654 input sel1;
7655 input [30:0] din2;
7656 input sel2;
7657 output [30:0] dout;
7658
7659
7660
7661
7662
7663cl_dp1_muxbuff3_8x c0_0 (
7664 .in0(sel0),
7665 .in1(sel1),
7666 .in2(sel2),
7667 .out0(buffout0),
7668 .out1(buffout1),
7669 .out2(buffout2)
7670);
7671mux3s #(31) d0_0 (
7672 .sel0(buffout0),
7673 .sel1(buffout1),
7674 .sel2(buffout2),
7675 .in0(din0[30:0]),
7676 .in1(din1[30:0]),
7677 .in2(din2[30:0]),
7678.dout(dout[30:0])
7679);
7680
7681
7682
7683
7684
7685
7686
7687
7688
7689
7690
7691
7692
7693endmodule
7694
7695
7696//
7697// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
7698//
7699//
7700
7701
7702
7703
7704
7705module l2t_arbadr_dp_cmp_macro__dcmp_8x__width_32 (
7706 din0,
7707 din1,
7708 dout);
7709 input [31:0] din0;
7710 input [31:0] din1;
7711 output dout;
7712
7713
7714
7715
7716
7717
7718cmp #(32) m0_0 (
7719.in0(din0[31:0]),
7720.in1(din1[31:0]),
7721.out(dout)
7722);
7723
7724
7725
7726
7727
7728
7729
7730
7731
7732
7733endmodule
7734
7735
7736
7737
7738
7739//
7740// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
7741//
7742//
7743
7744
7745
7746
7747
7748module l2t_arbadr_dp_cmp_macro__dcmp_8x__width_12 (
7749 din0,
7750 din1,
7751 dout);
7752 input [11:0] din0;
7753 input [11:0] din1;
7754 output dout;
7755
7756
7757
7758
7759
7760
7761cmp #(12) m0_0 (
7762.in0(din0[11:0]),
7763.in1(din1[11:0]),
7764.out(dout)
7765);
7766
7767
7768
7769
7770
7771
7772
7773
7774
7775
7776endmodule
7777
7778
7779
7780
7781
7782//
7783// buff macro
7784//
7785//
7786
7787
7788
7789
7790
7791module l2t_arbadr_dp_buff_macro__dbuff_48x__width_2 (
7792 din,
7793 dout);
7794 input [1:0] din;
7795 output [1:0] dout;
7796
7797
7798
7799
7800
7801
7802buff #(2) d0_0 (
7803.in(din[1:0]),
7804.out(dout[1:0])
7805);
7806
7807
7808
7809
7810
7811
7812
7813
7814endmodule
7815
7816
7817
7818
7819
7820//
7821// invert macro
7822//
7823//
7824
7825
7826
7827
7828
7829module l2t_arbadr_dp_inv_macro__dinv_32x__width_4 (
7830 din,
7831 dout);
7832 input [3:0] din;
7833 output [3:0] dout;
7834
7835
7836
7837
7838
7839
7840inv #(4) d0_0 (
7841.in(din[3:0]),
7842.out(dout[3:0])
7843);
7844
7845
7846
7847
7848
7849
7850
7851
7852
7853endmodule
7854
7855
7856
7857
7858
7859// general mux macro for pass-gate and and-or muxes with/wout priority encoders
7860// also for pass-gate with decoder
7861
7862
7863
7864
7865
7866// any PARAMS parms go into naming of macro
7867
7868module l2t_arbadr_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_24r__width_24 (
7869 din0,
7870 sel0,
7871 din1,
7872 sel1,
7873 din2,
7874 sel2,
7875 dout);
7876wire buffout0;
7877wire buffout1;
7878wire buffout2;
7879
7880 input [23:0] din0;
7881 input sel0;
7882 input [23:0] din1;
7883 input sel1;
7884 input [23:0] din2;
7885 input sel2;
7886 output [23:0] dout;
7887
7888
7889
7890
7891
7892cl_dp1_muxbuff3_8x c0_0 (
7893 .in0(sel0),
7894 .in1(sel1),
7895 .in2(sel2),
7896 .out0(buffout0),
7897 .out1(buffout1),
7898 .out2(buffout2)
7899);
7900mux3s #(24) d0_0 (
7901 .sel0(buffout0),
7902 .sel1(buffout1),
7903 .sel2(buffout2),
7904 .in0(din0[23:0]),
7905 .in1(din1[23:0]),
7906 .in2(din2[23:0]),
7907.dout(dout[23:0])
7908);
7909
7910
7911
7912
7913
7914
7915
7916
7917
7918
7919
7920
7921
7922endmodule
7923
7924
7925//
7926// buff macro
7927//
7928//
7929
7930
7931
7932
7933
7934module l2t_arbadr_dp_buff_macro__dbuff_16x__stack_33r__width_33 (
7935 din,
7936 dout);
7937 input [32:0] din;
7938 output [32:0] dout;
7939
7940
7941
7942
7943
7944
7945buff #(33) d0_0 (
7946.in(din[32:0]),
7947.out(dout[32:0])
7948);
7949
7950
7951
7952
7953
7954
7955
7956
7957endmodule
7958
7959
7960
7961
7962
7963//
7964// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
7965//
7966//
7967
7968
7969
7970
7971
7972module l2t_arbadr_dp_cmp_macro__dcmp_8x__dcmp_8x__width_32 (
7973 din0,
7974 din1,
7975 dout);
7976 input [31:0] din0;
7977 input [31:0] din1;
7978 output dout;
7979
7980
7981
7982
7983
7984
7985cmp #(32) m0_0 (
7986.in0(din0[31:0]),
7987.in1(din1[31:0]),
7988.out(dout)
7989);
7990
7991
7992
7993
7994
7995
7996
7997
7998
7999
8000endmodule
8001
8002
8003
8004
8005
8006//
8007// xnor macro for ports = 2,3
8008//
8009//
8010
8011
8012
8013
8014
8015module l2t_arbadr_dp_xnor_macro__dxnor_8x__ports_2__width_1 (
8016 din0,
8017 din1,
8018 dout);
8019 input [0:0] din0;
8020 input [0:0] din1;
8021 output [0:0] dout;
8022
8023
8024
8025
8026
8027
8028xnor2 #(1) d0_0 (
8029.in0(din0[0:0]),
8030.in1(din1[0:0]),
8031.out(dout[0:0])
8032);
8033
8034
8035
8036
8037
8038
8039
8040endmodule
8041
8042
8043
8044
8045
8046//
8047// buff macro
8048//
8049//
8050
8051
8052
8053
8054
8055module l2t_arbadr_dp_buff_macro__dbuff_32x__stack_1r__width_1 (
8056 din,
8057 dout);
8058 input [0:0] din;
8059 output [0:0] dout;
8060
8061
8062
8063
8064
8065
8066buff #(1) d0_0 (
8067.in(din[0:0]),
8068.out(dout[0:0])
8069);
8070
8071
8072
8073
8074
8075
8076
8077
8078endmodule
8079
8080
8081
8082
Full OpenSPARC design & verification tarball including full HDL.