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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_arbdec_dp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_arbdec_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016////////////////////////////////////////////////////////////////////////
1017// Local header file includes / local define
1018////////////////////////////////////////////////////////////////////////
1019
1020module l2t_arbdec_dp (
1021 tcu_pce_ov,
1022 tcu_aclk,
1023 tcu_bclk,
1024 tcu_scan_en,
1025 tcu_clk_stop,
1026 snpd_snpq_arbdp_inst_px2,
1027 ique_iq_arbdp_inst_px2,
1028 sel_diag_store_data_c7,
1029 misbuf_buf_rd_en,
1030 mbdata_cmp_sel,
1031 l2t_mb2_wdata,
1032 mbdata_fail,
1033 mbdata_fail_bot,
1034 mb_data_read_data,
1035 snpd_ecc_px2,
1036 misbuf_arbdp_ctrue_px2,
1037 misbuf_arb_l2rd_en,
1038 filbuf_arbdp_entry_px2,
1039 filbuf_arbdp_tecc_px2,
1040 csr_l2_steering_tid,
1041 filbuf_arbdp_way_px2,
1042 arb_mux1_mbsel_px2,
1043 arb_mux2_snpsel_px2,
1044 arb_mux3_bufsel_px2,
1045 arb_mux4_c1sel_px2,
1046 scan_in,
1047 l2clk,
1048 arbadr_arbdp_byte_addr_c6,
1049 scan_out,
1050 arbdec_arbdp_inst_c8,
1051 arbdec_snpd_ecc_c8,
1052 arbdec_arbdp_inst_bufidhi_c8,
1053 arbdec_pf_ice_inst_c1,
1054 arbdec_arbdp_inst_way_c1,
1055 arbdec_arbdp_tecc_c1,
1056 arbdec_arbdp_poison_c1,
1057 arbdec_arbdp_inst_mb_entry_c1,
1058 arbdec_arbdp_inst_fb_c1,
1059 arbdec_arbdp_inst_mb_c1,
1060 arbdec_arbdp_evict_c1,
1061 arbdec_arbdp_inst_rqtyp_c1,
1062 arbdec_arbdp_inst_nc_c1,
1063 arbdec_arbdp_inst_size_c1,
1064 arbdec_arbdp_inst_bufidhi_c1,
1065 arbdec_arbdp_inst_bufid1_c1,
1066 arbdec_arbdp_inst_ctrue_c1,
1067 arbdec_arbdp_inst_fb_c2,
1068 arbdec_arbdp_inst_mb_c2,
1069 arbdec_arbdp_rdma_entry_c3,
1070 arbdec_arbdp_rdma_inst_c1,
1071 arbdec_arbdp_inst_rsvd_c1_1,
1072 arbdec_arbdp_rdma_inst_c2,
1073 arbdec_arbdp_inst_dep_c2,
1074 arbdec_arbdp_inst_way_c2,
1075 arbdec_arbdp_inst_rqtyp_c2,
1076 arbdec_arbdp_inst_bufidlo_c2,
1077 arbdec_arbdp_inst_rqtyp_c6,
1078 arbdec_arbdp_inst_way_c3,
1079 arbdec_arbdp_inst_mb_c3,
1080 arbdec_arbdp_inst_tecc_c3,
1081 arbdec_arbdp_inst_nc_c3,
1082 arbdec_arbdp_l1way_c3,
1083 arbdec_arbdp_cpuid_c2,
1084 arbdec_arbdp_cpuid_c5,
1085 arbdec_arbdp_int_bcast_c5,
1086 arbdec_arbdp_inst_l1way_c7,
1087 arbdec_arbdp_inst_size_c7,
1088 st_ack_bmask,
1089 arbdec_arbdp_inst_tid_c7,
1090 arbdec_arbdp_inst_cpuid_c7,
1091 arbdec_arbdp_inst_nc_c7,
1092 arbdec_ctag_c6,
1093 arbdec_size_field_c8,
1094 arbdec_csr_ttype_c6,
1095 arbdec_csr_vcid_c6,
1096 l2t_dbg_xbar_vcid);
1097wire stop;
1098wire pce_ov;
1099wire siclk;
1100wire soclk;
1101wire se;
1102wire ff_read_mbdata_reg_inst1_scanin;
1103wire ff_read_mbdata_reg_inst1_scanout;
1104wire ff_mbdata_snp_ecc_scanin;
1105wire ff_mbdata_snp_ecc_scanout;
1106wire [6:0] mbdata_snp_ecc_px2;
1107wire ff_read_mbdata_reg_inst2_scanin;
1108wire ff_read_mbdata_reg_inst2_scanout;
1109wire arb_mux1_mbsel_px2_n;
1110wire arb_mux2_snpsel_px2_n;
1111wire arb_mux3_bufsel_px2_n;
1112wire arb_mux4_c1sel_px2_n;
1113wire ff_inst1_c1_scanin;
1114wire ff_inst1_c1_scanout;
1115wire [12:9] arbdp_inst_c1_rep1;
1116wire [19:19] arbdp_inst_c1_rep;
1117wire ff_inst1_c2_scanin;
1118wire ff_inst1_c2_scanout;
1119wire ff_inst1_c3_scanin;
1120wire ff_inst1_c3_scanout;
1121wire [5:0] mux1_snp_ecc_px2;
1122wire [5:0] mux2_snp_ecc_px2;
1123wire [5:0] mux3_snp_ecc_px2;
1124wire [5:0] mux4_snp_ecc_px2;
1125wire [5:0] arbdp_snp_ecc_c1;
1126wire ff_inst2_c1_scanin;
1127wire ff_inst2_c1_scanout;
1128wire ff_inst2_c2_scanin;
1129wire ff_inst2_c2_scanout;
1130wire [5:0] arbdp_snp_ecc_c2;
1131wire ff_inst2_c3_scanin;
1132wire ff_inst2_c3_scanout;
1133wire [5:0] arbdp_snp_ecc_c3;
1134wire ff_inst2_c4_scanin;
1135wire ff_inst2_c4_scanout;
1136wire [5:0] arbdp_snp_ecc_c4;
1137wire ff_inst2_c5_scanin;
1138wire ff_inst2_c5_scanout;
1139wire [5:0] arbdp_snp_ecc_c5;
1140wire ff_inst2_c52_scanin;
1141wire ff_inst2_c52_scanout;
1142wire [5:0] arbdp_snp_ecc_c52;
1143wire ff_inst2_c6_scanin;
1144wire ff_inst2_c6_scanout;
1145wire [5:0] arbdp_snp_ecc_c6;
1146wire ff_inst2_c7_scanin;
1147wire ff_inst2_c7_scanout;
1148wire [5:0] arbdp_snp_ecc_c7;
1149wire ff_inst2_c8_scanin;
1150wire ff_inst2_c8_scanout;
1151wire arbdec_arbdp_rdma_inst_c1_n;
1152wire [7:0] l2t_mb2_wdata_r2;
1153wire sel_diag_store_data_c7_n;
1154wire ff_inst_size_c8_scanin;
1155wire ff_inst_size_c8_scanout;
1156wire [7:0] l2t_mb2_wdata_r3;
1157wire sel_diag_store_data_c8;
1158wire sel_diag_store_data_c8_n;
1159wire [7:0] st_ack_bmask_unbuff;
1160wire [4:0] req_type_n;
1161wire arbdec_arbdp_inst_rsvd_c1_1_n;
1162wire req_type_n_1;
1163wire req_type_n_2;
1164wire its_a_load;
1165wire pf_ice_qual;
1166wire ff_mb_data_read_data0_scanin;
1167wire ff_mb_data_read_data0_scanout;
1168wire [127:64] mb_data_read_data_r1;
1169wire ff_mb_data_read_data1_scanin;
1170wire ff_mb_data_read_data1_scanout;
1171wire [31:0] mbdata_cmp_data;
1172wire mbdata_fail_unreg;
1173wire [7:0] l2t_mb2_wdata_r4;
1174wire ff_mbdata_mbist_reg_scanin;
1175wire ff_mbdata_mbist_reg_scanout;
1176wire mbdata_fail_top;
1177wire [7:0] l2t_mb2_wdata_r1;
1178wire misbuf_buf_rd_en_r1;
1179wire misbuf_buf_rd_en_r2;
1180wire mbdata_fail_top_or_bot;
1181wire mbdata_fail_unreg_w;
1182wire misbuf_buf_rd_en_r2_qual;
1183wire misbuf_buf_rd_en_r2_n;
1184wire mbdata_test_active;
1185
1186
1187input tcu_pce_ov;
1188input tcu_aclk;
1189input tcu_bclk;
1190input tcu_scan_en;
1191input tcu_clk_stop;
1192
1193
1194// snp IQ instruction fields
1195input [`JBI_HDR_SZ-1:0] snpd_snpq_arbdp_inst_px2; // grown by 1 bit since 2.0
1196
1197
1198// IQ instruction fields
1199input [24:0] ique_iq_arbdp_inst_px2 ; // from iq ( no valid bit required ) , BS and SR 11/12/03 N2 Xbar Packet format
1200input sel_diag_store_data_c7 ; // from tag , for diagnostic store ack cases
1201
1202// Miss buffer instruction fields
1203//input [`MBD_POISON:`MBD_SZ_LO] mb_data_read_data_low ; // grown by 1 bit since 2.0 , BS & SR 11/04/03, MB grows to 32
1204//input [`MBD_EVICT:`MBD_TECC] mb_data_read_data_mid; // BS & SR 11/04/03, MB grows to 32
1205//input [`MBD_ECC_HI+5: `MBD_ECC_HI+1] mb_data_read_data_hi; // BS & SR 11/04/03, MB grows to 32
1206//input [6:0] mbdata_snp_ecc; // RAS implementation 14/10/04
1207input misbuf_buf_rd_en;
1208input [3:2] mbdata_cmp_sel;
1209input [7:0] l2t_mb2_wdata;
1210output mbdata_fail;
1211input mbdata_fail_bot;
1212input [127:64] mb_data_read_data;
1213
1214/////////////////////////////
1215
1216input [6:0] snpd_ecc_px2; // RAS implementation 14/10/04
1217
1218
1219
1220input misbuf_arbdp_ctrue_px2;
1221input misbuf_arb_l2rd_en ; // from misbuf
1222
1223// Fill buffer instruction fields
1224input [2:0] filbuf_arbdp_entry_px2;
1225input filbuf_arbdp_tecc_px2;
1226input [5:0] csr_l2_steering_tid; // BS and SR 11/12/03 N2 Xbar Packet format change
1227input [3:0] filbuf_arbdp_way_px2;
1228
1229
1230input arb_mux1_mbsel_px2; // arb
1231input arb_mux2_snpsel_px2; // arb
1232input arb_mux3_bufsel_px2; // arb
1233input arb_mux4_c1sel_px2; // arb
1234
1235input scan_in;
1236input l2clk;
1237
1238input [2:0] arbadr_arbdp_byte_addr_c6; // from arbaddr // Phase 2 : SIU inteface and packet format change 2/7/04
1239
1240
1241output scan_out;
1242output [`L2_POISON:`L2_SZ_LO] arbdec_arbdp_inst_c8; // to mbdata.
1243output [6:0] arbdec_snpd_ecc_c8;
1244output arbdec_arbdp_inst_bufidhi_c8; // to misbuf
1245
1246
1247 output arbdec_pf_ice_inst_c1;
1248 output [3:0] arbdec_arbdp_inst_way_c1;
1249 output arbdec_arbdp_tecc_c1 ; // used in arb for waysel gate
1250
1251 output arbdec_arbdp_poison_c1; // NEW_PIN to arbdata
1252 output [4:0] arbdec_arbdp_inst_mb_entry_c1; // Miss Buffer entry to misbuf , BS & SR 11/04/03, MB grows to 32
1253 output arbdec_arbdp_inst_fb_c1 ; // used by arb to turn off fb hits.
1254 output arbdec_arbdp_inst_mb_c1 ; // used by arb to turn off fb hits.
1255 output arbdec_arbdp_evict_c1; // unqualled evict to arb
1256 output [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdec_arbdp_inst_rqtyp_c1 ; // NEW_PIN decode
1257 output arbdec_arbdp_inst_nc_c1 ; // NEW_PIN decode
1258 output [`L2_SZ_HI:`L2_SZ_LO] arbdec_arbdp_inst_size_c1; // NEW_PIN decode
1259 output arbdec_arbdp_inst_bufidhi_c1;
1260 output arbdec_arbdp_inst_bufid1_c1; // buf_id hi-1
1261 output arbdec_arbdp_inst_ctrue_c1;
1262
1263
1264
1265 output arbdec_arbdp_inst_fb_c2; // output to arb for
1266 // generation of l2d wrdata mux sel.
1267 output arbdec_arbdp_inst_mb_c2;
1268 output [1:0] arbdec_arbdp_rdma_entry_c3;
1269 output arbdec_arbdp_rdma_inst_c1; // used in misbuf,filbuf,tag.
1270 output arbdec_arbdp_inst_rsvd_c1_1; // used in arb
1271 output arbdec_arbdp_rdma_inst_c2; // used in arb.
1272 output arbdec_arbdp_inst_dep_c2; // to arb for dir cam logic
1273 output [3:0] arbdec_arbdp_inst_way_c2; // used in l2t_vuaddp.sv
1274 output [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdec_arbdp_inst_rqtyp_c2 ; // NEW_PIN decode
1275 output arbdec_arbdp_inst_bufidlo_c2 ; // NEW_PIN decode
1276 output [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdec_arbdp_inst_rqtyp_c6 ;
1277
1278
1279 output [3:0] arbdec_arbdp_inst_way_c3; // used in l2t_tag_ctl.sv
1280// output arbdec_arbdp_inst_fb_c3;
1281 output arbdec_arbdp_inst_mb_c3;
1282 output arbdec_arbdp_inst_tecc_c3;
1283 output arbdec_arbdp_inst_nc_c3; // L1 non allocating instruction
1284 output [1:0] arbdec_arbdp_l1way_c3; // l1 replacement way.
1285 output [2:0] arbdec_arbdp_cpuid_c2;
1286
1287
1288 output [2:0] arbdec_arbdp_cpuid_c5;
1289 output arbdec_arbdp_int_bcast_c5; // to oqu.
1290
1291 output [1:0] arbdec_arbdp_inst_l1way_c7; // to oque
1292 output [7:0] arbdec_arbdp_inst_size_c7; // to oque , BS and SR 11/12/03 N2 Xbar Packet format change
1293 output [7:0] st_ack_bmask; // to dirvec, BS and SR 1/30/04, Bmask for store ack including diagnostic stores
1294 output [2:0] arbdec_arbdp_inst_tid_c7; // to oque, BS and SR 11/12/03 N2 Xbar Packet format change
1295 output [2:0] arbdec_arbdp_inst_cpuid_c7; // to oque
1296 output arbdec_arbdp_inst_nc_c7; // to oque
1297 output [31:0] arbdec_ctag_c6; // Phase 2 : SIU inteface and packet format change 2/7/04
1298
1299 output [1:0] arbdec_size_field_c8; // used for CAS instructions compare qualification
1300
1301// debug changes
1302
1303output [4:0] arbdec_csr_ttype_c6;
1304output [5:0] arbdec_csr_vcid_c6;
1305output [5:0] l2t_dbg_xbar_vcid;
1306
1307
1308
1309assign stop = tcu_clk_stop;
1310assign pce_ov = tcu_pce_ov;
1311assign siclk = tcu_aclk;
1312assign soclk = tcu_bclk;
1313assign se = tcu_scan_en;
1314
1315
1316//assign scan_out = 1'b0;
1317
1318 wire [`L2_FBF :`L2_SZ_LO] snpq_inst_px2;
1319 wire [`L2_FBF :`L2_SZ_LO] iq_inst_px2;
1320 wire [`L2_FBF :`L2_SZ_LO] fbf_inst_px2;
1321 wire [`L2_FBF :`L2_SZ_LO] mbf_inst_px2; // BS & SR 11/04/03, MB grows to 32
1322
1323 wire [`L2_FBF :`L2_SZ_LO] mux1_inst_px2; // BS & SR 11/04/03, MB grows to 32
1324 wire [`L2_FBF :`L2_SZ_LO] mux2_inst_px2; // BS & SR 11/04/03, MB grows to 32
1325 wire [`L2_FBF :`L2_SZ_LO] mux3_inst_px2; // BS & SR 11/04/03, MB grows to 32
1326 wire [`L2_FBF :`L2_SZ_LO] mux4_inst_px2; // BS & SR 11/04/03, MB grows to 32
1327
1328 wire [`L2_FBF :`L2_SZ_LO] arbdp_inst_c1; // BS & SR 11/04/03, MB grows to 32
1329 wire [`L2_FBF :`L2_SZ_LO] arbdp_inst_c2; // BS & SR 11/04/03, MB grows to 32
1330 wire [`L2_FBF :`L2_SZ_LO] arbdp_inst_c3; // BS & SR 11/04/03, MB grows to 32
1331
1332 wire [`L2_POISON :`L2_SZ_LO] arbdp_inst_c4;
1333 wire [`L2_POISON :`L2_SZ_LO] arbdp_inst_c5;
1334 wire [`L2_POISON :`L2_SZ_LO] arbdp_inst_c52; // BS 03/11/04 extra cycle for mem access
1335 wire [`L2_POISON :`L2_SZ_LO] arbdp_inst_c6;
1336 wire [`L2_POISON :`L2_SZ_LO] arbdp_inst_c7;
1337
1338 wire [7:0] arbdec_arbdp_inst_size_c8; // BS and SR 1/30/04, Bmask for store ack including diagnostic stores
1339
1340
1341//
1342// Congestion made me move this logic
1343//
1344
1345wire [`MBD_POISON:`MBD_SZ_LO] mb_data_read_data_low;
1346wire [`MBD_EVICT:`MBD_TECC] mb_data_read_data_mid;
1347wire [`MBD_ECC_HI+5: `MBD_ECC_HI+1] mb_data_read_data_hi;
1348wire [6:0] mbdata_snp_ecc;
1349
1350assign mb_data_read_data_low[`MBD_POISON:`MBD_SZ_LO] = mb_data_read_data[`MBD_POISON:`MBD_SZ_LO];
1351assign mb_data_read_data_mid[`MBD_EVICT:`MBD_TECC] = mb_data_read_data[`MBD_EVICT:`MBD_TECC];
1352assign mb_data_read_data_hi[`MBD_ECC_HI+5: `MBD_ECC_HI+1] =mb_data_read_data[`MBD_ECC_HI+5: `MBD_ECC_HI+1];
1353assign mbdata_snp_ecc[6:0] = mb_data_read_data[117:111];
1354
1355//////////////////////////////////////////////////////////////////////////////////////
1356// INSTRUCTION FIELDS MBF FBF SNP IQ/PCX
1357//////////////////////////////////////////////////////////////////////////////////////
1358// L2_FBF 0 1 0 0
1359// L2_MBF 1 0 0 0
1360// L2_SNP 0 0 1 0
1361// L2_CTRUE V 0 0 0
1362// L2_EVICT V 0 0 0
1363// L2_DEP V 0 0 0
1364// L2_TECC V V 0 0
1365// L2_ENTRY<4:0> mbid fbid // BS & SR 11/04/03, MB grows to 32
1366// L2_POISON 0 0 V 0
1367// L2_RDMA<1:0> V 0 V 0
1368// L2_RQTYP<4:0> V** 1F {1'b0,"O", req<2:0>} V // Phase 2 : SIU inteface and packet format change 2/7/04
1369// L2_NC V 0 0 V // Phase 2 : SIU inteface and packet format change 2/7/04
1370// L2_RSVD 0 0 1 0
1371// L2_CPUID<2:0> V** 0*** "PES" bits V // Phase 2 : SIU inteface and packet format change 2/7/04
1372// L2_TID<2:0> V 0*** ctag<15:13> V //BS and SR 11/12/03 N2 Xbar Packet formaT
1373// L2_BUFID<2:0> rsvd X ctag<12:10> rsvd // Phase 2 : SIU inteface and packet format change 2/7/04
1374// L2_L1WY<1:0> V X ctag<9:8> V // Phase 2 : SIU inteface and packet format change 2/7/04
1375// L2_SZ_HI<7:0> V X V/ctag7:0 V BS and SR 11/12/03 N2 Xbar Packet forma // Phase 2 : SIU inteface and packet format change 2/7/04
1376//////////////////////////////////////////////////////////////////////////////////////
1377// snoop instuction bits [40:0].
1378// // Phase 2 : SIU inteface and packet format change 2/7/04
1379// instruction format is as follows
1380// WRI RDD WR8
1381// 0-15 : tag[15:0] tag[15:0] {8'bdontcare, byteenable[7:0]}
1382// 16 : 0 1 0
1383// 17 : 0 0 1
1384// 18 : 1 0 0
1385// 22-19: {O,P,E,S} {O,P,E,S} {O,P,E,S}
1386// 23 : dont care dont care dont care
1387// 25-24: rdma rdma rdma entry
1388// 27 : poison poison poison
1389
1390
1391
1392
1393 assign snpq_inst_px2[`L2_FBF] = 1'b0 ;
1394 assign snpq_inst_px2[`L2_MBF] = 1'b0 ;
1395 assign snpq_inst_px2[`L2_SNP] = 1'b1 ; // currently this bit is RSVD
1396 assign snpq_inst_px2[`L2_CTRUE] = 1'b0 ;
1397 assign snpq_inst_px2[`L2_EVICT] = 1'b0;
1398 assign snpq_inst_px2[`L2_DEP] = 1'b0 ;
1399 assign snpq_inst_px2[`L2_TECC] = 1'b0 ;
1400 assign snpq_inst_px2[`L2_POISON] = snpd_snpq_arbdp_inst_px2[`JBINST_POISON];
1401 assign snpq_inst_px2[`L2_ENTRY_HI:`L2_ENTRY_LO] = 5'b0 ;
1402
1403 assign snpq_inst_px2[`L2_RDMA_HI:`L2_RDMA_LO] = {
1404 snpd_snpq_arbdp_inst_px2[`JBINST_ENTRY_HI:`JBINST_ENTRY_LO] } ;
1405
1406 assign snpq_inst_px2[`L2_RQTYP_HI:`L2_RQTYP_LO] =
1407 {
1408 1'b0, snpd_snpq_arbdp_inst_px2[`JBINST_OPES_HI],
1409 snpd_snpq_arbdp_inst_px2[`JBINST_RQ_WR64:`JBINST_RQ_RD]
1410 } ;
1411
1412 assign snpq_inst_px2[`L2_NC] = 1'b0 ;
1413
1414 assign snpq_inst_px2[`L2_RSVD] = 1'b1 ;
1415
1416 assign snpq_inst_px2[`L2_CPUID_HI:`L2_CPUID_LO] =
1417 { snpd_snpq_arbdp_inst_px2[`JBINST_OPES_LO+2:`JBINST_OPES_LO]};
1418
1419
1420
1421// RDD AND WRI will have tag[15:0] but WR8 will have
1422// 7:0 valid
1423 assign snpq_inst_px2[`L2_TID_HI:`L2_TID_LO] =
1424 {snpd_snpq_arbdp_inst_px2[`JBINST_CTAG_HI:`JBINST_CTAG_LO+5]};
1425 // BS and SR 11/12/03 N2 Xbar Packet format change
1426
1427 assign snpq_inst_px2[`L2_BUFID_HI:`L2_BUFID_LO] =
1428 { snpd_snpq_arbdp_inst_px2[`JBINST_CTAG_LO+4:`JBINST_CTAG_LO+2]};
1429
1430 assign snpq_inst_px2[`L2_L1WY_HI:`L2_L1WY_LO] =
1431 { snpd_snpq_arbdp_inst_px2[`JBINST_CTAG_LO+1:`JBINST_CTAG_LO]};
1432
1433 assign snpq_inst_px2[`L2_SZ_HI:`L2_SZ_LO] =
1434 snpd_snpq_arbdp_inst_px2[`JBINST_SZ_HI:`JBINST_SZ_LO];
1435
1436
1437//**********************
1438// iq instuction.
1439//**********************
1440
1441// inst bits 40:26
1442 assign iq_inst_px2[`L2_FBF:`L2_ENTRY_LO] = 12'b0 ;
1443 assign iq_inst_px2[`L2_POISON] = 1'b0 ;
1444
1445 assign iq_inst_px2[`L2_RDMA_HI:`L2_RDMA_LO] = 2'b0;
1446// inst bits 25:0 BS and SR 11/12/03 N2 Xbar Packet format
1447 assign iq_inst_px2[`L2_RQTYP_HI:`L2_SZ_LO] =
1448 {ique_iq_arbdp_inst_px2[24:19],
1449 1'b0, // RSVD bit
1450 ique_iq_arbdp_inst_px2[`L2_CPUID_HI:`L2_SZ_LO]} ;
1451
1452
1453//**********************
1454// fill buffer instuction.
1455//**********************
1456// inst bits 40:29
1457 assign fbf_inst_px2[`L2_FBF] = 1'b1 ;
1458 assign fbf_inst_px2[`L2_MBF] = 1'b0 ;
1459 assign fbf_inst_px2[`L2_SNP] = 1'b0 ;
1460 assign fbf_inst_px2[`L2_RSVD] = 1'b0 ;
1461
1462 assign fbf_inst_px2[`L2_CTRUE] = 1'b0 ;
1463 assign fbf_inst_px2[`L2_EVICT] = 1'b0;
1464 assign fbf_inst_px2[`L2_DEP] = 1'b0 ;
1465 assign fbf_inst_px2[`L2_TECC] = filbuf_arbdp_tecc_px2 ;
1466 assign fbf_inst_px2[`L2_ENTRY_HI:`L2_ENTRY_LO] = { 2'b00 , filbuf_arbdp_entry_px2[2:0] } ;
1467
1468// inst bits 28:0
1469 assign fbf_inst_px2[`L2_POISON] = 1'b0;
1470 assign fbf_inst_px2[`L2_RDMA_HI:`L2_RDMA_LO] = 2'b0;
1471 assign fbf_inst_px2[`L2_RQTYP_HI:`L2_RQTYP_LO] = 5'b11111;
1472 assign fbf_inst_px2[`L2_NC] = 1'b0 ;
1473 assign fbf_inst_px2[`L2_CPUID_HI:`L2_CPUID_LO] = csr_l2_steering_tid[5:3];
1474 assign fbf_inst_px2[`L2_TID_HI:`L2_TID_LO] = csr_l2_steering_tid[2:0]; // BS and SR 11/12/03 N2 Xbar Packet format change
1475 assign fbf_inst_px2[`L2_BUFID_HI:`L2_BUFID_HI-3] = filbuf_arbdp_way_px2[3:0] ;
1476 assign fbf_inst_px2[`L2_BUFID_HI-4:`L2_SZ_LO] = 9'b0 ; // BS and SR 11/12/03 N2 Xbar Packet format change
1477
1478
1479//**********************
1480// miss buffer instuction.
1481//**********************
1482
1483// bits [40:37]
1484
1485 assign mbf_inst_px2[`L2_FBF] = 1'b0 ; // BS & SR 11/04/03, MB grows to 32
1486 assign mbf_inst_px2[`L2_MBF] = 1'b1 ; // BS & SR 11/04/03, MB grows to 32
1487 assign mbf_inst_px2[`L2_SNP] = 1'b0 ; // BS & SR 11/04/03, MB grows to 32
1488 assign mbf_inst_px2[`L2_CTRUE] = misbuf_arbdp_ctrue_px2; // BS & SR 11/04/03, MB grows to 32
1489
1490// bits [36:29]
1491
1492
1493//msff_macro ff_mbdata_snp_ecc_d1 (width=7,stack=7c)
1494// (
1495// .din(mbdata_snp_ecc_d1[6:0]),
1496// .scan_in(),
1497// .scan_out(),
1498// .clk(l2clk),
1499// .dout(mbdata_snp_ecc_px2[6:0]),
1500// .en(1'b1)
1501// );
1502//
1503//msff_macro ff_read_mbdata_reg_inst1 (width=15,stack=15c)
1504// (
1505// .din({mbdata_snp_ecc[6:0],mb_data_read_data_mid,mb_data_read_data_hi}), // BS & SR 11/04/03, MB grows to 32
1506// .scan_in(ff_read_mbdata_reg_inst1_scanin),
1507// .scan_out(ff_read_mbdata_reg_inst1_scanout),
1508// .clk(l2clk),
1509// .dout({mbdata_snp_ecc_px2[6:0],mbf_inst_px2[`L2_EVICT:`L2_ENTRY_LO]}),
1510// .en(misbuf_arb_l2rd_en)
1511// );
1512//
1513
1514l2t_arbdec_dp_msff_macro__stack_8c__width_8 ff_read_mbdata_reg_inst1
1515 (
1516 .scan_in(ff_read_mbdata_reg_inst1_scanin),
1517 .scan_out(ff_read_mbdata_reg_inst1_scanout),
1518 .din({mb_data_read_data_mid,mb_data_read_data_hi}), // BS & SR 11/04/03, MB grows to 32
1519 .clk(l2clk),
1520 .dout(mbf_inst_px2[`L2_EVICT:`L2_ENTRY_LO]),
1521 .en(misbuf_arb_l2rd_en),
1522 .se(se),
1523 .siclk(siclk),
1524 .soclk(soclk),
1525 .pce_ov(pce_ov),
1526 .stop(stop)
1527 );
1528
1529//
1530//msff_macro ff_misbuf_arb_l2rd_en_d1 (width=1,stack=1c)
1531// (
1532// .scan_in(ff_misbuf_arb_l2rd_en_d1_scanin),
1533// .scan_out(ff_misbuf_arb_l2rd_en_d1_scanout),
1534// .din(misbuf_arb_l2rd_en),
1535// .clk(l2clk),
1536// .dout(misbuf_arb_l2rd_en_d1),
1537// .en(1'b1)
1538// );
1539//
1540
1541l2t_arbdec_dp_msff_macro__stack_7c__width_7 ff_mbdata_snp_ecc
1542 (
1543 .scan_in(ff_mbdata_snp_ecc_scanin),
1544 .scan_out(ff_mbdata_snp_ecc_scanout),
1545 .din(mbdata_snp_ecc[6:0]), // BS & SR 11/04/03, MB grows to 32
1546 .clk(l2clk),
1547 .dout(mbdata_snp_ecc_px2[6:0]),
1548 .en(misbuf_arb_l2rd_en),
1549 .se(se),
1550 .siclk(siclk),
1551 .soclk(soclk),
1552 .pce_ov(pce_ov),
1553 .stop(stop)
1554 );
1555
1556// bits [28:0]
1557
1558l2t_arbdec_dp_msff_macro__stack_29c__width_29 ff_read_mbdata_reg_inst2 // BS and SR 11/12/03 N2 Xbar Packet format change
1559 (
1560 .scan_in(ff_read_mbdata_reg_inst2_scanin),
1561 .scan_out(ff_read_mbdata_reg_inst2_scanout),
1562 .din(mb_data_read_data_low), // BS & SR 11/04/03, MB grows to 32
1563 .clk(l2clk),
1564 .dout(mbf_inst_px2[`L2_POISON:`L2_SZ_LO]),
1565 .en(misbuf_arb_l2rd_en),
1566 .se(se),
1567 .siclk(siclk),
1568 .soclk(soclk),
1569 .pce_ov(pce_ov),
1570 .stop(stop)
1571 );
1572
1573
1574
1575//************************
1576// arbiter muxes
1577// arbiter is split into two rows
1578// The first row contains 11 bits. The second row contains 20 bits.
1579//************************
1580l2t_arbdec_dp_inv_macro__width_1 arb_mux1_mbsel_px2_inv_slice
1581 (
1582 .dout (arb_mux1_mbsel_px2_n ),
1583 .din (arb_mux1_mbsel_px2 )
1584 );
1585
1586l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_12c__width_12 mux_mux1_inst1_px2 // BS & SR 11/04/03, MB grows to 32
1587 (
1588 .dout (mux1_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
1589 .din0(mbf_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // mbf inst 40:29
1590 .din1(fbf_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // fbf inst 40:29
1591 .sel0(arb_mux1_mbsel_px2),
1592 .sel1(arb_mux1_mbsel_px2_n)
1593 );
1594
1595l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_29c__width_29 mux_mux1_inst2_px2 // BS and SR 11/12/03 N2 Xbar Packet format change
1596 (
1597 .dout (mux1_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
1598 .din0(mbf_inst_px2[`L2_POISON:`L2_SZ_LO]), // mbf inst 28:0
1599 .din1(fbf_inst_px2[`L2_POISON:`L2_SZ_LO] ), // fbf inst 28:0
1600 .sel0(arb_mux1_mbsel_px2),
1601 .sel1(arb_mux1_mbsel_px2_n)
1602 );
1603
1604l2t_arbdec_dp_inv_macro__width_1 arb_mux2_snpsel_px2_inv_slice
1605 (
1606 .dout (arb_mux2_snpsel_px2_n ),
1607 .din (arb_mux2_snpsel_px2 )
1608 );
1609
1610l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_12c__width_12 mux_mux2_inst1_px2 // BS & SR 11/04/03, MB grows to 32
1611 (
1612 .dout (mux2_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
1613 .din0(snpq_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // snoop
1614 .din1(mux1_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // fbf/mbf instuction 40:29
1615 .sel0(arb_mux2_snpsel_px2),
1616 .sel1(arb_mux2_snpsel_px2_n)
1617 );
1618
1619l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_29c__width_29 mux_mux2_inst2_px2 // BS and SR 11/12/03 N2 Xbar Packet format change
1620 (
1621 .dout (mux2_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
1622 .din0(snpq_inst_px2[`L2_POISON:`L2_SZ_LO]), // snoop inst 28:0
1623 .din1(mux1_inst_px2[`L2_POISON:`L2_SZ_LO] ), // fbf/mbf inst 28:0
1624 .sel0(arb_mux2_snpsel_px2),
1625 .sel1(arb_mux2_snpsel_px2_n)
1626 );
1627
1628l2t_arbdec_dp_inv_macro__width_1 arb_mux3_bufsel_px2_inv_slice
1629 (
1630 .dout (arb_mux3_bufsel_px2_n ),
1631 .din (arb_mux3_bufsel_px2 )
1632 );
1633
1634l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_12c__width_12 mux_mux3_inst1_px2 // BS & SR 11/04/03, MB grows to 32
1635 (
1636 .dout (mux3_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
1637 .din0(mux2_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // snoop and mbf and fbf
1638 .din1(iq_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // iq instuction 40:29
1639 .sel0(arb_mux3_bufsel_px2),
1640 .sel1(arb_mux3_bufsel_px2_n)
1641 );
1642
1643
1644l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_29c__width_29 mux_mux3_inst2_px2 // BS and SR 11/12/03 N2 Xbar Packet format change
1645 (
1646 .dout (mux3_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
1647 .din0(mux2_inst_px2[`L2_POISON:`L2_SZ_LO]), // snoop and mbf and fbf
1648 .din1(iq_inst_px2[`L2_POISON:`L2_SZ_LO] ), // iq inst 28:0
1649 .sel0(arb_mux3_bufsel_px2),
1650 .sel1(arb_mux3_bufsel_px2_n)
1651 );
1652
1653
1654 // a mux flop cannot be used here.
1655l2t_arbdec_dp_inv_macro__width_1 arb_mux4_c1sel_px2_inv_slice
1656 (
1657 .dout (arb_mux4_c1sel_px2_n ),
1658 .din (arb_mux4_c1sel_px2 )
1659 );
1660
1661
1662l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_12c__width_12 mux_mux4_inst1_px2 // BS & SR 11/04/03, MB grows to 32
1663 (
1664 .dout (mux4_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
1665 .din0(mux3_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // snoop and mbf and fbf and iq
1666 .din1(arbdp_inst_c1[`L2_FBF:`L2_ENTRY_LO]), // c1 instuction 40:29
1667 .sel0(arb_mux4_c1sel_px2_n),
1668 .sel1(arb_mux4_c1sel_px2)
1669 );
1670
1671l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_29c__width_29 mux_mux4_inst2_px2 // BS and SR 11/12/03 N2 Xbar Packet format
1672 (
1673 .dout (mux4_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
1674 .din0(mux3_inst_px2[`L2_POISON:`L2_SZ_LO]), // snoop and mbf and fbf and iq
1675 .din1(arbdp_inst_c1[`L2_POISON:`L2_SZ_LO] ), // c1 inst 28:0
1676 .sel0(arb_mux4_c1sel_px2_n),
1677 .sel1(arb_mux4_c1sel_px2)
1678 );
1679
1680// Upper part : 40:29
1681
1682
1683l2t_arbdec_dp_msff_macro__stack_18c__width_17 ff_inst1_c1 // BS & SR 11/04/03, MB grows to 32
1684 (
1685 .scan_in(ff_inst1_c1_scanin),
1686 .scan_out(ff_inst1_c1_scanout),
1687 .din({mux4_inst_px2[`L2_BUFID_HI:`L2_BUFID_HI-3],mux4_inst_px2[`L2_RSVD],mux4_inst_px2[`L2_FBF:`L2_ENTRY_LO]}),
1688 .clk(l2clk),
1689 .dout({arbdp_inst_c1_rep1[`L2_BUFID_HI:`L2_BUFID_HI-3],arbdp_inst_c1_rep[`L2_RSVD],arbdp_inst_c1[`L2_FBF:`L2_ENTRY_LO]}),
1690 .en(1'b1),
1691 .se(se),
1692 .siclk(siclk),
1693 .soclk(soclk),
1694 .pce_ov(pce_ov),
1695 .stop(stop)
1696 );
1697
1698l2t_arbdec_dp_msff_macro__stack_12c__width_12 ff_inst1_c2 // BS & SR 11/04/03, MB grows to 32
1699 (
1700 .scan_in(ff_inst1_c2_scanin),
1701 .scan_out(ff_inst1_c2_scanout),
1702 .din(arbdp_inst_c1[`L2_FBF:`L2_ENTRY_LO]),
1703 .clk(l2clk),
1704 .dout(arbdp_inst_c2[`L2_FBF:`L2_ENTRY_LO]),
1705 .en(1'b1),
1706 .se(se),
1707 .siclk(siclk),
1708 .soclk(soclk),
1709 .pce_ov(pce_ov),
1710 .stop(stop)
1711 );
1712
1713l2t_arbdec_dp_msff_macro__stack_12c__width_12 ff_inst1_c3 // BS & SR 11/04/03, MB grows to 32
1714 (
1715 .scan_in(ff_inst1_c3_scanin),
1716 .scan_out(ff_inst1_c3_scanout),
1717 .din(arbdp_inst_c2[`L2_FBF:`L2_ENTRY_LO]),
1718 .clk(l2clk),
1719 .dout(arbdp_inst_c3[`L2_FBF:`L2_ENTRY_LO]),
1720 .en(1'b1),
1721 .se(se),
1722 .siclk(siclk),
1723 .soclk(soclk),
1724 .pce_ov(pce_ov),
1725 .stop(stop)
1726 );
1727
1728// Lower part : 28:0 and siu ecc bits
1729
1730//////////////////////// SNOOP ECC CALCULATIONS ////////////////////////////////
1731//mux_macro mux_snp_ecc (width=7,mux=aonpe,ports=2,stack=7c)
1732// (
1733// .dout (snp_ecc_px2[6:0]),
1734// .din0 (snpd_ecc_px2[6:0]),
1735// .din1 (mbdata_snp_ecc_px2[6:0]),
1736// .sel0 (arb_mux2_snpsel_px2),
1737// .sel1 (arb_mux2_snpsel_px2_n)
1738// );
1739
1740l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_6c__width_6 mux_mux1_snp_ecc1_px2
1741 (
1742 .dout(mux1_snp_ecc_px2[5:0]) ,
1743 .din0(mbdata_snp_ecc_px2[5:0]),
1744 .din1(6'b0),
1745 .sel0(arb_mux1_mbsel_px2),
1746 .sel1(arb_mux1_mbsel_px2_n)
1747 );
1748
1749
1750l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_6c__width_6 mux_mux2_snp_ecc2_px2
1751 (
1752 .dout(mux2_snp_ecc_px2[5:0]) ,
1753 .din0(snpd_ecc_px2[5:0]),
1754 .din1(mux1_snp_ecc_px2[5:0]),
1755 .sel0(arb_mux2_snpsel_px2),
1756 .sel1(arb_mux2_snpsel_px2_n)
1757 );
1758l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_6c__width_6 mux_mux3_snp_ecc2_px2
1759 (
1760 .dout(mux3_snp_ecc_px2[5:0]) ,
1761 .din0(mux2_snp_ecc_px2[5:0]),
1762 .din1(6'b0),
1763 .sel0(arb_mux3_bufsel_px2),
1764 .sel1(arb_mux3_bufsel_px2_n)
1765 );
1766
1767
1768l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_6c__width_6 mux_mux4_snp_ecc2_px2
1769 (
1770 .dout(mux4_snp_ecc_px2[5:0]) ,
1771 .din0(mux3_snp_ecc_px2[5:0]),
1772 .din1(arbdp_snp_ecc_c1[5:0] ),
1773 .sel0(arb_mux4_c1sel_px2_n),
1774 .sel1(arb_mux4_c1sel_px2)
1775 );
1776
1777//////////////////////// SNOOP ECC CALCULATIONS ////////////////////////////////
1778l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c1 // BS and SR 11/12/03 N2 Xbar Packet format change
1779 (
1780 .scan_in(ff_inst2_c1_scanin),
1781 .scan_out(ff_inst2_c1_scanout),
1782 .din({mux4_snp_ecc_px2[5:0],mux4_inst_px2[`L2_POISON:`L2_SZ_LO]}),
1783 .clk(l2clk),
1784 .dout({arbdp_snp_ecc_c1[5:0],arbdp_inst_c1[`L2_POISON:`L2_SZ_LO]}),
1785 .en(1'b1),
1786 .se(se),
1787 .siclk(siclk),
1788 .soclk(soclk),
1789 .pce_ov(pce_ov),
1790 .stop(stop)
1791 );
1792
1793
1794l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c2 // BS and SR 11/12/03 N2 Xbar Packet format change
1795 (
1796 .scan_in(ff_inst2_c2_scanin),
1797 .scan_out(ff_inst2_c2_scanout),
1798 .din({arbdp_snp_ecc_c1[5:0],arbdp_inst_c1[`L2_POISON:`L2_SZ_LO]}),
1799 .clk(l2clk),
1800 .dout({arbdp_snp_ecc_c2[5:0],arbdp_inst_c2[`L2_POISON:`L2_SZ_LO]}),
1801 .en(1'b1),
1802 .se(se),
1803 .siclk(siclk),
1804 .soclk(soclk),
1805 .pce_ov(pce_ov),
1806 .stop(stop)
1807 );
1808
1809l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c3 // BS and SR 11/12/03 N2 Xbar Packet format change
1810 (
1811 .scan_in(ff_inst2_c3_scanin),
1812 .scan_out(ff_inst2_c3_scanout),
1813 .din({arbdp_snp_ecc_c2[5:0],arbdp_inst_c2[`L2_POISON:`L2_SZ_LO]}),
1814 .clk(l2clk),
1815 .dout({arbdp_snp_ecc_c3[5:0],arbdp_inst_c3[`L2_POISON:`L2_SZ_LO]}),
1816 .en(1'b1),
1817 .se(se),
1818 .siclk(siclk),
1819 .soclk(soclk),
1820 .pce_ov(pce_ov),
1821 .stop(stop)
1822 );
1823
1824
1825l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c4 // BS and SR 11/12/03 N2 Xbar Packet format change
1826 (
1827 .scan_in(ff_inst2_c4_scanin),
1828 .scan_out(ff_inst2_c4_scanout),
1829 .din({arbdp_snp_ecc_c3[5:0],arbdp_inst_c3[`L2_POISON:`L2_SZ_LO]}),
1830 .clk(l2clk),
1831 .dout({arbdp_snp_ecc_c4[5:0],arbdp_inst_c4[`L2_POISON:`L2_SZ_LO]}),
1832 .en(1'b1),
1833 .se(se),
1834 .siclk(siclk),
1835 .soclk(soclk),
1836 .pce_ov(pce_ov),
1837 .stop(stop)
1838 );
1839
1840l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c5 // BS and SR 11/12/03 N2 Xbar Packet format change
1841 (
1842 .scan_in(ff_inst2_c5_scanin),
1843 .scan_out(ff_inst2_c5_scanout),
1844 .din({arbdp_snp_ecc_c4[5:0],arbdp_inst_c4[`L2_POISON:`L2_SZ_LO]}),
1845 .clk(l2clk),
1846 .dout({arbdp_snp_ecc_c5[5:0],arbdp_inst_c5[`L2_POISON:`L2_SZ_LO]}),
1847 .en(1'b1),
1848 .se(se),
1849 .siclk(siclk),
1850 .soclk(soclk),
1851 .pce_ov(pce_ov),
1852 .stop(stop)
1853 );
1854
1855// BS 03/11/04 extra cycle for mem access
1856
1857l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c52 // BS and SR 11/12/03 N2 Xbar Packet format change
1858 (
1859 .scan_in(ff_inst2_c52_scanin),
1860 .scan_out(ff_inst2_c52_scanout),
1861 .din({arbdp_snp_ecc_c5[5:0],arbdp_inst_c5[`L2_POISON:`L2_SZ_LO]}),
1862 .clk(l2clk),
1863 .dout({arbdp_snp_ecc_c52[5:0],arbdp_inst_c52[`L2_POISON:`L2_SZ_LO]}),
1864 .en(1'b1),
1865 .se(se),
1866 .siclk(siclk),
1867 .soclk(soclk),
1868 .pce_ov(pce_ov),
1869 .stop(stop)
1870 );
1871
1872
1873l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c6 // BS and SR 11/12/03 N2 Xbar Packet format change
1874 (
1875 .scan_in(ff_inst2_c6_scanin),
1876 .scan_out(ff_inst2_c6_scanout),
1877 .din({arbdp_snp_ecc_c52[5:0],arbdp_inst_c52[`L2_POISON:`L2_SZ_LO]}),
1878 .clk(l2clk),
1879 .dout({arbdp_snp_ecc_c6[5:0],arbdp_inst_c6[`L2_POISON:`L2_SZ_LO]}),
1880 .en(1'b1),
1881 .se(se),
1882 .siclk(siclk),
1883 .soclk(soclk),
1884 .pce_ov(pce_ov),
1885 .stop(stop)
1886 );
1887
1888
1889l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c7 //BS and SR 11/12/03 N2 Xbar Packet format change
1890 (
1891 .scan_in(ff_inst2_c7_scanin),
1892 .scan_out(ff_inst2_c7_scanout),
1893 .din({arbdp_snp_ecc_c6[5:0],arbdp_inst_c6[`L2_POISON:`L2_SZ_LO]}),
1894 .clk(l2clk),
1895 .dout({arbdp_snp_ecc_c7[5:0],arbdp_inst_c7[`L2_POISON:`L2_SZ_LO]}),
1896 .en(1'b1),
1897 .se(se),
1898 .siclk(siclk),
1899 .soclk(soclk),
1900 .pce_ov(pce_ov),
1901 .stop(stop)
1902 );
1903
1904l2t_arbdec_dp_msff_macro__stack_35c__width_35 ff_inst2_c8 //BS and SR 11/12/03 N2 Xbar Packet format change
1905 (
1906 .scan_in(ff_inst2_c8_scanin),
1907 .scan_out(ff_inst2_c8_scanout),
1908 .din({arbdp_snp_ecc_c7[5:0],arbdp_inst_c7[`L2_POISON:`L2_SZ_LO]}),
1909 .clk(l2clk),
1910 .dout({arbdec_snpd_ecc_c8[5:0],arbdec_arbdp_inst_c8[`L2_POISON:`L2_SZ_LO]}),
1911 .en(1'b1),
1912 .se(se),
1913 .siclk(siclk),
1914 .soclk(soclk),
1915 .pce_ov(pce_ov),
1916 .stop(stop)
1917 );
1918
1919assign arbdec_snpd_ecc_c8[6] = 1'b0;
1920
1921//////////////////////////////////////////////////////
1922// C1 Bits used in decode
1923//////////////////////////////////////////////////////
1924
1925assign arbdec_arbdp_poison_c1 = 1'b0;
1926
1927// For timing reasons will duplicate
1928//assign arbdec_arbdp_inst_way_c1 = arbdp_inst_c1[`L2_BUFID_HI:`L2_BUFID_HI-3] ;
1929assign arbdec_arbdp_inst_way_c1 = arbdp_inst_c1_rep1[`L2_BUFID_HI:`L2_BUFID_HI-3] ;
1930
1931assign arbdec_arbdp_inst_fb_c1 = arbdp_inst_c1[`L2_FBF] ; // used by
1932 // arb to turn off fb hits.
1933 // BS & SR 11/04/03, MB grows to 32
1934assign arbdec_arbdp_evict_c1 = arbdp_inst_c1[`L2_EVICT] ; // BS & SR 11/04/03, MB grows to 32
1935
1936assign arbdec_arbdp_tecc_c1 = arbdp_inst_c1[`L2_TECC] ;// BS & SR 11/04/03, MB grows to 32
1937
1938assign arbdec_arbdp_inst_mb_c1 = arbdp_inst_c1[`L2_MBF] ;// BS & SR 11/04/03, MB grows to 32
1939
1940assign arbdec_arbdp_inst_rsvd_c1_1 = arbdp_inst_c1_rep[`L2_RSVD] ;
1941
1942assign arbdec_arbdp_inst_nc_c1 = arbdp_inst_c1[`L2_NC] ;
1943
1944assign arbdec_arbdp_inst_ctrue_c1 = arbdp_inst_c1[`L2_CTRUE] ;// BS & SR 11/04/03, MB grows to 32
1945
1946assign arbdec_arbdp_inst_size_c1[`L2_SZ_HI:`L2_SZ_LO] =
1947 arbdp_inst_c1[`L2_SZ_HI:`L2_SZ_LO];
1948
1949// assign arbdec_arbdp_inst_bufidhi_c1 = (arbdp_inst_c1[`L2_BUFID_HI] & ~arbdec_arbdp_rdma_inst_c1);
1950
1951
1952l2t_arbdec_dp_inv_macro__width_1 inv_arbdec_arbdp_rdma_inst_c1
1953 (
1954 .dout (arbdec_arbdp_rdma_inst_c1_n),
1955 .din (arbdec_arbdp_rdma_inst_c1)
1956 );
1957
1958l2t_arbdec_dp_and_macro__width_1 and_arbdec_arbdp_inst_bufidhi_c1
1959 (
1960 .dout (arbdec_arbdp_inst_bufidhi_c1),
1961 .din0 (arbdp_inst_c1[`L2_BUFID_HI]),
1962 .din1 (arbdec_arbdp_rdma_inst_c1_n)
1963 );
1964
1965
1966
1967assign arbdec_arbdp_inst_bufid1_c1 = arbdp_inst_c1[`L2_BUFID_HI-1];
1968
1969assign arbdec_arbdp_inst_rqtyp_c1 = arbdp_inst_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] ;
1970
1971assign arbdec_arbdp_inst_mb_entry_c1 = arbdp_inst_c1[`L2_ENTRY_HI:`L2_ENTRY_LO] ;// BS & SR 11/04/03, MB grows to 32
1972
1973assign arbdec_arbdp_rdma_inst_c1 = arbdp_inst_c1[`L2_RSVD] ;
1974
1975//////////////////////////////////////////////////////
1976// C2 Bits used in decode
1977//////////////////////////////////////////////////////
1978
1979assign arbdec_arbdp_inst_bufidlo_c2 = arbdp_inst_c2[`L2_BUFID_LO] ;
1980
1981assign arbdec_arbdp_inst_mb_c2 = arbdp_inst_c2[`L2_MBF] ; // used in vuad dp, arb// BS & SR 11/04/03, MB grows to 32
1982
1983assign arbdec_arbdp_inst_fb_c2 = arbdp_inst_c2[`L2_FBF] ; // fill instruction in C2.
1984 // output to arb and vuad dp.// BS & SR 11/04/03, MB grows to 32
1985assign arbdec_arbdp_inst_dep_c2 = arbdp_inst_c2[`L2_DEP];// BS & SR 11/04/03, MB grows to 32
1986
1987assign arbdec_arbdp_rdma_inst_c2 = arbdp_inst_c2[`L2_RSVD] ;
1988
1989assign arbdec_arbdp_inst_rqtyp_c2 = arbdp_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] ;
1990
1991assign arbdec_arbdp_inst_way_c2 = arbdp_inst_c2[`L2_BUFID_HI:`L2_BUFID_HI-3] ;
1992
1993//////////////////////////////////////////////////////
1994// C3 Bits used in decode
1995//////////////////////////////////////////////////////
1996
1997assign arbdec_arbdp_inst_mb_c3 = arbdp_inst_c3[`L2_MBF] ;// BS & SR 11/04/03, MB grows to 32
1998
1999//assign arbdec_arbdp_inst_fb_c3 = arbdp_inst_c3[`L2_FBF] ;// BS & SR 11/04/03, MB grows to 32
2000
2001assign arbdec_arbdp_inst_tecc_c3 = arbdp_inst_c3[`L2_TECC];// BS & SR 11/04/03, MB grows to 32
2002
2003assign arbdec_arbdp_inst_way_c3 = arbdp_inst_c3[`L2_BUFID_HI:`L2_BUFID_HI-3] ;
2004
2005assign arbdec_arbdp_rdma_entry_c3 = arbdp_inst_c3[`L2_RDMA_HI:`L2_RDMA_LO] ;
2006
2007assign arbdec_arbdp_inst_nc_c3 = arbdp_inst_c3[`L2_NC] ;
2008
2009assign arbdec_arbdp_l1way_c3 = arbdp_inst_c3[`L2_L1WY_HI:`L2_L1WY_LO] ;
2010
2011//////////////////////////////////////////////////////
2012// C5+ Bits used in decode
2013//////////////////////////////////////////////////////
2014
2015// Debug related signals
2016assign arbdec_csr_ttype_c6[4:0] = arbdp_inst_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] ;
2017assign arbdec_csr_vcid_c6[5:0] = {arbdp_inst_c6[`L2_CPUID_HI:`L2_CPUID_LO],
2018 arbdp_inst_c6[`L2_TID_HI:`L2_TID_LO]};
2019
2020assign l2t_dbg_xbar_vcid[5:0] = {arbdp_inst_c6[`L2_CPUID_HI:`L2_CPUID_LO],
2021 arbdp_inst_c6[`L2_TID_HI:`L2_TID_LO]} ;
2022
2023assign arbdec_arbdp_int_bcast_c5 = arbdp_inst_c5[`L2_NC] ;
2024assign arbdec_arbdp_inst_rqtyp_c6 = arbdp_inst_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] ;
2025assign arbdec_arbdp_inst_bufidhi_c8 = arbdec_arbdp_inst_c8[`L2_BUFID_HI]; // to l2t_misbuf_ctl to force compare result = 1
2026 // on a CAS1 from Core with PCX[116] = 1'b1
2027 // to indicate Notdata
2028
2029
2030
2031//////////////////////////////////////////////////////
2032// CTAG sent to l2b
2033// Ctag<23:0> = { Ordered,read_bit,PES bits,tag[15:0]}
2034//////////////////////////////////////////////////////
2035//assign arbdec_ctag_c6[14:0] = { arbadr_arbdp_byte_addr_c6[1:0], // BS and SR 11/12/03 N2 Xbar Packet format change
2036// arbdp_inst_c6[`L2_RQTYP_LO], // rd
2037// arbdp_inst_c6[`L2_RQTYP_HI:`L2_RQTYP_HI-1], // ctag 11:10
2038// arbdp_inst_c6[`L2_CPUID_HI:`L2_CPUID_LO], // ctag 9:7
2039// arbdp_inst_c6[`L2_TID_HI-1:`L2_L1WY_LO] } ; // ctag 6:0
2040
2041// Phase 2 : SIU inteface and packet format change 2/7/04
2042
2043assign arbdec_ctag_c6[31:0] = {
2044 arbdp_inst_c6[`L2_POISON], // J bit
2045 arbdp_snp_ecc_c6[5:0], // RAS implementation 14/10/04
2046 1'b0,
2047 arbdp_inst_c6[`L2_RQTYP_HI-1], // O bit
2048 arbdp_inst_c6[`L2_CPUID_HI:`L2_CPUID_LO], // PES
2049 arbadr_arbdp_byte_addr_c6[2:0], // CBA
2050 arbdp_inst_c6[`L2_RQTYP_LO], // RDD
2051 arbdp_inst_c6[`L2_TID_HI:`L2_SZ_LO] }; // tag 15:0
2052
2053
2054// Fields that go to oque for return to the
2055// sparcs
2056
2057assign arbdec_arbdp_inst_l1way_c7 = arbdp_inst_c7[`L2_L1WY_HI:`L2_L1WY_LO] ;
2058assign arbdec_arbdp_inst_size_c7 = arbdp_inst_c7[`L2_SZ_HI:`L2_SZ_LO] ;
2059assign arbdec_arbdp_inst_tid_c7 = arbdp_inst_c7[`L2_TID_HI:`L2_TID_LO] ;
2060assign arbdec_arbdp_inst_cpuid_c7 = arbdp_inst_c7[`L2_CPUID_HI:`L2_CPUID_LO] ;
2061assign arbdec_arbdp_inst_nc_c7 = arbdp_inst_c7[`L2_NC] ;
2062
2063
2064
2065
2066l2t_arbdec_dp_msff_macro__stack_18c__width_18 ff_inst_size_c8
2067 (.din({l2t_mb2_wdata_r2[7:0],sel_diag_store_data_c7,sel_diag_store_data_c7_n,arbdec_arbdp_inst_size_c7[7:0]}), .clk(l2clk),
2068 .scan_in(ff_inst_size_c8_scanin),
2069 .scan_out(ff_inst_size_c8_scanout),
2070 .dout({l2t_mb2_wdata_r3[7:0],sel_diag_store_data_c8,sel_diag_store_data_c8_n,arbdec_arbdp_inst_size_c8[7:0]}), .en(1'b1),
2071 .se(se),
2072 .siclk(siclk),
2073 .soclk(soclk),
2074 .pce_ov(pce_ov),
2075 .stop(stop)
2076);
2077
2078// BS and SR 12/22/03, store ack generation for diagnostic store
2079l2t_arbdec_dp_inv_macro__width_1 inv_sel_diag_store_data_c8
2080 (
2081 .dout (sel_diag_store_data_c7_n ),
2082 .din (sel_diag_store_data_c7 )
2083 );
2084
2085
2086// BS and SR 1/30/04, bmask for store ack generation , including diagnostic store
2087l2t_arbdec_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_8c__width_8 mux_st_ack_bmask
2088 (
2089 .dout (st_ack_bmask_unbuff[7:0]),
2090 .din0 (arbdec_arbdp_inst_size_c8[7:0]),
2091 .din1 (arbdec_arbdp_inst_size_c7[7:0]),
2092 .sel0 (sel_diag_store_data_c8), // for diagnostic store ack cases
2093 .sel1 (sel_diag_store_data_c8_n) // for default cases
2094 );
2095
2096l2t_arbdec_dp_buff_macro__dbuff_32x__stack_8c__width_8 buff_st_ack_bmask
2097 (
2098 .dout (st_ack_bmask[7:0]),
2099 .din (st_ack_bmask_unbuff[7:0])
2100 );
2101
2102
2103
2104
2105// to arb for determining if an instruction
2106// is a CAS or CASX.
2107
2108// assign arbdec_size_field_c8[1:0]= arbdec_arbdp_inst_c8[`L2_SZ_HI-1:`L2_SZ_LO] ;
2109
2110
2111// BS and SR 11/12/03 N2 Xbar Packet format change :
2112//
2113//assign arbdec_size_field_c8[1:0] = {((arbdec_arbdp_inst_c8[`L2_SZ_LO] & arbdec_arbdp_inst_c8[`L2_SZ_LO+1] &
2114// arbdec_arbdp_inst_c8[`L2_SZ_LO+2] & arbdec_arbdp_inst_c8[`L2_SZ_LO+3]) &
2115// (~arbdec_arbdp_inst_c8[`L2_SZ_HI] & ~arbdec_arbdp_inst_c8[`L2_SZ_HI-1] &
2116// ~arbdec_arbdp_inst_c8[`L2_SZ_HI-2] & ~arbdec_arbdp_inst_c8[`L2_SZ_HI-3])),
2117// // size [7:0] == 11110000
2118// ((~arbdec_arbdp_inst_c8[`L2_SZ_LO] & ~arbdec_arbdp_inst_c8[`L2_SZ_LO+1] &
2119// ~arbdec_arbdp_inst_c8[`L2_SZ_LO+2] & ~arbdec_arbdp_inst_c8[`L2_SZ_LO+3]) &
2120// (arbdec_arbdp_inst_c8[`L2_SZ_HI] & arbdec_arbdp_inst_c8[`L2_SZ_HI-1] &
2121// arbdec_arbdp_inst_c8[`L2_SZ_HI-2] & arbdec_arbdp_inst_c8[`L2_SZ_HI-3]))};
2122// // size [7:0] == 00001111
2123//
2124
2125l2t_arbdec_dp_cmp_macro__width_8 arbdec_size_field_c8_slice0
2126 (
2127 .din0 ({arbdec_arbdp_inst_c8[`L2_SZ_LO], arbdec_arbdp_inst_c8[`L2_SZ_LO+1], arbdec_arbdp_inst_c8[`L2_SZ_LO+2],
2128 arbdec_arbdp_inst_c8[`L2_SZ_LO+3], arbdec_arbdp_inst_c8[`L2_SZ_HI], arbdec_arbdp_inst_c8[`L2_SZ_HI-1],
2129 arbdec_arbdp_inst_c8[`L2_SZ_HI-2], arbdec_arbdp_inst_c8[`L2_SZ_HI-3]}),
2130 .din1 (8'b11110000),
2131 .dout (arbdec_size_field_c8[1])
2132 );
2133
2134l2t_arbdec_dp_cmp_macro__width_8 arbdec_size_field_c8_slice1
2135 (
2136 .din0 ({arbdec_arbdp_inst_c8[`L2_SZ_LO], arbdec_arbdp_inst_c8[`L2_SZ_LO+1], arbdec_arbdp_inst_c8[`L2_SZ_LO+2],
2137 arbdec_arbdp_inst_c8[`L2_SZ_LO+3], arbdec_arbdp_inst_c8[`L2_SZ_HI], arbdec_arbdp_inst_c8[`L2_SZ_HI-1],
2138 arbdec_arbdp_inst_c8[`L2_SZ_HI-2], arbdec_arbdp_inst_c8[`L2_SZ_HI-3]}),
2139 .din1 (8'b00001111),
2140 .dout (arbdec_size_field_c8[0])
2141 );
2142
2143
2144 // cpu id in C3,C4,C5,C6 to arb for
2145 // directory invalidation mask calculation.
2146// C6 and C7 cpuid are used in direvec_ctl for
2147 // dirvec mux selects
2148assign arbdec_arbdp_cpuid_c2 = arbdp_inst_c2[`L2_CPUID_HI:`L2_CPUID_LO] ; // BS 03/25/04 for partial bank/core modes support
2149assign arbdec_arbdp_cpuid_c5 = arbdp_inst_c5[`L2_CPUID_HI:`L2_CPUID_LO] ;
2150
2151///////////////////////////////////////////////////////////////////
2152// Prfetch ICE decode
2153///////////////////////////////////////////////////////////////////
2154// For timing reasons will redo this logic
2155
2156//assign arbdec_pf_ice_inst_c1 = ~arbdec_arbdp_inst_rsvd_c1_1 &
2157// arbdec_arbdp_inst_bufid1_c1 & arbdec_arbdp_inst_bufidhi_c1 & // inv bit = 1, pf bit =1
2158// ( arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ ) ;
2159
2160l2t_arbdec_dp_inv_macro__dinv_16x__stack_8c__width_6 inv_req_type
2161 (
2162 .dout({req_type_n[4:0],arbdec_arbdp_inst_rsvd_c1_1_n}),
2163 .din({arbdec_arbdp_inst_rqtyp_c1[`L2_RQTYP_HI:`L2_RQTYP_LO],arbdec_arbdp_inst_rsvd_c1_1})
2164 );
2165
2166l2t_arbdec_dp_nand_macro__dnand_16x__ports_3__stack_3r__width_1 nand_pf_ice_instr_1
2167 (
2168 .dout (req_type_n_1),
2169 .din0 (req_type_n[0]),
2170 .din1 (req_type_n[1]),
2171 .din2 (req_type_n[2])
2172 );
2173
2174l2t_arbdec_dp_nand_macro__dnand_16x__ports_2__stack_3r__width_1 nand_pf_ice_instr
2175 (
2176 .dout (req_type_n_2),
2177 .din0 (req_type_n[3]),
2178 .din1 (req_type_n[4])
2179 );
2180
2181l2t_arbdec_dp_nor_macro__dnor_16x__ports_2__stack_3r__width_1 nor_pf_ice_instr1
2182 (
2183 .dout (its_a_load),
2184 .din0 (req_type_n_1),
2185 .din1 (req_type_n_2)
2186 );
2187
2188l2t_arbdec_dp_and_macro__dnand_16x__ports_3__stack_3r__width_1 nand_inv_pf_bit_notrsvd
2189 (
2190 .dout (pf_ice_qual),
2191 .din0 (arbdec_arbdp_inst_rsvd_c1_1_n),
2192 .din1 (arbdec_arbdp_inst_bufid1_c1),
2193 .din2 (arbdec_arbdp_inst_bufidhi_c1)
2194 );
2195
2196
2197l2t_arbdec_dp_and_macro__dinv_32x__dnand_24x__ports_2__stack_3r__width_1 nand_pf_ice_instr_fnl
2198 (
2199 .dout (arbdec_pf_ice_inst_c1),
2200 .din0 (pf_ice_qual),
2201 .din1 (its_a_load)
2202 );
2203
2204/////////////////////////////////////////////////////////////
2205// MBDATA MBIST SIGNALS
2206/////////////////////////////////////////////////////////////
2207
2208
2209l2t_arbdec_dp_msff_macro__stack_32c__width_32 ff_mb_data_read_data0
2210 (
2211 .scan_in(ff_mb_data_read_data0_scanin),
2212 .scan_out(ff_mb_data_read_data0_scanout),
2213 .dout (mb_data_read_data_r1[95:64]),
2214 .din (mb_data_read_data[95:64]),
2215 .clk (l2clk),
2216 .en (1'b1),
2217 .se(se),
2218 .siclk(siclk),
2219 .soclk(soclk),
2220 .pce_ov(pce_ov),
2221 .stop(stop)
2222 );
2223
2224l2t_arbdec_dp_msff_macro__stack_32c__width_32 ff_mb_data_read_data1
2225 (
2226 .scan_in(ff_mb_data_read_data1_scanin),
2227 .scan_out(ff_mb_data_read_data1_scanout),
2228 .dout (mb_data_read_data_r1[127:96]),
2229 .din (mb_data_read_data[127:96]),
2230 .clk (l2clk),
2231 .en (1'b1),
2232 .se(se),
2233 .siclk(siclk),
2234 .soclk(soclk),
2235 .pce_ov(pce_ov),
2236 .stop(stop)
2237 );
2238
2239
2240
2241l2t_arbdec_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_mb_data_read_data0
2242 (
2243 .dout (mbdata_cmp_data[31:0]),
2244 .din0 (mb_data_read_data_r1[95:64]),
2245 .din1 (mb_data_read_data_r1[127:96]),
2246 .sel0 (mbdata_cmp_sel[2]),
2247 .sel1 (mbdata_cmp_sel[3])
2248 );
2249
2250l2t_arbdec_dp_cmp_macro__dcmp_8x__width_32 cmp_mbdata_cmp_data
2251 (
2252 .dout (mbdata_fail_unreg),
2253 .din0 ({4{l2t_mb2_wdata_r4[7:0]}}),
2254 .din1 (mbdata_cmp_data[31:0])
2255 );
2256
2257l2t_arbdec_dp_msff_macro__stack_32c__width_28 ff_mbdata_mbist_reg
2258 (
2259 .scan_in(ff_mbdata_mbist_reg_scanin),
2260 .scan_out(ff_mbdata_mbist_reg_scanout),
2261 .dout ({mbdata_fail,
2262 mbdata_fail_top,
2263 l2t_mb2_wdata_r1[7:0],
2264 l2t_mb2_wdata_r2[7:0],
2265 l2t_mb2_wdata_r4[7:0],
2266 misbuf_buf_rd_en_r1,
2267 misbuf_buf_rd_en_r2}),
2268 .din ({mbdata_fail_top_or_bot,
2269 mbdata_fail_unreg_w,
2270 l2t_mb2_wdata[7:0],
2271 l2t_mb2_wdata_r1[7:0],
2272 l2t_mb2_wdata_r3[7:0],
2273 misbuf_buf_rd_en,
2274 misbuf_buf_rd_en_r1}),
2275 .clk (l2clk),
2276 .en (1'b1),
2277 .se(se),
2278 .siclk(siclk),
2279 .soclk(soclk),
2280 .pce_ov(pce_ov),
2281 .stop(stop)
2282 );
2283
2284l2t_arbdec_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c__width_1 mux_mbdata_fail_unreg
2285 (
2286 .dout (mbdata_fail_unreg_w),
2287 .din0 (mbdata_fail_unreg),
2288 .din1 (1'b1),
2289 .sel0 (misbuf_buf_rd_en_r2_qual),
2290 .sel1 (misbuf_buf_rd_en_r2_n)
2291 );
2292
2293l2t_arbdec_dp_inv_macro__width_1 inv_misbuf_buf_rd_en_r2
2294 (
2295 .dout (misbuf_buf_rd_en_r2_n),
2296 .din (misbuf_buf_rd_en_r2_qual)
2297 );
2298
2299
2300l2t_arbdec_dp_and_macro__width_2 and_enable_mbdata_rd
2301 (
2302 .dout ({misbuf_buf_rd_en_r2_qual,mbdata_fail_top_or_bot}),
2303 .din0 ({mbdata_test_active, mbdata_fail_top}),
2304 .din1 ({misbuf_buf_rd_en_r2, mbdata_fail_bot})
2305 );
2306
2307l2t_arbdec_dp_or_macro__width_1 or_mbdata_mbist_active
2308 (
2309 .dout (mbdata_test_active),
2310 .din0 (mbdata_cmp_sel[3]),
2311 .din1 (mbdata_cmp_sel[2])
2312 );
2313
2314
2315// fixscan start:
2316assign ff_read_mbdata_reg_inst1_scanin = scan_in ;
2317assign ff_mbdata_snp_ecc_scanin = ff_read_mbdata_reg_inst1_scanout;
2318assign ff_read_mbdata_reg_inst2_scanin = ff_mbdata_snp_ecc_scanout;
2319assign ff_inst1_c1_scanin = ff_read_mbdata_reg_inst2_scanout;
2320assign ff_inst1_c2_scanin = ff_inst1_c1_scanout ;
2321assign ff_inst1_c3_scanin = ff_inst1_c2_scanout ;
2322assign ff_inst2_c1_scanin = ff_inst1_c3_scanout ;
2323assign ff_inst2_c2_scanin = ff_inst2_c1_scanout ;
2324assign ff_inst2_c3_scanin = ff_inst2_c2_scanout ;
2325assign ff_inst2_c4_scanin = ff_inst2_c3_scanout ;
2326assign ff_inst2_c5_scanin = ff_inst2_c4_scanout ;
2327assign ff_inst2_c52_scanin = ff_inst2_c5_scanout ;
2328assign ff_inst2_c6_scanin = ff_inst2_c52_scanout ;
2329assign ff_inst2_c7_scanin = ff_inst2_c6_scanout ;
2330assign ff_inst2_c8_scanin = ff_inst2_c7_scanout ;
2331assign ff_inst_size_c8_scanin = ff_inst2_c8_scanout ;
2332assign ff_mb_data_read_data0_scanin = ff_inst_size_c8_scanout ;
2333assign ff_mb_data_read_data1_scanin = ff_mb_data_read_data0_scanout;
2334assign ff_mbdata_mbist_reg_scanin = ff_mb_data_read_data1_scanout;
2335assign scan_out = ff_mbdata_mbist_reg_scanout;
2336// fixscan end:
2337endmodule
2338
2339
2340
2341
2342
2343
2344// any PARAMS parms go into naming of macro
2345
2346module l2t_arbdec_dp_msff_macro__stack_8c__width_8 (
2347 din,
2348 clk,
2349 en,
2350 se,
2351 scan_in,
2352 siclk,
2353 soclk,
2354 pce_ov,
2355 stop,
2356 dout,
2357 scan_out);
2358wire l1clk;
2359wire siclk_out;
2360wire soclk_out;
2361wire [6:0] so;
2362
2363 input [7:0] din;
2364
2365
2366 input clk;
2367 input en;
2368 input se;
2369 input scan_in;
2370 input siclk;
2371 input soclk;
2372 input pce_ov;
2373 input stop;
2374
2375
2376
2377 output [7:0] dout;
2378
2379
2380 output scan_out;
2381
2382
2383
2384
2385cl_dp1_l1hdr_8x c0_0 (
2386.l2clk(clk),
2387.pce(en),
2388.aclk(siclk),
2389.bclk(soclk),
2390.l1clk(l1clk),
2391 .se(se),
2392 .pce_ov(pce_ov),
2393 .stop(stop),
2394 .siclk_out(siclk_out),
2395 .soclk_out(soclk_out)
2396);
2397dff #(8) d0_0 (
2398.l1clk(l1clk),
2399.siclk(siclk_out),
2400.soclk(soclk_out),
2401.d(din[7:0]),
2402.si({scan_in,so[6:0]}),
2403.so({so[6:0],scan_out}),
2404.q(dout[7:0])
2405);
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426endmodule
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440// any PARAMS parms go into naming of macro
2441
2442module l2t_arbdec_dp_msff_macro__stack_7c__width_7 (
2443 din,
2444 clk,
2445 en,
2446 se,
2447 scan_in,
2448 siclk,
2449 soclk,
2450 pce_ov,
2451 stop,
2452 dout,
2453 scan_out);
2454wire l1clk;
2455wire siclk_out;
2456wire soclk_out;
2457wire [5:0] so;
2458
2459 input [6:0] din;
2460
2461
2462 input clk;
2463 input en;
2464 input se;
2465 input scan_in;
2466 input siclk;
2467 input soclk;
2468 input pce_ov;
2469 input stop;
2470
2471
2472
2473 output [6:0] dout;
2474
2475
2476 output scan_out;
2477
2478
2479
2480
2481cl_dp1_l1hdr_8x c0_0 (
2482.l2clk(clk),
2483.pce(en),
2484.aclk(siclk),
2485.bclk(soclk),
2486.l1clk(l1clk),
2487 .se(se),
2488 .pce_ov(pce_ov),
2489 .stop(stop),
2490 .siclk_out(siclk_out),
2491 .soclk_out(soclk_out)
2492);
2493dff #(7) d0_0 (
2494.l1clk(l1clk),
2495.siclk(siclk_out),
2496.soclk(soclk_out),
2497.d(din[6:0]),
2498.si({scan_in,so[5:0]}),
2499.so({so[5:0],scan_out}),
2500.q(dout[6:0])
2501);
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522endmodule
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536// any PARAMS parms go into naming of macro
2537
2538module l2t_arbdec_dp_msff_macro__stack_29c__width_29 (
2539 din,
2540 clk,
2541 en,
2542 se,
2543 scan_in,
2544 siclk,
2545 soclk,
2546 pce_ov,
2547 stop,
2548 dout,
2549 scan_out);
2550wire l1clk;
2551wire siclk_out;
2552wire soclk_out;
2553wire [27:0] so;
2554
2555 input [28:0] din;
2556
2557
2558 input clk;
2559 input en;
2560 input se;
2561 input scan_in;
2562 input siclk;
2563 input soclk;
2564 input pce_ov;
2565 input stop;
2566
2567
2568
2569 output [28:0] dout;
2570
2571
2572 output scan_out;
2573
2574
2575
2576
2577cl_dp1_l1hdr_8x c0_0 (
2578.l2clk(clk),
2579.pce(en),
2580.aclk(siclk),
2581.bclk(soclk),
2582.l1clk(l1clk),
2583 .se(se),
2584 .pce_ov(pce_ov),
2585 .stop(stop),
2586 .siclk_out(siclk_out),
2587 .soclk_out(soclk_out)
2588);
2589dff #(29) d0_0 (
2590.l1clk(l1clk),
2591.siclk(siclk_out),
2592.soclk(soclk_out),
2593.d(din[28:0]),
2594.si({scan_in,so[27:0]}),
2595.so({so[27:0],scan_out}),
2596.q(dout[28:0])
2597);
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618endmodule
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628//
2629// invert macro
2630//
2631//
2632
2633
2634
2635
2636
2637module l2t_arbdec_dp_inv_macro__width_1 (
2638 din,
2639 dout);
2640 input [0:0] din;
2641 output [0:0] dout;
2642
2643
2644
2645
2646
2647
2648inv #(1) d0_0 (
2649.in(din[0:0]),
2650.out(dout[0:0])
2651);
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661endmodule
2662
2663
2664
2665
2666
2667// general mux macro for pass-gate and and-or muxes with/wout priority encoders
2668// also for pass-gate with decoder
2669
2670
2671
2672
2673
2674// any PARAMS parms go into naming of macro
2675
2676module l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_12c__width_12 (
2677 din0,
2678 sel0,
2679 din1,
2680 sel1,
2681 dout);
2682wire buffout0;
2683wire buffout1;
2684
2685 input [11:0] din0;
2686 input sel0;
2687 input [11:0] din1;
2688 input sel1;
2689 output [11:0] dout;
2690
2691
2692
2693
2694
2695cl_dp1_muxbuff2_8x c0_0 (
2696 .in0(sel0),
2697 .in1(sel1),
2698 .out0(buffout0),
2699 .out1(buffout1)
2700);
2701mux2s #(12) d0_0 (
2702 .sel0(buffout0),
2703 .sel1(buffout1),
2704 .in0(din0[11:0]),
2705 .in1(din1[11:0]),
2706.dout(dout[11:0])
2707);
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721endmodule
2722
2723
2724// general mux macro for pass-gate and and-or muxes with/wout priority encoders
2725// also for pass-gate with decoder
2726
2727
2728
2729
2730
2731// any PARAMS parms go into naming of macro
2732
2733module l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_29c__width_29 (
2734 din0,
2735 sel0,
2736 din1,
2737 sel1,
2738 dout);
2739wire buffout0;
2740wire buffout1;
2741
2742 input [28:0] din0;
2743 input sel0;
2744 input [28:0] din1;
2745 input sel1;
2746 output [28:0] dout;
2747
2748
2749
2750
2751
2752cl_dp1_muxbuff2_8x c0_0 (
2753 .in0(sel0),
2754 .in1(sel1),
2755 .out0(buffout0),
2756 .out1(buffout1)
2757);
2758mux2s #(29) d0_0 (
2759 .sel0(buffout0),
2760 .sel1(buffout1),
2761 .in0(din0[28:0]),
2762 .in1(din1[28:0]),
2763.dout(dout[28:0])
2764);
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778endmodule
2779
2780
2781
2782
2783
2784
2785// any PARAMS parms go into naming of macro
2786
2787module l2t_arbdec_dp_msff_macro__stack_18c__width_17 (
2788 din,
2789 clk,
2790 en,
2791 se,
2792 scan_in,
2793 siclk,
2794 soclk,
2795 pce_ov,
2796 stop,
2797 dout,
2798 scan_out);
2799wire l1clk;
2800wire siclk_out;
2801wire soclk_out;
2802wire [15:0] so;
2803
2804 input [16:0] din;
2805
2806
2807 input clk;
2808 input en;
2809 input se;
2810 input scan_in;
2811 input siclk;
2812 input soclk;
2813 input pce_ov;
2814 input stop;
2815
2816
2817
2818 output [16:0] dout;
2819
2820
2821 output scan_out;
2822
2823
2824
2825
2826cl_dp1_l1hdr_8x c0_0 (
2827.l2clk(clk),
2828.pce(en),
2829.aclk(siclk),
2830.bclk(soclk),
2831.l1clk(l1clk),
2832 .se(se),
2833 .pce_ov(pce_ov),
2834 .stop(stop),
2835 .siclk_out(siclk_out),
2836 .soclk_out(soclk_out)
2837);
2838dff #(17) d0_0 (
2839.l1clk(l1clk),
2840.siclk(siclk_out),
2841.soclk(soclk_out),
2842.d(din[16:0]),
2843.si({scan_in,so[15:0]}),
2844.so({so[15:0],scan_out}),
2845.q(dout[16:0])
2846);
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867endmodule
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881// any PARAMS parms go into naming of macro
2882
2883module l2t_arbdec_dp_msff_macro__stack_12c__width_12 (
2884 din,
2885 clk,
2886 en,
2887 se,
2888 scan_in,
2889 siclk,
2890 soclk,
2891 pce_ov,
2892 stop,
2893 dout,
2894 scan_out);
2895wire l1clk;
2896wire siclk_out;
2897wire soclk_out;
2898wire [10:0] so;
2899
2900 input [11:0] din;
2901
2902
2903 input clk;
2904 input en;
2905 input se;
2906 input scan_in;
2907 input siclk;
2908 input soclk;
2909 input pce_ov;
2910 input stop;
2911
2912
2913
2914 output [11:0] dout;
2915
2916
2917 output scan_out;
2918
2919
2920
2921
2922cl_dp1_l1hdr_8x c0_0 (
2923.l2clk(clk),
2924.pce(en),
2925.aclk(siclk),
2926.bclk(soclk),
2927.l1clk(l1clk),
2928 .se(se),
2929 .pce_ov(pce_ov),
2930 .stop(stop),
2931 .siclk_out(siclk_out),
2932 .soclk_out(soclk_out)
2933);
2934dff #(12) d0_0 (
2935.l1clk(l1clk),
2936.siclk(siclk_out),
2937.soclk(soclk_out),
2938.d(din[11:0]),
2939.si({scan_in,so[10:0]}),
2940.so({so[10:0],scan_out}),
2941.q(dout[11:0])
2942);
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963endmodule
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973// general mux macro for pass-gate and and-or muxes with/wout priority encoders
2974// also for pass-gate with decoder
2975
2976
2977
2978
2979
2980// any PARAMS parms go into naming of macro
2981
2982module l2t_arbdec_dp_mux_macro__mux_aonpe__ports_2__stack_6c__width_6 (
2983 din0,
2984 sel0,
2985 din1,
2986 sel1,
2987 dout);
2988wire buffout0;
2989wire buffout1;
2990
2991 input [5:0] din0;
2992 input sel0;
2993 input [5:0] din1;
2994 input sel1;
2995 output [5:0] dout;
2996
2997
2998
2999
3000
3001cl_dp1_muxbuff2_8x c0_0 (
3002 .in0(sel0),
3003 .in1(sel1),
3004 .out0(buffout0),
3005 .out1(buffout1)
3006);
3007mux2s #(6) d0_0 (
3008 .sel0(buffout0),
3009 .sel1(buffout1),
3010 .in0(din0[5:0]),
3011 .in1(din1[5:0]),
3012.dout(dout[5:0])
3013);
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027endmodule
3028
3029
3030
3031
3032
3033
3034// any PARAMS parms go into naming of macro
3035
3036module l2t_arbdec_dp_msff_macro__stack_35c__width_35 (
3037 din,
3038 clk,
3039 en,
3040 se,
3041 scan_in,
3042 siclk,
3043 soclk,
3044 pce_ov,
3045 stop,
3046 dout,
3047 scan_out);
3048wire l1clk;
3049wire siclk_out;
3050wire soclk_out;
3051wire [33:0] so;
3052
3053 input [34:0] din;
3054
3055
3056 input clk;
3057 input en;
3058 input se;
3059 input scan_in;
3060 input siclk;
3061 input soclk;
3062 input pce_ov;
3063 input stop;
3064
3065
3066
3067 output [34:0] dout;
3068
3069
3070 output scan_out;
3071
3072
3073
3074
3075cl_dp1_l1hdr_8x c0_0 (
3076.l2clk(clk),
3077.pce(en),
3078.aclk(siclk),
3079.bclk(soclk),
3080.l1clk(l1clk),
3081 .se(se),
3082 .pce_ov(pce_ov),
3083 .stop(stop),
3084 .siclk_out(siclk_out),
3085 .soclk_out(soclk_out)
3086);
3087dff #(35) d0_0 (
3088.l1clk(l1clk),
3089.siclk(siclk_out),
3090.soclk(soclk_out),
3091.d(din[34:0]),
3092.si({scan_in,so[33:0]}),
3093.so({so[33:0],scan_out}),
3094.q(dout[34:0])
3095);
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116endmodule
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126//
3127// and macro for ports = 2,3,4
3128//
3129//
3130
3131
3132
3133
3134
3135module l2t_arbdec_dp_and_macro__width_1 (
3136 din0,
3137 din1,
3138 dout);
3139 input [0:0] din0;
3140 input [0:0] din1;
3141 output [0:0] dout;
3142
3143
3144
3145
3146
3147
3148and2 #(1) d0_0 (
3149.in0(din0[0:0]),
3150.in1(din1[0:0]),
3151.out(dout[0:0])
3152);
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162endmodule
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172// any PARAMS parms go into naming of macro
3173
3174module l2t_arbdec_dp_msff_macro__stack_18c__width_18 (
3175 din,
3176 clk,
3177 en,
3178 se,
3179 scan_in,
3180 siclk,
3181 soclk,
3182 pce_ov,
3183 stop,
3184 dout,
3185 scan_out);
3186wire l1clk;
3187wire siclk_out;
3188wire soclk_out;
3189wire [16:0] so;
3190
3191 input [17:0] din;
3192
3193
3194 input clk;
3195 input en;
3196 input se;
3197 input scan_in;
3198 input siclk;
3199 input soclk;
3200 input pce_ov;
3201 input stop;
3202
3203
3204
3205 output [17:0] dout;
3206
3207
3208 output scan_out;
3209
3210
3211
3212
3213cl_dp1_l1hdr_8x c0_0 (
3214.l2clk(clk),
3215.pce(en),
3216.aclk(siclk),
3217.bclk(soclk),
3218.l1clk(l1clk),
3219 .se(se),
3220 .pce_ov(pce_ov),
3221 .stop(stop),
3222 .siclk_out(siclk_out),
3223 .soclk_out(soclk_out)
3224);
3225dff #(18) d0_0 (
3226.l1clk(l1clk),
3227.siclk(siclk_out),
3228.soclk(soclk_out),
3229.d(din[17:0]),
3230.si({scan_in,so[16:0]}),
3231.so({so[16:0],scan_out}),
3232.q(dout[17:0])
3233);
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254endmodule
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3265// also for pass-gate with decoder
3266
3267
3268
3269
3270
3271// any PARAMS parms go into naming of macro
3272
3273module l2t_arbdec_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_8c__width_8 (
3274 din0,
3275 sel0,
3276 din1,
3277 sel1,
3278 dout);
3279wire buffout0;
3280wire buffout1;
3281
3282 input [7:0] din0;
3283 input sel0;
3284 input [7:0] din1;
3285 input sel1;
3286 output [7:0] dout;
3287
3288
3289
3290
3291
3292cl_dp1_muxbuff2_8x c0_0 (
3293 .in0(sel0),
3294 .in1(sel1),
3295 .out0(buffout0),
3296 .out1(buffout1)
3297);
3298mux2s #(8) d0_0 (
3299 .sel0(buffout0),
3300 .sel1(buffout1),
3301 .in0(din0[7:0]),
3302 .in1(din1[7:0]),
3303.dout(dout[7:0])
3304);
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318endmodule
3319
3320
3321//
3322// buff macro
3323//
3324//
3325
3326
3327
3328
3329
3330module l2t_arbdec_dp_buff_macro__dbuff_32x__stack_8c__width_8 (
3331 din,
3332 dout);
3333 input [7:0] din;
3334 output [7:0] dout;
3335
3336
3337
3338
3339
3340
3341buff #(8) d0_0 (
3342.in(din[7:0]),
3343.out(dout[7:0])
3344);
3345
3346
3347
3348
3349
3350
3351
3352
3353endmodule
3354
3355
3356
3357
3358
3359//
3360// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
3361//
3362//
3363
3364
3365
3366
3367
3368module l2t_arbdec_dp_cmp_macro__width_8 (
3369 din0,
3370 din1,
3371 dout);
3372 input [7:0] din0;
3373 input [7:0] din1;
3374 output dout;
3375
3376
3377
3378
3379
3380
3381cmp #(8) m0_0 (
3382.in0(din0[7:0]),
3383.in1(din1[7:0]),
3384.out(dout)
3385);
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396endmodule
3397
3398
3399
3400
3401
3402//
3403// invert macro
3404//
3405//
3406
3407
3408
3409
3410
3411module l2t_arbdec_dp_inv_macro__dinv_16x__stack_8c__width_6 (
3412 din,
3413 dout);
3414 input [5:0] din;
3415 output [5:0] dout;
3416
3417
3418
3419
3420
3421
3422inv #(6) d0_0 (
3423.in(din[5:0]),
3424.out(dout[5:0])
3425);
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435endmodule
3436
3437
3438
3439
3440
3441//
3442// nand macro for ports = 2,3,4
3443//
3444//
3445
3446
3447
3448
3449
3450module l2t_arbdec_dp_nand_macro__dnand_16x__ports_3__stack_3r__width_1 (
3451 din0,
3452 din1,
3453 din2,
3454 dout);
3455 input [0:0] din0;
3456 input [0:0] din1;
3457 input [0:0] din2;
3458 output [0:0] dout;
3459
3460
3461
3462
3463
3464
3465nand3 #(1) d0_0 (
3466.in0(din0[0:0]),
3467.in1(din1[0:0]),
3468.in2(din2[0:0]),
3469.out(dout[0:0])
3470);
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480endmodule
3481
3482
3483
3484
3485
3486//
3487// nand macro for ports = 2,3,4
3488//
3489//
3490
3491
3492
3493
3494
3495module l2t_arbdec_dp_nand_macro__dnand_16x__ports_2__stack_3r__width_1 (
3496 din0,
3497 din1,
3498 dout);
3499 input [0:0] din0;
3500 input [0:0] din1;
3501 output [0:0] dout;
3502
3503
3504
3505
3506
3507
3508nand2 #(1) d0_0 (
3509.in0(din0[0:0]),
3510.in1(din1[0:0]),
3511.out(dout[0:0])
3512);
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522endmodule
3523
3524
3525
3526
3527
3528//
3529// nor macro for ports = 2,3
3530//
3531//
3532
3533
3534
3535
3536
3537module l2t_arbdec_dp_nor_macro__dnor_16x__ports_2__stack_3r__width_1 (
3538 din0,
3539 din1,
3540 dout);
3541 input [0:0] din0;
3542 input [0:0] din1;
3543 output [0:0] dout;
3544
3545
3546
3547
3548
3549
3550nor2 #(1) d0_0 (
3551.in0(din0[0:0]),
3552.in1(din1[0:0]),
3553.out(dout[0:0])
3554);
3555
3556
3557
3558
3559
3560
3561
3562endmodule
3563
3564
3565
3566
3567
3568//
3569// and macro for ports = 2,3,4
3570//
3571//
3572
3573
3574
3575
3576
3577module l2t_arbdec_dp_and_macro__dnand_16x__ports_3__stack_3r__width_1 (
3578 din0,
3579 din1,
3580 din2,
3581 dout);
3582 input [0:0] din0;
3583 input [0:0] din1;
3584 input [0:0] din2;
3585 output [0:0] dout;
3586
3587
3588
3589
3590
3591
3592and3 #(1) d0_0 (
3593.in0(din0[0:0]),
3594.in1(din1[0:0]),
3595.in2(din2[0:0]),
3596.out(dout[0:0])
3597);
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607endmodule
3608
3609
3610
3611
3612
3613//
3614// and macro for ports = 2,3,4
3615//
3616//
3617
3618
3619
3620
3621
3622module l2t_arbdec_dp_and_macro__dinv_32x__dnand_24x__ports_2__stack_3r__width_1 (
3623 din0,
3624 din1,
3625 dout);
3626 input [0:0] din0;
3627 input [0:0] din1;
3628 output [0:0] dout;
3629
3630
3631
3632
3633
3634
3635and2 #(1) d0_0 (
3636.in0(din0[0:0]),
3637.in1(din1[0:0]),
3638.out(dout[0:0])
3639);
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649endmodule
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659// any PARAMS parms go into naming of macro
3660
3661module l2t_arbdec_dp_msff_macro__stack_32c__width_32 (
3662 din,
3663 clk,
3664 en,
3665 se,
3666 scan_in,
3667 siclk,
3668 soclk,
3669 pce_ov,
3670 stop,
3671 dout,
3672 scan_out);
3673wire l1clk;
3674wire siclk_out;
3675wire soclk_out;
3676wire [30:0] so;
3677
3678 input [31:0] din;
3679
3680
3681 input clk;
3682 input en;
3683 input se;
3684 input scan_in;
3685 input siclk;
3686 input soclk;
3687 input pce_ov;
3688 input stop;
3689
3690
3691
3692 output [31:0] dout;
3693
3694
3695 output scan_out;
3696
3697
3698
3699
3700cl_dp1_l1hdr_8x c0_0 (
3701.l2clk(clk),
3702.pce(en),
3703.aclk(siclk),
3704.bclk(soclk),
3705.l1clk(l1clk),
3706 .se(se),
3707 .pce_ov(pce_ov),
3708 .stop(stop),
3709 .siclk_out(siclk_out),
3710 .soclk_out(soclk_out)
3711);
3712dff #(32) d0_0 (
3713.l1clk(l1clk),
3714.siclk(siclk_out),
3715.soclk(soclk_out),
3716.d(din[31:0]),
3717.si({scan_in,so[30:0]}),
3718.so({so[30:0],scan_out}),
3719.q(dout[31:0])
3720);
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741endmodule
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3752// also for pass-gate with decoder
3753
3754
3755
3756
3757
3758// any PARAMS parms go into naming of macro
3759
3760module l2t_arbdec_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 (
3761 din0,
3762 sel0,
3763 din1,
3764 sel1,
3765 dout);
3766wire buffout0;
3767wire buffout1;
3768
3769 input [31:0] din0;
3770 input sel0;
3771 input [31:0] din1;
3772 input sel1;
3773 output [31:0] dout;
3774
3775
3776
3777
3778
3779cl_dp1_muxbuff2_8x c0_0 (
3780 .in0(sel0),
3781 .in1(sel1),
3782 .out0(buffout0),
3783 .out1(buffout1)
3784);
3785mux2s #(32) d0_0 (
3786 .sel0(buffout0),
3787 .sel1(buffout1),
3788 .in0(din0[31:0]),
3789 .in1(din1[31:0]),
3790.dout(dout[31:0])
3791);
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805endmodule
3806
3807
3808//
3809// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
3810//
3811//
3812
3813
3814
3815
3816
3817module l2t_arbdec_dp_cmp_macro__dcmp_8x__width_32 (
3818 din0,
3819 din1,
3820 dout);
3821 input [31:0] din0;
3822 input [31:0] din1;
3823 output dout;
3824
3825
3826
3827
3828
3829
3830cmp #(32) m0_0 (
3831.in0(din0[31:0]),
3832.in1(din1[31:0]),
3833.out(dout)
3834);
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845endmodule
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855// any PARAMS parms go into naming of macro
3856
3857module l2t_arbdec_dp_msff_macro__stack_32c__width_28 (
3858 din,
3859 clk,
3860 en,
3861 se,
3862 scan_in,
3863 siclk,
3864 soclk,
3865 pce_ov,
3866 stop,
3867 dout,
3868 scan_out);
3869wire l1clk;
3870wire siclk_out;
3871wire soclk_out;
3872wire [26:0] so;
3873
3874 input [27:0] din;
3875
3876
3877 input clk;
3878 input en;
3879 input se;
3880 input scan_in;
3881 input siclk;
3882 input soclk;
3883 input pce_ov;
3884 input stop;
3885
3886
3887
3888 output [27:0] dout;
3889
3890
3891 output scan_out;
3892
3893
3894
3895
3896cl_dp1_l1hdr_8x c0_0 (
3897.l2clk(clk),
3898.pce(en),
3899.aclk(siclk),
3900.bclk(soclk),
3901.l1clk(l1clk),
3902 .se(se),
3903 .pce_ov(pce_ov),
3904 .stop(stop),
3905 .siclk_out(siclk_out),
3906 .soclk_out(soclk_out)
3907);
3908dff #(28) d0_0 (
3909.l1clk(l1clk),
3910.siclk(siclk_out),
3911.soclk(soclk_out),
3912.d(din[27:0]),
3913.si({scan_in,so[26:0]}),
3914.so({so[26:0],scan_out}),
3915.q(dout[27:0])
3916);
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937endmodule
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3948// also for pass-gate with decoder
3949
3950
3951
3952
3953
3954// any PARAMS parms go into naming of macro
3955
3956module l2t_arbdec_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c__width_1 (
3957 din0,
3958 sel0,
3959 din1,
3960 sel1,
3961 dout);
3962wire buffout0;
3963wire buffout1;
3964
3965 input [0:0] din0;
3966 input sel0;
3967 input [0:0] din1;
3968 input sel1;
3969 output [0:0] dout;
3970
3971
3972
3973
3974
3975cl_dp1_muxbuff2_8x c0_0 (
3976 .in0(sel0),
3977 .in1(sel1),
3978 .out0(buffout0),
3979 .out1(buffout1)
3980);
3981mux2s #(1) d0_0 (
3982 .sel0(buffout0),
3983 .sel1(buffout1),
3984 .in0(din0[0:0]),
3985 .in1(din1[0:0]),
3986.dout(dout[0:0])
3987);
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001endmodule
4002
4003
4004//
4005// and macro for ports = 2,3,4
4006//
4007//
4008
4009
4010
4011
4012
4013module l2t_arbdec_dp_and_macro__width_2 (
4014 din0,
4015 din1,
4016 dout);
4017 input [1:0] din0;
4018 input [1:0] din1;
4019 output [1:0] dout;
4020
4021
4022
4023
4024
4025
4026and2 #(2) d0_0 (
4027.in0(din0[1:0]),
4028.in1(din1[1:0]),
4029.out(dout[1:0])
4030);
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040endmodule
4041
4042
4043
4044
4045
4046//
4047// or macro for ports = 2,3
4048//
4049//
4050
4051
4052
4053
4054
4055module l2t_arbdec_dp_or_macro__width_1 (
4056 din0,
4057 din1,
4058 dout);
4059 input [0:0] din0;
4060 input [0:0] din1;
4061 output [0:0] dout;
4062
4063
4064
4065
4066
4067
4068or2 #(1) d0_0 (
4069.in0(din0[0:0]),
4070.in1(din1[0:0]),
4071.out(dout[0:0])
4072);
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082endmodule
4083
4084
4085
4086
Full OpenSPARC design & verification tarball including full HDL.