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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_csr_ctl.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_csr_ctl.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016
1017////////////////////////////////////////////////////////////////////////
1018// Local header file includes / local defines
1019////////////////////////////////////////////////////////////////////////
1020
1021module l2t_csr_ctl (
1022 scan_out,
1023 csr_filbuf_scrub_ready,
1024 csr_l2_bypass_mode_on,
1025 csr_filbuf_l2off,
1026 csr_tag_l2off,
1027 csr_wbuf_l2off,
1028 csr_misbuf_l2off,
1029 csr_vuad_l2off,
1030 csr_l2_dir_map_on,
1031 csr_l2_steering_tid,
1032 csr_error_nceen,
1033 csr_error_ceen,
1034 csr_wr_dirpinj_en,
1035 csr_oneshot_dir_clear_c3,
1036 csr_rd_data_c8,
1037 csr_error_status_veu,
1038 csr_error_status_vec,
1039 csr_report_ldrc,
1040 csreg_report_ldrc_inpkt,
1041 notdata_higher_priority_err,
1042 arbdat_csr_inst_wr_data_c8,
1043 csreg_csr_bist_wr_en_c8,
1044 scan_in,
1045 l2clk,
1046 tcu_pce_ov,
1047 tcu_aclk,
1048 tcu_bclk,
1049 tcu_scan_en,
1050 aclk_wmr,
1051 wmr_protect,
1052 csreg_csr_erren_wr_en_c8,
1053 csreg_csr_wr_en_c8,
1054 csreg_csr_errstate_wr_en_c8,
1055 csreg_csr_errinj_wr_en_c8,
1056 csreg_l2_cmpr_reg_wr_en_c8,
1057 csreg_l2_mask_reg_wr_en_c8,
1058 arb_inst_vld_c2,
1059 csreg_csr_rd_mux4_sel_c7,
1060 csreg_csr_rd_mux_fnl_c7,
1061 arbdec_csr_ttype_c6,
1062 arbdec_csr_vcid_c6,
1063 arbadr_csr_debug_addr,
1064 csreg_wr_enable_notdata_nddm_vcid_c9,
1065 l2t_dbg_err_event,
1066 l2t_dbg_pa_match,
1067 csreg_csr_rd_mux1_sel_c7,
1068 csreg_csr_rd_mux2_sel_c7,
1069 csreg_csr_rd_mux3_sel_c7,
1070 arbadr_arbdp_csr_addr_c9,
1071 evctag_evict_addr,
1072 arbadr_rdmard_addr_c12,
1073 arb_dir_addr_c9,
1074 tag_scrub_addr_way,
1075 arbadr_data_ecc_idx,
1076 csreg_err_state_in_rw,
1077 csreg_err_state_in_mec,
1078 csreg_err_state_in_meu,
1079 csreg_err_state_in,
1080 csreg_mux1_synd_sel,
1081 csreg_mux2_synd_sel,
1082 csreg_csr_synd_wr_en,
1083 usaloc_ua_synd_c9,
1084 vlddir_vd_synd_c9,
1085 decc_lda_syndrome_c9,
1086 csreg_wr_enable_tid_c9,
1087 csreg_csr_tid_wr_en,
1088 csreg_csr_async_wr_en,
1089 set_async_c9,
1090 error_rw_en,
1091 diag_wr_en,
1092 csreg_mux1_addr_sel,
1093 csreg_mux2_addr_sel,
1094 csreg_csr_addr_wr_en,
1095 arb_dir_wr_en_c4,
1096 oque_tid_c8,
1097 csreg_csr_notdata_wr_en_c8,
1098 csreg_wr_enable_notdata_vcid_c9,
1099 csreg_csr_notdata_vcid_wr_en,
1100 csreg_notdata_err_state_in_rw,
1101 csreg_notdata_err_state_in_mend,
1102 csreg_notdata_err_state_in,
1103 csreg_notdata_diag_wr_en,
1104 csreg_notdata_error_rw_en,
1105 csreg_csr_notdata_addr_wr_en,
1106 csreg_notdata_addr_mux_sel,
1107 csr_error_status_notdata,
1108 shadow_l2erraddr_reg,
1109 shadow_notdata_reg,
1110 shadow_error_status_reg);
1111wire pce_ov;
1112wire stop;
1113wire siclk;
1114wire soclk;
1115wire se;
1116wire l1clk;
1117wire spares_scanin;
1118wire arb_inst_vld_c6;
1119wire arb_inst_vld_c7;
1120wire spares_scanout;
1121wire ff_csr_l2_control_reg_0_scanin;
1122wire ff_csr_l2_control_reg_0_scanout;
1123wire ff_csr_l2_control_reg_2to1_scanin;
1124wire ff_csr_l2_control_reg_2to1_scanout;
1125wire ff_csr_l2_control_reg_scb_int_scanin;
1126wire ff_csr_l2_control_reg_scb_int_scanout;
1127wire ff_csr_l2_control_reg_steering_scanin;
1128wire ff_csr_l2_control_reg_steering_scanout;
1129wire ff_csr_l2_control_reg_dbg_scanin;
1130wire ff_csr_l2_control_reg_dbg_scanout;
1131wire ff_csr_l2_control_reg_dir_clr_scanin;
1132wire ff_csr_l2_control_reg_dir_clr_scanout;
1133wire ff_dir_clr_d1_scanin;
1134wire ff_dir_clr_d1_scanout;
1135wire dir_clr_d1;
1136wire ff_dir_clr_d2_scanin;
1137wire ff_dir_clr_d2_scanout;
1138wire dir_clr_d2;
1139wire ff_scrub_count_scanin;
1140wire ff_scrub_count_scanout;
1141wire ff_csr_l2_erren_d1_scanin;
1142wire ff_csr_l2_erren_d1_scanout;
1143wire mbist_done;
1144wire [2:0] mbist_err;
1145wire [10:0] bist_data_prev;
1146wire ff_bist_registrer_scanin;
1147wire ff_bist_registrer_scanout;
1148wire [10:0] csr_bist_read_data_unused;
1149wire ff_csr_l2_errsynd_d1_scanin;
1150wire ff_csr_l2_errsynd_d1_scanout;
1151wire ff_inst_tid_c9_scanin;
1152wire ff_inst_tid_c9_scanout;
1153wire ff_csr_l2_erritid_d1_scanin;
1154wire ff_csr_l2_erritid_d1_scanout;
1155wire ff_async_bit_scanin;
1156wire ff_async_bit_scanout;
1157wire ff_csr_l2_errrw_d1_scanin;
1158wire ff_csr_l2_errrw_d1_scanout;
1159wire ff_csr_l2_errmeu_d1_scanin;
1160wire ff_csr_l2_errmeu_d1_scanout;
1161wire ff_csr_l2_errmec_d1_scanin;
1162wire ff_csr_l2_errmec_d1_scanout;
1163wire ff_csr_l2_errstate_d1_scanin;
1164wire ff_csr_l2_errstate_d1_scanout;
1165wire ff_csr_l2_erraddr_d1_scanin;
1166wire ff_csr_l2_erraddr_d1_scanout;
1167wire ff_csr_l2_errinj_d1_scanin;
1168wire ff_csr_l2_errinj_d1_scanout;
1169wire [63:0] csr_rd_data_c7_1;
1170wire [63:0] debug_csr_read_data;
1171wire [63:0] l2_mask_register;
1172wire [63:0] l2_compare_register;
1173wire ff_csr_rd_data_c8_scanin;
1174wire ff_csr_rd_data_c8_scanout;
1175wire ff_csr_l2_notdata_rw_d1_scanin;
1176wire ff_csr_l2_notdata_rw_d1_scanout;
1177wire ff_csr_l2_notdata_mend_d1_scanin;
1178wire ff_csr_l2_notdata_mend_d1_scanout;
1179wire ff_csr_l2_notdata_ndspnddm_d1_scanin;
1180wire ff_csr_l2_notdata_ndspnddm_d1_scanout;
1181wire sel_diag_notdata_wr;
1182wire ff_csr_l2_notdata_vcid_d1_scanin;
1183wire ff_csr_l2_notdata_vcid_d1_scanout;
1184wire ff_csr_l2_notdata_addr_d1_scanin;
1185wire ff_csr_l2_notdata_addr_d1_scanout;
1186wire [63:0] l2_compare_register_prev;
1187wire ff_l2_compare_register_scanin;
1188wire ff_l2_compare_register_scanout;
1189wire [63:0] l2_mask_register_prev;
1190wire ff_l2_mask_register_scanin;
1191wire ff_l2_mask_register_scanout;
1192wire [63:0] debug_address_inpipe;
1193wire ff_debug_address_inpipe_scanin;
1194wire ff_debug_address_inpipe_scanout;
1195wire [63:0] debug_address_inpipe_d1;
1196wire ff_instruction_vld_piped_scanin;
1197wire ff_instruction_vld_piped_scanout;
1198wire arb_inst_vld_c3;
1199wire arb_inst_vld_c4;
1200wire arb_inst_vld_c5;
1201wire arb_inst_vld_c52;
1202wire l2t_dbg_pa_match_unreg;
1203wire l2t_dbg_err_event_unreg;
1204wire ff_l2t_dbg_pa_match_scanin;
1205wire ff_l2t_dbg_pa_match_scanout;
1206wire warm_scanout_n;
1207wire warm_scanout;
1208
1209
1210output scan_out;
1211output csr_filbuf_scrub_ready; // to filbuf.
1212output csr_l2_bypass_mode_on; // to arb
1213output csr_filbuf_l2off;
1214output csr_tag_l2off;
1215output csr_wbuf_l2off;
1216output csr_misbuf_l2off;
1217output csr_vuad_l2off;
1218output csr_l2_dir_map_on; // NEW_PIN
1219output [5:0] csr_l2_steering_tid; // NEW_PIN, BS and SR 11/12/03 N2 Xbar Packet format change
1220output csr_error_nceen;
1221output csr_error_ceen;
1222output csr_wr_dirpinj_en;
1223output csr_oneshot_dir_clear_c3; // NEW_PIN left
1224
1225// STM register.
1226output [63:0] csr_rd_data_c8;
1227output csr_error_status_veu;
1228output csr_error_status_vec;
1229output csr_report_ldrc;
1230input csreg_report_ldrc_inpkt;
1231
1232output notdata_higher_priority_err;
1233
1234input [63:0] arbdat_csr_inst_wr_data_c8;// from arbdata POST_2.0 Left Replacement for mbdata*
1235input csreg_csr_bist_wr_en_c8;
1236input scan_in;
1237input l2clk;
1238input tcu_pce_ov;
1239input tcu_aclk;
1240input tcu_bclk;
1241input tcu_scan_en;
1242input aclk_wmr;
1243input wmr_protect;
1244
1245// from CSR CTL.
1246input csreg_csr_erren_wr_en_c8;
1247input csreg_csr_wr_en_c8;
1248input csreg_csr_errstate_wr_en_c8;
1249input csreg_csr_errinj_wr_en_c8;
1250
1251// debug changes
1252input csreg_l2_cmpr_reg_wr_en_c8;
1253input csreg_l2_mask_reg_wr_en_c8;
1254input arb_inst_vld_c2;
1255input [1:0] csreg_csr_rd_mux4_sel_c7;
1256input [1:0] csreg_csr_rd_mux_fnl_c7;
1257input [4:0] arbdec_csr_ttype_c6;
1258input [5:0] arbdec_csr_vcid_c6;
1259input [33:2] arbadr_csr_debug_addr;
1260
1261input csreg_wr_enable_notdata_nddm_vcid_c9;
1262output l2t_dbg_err_event;
1263output l2t_dbg_pa_match;
1264
1265
1266// read enables from csr.
1267input [3:0] csreg_csr_rd_mux1_sel_c7;
1268input csreg_csr_rd_mux2_sel_c7;
1269input [1:0] csreg_csr_rd_mux3_sel_c7;
1270
1271
1272// Address inputs.
1273input [39:4] arbadr_arbdp_csr_addr_c9 ; // c9 instruction addr from arbadr
1274input [39:6] evctag_evict_addr ; // from evctag.
1275input [39:6] arbadr_rdmard_addr_c12; // from arbadr.
1276input [10:0] arb_dir_addr_c9 ; // from arb
1277input [3:0] tag_scrub_addr_way; // from tag
1278input [8:0] arbadr_data_ecc_idx; // from arbaddr
1279
1280
1281
1282// Status register bits from csr
1283input csreg_err_state_in_rw ;
1284input csreg_err_state_in_mec ;
1285input csreg_err_state_in_meu ;
1286input [`ERR_LDAC:`ERR_LVC] csreg_err_state_in ;
1287
1288// Syndrome mux selects
1289input [1:0] csreg_mux1_synd_sel; // vuad and wr data
1290input [1:0] csreg_mux2_synd_sel; // ldau and default
1291input csreg_csr_synd_wr_en;
1292
1293// Syndrome inputs.
1294input [6:0] usaloc_ua_synd_c9;
1295input [6:0] vlddir_vd_synd_c9;
1296input [27:0] decc_lda_syndrome_c9; // from decc
1297
1298// TID
1299input csreg_wr_enable_tid_c9 ;
1300input csreg_csr_tid_wr_en;
1301
1302// ASYNC
1303input csreg_csr_async_wr_en;
1304
1305// int 5.0 changes
1306input set_async_c9; // ADDED POST_4.0
1307input error_rw_en; // ADDED POST_4.0
1308input diag_wr_en; // ADDED POST_4.0
1309
1310
1311
1312
1313// Addr
1314input [3:0] csreg_mux1_addr_sel;
1315input [2:0] csreg_mux2_addr_sel;
1316input csreg_csr_addr_wr_en;
1317
1318
1319input arb_dir_wr_en_c4;
1320input [5:0] oque_tid_c8; // From oque of l2t_oque_dp.sv, BS and SR 11/12/03 N2 Xbar Packet format change
1321
1322
1323// Notdata related signals from l2t_csreg_ctl
1324
1325input csreg_csr_notdata_wr_en_c8;
1326input csreg_wr_enable_notdata_vcid_c9;
1327input csreg_csr_notdata_vcid_wr_en;
1328input csreg_notdata_err_state_in_rw;
1329input csreg_notdata_err_state_in_mend;
1330input [`ERR_NDSP:`ERR_NDDM] csreg_notdata_err_state_in;
1331input csreg_notdata_diag_wr_en;
1332input csreg_notdata_error_rw_en;
1333input csreg_csr_notdata_addr_wr_en;
1334input [2:0] csreg_notdata_addr_mux_sel; // 0 : c9 address, 1 : siu read address, 2 : diagnostic wr address
1335
1336output csr_error_status_notdata; // a Notdata error is already logged
1337
1338//// shadow scan ports
1339
1340output [39:4] shadow_l2erraddr_reg;
1341output [`ERR_MEND:`ERR_NDADR_LO] shadow_notdata_reg;
1342output [63:0] shadow_error_status_reg;
1343
1344
1345
1346//////////////////////////////////////////////////
1347// L1 clk header
1348//////////////////////////////////////////////////
1349assign pce_ov = tcu_pce_ov;
1350assign stop = 1'b0;
1351assign siclk = tcu_aclk;
1352assign soclk = tcu_bclk;
1353assign se = tcu_scan_en;
1354
1355l2t_csr_ctl_l1clkhdr_ctl_macro clkgen (
1356 .l2clk(l2clk),
1357 .l1en(1'b1 ),
1358 .l1clk(l1clk),
1359 .pce_ov(pce_ov),
1360 .stop(stop),
1361 .se(se));
1362
1363//////////////////////////////////////////////////
1364
1365//////////////////////////////////////////
1366// Spare gate insertion
1367//////////////////////////////////////////
1368//spare_ctl_macro spares (num=10) (
1369// .scan_in(spares_scanin),
1370// .scan_out(spares_scanout),
1371// .l1clk (l1clk)
1372//);
1373wire si_0;
1374wire so_0;
1375wire spare0_flop_unused;
1376wire spare0_buf_32x_unused;
1377wire spare0_nand3_8x_unused;
1378wire spare0_inv_8x_unused;
1379wire spare0_aoi22_4x_unused;
1380wire spare0_buf_8x_unused;
1381wire spare0_oai22_4x_unused;
1382wire spare0_inv_16x_unused;
1383wire spare0_nand2_16x_unused;
1384wire spare0_nor3_4x_unused;
1385wire spare0_nand2_8x_unused;
1386wire spare0_buf_16x_unused;
1387wire spare0_nor2_16x_unused;
1388wire spare0_inv_32x_unused;
1389wire si_1;
1390wire so_1;
1391wire spare1_flop_unused;
1392wire spare1_buf_32x_unused;
1393wire spare1_nand3_8x_unused;
1394wire spare1_inv_8x_unused;
1395wire spare1_aoi22_4x_unused;
1396wire spare1_buf_8x_unused;
1397wire spare1_oai22_4x_unused;
1398wire spare1_inv_16x_unused;
1399wire spare1_nand2_16x_unused;
1400wire spare1_nor3_4x_unused;
1401wire spare1_nand2_8x_unused;
1402wire spare1_buf_16x_unused;
1403wire spare1_nor2_16x_unused;
1404wire spare1_inv_32x_unused;
1405wire si_2;
1406wire so_2;
1407wire spare2_flop_unused;
1408wire spare2_buf_32x_unused;
1409wire spare2_nand3_8x_unused;
1410wire spare2_inv_8x_unused;
1411wire spare2_aoi22_4x_unused;
1412wire spare2_buf_8x_unused;
1413wire spare2_oai22_4x_unused;
1414wire spare2_inv_16x_unused;
1415wire spare2_nand2_16x_unused;
1416wire spare2_nor3_4x_unused;
1417wire spare2_nand2_8x_unused;
1418wire spare2_buf_16x_unused;
1419wire spare2_nor2_16x_unused;
1420wire spare2_inv_32x_unused;
1421wire si_3;
1422wire so_3;
1423wire spare3_flop_unused;
1424wire spare3_buf_32x_unused;
1425wire spare3_nand3_8x_unused;
1426wire spare3_inv_8x_unused;
1427wire spare3_aoi22_4x_unused;
1428wire spare3_buf_8x_unused;
1429wire spare3_oai22_4x_unused;
1430wire spare3_inv_16x_unused;
1431wire spare3_nand2_16x_unused;
1432wire spare3_nor3_4x_unused;
1433wire spare3_nand2_8x_unused;
1434wire spare3_buf_16x_unused;
1435wire spare3_nor2_16x_unused;
1436wire spare3_inv_32x_unused;
1437wire si_4;
1438wire so_4;
1439wire spare4_flop_unused;
1440wire spare4_buf_32x_unused;
1441wire spare4_nand3_8x_unused;
1442wire spare4_inv_8x_unused;
1443wire spare4_aoi22_4x_unused;
1444wire spare4_buf_8x_unused;
1445wire spare4_oai22_4x_unused;
1446wire spare4_inv_16x_unused;
1447wire spare4_nand2_16x_unused;
1448wire spare4_nor3_4x_unused;
1449wire spare4_nand2_8x_unused;
1450wire spare4_buf_16x_unused;
1451wire spare4_nor2_16x_unused;
1452wire spare4_inv_32x_unused;
1453wire si_5;
1454wire so_5;
1455wire spare5_flop_unused;
1456wire spare5_buf_32x_unused;
1457wire spare5_nand3_8x_unused;
1458wire spare5_inv_8x_unused;
1459wire spare5_aoi22_4x_unused;
1460wire spare5_buf_8x_unused;
1461wire spare5_oai22_4x_unused;
1462wire spare5_inv_16x_unused;
1463wire spare5_nand2_16x_unused;
1464wire spare5_nor3_4x_unused;
1465wire spare5_nand2_8x_unused;
1466wire spare5_buf_16x_unused;
1467wire spare5_nor2_16x_unused;
1468wire spare5_inv_32x_unused;
1469wire si_6;
1470wire so_6;
1471wire spare6_flop_unused;
1472wire spare6_buf_32x_unused;
1473wire spare6_nand3_8x_unused;
1474wire spare6_inv_8x_unused;
1475wire spare6_aoi22_4x_unused;
1476wire spare6_buf_8x_unused;
1477wire spare6_oai22_4x_unused;
1478wire spare6_inv_16x_unused;
1479wire spare6_nand2_16x_unused;
1480wire spare6_nor3_4x_unused;
1481wire spare6_nand2_8x_unused;
1482wire spare6_buf_16x_unused;
1483wire spare6_nor2_16x_unused;
1484wire spare6_inv_32x_unused;
1485wire si_7;
1486wire so_7;
1487wire spare7_flop_unused;
1488wire spare7_buf_32x_unused;
1489wire spare7_nand3_8x_unused;
1490wire spare7_inv_8x_unused;
1491wire spare7_aoi22_4x_unused;
1492wire spare7_buf_8x_unused;
1493wire spare7_oai22_4x_unused;
1494wire spare7_inv_16x_unused;
1495wire spare7_nand2_16x_unused;
1496wire spare7_nor3_4x_unused;
1497wire spare7_nand2_8x_unused;
1498wire spare7_buf_16x_unused;
1499wire spare7_nor2_16x_unused;
1500wire spare7_inv_32x_unused;
1501wire si_8;
1502wire so_8;
1503wire spare8_flop_unused;
1504wire spare8_buf_32x_unused;
1505wire spare8_nand3_8x_unused;
1506wire spare8_inv_8x_unused;
1507wire spare8_aoi22_4x_unused;
1508wire spare8_buf_8x_unused;
1509wire spare8_oai22_4x_unused;
1510wire spare8_inv_16x_unused;
1511wire spare8_nand2_16x_unused;
1512wire spare8_nor3_4x_unused;
1513wire spare8_nand2_8x_unused;
1514wire spare8_buf_16x_unused;
1515wire spare8_nor2_16x_unused;
1516wire spare8_inv_32x_unused;
1517wire si_9;
1518wire so_9;
1519wire spare9_flop_unused;
1520wire spare9_buf_32x_unused;
1521wire spare9_nand3_8x_unused;
1522wire spare9_inv_8x_unused;
1523wire spare9_aoi22_4x_unused;
1524wire spare9_buf_8x_unused;
1525wire spare9_oai22_4x_unused;
1526wire spare9_inv_16x_unused;
1527wire spare9_nand2_16x_unused;
1528wire spare9_nor3_4x_unused;
1529wire spare9_nand2_8x_unused;
1530wire spare9_buf_16x_unused;
1531wire spare9_nor2_16x_unused;
1532wire spare9_inv_32x_unused;
1533
1534cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
1535 .siclk(siclk),
1536 .soclk(soclk),
1537 .si(si_0),
1538 .so(so_0),
1539 .d(1'b0),
1540 .q(spare0_flop_unused));
1541assign si_0 = spares_scanin;
1542
1543cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
1544 .out(spare0_buf_32x_unused));
1545cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
1546 .in1(1'b1),
1547 .in2(1'b1),
1548 .out(spare0_nand3_8x_unused));
1549cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
1550 .out(spare0_inv_8x_unused));
1551cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
1552 .in01(1'b1),
1553 .in10(1'b1),
1554 .in11(1'b1),
1555 .out(spare0_aoi22_4x_unused));
1556cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
1557 .out(spare0_buf_8x_unused));
1558cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
1559 .in01(1'b1),
1560 .in10(1'b1),
1561 .in11(1'b1),
1562 .out(spare0_oai22_4x_unused));
1563cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
1564 .out(spare0_inv_16x_unused));
1565cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
1566 .in1(1'b1),
1567 .out(spare0_nand2_16x_unused));
1568cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
1569 .in1(1'b0),
1570 .in2(1'b0),
1571 .out(spare0_nor3_4x_unused));
1572cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
1573 .in1(1'b1),
1574 .out(spare0_nand2_8x_unused));
1575cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
1576 .out(spare0_buf_16x_unused));
1577cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
1578 .in1(1'b0),
1579 .out(spare0_nor2_16x_unused));
1580cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
1581 .out(spare0_inv_32x_unused));
1582
1583cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
1584 .siclk(siclk),
1585 .soclk(soclk),
1586 .si(si_1),
1587 .so(so_1),
1588 .d(1'b0),
1589 .q(spare1_flop_unused));
1590assign si_1 = so_0;
1591
1592cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
1593 .out(spare1_buf_32x_unused));
1594cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
1595 .in1(1'b1),
1596 .in2(1'b1),
1597 .out(spare1_nand3_8x_unused));
1598cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
1599 .out(spare1_inv_8x_unused));
1600cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
1601 .in01(1'b1),
1602 .in10(1'b1),
1603 .in11(1'b1),
1604 .out(spare1_aoi22_4x_unused));
1605cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
1606 .out(spare1_buf_8x_unused));
1607cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
1608 .in01(1'b1),
1609 .in10(1'b1),
1610 .in11(1'b1),
1611 .out(spare1_oai22_4x_unused));
1612cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
1613 .out(spare1_inv_16x_unused));
1614cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
1615 .in1(1'b1),
1616 .out(spare1_nand2_16x_unused));
1617cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
1618 .in1(1'b0),
1619 .in2(1'b0),
1620 .out(spare1_nor3_4x_unused));
1621cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
1622 .in1(1'b1),
1623 .out(spare1_nand2_8x_unused));
1624cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
1625 .out(spare1_buf_16x_unused));
1626cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
1627 .in1(1'b0),
1628 .out(spare1_nor2_16x_unused));
1629cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
1630 .out(spare1_inv_32x_unused));
1631
1632cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
1633 .siclk(siclk),
1634 .soclk(soclk),
1635 .si(si_2),
1636 .so(so_2),
1637 .d(1'b0),
1638 .q(spare2_flop_unused));
1639assign si_2 = so_1;
1640
1641cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
1642 .out(spare2_buf_32x_unused));
1643cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
1644 .in1(1'b1),
1645 .in2(1'b1),
1646 .out(spare2_nand3_8x_unused));
1647cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
1648 .out(spare2_inv_8x_unused));
1649cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
1650 .in01(1'b1),
1651 .in10(1'b1),
1652 .in11(1'b1),
1653 .out(spare2_aoi22_4x_unused));
1654cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
1655 .out(spare2_buf_8x_unused));
1656cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
1657 .in01(1'b1),
1658 .in10(1'b1),
1659 .in11(1'b1),
1660 .out(spare2_oai22_4x_unused));
1661cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
1662 .out(spare2_inv_16x_unused));
1663cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
1664 .in1(1'b1),
1665 .out(spare2_nand2_16x_unused));
1666cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
1667 .in1(1'b0),
1668 .in2(1'b0),
1669 .out(spare2_nor3_4x_unused));
1670cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
1671 .in1(1'b1),
1672 .out(spare2_nand2_8x_unused));
1673cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
1674 .out(spare2_buf_16x_unused));
1675cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
1676 .in1(1'b0),
1677 .out(spare2_nor2_16x_unused));
1678cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
1679 .out(spare2_inv_32x_unused));
1680
1681cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
1682 .siclk(siclk),
1683 .soclk(soclk),
1684 .si(si_3),
1685 .so(so_3),
1686 .d(1'b0),
1687 .q(spare3_flop_unused));
1688assign si_3 = so_2;
1689
1690cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
1691 .out(spare3_buf_32x_unused));
1692cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
1693 .in1(1'b1),
1694 .in2(1'b1),
1695 .out(spare3_nand3_8x_unused));
1696cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
1697 .out(spare3_inv_8x_unused));
1698cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
1699 .in01(1'b1),
1700 .in10(1'b1),
1701 .in11(1'b1),
1702 .out(spare3_aoi22_4x_unused));
1703cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
1704 .out(spare3_buf_8x_unused));
1705cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
1706 .in01(1'b1),
1707 .in10(1'b1),
1708 .in11(1'b1),
1709 .out(spare3_oai22_4x_unused));
1710cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
1711 .out(spare3_inv_16x_unused));
1712cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
1713 .in1(1'b1),
1714 .out(spare3_nand2_16x_unused));
1715cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
1716 .in1(1'b0),
1717 .in2(1'b0),
1718 .out(spare3_nor3_4x_unused));
1719cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
1720 .in1(1'b1),
1721 .out(spare3_nand2_8x_unused));
1722cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
1723 .out(spare3_buf_16x_unused));
1724cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
1725 .in1(1'b0),
1726 .out(spare3_nor2_16x_unused));
1727cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
1728 .out(spare3_inv_32x_unused));
1729
1730cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
1731 .siclk(siclk),
1732 .soclk(soclk),
1733 .si(si_4),
1734 .so(so_4),
1735 .d(1'b0),
1736 .q(spare4_flop_unused));
1737assign si_4 = so_3;
1738
1739cl_u1_buf_32x spare4_buf_32x (.in(1'b1),
1740 .out(spare4_buf_32x_unused));
1741cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
1742 .in1(1'b1),
1743 .in2(1'b1),
1744 .out(spare4_nand3_8x_unused));
1745cl_u1_inv_8x spare4_inv_8x (.in(1'b1),
1746 .out(spare4_inv_8x_unused));
1747cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
1748 .in01(1'b1),
1749 .in10(1'b1),
1750 .in11(1'b1),
1751 .out(spare4_aoi22_4x_unused));
1752cl_u1_buf_8x spare4_buf_8x (.in(1'b1),
1753 .out(spare4_buf_8x_unused));
1754cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
1755 .in01(1'b1),
1756 .in10(1'b1),
1757 .in11(1'b1),
1758 .out(spare4_oai22_4x_unused));
1759cl_u1_inv_16x spare4_inv_16x (.in(1'b1),
1760 .out(spare4_inv_16x_unused));
1761cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
1762 .in1(1'b1),
1763 .out(spare4_nand2_16x_unused));
1764cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
1765 .in1(1'b0),
1766 .in2(1'b0),
1767 .out(spare4_nor3_4x_unused));
1768cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
1769 .in1(1'b1),
1770 .out(spare4_nand2_8x_unused));
1771cl_u1_buf_16x spare4_buf_16x (.in(1'b1),
1772 .out(spare4_buf_16x_unused));
1773cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
1774 .in1(1'b0),
1775 .out(spare4_nor2_16x_unused));
1776cl_u1_inv_32x spare4_inv_32x (.in(1'b1),
1777 .out(spare4_inv_32x_unused));
1778
1779cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
1780 .siclk(siclk),
1781 .soclk(soclk),
1782 .si(si_5),
1783 .so(so_5),
1784 .d(1'b0),
1785 .q(spare5_flop_unused));
1786assign si_5 = so_4;
1787
1788cl_u1_buf_32x spare5_buf_32x (.in(1'b1),
1789 .out(spare5_buf_32x_unused));
1790cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
1791 .in1(1'b1),
1792 .in2(1'b1),
1793 .out(spare5_nand3_8x_unused));
1794cl_u1_inv_8x spare5_inv_8x (.in(1'b1),
1795 .out(spare5_inv_8x_unused));
1796cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
1797 .in01(1'b1),
1798 .in10(1'b1),
1799 .in11(1'b1),
1800 .out(spare5_aoi22_4x_unused));
1801cl_u1_buf_8x spare5_buf_8x (.in(1'b1),
1802 .out(spare5_buf_8x_unused));
1803cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
1804 .in01(1'b1),
1805 .in10(1'b1),
1806 .in11(1'b1),
1807 .out(spare5_oai22_4x_unused));
1808cl_u1_inv_16x spare5_inv_16x (.in(1'b1),
1809 .out(spare5_inv_16x_unused));
1810cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
1811 .in1(1'b1),
1812 .out(spare5_nand2_16x_unused));
1813cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
1814 .in1(1'b0),
1815 .in2(1'b0),
1816 .out(spare5_nor3_4x_unused));
1817cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
1818 .in1(1'b1),
1819 .out(spare5_nand2_8x_unused));
1820cl_u1_buf_16x spare5_buf_16x (.in(1'b1),
1821 .out(spare5_buf_16x_unused));
1822cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
1823 .in1(1'b0),
1824 .out(spare5_nor2_16x_unused));
1825cl_u1_inv_32x spare5_inv_32x (.in(1'b1),
1826 .out(spare5_inv_32x_unused));
1827
1828cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
1829 .siclk(siclk),
1830 .soclk(soclk),
1831 .si(si_6),
1832 .so(so_6),
1833 .d(1'b0),
1834 .q(spare6_flop_unused));
1835assign si_6 = so_5;
1836
1837cl_u1_buf_32x spare6_buf_32x (.in(1'b1),
1838 .out(spare6_buf_32x_unused));
1839cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
1840 .in1(1'b1),
1841 .in2(1'b1),
1842 .out(spare6_nand3_8x_unused));
1843cl_u1_inv_8x spare6_inv_8x (.in(1'b1),
1844 .out(spare6_inv_8x_unused));
1845cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
1846 .in01(1'b1),
1847 .in10(1'b1),
1848 .in11(1'b1),
1849 .out(spare6_aoi22_4x_unused));
1850cl_u1_buf_8x spare6_buf_8x (.in(1'b1),
1851 .out(spare6_buf_8x_unused));
1852cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
1853 .in01(1'b1),
1854 .in10(1'b1),
1855 .in11(1'b1),
1856 .out(spare6_oai22_4x_unused));
1857cl_u1_inv_16x spare6_inv_16x (.in(1'b1),
1858 .out(spare6_inv_16x_unused));
1859cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
1860 .in1(1'b1),
1861 .out(spare6_nand2_16x_unused));
1862cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
1863 .in1(1'b0),
1864 .in2(1'b0),
1865 .out(spare6_nor3_4x_unused));
1866cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
1867 .in1(1'b1),
1868 .out(spare6_nand2_8x_unused));
1869cl_u1_buf_16x spare6_buf_16x (.in(1'b1),
1870 .out(spare6_buf_16x_unused));
1871cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
1872 .in1(1'b0),
1873 .out(spare6_nor2_16x_unused));
1874cl_u1_inv_32x spare6_inv_32x (.in(1'b1),
1875 .out(spare6_inv_32x_unused));
1876
1877cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
1878 .siclk(siclk),
1879 .soclk(soclk),
1880 .si(si_7),
1881 .so(so_7),
1882 .d(1'b0),
1883 .q(spare7_flop_unused));
1884assign si_7 = so_6;
1885
1886cl_u1_buf_32x spare7_buf_32x (.in(1'b1),
1887 .out(spare7_buf_32x_unused));
1888cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
1889 .in1(1'b1),
1890 .in2(1'b1),
1891 .out(spare7_nand3_8x_unused));
1892cl_u1_inv_8x spare7_inv_8x (.in(1'b1),
1893 .out(spare7_inv_8x_unused));
1894cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
1895 .in01(1'b1),
1896 .in10(1'b1),
1897 .in11(1'b1),
1898 .out(spare7_aoi22_4x_unused));
1899cl_u1_buf_8x spare7_buf_8x (.in(1'b1),
1900 .out(spare7_buf_8x_unused));
1901cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
1902 .in01(1'b1),
1903 .in10(1'b1),
1904 .in11(1'b1),
1905 .out(spare7_oai22_4x_unused));
1906cl_u1_inv_16x spare7_inv_16x (.in(1'b1),
1907 .out(spare7_inv_16x_unused));
1908cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
1909 .in1(1'b1),
1910 .out(spare7_nand2_16x_unused));
1911cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
1912 .in1(1'b0),
1913 .in2(1'b0),
1914 .out(spare7_nor3_4x_unused));
1915cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
1916 .in1(1'b1),
1917 .out(spare7_nand2_8x_unused));
1918cl_u1_buf_16x spare7_buf_16x (.in(1'b1),
1919 .out(spare7_buf_16x_unused));
1920cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
1921 .in1(1'b0),
1922 .out(spare7_nor2_16x_unused));
1923cl_u1_inv_32x spare7_inv_32x (.in(1'b1),
1924 .out(spare7_inv_32x_unused));
1925
1926cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
1927 .siclk(siclk),
1928 .soclk(soclk),
1929 .si(si_8),
1930 .so(so_8),
1931 .d(1'b0),
1932 .q(spare8_flop_unused));
1933assign si_8 = so_7;
1934
1935cl_u1_buf_32x spare8_buf_32x (.in(1'b1),
1936 .out(spare8_buf_32x_unused));
1937cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
1938 .in1(1'b1),
1939 .in2(1'b1),
1940 .out(spare8_nand3_8x_unused));
1941cl_u1_inv_8x spare8_inv_8x (.in(1'b1),
1942 .out(spare8_inv_8x_unused));
1943cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
1944 .in01(1'b1),
1945 .in10(1'b1),
1946 .in11(1'b1),
1947 .out(spare8_aoi22_4x_unused));
1948cl_u1_buf_8x spare8_buf_8x (.in(1'b1),
1949 .out(spare8_buf_8x_unused));
1950cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
1951 .in01(1'b1),
1952 .in10(1'b1),
1953 .in11(1'b1),
1954 .out(spare8_oai22_4x_unused));
1955cl_u1_inv_16x spare8_inv_16x (.in(1'b1),
1956 .out(spare8_inv_16x_unused));
1957cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
1958 .in1(1'b1),
1959 .out(spare8_nand2_16x_unused));
1960cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
1961 .in1(1'b0),
1962 .in2(1'b0),
1963 .out(spare8_nor3_4x_unused));
1964cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
1965 .in1(1'b1),
1966 .out(spare8_nand2_8x_unused));
1967cl_u1_buf_16x spare8_buf_16x (.in(1'b1),
1968 .out(spare8_buf_16x_unused));
1969cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
1970 .in1(1'b0),
1971 .out(spare8_nor2_16x_unused));
1972cl_u1_inv_32x spare8_inv_32x (.in(1'b1),
1973 .out(spare8_inv_32x_unused));
1974
1975cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
1976 .siclk(siclk),
1977 .soclk(soclk),
1978 .si(si_9),
1979 .so(so_9),
1980// BUG ID 110568 .d(1'b0), .q(spare9_flop_unused));
1981 .d(arb_inst_vld_c6), .q(arb_inst_vld_c7));
1982
1983assign si_9 = so_8;
1984
1985cl_u1_buf_32x spare9_buf_32x (.in(1'b1),
1986 .out(spare9_buf_32x_unused));
1987cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
1988 .in1(1'b1),
1989 .in2(1'b1),
1990 .out(spare9_nand3_8x_unused));
1991cl_u1_inv_8x spare9_inv_8x (.in(1'b1),
1992 .out(spare9_inv_8x_unused));
1993cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
1994 .in01(1'b1),
1995 .in10(1'b1),
1996 .in11(1'b1),
1997 .out(spare9_aoi22_4x_unused));
1998cl_u1_buf_8x spare9_buf_8x (.in(1'b1),
1999 .out(spare9_buf_8x_unused));
2000cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
2001 .in01(1'b1),
2002 .in10(1'b1),
2003 .in11(1'b1),
2004 .out(spare9_oai22_4x_unused));
2005cl_u1_inv_16x spare9_inv_16x (.in(1'b1),
2006 .out(spare9_inv_16x_unused));
2007cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
2008 .in1(1'b1),
2009 .out(spare9_nand2_16x_unused));
2010cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
2011 .in1(1'b0),
2012 .in2(1'b0),
2013 .out(spare9_nor3_4x_unused));
2014cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
2015 .in1(1'b1),
2016 .out(spare9_nand2_8x_unused));
2017cl_u1_buf_16x spare9_buf_16x (.in(1'b1),
2018 .out(spare9_buf_16x_unused));
2019cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
2020 .in1(1'b0),
2021 .out(spare9_nor2_16x_unused));
2022cl_u1_inv_32x spare9_inv_32x (.in(1'b1),
2023 .out(spare9_inv_32x_unused));
2024assign spares_scanout = so_9;
2025
2026
2027///////////////////////////////////////////
2028
2029
2030
2031
2032
2033wire [5:0] inst_tid_c9; // BS and SR 11/12/03 N2 Xbar Packet format change
2034wire [22:0] csr_l2_control_prev; // BS and SR 11/12/03 N2 Xbar Packet format change
2035wire [22:0] csr_l2_control_reg; // BS and SR 11/12/03 N2 Xbar Packet format change
2036wire [31:0] scrub_counter, scrub_counter_plus1;
2037wire [31:0] scrub_counter_p;
2038
2039wire [2:0] csr_l2_erren_prev;
2040wire [2:0] csr_l2_erren_reg;
2041
2042wire unqual_scrub_ready;
2043wire sel_scrub_zero;
2044wire [39:4] csr_l2_erraddr_reg; // int 5.0 changes
2045wire [63:0] csr_l2_errstate_reg;
2046wire [`ERR_MEND:`ERR_NDADR_LO] csr_l2_notdata_reg;
2047wire [`ERR_MEND:`ERR_NDADR_LO] rd_notdata_reg;
2048wire [1:0] csr_l2_errinj_reg;
2049wire [63:0] mux1_data_out_c7, mux2_data_out_c7;
2050
2051
2052wire csr_l2_control_prev_0_l, csr_l2_control_reg_0_l ;
2053wire [63:0] csr_rd_data_c7;
2054wire [31:0] mux1_synd_c9 ;
2055wire [63:0] csr_l2_errstate_prev;
2056wire [`ERR_MEND:`ERR_NDADR_LO] csr_l2_notdata_prev;
2057wire [12:0] scrub_addr;
2058wire [39:4] mux1_addr_c9; // int 5.0 changes
2059wire [39:4] csr_l2_erraddr_prev; // int 5.0 changes
2060wire [1:0] csr_l2_errinj_prev;
2061
2062wire [63:0] rd_errstate_reg;
2063wire dbb_rst_l;
2064wire dbg_trigger;
2065//wire error_in;
2066//wire l2t_clk_tr_prev;
2067// shadow scan
2068wire [63:0] shdw_rd_errstate_reg;
2069wire [63:0] shdw_rd_notdata_reg;
2070wire [63:0] shdw_csr_l2_erraddr_reg;
2071
2072
2073///////////////////////////////////////////////////////////////////////////////////
2074// L2 BIST CONTROL REGISTER Address<39:32>= 0xa8
2075//
2076//______________________________________________________________________________
2077//
2078// BIST_ReadOnly<12:9> BIST_WR fields<8:0>
2079//______________________________________________________________________________
2080// This register is physically located in the test stub.
2081// a 13 bit bus from the tstub is used for read.
2082///////////////////////////////////////////////////////////////////////////////////
2083
2084///////////////////////////////////////////////////////////////////////////////////
2085// L2 BANK CONTROL REgister Address<39:32> 0xa9 ;
2086//______________________________________________________________________________
2087//
2088// DIR_CLEAR DBG_EN Steering <19:15> SCB INERVal<14:3> SCB_EN direct_mapped_on L2_OFF
2089//_____________________________________________________________________________
2090// dir clr: This bit is used to perform a one shot clear of the
2091// dbg en: mux select for the dbgbus that goes to the IOB
2092// Steering id = {cpuid, tid }
2093// scrub_interval: SCB interval 12 bits
2094// scrub_enable: scb_en
2095// direct_mapped_on : direct mapped mode.
2096// l2_off: l2 off mode.
2097///////////////////////////////////////////////////////////////////////////////////
2098
2099assign csr_l2_control_prev[22:1] = arbdat_csr_inst_wr_data_c8[22:1] ; // BS and SR 11/12/03 N2 Xbar Packet format change
2100
2101//////////////
2102// L2 off bit
2103// This bit is set to
2104// 1 at POR.
2105//////////////
2106
2107
2108assign csr_l2_control_prev_0_l = ~arbdat_csr_inst_wr_data_c8[0] ;
2109
2110l2t_csr_ctl_msff_ctl_macro__en_1__width_1 ff_csr_l2_control_reg_0 // sync reset active high
2111 ( // FS:wmr_protect
2112 .scan_in(ff_csr_l2_control_reg_0_scanin),
2113 .scan_out(ff_csr_l2_control_reg_0_scanout),
2114 .siclk (aclk_wmr),
2115 .din(csr_l2_control_prev_0_l),
2116 .en(csreg_csr_wr_en_c8),
2117 .l1clk(l1clk), .dout(csr_l2_control_reg_0_l),
2118 .soclk(soclk)
2119 );
2120
2121assign csr_l2_control_reg[0] = ~csr_l2_control_reg_0_l ;
2122
2123assign csr_l2_bypass_mode_on = csr_l2_control_reg[0] ;
2124assign csr_filbuf_l2off = csr_l2_control_reg[0] ;
2125assign csr_tag_l2off = csr_l2_control_reg[0] ;
2126assign csr_wbuf_l2off = csr_l2_control_reg[0] ;
2127assign csr_misbuf_l2off = csr_l2_control_reg[0] ;
2128assign csr_vuad_l2off = csr_l2_control_reg[0] ;
2129
2130assign csr_l2_dir_map_on = csr_l2_control_reg[1] & ~csr_l2_control_reg[0]; // when both L2_OFF and L2_DIR_MAP
2131 // are 1, L2_DIR_MAP is ignored.
2132assign csr_l2_steering_tid = csr_l2_control_reg[20:15] ;
2133
2134
2135//////////////
2136// other mode bits
2137//////////////
2138l2t_csr_ctl_msff_ctl_macro__en_1__width_2 ff_csr_l2_control_reg_2to1 // sync reset active high
2139 ( // FS:wmr_protect
2140 .scan_in(ff_csr_l2_control_reg_2to1_scanin),
2141 .scan_out(ff_csr_l2_control_reg_2to1_scanout),
2142 .siclk (aclk_wmr),
2143 .din(csr_l2_control_prev[2:1]),
2144 .en(csreg_csr_wr_en_c8),
2145 .l1clk(l1clk), .dout(csr_l2_control_reg[2:1]),
2146 .soclk(soclk)
2147 );
2148
2149//////////////
2150// scrub interval.
2151//////////////
2152l2t_csr_ctl_msff_ctl_macro__en_1__width_12 ff_csr_l2_control_reg_scb_int // sync reset active high
2153 ( // FS:wmr_protect
2154 .scan_in(ff_csr_l2_control_reg_scb_int_scanin),
2155 .scan_out(ff_csr_l2_control_reg_scb_int_scanout),
2156 .siclk (aclk_wmr),
2157 .din(csr_l2_control_prev[14:3]),
2158 .en(csreg_csr_wr_en_c8),
2159 .l1clk(l1clk), .dout(csr_l2_control_reg[14:3]),
2160 .soclk(soclk)
2161 );
2162
2163//////////////
2164// steering bits + dbgen
2165//////////////
2166l2t_csr_ctl_msff_ctl_macro__en_1__width_6 ff_csr_l2_control_reg_steering // sync reset active high , BS and SR 11/12/03 N2 Xbar Packet format change
2167 ( // FS:wmr_protect
2168 .scan_in(ff_csr_l2_control_reg_steering_scanin),
2169 .scan_out(ff_csr_l2_control_reg_steering_scanout),
2170 .siclk (aclk_wmr),
2171 .din(csr_l2_control_prev[20:15]),
2172 .en(csreg_csr_wr_en_c8),
2173 .l1clk(l1clk), .dout(csr_l2_control_reg[20:15]),
2174 .soclk(soclk)
2175 );
2176
2177//////////////
2178// dbgen needs to be preserved across
2179// a reset
2180//////////////
2181
2182l2t_csr_ctl_msff_ctl_macro__en_1__width_1 ff_csr_l2_control_reg_dbg // BS and SR 11/12/03 N2 Xbar Packet format change
2183 ( // FS:wmr_protect
2184 .scan_in(ff_csr_l2_control_reg_dbg_scanin),
2185 .scan_out(ff_csr_l2_control_reg_dbg_scanout),
2186 .siclk (aclk_wmr),
2187 .din(csr_l2_control_prev[21]),
2188 .en(csreg_csr_wr_en_c8),
2189 .l1clk(l1clk), .dout(csr_l2_control_reg[21]),
2190 .soclk(soclk)
2191 );
2192
2193
2194//////////////
2195// Directory clear bit.
2196//////////////
2197l2t_csr_ctl_msff_ctl_macro__en_1__width_1 ff_csr_l2_control_reg_dir_clr // sync reset active high, BS and SR 11/12/03 N2 Xbar Packet format change
2198 ( // FS:wmr_protect
2199 .scan_in(ff_csr_l2_control_reg_dir_clr_scanin),
2200 .scan_out(ff_csr_l2_control_reg_dir_clr_scanout),
2201 .siclk (aclk_wmr),
2202 .din(csr_l2_control_prev[22]),
2203 .en(csreg_csr_wr_en_c8),
2204 .l1clk(l1clk), .dout(csr_l2_control_reg[22]),
2205 .soclk(soclk)
2206 );
2207
2208/////////////////////////
2209// Directory clear logic
2210// The dir clr bit is followed by
2211// two shadow flops.
2212// If the pattern on the two following flops is
2213// 2'b10, the directory is cleared. Else it is not.
2214// This ensures that one diagnostic write will perform
2215// only one clear without destroying the contents of the
2216// L2.ESR dir_Ctl bit.
2217/////////////////////////
2218
2219l2t_csr_ctl_msff_ctl_macro__width_1 ff_dir_clr_d1
2220 ( // FS:wmr_protect
2221 .scan_in(ff_dir_clr_d1_scanin),
2222 .scan_out(ff_dir_clr_d1_scanout),
2223 .siclk (aclk_wmr),
2224 .din(csr_l2_control_reg[22]), .l1clk(l1clk),
2225 .dout(dir_clr_d1),
2226 .soclk(soclk)
2227 );
2228
2229l2t_csr_ctl_msff_ctl_macro__width_1 ff_dir_clr_d2
2230 ( // FS:wmr_protect
2231 .scan_in(ff_dir_clr_d2_scanin),
2232 .scan_out(ff_dir_clr_d2_scanout),
2233 .siclk (aclk_wmr),
2234 .din(dir_clr_d1), .l1clk(l1clk),
2235 .dout(dir_clr_d2),
2236 .soclk(soclk)
2237 );
2238
2239assign csr_oneshot_dir_clear_c3 = (dir_clr_d1 & ~dir_clr_d2);
2240
2241
2242
2243/////////////////////////////////////////////////////////
2244// Scrub counter.
2245// The scrub interval is programmable and has a range of
2246// 1M - 4B cycles.
2247// After a scrub interval, one set of the cache is
2248// scrubbed. The scrub operation is synchronized with the
2249// occurrence of the next fill after the scrub counter
2250// expires.
2251/////////////////////////////////////////////////////////
2252
2253
2254 assign sel_scrub_zero = unqual_scrub_ready ;
2255
2256 assign scrub_counter_plus1 = scrub_counter + 32'b1;
2257
2258l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_32 mux_scrub_count
2259 (.dout(scrub_counter_p[31:0]),
2260 .din0(32'b0), .din1(scrub_counter_plus1[31:0]),
2261 .sel0(sel_scrub_zero), .sel1(~sel_scrub_zero));
2262
2263l2t_csr_ctl_msff_ctl_macro__width_32 ff_scrub_count
2264 ( // FS:wmr_protect
2265 .scan_in(ff_scrub_count_scanin),
2266 .scan_out(ff_scrub_count_scanout),
2267 .siclk (aclk_wmr),
2268 .din(scrub_counter_p[31:0]), .l1clk(l1clk),
2269 .dout(scrub_counter[31:0]),
2270 .soclk(soclk)
2271 );
2272
2273 assign unqual_scrub_ready = ( scrub_counter[31:0] ==
2274 { csr_l2_control_reg[14:3], 20'b0} ) ;
2275
2276 assign csr_filbuf_scrub_ready = unqual_scrub_ready &
2277 csr_l2_control_reg[2] ;
2278
2279/////////////////////////////////////////////////////////
2280// L2 error enable register.
2281// --------------------------
2282//DBG_TRIG_EN NCEEN CEEN
2283//---------------------------
2284/////////////////////////////////////////////////////////
2285
2286
2287 assign csr_l2_erren_prev[0] = arbdat_csr_inst_wr_data_c8[0] ;
2288 assign csr_l2_erren_prev[1] = arbdat_csr_inst_wr_data_c8[1] ;
2289 assign csr_l2_erren_prev[2] = arbdat_csr_inst_wr_data_c8[2] ;
2290
2291l2t_csr_ctl_msff_ctl_macro__en_1__width_3 ff_csr_l2_erren_d1 // sync reset active high
2292 ( // FS:wmr_protect
2293 .scan_in(ff_csr_l2_erren_d1_scanin),
2294 .scan_out(ff_csr_l2_erren_d1_scanout),
2295 .siclk (aclk_wmr),
2296 .din(csr_l2_erren_prev[2:0]),
2297 .en(csreg_csr_erren_wr_en_c8), .l1clk(l1clk),
2298 .dout(csr_l2_erren_reg[2:0]),
2299 .soclk(soclk)
2300 );
2301
2302 assign dbg_trigger = csr_l2_erren_reg[2] ;
2303 assign csr_error_nceen = csr_l2_erren_reg[1] ;
2304 assign csr_error_ceen = csr_l2_erren_reg[0] ;
2305
2306
2307////////////////////////////////////////////////////////////////////////////////
2308//
2309// BIST register
2310// This register is now in TCU hence always read as zeros
2311//
2312////////////////////////////////////////////////////////////////////////////////
2313
2314
2315assign mbist_done = 1'b0;
2316assign mbist_err = 3'b0;
2317
2318assign bist_data_prev[10:0] = {mbist_done, mbist_err[2:0], arbdat_csr_inst_wr_data_c8[6:0]};
2319
2320l2t_csr_ctl_msff_ctl_macro__en_1__width_11 ff_bist_registrer
2321 (// FS:wmr_protect
2322 .scan_in(ff_bist_registrer_scanin),
2323 .scan_out(ff_bist_registrer_scanout),
2324 .siclk (aclk_wmr),
2325 .din(bist_data_prev[10:0]),
2326 .en(csreg_csr_bist_wr_en_c8),
2327 .l1clk(l1clk),
2328 .dout(csr_bist_read_data_unused[10:0]),
2329 .soclk(soclk)
2330 );
2331
2332//////////////////////////////////////////////////////////////////////////////////
2333// L2 error status register. ( addr = ab )
2334// ------------------------------------------------------------------------------
2335// MEU MEC RW ASYN TID LDAC LDAU LDWC LDWULDRC LDRU LDSC LDSU LTC LRU LVU DAC DAU
2336//-------------------------------------------------------------------------------
2337// DRC DRU DSC DSU VEC VEU RSVD<34:32> SYND<31:0>
2338//-------------------------------------------------------------------------------
2339// Keep the old value unless the new value being written is a 1.
2340//////////////////////////////////////////////////////////////////////////////////
2341
2342
2343
2344//////////////////////////////////////
2345// SYNDROME (NON_STICKY) // int 5.0 changes
2346// * vuad errors
2347// * ldac/ldau
2348// * ldrc/ldru for rdma writes only.
2349//////////////////////////////////////
2350
2351l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_32 synd_c9_mux1 // VUAD ecc change
2352 (.dout(mux1_synd_c9[31:0]),
2353 .din0({18'b0,vlddir_vd_synd_c9[6:0],usaloc_ua_synd_c9[6:0]}),
2354 .din1({4'b0,arbdat_csr_inst_wr_data_c8[27:0]}),
2355 .sel0(csreg_mux1_synd_sel[0]),
2356 .sel1(csreg_mux1_synd_sel[1]));
2357
2358l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_32 synd_c9_mux2
2359 (.dout(csr_l2_errstate_prev[31:0]),
2360 .din0(mux1_synd_c9[31:0]),
2361 .din1({4'b0,decc_lda_syndrome_c9[27:0]}),
2362 .sel0(csreg_mux2_synd_sel[1]),
2363 .sel1(csreg_mux2_synd_sel[0]));
2364
2365l2t_csr_ctl_msff_ctl_macro__en_1__width_32 ff_csr_l2_errsynd_d1
2366 ( // FS:wmr_protect
2367 .scan_in(ff_csr_l2_errsynd_d1_scanin),
2368 .scan_out(ff_csr_l2_errsynd_d1_scanout),
2369 .siclk (aclk_wmr),
2370 .din(csr_l2_errstate_prev[31:0]),
2371 .en(csreg_csr_synd_wr_en), .l1clk(l1clk),
2372 .dout(csr_l2_errstate_reg[31:0]),
2373 .soclk(soclk)
2374
2375);
2376
2377
2378//////////////////////////////////////
2379// TID BITS
2380//////////////////////////////////////
2381
2382
2383l2t_csr_ctl_msff_ctl_macro__width_6 ff_inst_tid_c9 // BS and SR 11/12/03 N2 Xbar Packet format change
2384 ( // FS:wmr_protect
2385 .scan_in(ff_inst_tid_c9_scanin),
2386 .scan_out(ff_inst_tid_c9_scanout),
2387 .siclk (aclk_wmr),
2388 .dout(inst_tid_c9[5:0]), .l1clk(l1clk),
2389 .din(oque_tid_c8[5:0]),
2390 .soclk(soclk)
2391
2392);
2393
2394l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 mux_tid_c9 // BS and SR 11/12/03 N2 Xbar Packet format change
2395 (.dout(csr_l2_errstate_prev[`ERR_TID_HI:`ERR_TID_LO]),
2396 .din0(inst_tid_c9[5:0]),
2397 .din1(arbdat_csr_inst_wr_data_c8[`ERR_TID_HI:`ERR_TID_LO]),
2398 .sel0(csreg_wr_enable_tid_c9),
2399 .sel1(~csreg_wr_enable_tid_c9));
2400
2401l2t_csr_ctl_msff_ctl_macro__en_1__width_6 ff_csr_l2_erritid_d1 // BS and SR 11/12/03 N2 Xbar Packet format change
2402 ( // FS:wmr_protect
2403 .scan_in(ff_csr_l2_erritid_d1_scanin),
2404 .scan_out(ff_csr_l2_erritid_d1_scanout),
2405 .siclk (aclk_wmr),
2406 .din(csr_l2_errstate_prev[`ERR_TID_HI:`ERR_TID_LO]),
2407 .en(csreg_csr_tid_wr_en), .l1clk(l1clk),
2408 .dout(csr_l2_errstate_reg[`ERR_TID_HI:`ERR_TID_LO]),
2409 .soclk(soclk)
2410
2411);
2412
2413
2414//////////////////////////////////////
2415// ASYNC BIT (NON_STICKY) // int 5.0 changes
2416//////////////////////////////////////
2417
2418
2419
2420assign csr_l2_errstate_prev[`ERR_ASYNC] = // int 5.0 change
2421 ( diag_wr_en & arbdat_csr_inst_wr_data_c8[`ERR_ASYNC]) | // diag write
2422 ( set_async_c9) ; // async ld hit
2423
2424l2t_csr_ctl_msff_ctl_macro__en_1__width_1 ff_async_bit // int 5.0 change
2425 (// FS:wmr_protect
2426 .scan_in(ff_async_bit_scanin),
2427 .scan_out(ff_async_bit_scanout),
2428 .siclk (aclk_wmr),
2429 .din(csr_l2_errstate_prev[`ERR_ASYNC]), .l1clk(l1clk),
2430 .dout(csr_l2_errstate_reg[`ERR_ASYNC]), .en(csreg_csr_async_wr_en),
2431 .soclk(soclk)
2432 );
2433
2434
2435
2436//////////////////////////////////////
2437// RW BITS
2438//////////////////////////////////////
2439
2440// int 5.0 changes
2441assign csr_l2_errstate_prev[`ERR_RW] =
2442 ( diag_wr_en & arbdat_csr_inst_wr_data_c8[`ERR_RW] ) |
2443 csreg_err_state_in_rw ;
2444
2445
2446
2447l2t_csr_ctl_msff_ctl_macro__en_1__width_1 ff_csr_l2_errrw_d1 // int 5.0 changes
2448 ( // FS:wmr_protect
2449 .scan_in(ff_csr_l2_errrw_d1_scanin),
2450 .scan_out(ff_csr_l2_errrw_d1_scanout),
2451 .siclk (aclk_wmr),
2452 .din(csr_l2_errstate_prev[`ERR_RW]), .l1clk(l1clk),
2453 .dout(csr_l2_errstate_reg[`ERR_RW]), .en(error_rw_en),
2454 .soclk(soclk)
2455
2456);
2457
2458
2459//////////////////////////////////////
2460// Error bits (STICKY)
2461//////////////////////////////////////
2462
2463// int 5.0 changes
2464// assign csr_l2_errstate_prev[60] = arbdat_csr_inst_wr_data_c8[60];
2465// Reserved position in N1 and is now assignedto TID growing to 3 bits
2466
2467
2468
2469assign csr_l2_errstate_prev[`ERR_MEU] =
2470 ( ~( csreg_csr_errstate_wr_en_c8 &
2471 arbdat_csr_inst_wr_data_c8[`ERR_MEU] ) &
2472 csr_l2_errstate_reg[`ERR_MEU]
2473 ) | csreg_err_state_in_meu ;
2474
2475
2476assign csr_l2_errstate_prev[`ERR_MEC] =
2477 ( ~( csreg_csr_errstate_wr_en_c8 &
2478 arbdat_csr_inst_wr_data_c8[`ERR_MEC] ) &
2479 csr_l2_errstate_reg[`ERR_MEC]
2480 ) | csreg_err_state_in_mec ;
2481
2482assign csr_l2_errstate_prev[`ERR_LDAC:`ERR_LVC] =
2483 ( ~({20{csreg_csr_errstate_wr_en_c8}} &
2484 arbdat_csr_inst_wr_data_c8[`ERR_LDAC:`ERR_LVC]) &
2485 csr_l2_errstate_reg[`ERR_LDAC:`ERR_LVC]
2486 ) | csreg_err_state_in[`ERR_LDAC:`ERR_LVC] ;
2487
2488
2489l2t_csr_ctl_msff_ctl_macro__width_1 ff_csr_l2_errmeu_d1
2490 (// FS:wmr_protect
2491 .scan_in(ff_csr_l2_errmeu_d1_scanin),
2492 .scan_out(ff_csr_l2_errmeu_d1_scanout),
2493 .siclk (aclk_wmr),
2494 .din(csr_l2_errstate_prev[`ERR_MEU]),
2495 .l1clk(l1clk),
2496 .dout(csr_l2_errstate_reg[`ERR_MEU]),
2497 .soclk(soclk)
2498
2499);
2500
2501l2t_csr_ctl_msff_ctl_macro__width_1 ff_csr_l2_errmec_d1
2502 (// FS:wmr_protect
2503 .scan_in(ff_csr_l2_errmec_d1_scanin),
2504 .scan_out(ff_csr_l2_errmec_d1_scanout),
2505 .siclk (aclk_wmr),
2506 .din(csr_l2_errstate_prev[`ERR_MEC]),
2507 .l1clk(l1clk),
2508 .dout(csr_l2_errstate_reg[`ERR_MEC]),
2509 .soclk(soclk)
2510
2511);
2512
2513l2t_csr_ctl_msff_ctl_macro__width_20 ff_csr_l2_errstate_d1
2514 (// FS:wmr_protect
2515 .scan_in(ff_csr_l2_errstate_d1_scanin),
2516 .scan_out(ff_csr_l2_errstate_d1_scanout),
2517 .siclk (aclk_wmr),
2518 .din(csr_l2_errstate_prev[`ERR_LDAC:`ERR_LVC]),
2519 .l1clk(l1clk),
2520 .dout(csr_l2_errstate_reg[`ERR_LDAC:`ERR_LVC]),
2521 .soclk(soclk)
2522
2523);
2524
2525assign csr_error_status_veu = csr_l2_errstate_reg[`ERR_VEU] ;
2526assign csr_error_status_vec = csr_l2_errstate_reg[`ERR_VEC] ;
2527
2528
2529
2530//////////////////////////////////////////////////////////////////////////////////
2531// L2 Error Address Register ( addr = ac )
2532// -------------------------------------------
2533// Addr<39:4>,4'b0
2534// -------------------------------------------
2535// dir_addr<10:6> = panel #
2536// dir_addr<5:1> = entry #
2537// dir_addr<0> = I$ , 0= d$
2538//////////////////////////////////////////////////////////////////////////////////
2539
2540
2541
2542assign scrub_addr = { tag_scrub_addr_way, arbadr_data_ecc_idx } ;
2543
2544l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_36 addr_c9_mux1 // int 5.0 changes
2545 (.dout(mux1_addr_c9[39:4]),
2546 .din0({24'b0,arb_dir_addr_c9[10:9],arb_dir_addr_c9[7:0],2'b0}),
2547 .din1({18'b0,scrub_addr[12:0],5'b0}),
2548 .din2({evctag_evict_addr[39:6],2'b0}),
2549 .din3({arbadr_rdmard_addr_c12[39:6],2'b0}),
2550 .sel0(csreg_mux1_addr_sel[0]),
2551 .sel1(csreg_mux1_addr_sel[1]),
2552 .sel2(csreg_mux1_addr_sel[2]),
2553 .sel3(csreg_mux1_addr_sel[3]));
2554
2555l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_36 addr_c9_mux2 // int 5.0 changes
2556 (.dout(csr_l2_erraddr_prev[39:4]),
2557 .din0(mux1_addr_c9[39:4]),
2558 .din1(arbadr_arbdp_csr_addr_c9[39:4]),
2559 .din2(arbdat_csr_inst_wr_data_c8[39:4]),
2560 .sel0(csreg_mux2_addr_sel[0]),
2561 .sel1(csreg_mux2_addr_sel[1]),
2562 .sel2(csreg_mux2_addr_sel[2]));
2563
2564l2t_csr_ctl_msff_ctl_macro__en_1__width_36 ff_csr_l2_erraddr_d1 // int 5.0 changes
2565 (// FS:wmr_protect
2566 .scan_in(ff_csr_l2_erraddr_d1_scanin),
2567 .scan_out(ff_csr_l2_erraddr_d1_scanout),
2568 .siclk (aclk_wmr),
2569 .din(csr_l2_erraddr_prev[39:4]),
2570 .en(csreg_csr_addr_wr_en), .l1clk(l1clk),
2571 .dout(csr_l2_erraddr_reg[39:4]),
2572 .soclk(soclk)
2573
2574);
2575
2576//////////////////////////////////////////////////////////////////////////////////
2577// L2 Error INJ Register ( addr = ad )
2578// -------------------------------------------
2579// SSHOT,ENB
2580// -------------------------------------------
2581//////////////////////////////////////////////////////////////////////////////////
2582
2583
2584// ENB bit.
2585// Set on write.
2586// Reset on write OR if ONESHOT bit is set.
2587
2588assign csr_l2_errinj_prev[0] = ( csr_l2_errinj_reg[0] |
2589 csreg_csr_errinj_wr_en_c8 & arbdat_csr_inst_wr_data_c8[0] )
2590 & ~((arb_dir_wr_en_c4 & csr_l2_errinj_reg[1] ) |
2591 (csreg_csr_errinj_wr_en_c8 & ~arbdat_csr_inst_wr_data_c8[0] )) ;
2592
2593// SSHOT bit can only be set or reset using a CSR Write
2594assign csr_l2_errinj_prev[1] = ( csr_l2_errinj_reg[1] |
2595 csreg_csr_errinj_wr_en_c8 & arbdat_csr_inst_wr_data_c8[1] )
2596 & ~( csreg_csr_errinj_wr_en_c8 & ~arbdat_csr_inst_wr_data_c8[1] ) ;
2597
2598
2599
2600l2t_csr_ctl_msff_ctl_macro__width_2 ff_csr_l2_errinj_d1 // sync reset active low
2601 (// FS:wmr_protect
2602 .scan_in(ff_csr_l2_errinj_d1_scanin),
2603 .scan_out(ff_csr_l2_errinj_d1_scanout),
2604 .siclk (aclk_wmr),
2605 .din(csr_l2_errinj_prev[1:0]), .l1clk(l1clk),
2606 .dout(csr_l2_errinj_reg[1:0]),
2607 .soclk(soclk)
2608
2609);
2610
2611assign csr_wr_dirpinj_en = csr_l2_errinj_reg[0] ;
2612
2613
2614//////////////////////////////////////////////////////////////////////////////////
2615// THIS REGISTER DOES NOT EXIST ANYMORE
2616// L2 SELF TIME MARGIN REGISTER ( ae or af)
2617// ------------------------------------------------
2618// CAM2<7:0> DIR<7:0> DATA<3:0> TAG<3:0>
2619// ------------------------------------------------
2620////////////////////////////////////////////////////////////////////////////////////
2621//
2622//
2623// assign csr_l2_stm_prev[23:0] = arbdat_csr_inst_wr_data_c8[23:0] ;
2624//
2625//msff_ctl_macro ff_csr_l2_stm_reg (width=24,en=1,clr=1) // sync reset active high
2626// (.din(csr_l2_stm_prev[23:0]),
2627// .en(csreg_csr_stm_wr_en_c8), .l1clk(l1clk), .clr(~dbb_rst_l),
2628// .dout(csr_l2_stm_reg[23:0]),
2629// .scan_in(),
2630// .scan_out()
2631//);
2632//
2633// assign l2t_l2d_l2d_cbit = csr_l2_stm_reg[3:0] ;
2634// //assign l2t_cam2_stm = csr_l2_stm_reg[23:16] ;
2635// assign l2t_dir_stm = csr_l2_stm_reg[15:8] ;
2636// //assign l2t_tag_stm = csr_l2_stm_reg[7:4] ;
2637//
2638//
2639//
2640//
2641////////////////////////////////////////////////////////////////////////////////////
2642// READ OPERATION
2643//////////////////////////////////////////////////////////////////////////////////
2644
2645assign rd_errstate_reg = { csr_l2_errstate_reg[63:60], // bit 60 ERR_ASYNC has to be used
2646 csr_l2_errstate_reg[59:34],
2647 5'b0,
2648 csr_l2_errstate_reg[28:0] } ;
2649
2650assign csr_report_ldrc = csreg_report_ldrc_inpkt;
2651
2652
2653l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_64 mux_mux1_data_out_c7
2654 (.dout ( mux1_data_out_c7[63:0] ) ,
2655 .din0(64'b0), // A8
2656 .din1({42'b0,csr_l2_control_reg[21:0]}), // A9
2657 .din2({61'b0,csr_l2_erren_reg[2:0]}), // AA
2658 .din3(rd_errstate_reg[63:0]), // AB
2659 .sel0(csreg_csr_rd_mux1_sel_c7[0]),
2660 .sel1(csreg_csr_rd_mux1_sel_c7[1]),
2661 .sel2(csreg_csr_rd_mux1_sel_c7[2]),
2662 .sel3(csreg_csr_rd_mux1_sel_c7[3]));
2663
2664l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_64 mux_mux2_data_out_c7
2665 (.dout (mux2_data_out_c7[63:0] ) ,
2666 .din0({24'b0,csr_l2_erraddr_reg[39:4],4'b0}), // AC
2667 .din1({62'b0,csr_l2_errinj_reg[1:0]}), // AD
2668 .din2({12'b0,rd_notdata_reg[`ERR_MEND:`ERR_NDADR_LO],4'b0}), // AE or AF
2669 .sel0(csreg_csr_rd_mux1_sel_c7[0]),
2670 .sel1(csreg_csr_rd_mux1_sel_c7[1]),
2671 .sel2(csreg_csr_rd_mux2_sel_c7));
2672
2673l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_64 mux3_data_out_c8
2674 (.dout ( csr_rd_data_c7_1[63:0] ) ,
2675 .din0({mux1_data_out_c7[63:0]}),
2676 .din1({mux2_data_out_c7[63:0]}),
2677 .sel0(csreg_csr_rd_mux3_sel_c7[0]),
2678 .sel1(csreg_csr_rd_mux3_sel_c7[1])
2679 );
2680
2681
2682l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_64 mux_fnl_data_out_c8
2683 (.dout ( csr_rd_data_c7[63:0] ) ,
2684 .din0(csr_rd_data_c7_1[63:0]),
2685 .din1(debug_csr_read_data[63:0]),
2686 .sel0(csreg_csr_rd_mux_fnl_c7[0]),
2687 .sel1(csreg_csr_rd_mux_fnl_c7[1])
2688 );
2689
2690
2691
2692l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_64 mux4_data_out_c8
2693 (.dout ( debug_csr_read_data[63:0] ) ,
2694 .din0(l2_mask_register[63:0]),
2695 .din1(l2_compare_register[63:0]),
2696 .sel0(csreg_csr_rd_mux4_sel_c7[1]),
2697 .sel1(csreg_csr_rd_mux4_sel_c7[0]));
2698
2699
2700
2701
2702
2703
2704l2t_csr_ctl_msff_ctl_macro__width_64 ff_csr_rd_data_c8
2705 (// FS:wmr_protect
2706 .scan_in(ff_csr_rd_data_c8_scanin),
2707 .scan_out(ff_csr_rd_data_c8_scanout),
2708 .siclk (aclk_wmr),
2709 .din(csr_rd_data_c7[63:0]),
2710 .l1clk(l1clk),
2711 .dout(csr_rd_data_c8[63:0]),
2712 .soclk(soclk)
2713
2714);
2715
2716// Follow Bug id : 87784
2717// Notdata Error Register BS 06/13/04
2718// 51 : NDRW R/W
2719// 50 : MEND R/W1C
2720// 49 : NDSP R/W1C
2721// 48 : NDDM R/W1C
2722// 47:46 : RSVD R(0's)
2723// 45:40 : NDVCID R/W
2724// 39:4 : NDADR R/W
2725// 3:0 : RSVD R(0's)
2726
2727//////////////////////////////////////
2728// NDRW BIT
2729//////////////////////////////////////
2730//
2731//assign csr_l2_notdata_prev[`ERR_NDRW] =
2732// ( csreg_notdata_diag_wr_en & arbdat_csr_inst_wr_data_c8[`ERR_NDRW] ) |
2733// csreg_notdata_err_state_in_rw;
2734//
2735
2736
2737assign csr_l2_notdata_prev[`ERR_NDRW] = ( csreg_notdata_diag_wr_en & arbdat_csr_inst_wr_data_c8[`ERR_NDRW] ) |
2738 csreg_notdata_err_state_in_rw & ~(csr_l2_notdata_reg[`ERR_NDSP] & csr_l2_notdata_reg[`ERR_NDRW]);
2739
2740
2741
2742l2t_csr_ctl_msff_ctl_macro__en_1__width_1 ff_csr_l2_notdata_rw_d1
2743 (// FS:wmr_protect
2744 .scan_in(ff_csr_l2_notdata_rw_d1_scanin),
2745 .scan_out(ff_csr_l2_notdata_rw_d1_scanout),
2746 .siclk (aclk_wmr),
2747 .din(csr_l2_notdata_prev[`ERR_NDRW]), .l1clk(l1clk),
2748 .dout(csr_l2_notdata_reg[`ERR_NDRW]), .en(csreg_notdata_error_rw_en),
2749 .soclk(soclk)
2750
2751);
2752
2753assign notdata_higher_priority_err = csr_l2_notdata_reg[`ERR_NDRW] & csr_l2_notdata_reg[`ERR_NDSP];
2754
2755//////////////////////////////////////
2756// MEND BIT
2757//////////////////////////////////////
2758
2759assign csr_l2_notdata_prev[`ERR_MEND] =
2760 ( ~( csreg_csr_notdata_wr_en_c8 &
2761 arbdat_csr_inst_wr_data_c8[`ERR_MEND] ) &
2762 csr_l2_notdata_reg[`ERR_MEND]
2763 ) | csreg_notdata_err_state_in_mend;
2764
2765l2t_csr_ctl_msff_ctl_macro__width_1 ff_csr_l2_notdata_mend_d1
2766 (// FS:wmr_protect
2767 .scan_in(ff_csr_l2_notdata_mend_d1_scanin),
2768 .scan_out(ff_csr_l2_notdata_mend_d1_scanout),
2769 .siclk (aclk_wmr),
2770 .din(csr_l2_notdata_prev[`ERR_MEND]),
2771 .l1clk(l1clk),
2772 .dout(csr_l2_notdata_reg[`ERR_MEND]),
2773 .soclk(soclk)
2774);
2775
2776//////////////////////////////////////
2777// NDSP and NDRW BITS
2778//////////////////////////////////////
2779
2780assign csr_l2_notdata_prev[`ERR_NDSP:`ERR_NDDM] =
2781 ( ~({2{csreg_csr_notdata_wr_en_c8}} &
2782 arbdat_csr_inst_wr_data_c8[`ERR_NDSP:`ERR_NDDM]) &
2783 csr_l2_notdata_reg[`ERR_NDSP:`ERR_NDDM]
2784 ) | csreg_notdata_err_state_in[`ERR_NDSP:`ERR_NDDM];
2785
2786l2t_csr_ctl_msff_ctl_macro__width_4 ff_csr_l2_notdata_ndspnddm_d1
2787 (// FS:wmr_protect
2788 .scan_in(ff_csr_l2_notdata_ndspnddm_d1_scanin),
2789 .scan_out(ff_csr_l2_notdata_ndspnddm_d1_scanout),
2790 .siclk (aclk_wmr),
2791 .din({csr_l2_notdata_prev[`ERR_NDSP:`ERR_NDDM],2'b0}),
2792 .l1clk(l1clk),
2793 .dout(csr_l2_notdata_reg[`ERR_NDSP:`ERR_NDDM-2]),
2794 .soclk(soclk)
2795);
2796
2797
2798//////////////////////////////////////
2799// NDVCID BITS
2800//////////////////////////////////////
2801
2802
2803assign sel_diag_notdata_wr = ~(csreg_wr_enable_notdata_vcid_c9 | csreg_wr_enable_notdata_nddm_vcid_c9);
2804
2805l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_6 mux_ndvcid_c9
2806 (
2807 .dout(csr_l2_notdata_prev[`ERR_NDVCID_HI:`ERR_NDVCID_LO]),
2808 .din0(inst_tid_c9[5:0]),
2809 .din1(csr_l2_steering_tid[5:0]),
2810 .din2(arbdat_csr_inst_wr_data_c8[`ERR_NDVCID_HI:`ERR_NDVCID_LO]),
2811 .sel0(csreg_wr_enable_notdata_vcid_c9),
2812 .sel1(csreg_wr_enable_notdata_nddm_vcid_c9),
2813 .sel2(sel_diag_notdata_wr)
2814 );
2815
2816
2817
2818
2819
2820l2t_csr_ctl_msff_ctl_macro__en_1__width_6 ff_csr_l2_notdata_vcid_d1 // BS and SR 11/12/03 N2 Xbar Packet format change
2821 (// FS:wmr_protect
2822 .scan_in(ff_csr_l2_notdata_vcid_d1_scanin),
2823 .scan_out(ff_csr_l2_notdata_vcid_d1_scanout),
2824 .siclk (aclk_wmr),
2825 .din(csr_l2_notdata_prev[`ERR_NDVCID_HI:`ERR_NDVCID_LO]),
2826 .en(csreg_csr_notdata_vcid_wr_en), .l1clk(l1clk),
2827 .dout(csr_l2_notdata_reg[`ERR_NDVCID_HI:`ERR_NDVCID_LO]),
2828 .soclk(soclk)
2829
2830);
2831
2832//////////////////////////////////////
2833// NDADR BITS
2834//////////////////////////////////////
2835
2836l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_36 mux_ndadr_c9 // int 5.0 changes
2837 (.dout(csr_l2_notdata_prev[`ERR_NDADR_HI:`ERR_NDADR_LO]),
2838 .din0(arbadr_arbdp_csr_addr_c9[39:4]), // c9 address
2839 .din1({arbadr_rdmard_addr_c12[39:6],2'b0}), // siu address
2840 .din2(arbdat_csr_inst_wr_data_c8[`ERR_NDADR_HI:`ERR_NDADR_LO]), // diagnostic wr data
2841 .sel0(csreg_notdata_addr_mux_sel[0]),
2842 .sel1(csreg_notdata_addr_mux_sel[1]),
2843 .sel2(csreg_notdata_addr_mux_sel[2]));
2844
2845l2t_csr_ctl_msff_ctl_macro__en_1__width_36 ff_csr_l2_notdata_addr_d1 // int 5.0 changes
2846 (// FS:wmr_protect
2847 .scan_in(ff_csr_l2_notdata_addr_d1_scanin),
2848 .scan_out(ff_csr_l2_notdata_addr_d1_scanout),
2849 .siclk (aclk_wmr),
2850 .din(csr_l2_notdata_prev[`ERR_NDADR_HI:`ERR_NDADR_LO]),
2851 .en(csreg_csr_notdata_addr_wr_en), .l1clk(l1clk),
2852 .dout(csr_l2_notdata_reg[`ERR_NDADR_HI:`ERR_NDADR_LO]),
2853 .soclk(soclk)
2854
2855);
2856
2857// Bug id : 87784
2858// 50 : NDRW
2859// 51 : MEND It is difficult to go change the entire logic around
2860// Hence swapping just these two bit definitions while reading it
2861// to keep it consistent with PRM
2862//assign rd_notdata_reg = {csr_l2_notdata_reg[`ERR_MEND],csr_l2_notdata_reg[`ERR_NDRW],csr_l2_notdata_reg[ERR_NDSP:`ERR_NDADR_LO]};
2863
2864assign rd_notdata_reg = csr_l2_notdata_reg[`ERR_MEND:`ERR_NDADR_LO];
2865
2866assign csr_error_status_notdata = (|(csr_l2_notdata_reg[`ERR_NDSP:`ERR_NDDM]));
2867 // a Notdata Error is already logged
2868
2869//////////////////////////////////////
2870//// Shadow scan registers
2871////////////////////////////////////////
2872assign shadow_l2erraddr_reg[39:4] = csr_l2_erraddr_reg[39:4];
2873assign shadow_notdata_reg[`ERR_MEND:`ERR_NDADR_LO] = rd_notdata_reg[`ERR_MEND:`ERR_NDADR_LO];
2874assign shadow_error_status_reg[63:0] = rd_errstate_reg[63:0];
2875
2876
2877
2878// input csreg_l2_cmpr_reg_wr_en_c8;
2879// input csreg_l2_mask_reg_wr_en_c8;
2880//////////////////////////////////////
2881//// Debug block
2882////////////////////////////////////////
2883
2884
2885// L2 Compare Register
2886
2887//assign l2_compare_register_prev[63:0] = ({64{csreg_l2_cmpr_reg_wr_en_c8}} &
2888// {12'b0,arbdat_csr_inst_wr_data_c8[51:48],2'b0,arbdat_csr_inst_wr_data_c8[45:40],6'b0,
2889// arbdat_csr_inst_wr_data_c8[33:2],2'b0} );// | l2_compare_register;
2890
2891assign l2_compare_register_prev[63:0] = ( {11'b0,arbdat_csr_inst_wr_data_c8[52:48],2'b0,
2892arbdat_csr_inst_wr_data_c8[45:40],6'b0,arbdat_csr_inst_wr_data_c8[33:2],2'b0} );
2893
2894l2t_csr_ctl_msff_ctl_macro__en_1__width_64 ff_l2_compare_register
2895 (// FS:wmr_protect
2896 .scan_in(ff_l2_compare_register_scanin),
2897 .scan_out(ff_l2_compare_register_scanout),
2898 .siclk (aclk_wmr),
2899 .dout (l2_compare_register[63:0]),
2900 .l1clk (l1clk),
2901 .en (csreg_l2_cmpr_reg_wr_en_c8),
2902 .din (l2_compare_register_prev[63:0]),
2903 .soclk(soclk)
2904 );
2905
2906// L2 Mask register
2907
2908//assign l2_mask_register_prev[63:0] = ({64{csreg_l2_mask_reg_wr_en_c8}} &
2909// {12'b0,arbdat_csr_inst_wr_data_c8[51:48],2'b0,arbdat_csr_inst_wr_data_c8[45:40],
2910// 6'b0,arbdat_csr_inst_wr_data_c8[33:2],2'b0} ) ;// | l2_mask_register;
2911
2912assign l2_mask_register_prev[63:0] = ({11'b0,arbdat_csr_inst_wr_data_c8[52:48],
2913 2'b0,arbdat_csr_inst_wr_data_c8[45:40],6'b0,arbdat_csr_inst_wr_data_c8[33:2],2'b0} ) ;
2914
2915l2t_csr_ctl_msff_ctl_macro__en_1__width_64 ff_l2_mask_register
2916 (// FS:wmr_protect
2917 .scan_in(ff_l2_mask_register_scanin),
2918 .scan_out(ff_l2_mask_register_scanout),
2919 .siclk (aclk_wmr),
2920 .dout (l2_mask_register[63:0]),
2921 .l1clk (l1clk),
2922 .en (csreg_l2_mask_reg_wr_en_c8),
2923 .din (l2_mask_register_prev[63:0]),
2924 .soclk(soclk)
2925 );
2926
2927assign debug_address_inpipe[63:0] = ({11'b0,arbdec_csr_ttype_c6[4:0],2'b0,
2928 arbdec_csr_vcid_c6[5:0],6'b0,arbadr_csr_debug_addr[33:2],2'b0});
2929
2930l2t_csr_ctl_msff_ctl_macro__width_64 ff_debug_address_inpipe
2931 (// FS:wmr_protect
2932 .scan_in(ff_debug_address_inpipe_scanin),
2933 .scan_out(ff_debug_address_inpipe_scanout),
2934 .siclk (aclk_wmr),
2935 .dout (debug_address_inpipe_d1[63:0]),
2936 .l1clk (l1clk),
2937 .din (debug_address_inpipe[63:0]),
2938 .soclk(soclk)
2939 );
2940
2941l2t_csr_ctl_msff_ctl_macro__width_5 ff_instruction_vld_piped
2942 (// FS:wmr_protect
2943 .scan_in(ff_instruction_vld_piped_scanin),
2944 .scan_out(ff_instruction_vld_piped_scanout),
2945 .siclk (aclk_wmr),
2946 .dout ({arb_inst_vld_c3,arb_inst_vld_c4,arb_inst_vld_c5,arb_inst_vld_c52,arb_inst_vld_c6}),
2947 .l1clk (l1clk),
2948 .din ({arb_inst_vld_c2,arb_inst_vld_c3,arb_inst_vld_c4,arb_inst_vld_c5,arb_inst_vld_c52}),
2949 .soclk(soclk)
2950 );
2951
2952
2953assign l2t_dbg_pa_match_unreg = ((debug_address_inpipe_d1[63:0] & l2_mask_register[63:0])
2954// BUG ID 110568 == l2_compare_register[63:0]) & arb_inst_vld_c6;
2955 == l2_compare_register[63:0]) & arb_inst_vld_c7;
2956
2957assign l2t_dbg_err_event_unreg = (csr_error_status_notdata | csr_error_status_veu | csr_error_status_vec)
2958 & dbg_trigger;
2959
2960
2961l2t_csr_ctl_msff_ctl_macro__width_2 ff_l2t_dbg_pa_match
2962 (// FS:wmr_protect
2963 .scan_in(ff_l2t_dbg_pa_match_scanin),
2964 .scan_out(ff_l2t_dbg_pa_match_scanout),
2965 .siclk (aclk_wmr),
2966 .dout ({l2t_dbg_pa_match,l2t_dbg_err_event}),
2967 .l1clk (l1clk),
2968 .din ({l2t_dbg_pa_match_unreg,l2t_dbg_err_event_unreg}),
2969 .soclk(soclk)
2970 );
2971
2972
2973assign warm_scanout_n = ~warm_scanout;
2974
2975assign scan_out = ~(warm_scanout_n | wmr_protect);
2976
2977
2978
2979///////////////////////////////////////////////////////////////////////////////////////////////////
2980// fixscan start:
2981assign spares_scanin = scan_in ;
2982assign ff_csr_l2_control_reg_0_scanin = spares_scanout ;
2983assign ff_csr_l2_control_reg_2to1_scanin = ff_csr_l2_control_reg_0_scanout;
2984assign ff_csr_l2_control_reg_scb_int_scanin = ff_csr_l2_control_reg_2to1_scanout;
2985assign ff_csr_l2_control_reg_steering_scanin = ff_csr_l2_control_reg_scb_int_scanout;
2986assign ff_csr_l2_control_reg_dbg_scanin = ff_csr_l2_control_reg_steering_scanout;
2987assign ff_csr_l2_control_reg_dir_clr_scanin = ff_csr_l2_control_reg_dbg_scanout;
2988assign ff_dir_clr_d1_scanin = ff_csr_l2_control_reg_dir_clr_scanout;
2989assign ff_dir_clr_d2_scanin = ff_dir_clr_d1_scanout ;
2990assign ff_scrub_count_scanin = ff_dir_clr_d2_scanout ;
2991assign ff_csr_l2_erren_d1_scanin = ff_scrub_count_scanout ;
2992assign ff_bist_registrer_scanin = ff_csr_l2_erren_d1_scanout;
2993assign ff_csr_l2_errsynd_d1_scanin = ff_bist_registrer_scanout;
2994assign ff_inst_tid_c9_scanin = ff_csr_l2_errsynd_d1_scanout;
2995assign ff_csr_l2_erritid_d1_scanin = ff_inst_tid_c9_scanout ;
2996assign ff_async_bit_scanin = ff_csr_l2_erritid_d1_scanout;
2997assign ff_csr_l2_errrw_d1_scanin = ff_async_bit_scanout ;
2998assign ff_csr_l2_errmeu_d1_scanin = ff_csr_l2_errrw_d1_scanout;
2999assign ff_csr_l2_errmec_d1_scanin = ff_csr_l2_errmeu_d1_scanout;
3000assign ff_csr_l2_errstate_d1_scanin = ff_csr_l2_errmec_d1_scanout;
3001assign ff_csr_l2_erraddr_d1_scanin = ff_csr_l2_errstate_d1_scanout;
3002assign ff_csr_l2_errinj_d1_scanin = ff_csr_l2_erraddr_d1_scanout;
3003assign ff_csr_rd_data_c8_scanin = ff_csr_l2_errinj_d1_scanout;
3004assign ff_csr_l2_notdata_rw_d1_scanin = ff_csr_rd_data_c8_scanout;
3005assign ff_csr_l2_notdata_mend_d1_scanin = ff_csr_l2_notdata_rw_d1_scanout;
3006assign ff_csr_l2_notdata_ndspnddm_d1_scanin = ff_csr_l2_notdata_mend_d1_scanout;
3007assign ff_csr_l2_notdata_vcid_d1_scanin = ff_csr_l2_notdata_ndspnddm_d1_scanout;
3008assign ff_csr_l2_notdata_addr_d1_scanin = ff_csr_l2_notdata_vcid_d1_scanout;
3009assign ff_l2_compare_register_scanin = ff_csr_l2_notdata_addr_d1_scanout;
3010assign ff_l2_mask_register_scanin = ff_l2_compare_register_scanout;
3011assign ff_debug_address_inpipe_scanin = ff_l2_mask_register_scanout;
3012assign ff_instruction_vld_piped_scanin = ff_debug_address_inpipe_scanout;
3013assign ff_l2t_dbg_pa_match_scanin = ff_instruction_vld_piped_scanout;
3014assign warm_scanout = ff_l2t_dbg_pa_match_scanout;
3015// fixscan end:
3016endmodule
3017
3018
3019
3020
3021
3022
3023// any PARAMS parms go into naming of macro
3024
3025module l2t_csr_ctl_l1clkhdr_ctl_macro (
3026 l2clk,
3027 l1en,
3028 pce_ov,
3029 stop,
3030 se,
3031 l1clk);
3032
3033
3034 input l2clk;
3035 input l1en;
3036 input pce_ov;
3037 input stop;
3038 input se;
3039 output l1clk;
3040
3041
3042
3043
3044
3045cl_sc1_l1hdr_8x c_0 (
3046
3047
3048 .l2clk(l2clk),
3049 .pce(l1en),
3050 .l1clk(l1clk),
3051 .se(se),
3052 .pce_ov(pce_ov),
3053 .stop(stop)
3054);
3055
3056
3057
3058endmodule
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072// any PARAMS parms go into naming of macro
3073
3074module l2t_csr_ctl_msff_ctl_macro__en_1__width_1 (
3075 din,
3076 en,
3077 l1clk,
3078 scan_in,
3079 siclk,
3080 soclk,
3081 dout,
3082 scan_out);
3083wire [0:0] fdin;
3084
3085 input [0:0] din;
3086 input en;
3087 input l1clk;
3088 input scan_in;
3089
3090
3091 input siclk;
3092 input soclk;
3093
3094 output [0:0] dout;
3095 output scan_out;
3096assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
3097
3098
3099
3100
3101
3102
3103dff #(1) d0_0 (
3104.l1clk(l1clk),
3105.siclk(siclk),
3106.soclk(soclk),
3107.d(fdin[0:0]),
3108.si(scan_in),
3109.so(scan_out),
3110.q(dout[0:0])
3111);
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124endmodule
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138// any PARAMS parms go into naming of macro
3139
3140module l2t_csr_ctl_msff_ctl_macro__en_1__width_2 (
3141 din,
3142 en,
3143 l1clk,
3144 scan_in,
3145 siclk,
3146 soclk,
3147 dout,
3148 scan_out);
3149wire [1:0] fdin;
3150wire [0:0] so;
3151
3152 input [1:0] din;
3153 input en;
3154 input l1clk;
3155 input scan_in;
3156
3157
3158 input siclk;
3159 input soclk;
3160
3161 output [1:0] dout;
3162 output scan_out;
3163assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}});
3164
3165
3166
3167
3168
3169
3170dff #(2) d0_0 (
3171.l1clk(l1clk),
3172.siclk(siclk),
3173.soclk(soclk),
3174.d(fdin[1:0]),
3175.si({scan_in,so[0:0]}),
3176.so({so[0:0],scan_out}),
3177.q(dout[1:0])
3178);
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191endmodule
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205// any PARAMS parms go into naming of macro
3206
3207module l2t_csr_ctl_msff_ctl_macro__en_1__width_12 (
3208 din,
3209 en,
3210 l1clk,
3211 scan_in,
3212 siclk,
3213 soclk,
3214 dout,
3215 scan_out);
3216wire [11:0] fdin;
3217wire [10:0] so;
3218
3219 input [11:0] din;
3220 input en;
3221 input l1clk;
3222 input scan_in;
3223
3224
3225 input siclk;
3226 input soclk;
3227
3228 output [11:0] dout;
3229 output scan_out;
3230assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}});
3231
3232
3233
3234
3235
3236
3237dff #(12) d0_0 (
3238.l1clk(l1clk),
3239.siclk(siclk),
3240.soclk(soclk),
3241.d(fdin[11:0]),
3242.si({scan_in,so[10:0]}),
3243.so({so[10:0],scan_out}),
3244.q(dout[11:0])
3245);
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258endmodule
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272// any PARAMS parms go into naming of macro
3273
3274module l2t_csr_ctl_msff_ctl_macro__en_1__width_6 (
3275 din,
3276 en,
3277 l1clk,
3278 scan_in,
3279 siclk,
3280 soclk,
3281 dout,
3282 scan_out);
3283wire [5:0] fdin;
3284wire [4:0] so;
3285
3286 input [5:0] din;
3287 input en;
3288 input l1clk;
3289 input scan_in;
3290
3291
3292 input siclk;
3293 input soclk;
3294
3295 output [5:0] dout;
3296 output scan_out;
3297assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}});
3298
3299
3300
3301
3302
3303
3304dff #(6) d0_0 (
3305.l1clk(l1clk),
3306.siclk(siclk),
3307.soclk(soclk),
3308.d(fdin[5:0]),
3309.si({scan_in,so[4:0]}),
3310.so({so[4:0],scan_out}),
3311.q(dout[5:0])
3312);
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325endmodule
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339// any PARAMS parms go into naming of macro
3340
3341module l2t_csr_ctl_msff_ctl_macro__width_1 (
3342 din,
3343 l1clk,
3344 scan_in,
3345 siclk,
3346 soclk,
3347 dout,
3348 scan_out);
3349wire [0:0] fdin;
3350
3351 input [0:0] din;
3352 input l1clk;
3353 input scan_in;
3354
3355
3356 input siclk;
3357 input soclk;
3358
3359 output [0:0] dout;
3360 output scan_out;
3361assign fdin[0:0] = din[0:0];
3362
3363
3364
3365
3366
3367
3368dff #(1) d0_0 (
3369.l1clk(l1clk),
3370.siclk(siclk),
3371.soclk(soclk),
3372.d(fdin[0:0]),
3373.si(scan_in),
3374.so(scan_out),
3375.q(dout[0:0])
3376);
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389endmodule
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3400// also for pass-gate with decoder
3401
3402
3403
3404
3405
3406// any PARAMS parms go into naming of macro
3407
3408module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_32 (
3409 din0,
3410 sel0,
3411 din1,
3412 sel1,
3413 dout);
3414 input [31:0] din0;
3415 input sel0;
3416 input [31:0] din1;
3417 input sel1;
3418 output [31:0] dout;
3419
3420
3421
3422
3423
3424assign dout[31:0] = ( {32{sel0}} & din0[31:0] ) |
3425 ( {32{sel1}} & din1[31:0]);
3426
3427
3428
3429
3430
3431endmodule
3432
3433
3434
3435
3436
3437
3438// any PARAMS parms go into naming of macro
3439
3440module l2t_csr_ctl_msff_ctl_macro__width_32 (
3441 din,
3442 l1clk,
3443 scan_in,
3444 siclk,
3445 soclk,
3446 dout,
3447 scan_out);
3448wire [31:0] fdin;
3449wire [30:0] so;
3450
3451 input [31:0] din;
3452 input l1clk;
3453 input scan_in;
3454
3455
3456 input siclk;
3457 input soclk;
3458
3459 output [31:0] dout;
3460 output scan_out;
3461assign fdin[31:0] = din[31:0];
3462
3463
3464
3465
3466
3467
3468dff #(32) d0_0 (
3469.l1clk(l1clk),
3470.siclk(siclk),
3471.soclk(soclk),
3472.d(fdin[31:0]),
3473.si({scan_in,so[30:0]}),
3474.so({so[30:0],scan_out}),
3475.q(dout[31:0])
3476);
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489endmodule
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503// any PARAMS parms go into naming of macro
3504
3505module l2t_csr_ctl_msff_ctl_macro__en_1__width_3 (
3506 din,
3507 en,
3508 l1clk,
3509 scan_in,
3510 siclk,
3511 soclk,
3512 dout,
3513 scan_out);
3514wire [2:0] fdin;
3515wire [1:0] so;
3516
3517 input [2:0] din;
3518 input en;
3519 input l1clk;
3520 input scan_in;
3521
3522
3523 input siclk;
3524 input soclk;
3525
3526 output [2:0] dout;
3527 output scan_out;
3528assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}});
3529
3530
3531
3532
3533
3534
3535dff #(3) d0_0 (
3536.l1clk(l1clk),
3537.siclk(siclk),
3538.soclk(soclk),
3539.d(fdin[2:0]),
3540.si({scan_in,so[1:0]}),
3541.so({so[1:0],scan_out}),
3542.q(dout[2:0])
3543);
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556endmodule
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570// any PARAMS parms go into naming of macro
3571
3572module l2t_csr_ctl_msff_ctl_macro__en_1__width_11 (
3573 din,
3574 en,
3575 l1clk,
3576 scan_in,
3577 siclk,
3578 soclk,
3579 dout,
3580 scan_out);
3581wire [10:0] fdin;
3582wire [9:0] so;
3583
3584 input [10:0] din;
3585 input en;
3586 input l1clk;
3587 input scan_in;
3588
3589
3590 input siclk;
3591 input soclk;
3592
3593 output [10:0] dout;
3594 output scan_out;
3595assign fdin[10:0] = (din[10:0] & {11{en}}) | (dout[10:0] & ~{11{en}});
3596
3597
3598
3599
3600
3601
3602dff #(11) d0_0 (
3603.l1clk(l1clk),
3604.siclk(siclk),
3605.soclk(soclk),
3606.d(fdin[10:0]),
3607.si({scan_in,so[9:0]}),
3608.so({so[9:0],scan_out}),
3609.q(dout[10:0])
3610);
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623endmodule
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637// any PARAMS parms go into naming of macro
3638
3639module l2t_csr_ctl_msff_ctl_macro__en_1__width_32 (
3640 din,
3641 en,
3642 l1clk,
3643 scan_in,
3644 siclk,
3645 soclk,
3646 dout,
3647 scan_out);
3648wire [31:0] fdin;
3649wire [30:0] so;
3650
3651 input [31:0] din;
3652 input en;
3653 input l1clk;
3654 input scan_in;
3655
3656
3657 input siclk;
3658 input soclk;
3659
3660 output [31:0] dout;
3661 output scan_out;
3662assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}});
3663
3664
3665
3666
3667
3668
3669dff #(32) d0_0 (
3670.l1clk(l1clk),
3671.siclk(siclk),
3672.soclk(soclk),
3673.d(fdin[31:0]),
3674.si({scan_in,so[30:0]}),
3675.so({so[30:0],scan_out}),
3676.q(dout[31:0])
3677);
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690endmodule
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704// any PARAMS parms go into naming of macro
3705
3706module l2t_csr_ctl_msff_ctl_macro__width_6 (
3707 din,
3708 l1clk,
3709 scan_in,
3710 siclk,
3711 soclk,
3712 dout,
3713 scan_out);
3714wire [5:0] fdin;
3715wire [4:0] so;
3716
3717 input [5:0] din;
3718 input l1clk;
3719 input scan_in;
3720
3721
3722 input siclk;
3723 input soclk;
3724
3725 output [5:0] dout;
3726 output scan_out;
3727assign fdin[5:0] = din[5:0];
3728
3729
3730
3731
3732
3733
3734dff #(6) d0_0 (
3735.l1clk(l1clk),
3736.siclk(siclk),
3737.soclk(soclk),
3738.d(fdin[5:0]),
3739.si({scan_in,so[4:0]}),
3740.so({so[4:0],scan_out}),
3741.q(dout[5:0])
3742);
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755endmodule
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3766// also for pass-gate with decoder
3767
3768
3769
3770
3771
3772// any PARAMS parms go into naming of macro
3773
3774module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 (
3775 din0,
3776 sel0,
3777 din1,
3778 sel1,
3779 dout);
3780 input [5:0] din0;
3781 input sel0;
3782 input [5:0] din1;
3783 input sel1;
3784 output [5:0] dout;
3785
3786
3787
3788
3789
3790assign dout[5:0] = ( {6{sel0}} & din0[5:0] ) |
3791 ( {6{sel1}} & din1[5:0]);
3792
3793
3794
3795
3796
3797endmodule
3798
3799
3800
3801
3802
3803
3804// any PARAMS parms go into naming of macro
3805
3806module l2t_csr_ctl_msff_ctl_macro__width_20 (
3807 din,
3808 l1clk,
3809 scan_in,
3810 siclk,
3811 soclk,
3812 dout,
3813 scan_out);
3814wire [19:0] fdin;
3815wire [18:0] so;
3816
3817 input [19:0] din;
3818 input l1clk;
3819 input scan_in;
3820
3821
3822 input siclk;
3823 input soclk;
3824
3825 output [19:0] dout;
3826 output scan_out;
3827assign fdin[19:0] = din[19:0];
3828
3829
3830
3831
3832
3833
3834dff #(20) d0_0 (
3835.l1clk(l1clk),
3836.siclk(siclk),
3837.soclk(soclk),
3838.d(fdin[19:0]),
3839.si({scan_in,so[18:0]}),
3840.so({so[18:0],scan_out}),
3841.q(dout[19:0])
3842);
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855endmodule
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3866// also for pass-gate with decoder
3867
3868
3869
3870
3871
3872// any PARAMS parms go into naming of macro
3873
3874module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_36 (
3875 din0,
3876 sel0,
3877 din1,
3878 sel1,
3879 din2,
3880 sel2,
3881 din3,
3882 sel3,
3883 dout);
3884 input [35:0] din0;
3885 input sel0;
3886 input [35:0] din1;
3887 input sel1;
3888 input [35:0] din2;
3889 input sel2;
3890 input [35:0] din3;
3891 input sel3;
3892 output [35:0] dout;
3893
3894
3895
3896
3897
3898assign dout[35:0] = ( {36{sel0}} & din0[35:0] ) |
3899 ( {36{sel1}} & din1[35:0]) |
3900 ( {36{sel2}} & din2[35:0]) |
3901 ( {36{sel3}} & din3[35:0]);
3902
3903
3904
3905
3906
3907endmodule
3908
3909
3910// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3911// also for pass-gate with decoder
3912
3913
3914
3915
3916
3917// any PARAMS parms go into naming of macro
3918
3919module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_36 (
3920 din0,
3921 sel0,
3922 din1,
3923 sel1,
3924 din2,
3925 sel2,
3926 dout);
3927 input [35:0] din0;
3928 input sel0;
3929 input [35:0] din1;
3930 input sel1;
3931 input [35:0] din2;
3932 input sel2;
3933 output [35:0] dout;
3934
3935
3936
3937
3938
3939assign dout[35:0] = ( {36{sel0}} & din0[35:0] ) |
3940 ( {36{sel1}} & din1[35:0]) |
3941 ( {36{sel2}} & din2[35:0]);
3942
3943
3944
3945
3946
3947endmodule
3948
3949
3950
3951
3952
3953
3954// any PARAMS parms go into naming of macro
3955
3956module l2t_csr_ctl_msff_ctl_macro__en_1__width_36 (
3957 din,
3958 en,
3959 l1clk,
3960 scan_in,
3961 siclk,
3962 soclk,
3963 dout,
3964 scan_out);
3965wire [35:0] fdin;
3966wire [34:0] so;
3967
3968 input [35:0] din;
3969 input en;
3970 input l1clk;
3971 input scan_in;
3972
3973
3974 input siclk;
3975 input soclk;
3976
3977 output [35:0] dout;
3978 output scan_out;
3979assign fdin[35:0] = (din[35:0] & {36{en}}) | (dout[35:0] & ~{36{en}});
3980
3981
3982
3983
3984
3985
3986dff #(36) d0_0 (
3987.l1clk(l1clk),
3988.siclk(siclk),
3989.soclk(soclk),
3990.d(fdin[35:0]),
3991.si({scan_in,so[34:0]}),
3992.so({so[34:0],scan_out}),
3993.q(dout[35:0])
3994);
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007endmodule
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021// any PARAMS parms go into naming of macro
4022
4023module l2t_csr_ctl_msff_ctl_macro__width_2 (
4024 din,
4025 l1clk,
4026 scan_in,
4027 siclk,
4028 soclk,
4029 dout,
4030 scan_out);
4031wire [1:0] fdin;
4032wire [0:0] so;
4033
4034 input [1:0] din;
4035 input l1clk;
4036 input scan_in;
4037
4038
4039 input siclk;
4040 input soclk;
4041
4042 output [1:0] dout;
4043 output scan_out;
4044assign fdin[1:0] = din[1:0];
4045
4046
4047
4048
4049
4050
4051dff #(2) d0_0 (
4052.l1clk(l1clk),
4053.siclk(siclk),
4054.soclk(soclk),
4055.d(fdin[1:0]),
4056.si({scan_in,so[0:0]}),
4057.so({so[0:0],scan_out}),
4058.q(dout[1:0])
4059);
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072endmodule
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4083// also for pass-gate with decoder
4084
4085
4086
4087
4088
4089// any PARAMS parms go into naming of macro
4090
4091module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_64 (
4092 din0,
4093 sel0,
4094 din1,
4095 sel1,
4096 din2,
4097 sel2,
4098 din3,
4099 sel3,
4100 dout);
4101 input [63:0] din0;
4102 input sel0;
4103 input [63:0] din1;
4104 input sel1;
4105 input [63:0] din2;
4106 input sel2;
4107 input [63:0] din3;
4108 input sel3;
4109 output [63:0] dout;
4110
4111
4112
4113
4114
4115assign dout[63:0] = ( {64{sel0}} & din0[63:0] ) |
4116 ( {64{sel1}} & din1[63:0]) |
4117 ( {64{sel2}} & din2[63:0]) |
4118 ( {64{sel3}} & din3[63:0]);
4119
4120
4121
4122
4123
4124endmodule
4125
4126
4127// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4128// also for pass-gate with decoder
4129
4130
4131
4132
4133
4134// any PARAMS parms go into naming of macro
4135
4136module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_64 (
4137 din0,
4138 sel0,
4139 din1,
4140 sel1,
4141 din2,
4142 sel2,
4143 dout);
4144 input [63:0] din0;
4145 input sel0;
4146 input [63:0] din1;
4147 input sel1;
4148 input [63:0] din2;
4149 input sel2;
4150 output [63:0] dout;
4151
4152
4153
4154
4155
4156assign dout[63:0] = ( {64{sel0}} & din0[63:0] ) |
4157 ( {64{sel1}} & din1[63:0]) |
4158 ( {64{sel2}} & din2[63:0]);
4159
4160
4161
4162
4163
4164endmodule
4165
4166
4167// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4168// also for pass-gate with decoder
4169
4170
4171
4172
4173
4174// any PARAMS parms go into naming of macro
4175
4176module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_64 (
4177 din0,
4178 sel0,
4179 din1,
4180 sel1,
4181 dout);
4182 input [63:0] din0;
4183 input sel0;
4184 input [63:0] din1;
4185 input sel1;
4186 output [63:0] dout;
4187
4188
4189
4190
4191
4192assign dout[63:0] = ( {64{sel0}} & din0[63:0] ) |
4193 ( {64{sel1}} & din1[63:0]);
4194
4195
4196
4197
4198
4199endmodule
4200
4201
4202
4203
4204
4205
4206// any PARAMS parms go into naming of macro
4207
4208module l2t_csr_ctl_msff_ctl_macro__width_64 (
4209 din,
4210 l1clk,
4211 scan_in,
4212 siclk,
4213 soclk,
4214 dout,
4215 scan_out);
4216wire [63:0] fdin;
4217wire [62:0] so;
4218
4219 input [63:0] din;
4220 input l1clk;
4221 input scan_in;
4222
4223
4224 input siclk;
4225 input soclk;
4226
4227 output [63:0] dout;
4228 output scan_out;
4229assign fdin[63:0] = din[63:0];
4230
4231
4232
4233
4234
4235
4236dff #(64) d0_0 (
4237.l1clk(l1clk),
4238.siclk(siclk),
4239.soclk(soclk),
4240.d(fdin[63:0]),
4241.si({scan_in,so[62:0]}),
4242.so({so[62:0],scan_out}),
4243.q(dout[63:0])
4244);
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257endmodule
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271// any PARAMS parms go into naming of macro
4272
4273module l2t_csr_ctl_msff_ctl_macro__width_4 (
4274 din,
4275 l1clk,
4276 scan_in,
4277 siclk,
4278 soclk,
4279 dout,
4280 scan_out);
4281wire [3:0] fdin;
4282wire [2:0] so;
4283
4284 input [3:0] din;
4285 input l1clk;
4286 input scan_in;
4287
4288
4289 input siclk;
4290 input soclk;
4291
4292 output [3:0] dout;
4293 output scan_out;
4294assign fdin[3:0] = din[3:0];
4295
4296
4297
4298
4299
4300
4301dff #(4) d0_0 (
4302.l1clk(l1clk),
4303.siclk(siclk),
4304.soclk(soclk),
4305.d(fdin[3:0]),
4306.si({scan_in,so[2:0]}),
4307.so({so[2:0],scan_out}),
4308.q(dout[3:0])
4309);
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322endmodule
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4333// also for pass-gate with decoder
4334
4335
4336
4337
4338
4339// any PARAMS parms go into naming of macro
4340
4341module l2t_csr_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_6 (
4342 din0,
4343 sel0,
4344 din1,
4345 sel1,
4346 din2,
4347 sel2,
4348 dout);
4349 input [5:0] din0;
4350 input sel0;
4351 input [5:0] din1;
4352 input sel1;
4353 input [5:0] din2;
4354 input sel2;
4355 output [5:0] dout;
4356
4357
4358
4359
4360
4361assign dout[5:0] = ( {6{sel0}} & din0[5:0] ) |
4362 ( {6{sel1}} & din1[5:0]) |
4363 ( {6{sel2}} & din2[5:0]);
4364
4365
4366
4367
4368
4369endmodule
4370
4371
4372
4373
4374
4375
4376// any PARAMS parms go into naming of macro
4377
4378module l2t_csr_ctl_msff_ctl_macro__en_1__width_64 (
4379 din,
4380 en,
4381 l1clk,
4382 scan_in,
4383 siclk,
4384 soclk,
4385 dout,
4386 scan_out);
4387wire [63:0] fdin;
4388wire [62:0] so;
4389
4390 input [63:0] din;
4391 input en;
4392 input l1clk;
4393 input scan_in;
4394
4395
4396 input siclk;
4397 input soclk;
4398
4399 output [63:0] dout;
4400 output scan_out;
4401assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}});
4402
4403
4404
4405
4406
4407
4408dff #(64) d0_0 (
4409.l1clk(l1clk),
4410.siclk(siclk),
4411.soclk(soclk),
4412.d(fdin[63:0]),
4413.si({scan_in,so[62:0]}),
4414.so({so[62:0],scan_out}),
4415.q(dout[63:0])
4416);
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429endmodule
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443// any PARAMS parms go into naming of macro
4444
4445module l2t_csr_ctl_msff_ctl_macro__width_5 (
4446 din,
4447 l1clk,
4448 scan_in,
4449 siclk,
4450 soclk,
4451 dout,
4452 scan_out);
4453wire [4:0] fdin;
4454wire [3:0] so;
4455
4456 input [4:0] din;
4457 input l1clk;
4458 input scan_in;
4459
4460
4461 input siclk;
4462 input soclk;
4463
4464 output [4:0] dout;
4465 output scan_out;
4466assign fdin[4:0] = din[4:0];
4467
4468
4469
4470
4471
4472
4473dff #(5) d0_0 (
4474.l1clk(l1clk),
4475.siclk(siclk),
4476.soclk(soclk),
4477.d(fdin[4:0]),
4478.si({scan_in,so[3:0]}),
4479.so({so[3:0],scan_out}),
4480.q(dout[4:0])
4481);
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494endmodule
4495
4496
4497
4498
4499
4500
4501
4502
Full OpenSPARC design & verification tarball including full HDL.