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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_csreg_ctl.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_csreg_ctl.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016
1017////////////////////////////////////////////////////////////////////////
1018// Local header file includes / local defines
1019////////////////////////////////////////////////////////////////////////
1020
1021module l2t_csreg_ctl (
1022 tcu_pce_ov,
1023 tcu_aclk,
1024 tcu_bclk,
1025 tcu_scan_en,
1026 arb_csr_wr_en_c7,
1027 arbadr_arbdp_word_addr_c6,
1028 l2clk,
1029 cmp_io_sync_en,
1030 scan_in,
1031 vuaddp_vuad_error_c8,
1032 dirrep_dir_error_c8,
1033 deccck_spcd_corr_err_c8,
1034 deccck_spcd_uncorr_err_c8,
1035 deccck_spcd_notdata_err_c8,
1036 deccck_scrd_corr_err_c8,
1037 deccck_scrd_uncorr_err_c8,
1038 deccck_spcfb_corr_err_c8,
1039 deccck_spcfb_uncorr_err_c8,
1040 deccck_bscd_corr_err_c8,
1041 deccck_bscd_uncorr_err_c8,
1042 deccck_bscd_notdata_err_c8,
1043 tagdp_tag_error_c8,
1044 csr_l2_dir_map_on,
1045 misbuf_vuad_ce_err_c8,
1046 csreg_tagdp_l2_dir_map_on,
1047 csreg_misbuf_l2_dir_map_on,
1048 csreg_filbuf_l2_dir_map_on,
1049 csreg_wr_enable_notdata_nddm_vcid_c9,
1050 notdata_higher_priority_err,
1051 filbuf_mcu_scb_secc_err_d1,
1052 filbuf_mcu_scb_mecc_err_d1,
1053 filbuf_uncorr_err_c8,
1054 filbuf_corr_err_c8,
1055 filbuf_bsc_corr_err_c12,
1056 filbuf_ld64_fb_hit_c12,
1057 rdmat_ev_uerr_r6,
1058 rdmat_ev_cerr_r6,
1059 rdmat_rdmard_uerr_c12,
1060 rdmat_rdmard_cerr_c12,
1061 rdmat_rdmard_notdata_c12,
1062 csr_error_status_vec,
1063 csr_error_status_veu,
1064 csr_error_status_notdata,
1065 csr_l2_bypass_mode_on,
1066 arb_store_err_c8,
1067 oqu_str_ld_hit_c7,
1068 scan_out,
1069 csreg_csr_wr_en_c8,
1070 csreg_csr_erren_wr_en_c8,
1071 csreg_csr_errstate_wr_en_c8,
1072 csreg_csr_errinj_wr_en_c8,
1073 csreg_csr_notdata_wr_en_c8,
1074 csreg_err_state_in_rw,
1075 csreg_err_state_in_mec,
1076 csreg_err_state_in_meu,
1077 csreg_err_state_in,
1078 csreg_csr_synd_wr_en,
1079 csreg_mux1_synd_sel,
1080 csreg_mux2_synd_sel,
1081 csreg_wr_enable_tid_c9,
1082 csreg_csr_tid_wr_en,
1083 csreg_csr_async_wr_en,
1084 csreg_wr_enable_notdata_vcid_c9,
1085 csreg_csr_notdata_vcid_wr_en,
1086 csreg_notdata_err_state_in_rw,
1087 csreg_notdata_err_state_in_mend,
1088 csreg_notdata_err_state_in,
1089 set_async_c9,
1090 error_rw_en,
1091 diag_wr_en,
1092 csreg_notdata_diag_wr_en,
1093 csreg_report_ldrc_inpkt,
1094 arb_fill_vld_c2,
1095 csreg_mux1_addr_sel,
1096 csreg_mux2_addr_sel,
1097 csreg_csr_addr_wr_en,
1098 csreg_csr_notdata_addr_wr_en,
1099 csreg_notdata_addr_mux_sel,
1100 csreg_notdata_error_rw_en,
1101 csreg_csr_rd_mux1_sel_c7,
1102 csreg_csr_rd_mux2_sel_c7,
1103 csreg_csr_rd_mux3_sel_c7,
1104 l2t_rst_fatal_error,
1105 csreg_csr_bist_wr_en_c8,
1106 csreg_l2_cmpr_reg_wr_en_c8,
1107 csreg_l2_mask_reg_wr_en_c8,
1108 csreg_csr_rd_mux4_sel_c7,
1109 csreg_csr_rd_mux_fnl_c7);
1110wire pce_ov;
1111wire stop;
1112wire siclk;
1113wire soclk;
1114wire se;
1115wire l1clk;
1116wire spares_scanin;
1117wire spares_scanout;
1118wire ff_word_addr_c7_scanin;
1119wire ff_word_addr_c7_scanout;
1120wire ff_bist_reg_write_en_d1_scanin;
1121wire ff_bist_reg_write_en_d1_scanout;
1122wire ff_control_reg_write_en_d1_scanin;
1123wire ff_control_reg_write_en_d1_scanout;
1124wire ff_erren_reg_write_en_d1_scanin;
1125wire ff_erren_reg_write_en_d1_scanout;
1126wire ff_errst_reg_write_en_d1_scanin;
1127wire ff_errst_reg_write_en_d1_scanout;
1128wire ff_erraddr_reg_write_en_d1_scanin;
1129wire ff_erraddr_reg_write_en_d1_scanout;
1130wire ff_errinj_reg_write_en_d1_scanin;
1131wire ff_errinj_reg_write_en_d1_scanout;
1132wire ff_mux1_sel_c7_scanin;
1133wire ff_mux1_sel_c7_scanout;
1134wire ff_err_state_new_c9_lvu_scanin;
1135wire ff_err_state_new_c9_lvu_scanout;
1136wire ff_err_state_new_c9_lru_scanin;
1137wire ff_err_state_new_c9_lru_scanout;
1138wire ff_err_state_new_c9_ldsu_scanin;
1139wire ff_err_state_new_c9_ldsu_scanout;
1140wire ff_err_state_new_c9_ldau_scanin;
1141wire ff_err_state_new_c9_ldau_scanout;
1142wire ff_err_state_new_c9_ldwu_scanin;
1143wire ff_err_state_new_c9_ldwu_scanout;
1144wire ff_err_state_new_c9_ldru_scanin;
1145wire ff_err_state_new_c9_ldru_scanout;
1146wire ff_err_state_new_c9_dru_scanin;
1147wire ff_err_state_new_c9_dru_scanout;
1148wire ff_err_state_new_c9_dau_scanin;
1149wire ff_err_state_new_c9_dau_scanout;
1150wire ff_err_state_new_c9_dsu_scanin;
1151wire ff_err_state_new_c9_dsu_scanout;
1152wire ff_err_state_new_c9_lvc_scanin;
1153wire ff_err_state_new_c9_lvc_scanout;
1154wire ff_err_state_new_c9_ltc_scanin;
1155wire ff_err_state_new_c9_ltc_scanout;
1156wire ff_err_state_new_c9_ldsc_scanin;
1157wire ff_err_state_new_c9_ldsc_scanout;
1158wire ff_err_state_new_c9_ldac_scanin;
1159wire ff_err_state_new_c9_ldac_scanout;
1160wire ff_err_state_new_c9_ldwc_scanin;
1161wire ff_err_state_new_c9_ldwc_scanout;
1162wire ff_arb_fill_vld_c3_scanin;
1163wire ff_arb_fill_vld_c3_scanout;
1164wire arb_fill_vld_c3;
1165wire ldrc_reporting_data_in;
1166wire rst_report_ldrc_inpkt_c3;
1167wire ff_ldrc_reporting_scanin;
1168wire ff_ldrc_reporting_scanout;
1169wire csreg_report_ldrc_inpkt_data_in;
1170wire ff_csreg_report_ldrc_inpkt_staging_scanin;
1171wire ff_csreg_report_ldrc_inpkt_staging_scanout;
1172wire ff_err_state_new_c9_ldrc_scanin;
1173wire ff_err_state_new_c9_ldrc_scanout;
1174wire ff_err_state_new_c9_drc_scanin;
1175wire ff_err_state_new_c9_drc_scanout;
1176wire ff_err_state_new_c9_dac_scanin;
1177wire ff_err_state_new_c9_dac_scanout;
1178wire ff_err_state_new_c9_dsc_scanin;
1179wire ff_err_state_new_c9_dsc_scanout;
1180wire ff_store_error_c9_scanin;
1181wire ff_store_error_c9_scanout;
1182wire rdmat_rdmard_uerr_c12_reg_in;
1183wire ff_rdmard_uerr_c13_scanin;
1184wire ff_rdmard_uerr_c13_scanout;
1185wire ff_rdmard_cerr_c13_scanin;
1186wire ff_rdmard_cerr_c13_scanout;
1187wire ff_str_ld_hit_c8_scanin;
1188wire ff_str_ld_hit_c8_scanout;
1189wire ff_str_ld_hit_c9_scanin;
1190wire ff_str_ld_hit_c9_scanout;
1191wire ff_deccck_bscd_uncorr_err_c9_scanin;
1192wire ff_deccck_bscd_uncorr_err_c9_scanout;
1193wire ff_deccck_bscd_corr_err_c9_scanin;
1194wire ff_deccck_bscd_corr_err_c9_scanout;
1195wire ff_deccck_bscd_notdata_err_c9_scanin;
1196wire ff_deccck_bscd_notdata_err_c9_scanout;
1197wire deccck_bscd_notdata_err_c9;
1198wire ff_bsc_corr_err_c13_scanin;
1199wire ff_bsc_corr_err_c13_scanout;
1200wire ff_en_por_c7_d1_scanin;
1201wire ff_en_por_c7_d1_scanout;
1202wire ff_en_por_c7_d2_scanin;
1203wire ff_en_por_c7_d2_scanout;
1204wire en_por_c7_d2;
1205wire ff_en_por_c7_d3_scanin;
1206wire ff_en_por_c7_d3_scanout;
1207wire en_por_c7_d3;
1208wire ff_en_por_c7_d4_scanin;
1209wire ff_en_por_c7_d4_scanout;
1210wire en_por_c7_d4;
1211wire en_por_streatched;
1212wire ff_l2t_rst_fatal_error_scanin;
1213wire ff_l2t_rst_fatal_error_scanout;
1214wire cmp_io_sync_en_r1;
1215wire ff_cmp_io_sync_en_scanin;
1216wire ff_cmp_io_sync_en_scanout;
1217wire ff_err_state_new_c9_nddm_scanin;
1218wire ff_err_state_new_c9_nddm_scanout;
1219wire ff_err_state_new_c9_ndsp_scanin;
1220wire ff_err_state_new_c9_ndsp_scanout;
1221wire ff_rdmard_notdata_err_c13_scanin;
1222wire ff_rdmard_notdata_err_c13_scanout;
1223wire rdmard_notdata_err_c13;
1224wire notdata_reg_write_en;
1225wire ff_notdata_reg_write_en_d1_scanin;
1226wire ff_notdata_reg_write_en_d1_scanout;
1227wire notdata_reg_write_en_d1;
1228wire csreg_csr_l2_mask_reg_wr_en;
1229wire ff_l2_mask_reg_wr_en_scanin;
1230wire ff_l2_mask_reg_wr_en_scanout;
1231wire csreg_csr_l2_mask_reg_wr_en_d1;
1232wire csreg_csr_l2_cmpr_reg_wr_en;
1233wire ff_l2_cmpr_reg_wr_en_scanin;
1234wire ff_l2_cmpr_reg_wr_en_scanout;
1235wire csreg_csr_l2_cmpr_reg_wr_en_d1;
1236
1237
1238 input tcu_pce_ov;
1239 input tcu_aclk;
1240 input tcu_bclk;
1241 input tcu_scan_en;
1242
1243input arb_csr_wr_en_c7;
1244input [4:0] arbadr_arbdp_word_addr_c6;
1245
1246input l2clk;
1247input cmp_io_sync_en;
1248input scan_in;
1249
1250// from vuaddp
1251input vuaddp_vuad_error_c8; // from vuad dp.
1252// from arb.
1253input dirrep_dir_error_c8 ; // from the directory
1254
1255
1256// from l2t_deccck_ctl.sv
1257input deccck_spcd_corr_err_c8 ; // error in 156 bit data
1258input deccck_spcd_uncorr_err_c8 ; // error in 156 bit data
1259input deccck_spcd_notdata_err_c8 ; // Notdata error in 156 bit data
1260input deccck_scrd_corr_err_c8 ;// error in 156 bit data
1261input deccck_scrd_uncorr_err_c8 ;// error in 156 bit data
1262input deccck_spcfb_corr_err_c8 ; // error in 156 bit data or error
1263input deccck_spcfb_uncorr_err_c8 ; // error in 156 bit data or error
1264input deccck_bscd_corr_err_c8; // error in 156 bit data ( for WR8s)
1265input deccck_bscd_uncorr_err_c8; // error in 156 bit data ( for WR8s)
1266input deccck_bscd_notdata_err_c8; // notdata error in 156 bit data ( for WR8s)
1267
1268
1269
1270// from l2t_tagd_ctl.sv
1271input tagdp_tag_error_c8;
1272
1273
1274// start int 5.0 changes
1275input csr_l2_dir_map_on; // POST_4.2 ( Left)
1276input misbuf_vuad_ce_err_c8;
1277
1278//output csreg_filbuf_deccck_scrd_corr_err_c8; // POST_4.2 ( Top)
1279//output csreg_filbuf_deccck_scrd_uncorr_err_c8; // POST_4.2 ( Top)
1280//output csreg_misbuf_deccck_spcfb_corr_err_c8; // POST_4.2 (Top)
1281//output csreg_misbuf_deccck_spcd_corr_err_c8 ; // POST_4.2 (Top)
1282//output csreg_filbuf_deccck_bscd_corr_err_c8; // POST_4.2 ( Top)
1283//output csreg_filbuf_deccck_bscd_uncorr_err_c8; // POST_4.2 ( Top)
1284//output csreg_arb_data_ecc_active_c3; // POST_4.2 ( Top)
1285//output csreg_decc_data_ecc_active_c3; // POST_4.2 ( Top)
1286output csreg_tagdp_l2_dir_map_on; // POST_4.2 ( Left/Bottom)
1287output csreg_misbuf_l2_dir_map_on; // POST_4.2 ( Top)
1288output csreg_filbuf_l2_dir_map_on; // POST_4.2 ( Top)
1289
1290output csreg_wr_enable_notdata_nddm_vcid_c9;
1291
1292//output csreg_arb_dbginit_l ; // POST_4.2 TOp
1293//output csreg_misbuf_dbginit_l ; // POST_4.2 Top
1294////output csreg_filbuf_dbginit_l ; // POST_4.2 Top
1295//output csreg_tag_dbginit_l ; // POST_4.2 Top
1296//output csreg_tagdp_ctl_dbginit_l ; // POST_4.2 Left
1297//output csreg_csr_dbginit_l ; // POST_4.2 Left
1298//output csreg_wbuf_dbginit_l ; // POST_4.2 Top
1299
1300// End 5.0 changes
1301
1302
1303input notdata_higher_priority_err;
1304
1305// from l2t_filbuf_ctl.sv
1306input filbuf_mcu_scb_secc_err_d1; // scrub error from DRAM
1307input filbuf_mcu_scb_mecc_err_d1; // scrub error from DRAM
1308input filbuf_uncorr_err_c8 ; // Errors from DRAM in response to a read
1309input filbuf_corr_err_c8 ; // Errors from DRAM in response to a read
1310input filbuf_bsc_corr_err_c12; // Errors from DRAM in response to a rd64 miss.
1311input filbuf_ld64_fb_hit_c12; // qualification for errors found in
1312 // rdma rd stream out data path.
1313
1314// from l2t_rdmat_ctl.sv
1315input rdmat_ev_uerr_r6;// wb errors from the evict dp.
1316input rdmat_ev_cerr_r6;// wb errors from the evict dp.
1317input rdmat_rdmard_uerr_c12;
1318input rdmat_rdmard_cerr_c12;
1319input rdmat_rdmard_notdata_c12;
1320
1321// from csr
1322input csr_error_status_vec;
1323input csr_error_status_veu;
1324input csr_error_status_notdata;
1325input csr_l2_bypass_mode_on;
1326
1327
1328// from arbdec
1329input arb_store_err_c8;
1330
1331input oqu_str_ld_hit_c7; // from oqu.
1332
1333// csreg
1334output scan_out;
1335
1336// write enables for all csrs after address decode
1337
1338output csreg_csr_wr_en_c8 ;
1339output csreg_csr_erren_wr_en_c8;
1340output csreg_csr_errstate_wr_en_c8;
1341output csreg_csr_errinj_wr_en_c8;
1342output csreg_csr_notdata_wr_en_c8;
1343
1344// 21 control bits in Status register.
1345output csreg_err_state_in_rw ;
1346output csreg_err_state_in_mec ;
1347output csreg_err_state_in_meu ;
1348output [`ERR_LDAC:`ERR_LVC] csreg_err_state_in ;
1349
1350// L2 Error syndrome (for UE and CE only)
1351
1352output csreg_csr_synd_wr_en;
1353output [1:0] csreg_mux1_synd_sel;
1354output [1:0] csreg_mux2_synd_sel;
1355
1356// TID(VCID) write enable for UE and CE
1357
1358output csreg_wr_enable_tid_c9;
1359output csreg_csr_tid_wr_en;
1360output csreg_csr_async_wr_en;
1361
1362// VCID write enable for Notdata
1363
1364output csreg_wr_enable_notdata_vcid_c9;
1365output csreg_csr_notdata_vcid_wr_en;
1366
1367
1368// Notdata error bits in L2 Notdata register
1369
1370output csreg_notdata_err_state_in_rw;
1371output csreg_notdata_err_state_in_mend;
1372output [`ERR_NDSP:`ERR_NDDM] csreg_notdata_err_state_in;
1373
1374// start int 5.0 changes
1375output set_async_c9 ; // ADDED POST_4.0
1376output error_rw_en ; // ADDED POST_4.0
1377
1378// Diagnostic write enable for UE/CE Error status register
1379output diag_wr_en; // ADDED POST_4.0
1380
1381// Diagnostic write enable for Notdata Error register
1382
1383output csreg_notdata_diag_wr_en;
1384output csreg_report_ldrc_inpkt;
1385input arb_fill_vld_c2;
1386
1387// end int 5.0 changes
1388
1389
1390output [3:0] csreg_mux1_addr_sel;
1391output [2:0] csreg_mux2_addr_sel;
1392
1393// UE/CE EAR write enable
1394output csreg_csr_addr_wr_en;
1395
1396// Notdata EAR write enable
1397output csreg_csr_notdata_addr_wr_en;
1398
1399// Notdata EAR address select
1400
1401output [2:0] csreg_notdata_addr_mux_sel;
1402
1403// Notdata RW write enable
1404
1405output csreg_notdata_error_rw_en;
1406
1407// read enables.
1408output [3:0] csreg_csr_rd_mux1_sel_c7;
1409output csreg_csr_rd_mux2_sel_c7;
1410output [1:0] csreg_csr_rd_mux3_sel_c7;
1411
1412// these outputs need to be removed.
1413output l2t_rst_fatal_error;
1414output csreg_csr_bist_wr_en_c8; // POST_2.0
1415
1416// debug changes
1417output csreg_l2_cmpr_reg_wr_en_c8;
1418output csreg_l2_mask_reg_wr_en_c8;
1419output [1:0] csreg_csr_rd_mux4_sel_c7;
1420output [1:0] csreg_csr_rd_mux_fnl_c7;
1421
1422
1423
1424//////////////////////////////////////////////////
1425// L1 clk header
1426//////////////////////////////////////////////////
1427assign pce_ov = tcu_pce_ov;
1428assign stop = 1'b0;
1429assign siclk = tcu_aclk;
1430assign soclk = tcu_bclk;
1431assign se = tcu_scan_en;
1432
1433l2t_csreg_ctl_l1clkhdr_ctl_macro clkgen (
1434 .l2clk(l2clk),
1435 .l1en(1'b1 ),
1436 .l1clk(l1clk),
1437 .pce_ov(pce_ov),
1438 .stop(stop),
1439 .se(se));
1440
1441//////////////////////////////////////////////////
1442
1443//////////////////////////////////////////
1444// Spare gate insertion
1445//////////////////////////////////////////
1446l2t_csreg_ctl_spare_ctl_macro__num_4 spares (
1447 .scan_in(spares_scanin),
1448 .scan_out(spares_scanout),
1449 .l1clk (l1clk),
1450 .siclk(siclk),
1451 .soclk(soclk)
1452);
1453//////////////////////////////////////////
1454
1455
1456
1457wire [1:0] new_notdata_err_vec_c9;
1458wire [1:0] wr_notdata_err_vec_c9;
1459wire report_ldrc_inpkt;
1460wire csreg_report_ldrc_inpkt_c4,csreg_report_ldrc_inpkt_c5;
1461wire csreg_report_ldrc_inpkt_c52,csreg_report_ldrc_inpkt_c6;
1462wire csreg_report_ldrc_inpkt_c7,csreg_report_ldrc_inpkt_c8,csreg_report_ldrc_inpkt_c9;
1463
1464wire control_reg_write_en, control_reg_write_en_d1;
1465wire erren_reg_write_en, erren_reg_write_en_d1;
1466wire errst_reg_write_en, errst_reg_write_en_d1;
1467wire erraddr_reg_write_en, erraddr_reg_write_en_d1;
1468wire errinj_reg_write_en, errinj_reg_write_en_d1;
1469
1470wire [4:0] word_addr_c7;
1471wire [2:0] mux1_sel_c6, mux1_sel_c7;
1472wire addr2_c7;
1473
1474wire [63:0] err_status_in;
1475wire [63:0] err_state_new_c9;
1476wire [63:0] err_state_new_c8;
1477wire [7:0] new_uerr_vec_c9 ;
1478wire [7:0] wr_uerr_vec_c9 ;
1479wire [7:0] new_cerr_vec_c9 ;
1480wire [7:0] wr_cerr_vec_c9 ;
1481wire [`ERR_NDSP:`ERR_NDDM] err_state_notdata_new_c8;
1482wire [`ERR_NDSP:`ERR_NDDM] err_state_notdata_new_c9;
1483wire [`ERR_MEND:`ERR_NDDM] err_status_notdata_in;
1484
1485wire rdma_pst_err_c9;
1486wire rdma_pst_notdata_err_c9;
1487wire store_error_c9 ;
1488wire rdmard_uerr_c13, rdmard_cerr_c13 ;
1489
1490wire str_ld_hit_c8, str_ld_hit_c9 ;
1491wire err_sel, new_err_sel;
1492wire rdmard_addr_sel_c13;
1493wire bsc_corr_err_c13;
1494
1495wire en_por_c7, en_por_c7_d1;
1496wire bist_reg_write_en, bist_reg_write_en_d1;
1497wire [3:0] mux1_addr_sel_tmp;
1498wire [2:0] mux2_addr_sel_tmp ;
1499wire pipe_addr_sel;
1500
1501// int 5.0 changes
1502wire deccck_bscd_uncorr_err_c9, deccck_bscd_corr_err_c9 ;
1503wire csreg_csr_erraddr_wr_en_c8;
1504wire csreg_wr_enable_async_c9;
1505wire error_spc, error_bsc ;
1506
1507// start int 5.0 changes
1508// --------------\/------- Added repeaters post_4.2 ---\/ --------
1509
1510// assign csreg_arb_dbginit_l = dbginit_l ;
1511// assign csreg_misbuf_dbginit_l = dbginit_l ;
1512// assign csreg_filbuf_dbginit_l = dbginit_l ;
1513// assign csreg_wbuf_dbginit_l = dbginit_l ;
1514// assign csreg_csr_dbginit_l = dbginit_l ;
1515// assign csreg_tag_dbginit_l = dbginit_l ;
1516// assign csreg_tagdp_ctl_dbginit_l = dbginit_l ;
1517//////////
1518 //decc_spcd_uncorr_err_c8 repeater not needed.
1519 //decc_spcfb_corr_err_c8 repeater not needed.
1520
1521// assign csreg_filbuf_deccck_scrd_corr_err_c8 = deccck_scrd_corr_err_c8;
1522// assign csreg_filbuf_deccck_scrd_uncorr_err_c8 = deccck_scrd_uncorr_err_c8 ;
1523// assign csreg_filbuf_deccck_bscd_corr_err_c8 = deccck_bscd_corr_err_c8 ;
1524// assign csreg_filbuf_deccck_bscd_uncorr_err_c8 = deccck_bscd_uncorr_err_c8 ;
1525// assign csreg_misbuf_deccck_spcd_corr_err_c8 = deccck_spcd_corr_err_c8 ;
1526// assign csreg_misbuf_deccck_spcfb_corr_err_c8 = deccck_spcfb_corr_err_c8 ;
1527// assign csreg_arb_data_ecc_active_c3 = tag_data_ecc_active_c3 ;
1528// assign csreg_decc_data_ecc_active_c3 = tag_data_ecc_active_c3 ;
1529 assign csreg_tagdp_l2_dir_map_on = csr_l2_dir_map_on ;
1530 assign csreg_misbuf_l2_dir_map_on = csr_l2_dir_map_on ;
1531 assign csreg_filbuf_l2_dir_map_on = csr_l2_dir_map_on ;
1532
1533// --------------\/------- Added repeaters post_4.2 ---\/ --------
1534// end int 5.0 changes
1535
1536
1537
1538/////////////////////////////////////////////////////
1539// Exception cases:
1540//
1541// - Wr8s will cause DAU to be set in OFF mode. ( if an uncorr err
1542// is signalled by DRAM).
1543// - Wr8 will cause DAC to be set. in OFF/ON mode.
1544/////////////////////////////////////////////////////
1545
1546////////////////////////////////////////////////////////////////////////////////
1547// CSR pipeline.
1548//
1549//============================================================
1550// C7 C8 C9
1551//============================================================
1552// generate mux out xmit
1553// mux selects rd data to
1554// ccx
1555//
1556// enable
1557// a write
1558//
1559//============================================================
1560//
1561// Eventhough the Write and Read operations do not happen in the
1562// same cycle, no data forwarding is required because the write
1563// is followed by ATLEAST one bubble
1564//
1565// Errors update the ESR and EAR in the C10 cycle.
1566// Hence a CSR load may actually miss the error that occurred
1567// just before it.
1568////////////////////////////////////////////////////////////////////////////////
1569
1570//////////////////////////
1571// I) WR ENABLE GENERATION
1572//
1573// Write pipeline.
1574// A CSR store is performed
1575// in the C8 cycle.
1576//////////////////////////
1577
1578l2t_csreg_ctl_msff_ctl_macro__width_5 ff_word_addr_c7
1579 (.din(arbadr_arbdp_word_addr_c6[4:0]),
1580 .scan_in(ff_word_addr_c7_scanin),
1581 .scan_out(ff_word_addr_c7_scanout),
1582 .l1clk(l1clk),
1583 .dout(word_addr_c7[4:0]),
1584 .siclk(siclk),
1585 .soclk(soclk)
1586
1587);
1588
1589//////////////////////////
1590// BIST REG A8
1591// This register can be written by software or
1592// by JTAG via the CTU
1593//////////////////////////
1594
1595
1596
1597assign bist_reg_write_en = arb_csr_wr_en_c7 &
1598 (word_addr_c7[2:0]==3'h0 ) ; // A8
1599
1600l2t_csreg_ctl_msff_ctl_macro__width_1 ff_bist_reg_write_en_d1
1601 (.din(bist_reg_write_en),
1602 .scan_in(ff_bist_reg_write_en_d1_scanin),
1603 .scan_out(ff_bist_reg_write_en_d1_scanout),
1604 .l1clk(l1clk),
1605 .dout(bist_reg_write_en_d1),
1606 .siclk(siclk),
1607 .soclk(soclk)
1608
1609);
1610
1611assign csreg_csr_bist_wr_en_c8 = bist_reg_write_en_d1 ;
1612
1613//////////////////////////
1614// CONTROL REG A9
1615//////////////////////////
1616assign control_reg_write_en = arb_csr_wr_en_c7 &
1617 (word_addr_c7[2:0]==3'h1 ) ; // A9
1618
1619l2t_csreg_ctl_msff_ctl_macro__width_1 ff_control_reg_write_en_d1
1620 (.din(control_reg_write_en),
1621 .scan_in(ff_control_reg_write_en_d1_scanin),
1622 .scan_out(ff_control_reg_write_en_d1_scanout),
1623 .l1clk(l1clk),
1624 .dout(control_reg_write_en_d1),
1625 .siclk(siclk),
1626 .soclk(soclk)
1627
1628);
1629
1630assign csreg_csr_wr_en_c8 = control_reg_write_en_d1 ;
1631
1632//////////////////////////
1633// ERR ENABLE REG AA
1634//////////////////////////
1635assign erren_reg_write_en = arb_csr_wr_en_c7 &
1636 (word_addr_c7[2:0]==3'h2) ; // AA
1637
1638l2t_csreg_ctl_msff_ctl_macro__width_1 ff_erren_reg_write_en_d1
1639 (.din(erren_reg_write_en),
1640 .scan_in(ff_erren_reg_write_en_d1_scanin),
1641 .scan_out(ff_erren_reg_write_en_d1_scanout),
1642 .l1clk(l1clk),
1643 .dout(erren_reg_write_en_d1),
1644 .siclk(siclk),
1645 .soclk(soclk)
1646
1647);
1648
1649assign csreg_csr_erren_wr_en_c8 = erren_reg_write_en_d1 ;
1650
1651//////////////////////////
1652// ERR STATE REG AB
1653//////////////////////////
1654assign errst_reg_write_en = arb_csr_wr_en_c7 &
1655 (word_addr_c7[2:0]==3'h3) ; // AB
1656
1657l2t_csreg_ctl_msff_ctl_macro__width_1 ff_errst_reg_write_en_d1
1658 (.din(errst_reg_write_en), .l1clk(l1clk),
1659 .scan_in(ff_errst_reg_write_en_d1_scanin),
1660 .scan_out(ff_errst_reg_write_en_d1_scanout),
1661 .dout(errst_reg_write_en_d1),
1662 .siclk(siclk),
1663 .soclk(soclk)
1664
1665);
1666
1667assign csreg_csr_errstate_wr_en_c8 = errst_reg_write_en_d1 ;
1668
1669//////////////////////////
1670// ERR ADDR REG AC
1671//////////////////////////
1672assign erraddr_reg_write_en = arb_csr_wr_en_c7 &
1673 (word_addr_c7[2:0]==3'h4) ; // AC
1674
1675l2t_csreg_ctl_msff_ctl_macro__width_1 ff_erraddr_reg_write_en_d1
1676 (.din(erraddr_reg_write_en), .l1clk(l1clk),
1677 .scan_in(ff_erraddr_reg_write_en_d1_scanin),
1678 .scan_out(ff_erraddr_reg_write_en_d1_scanout),
1679 .dout(erraddr_reg_write_en_d1),
1680 .siclk(siclk),
1681 .soclk(soclk)
1682
1683);
1684
1685
1686assign csreg_csr_erraddr_wr_en_c8 = erraddr_reg_write_en_d1 ;
1687
1688//////////////////////////
1689// ERR INJ REG AD
1690//////////////////////////
1691assign errinj_reg_write_en = arb_csr_wr_en_c7 &
1692 (word_addr_c7[2:0]==3'h5) ; // AD
1693
1694
1695l2t_csreg_ctl_msff_ctl_macro__width_1 ff_errinj_reg_write_en_d1
1696 (.din(errinj_reg_write_en), .l1clk(l1clk),
1697 .scan_in(ff_errinj_reg_write_en_d1_scanin),
1698 .scan_out(ff_errinj_reg_write_en_d1_scanout),
1699 .dout(errinj_reg_write_en_d1),
1700 .siclk(siclk),
1701 .soclk(soclk)
1702
1703);
1704
1705assign csreg_csr_errinj_wr_en_c8 = errinj_reg_write_en_d1 ;
1706
1707//////////////////////////
1708// THIS REGISTER HAS BEEN REMOVED FROM THE SPEC
1709// STM REG AE or AF
1710//////////////////////////
1711//assign stm_reg_write_en = arb_csr_wr_en_c7 &
1712// ( (word_addr_c7[2:0]==3'h6) |
1713// (word_addr_c7[2:0]==3'h7)
1714// ) ;
1715//msff_ctl_macro ff_stm_reg_write_en_d1 (width=1)
1716// (.din(stm_reg_write_en), .l1clk(l1clk),
1717// .dout(stm_reg_write_en_d1),
1718//
1719// .scan_in(),
1720// .scan_out()
1721//);
1722//
1723//
1724//assign csreg_csr_stm_wr_en_c8 = stm_reg_write_en_d1 ;
1725//
1726//
1727//
1728//
1729//
1730//
1731//////////////////////////
1732// RD enable generation.
1733//////////////////////////
1734
1735assign mux1_sel_c6[0] = ( arbadr_arbdp_word_addr_c6[1:0] == 2'd0 ) ; // A8 or Ac
1736assign mux1_sel_c6[1] = ( arbadr_arbdp_word_addr_c6[1:0] == 2'd1 ) ; // A9 or Ad
1737assign mux1_sel_c6[2] = ( arbadr_arbdp_word_addr_c6[1:0] == 2'd2 ) ; //Aa or Ae
1738
1739
1740l2t_csreg_ctl_msff_ctl_macro__width_3 ff_mux1_sel_c7
1741 (.din(mux1_sel_c6[2:0]), .l1clk(l1clk),
1742 .scan_in(ff_mux1_sel_c7_scanin),
1743 .scan_out(ff_mux1_sel_c7_scanout),
1744 .dout(mux1_sel_c7[2:0]),
1745 .siclk(siclk),
1746 .soclk(soclk)
1747
1748);
1749
1750assign csreg_csr_rd_mux1_sel_c7[0] = mux1_sel_c7[0] ;
1751assign csreg_csr_rd_mux1_sel_c7[1] = mux1_sel_c7[1] ;
1752assign csreg_csr_rd_mux1_sel_c7[2] = mux1_sel_c7[2] ;
1753assign csreg_csr_rd_mux1_sel_c7[3] = ~(|(mux1_sel_c7[2:0]));
1754
1755assign csreg_csr_rd_mux2_sel_c7 = ~( mux1_sel_c7[0] | mux1_sel_c7[1] ) ;
1756
1757
1758assign csreg_csr_rd_mux3_sel_c7[0] = ~word_addr_c7[2] ;
1759assign csreg_csr_rd_mux3_sel_c7[1] = word_addr_c7[2] ;
1760
1761
1762// Debug related signals
1763assign csreg_csr_rd_mux4_sel_c7[0] = (word_addr_c7[4:0]==5'h1F );
1764assign csreg_csr_rd_mux4_sel_c7[1] = (word_addr_c7[4:0]==5'h0F );
1765
1766assign csreg_csr_rd_mux_fnl_c7[0] = ~(csreg_csr_rd_mux4_sel_c7[0] | csreg_csr_rd_mux4_sel_c7[1]);
1767assign csreg_csr_rd_mux_fnl_c7[1] = csreg_csr_rd_mux4_sel_c7[0] | csreg_csr_rd_mux4_sel_c7[1];
1768
1769
1770
1771
1772
1773//////////////////////////
1774// ERROR LOGGING LOGIC.
1775// UNCORR ERRORS.
1776//////////////////////////
1777
1778/////////////////////////////////////////////////////
1779// LVU bit
1780// vuad UE. Addr=C9, syndrome = {VD_syndrome[5:0], UA_syndrome[5:0] }
1781// set this bit, if there is no pending uncorr err.
1782/////////////////////////////////////////////////////
1783
1784assign err_state_new_c8[`ERR_LVU] = vuaddp_vuad_error_c8 ;
1785
1786l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_lvu
1787 (.din(err_state_new_c8[`ERR_LVU]), .l1clk(l1clk),
1788 .scan_in(ff_err_state_new_c9_lvu_scanin),
1789 .scan_out(ff_err_state_new_c9_lvu_scanout),
1790 .dout(err_state_new_c9[`ERR_LVU]),
1791 .siclk(siclk),
1792 .soclk(soclk)
1793
1794);
1795
1796//assign err_status_in[`ERR_LVU] = ~(csr_error_status_veu | err_state_new_c9[`ERR_LVU]) & err_state_new_c9[`ERR_LVU] ;
1797assign err_status_in[`ERR_LVU] = ~csr_error_status_veu & err_state_new_c9[`ERR_LVU];
1798
1799/////////////////////////////////////////////////////
1800// LRU bit
1801// dir parity. Addr=index syndrome = X
1802// set this bit if no lvu occurs and no pending uncorr err.
1803/////////////////////////////////////////////////////
1804
1805assign err_state_new_c8[`ERR_LRU] = dirrep_dir_error_c8 ; // directory error
1806
1807l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_lru
1808 (.din(err_state_new_c8[`ERR_LRU]), .l1clk(l1clk),
1809 .scan_in(ff_err_state_new_c9_lru_scanin),
1810 .scan_out(ff_err_state_new_c9_lru_scanout),
1811 .dout(err_state_new_c9[`ERR_LRU]),
1812 .siclk(siclk),
1813 .soclk(soclk)
1814
1815);
1816
1817assign err_status_in[`ERR_LRU] = ~( err_state_new_c9[`ERR_LVU] |
1818 csr_error_status_veu ) &
1819 err_state_new_c9[`ERR_LRU] ;
1820// int 5.0 changes start
1821
1822/////////////////////////////////////////////////////
1823// LDSU bit
1824// set for a scrub
1825// Address=C7. Syndrome = data_syndrome from decc
1826/////////////////////////////////////////////////////
1827
1828assign err_state_new_c8[`ERR_LDSU] = deccck_scrd_uncorr_err_c8 ; // scrub uncorr err
1829
1830l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldsu
1831 (.din(err_state_new_c8[`ERR_LDSU]), .l1clk(l1clk),
1832 .scan_in(ff_err_state_new_c9_ldsu_scanin),
1833 .scan_out(ff_err_state_new_c9_ldsu_scanout),
1834 .dout(err_state_new_c9[`ERR_LDSU]),
1835 .siclk(siclk),
1836 .soclk(soclk)
1837
1838);
1839
1840assign err_status_in[`ERR_LDSU] = ~( err_state_new_c9[`ERR_LVU] |
1841 err_state_new_c9[`ERR_LRU] |
1842 csr_error_status_veu ) &
1843 err_state_new_c9[`ERR_LDSU] ;
1844
1845// int 5.0 changes end
1846
1847/////////////////////////////////////////////////////
1848// LDAU bit
1849// set for any kind of access LD/ST/ATOMIC/PST
1850// Address=C9. Syndrome = data_syndrome from deccck
1851// Only set for accesses that hit the $
1852/////////////////////////////////////////////////////
1853
1854assign err_state_new_c8[`ERR_LDAU] = deccck_spcd_uncorr_err_c8 ; // data uncorr err
1855
1856l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldau
1857 (.din(err_state_new_c8[`ERR_LDAU]), .l1clk(l1clk),
1858 .scan_in(ff_err_state_new_c9_ldau_scanin),
1859 .scan_out(ff_err_state_new_c9_ldau_scanout),
1860 .dout(err_state_new_c9[`ERR_LDAU]),
1861 .siclk(siclk),
1862 .soclk(soclk)
1863
1864);
1865
1866assign err_status_in[`ERR_LDAU] = ~( err_state_new_c9[`ERR_LVU] |
1867 err_state_new_c9[`ERR_LRU] |
1868 csr_error_status_veu ) &
1869 err_state_new_c9[`ERR_LDAU] ;
1870
1871/////////////////////////////////////////////////////
1872// LDWU bit // eviction error logging done in cycles r7 through r14
1873// of an evict. Address logging is also done in the
1874// same 8 cycle window
1875// ??? may need to change leave_state2 counter to 13
1876// in wbuf.v
1877/////////////////////////////////////////////////////
1878
1879assign err_state_new_c8[`ERR_LDWU] = rdmat_ev_uerr_r6 ; // eviction uncorr err
1880
1881l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldwu
1882 (.din(err_state_new_c8[`ERR_LDWU]), .l1clk(l1clk),
1883 .scan_in(ff_err_state_new_c9_ldwu_scanin),
1884 .scan_out(ff_err_state_new_c9_ldwu_scanout),
1885 .dout(err_state_new_c9[`ERR_LDWU]),
1886 .siclk(siclk),
1887 .soclk(soclk)
1888
1889);
1890
1891assign err_status_in[`ERR_LDWU] = ~( err_state_new_c9[`ERR_LVU] |
1892 err_state_new_c9[`ERR_LRU] |
1893 err_state_new_c9[`ERR_LDAU] |
1894 err_state_new_c9[`ERR_LDSU] |
1895 csr_error_status_veu ) &
1896 err_state_new_c9[`ERR_LDWU] ;
1897
1898
1899/////////////////////////////////////////////////////
1900// LDRU bit
1901// Set for an RDMA Read or an RDMA Write ( Partial )
1902// or RDMA Write which
1903// returns with an error from the DRAM.
1904// Only set for accesses that hit the $
1905/////////////////////////////////////////////////////
1906
1907
1908// int 5.0 changes : Fix for bug 92901
1909//assign err_state_new_c8[`ERR_LDRU] = deccck_bscd_uncorr_err_c8 |
1910// ( (rdmat_rdmard_uerr_c12 | rdmat_rdmard_notdata_c12) &
1911// ~filbuf_ld64_fb_hit_c12 ) ;
1912//
1913
1914assign err_state_new_c8[`ERR_LDRU] = deccck_bscd_uncorr_err_c8 |
1915 ( rdmat_rdmard_uerr_c12 & ~filbuf_ld64_fb_hit_c12 ) ;
1916
1917
1918
1919
1920
1921
1922// int 5.0 changes
1923l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldru
1924 (.din(err_state_new_c8[`ERR_LDRU]), .l1clk(l1clk),
1925 .scan_in(ff_err_state_new_c9_ldru_scanin),
1926 .scan_out(ff_err_state_new_c9_ldru_scanout),
1927 .dout(err_state_new_c9[`ERR_LDRU]),
1928 .siclk(siclk),
1929 .soclk(soclk)
1930
1931);
1932
1933// int 5.0 changes
1934assign err_status_in[`ERR_LDRU] = ~( err_state_new_c9[`ERR_LVU] |
1935 err_state_new_c9[`ERR_LRU] |
1936 err_state_new_c9[`ERR_LDAU] |
1937 err_state_new_c9[`ERR_LDSU] |
1938 err_state_new_c9[`ERR_LDWU] |
1939 csr_error_status_veu ) &
1940 err_state_new_c9[`ERR_LDRU] ;
1941
1942// int 5.0 changes
1943/////////////////////////////////////////////////////
1944// DRU bit
1945// FB hit only for LD64/
1946// Wr8s will cause DAU to be set in OFF mode.
1947/////////////////////////////////////////////////////
1948
1949assign err_state_new_c8[`ERR_DRU] = ( (rdmat_rdmard_uerr_c12 | rdmat_rdmard_notdata_c12) &
1950 filbuf_ld64_fb_hit_c12) ;
1951
1952l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_dru
1953 (.din(err_state_new_c8[`ERR_DRU]), .l1clk(l1clk),
1954 .scan_in(ff_err_state_new_c9_dru_scanin),
1955 .scan_out(ff_err_state_new_c9_dru_scanout),
1956 .dout(err_state_new_c9[`ERR_DRU]),
1957 .siclk(siclk),
1958 .soclk(soclk)
1959
1960);
1961
1962assign err_status_in[`ERR_DRU] = ~( err_state_new_c9[`ERR_LVU] |
1963 err_state_new_c9[`ERR_LRU] |
1964 err_state_new_c9[`ERR_LDAU] |
1965 err_state_new_c9[`ERR_LDRU] |
1966 err_state_new_c9[`ERR_LDSU] |
1967 err_state_new_c9[`ERR_LDRU] |
1968 err_state_new_c9[`ERR_LDWU] |
1969 csr_error_status_veu) &
1970 err_state_new_c9[`ERR_DRU] ;
1971
1972/////////////////////////////////////////////////////
1973// DAU bit
1974// only set for a FB hit or a FILL
1975/////////////////////////////////////////////////////
1976
1977assign err_state_new_c8[`ERR_DAU] =
1978 ( deccck_spcfb_uncorr_err_c8 | // from a spc instruction
1979 filbuf_uncorr_err_c8 ) ; // from a fill.
1980
1981l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_dau
1982 (.din(err_state_new_c8[`ERR_DAU]), .l1clk(l1clk),
1983 .scan_in(ff_err_state_new_c9_dau_scanin),
1984 .scan_out(ff_err_state_new_c9_dau_scanout),
1985 .dout(err_state_new_c9[`ERR_DAU]),
1986 .siclk(siclk),
1987 .soclk(soclk)
1988
1989);
1990
1991assign err_status_in[`ERR_DAU] = ~( err_state_new_c9[`ERR_LVU] |
1992 err_state_new_c9[`ERR_LRU] |
1993 err_state_new_c9[`ERR_LDAU] |
1994 err_state_new_c9[`ERR_LDRU] |
1995 err_state_new_c9[`ERR_LDSU] |
1996 err_state_new_c9[`ERR_LDRU] |
1997 err_state_new_c9[`ERR_LDWU] |
1998 err_state_new_c9[`ERR_DRU] |
1999 csr_error_status_veu ) &
2000 err_state_new_c9[`ERR_DAU] ;
2001
2002/////////////////////////////////////////////////////
2003// DSU bit
2004// This bit does not influence MEU
2005// and does not need to go through the
2006// priority logic
2007/////////////////////////////////////////////////////
2008
2009assign err_state_new_c8[`ERR_DSU] = filbuf_mcu_scb_mecc_err_d1 ;
2010 // scrub in DRAM causing an error.
2011
2012l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_dsu
2013 (.din(err_state_new_c8[`ERR_DSU]), .l1clk(l1clk),
2014 .scan_in(ff_err_state_new_c9_dsu_scanin),
2015 .scan_out(ff_err_state_new_c9_dsu_scanout),
2016 .dout(err_state_new_c9[`ERR_DSU]),
2017 .siclk(siclk),
2018 .soclk(soclk)
2019
2020);
2021
2022assign err_status_in[`ERR_DSU] = err_state_new_c9[`ERR_DSU] ;
2023
2024
2025
2026/////////////////////////////////////////////////////
2027// MEU bit
2028// Multiple error uncorrectable bit is set if multiple
2029// uncorrectable errors happen in the same cycle or
2030// are separated in time.
2031// This bit is set if the vector being written in
2032// is different from the vector that is detected
2033/////////////////////////////////////////////////////
2034
2035assign new_uerr_vec_c9 = { err_state_new_c9[`ERR_LDAU],
2036 err_state_new_c9[`ERR_LDWU],
2037 err_state_new_c9[`ERR_LDRU],
2038 err_state_new_c9[`ERR_LDSU],
2039 err_state_new_c9[`ERR_LRU],
2040 err_state_new_c9[`ERR_LVU],
2041 err_state_new_c9[`ERR_DAU],
2042 err_state_new_c9[`ERR_DRU] } ;
2043
2044// atleast 10 gates to do the priority.
2045assign wr_uerr_vec_c9 = { err_status_in[`ERR_LDAU],
2046 err_status_in[`ERR_LDWU],
2047 err_status_in[`ERR_LDRU],
2048 err_status_in[`ERR_LDSU],
2049 err_status_in[`ERR_LRU],
2050 err_status_in[`ERR_LVU],
2051 err_status_in[`ERR_DAU],
2052 err_status_in[`ERR_DRU] } ;
2053
2054assign err_status_in[`ERR_MEU] = |( ~wr_uerr_vec_c9 & new_uerr_vec_c9 ) ;
2055
2056
2057
2058
2059/////////////////////////////////////////////////////
2060// VEU bit
2061/////////////////////////////////////////////////////
2062assign err_status_in[`ERR_VEU] = |(new_uerr_vec_c9) ;
2063
2064
2065
2066/////////////////////////////////////////////////////
2067// ERROR LOGGING LOGIC.
2068// CORR ERRORS.
2069// correctible errors are logged if
2070// * there is no uncorr err in the same cycle.
2071// * there is no pending corr or uncorr err.
2072/////////////////////////////////////////////////////
2073
2074/////////////////////////////////////////////////////
2075// LVC bit
2076/////////////////////////////////////////////////////
2077
2078assign err_state_new_c8[`ERR_LVC] = misbuf_vuad_ce_err_c8 ; // VUAD SBE
2079
2080l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_lvc
2081 (.din(err_state_new_c8[`ERR_LVC]), .l1clk(l1clk),
2082 .scan_in(ff_err_state_new_c9_lvc_scanin),
2083 .scan_out(ff_err_state_new_c9_lvc_scanout),
2084 .dout(err_state_new_c9[`ERR_LVC]),
2085 .siclk(siclk),
2086 .soclk(soclk)
2087);
2088
2089assign err_status_in[`ERR_LVC] = ~( err_status_in[`ERR_VEU] |
2090 csr_error_status_veu |
2091 csr_error_status_vec ) &
2092 err_state_new_c9[`ERR_LVC] ;
2093
2094
2095/////////////////////////////////////////////////////
2096// LTC bit
2097/////////////////////////////////////////////////////
2098
2099assign err_state_new_c8[`ERR_LTC] = tagdp_tag_error_c8 ;
2100
2101l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ltc
2102 (.din(err_state_new_c8[`ERR_LTC]), .l1clk(l1clk),
2103 .scan_in(ff_err_state_new_c9_ltc_scanin),
2104 .scan_out(ff_err_state_new_c9_ltc_scanout),
2105 .dout(err_state_new_c9[`ERR_LTC]),
2106 .siclk(siclk),
2107 .soclk(soclk)
2108
2109);
2110
2111assign err_status_in[`ERR_LTC] = ~( err_status_in[`ERR_VEU] |
2112 csr_error_status_veu |
2113 csr_error_status_vec |
2114 err_state_new_c9[`ERR_LVC]) &
2115 err_state_new_c9[`ERR_LTC] ;
2116
2117/////////////////////////////////////////////////////
2118// LDSC bit
2119// addr=C9 and syndrome = data synd.
2120/////////////////////////////////////////////////////
2121
2122assign err_state_new_c8[`ERR_LDSC] = deccck_scrd_corr_err_c8 ;
2123
2124l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldsc
2125 (.din(err_state_new_c8[`ERR_LDSC]), .l1clk(l1clk),
2126 .scan_in(ff_err_state_new_c9_ldsc_scanin),
2127 .scan_out(ff_err_state_new_c9_ldsc_scanout),
2128 .dout(err_state_new_c9[`ERR_LDSC]),
2129 .siclk(siclk),
2130 .soclk(soclk)
2131
2132);
2133
2134assign err_status_in[`ERR_LDSC] = ~( err_status_in[`ERR_VEU] |
2135 csr_error_status_veu |
2136 csr_error_status_vec |
2137 err_state_new_c9[`ERR_LVC] |
2138 err_state_new_c9[`ERR_LTC] ) &
2139 err_state_new_c9[`ERR_LDSC] ; // LDAC and LDSC are mutex
2140
2141/////////////////////////////////////////////////////
2142// LDAC bit
2143/////////////////////////////////////////////////////
2144assign err_state_new_c8[`ERR_LDAC] = deccck_spcd_corr_err_c8 ;
2145
2146// int 5.0 changes
2147l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldac
2148 (.din(err_state_new_c8[`ERR_LDAC]), .l1clk(l1clk),
2149 .scan_in(ff_err_state_new_c9_ldac_scanin),
2150 .scan_out(ff_err_state_new_c9_ldac_scanout),
2151 .dout(err_state_new_c9[`ERR_LDAC]),
2152 .siclk(siclk),
2153 .soclk(soclk)
2154
2155);
2156
2157
2158// int 5.0 changes
2159assign err_status_in[`ERR_LDAC] = ~( err_status_in[`ERR_VEU] |
2160 csr_error_status_veu |
2161 csr_error_status_vec |
2162 err_state_new_c9[`ERR_LVC] |
2163 err_state_new_c9[`ERR_LTC] ) &
2164 err_state_new_c9[`ERR_LDAC] ;
2165
2166
2167/////////////////////////////////////////////////////
2168// LDWC bit
2169// comes from a Wback
2170// addr = evicted address and syndrome = datasyndrome.
2171/////////////////////////////////////////////////////
2172
2173assign err_state_new_c8[`ERR_LDWC] = rdmat_ev_cerr_r6 & ~csr_l2_bypass_mode_on;
2174
2175l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldwc
2176 (.din(err_state_new_c8[`ERR_LDWC]), .l1clk(l1clk),
2177 .scan_in(ff_err_state_new_c9_ldwc_scanin),
2178 .scan_out(ff_err_state_new_c9_ldwc_scanout),
2179 .dout(err_state_new_c9[`ERR_LDWC]),
2180 .siclk(siclk),
2181 .soclk(soclk)
2182
2183);
2184
2185assign err_status_in[`ERR_LDWC] = ~( err_status_in[`ERR_VEU] |
2186 csr_error_status_veu |
2187 csr_error_status_vec |
2188 err_state_new_c9[`ERR_LVC] |
2189 err_state_new_c9[`ERR_LTC] |
2190 err_state_new_c9[`ERR_LDSC] |
2191 err_state_new_c9[`ERR_LDAC] ) &
2192 err_state_new_c9[`ERR_LDWC] ; // LDAC and LDSC are mutex
2193
2194
2195/////////////////////////////////////////////////////
2196// LDRC bit
2197// comes from an RDMA Read access and
2198// only for a $ hit
2199/////////////////////////////////////////////////////
2200
2201assign err_state_new_c8[`ERR_LDRC] = deccck_bscd_corr_err_c8 |
2202 ( rdmat_rdmard_cerr_c12 &
2203 ~filbuf_ld64_fb_hit_c12 ) ;
2204
2205
2206l2t_csreg_ctl_msff_ctl_macro__width_1 ff_arb_fill_vld_c3
2207 (
2208 .scan_in(ff_arb_fill_vld_c3_scanin),
2209 .scan_out(ff_arb_fill_vld_c3_scanout),
2210 .din(arb_fill_vld_c2),
2211 .l1clk(l1clk),
2212 .dout(arb_fill_vld_c3),
2213 .siclk(siclk),
2214 .soclk(soclk)
2215 );
2216
2217
2218assign ldrc_reporting_data_in = (err_state_new_c8[`ERR_LDRC]) ? 1'b1 : report_ldrc_inpkt;
2219
2220
2221assign rst_report_ldrc_inpkt_c3 = report_ldrc_inpkt & arb_fill_vld_c3 & ~err_state_new_c8[`ERR_LDRC];
2222
2223l2t_csreg_ctl_msff_ctl_macro__clr_1__width_1 ff_ldrc_reporting
2224 (
2225 .scan_in(ff_ldrc_reporting_scanin),
2226 .scan_out(ff_ldrc_reporting_scanout),
2227 .dout (report_ldrc_inpkt),
2228 .din (ldrc_reporting_data_in),
2229 .l1clk (l1clk),
2230 .clr (rst_report_ldrc_inpkt_c3),
2231 .siclk(siclk),
2232 .soclk(soclk)
2233 );
2234
2235assign csreg_report_ldrc_inpkt_data_in = report_ldrc_inpkt & arb_fill_vld_c3;
2236
2237
2238l2t_csreg_ctl_msff_ctl_macro__width_5 ff_csreg_report_ldrc_inpkt_staging
2239 (
2240 .scan_in(ff_csreg_report_ldrc_inpkt_staging_scanin),
2241 .scan_out(ff_csreg_report_ldrc_inpkt_staging_scanout),
2242 .din({csreg_report_ldrc_inpkt_data_in,csreg_report_ldrc_inpkt_c4,csreg_report_ldrc_inpkt_c5,
2243 csreg_report_ldrc_inpkt_c52,csreg_report_ldrc_inpkt_c6}),
2244 .l1clk(l1clk),
2245 .dout({csreg_report_ldrc_inpkt_c4,csreg_report_ldrc_inpkt_c5,
2246 csreg_report_ldrc_inpkt_c52,csreg_report_ldrc_inpkt_c6,
2247 csreg_report_ldrc_inpkt_c7}),
2248 .siclk(siclk),
2249 .soclk(soclk));
2250
2251assign csreg_report_ldrc_inpkt = csreg_report_ldrc_inpkt_c7;
2252
2253
2254
2255l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ldrc
2256 (.din(err_state_new_c8[`ERR_LDRC]), .l1clk(l1clk),
2257 .scan_in(ff_err_state_new_c9_ldrc_scanin),
2258 .scan_out(ff_err_state_new_c9_ldrc_scanout),
2259 .dout(err_state_new_c9[`ERR_LDRC]),
2260 .siclk(siclk),
2261 .soclk(soclk)
2262
2263);
2264
2265assign err_status_in[`ERR_LDRC] = ~( err_status_in[`ERR_VEU] |
2266 csr_error_status_veu |
2267 csr_error_status_vec |
2268 err_state_new_c9[`ERR_LVC] |
2269 err_state_new_c9[`ERR_LTC] |
2270 err_state_new_c9[`ERR_LDSC] |
2271 err_state_new_c9[`ERR_LDWC] |
2272 err_state_new_c9[`ERR_LDAC] ) &
2273 err_state_new_c9[`ERR_LDRC] ;
2274
2275/////////////////////////////////////////////////////
2276// DRC bit
2277// ld 64 will cause DRC to be set.
2278/////////////////////////////////////////////////////
2279// int 5.0 changes
2280assign err_state_new_c8[`ERR_DRC] = filbuf_bsc_corr_err_c12 ;
2281
2282// int 5.0 changes
2283l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_drc
2284 (.din(err_state_new_c8[`ERR_DRC]), .l1clk(l1clk),
2285 .scan_in(ff_err_state_new_c9_drc_scanin),
2286 .scan_out(ff_err_state_new_c9_drc_scanout),
2287 .dout(err_state_new_c9[`ERR_DRC]),
2288 .siclk(siclk),
2289 .soclk(soclk)
2290
2291);
2292
2293// int 5.0 changes
2294assign err_status_in[`ERR_DRC] = ~( err_status_in[`ERR_VEU] |
2295 csr_error_status_veu |
2296 csr_error_status_vec |
2297 err_state_new_c9[`ERR_LVC] |
2298 err_state_new_c9[`ERR_LTC] |
2299 err_state_new_c9[`ERR_LDSC] |
2300 err_state_new_c9[`ERR_LDAC] |
2301 err_state_new_c9[`ERR_LDWC] |
2302 err_state_new_c9[`ERR_LDRC]
2303 ) &
2304 err_state_new_c9[`ERR_DRC];
2305
2306
2307/////////////////////////////////////////////////////
2308// DAC bit
2309// Only an fb hit or a fill
2310/////////////////////////////////////////////////////
2311assign err_state_new_c8[`ERR_DAC] = ( deccck_spcfb_corr_err_c8 |
2312 filbuf_corr_err_c8 ) ;
2313
2314l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_dac
2315 (.din(err_state_new_c8[`ERR_DAC]), .l1clk(l1clk),
2316 .scan_in(ff_err_state_new_c9_dac_scanin),
2317 .scan_out(ff_err_state_new_c9_dac_scanout),
2318 .dout(err_state_new_c9[`ERR_DAC]),
2319 .siclk(siclk),
2320 .soclk(soclk)
2321
2322);
2323
2324assign err_status_in[`ERR_DAC] = ~( err_status_in[`ERR_VEU] |
2325 csr_error_status_veu |
2326 csr_error_status_vec |
2327 err_state_new_c9[`ERR_LVC] |
2328 err_state_new_c9[`ERR_LTC] |
2329 err_state_new_c9[`ERR_LDSC] |
2330 err_state_new_c9[`ERR_LDAC] |
2331 err_state_new_c9[`ERR_LDWC] |
2332 err_state_new_c9[`ERR_LDRC] |
2333 err_state_new_c9[`ERR_DRC]
2334 ) &
2335 err_state_new_c9[`ERR_DAC];
2336
2337
2338/////////////////////////////////////////////////////
2339// DSC bit
2340/////////////////////////////////////////////////////
2341assign err_state_new_c8[`ERR_DSC] = filbuf_mcu_scb_secc_err_d1 ;
2342
2343l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_dsc
2344 (.din(err_state_new_c8[`ERR_DSC]), .l1clk(l1clk),
2345 .scan_in(ff_err_state_new_c9_dsc_scanin),
2346 .scan_out(ff_err_state_new_c9_dsc_scanout),
2347 .dout(err_state_new_c9[`ERR_DSC]),
2348 .siclk(siclk),
2349 .soclk(soclk)
2350
2351);
2352
2353assign err_status_in[`ERR_DSC] = err_state_new_c9[`ERR_DSC] ;
2354
2355/////////////////////////////////////////////////////
2356// MEC bit
2357// set if the corr err detected is unable to record in the L2 esr
2358// OR if an uncorrectable err happens when a corr err has already occurred.
2359/////////////////////////////////////////////////////
2360
2361assign wr_cerr_vec_c9 = { err_status_in[`ERR_LVC],
2362 err_status_in[`ERR_LTC],
2363 err_status_in[`ERR_LDAC],
2364 err_status_in[`ERR_LDRC],
2365 err_status_in[`ERR_LDWC],
2366 err_status_in[`ERR_LDSC],
2367 err_status_in[`ERR_DAC],
2368 err_status_in[`ERR_DRC] } ;
2369
2370assign new_cerr_vec_c9 = { err_state_new_c9[`ERR_LVC],
2371 err_state_new_c9[`ERR_LTC],
2372 err_state_new_c9[`ERR_LDAC],
2373 err_state_new_c9[`ERR_LDRC],
2374 err_state_new_c9[`ERR_LDWC],
2375 err_state_new_c9[`ERR_LDSC],
2376 err_state_new_c9[`ERR_DAC],
2377 err_state_new_c9[`ERR_DRC] } ;
2378
2379assign err_status_in[`ERR_MEC] = (|( ~wr_cerr_vec_c9 & new_cerr_vec_c9 )) |
2380 ( err_status_in[`ERR_VEU] & csr_error_status_vec ) ;
2381
2382/////////////////////////////////////////////////////
2383// VEC bit
2384/////////////////////////////////////////////////////
2385assign err_status_in[`ERR_VEC] = |( new_cerr_vec_c9 ) ;
2386
2387
2388
2389/////////////////////////////////////////////////////
2390// RW bit
2391// 1 for a write access
2392// Set to 1 for Stores, strm stores, CAs, SWAP, LDSTUB
2393// or rdma psts that encounter an error.
2394/////////////////////////////////////////////////////
2395
2396// int 5.0 changes
2397assign rdma_pst_err_c9 = deccck_bscd_uncorr_err_c9 |
2398 deccck_bscd_corr_err_c9 ;
2399
2400// int 5.0 changes
2401l2t_csreg_ctl_msff_ctl_macro__width_1 ff_store_error_c9
2402 (.din(arb_store_err_c8), .l1clk(l1clk),
2403 .scan_in(ff_store_error_c9_scanin),
2404 .scan_out(ff_store_error_c9_scanout),
2405 .dout(store_error_c9),
2406 .siclk(siclk),
2407 .soclk(soclk)
2408
2409);
2410
2411// int 5.0 changes
2412assign error_spc = ( err_status_in[`ERR_LDAU] | err_status_in[`ERR_LDAC] |
2413 err_status_in[`ERR_DAU] | err_status_in[`ERR_DAC]) ;
2414
2415// int 5.0 changes
2416assign error_bsc = ( err_status_in[`ERR_LDRU] | err_status_in[`ERR_LDRC] |
2417 err_status_in[`ERR_DRU] | err_status_in[`ERR_DRC] );
2418
2419
2420// int 5.0 changes
2421assign err_status_in[`ERR_RW] = ( store_error_c9 & error_spc) |
2422 ( rdma_pst_err_c9 & error_bsc &
2423 ~( rdmard_uerr_c13 | rdmard_cerr_c13 ) ) ;
2424
2425// int 5.0 changes
2426assign error_rw_en = ( error_spc | error_bsc ) |
2427 ( diag_wr_en ) ;
2428
2429
2430/////////////////////////////////////////////////////
2431// ERROR STATUS BITS to CSR from csreg.
2432/////////////////////////////////////////////////////
2433assign csreg_err_state_in_mec = err_status_in[`ERR_MEC];
2434assign csreg_err_state_in_meu = err_status_in[`ERR_MEU];
2435assign csreg_err_state_in_rw = err_status_in[`ERR_RW];
2436assign csreg_err_state_in[`ERR_LDAC:`ERR_LVC] = err_status_in[`ERR_LDAC:`ERR_LVC] ;
2437
2438
2439/////////////////////////////////////////////////////
2440// SYNDROME
2441// recorded for
2442// * vuad errors
2443// * ldac/ldau
2444// * ldrc/ldru for rdma writes only.
2445/////////////////////////////////////////////////////
2446
2447assign rdmat_rdmard_uerr_c12_reg_in = (rdmat_rdmard_uerr_c12 | (rdmat_rdmard_notdata_c12 & filbuf_ld64_fb_hit_c12));
2448
2449l2t_csreg_ctl_msff_ctl_macro__width_1 ff_rdmard_uerr_c13
2450// (.din(rdmat_rdmard_uerr_c12), .l1clk(l1clk),
2451 (.din(rdmat_rdmard_uerr_c12_reg_in), .l1clk(l1clk),
2452 .scan_in(ff_rdmard_uerr_c13_scanin),
2453 .scan_out(ff_rdmard_uerr_c13_scanout),
2454 .dout(rdmard_uerr_c13),
2455 .siclk(siclk),
2456 .soclk(soclk)
2457
2458);
2459
2460l2t_csreg_ctl_msff_ctl_macro__width_1 ff_rdmard_cerr_c13
2461 (.din(rdmat_rdmard_cerr_c12), .l1clk(l1clk),
2462 .scan_in(ff_rdmard_cerr_c13_scanin),
2463 .scan_out(ff_rdmard_cerr_c13_scanout),
2464 .dout(rdmard_cerr_c13),
2465 .siclk(siclk),
2466 .soclk(soclk)
2467
2468);
2469
2470
2471assign csreg_mux1_synd_sel[0] = err_status_in[`ERR_LVU] | err_status_in[`ERR_LVC];
2472assign csreg_mux1_synd_sel[1] = ~csreg_mux1_synd_sel[0]; // fix for bug 117562
2473assign csreg_mux2_synd_sel[0] = ((err_state_new_c9[`ERR_LDAU] |
2474 err_state_new_c9[`ERR_LDAC]) |
2475 (( err_state_new_c9[`ERR_LDRU] |
2476 err_state_new_c9[`ERR_LDRC] ) &
2477 ~( rdmard_uerr_c13 | rdmard_cerr_c13 ))
2478 ) ;
2479
2480assign csreg_mux2_synd_sel[1] = ~csreg_mux2_synd_sel[0] ;
2481
2482
2483assign csreg_csr_synd_wr_en = diag_wr_en |
2484 ( new_err_sel & ( csreg_mux1_synd_sel[0] | csreg_mux2_synd_sel[0] )) ;
2485
2486
2487/////////////////////////////////////////////////////
2488// TID
2489// reported for
2490// * ldac/ldau errors
2491// * dac/dau errors when they are
2492// detected/reported by an instruction other than a FILL
2493/////////////////////////////////////////////////////
2494
2495
2496assign csreg_wr_enable_tid_c9 = ( err_status_in[`ERR_LDAC] |
2497 err_status_in[`ERR_LDAU] |
2498 err_status_in[`ERR_DAC] |
2499 err_status_in[`ERR_DAU] ) ;
2500
2501assign csreg_csr_tid_wr_en = ( csreg_wr_enable_tid_c9 | diag_wr_en ) ;
2502
2503
2504/////////////////////////////////////////////////////
2505// ASYNC
2506// reported for only ldac/ldau errors.
2507/////////////////////////////////////////////////////
2508
2509l2t_csreg_ctl_msff_ctl_macro__width_1 ff_str_ld_hit_c8
2510 (.din(oqu_str_ld_hit_c7), .l1clk(l1clk),
2511 .scan_in(ff_str_ld_hit_c8_scanin),
2512 .scan_out(ff_str_ld_hit_c8_scanout),
2513 .dout(str_ld_hit_c8),
2514 .siclk(siclk),
2515 .soclk(soclk)
2516
2517);
2518
2519l2t_csreg_ctl_msff_ctl_macro__width_1 ff_str_ld_hit_c9
2520 (.din(str_ld_hit_c8), .l1clk(l1clk),
2521 .scan_in(ff_str_ld_hit_c9_scanin),
2522 .scan_out(ff_str_ld_hit_c9_scanout),
2523 .dout(str_ld_hit_c9),
2524 .siclk(siclk),
2525 .soclk(soclk)
2526
2527);
2528// int 5.0 changes
2529assign csreg_wr_enable_async_c9 = (err_status_in[`ERR_LDAC] |
2530 err_status_in[`ERR_DAC] |
2531 err_status_in[`ERR_DAU] |
2532 err_status_in[`ERR_LDAU] ) ;
2533
2534
2535// int 5.0 changes
2536assign set_async_c9 = str_ld_hit_c9 ;
2537
2538// int 5.0 changes
2539assign csreg_csr_async_wr_en = ( csreg_wr_enable_async_c9 |
2540 diag_wr_en ) ;
2541
2542
2543/////////////////////////////////////////////////////
2544// ADDRESS PRIORITIES
2545/////////////////////////////////////////////////////
2546// int 5.0 changes
2547//
2548// 1. LVU pipe-addr
2549// 2. LRU dir_addr
2550// 3a. LDSU scrub addr
2551// 3b. LDAU pipe_addr.
2552// 4. LDWU evict_addr
2553// 5a. LDRU rdma rd addr.
2554// 5b. LDRU pipe_addr.
2555// 6a. DRU rdma rd addr.
2556// 6b. DRU pipe addr
2557// 6c. DAU pipe_addr
2558// 7. LVC pipe addr
2559// 8. LTC pipe_addr
2560// 9a. LDSC scrub addr.
2561// 9b. LDAC pipe_addr
2562// 10. LDWC evict_addr
2563// 11a. LDRC rdma rd addr.
2564// 11b. LDRC pipe_addr.
2565// 12a DRC rdma rd addr.
2566// 12b DRC pipe addr
2567// 12c DAC pipe_addr.
2568/////////////////////////////////////////////////////
2569// int 5.0 changes
2570l2t_csreg_ctl_msff_ctl_macro__width_1 ff_deccck_bscd_uncorr_err_c9
2571 (.din(deccck_bscd_uncorr_err_c8), .l1clk(l1clk),
2572 .scan_in(ff_deccck_bscd_uncorr_err_c9_scanin),
2573 .scan_out(ff_deccck_bscd_uncorr_err_c9_scanout),
2574 .dout(deccck_bscd_uncorr_err_c9),
2575 .siclk(siclk),
2576 .soclk(soclk)
2577
2578);
2579// int 5.0 changes
2580l2t_csreg_ctl_msff_ctl_macro__width_1 ff_deccck_bscd_corr_err_c9
2581 (.din(deccck_bscd_corr_err_c8), .l1clk(l1clk),
2582 .scan_in(ff_deccck_bscd_corr_err_c9_scanin),
2583 .scan_out(ff_deccck_bscd_corr_err_c9_scanout),
2584 .dout(deccck_bscd_corr_err_c9),
2585 .siclk(siclk),
2586 .soclk(soclk)
2587
2588);
2589
2590l2t_csreg_ctl_msff_ctl_macro__width_1 ff_deccck_bscd_notdata_err_c9
2591 (.din(deccck_bscd_notdata_err_c8), .l1clk(l1clk),
2592 .scan_in(ff_deccck_bscd_notdata_err_c9_scanin),
2593 .scan_out(ff_deccck_bscd_notdata_err_c9_scanout),
2594 .dout(deccck_bscd_notdata_err_c9),
2595 .siclk(siclk),
2596 .soclk(soclk)
2597
2598);
2599
2600
2601l2t_csreg_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c13
2602 (.din(filbuf_bsc_corr_err_c12), .l1clk(l1clk),
2603 .scan_in(ff_bsc_corr_err_c13_scanin),
2604 .scan_out(ff_bsc_corr_err_c13_scanout),
2605 .dout(bsc_corr_err_c13),
2606 .siclk(siclk),
2607 .soclk(soclk)
2608
2609);
2610
2611// int 5.0 changes
2612assign mux1_addr_sel_tmp[0] = err_state_new_c9[`ERR_LRU] ; // sel dir addr.
2613
2614// int 5.0 changes
2615assign mux1_addr_sel_tmp[1] =
2616 (( err_state_new_c9[`ERR_LDSU] & ~err_state_new_c9[`ERR_LRU] ) |
2617 ( err_state_new_c9[`ERR_LDSC] & ~err_status_in[`ERR_VEU]) ) ; // scrub addr.
2618
2619// int 5.0 changes
2620assign mux1_addr_sel_tmp[2] = (( err_state_new_c9[`ERR_LDWU] & ~err_state_new_c9[`ERR_LDSU]
2621 & ~err_state_new_c9[`ERR_LRU] ) |
2622 ( err_state_new_c9[`ERR_LDWC] &
2623 ~err_status_in[`ERR_VEU] &
2624 ~err_state_new_c9[`ERR_LDSC]) ) ; // evict addr.
2625
2626assign mux1_addr_sel_tmp[3] = ~|(mux1_addr_sel_tmp[2:0]);
2627
2628
2629assign csreg_mux1_addr_sel[0] = mux1_addr_sel_tmp[0] ;
2630assign csreg_mux1_addr_sel[1] = mux1_addr_sel_tmp[1] ;
2631assign csreg_mux1_addr_sel[2] = mux1_addr_sel_tmp[2] ;
2632assign csreg_mux1_addr_sel[3] = ( mux1_addr_sel_tmp[3]) ;
2633
2634
2635assign err_sel = ( err_status_in[`ERR_VEC] |
2636 err_status_in[`ERR_VEU] ) ;
2637
2638// int 5.0 changes
2639assign diag_wr_en = csreg_csr_errstate_wr_en_c8 & ~err_sel ;
2640
2641// int 5.0 changes
2642assign rdmard_addr_sel_c13 = ( (err_state_new_c9[`ERR_LDRU] | err_state_new_c9[`ERR_DRU] ) |
2643 (( err_state_new_c9[`ERR_LDRC] | err_state_new_c9[`ERR_DRC])
2644 & ~err_status_in[`ERR_VEU])) &
2645 (rdmard_uerr_c13 | rdmard_cerr_c13 | bsc_corr_err_c13 ); // rdma rd addr only
2646
2647
2648// int 5.0 changes
2649// Fix for bug#4375
2650// when an error is detected in a rdma rd and a wr8 in the same cycle,
2651// the wr8 address is discarded and the rdma rd address is selected.
2652// the pipe_addr_sel expression needed appropriate qualifications with
2653// rdmard_uerr_c13 & ( rdmard_cerr_c13 | bsc_corr_err_c13 )
2654
2655
2656// int 5.0 changes
2657assign pipe_addr_sel = ( err_state_new_c9[`ERR_LVU] |
2658 (~err_state_new_c9[`ERR_LRU] & err_state_new_c9[`ERR_LDAU] ) |
2659 (~err_state_new_c9[`ERR_LRU] & ~err_state_new_c9[`ERR_LDWU] & deccck_bscd_uncorr_err_c9 & ~rdmard_uerr_c13)) |
2660 (~err_status_in[`ERR_VEU] &
2661 (err_state_new_c9[`ERR_LTC] |
2662 err_state_new_c9[`ERR_LVC] |
2663 err_state_new_c9[`ERR_LDAC] |
2664 ( deccck_bscd_corr_err_c9 & ~err_state_new_c9[`ERR_LDWC] & ~rdmard_cerr_c13 & ~bsc_corr_err_c13 ))
2665 ); // pipe addr only
2666
2667
2668
2669
2670
2671// int 5.0 changes
2672assign mux2_addr_sel_tmp[0] = ( rdmard_addr_sel_c13 |
2673 (|(mux1_addr_sel_tmp[2:0])) ) &
2674 ~pipe_addr_sel ; // sel mux1
2675 // if err
2676 // or rdma rd
2677
2678assign mux2_addr_sel_tmp[1] = err_sel & ~mux2_addr_sel_tmp[0] ; // sel pipe addr
2679 // a9
2680
2681assign mux2_addr_sel_tmp[2] = ~(mux2_addr_sel_tmp[1] | mux2_addr_sel_tmp[0] ) ;
2682 // sel wr data.
2683
2684assign csreg_mux2_addr_sel[0] = mux2_addr_sel_tmp[0] ;
2685assign csreg_mux2_addr_sel[1] = mux2_addr_sel_tmp[1] ;
2686assign csreg_mux2_addr_sel[2] = ( mux2_addr_sel_tmp[2] ) ;
2687
2688assign new_err_sel = |(wr_uerr_vec_c9) | (|(wr_cerr_vec_c9) ) ;
2689
2690// int 5.0 changes
2691// An error gets priority to write into the EAR if an error
2692// and a diagnostic write try to update the EAR in the same cycle.
2693// Bug #3986.
2694// err_addr_sel indicates that an error occurred. In this case,
2695// any diagnostic write is disabled.
2696
2697// int 5.0 changes
2698assign csreg_csr_addr_wr_en = ( csreg_csr_erraddr_wr_en_c8 & ~err_sel ) | new_err_sel ;
2699
2700
2701
2702/////////////////////////////////////////////////////
2703// POR signalled for LVU/LRU
2704// PMB requires reset assertion for 6 cycles.
2705// The following signal is not a C8 signal but
2706// that is the name it has been given.
2707// int 5.0 changes
2708// This request is conditioned in JBI with an enable bit
2709// before actually causing a POR.
2710/////////////////////////////////////////////////////
2711
2712assign en_por_c7 = ( err_state_new_c9[`ERR_LVU] | err_state_new_c9[`ERR_LRU] ) ;
2713
2714l2t_csreg_ctl_msff_ctl_macro__width_1 ff_en_por_c7_d1
2715 (.din(en_por_c7), .l1clk(l1clk),
2716 .scan_in(ff_en_por_c7_d1_scanin),
2717 .scan_out(ff_en_por_c7_d1_scanout),
2718 .dout(en_por_c7_d1),
2719 .siclk(siclk),
2720 .soclk(soclk)
2721
2722);
2723
2724l2t_csreg_ctl_msff_ctl_macro__width_1 ff_en_por_c7_d2
2725 (.din(en_por_c7_d1), .l1clk(l1clk),
2726 .scan_in(ff_en_por_c7_d2_scanin),
2727 .scan_out(ff_en_por_c7_d2_scanout),
2728 .dout(en_por_c7_d2),
2729 .siclk(siclk),
2730 .soclk(soclk)
2731
2732);
2733
2734l2t_csreg_ctl_msff_ctl_macro__width_1 ff_en_por_c7_d3
2735 (.din(en_por_c7_d2), .l1clk(l1clk),
2736 .scan_in(ff_en_por_c7_d3_scanin),
2737 .scan_out(ff_en_por_c7_d3_scanout),
2738 .dout(en_por_c7_d3),
2739 .siclk(siclk),
2740 .soclk(soclk)
2741
2742);
2743
2744l2t_csreg_ctl_msff_ctl_macro__width_1 ff_en_por_c7_d4
2745 (.din(en_por_c7_d3), .l1clk(l1clk),
2746 .scan_in(ff_en_por_c7_d4_scanin),
2747 .scan_out(ff_en_por_c7_d4_scanout),
2748 .dout(en_por_c7_d4),
2749 .siclk(siclk),
2750 .soclk(soclk)
2751
2752);
2753
2754assign en_por_streatched = en_por_c7_d1 | en_por_c7_d2 | en_por_c7_d3 | en_por_c7_d4 ;
2755
2756
2757// For timing reason flipped to iol2clk domain
2758// assign l2t_rst_fatal_error = en_por_c7_d1 ;
2759///
2760
2761l2t_csreg_ctl_msff_ctl_macro__en_1__width_1 ff_l2t_rst_fatal_error
2762 (
2763 .scan_in(ff_l2t_rst_fatal_error_scanin),
2764 .scan_out(ff_l2t_rst_fatal_error_scanout),
2765 .dout (l2t_rst_fatal_error),
2766 .din (en_por_streatched),
2767 .l1clk (l1clk),
2768 .en (cmp_io_sync_en_r1),
2769 .siclk(siclk),
2770 .soclk(soclk)
2771 );
2772
2773
2774l2t_csreg_ctl_msff_ctl_macro__width_1 ff_cmp_io_sync_en
2775 (
2776 .scan_in(ff_cmp_io_sync_en_scanin),
2777 .scan_out(ff_cmp_io_sync_en_scanout),
2778 .dout (cmp_io_sync_en_r1),
2779 .din (cmp_io_sync_en),
2780 .l1clk (l1clk),
2781 .siclk(siclk),
2782 .soclk(soclk)
2783 );
2784
2785
2786
2787
2788
2789// BS 06/13/04 added Notdata error logic
2790///////////////////////////////////////////////////
2791
2792/////////////////////////////////////////////////////
2793// NDDM bit
2794// Set for an RDMA Read or an RDMA Write ( Partial )
2795// Only set for accesses that hit the $ and finds Notdata
2796/////////////////////////////////////////////////////
2797
2798
2799assign err_state_notdata_new_c8[`ERR_NDDM] = deccck_bscd_notdata_err_c8 |
2800 ( rdmat_rdmard_notdata_c12 &
2801 ~filbuf_ld64_fb_hit_c12 ) ;
2802
2803l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_nddm
2804 (.din(err_state_notdata_new_c8[`ERR_NDDM]), .l1clk(l1clk),
2805 .scan_in(ff_err_state_new_c9_nddm_scanin),
2806 .scan_out(ff_err_state_new_c9_nddm_scanout),
2807 .dout(err_state_notdata_new_c9[`ERR_NDDM]),
2808 .siclk(siclk),
2809 .soclk(soclk)
2810
2811);
2812
2813assign err_status_notdata_in[`ERR_NDDM] = (~( err_state_notdata_new_c9[`ERR_NDSP]) &
2814 err_state_notdata_new_c9[`ERR_NDDM]) &
2815 ~csr_error_status_notdata;
2816 // will log the error only if a notdata error is not logged already
2817
2818/////////////////////////////////////////////////////
2819// NDSP bit
2820// set for any kind of access LD/ST/ATOMIC/PST that hits the cache
2821// and finds Notdata
2822// Address=C9. Syndrome = all 1's and hence not stored
2823/////////////////////////////////////////////////////
2824
2825assign err_state_notdata_new_c8[`ERR_NDSP] = deccck_spcd_notdata_err_c8 ;
2826 // Notdata err on a sparc read hit
2827
2828l2t_csreg_ctl_msff_ctl_macro__width_1 ff_err_state_new_c9_ndsp
2829 (.din(err_state_notdata_new_c8[`ERR_NDSP]), .l1clk(l1clk),
2830 .scan_in(ff_err_state_new_c9_ndsp_scanin),
2831 .scan_out(ff_err_state_new_c9_ndsp_scanout),
2832 .dout(err_state_notdata_new_c9[`ERR_NDSP]),
2833 .siclk(siclk),
2834 .soclk(soclk)
2835
2836);
2837
2838assign err_status_notdata_in[`ERR_NDSP] = err_state_notdata_new_c9[`ERR_NDSP] & ~csr_error_status_notdata;
2839 // will log the error only if a notdata error is not logged already
2840
2841/////////////////////////////////////////////////////
2842// MEND bit
2843// Multiple error notdata bit is set if multiple
2844// notdata errors happen in the same cycle or
2845// are separated in time.
2846// This bit is set if the vector being written in
2847// is different from the vector that is detected
2848/////////////////////////////////////////////////////
2849
2850assign new_notdata_err_vec_c9 = { err_state_notdata_new_c9[`ERR_NDSP],
2851 err_state_notdata_new_c9[`ERR_NDDM] } ;
2852
2853assign wr_notdata_err_vec_c9 = { err_status_notdata_in[`ERR_NDSP],
2854 err_status_notdata_in[`ERR_NDDM] } ;
2855
2856assign err_status_notdata_in[`ERR_MEND] = |( ~wr_notdata_err_vec_c9 & new_notdata_err_vec_c9 ) ;
2857
2858/////////////////////////////////////////////////////
2859// NDRW bit
2860// 1 for a write access
2861// Set to 1 for Stores, strm stores, CAs, SWAP, LDSTUB
2862// or rdma psts that encounter a notdata error.
2863/////////////////////////////////////////////////////
2864
2865l2t_csreg_ctl_msff_ctl_macro__width_1 ff_rdmard_notdata_err_c13
2866 (.din(rdmat_rdmard_notdata_c12), .l1clk(l1clk),
2867 .scan_in(ff_rdmard_notdata_err_c13_scanin),
2868 .scan_out(ff_rdmard_notdata_err_c13_scanout),
2869 .dout(rdmard_notdata_err_c13),
2870 .siclk(siclk),
2871 .soclk(soclk)
2872
2873);
2874
2875
2876assign rdma_pst_notdata_err_c9 = deccck_bscd_notdata_err_c9;
2877
2878assign err_status_notdata_in[`ERR_NDRW] = ( store_error_c9 & err_status_notdata_in[`ERR_NDSP]) |
2879 ( rdma_pst_notdata_err_c9 & err_status_notdata_in[`ERR_NDDM]);
2880
2881
2882
2883assign csreg_notdata_error_rw_en = ( err_status_notdata_in[`ERR_NDSP] | err_status_notdata_in[`ERR_NDRW]
2884 | (err_status_notdata_in[`ERR_NDDM] & ~notdata_higher_priority_err ) |
2885 csreg_notdata_diag_wr_en) ;
2886
2887
2888
2889/////////////////////////////////////////////////////
2890// NOTDATA ERROR STATUS BITS to CSR from csreg.
2891/////////////////////////////////////////////////////
2892assign csreg_notdata_err_state_in_rw = err_status_notdata_in[`ERR_NDRW];
2893assign csreg_notdata_err_state_in_mend = err_status_notdata_in[`ERR_MEND];
2894assign csreg_notdata_err_state_in[`ERR_NDSP:`ERR_NDDM] = err_status_notdata_in[`ERR_NDSP:`ERR_NDDM] ;
2895
2896//////////////////////////////////////////
2897// NOTDATA ERROR REG AE,AF (AF is removed)
2898//////////////////////////////////////////
2899//assign notdata_reg_write_en = arb_csr_wr_en_c7 &
2900// ((word_addr_c7==3'h6) | (word_addr_c7==3'h7)) ; // AE or AF
2901// not data register accessed with ae or be
2902assign notdata_reg_write_en = arb_csr_wr_en_c7 &
2903 ((word_addr_c7[4:0]==5'h0E) | (word_addr_c7[4:0]==5'h1E)); // AE or BE
2904
2905l2t_csreg_ctl_msff_ctl_macro__width_1 ff_notdata_reg_write_en_d1
2906 (.din(notdata_reg_write_en), .l1clk(l1clk),
2907 .scan_in(ff_notdata_reg_write_en_d1_scanin),
2908 .scan_out(ff_notdata_reg_write_en_d1_scanout),
2909 .dout(notdata_reg_write_en_d1),
2910 .siclk(siclk),
2911 .soclk(soclk)
2912
2913);
2914
2915assign csreg_csr_notdata_wr_en_c8 = notdata_reg_write_en_d1;
2916
2917/////////////////////////////////////////////////////
2918// Notdata VCID write enable
2919// valid for
2920// * NDSP Errors
2921/////////////////////////////////////////////////////
2922//
2923// A Notdata error gets priority to write into the VCID if an error
2924// and a diagnostic write try to update the VCID in the same cycle.
2925// In case an error occurrs in the same cycle as the diagnostic write,
2926// the diagnostic write is disabled.
2927
2928assign csreg_wr_enable_notdata_vcid_c9 = (err_status_notdata_in[`ERR_NDSP]);
2929
2930assign csreg_wr_enable_notdata_nddm_vcid_c9 = ( err_status_notdata_in[`ERR_NDDM]);
2931
2932assign csreg_notdata_diag_wr_en = (csreg_csr_notdata_wr_en_c8 &
2933 ~(|(err_status_notdata_in[`ERR_NDSP:`ERR_NDDM])));
2934
2935assign csreg_csr_notdata_vcid_wr_en = ( csreg_wr_enable_notdata_vcid_c9 |
2936 csreg_wr_enable_notdata_nddm_vcid_c9 | csreg_notdata_diag_wr_en);
2937
2938/////////////////////////////////////////////////////
2939// Notdata address write enable
2940// valid for
2941// * NDSP and NDDM Errors
2942/////////////////////////////////////////////////////
2943// A Notdata error gets priority to write into the EAR if an error
2944// and a diagnostic write try to update the EAR in the same cycle.
2945// In case an error occurrs in the same cycle as the diagnostic write,
2946// the diagnostic write is disabled.
2947
2948assign csreg_csr_notdata_addr_wr_en = (|(err_status_notdata_in[`ERR_NDSP:`ERR_NDDM])) |
2949 csreg_csr_notdata_wr_en_c8;
2950
2951
2952
2953assign csreg_notdata_addr_mux_sel[2:0] =
2954 { (~err_status_notdata_in[`ERR_NDSP] & ~err_status_notdata_in[`ERR_NDDM]), // wr address from diagnostic
2955(~err_status_notdata_in[`ERR_NDSP] & err_status_notdata_in[`ERR_NDDM] &
2956 ~rdma_pst_notdata_err_c9 & rdmard_notdata_err_c13), // rdma rd address
2957(err_status_notdata_in[`ERR_NDSP] | ( rdma_pst_notdata_err_c9 & err_status_notdata_in[`ERR_NDDM])
2958 )}; // c9 address
2959
2960/////////////////////////////////////////////////////
2961// L2 Mask registers
2962//
2963/////////////////////////////////////////////////////
2964assign csreg_csr_l2_mask_reg_wr_en = arb_csr_wr_en_c7 & (word_addr_c7[4:0]==5'h0F ) ; // AF
2965
2966l2t_csreg_ctl_msff_ctl_macro__width_1 ff_l2_mask_reg_wr_en
2967 (
2968 .scan_in(ff_l2_mask_reg_wr_en_scanin),
2969 .scan_out(ff_l2_mask_reg_wr_en_scanout),
2970 .dout (csreg_csr_l2_mask_reg_wr_en_d1),
2971 .din (csreg_csr_l2_mask_reg_wr_en),
2972 .l1clk (l1clk),
2973 .siclk(siclk),
2974 .soclk(soclk)
2975 );
2976
2977assign csreg_l2_mask_reg_wr_en_c8 = csreg_csr_l2_mask_reg_wr_en_d1;
2978
2979
2980/////////////////////////////////////////////////////
2981// L2 Compare registers
2982//
2983/////////////////////////////////////////////////////
2984
2985
2986assign csreg_csr_l2_cmpr_reg_wr_en = arb_csr_wr_en_c7 & (word_addr_c7[4:0]==5'h1F ) ; // BF
2987
2988l2t_csreg_ctl_msff_ctl_macro__width_1 ff_l2_cmpr_reg_wr_en
2989 (
2990 .scan_in(ff_l2_cmpr_reg_wr_en_scanin),
2991 .scan_out(ff_l2_cmpr_reg_wr_en_scanout),
2992 .dout (csreg_csr_l2_cmpr_reg_wr_en_d1),
2993 .din (csreg_csr_l2_cmpr_reg_wr_en),
2994 .l1clk (l1clk),
2995 .siclk(siclk),
2996 .soclk(soclk)
2997 );
2998
2999assign csreg_l2_cmpr_reg_wr_en_c8 = csreg_csr_l2_cmpr_reg_wr_en_d1;
3000
3001
3002
3003
3004
3005// fixscan start:
3006assign spares_scanin = scan_in ;
3007assign ff_word_addr_c7_scanin = spares_scanout ;
3008assign ff_bist_reg_write_en_d1_scanin = ff_word_addr_c7_scanout ;
3009assign ff_control_reg_write_en_d1_scanin = ff_bist_reg_write_en_d1_scanout;
3010assign ff_erren_reg_write_en_d1_scanin = ff_control_reg_write_en_d1_scanout;
3011assign ff_errst_reg_write_en_d1_scanin = ff_erren_reg_write_en_d1_scanout;
3012assign ff_erraddr_reg_write_en_d1_scanin = ff_errst_reg_write_en_d1_scanout;
3013assign ff_errinj_reg_write_en_d1_scanin = ff_erraddr_reg_write_en_d1_scanout;
3014assign ff_mux1_sel_c7_scanin = ff_errinj_reg_write_en_d1_scanout;
3015assign ff_err_state_new_c9_lvu_scanin = ff_mux1_sel_c7_scanout ;
3016assign ff_err_state_new_c9_lru_scanin = ff_err_state_new_c9_lvu_scanout;
3017assign ff_err_state_new_c9_ldsu_scanin = ff_err_state_new_c9_lru_scanout;
3018assign ff_err_state_new_c9_ldau_scanin = ff_err_state_new_c9_ldsu_scanout;
3019assign ff_err_state_new_c9_ldwu_scanin = ff_err_state_new_c9_ldau_scanout;
3020assign ff_err_state_new_c9_ldru_scanin = ff_err_state_new_c9_ldwu_scanout;
3021assign ff_err_state_new_c9_dru_scanin = ff_err_state_new_c9_ldru_scanout;
3022assign ff_err_state_new_c9_dau_scanin = ff_err_state_new_c9_dru_scanout;
3023assign ff_err_state_new_c9_dsu_scanin = ff_err_state_new_c9_dau_scanout;
3024assign ff_err_state_new_c9_lvc_scanin = ff_err_state_new_c9_dsu_scanout;
3025assign ff_err_state_new_c9_ltc_scanin = ff_err_state_new_c9_lvc_scanout;
3026assign ff_err_state_new_c9_ldsc_scanin = ff_err_state_new_c9_ltc_scanout;
3027assign ff_err_state_new_c9_ldac_scanin = ff_err_state_new_c9_ldsc_scanout;
3028assign ff_err_state_new_c9_ldwc_scanin = ff_err_state_new_c9_ldac_scanout;
3029assign ff_arb_fill_vld_c3_scanin = ff_err_state_new_c9_ldwc_scanout;
3030assign ff_ldrc_reporting_scanin = ff_arb_fill_vld_c3_scanout;
3031assign ff_csreg_report_ldrc_inpkt_staging_scanin = ff_ldrc_reporting_scanout;
3032assign ff_err_state_new_c9_ldrc_scanin = ff_csreg_report_ldrc_inpkt_staging_scanout;
3033assign ff_err_state_new_c9_drc_scanin = ff_err_state_new_c9_ldrc_scanout;
3034assign ff_err_state_new_c9_dac_scanin = ff_err_state_new_c9_drc_scanout;
3035assign ff_err_state_new_c9_dsc_scanin = ff_err_state_new_c9_dac_scanout;
3036assign ff_store_error_c9_scanin = ff_err_state_new_c9_dsc_scanout;
3037assign ff_rdmard_uerr_c13_scanin = ff_store_error_c9_scanout;
3038assign ff_rdmard_cerr_c13_scanin = ff_rdmard_uerr_c13_scanout;
3039assign ff_str_ld_hit_c8_scanin = ff_rdmard_cerr_c13_scanout;
3040assign ff_str_ld_hit_c9_scanin = ff_str_ld_hit_c8_scanout ;
3041assign ff_deccck_bscd_uncorr_err_c9_scanin = ff_str_ld_hit_c9_scanout ;
3042assign ff_deccck_bscd_corr_err_c9_scanin = ff_deccck_bscd_uncorr_err_c9_scanout;
3043assign ff_deccck_bscd_notdata_err_c9_scanin = ff_deccck_bscd_corr_err_c9_scanout;
3044assign ff_bsc_corr_err_c13_scanin = ff_deccck_bscd_notdata_err_c9_scanout;
3045assign ff_en_por_c7_d1_scanin = ff_bsc_corr_err_c13_scanout;
3046assign ff_en_por_c7_d2_scanin = ff_en_por_c7_d1_scanout ;
3047assign ff_en_por_c7_d3_scanin = ff_en_por_c7_d2_scanout ;
3048assign ff_en_por_c7_d4_scanin = ff_en_por_c7_d3_scanout ;
3049assign ff_l2t_rst_fatal_error_scanin = ff_en_por_c7_d4_scanout ;
3050assign ff_cmp_io_sync_en_scanin = ff_l2t_rst_fatal_error_scanout;
3051assign ff_err_state_new_c9_nddm_scanin = ff_cmp_io_sync_en_scanout;
3052assign ff_err_state_new_c9_ndsp_scanin = ff_err_state_new_c9_nddm_scanout;
3053assign ff_rdmard_notdata_err_c13_scanin = ff_err_state_new_c9_ndsp_scanout;
3054assign ff_notdata_reg_write_en_d1_scanin = ff_rdmard_notdata_err_c13_scanout;
3055assign ff_l2_mask_reg_wr_en_scanin = ff_notdata_reg_write_en_d1_scanout;
3056assign ff_l2_cmpr_reg_wr_en_scanin = ff_l2_mask_reg_wr_en_scanout;
3057assign scan_out = ff_l2_cmpr_reg_wr_en_scanout;
3058// fixscan end:
3059endmodule
3060
3061
3062
3063
3064
3065
3066
3067// any PARAMS parms go into naming of macro
3068
3069module l2t_csreg_ctl_l1clkhdr_ctl_macro (
3070 l2clk,
3071 l1en,
3072 pce_ov,
3073 stop,
3074 se,
3075 l1clk);
3076
3077
3078 input l2clk;
3079 input l1en;
3080 input pce_ov;
3081 input stop;
3082 input se;
3083 output l1clk;
3084
3085
3086
3087
3088
3089cl_sc1_l1hdr_8x c_0 (
3090
3091
3092 .l2clk(l2clk),
3093 .pce(l1en),
3094 .l1clk(l1clk),
3095 .se(se),
3096 .pce_ov(pce_ov),
3097 .stop(stop)
3098);
3099
3100
3101
3102endmodule
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112// Description: Spare gate macro for control blocks
3113//
3114// Param num controls the number of times the macro is added
3115// flops=0 can be used to use only combination spare logic
3116
3117
3118module l2t_csreg_ctl_spare_ctl_macro__num_4 (
3119 l1clk,
3120 scan_in,
3121 siclk,
3122 soclk,
3123 scan_out);
3124wire si_0;
3125wire so_0;
3126wire spare0_flop_unused;
3127wire spare0_buf_32x_unused;
3128wire spare0_nand3_8x_unused;
3129wire spare0_inv_8x_unused;
3130wire spare0_aoi22_4x_unused;
3131wire spare0_buf_8x_unused;
3132wire spare0_oai22_4x_unused;
3133wire spare0_inv_16x_unused;
3134wire spare0_nand2_16x_unused;
3135wire spare0_nor3_4x_unused;
3136wire spare0_nand2_8x_unused;
3137wire spare0_buf_16x_unused;
3138wire spare0_nor2_16x_unused;
3139wire spare0_inv_32x_unused;
3140wire si_1;
3141wire so_1;
3142wire spare1_flop_unused;
3143wire spare1_buf_32x_unused;
3144wire spare1_nand3_8x_unused;
3145wire spare1_inv_8x_unused;
3146wire spare1_aoi22_4x_unused;
3147wire spare1_buf_8x_unused;
3148wire spare1_oai22_4x_unused;
3149wire spare1_inv_16x_unused;
3150wire spare1_nand2_16x_unused;
3151wire spare1_nor3_4x_unused;
3152wire spare1_nand2_8x_unused;
3153wire spare1_buf_16x_unused;
3154wire spare1_nor2_16x_unused;
3155wire spare1_inv_32x_unused;
3156wire si_2;
3157wire so_2;
3158wire spare2_flop_unused;
3159wire spare2_buf_32x_unused;
3160wire spare2_nand3_8x_unused;
3161wire spare2_inv_8x_unused;
3162wire spare2_aoi22_4x_unused;
3163wire spare2_buf_8x_unused;
3164wire spare2_oai22_4x_unused;
3165wire spare2_inv_16x_unused;
3166wire spare2_nand2_16x_unused;
3167wire spare2_nor3_4x_unused;
3168wire spare2_nand2_8x_unused;
3169wire spare2_buf_16x_unused;
3170wire spare2_nor2_16x_unused;
3171wire spare2_inv_32x_unused;
3172wire si_3;
3173wire so_3;
3174wire spare3_flop_unused;
3175wire spare3_buf_32x_unused;
3176wire spare3_nand3_8x_unused;
3177wire spare3_inv_8x_unused;
3178wire spare3_aoi22_4x_unused;
3179wire spare3_buf_8x_unused;
3180wire spare3_oai22_4x_unused;
3181wire spare3_inv_16x_unused;
3182wire spare3_nand2_16x_unused;
3183wire spare3_nor3_4x_unused;
3184wire spare3_nand2_8x_unused;
3185wire spare3_buf_16x_unused;
3186wire spare3_nor2_16x_unused;
3187wire spare3_inv_32x_unused;
3188
3189
3190input l1clk;
3191input scan_in;
3192input siclk;
3193input soclk;
3194output scan_out;
3195
3196cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
3197 .siclk(siclk),
3198 .soclk(soclk),
3199 .si(si_0),
3200 .so(so_0),
3201 .d(1'b0),
3202 .q(spare0_flop_unused));
3203assign si_0 = scan_in;
3204
3205cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
3206 .out(spare0_buf_32x_unused));
3207cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
3208 .in1(1'b1),
3209 .in2(1'b1),
3210 .out(spare0_nand3_8x_unused));
3211cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
3212 .out(spare0_inv_8x_unused));
3213cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
3214 .in01(1'b1),
3215 .in10(1'b1),
3216 .in11(1'b1),
3217 .out(spare0_aoi22_4x_unused));
3218cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
3219 .out(spare0_buf_8x_unused));
3220cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
3221 .in01(1'b1),
3222 .in10(1'b1),
3223 .in11(1'b1),
3224 .out(spare0_oai22_4x_unused));
3225cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
3226 .out(spare0_inv_16x_unused));
3227cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
3228 .in1(1'b1),
3229 .out(spare0_nand2_16x_unused));
3230cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
3231 .in1(1'b0),
3232 .in2(1'b0),
3233 .out(spare0_nor3_4x_unused));
3234cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
3235 .in1(1'b1),
3236 .out(spare0_nand2_8x_unused));
3237cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
3238 .out(spare0_buf_16x_unused));
3239cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
3240 .in1(1'b0),
3241 .out(spare0_nor2_16x_unused));
3242cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
3243 .out(spare0_inv_32x_unused));
3244
3245cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
3246 .siclk(siclk),
3247 .soclk(soclk),
3248 .si(si_1),
3249 .so(so_1),
3250 .d(1'b0),
3251 .q(spare1_flop_unused));
3252assign si_1 = so_0;
3253
3254cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
3255 .out(spare1_buf_32x_unused));
3256cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
3257 .in1(1'b1),
3258 .in2(1'b1),
3259 .out(spare1_nand3_8x_unused));
3260cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
3261 .out(spare1_inv_8x_unused));
3262cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
3263 .in01(1'b1),
3264 .in10(1'b1),
3265 .in11(1'b1),
3266 .out(spare1_aoi22_4x_unused));
3267cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
3268 .out(spare1_buf_8x_unused));
3269cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
3270 .in01(1'b1),
3271 .in10(1'b1),
3272 .in11(1'b1),
3273 .out(spare1_oai22_4x_unused));
3274cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
3275 .out(spare1_inv_16x_unused));
3276cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
3277 .in1(1'b1),
3278 .out(spare1_nand2_16x_unused));
3279cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
3280 .in1(1'b0),
3281 .in2(1'b0),
3282 .out(spare1_nor3_4x_unused));
3283cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
3284 .in1(1'b1),
3285 .out(spare1_nand2_8x_unused));
3286cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
3287 .out(spare1_buf_16x_unused));
3288cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
3289 .in1(1'b0),
3290 .out(spare1_nor2_16x_unused));
3291cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
3292 .out(spare1_inv_32x_unused));
3293
3294cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
3295 .siclk(siclk),
3296 .soclk(soclk),
3297 .si(si_2),
3298 .so(so_2),
3299 .d(1'b0),
3300 .q(spare2_flop_unused));
3301assign si_2 = so_1;
3302
3303cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
3304 .out(spare2_buf_32x_unused));
3305cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
3306 .in1(1'b1),
3307 .in2(1'b1),
3308 .out(spare2_nand3_8x_unused));
3309cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
3310 .out(spare2_inv_8x_unused));
3311cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
3312 .in01(1'b1),
3313 .in10(1'b1),
3314 .in11(1'b1),
3315 .out(spare2_aoi22_4x_unused));
3316cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
3317 .out(spare2_buf_8x_unused));
3318cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
3319 .in01(1'b1),
3320 .in10(1'b1),
3321 .in11(1'b1),
3322 .out(spare2_oai22_4x_unused));
3323cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
3324 .out(spare2_inv_16x_unused));
3325cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
3326 .in1(1'b1),
3327 .out(spare2_nand2_16x_unused));
3328cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
3329 .in1(1'b0),
3330 .in2(1'b0),
3331 .out(spare2_nor3_4x_unused));
3332cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
3333 .in1(1'b1),
3334 .out(spare2_nand2_8x_unused));
3335cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
3336 .out(spare2_buf_16x_unused));
3337cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
3338 .in1(1'b0),
3339 .out(spare2_nor2_16x_unused));
3340cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
3341 .out(spare2_inv_32x_unused));
3342
3343cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
3344 .siclk(siclk),
3345 .soclk(soclk),
3346 .si(si_3),
3347 .so(so_3),
3348 .d(1'b0),
3349 .q(spare3_flop_unused));
3350assign si_3 = so_2;
3351
3352cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
3353 .out(spare3_buf_32x_unused));
3354cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
3355 .in1(1'b1),
3356 .in2(1'b1),
3357 .out(spare3_nand3_8x_unused));
3358cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
3359 .out(spare3_inv_8x_unused));
3360cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
3361 .in01(1'b1),
3362 .in10(1'b1),
3363 .in11(1'b1),
3364 .out(spare3_aoi22_4x_unused));
3365cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
3366 .out(spare3_buf_8x_unused));
3367cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
3368 .in01(1'b1),
3369 .in10(1'b1),
3370 .in11(1'b1),
3371 .out(spare3_oai22_4x_unused));
3372cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
3373 .out(spare3_inv_16x_unused));
3374cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
3375 .in1(1'b1),
3376 .out(spare3_nand2_16x_unused));
3377cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
3378 .in1(1'b0),
3379 .in2(1'b0),
3380 .out(spare3_nor3_4x_unused));
3381cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
3382 .in1(1'b1),
3383 .out(spare3_nand2_8x_unused));
3384cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
3385 .out(spare3_buf_16x_unused));
3386cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
3387 .in1(1'b0),
3388 .out(spare3_nor2_16x_unused));
3389cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
3390 .out(spare3_inv_32x_unused));
3391assign scan_out = so_3;
3392
3393
3394
3395endmodule
3396
3397
3398
3399
3400
3401
3402// any PARAMS parms go into naming of macro
3403
3404module l2t_csreg_ctl_msff_ctl_macro__width_5 (
3405 din,
3406 l1clk,
3407 scan_in,
3408 siclk,
3409 soclk,
3410 dout,
3411 scan_out);
3412wire [4:0] fdin;
3413wire [3:0] so;
3414
3415 input [4:0] din;
3416 input l1clk;
3417 input scan_in;
3418
3419
3420 input siclk;
3421 input soclk;
3422
3423 output [4:0] dout;
3424 output scan_out;
3425assign fdin[4:0] = din[4:0];
3426
3427
3428
3429
3430
3431
3432dff #(5) d0_0 (
3433.l1clk(l1clk),
3434.siclk(siclk),
3435.soclk(soclk),
3436.d(fdin[4:0]),
3437.si({scan_in,so[3:0]}),
3438.so({so[3:0],scan_out}),
3439.q(dout[4:0])
3440);
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453endmodule
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467// any PARAMS parms go into naming of macro
3468
3469module l2t_csreg_ctl_msff_ctl_macro__width_1 (
3470 din,
3471 l1clk,
3472 scan_in,
3473 siclk,
3474 soclk,
3475 dout,
3476 scan_out);
3477wire [0:0] fdin;
3478
3479 input [0:0] din;
3480 input l1clk;
3481 input scan_in;
3482
3483
3484 input siclk;
3485 input soclk;
3486
3487 output [0:0] dout;
3488 output scan_out;
3489assign fdin[0:0] = din[0:0];
3490
3491
3492
3493
3494
3495
3496dff #(1) d0_0 (
3497.l1clk(l1clk),
3498.siclk(siclk),
3499.soclk(soclk),
3500.d(fdin[0:0]),
3501.si(scan_in),
3502.so(scan_out),
3503.q(dout[0:0])
3504);
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517endmodule
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531// any PARAMS parms go into naming of macro
3532
3533module l2t_csreg_ctl_msff_ctl_macro__width_3 (
3534 din,
3535 l1clk,
3536 scan_in,
3537 siclk,
3538 soclk,
3539 dout,
3540 scan_out);
3541wire [2:0] fdin;
3542wire [1:0] so;
3543
3544 input [2:0] din;
3545 input l1clk;
3546 input scan_in;
3547
3548
3549 input siclk;
3550 input soclk;
3551
3552 output [2:0] dout;
3553 output scan_out;
3554assign fdin[2:0] = din[2:0];
3555
3556
3557
3558
3559
3560
3561dff #(3) d0_0 (
3562.l1clk(l1clk),
3563.siclk(siclk),
3564.soclk(soclk),
3565.d(fdin[2:0]),
3566.si({scan_in,so[1:0]}),
3567.so({so[1:0],scan_out}),
3568.q(dout[2:0])
3569);
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582endmodule
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596// any PARAMS parms go into naming of macro
3597
3598module l2t_csreg_ctl_msff_ctl_macro__clr_1__width_1 (
3599 din,
3600 clr,
3601 l1clk,
3602 scan_in,
3603 siclk,
3604 soclk,
3605 dout,
3606 scan_out);
3607wire [0:0] fdin;
3608
3609 input [0:0] din;
3610 input clr;
3611 input l1clk;
3612 input scan_in;
3613
3614
3615 input siclk;
3616 input soclk;
3617
3618 output [0:0] dout;
3619 output scan_out;
3620assign fdin[0:0] = din[0:0] & ~{1{clr}};
3621
3622
3623
3624
3625
3626
3627dff #(1) d0_0 (
3628.l1clk(l1clk),
3629.siclk(siclk),
3630.soclk(soclk),
3631.d(fdin[0:0]),
3632.si(scan_in),
3633.so(scan_out),
3634.q(dout[0:0])
3635);
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648endmodule
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662// any PARAMS parms go into naming of macro
3663
3664module l2t_csreg_ctl_msff_ctl_macro__en_1__width_1 (
3665 din,
3666 en,
3667 l1clk,
3668 scan_in,
3669 siclk,
3670 soclk,
3671 dout,
3672 scan_out);
3673wire [0:0] fdin;
3674
3675 input [0:0] din;
3676 input en;
3677 input l1clk;
3678 input scan_in;
3679
3680
3681 input siclk;
3682 input soclk;
3683
3684 output [0:0] dout;
3685 output scan_out;
3686assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
3687
3688
3689
3690
3691
3692
3693dff #(1) d0_0 (
3694.l1clk(l1clk),
3695.siclk(siclk),
3696.soclk(soclk),
3697.d(fdin[0:0]),
3698.si(scan_in),
3699.so(scan_out),
3700.q(dout[0:0])
3701);
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714endmodule
3715
3716
3717
3718
3719
3720
3721
3722
Full OpenSPARC design & verification tarball including full HDL.