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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_decc_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_decc_dp ( | |
36 | tcu_pce_ov, | |
37 | tcu_aclk, | |
38 | tcu_bclk, | |
39 | tcu_scan_en, | |
40 | tcu_clk_stop, | |
41 | decc_ret_data_c7, | |
42 | decc_arbdp_data_c8, | |
43 | decc_ret_diag_data_c7, | |
44 | decc_lda_syndrome_c9, | |
45 | deccck_dword_sel_c7, | |
46 | deccck_muxsel_diag_out_c7, | |
47 | oqu_l2_miss_c7, | |
48 | oqu_uerr_ack_c7, | |
49 | oqu_cerr_ack_c7, | |
50 | oqu_imiss_hit_c8, | |
51 | rtn_err_field_c7, | |
52 | filbuf_spc_corr_err_c6, | |
53 | filbuf_spc_rd_vld_c6, | |
54 | filbuf_spc_uncorr_err_c6, | |
55 | tag_spc_rd_vld_c6, | |
56 | mbist_dmo_data_out, | |
57 | csr_error_ceen, | |
58 | csr_error_nceen, | |
59 | deccck_uncorr_err_c8, | |
60 | deccck_corr_err_c8, | |
61 | deccck_notdata_err_c8, | |
62 | deccdp_decck_uncorr_err_c7, | |
63 | deccdp_decck_corr_err_c7, | |
64 | l2d_l2t_decc_c6, | |
65 | l2clk, | |
66 | tcu_muxtest, | |
67 | tcu_dectest, | |
68 | scan_in, | |
69 | scan_out, | |
70 | mbist_l2data_fail, | |
71 | mbist_write_data, | |
72 | mbist_l2d_write, | |
73 | tagd_evict_tag_c3, | |
74 | tcu_l2t_tag_or_data_sel); | |
75 | wire stop; | |
76 | wire pce_ov; | |
77 | wire siclk; | |
78 | wire soclk; | |
79 | wire se; | |
80 | wire muxtst; | |
81 | wire test; | |
82 | wire [5:0] decc_check0_c7_n; | |
83 | wire [5:0] decc_check1_c7_n; | |
84 | wire [5:0] decc_check2_c7_n; | |
85 | wire [5:0] decc_check3_c7_n; | |
86 | wire [5:0] decc_check0_c7; | |
87 | wire [5:0] decc_check1_c7; | |
88 | wire [5:0] decc_check2_c7; | |
89 | wire [5:0] decc_check3_c7; | |
90 | wire ce_check0_1; | |
91 | wire ce_check0_2; | |
92 | wire ce_check0_3; | |
93 | wire ce_check1_1; | |
94 | wire ce_check1_2; | |
95 | wire ce_check1_3; | |
96 | wire ce_check2_1; | |
97 | wire ce_check2_2; | |
98 | wire ce_check2_3; | |
99 | wire ce_check3_1; | |
100 | wire ce_check3_2; | |
101 | wire ce_check3_3; | |
102 | wire check0_all_ones_n; | |
103 | wire check1_all_ones_n; | |
104 | wire check2_all_ones_n; | |
105 | wire check3_all_ones_n; | |
106 | wire check0_all_ones; | |
107 | wire check1_all_ones; | |
108 | wire check2_all_ones; | |
109 | wire check3_all_ones; | |
110 | wire [3:0] corr_err_c7; | |
111 | wire decc_parity0_c7_n; | |
112 | wire decc_parity1_c7_n; | |
113 | wire decc_parity2_c7_n; | |
114 | wire decc_parity3_c7_n; | |
115 | wire data_corr_err_c8; | |
116 | wire corr_err_c7_0_2; | |
117 | wire corr_err_c7_1_3; | |
118 | wire data_corr_err_c7; | |
119 | wire data_notdata_err_c7_3; | |
120 | wire data_notdata_err_c7_2; | |
121 | wire data_notdata_err_c7_1; | |
122 | wire data_notdata_err_c7_0; | |
123 | wire filbuf_spc_rd_vld_c7; | |
124 | wire data_notdata_err_c7_a; | |
125 | wire decc_parity0_c7; | |
126 | wire decc_parity1_c7; | |
127 | wire data_notdata_err_c7_b; | |
128 | wire decc_parity2_c7; | |
129 | wire decc_parity3_c7; | |
130 | wire data_notdata_err_c7; | |
131 | wire compute0_ue_0_1_2; | |
132 | wire compute0_ue_3_4_5; | |
133 | wire compute1_ue_0_1_2; | |
134 | wire compute1_ue_3_4_5; | |
135 | wire compute2_ue_0_1_2; | |
136 | wire compute2_ue_3_4_5; | |
137 | wire compute3_ue_0_1_2; | |
138 | wire compute3_ue_3_4_5; | |
139 | wire compute0_ue_n; | |
140 | wire compute1_ue_n; | |
141 | wire compute2_ue_n; | |
142 | wire compute3_ue_n; | |
143 | wire uncorr_err_c7_0; | |
144 | wire uncorr_err_c7_1; | |
145 | wire uncorr_err_c7_2; | |
146 | wire uncorr_err_c7_3; | |
147 | wire filbuf_spc_rd_vld_c7_n; | |
148 | wire compute3_ue; | |
149 | wire compute2_ue; | |
150 | wire compute1_ue; | |
151 | wire compute0_ue; | |
152 | wire uncorr_err_c7_0_2; | |
153 | wire uncorr_err_c7_1_3; | |
154 | wire uncorr_err_c7_0_2_n; | |
155 | wire uncorr_err_c7_1_3_n; | |
156 | wire data_uncorr_err_c7; | |
157 | wire tag_spc_rd_vld_c7; | |
158 | wire filbuf_spc_uncorr_err_c7; | |
159 | wire filbuf_spc_corr_err_c7; | |
160 | wire tag_spc_rd_vld_c7_n; | |
161 | wire filbuf_spc_uncorr_err_c7_n; | |
162 | wire filbuf_spc_corr_err_c7_n; | |
163 | wire tag_fb_spc_rd_ce_c7; | |
164 | wire [1:0] opt_c7terms_n; | |
165 | wire error_ceen_d1; | |
166 | wire [1:0] opt_c7terms; | |
167 | wire tag_fb_spc_rd_ue_c7; | |
168 | wire error_nceen_d1; | |
169 | wire [1:0] ret_err_c7_uece_n; | |
170 | wire [1:0] ret_err_c7_uece; | |
171 | wire ret_err_c7_nd_n; | |
172 | wire [2:1] ret_err_c7; | |
173 | wire [0:0] ret_err_c7_n; | |
174 | wire ret_err_c7_nd; | |
175 | wire oqu_cerr_ack_c7_or_ret_err_c7_nd_n; | |
176 | wire rtn_err_field_c7_1_n; | |
177 | wire ret_err_c8_1; | |
178 | wire [27:0] retbuf_ret_ecc_c7; | |
179 | wire [127:0] retbuf_ret_data_c7; | |
180 | wire ff_data_rtn_c8_127_96_scanin; | |
181 | wire ff_data_rtn_c8_127_96_scanout; | |
182 | wire ff_data_rtn_c8_95_64_scanin; | |
183 | wire ff_data_rtn_c8_95_64_scanout; | |
184 | wire ff_data_rtn_c8_63_32_scanin; | |
185 | wire ff_data_rtn_c8_63_32_scanout; | |
186 | wire ff_data_rtn_c8_31_0_scanin; | |
187 | wire ff_data_rtn_c8_31_0_scanout; | |
188 | wire ff_error_synd_c8_scanin; | |
189 | wire ff_error_synd_c8_scanout; | |
190 | wire ff_lda_syndrome_c9_scanin; | |
191 | wire ff_lda_syndrome_c9_scanout; | |
192 | wire mbist_l2data_fail0; | |
193 | wire [7:0] mbist_write_data_c6; | |
194 | wire mbist_l2data_fail1; | |
195 | wire mbist_l2data_fail_fnl; | |
196 | wire mbist_l2data_fail_w; | |
197 | wire mbist_l2d_write_c6_n; | |
198 | wire mbist_l2d_write_c6; | |
199 | wire ff_fame_mbist_flops_0_scanin; | |
200 | wire ff_fame_mbist_flops_0_scanout; | |
201 | wire [7:0] mbist_write_data_c4; | |
202 | wire [7:0] mbist_write_data_c5; | |
203 | wire [7:0] mbist_write_data_c52; | |
204 | wire mbist_l2d_write_c3; | |
205 | wire mbist_l2d_write_c4; | |
206 | wire mbist_l2d_write_c5; | |
207 | wire mbist_l2d_write_c52; | |
208 | wire ff_fame_mbist_flops_scanin; | |
209 | wire ff_fame_mbist_flops_scanout; | |
210 | wire [7:0] mbist_write_data_c1; | |
211 | wire [7:0] mbist_write_data_c2; | |
212 | wire mbist_l2d_write_c1; | |
213 | wire mbist_l2d_write_c2; | |
214 | wire [7:0] mbist_write_data_c3; | |
215 | wire [127:0] ret_data_c7_buf; | |
216 | wire [27:0] ret_ecc_c7_buf; | |
217 | wire [127:0] ret_data_c6; | |
218 | wire [27:0] ret_ecc_c6; | |
219 | wire ff_data_rtn_c7_1split1_scanin; | |
220 | wire ff_data_rtn_c7_1split1_scanout; | |
221 | wire ff_data_rtn_c7_1split2_scanin; | |
222 | wire ff_data_rtn_c7_1split2_scanout; | |
223 | wire ff_data_rtn_c7_1split3_scanin; | |
224 | wire ff_data_rtn_c7_1split3_scanout; | |
225 | wire ff_data_rtn_c7_1split4_scanin; | |
226 | wire ff_data_rtn_c7_1split4_scanout; | |
227 | ||
228 | ||
229 | input tcu_pce_ov; | |
230 | input tcu_aclk; | |
231 | input tcu_bclk; | |
232 | input tcu_scan_en; | |
233 | input tcu_clk_stop; | |
234 | ||
235 | output [127:0] decc_ret_data_c7; // data to oque | |
236 | output [63:0] decc_arbdp_data_c8; // data to arbdat | |
237 | output [38:0] decc_ret_diag_data_c7 ; // diagnostic data | |
238 | output [27:0] decc_lda_syndrome_c9; // to csr block | |
239 | ||
240 | ||
241 | // from and to decc | |
242 | //input deccck_sel_higher_word_c7; | |
243 | //input deccck_sel_higher_dword_c7; | |
244 | input deccck_dword_sel_c7; | |
245 | input [3:0] deccck_muxsel_diag_out_c7; | |
246 | ||
247 | //output [2:0] deccck_ret_err_c7; | |
248 | input oqu_l2_miss_c7 ; // NEW_PIN | |
249 | input oqu_uerr_ack_c7; // asynchronous uncorr err | |
250 | input oqu_cerr_ack_c7; // asynchronous corr err | |
251 | input oqu_imiss_hit_c8; | |
252 | output [2:0] rtn_err_field_c7; | |
253 | ||
254 | input filbuf_spc_corr_err_c6; | |
255 | input filbuf_spc_rd_vld_c6; | |
256 | input filbuf_spc_uncorr_err_c6; | |
257 | input tag_spc_rd_vld_c6; | |
258 | ||
259 | //input filbuf_spc_corr_err_c7; | |
260 | //input filbuf_spc_rd_vld_c7; | |
261 | //input filbuf_spc_uncorr_err_c7; | |
262 | //input tag_spc_rd_vld_c7; | |
263 | //////////////////////////////////////////// | |
264 | ||
265 | ||
266 | output [38:0] mbist_dmo_data_out; | |
267 | input csr_error_ceen; | |
268 | input csr_error_nceen; | |
269 | ||
270 | output deccck_uncorr_err_c8; // an uncorr err has happenned Unqual | |
271 | output deccck_corr_err_c8; // a correctable err has happened | |
272 | output deccck_notdata_err_c8; // a notdata err has happened | |
273 | ||
274 | output [3:0] deccdp_decck_uncorr_err_c7; // an uncorr err has happenned Unqual | |
275 | output [3:0] deccdp_decck_corr_err_c7; // a correctable err has happened | |
276 | ||
277 | ////////////////////////////////////////////////////////////////////////////////////////// | |
278 | ||
279 | //input [127:0] retbuf_ret_data_c7; | |
280 | //input [27:0] retbuf_ret_ecc_c7; | |
281 | ||
282 | input [155:0] l2d_l2t_decc_c6; | |
283 | ||
284 | ||
285 | input l2clk; | |
286 | input tcu_muxtest; | |
287 | input tcu_dectest; | |
288 | input scan_in; | |
289 | output scan_out; | |
290 | output mbist_l2data_fail; | |
291 | input [7:0] mbist_write_data; | |
292 | input mbist_l2d_write; | |
293 | ||
294 | input [27:0] tagd_evict_tag_c3; | |
295 | input tcu_l2t_tag_or_data_sel; | |
296 | ||
297 | assign stop = tcu_clk_stop; | |
298 | assign pce_ov = tcu_pce_ov; | |
299 | assign siclk = tcu_aclk; | |
300 | assign soclk = tcu_bclk; | |
301 | assign se = tcu_scan_en; | |
302 | assign muxtst = tcu_muxtest; | |
303 | assign test = tcu_dectest; | |
304 | ||
305 | wire [127:0] corr_data_c7; | |
306 | wire [38:0] data_word0_c7; | |
307 | wire [38:0] data_word1_c7; | |
308 | wire [38:0] data_word2_c7; | |
309 | wire [38:0] data_word3_c7; | |
310 | ||
311 | wire [38:0] left_diag_out_c7; | |
312 | wire [38:0] rgt_diag_out_c7; | |
313 | ||
314 | wire [127:0] decc_ret_data_c8; // data to oque | |
315 | ||
316 | wire [27:0] error_synd_c7; | |
317 | wire [27:0] error_synd_c8; | |
318 | ||
319 | wire dword_sel_c8; | |
320 | wire [3:0] uncorr_err_c7_n; | |
321 | ||
322 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
323 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
324 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
325 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
326 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
327 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
328 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
329 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
330 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
331 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
332 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
333 | ///////////////////////////////////////////////////////////////////////////////////////////////// | |
334 | //assign corr_err_c7[0] = decc_parity0_c7 & ~(decc_check0_c7[5:0] == 6'b111111); | |
335 | //assign corr_err_c7[1] = decc_parity1_c7 & ~(decc_check1_c7[5:0] == 6'b111111); | |
336 | //assign corr_err_c7[2] = decc_parity2_c7 & ~(decc_check2_c7[5:0] == 6'b111111); | |
337 | //assign corr_err_c7[3] = decc_parity3_c7 & ~(decc_check3_c7[5:0] == 6'b111111); | |
338 | //assign deccdp_decck_corr_err_c7[3:0] = corr_err_c7[3:0]; | |
339 | ||
340 | l2t_decc_dp_inv_macro__dinv_32x__stack_32r__width_24 inv_checkbits | |
341 | ( | |
342 | .dout ({decc_check0_c7_n[5:0],decc_check1_c7_n[5:0],decc_check2_c7_n[5:0],decc_check3_c7_n[5:0]}), | |
343 | .din ({decc_check0_c7[5:0],decc_check1_c7[5:0],decc_check2_c7[5:0],decc_check3_c7[5:0]}) | |
344 | ); | |
345 | ||
346 | l2t_decc_dp_nor_macro__dnor_16x__ports_2__width_3 nor_ce_check0_1 | |
347 | ( | |
348 | .dout ({ce_check0_1, ce_check0_2, ce_check0_3}), | |
349 | .din0 ({decc_check0_c7_n[0],decc_check0_c7_n[2],decc_check0_c7_n[4]}), | |
350 | .din1 ({decc_check0_c7_n[1],decc_check0_c7_n[3],decc_check0_c7_n[5]}) | |
351 | ); | |
352 | ||
353 | l2t_decc_dp_nor_macro__dnor_16x__ports_2__width_3 nor_ce_check1_1 | |
354 | ( | |
355 | .dout ({ce_check1_1, ce_check1_2, ce_check1_3}), | |
356 | .din0 ({decc_check1_c7_n[0],decc_check1_c7_n[2],decc_check1_c7_n[4]}), | |
357 | .din1 ({decc_check1_c7_n[1],decc_check1_c7_n[3],decc_check1_c7_n[5]}) | |
358 | ); | |
359 | ||
360 | l2t_decc_dp_nor_macro__dnor_16x__ports_2__width_3 nor_ce_check2_1 | |
361 | ( | |
362 | .dout ({ce_check2_1, ce_check2_2, ce_check2_3}), | |
363 | .din0 ({decc_check2_c7_n[0],decc_check2_c7_n[2],decc_check2_c7_n[4]}), | |
364 | .din1 ({decc_check2_c7_n[1],decc_check2_c7_n[3],decc_check2_c7_n[5]}) | |
365 | ); | |
366 | ||
367 | l2t_decc_dp_nor_macro__dnor_16x__ports_2__width_3 nor_ce_check3_1 | |
368 | ( | |
369 | .dout ({ce_check3_1, ce_check3_2, ce_check3_3}), | |
370 | .din0 ({decc_check3_c7_n[0],decc_check3_c7_n[2],decc_check3_c7_n[4]}), | |
371 | .din1 ({decc_check3_c7_n[1],decc_check3_c7_n[3],decc_check3_c7_n[5]}) | |
372 | ); | |
373 | ||
374 | l2t_decc_dp_nand_macro__dnand_24x__ports_3__width_4 nand_ce_check0_2 | |
375 | ( | |
376 | .dout ({check0_all_ones_n,check1_all_ones_n,check2_all_ones_n,check3_all_ones_n}), | |
377 | .din0 ({ce_check0_1, ce_check1_1, ce_check2_1, ce_check3_1 }), | |
378 | .din1 ({ce_check0_2, ce_check1_2, ce_check2_2, ce_check3_2 }), | |
379 | .din2 ({ce_check0_3, ce_check1_3, ce_check2_3, ce_check3_3 }) | |
380 | ); | |
381 | ||
382 | ||
383 | l2t_decc_dp_inv_macro__dinv_32x__width_4 inv_deccdp_decck_corr_err_c7 | |
384 | ( | |
385 | .din ({check0_all_ones_n,check1_all_ones_n,check2_all_ones_n,check3_all_ones_n}), | |
386 | .dout ({check0_all_ones,check1_all_ones,check2_all_ones,check3_all_ones}) | |
387 | ); | |
388 | ||
389 | l2t_decc_dp_nor_macro__dnor_16x__width_4 nor_corr_err_c7 | |
390 | ( | |
391 | .dout ({corr_err_c7[0],corr_err_c7[1],corr_err_c7[2],corr_err_c7[3]}), | |
392 | .din0 ({check0_all_ones,check1_all_ones,check2_all_ones,check3_all_ones}), | |
393 | .din1 ({decc_parity0_c7_n,decc_parity1_c7_n,decc_parity2_c7_n,decc_parity3_c7_n}) | |
394 | ); | |
395 | ||
396 | l2t_decc_dp_buff_macro__dbuff_32x__width_5 buff_deccdp_decck_corr_err_c7 | |
397 | ( | |
398 | .dout ({deccck_corr_err_c8,deccdp_decck_corr_err_c7[3:0]}), | |
399 | .din ({data_corr_err_c8,corr_err_c7[3:0]}) | |
400 | ); | |
401 | ||
402 | l2t_decc_dp_nor_macro__dnor_16x__width_2 nor_corr_err_c7_0_to_3 | |
403 | ( | |
404 | .dout ({corr_err_c7_0_2,corr_err_c7_1_3}), | |
405 | .din0 ({corr_err_c7[0] ,corr_err_c7[1] }), | |
406 | .din1 ({corr_err_c7[2] ,corr_err_c7[3] }) | |
407 | ); | |
408 | ||
409 | l2t_decc_dp_nand_macro__dnand_24x__width_1 nand_data_corr_err_c7 | |
410 | ( | |
411 | .dout (data_corr_err_c7), | |
412 | .din0 (corr_err_c7_0_2), | |
413 | .din1 (corr_err_c7_1_3) | |
414 | ); | |
415 | ||
416 | ||
417 | //////////////////////////////////////////////////////////////////////////////////////////////////////// | |
418 | //assign deccck_corr_err_c8 = data_corr_err_c8; | |
419 | // // BS 03/18/04 : taking out deccck_corr_err_c8 to gate off cas and | |
420 | // // swap/ldstub stores updates in case of Correctable Error as part | |
421 | // // of new requirment for RAS in N2 to retry the atomics on a CE. | |
422 | // // because of the retry, the update for the store should not happen | |
423 | // // in L2. | |
424 | //////////////////////////////////////////////////////////////////////////////////////////////////////// | |
425 | // in case the Notdata is detected on a sparc read of the Fill buffer itself, should | |
426 | // treat it as UE . this is because a UE trap has not been issued yet, as the | |
427 | // read of the fill buffer is happening before the fill. | |
428 | // | |
429 | //assign data_notdata_err_c7 = (decc_parity0_c7 & data_notdata_err_c7_0)| | |
430 | // (decc_parity1_c7 & data_notdata_err_c7_1) | | |
431 | // (decc_parity2_c7 & data_notdata_err_c7_2) | | |
432 | // (decc_parity3_c7 & data_notdata_err_c7_3); | |
433 | ||
434 | l2t_decc_dp_nor_macro__dnor_16x__ports_2__width_4 nor_data_notdata_err_c7_0to3 | |
435 | ( | |
436 | .dout ({data_notdata_err_c7_3,data_notdata_err_c7_2,data_notdata_err_c7_1,data_notdata_err_c7_0}), | |
437 | .din0 ({check3_all_ones_n, check2_all_ones_n, check1_all_ones_n, check0_all_ones_n}), | |
438 | .din1 ({filbuf_spc_rd_vld_c7, filbuf_spc_rd_vld_c7, filbuf_spc_rd_vld_c7, filbuf_spc_rd_vld_c7}) | |
439 | ); | |
440 | ||
441 | ||
442 | cl_u1_aoi22_8x aoi_data_notdata_err_c7_a | |
443 | ( | |
444 | .out (data_notdata_err_c7_a), | |
445 | .in00 (decc_parity0_c7), | |
446 | .in01 (data_notdata_err_c7_0), | |
447 | .in10 (decc_parity1_c7), | |
448 | .in11 (data_notdata_err_c7_1) | |
449 | ); | |
450 | ||
451 | ||
452 | ||
453 | cl_u1_aoi22_8x aoi_data_notdata_err_c7_b | |
454 | ( | |
455 | .out (data_notdata_err_c7_b), | |
456 | .in00 (decc_parity2_c7), | |
457 | .in01 (data_notdata_err_c7_2), | |
458 | .in10 (decc_parity3_c7), | |
459 | .in11 (data_notdata_err_c7_3) | |
460 | ); | |
461 | ||
462 | l2t_decc_dp_nand_macro__dnand_24x__width_1 nand_data_notdata_err_c7 | |
463 | ( | |
464 | .dout (data_notdata_err_c7), | |
465 | .din0 (data_notdata_err_c7_a), | |
466 | .din1 (data_notdata_err_c7_b) | |
467 | ); | |
468 | ||
469 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
470 | //assign uncorr_err_c7[0] = (|(decc_check0_c7[5:0]) & ~decc_parity0_c7) | | |
471 | // (({decc_parity0_c7,decc_check0_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7) ; | |
472 | //assign uncorr_err_c7[1] = (|(decc_check1_c7[5:0]) & ~decc_parity1_c7) | | |
473 | // (({decc_parity1_c7,decc_check1_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7); | |
474 | //assign uncorr_err_c7[2] = (|(decc_check2_c7[5:0]) & ~decc_parity2_c7) | | |
475 | // (({decc_parity2_c7,decc_check2_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7) ; | |
476 | //assign uncorr_err_c7[3] = (|(decc_check3_c7[5:0]) & ~decc_parity3_c7) | | |
477 | // (({decc_parity3_c7,decc_check3_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7) ; | |
478 | ||
479 | l2t_decc_dp_nand_macro__dnand_16x__ports_3__width_8 nand_checkbits_for_ue | |
480 | ( | |
481 | .dout ({compute0_ue_0_1_2, compute0_ue_3_4_5, | |
482 | compute1_ue_0_1_2, compute1_ue_3_4_5, | |
483 | compute2_ue_0_1_2, compute2_ue_3_4_5, | |
484 | compute3_ue_0_1_2, compute3_ue_3_4_5}), | |
485 | .din0 ({decc_check0_c7_n[0], decc_check0_c7_n[3], | |
486 | decc_check1_c7_n[0], decc_check1_c7_n[3], | |
487 | decc_check2_c7_n[0], decc_check2_c7_n[3], | |
488 | decc_check3_c7_n[0], decc_check3_c7_n[3]}), | |
489 | .din1 ({decc_check0_c7_n[1], decc_check0_c7_n[4], | |
490 | decc_check1_c7_n[1], decc_check1_c7_n[4], | |
491 | decc_check2_c7_n[1], decc_check2_c7_n[4], | |
492 | decc_check3_c7_n[1], decc_check3_c7_n[4]}), | |
493 | .din2 ({decc_check0_c7_n[2], decc_check0_c7_n[5], | |
494 | decc_check1_c7_n[2], decc_check1_c7_n[5], | |
495 | decc_check2_c7_n[2], decc_check2_c7_n[5], | |
496 | decc_check3_c7_n[2], decc_check3_c7_n[5]}) | |
497 | ); | |
498 | ||
499 | cl_u1_oai12_16x oai_compute0_ue_term1 | |
500 | ( | |
501 | .out (compute0_ue_n), | |
502 | .in00 (compute0_ue_0_1_2), | |
503 | .in01 (compute0_ue_3_4_5), | |
504 | .in10 (decc_parity0_c7_n) | |
505 | ); | |
506 | ||
507 | cl_u1_oai12_16x oai_compute1_ue_term1 | |
508 | ( | |
509 | .out (compute1_ue_n), | |
510 | .in00 (compute1_ue_0_1_2), | |
511 | .in01 (compute1_ue_3_4_5), | |
512 | .in10 (decc_parity1_c7_n) | |
513 | ); | |
514 | ||
515 | cl_u1_oai12_16x oai_compute2_ue_term1 | |
516 | ( | |
517 | .out (compute2_ue_n), | |
518 | .in00 (compute2_ue_0_1_2), | |
519 | .in01 (compute2_ue_3_4_5), | |
520 | .in10 (decc_parity2_c7_n) | |
521 | ); | |
522 | ||
523 | cl_u1_oai12_16x oai_compute3_ue_term1 | |
524 | ( | |
525 | .out (compute3_ue_n), | |
526 | .in00 (compute3_ue_0_1_2), | |
527 | .in01 (compute3_ue_3_4_5), | |
528 | .in10 (decc_parity3_c7_n) | |
529 | ); | |
530 | ||
531 | l2t_decc_dp_nor_macro__dnor_16x__width_4 nor_uncorr_err_c7_0123 | |
532 | ( | |
533 | .dout ({uncorr_err_c7_0,uncorr_err_c7_1,uncorr_err_c7_2,uncorr_err_c7_3}), | |
534 | .din0 ({check0_all_ones_n,check1_all_ones_n,check2_all_ones_n,check3_all_ones_n}), | |
535 | .din1 ({4{filbuf_spc_rd_vld_c7_n}}) | |
536 | ); | |
537 | ||
538 | l2t_decc_dp_inv_macro__dinv_32x__width_4 inv_computed_ue_signals | |
539 | ( | |
540 | .dout ({compute3_ue,compute2_ue,compute1_ue,compute0_ue}), | |
541 | .din ({compute3_ue_n,compute2_ue_n,compute1_ue_n,compute0_ue_n}) | |
542 | ); | |
543 | ||
544 | cl_u1_aoi12_16x aoi_uncorr_err_c7_bit0 | |
545 | ( | |
546 | .out (uncorr_err_c7_n[0]), | |
547 | .in00 (decc_parity0_c7), | |
548 | .in01 (uncorr_err_c7_0), | |
549 | .in10 (compute0_ue) | |
550 | ); | |
551 | ||
552 | cl_u1_aoi12_16x aoi_uncorr_err_c7_bit1 | |
553 | ( | |
554 | .out (uncorr_err_c7_n[1]), | |
555 | .in00 (decc_parity1_c7), | |
556 | .in01 (uncorr_err_c7_1), | |
557 | .in10 (compute1_ue) | |
558 | ); | |
559 | cl_u1_aoi12_16x aoi_uncorr_err_c7_bit2 | |
560 | ( | |
561 | .out (uncorr_err_c7_n[2]), | |
562 | .in00 (decc_parity2_c7), | |
563 | .in01 (uncorr_err_c7_2), | |
564 | .in10 (compute2_ue) | |
565 | ); | |
566 | cl_u1_aoi12_16x aoi_uncorr_err_c7_bit3 | |
567 | ( | |
568 | .out (uncorr_err_c7_n[3]), | |
569 | .in00 (decc_parity3_c7), | |
570 | .in01 (uncorr_err_c7_3), | |
571 | .in10 (compute3_ue) | |
572 | ); | |
573 | ||
574 | ||
575 | l2t_decc_dp_inv_macro__dinv_32x__width_4 inv_uncorr_err_c7 | |
576 | ( | |
577 | .dout (deccdp_decck_uncorr_err_c7[3:0]), | |
578 | .din (uncorr_err_c7_n[3:0]) | |
579 | ); | |
580 | ||
581 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
582 | //assign deccdp_decck_uncorr_err_c7[3:0] = uncorr_err_c7[3:0] ; | |
583 | ||
584 | l2t_decc_dp_nand_macro__dnand_16x__width_2 nand_uncorr_err_c7_0_to_3 | |
585 | ( | |
586 | .dout ({uncorr_err_c7_0_2,uncorr_err_c7_1_3}), | |
587 | .din0 ({uncorr_err_c7_n[0] ,uncorr_err_c7_n[1]}), | |
588 | .din1 ({uncorr_err_c7_n[2] ,uncorr_err_c7_n[3]}) | |
589 | ); | |
590 | ||
591 | l2t_decc_dp_inv_macro__dinv_24x__stack_2r__width_2 inv_uncorr_err_c7_0_2_n | |
592 | ( | |
593 | .dout ({uncorr_err_c7_0_2_n,uncorr_err_c7_1_3_n}), | |
594 | .din ({uncorr_err_c7_0_2,uncorr_err_c7_1_3}) | |
595 | ); | |
596 | ||
597 | l2t_decc_dp_nand_macro__dnand_32x__width_1 nand_data_uncorr_err_c7 | |
598 | ( | |
599 | .dout (data_uncorr_err_c7), | |
600 | .din0 (uncorr_err_c7_0_2_n), | |
601 | .din1 (uncorr_err_c7_1_3_n) | |
602 | ); | |
603 | ||
604 | ||
605 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
606 | // AOI = 20ps | |
607 | // | |
608 | //assign opt_c7terms[0] = ((tag_spc_rd_vld_c7 | filbuf_spc_rd_vld_c7 | filbuf_spc_corr_err_c7 ) | |
609 | // & error_ceen_d1 ); | |
610 | //assign opt_c7terms[1] = ((tag_spc_rd_vld_c7 | filbuf_spc_rd_vld_c7 | filbuf_spc_uncorr_err_c7 ) | |
611 | // & error_nceen_d1 ); | |
612 | // | |
613 | ||
614 | l2t_decc_dp_inv_macro__dinv_32x__width_4 inv_filbuf_spc_rd_vld_c7 | |
615 | ( | |
616 | .din({tag_spc_rd_vld_c7,filbuf_spc_uncorr_err_c7, | |
617 | filbuf_spc_corr_err_c7,filbuf_spc_rd_vld_c7}), | |
618 | .dout({tag_spc_rd_vld_c7_n,filbuf_spc_uncorr_err_c7_n, | |
619 | filbuf_spc_corr_err_c7_n,filbuf_spc_rd_vld_c7_n}) | |
620 | ); | |
621 | ||
622 | ||
623 | //msffi_macro ff_opt_c7terms (width=4,dmsffi=32x) | |
624 | // ( | |
625 | // .dout_l ({tag_spc_rd_vld_c7_n,filbuf_spc_rd_vld_c7_n, | |
626 | // filbuf_spc_corr_err_c7_n,filbuf_spc_uncorr_err_c7_n}), | |
627 | // .din ({tag_spc_rd_vld_c6,filbuf_spc_rd_vld_c6, | |
628 | // filbuf_spc_corr_err_c6,filbuf_spc_uncorr_err_c6}), | |
629 | // .scan_in(ff_opt_c7terms_scanin), | |
630 | // .scan_out(ff_opt_c7terms_scanout), | |
631 | // .clk (l2clk), | |
632 | // .en (1'b1), | |
633 | // ); | |
634 | ||
635 | ||
636 | l2t_decc_dp_nand_macro__ports_3__width_1 nand_opt_terms_bit0_1 | |
637 | ( | |
638 | .dout (tag_fb_spc_rd_ce_c7), | |
639 | .din0 (tag_spc_rd_vld_c7_n), | |
640 | .din1 (filbuf_spc_rd_vld_c7_n), | |
641 | .din2 (filbuf_spc_corr_err_c7_n) | |
642 | ); | |
643 | ||
644 | ||
645 | l2t_decc_dp_nand_macro__dnand_16x__width_1 nand_opt_c7terms_bit0_2 | |
646 | ( | |
647 | .dout (opt_c7terms_n[0]), | |
648 | .din0 (tag_fb_spc_rd_ce_c7), | |
649 | .din1 (error_ceen_d1) | |
650 | ); | |
651 | ||
652 | l2t_decc_dp_inv_macro__dinv_32x__width_2 inv_opt_c7terms_bit0 | |
653 | ( | |
654 | .dout (opt_c7terms[1:0]), | |
655 | .din (opt_c7terms_n[1:0]) | |
656 | ); | |
657 | ||
658 | l2t_decc_dp_nand_macro__ports_3__width_1 nand_opt_terms_bit1_2 | |
659 | ( | |
660 | .dout (tag_fb_spc_rd_ue_c7), | |
661 | .din0 (tag_spc_rd_vld_c7_n), | |
662 | .din1 (filbuf_spc_rd_vld_c7_n), | |
663 | .din2 (filbuf_spc_uncorr_err_c7_n) | |
664 | ); | |
665 | ||
666 | l2t_decc_dp_nand_macro__dnand_16x__width_1 nand_opt_c7terms_bit1_2 | |
667 | ( | |
668 | .dout (opt_c7terms_n[1]), | |
669 | .din0 (tag_fb_spc_rd_ue_c7), | |
670 | .din1 (error_nceen_d1) | |
671 | ); | |
672 | ||
673 | ||
674 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
675 | //assign ret_err_c7_uece[0] = (data_corr_err_c7 | filbuf_spc_corr_err_c7) & opt_c7terms[0]; | |
676 | //assign ret_err_c7_uece[1] = (data_uncorr_err_c7 | filbuf_spc_uncorr_err_c7) & opt_c7terms[1]; | |
677 | ||
678 | cl_u1_oai12_16x oai_ret_err_c7_uece_bit0 | |
679 | ( | |
680 | .out (ret_err_c7_uece_n[0]), | |
681 | .in00 (data_corr_err_c7), | |
682 | .in01 (filbuf_spc_corr_err_c7), | |
683 | .in10 (opt_c7terms[0]) | |
684 | ); | |
685 | ||
686 | cl_u1_oai12_16x oai_ret_err_c7_uece_bit1 | |
687 | ( | |
688 | .out (ret_err_c7_uece_n[1]), | |
689 | .in00 (data_uncorr_err_c7), | |
690 | .in01 (filbuf_spc_uncorr_err_c7), | |
691 | .in10 (opt_c7terms[1]) | |
692 | ); | |
693 | ||
694 | ||
695 | l2t_decc_dp_inv_macro__dinv_32x__width_2 inv_ret_err_c7_uece | |
696 | ( | |
697 | .dout (ret_err_c7_uece[1:0]), | |
698 | .din (ret_err_c7_uece_n[1:0]) | |
699 | ); | |
700 | ||
701 | ||
702 | ||
703 | ///////////////////////////////////////////////////////////////////////////////////////////////////// | |
704 | ||
705 | //assign ret_err_c7_nd = ~(~(tag_spc_rd_vld_c7 & error_nceen_d1 & data_notdata_err_c7)); | |
706 | ||
707 | l2t_decc_dp_nand_macro__dnand_16x__ports_3__width_1 nand_ret_err_c7_nd | |
708 | ( | |
709 | .dout (ret_err_c7_nd_n), | |
710 | .din0 (tag_spc_rd_vld_c7), | |
711 | .din1 (error_nceen_d1), | |
712 | .din2 (data_notdata_err_c7) | |
713 | ); | |
714 | ||
715 | //assign ret_err_c7_nd = ~ret_err_c7_nd_n; | |
716 | ||
717 | ||
718 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
719 | ||
720 | //assign ret_err_c7[0] = (ret_err_c7_uece[0] & ~ret_err_c7_uece[1]) | ret_err_c7_nd; | |
721 | //assign ret_err_c7[1] = ret_err_c7_uece[1] | ret_err_c7_nd[0]; | |
722 | ||
723 | assign ret_err_c7[2] = 1'b0 ; // RSVD | |
724 | ||
725 | l2t_decc_dp_nand_macro__width_1 nand_ret_err_c7_bit1 | |
726 | ( | |
727 | .dout (ret_err_c7[1]), | |
728 | .din0 (ret_err_c7_uece_n[1]), | |
729 | .din1 (ret_err_c7_nd_n) | |
730 | ); | |
731 | ||
732 | //cl_u1_aoi12_16x aoi_ret_err_c7_bit0 | |
733 | // ( | |
734 | // .out (ret_err_c7_n[0]), | |
735 | // .in00 (ret_err_c7_uece[0]), | |
736 | // .in01 (ret_err_c7_uece_n[1]), | |
737 | // .in10 (1'b0) | |
738 | // ); | |
739 | ||
740 | //assign ret_err_c7_n[0] = ~(ret_err_c7_uece[0] & ret_err_c7_uece_n[1]); | |
741 | ||
742 | l2t_decc_dp_nand_macro__dnand_32x__ports_2__width_1 nand_ret_err_c7_n_bit0 | |
743 | ( | |
744 | .dout (ret_err_c7_n[0]), | |
745 | .din0 (ret_err_c7_uece[0]), | |
746 | .din1 (ret_err_c7_uece_n[1]) | |
747 | ); | |
748 | ||
749 | l2t_decc_dp_inv_macro__dinv_32x__width_1 inv_oqu_cerr_ack_c7_n | |
750 | ( | |
751 | .dout (ret_err_c7_nd), | |
752 | .din (ret_err_c7_nd_n) | |
753 | ); | |
754 | ||
755 | //assign rtn_err_field_c7[0] = oqu_cerr_ack_c7 | ret_err_c7_n[0] | ret_err_c7_nd; | |
756 | //nand_macro nand_rtn_err_field_c7 (width=1,ports=3,dnand=24x) | |
757 | // ( | |
758 | // .dout (rtn_err_field_c7[0]), | |
759 | // .din0 (oqu_cerr_ack_c7_n), | |
760 | // .din1 (ret_err_c7_nd_n), | |
761 | // .din2 (ret_err_c7_n[0]) | |
762 | // ); | |
763 | ||
764 | ||
765 | l2t_decc_dp_nor_macro__dnor_16x__width_1 nor_cerr_nd | |
766 | ( | |
767 | .dout (oqu_cerr_ack_c7_or_ret_err_c7_nd_n), | |
768 | .din0 (oqu_cerr_ack_c7), | |
769 | .din1 (ret_err_c7_nd) | |
770 | ); | |
771 | ||
772 | l2t_decc_dp_nand_macro__dnand_32x__ports_2__width_1 nand_rtn_err_field_c7 | |
773 | ( | |
774 | .dout (rtn_err_field_c7[0]), | |
775 | .din0 (oqu_cerr_ack_c7_or_ret_err_c7_nd_n), | |
776 | .din1 (ret_err_c7_n[0]) | |
777 | ); | |
778 | ||
779 | ||
780 | ||
781 | ||
782 | cl_u1_aoi12_16x aoi_rtn_err_field_c7_1_slice | |
783 | ( | |
784 | .out (rtn_err_field_c7_1_n), | |
785 | .in00 (ret_err_c8_1), | |
786 | .in01 (oqu_imiss_hit_c8), | |
787 | .in10 (oqu_uerr_ack_c7) | |
788 | ); | |
789 | ||
790 | ||
791 | //assign rtn_err_field_c7[1] = oqu_uerr_ack_c7 | (ret_err_c8_1 & oqu_imiss_hit_c8) | | |
792 | // ret_err_c7_uece[1] | ret_err_c7_nd[0] ; | |
793 | //assign rtn_err_field_c7[1] = ~rtn_err_field_c7_1_n | ret_err_c7_uece[1] | ret_err_c7_nd[0] ; | |
794 | ||
795 | l2t_decc_dp_nand_macro__dnand_24x__ports_3__width_1 nand_rtn_err_field_c7_bit1 | |
796 | ( | |
797 | .dout (rtn_err_field_c7[1]), | |
798 | .din0 (rtn_err_field_c7_1_n), | |
799 | .din1 (ret_err_c7_uece_n[1]), | |
800 | .din2 (ret_err_c7_nd_n) | |
801 | ); | |
802 | //assign rtn_err_field_c7[2] = oqu_l2_miss_c7; | |
803 | l2t_decc_dp_buff_macro__dbuff_32x__width_1 buff_rtn_err_field_c7_bit2 | |
804 | ( | |
805 | .dout (rtn_err_field_c7[2]), | |
806 | .din (oqu_l2_miss_c7) | |
807 | ); | |
808 | ||
809 | ||
810 | ||
811 | ||
812 | ///////////////////////////////////////////////////////////////////////////////////////////////////// | |
813 | // | |
814 | //msff_macro ff_all_err_signals (width=6,stack=10r,dmsff=32x) | |
815 | // ( | |
816 | // .scan_in(ff_all_err_signals_scanin), | |
817 | // .scan_out(ff_all_err_signals_scanout), | |
818 | // .dout ({ret_err_c8_1,error_ceen_d1,error_nceen_d1,deccck_uncorr_err_c8, | |
819 | // data_corr_err_c8,deccck_notdata_err_c8}), | |
820 | // .din ({ret_err_c7[1],csr_error_ceen,csr_error_nceen,data_uncorr_err_c7, | |
821 | // data_corr_err_c7,data_notdata_err_c7}), | |
822 | // .en (1'b1), | |
823 | // .clk (l2clk) | |
824 | // ); | |
825 | // | |
826 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
827 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
828 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
829 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
830 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
831 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
832 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |
833 | ||
834 | ||
835 | l2t_ecc39a_dp bit117_155 | |
836 | ( | |
837 | .dout (corr_data_c7[127:96]), | |
838 | .cflag (decc_check3_c7[5:0]), | |
839 | .pflag (decc_parity3_c7), | |
840 | .pflag_n(decc_parity3_c7_n), | |
841 | .parity (retbuf_ret_ecc_c7[27:21]), | |
842 | .din (retbuf_ret_data_c7[127:96]) | |
843 | ); | |
844 | ||
845 | // msb to the left, arrange this flop in 4 rows. | |
846 | l2t_decc_dp_msff_macro__dmsff_32x__stack_32r__width_32 ff_data_rtn_c8_127_96 | |
847 | ( | |
848 | .scan_in(ff_data_rtn_c8_127_96_scanin), | |
849 | .scan_out(ff_data_rtn_c8_127_96_scanout), | |
850 | .din (corr_data_c7[127:96]), // For example, 96,100,104 .. belong to the same row | |
851 | .clk (l2clk), | |
852 | .dout (decc_ret_data_c8[127:96]), | |
853 | .en (1'b1), | |
854 | .se(se), | |
855 | .siclk(siclk), | |
856 | .soclk(soclk), | |
857 | .pce_ov(pce_ov), | |
858 | .stop(stop) | |
859 | ||
860 | ||
861 | // interleave the bits | |
862 | ); | |
863 | ||
864 | l2t_ecc39a_dp bit78_116 | |
865 | ( | |
866 | .dout (corr_data_c7[95:64]), | |
867 | .cflag (decc_check2_c7[5:0]), | |
868 | .pflag (decc_parity2_c7), | |
869 | .pflag_n(decc_parity2_c7_n), | |
870 | .parity (retbuf_ret_ecc_c7[20:14]), | |
871 | .din (retbuf_ret_data_c7[95:64]) | |
872 | ); | |
873 | ||
874 | // msb to the left , arrange this flop in 4 rows. | |
875 | l2t_decc_dp_msff_macro__dmsff_32x__stack_32r__width_32 ff_data_rtn_c8_95_64 | |
876 | ( | |
877 | .scan_in(ff_data_rtn_c8_95_64_scanin), | |
878 | .scan_out(ff_data_rtn_c8_95_64_scanout), | |
879 | .din (corr_data_c7[95:64]), // For example, 64,68,8 .. belong to the same row | |
880 | .clk (l2clk), | |
881 | .dout (decc_ret_data_c8[95:64]), | |
882 | .en (1'b1), | |
883 | .se(se), | |
884 | .siclk(siclk), | |
885 | .soclk(soclk), | |
886 | .pce_ov(pce_ov), | |
887 | .stop(stop) | |
888 | ||
889 | ||
890 | // interleave the bits | |
891 | ) ; | |
892 | ||
893 | l2t_ecc39a_dp bit39_77 | |
894 | (.dout(corr_data_c7[63:32]), | |
895 | .cflag(decc_check1_c7[5:0]), | |
896 | .pflag(decc_parity1_c7), | |
897 | .pflag_n(decc_parity1_c7_n), | |
898 | .parity(retbuf_ret_ecc_c7[13:7]), | |
899 | .din(retbuf_ret_data_c7[63:32]) | |
900 | ) ; | |
901 | ||
902 | // msb to the left, arrange this flop in 4 rows. | |
903 | l2t_decc_dp_msff_macro__dmsff_32x__stack_32r__width_32 ff_data_rtn_c8_63_32 | |
904 | ( | |
905 | .scan_in(ff_data_rtn_c8_63_32_scanin), | |
906 | .scan_out(ff_data_rtn_c8_63_32_scanout), | |
907 | .din (corr_data_c7[63:32]), // For example, 32,36,40 .. belong to the same row | |
908 | .clk (l2clk), | |
909 | .dout (decc_ret_data_c8[63:32]), | |
910 | .en (1'b1), | |
911 | .se(se), | |
912 | .siclk(siclk), | |
913 | .soclk(soclk), | |
914 | .pce_ov(pce_ov), | |
915 | .stop(stop) | |
916 | ||
917 | ||
918 | // interleave the bits | |
919 | ) ; | |
920 | ||
921 | l2t_ecc39a_dp bit0_38 | |
922 | (.dout (corr_data_c7[31:0]), | |
923 | .cflag (decc_check0_c7[5:0]), | |
924 | .pflag (decc_parity0_c7), | |
925 | .pflag_n(decc_parity0_c7_n), | |
926 | .parity (retbuf_ret_ecc_c7[6:0]), | |
927 | .din (retbuf_ret_data_c7[31:0]) | |
928 | ) ; | |
929 | ||
930 | // msb to the left, arrange this flop in 4 rows. | |
931 | l2t_decc_dp_msff_macro__dmsff_32x__stack_32r__width_32 ff_data_rtn_c8_31_0 | |
932 | ( | |
933 | .scan_in(ff_data_rtn_c8_31_0_scanin), | |
934 | .scan_out(ff_data_rtn_c8_31_0_scanout), | |
935 | .din (corr_data_c7[31:0]), // For example, 32,36,40 .. belong to the same row | |
936 | .clk (l2clk), | |
937 | .dout (decc_ret_data_c8[31:0]), | |
938 | .en (1'b1), | |
939 | .se(se), | |
940 | .siclk(siclk), | |
941 | .soclk(soclk), | |
942 | .pce_ov(pce_ov), | |
943 | .stop(stop) | |
944 | ||
945 | ||
946 | // interleave the bits | |
947 | ) ; | |
948 | ||
949 | ||
950 | ////////////////////////// | |
951 | // SYNDROME to csr. | |
952 | ////////////////////////// | |
953 | assign error_synd_c7 = {decc_parity3_c7,decc_check3_c7[5:0], decc_parity2_c7,decc_check2_c7[5:0], | |
954 | decc_parity1_c7,decc_check1_c7[5:0], decc_parity0_c7,decc_check0_c7[5:0]} ; | |
955 | ||
956 | ||
957 | l2t_decc_dp_msff_macro__dmsff_32x__stack_38r__width_38 ff_error_synd_c8 | |
958 | ( | |
959 | .scan_in(ff_error_synd_c8_scanin), | |
960 | .scan_out(ff_error_synd_c8_scanout), | |
961 | .dout ({tag_spc_rd_vld_c7,filbuf_spc_rd_vld_c7,filbuf_spc_corr_err_c7, | |
962 | filbuf_spc_uncorr_err_c7,ret_err_c8_1,error_ceen_d1,error_nceen_d1, | |
963 | deccck_uncorr_err_c8,data_corr_err_c8,deccck_notdata_err_c8, | |
964 | error_synd_c8[27:0]}), | |
965 | .clk (l2clk), | |
966 | .din({tag_spc_rd_vld_c6,filbuf_spc_rd_vld_c6,filbuf_spc_corr_err_c6, | |
967 | filbuf_spc_uncorr_err_c6,ret_err_c7[1],csr_error_ceen,csr_error_nceen, | |
968 | data_uncorr_err_c7,data_corr_err_c7,data_notdata_err_c7,error_synd_c7[27:0]}), | |
969 | .en(1'b1), | |
970 | .se(se), | |
971 | .siclk(siclk), | |
972 | .soclk(soclk), | |
973 | .pce_ov(pce_ov), | |
974 | .stop(stop) | |
975 | ) ; | |
976 | ||
977 | l2t_decc_dp_msff_macro__dmsff_32x__dmsff_32x__stack_30r__width_29 ff_lda_syndrome_c9 | |
978 | ( | |
979 | .scan_in(ff_lda_syndrome_c9_scanin), | |
980 | .scan_out(ff_lda_syndrome_c9_scanout), | |
981 | .din ({deccck_dword_sel_c7,error_synd_c8[27:0]}), | |
982 | .clk (l2clk), | |
983 | .dout ({dword_sel_c8,decc_lda_syndrome_c9[27:0]}), | |
984 | .en (1'b1), | |
985 | .se(se), | |
986 | .siclk(siclk), | |
987 | .soclk(soclk), | |
988 | .pce_ov(pce_ov), | |
989 | .stop(stop) | |
990 | ) ; | |
991 | ||
992 | //inv_macro inv_added (width=1) | |
993 | // ( | |
994 | // .dout (dword_sel_c8_n), | |
995 | // .din (dword_sel_c8) | |
996 | // ); | |
997 | ||
998 | l2t_decc_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_32r__width_32 ret_mux | |
999 | (.dout (decc_arbdp_data_c8[63:32]), | |
1000 | .din0 (decc_ret_data_c8[63:32]), | |
1001 | .din1 (decc_ret_data_c8[127:96]), | |
1002 | .sel0 (dword_sel_c8) | |
1003 | // .sel1 (dword_sel_c8) | |
1004 | ) ; | |
1005 | ||
1006 | l2t_decc_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_32r__width_32 ret_mux1 | |
1007 | (.dout (decc_arbdp_data_c8[31:0]), | |
1008 | .din0 (decc_ret_data_c8[31:0]), | |
1009 | .din1 (decc_ret_data_c8[95:64]), | |
1010 | .sel0 (dword_sel_c8) | |
1011 | //.sel0 (dword_sel_c8_n) | |
1012 | ) ; | |
1013 | ||
1014 | assign data_word1_c7 = {retbuf_ret_data_c7[95:64], retbuf_ret_ecc_c7[20:14]} ; | |
1015 | assign data_word0_c7 = {retbuf_ret_data_c7[127:96],retbuf_ret_ecc_c7[27:21]} ; | |
1016 | ||
1017 | ||
1018 | //inv_macro mux_rgt_diag_inv_slice (width=1) | |
1019 | // ( | |
1020 | // .dout (deccck_sel_higher_word_c7_n), | |
1021 | // .din (deccck_sel_higher_word_c7) | |
1022 | // ); | |
1023 | // | |
1024 | //mux_macro mux_left_diag_out (width=39,ports=2,mux=aonpe,stack=39r,dmux=8x) | |
1025 | // ( | |
1026 | // .dout (left_diag_out_c7[38:0]), | |
1027 | // .din0 (data_word0_c7[38:0]), | |
1028 | // .sel0 (deccck_sel_higher_word_c7_n), | |
1029 | // .din1 (data_word1_c7[38:0]), | |
1030 | // .sel1 (deccck_sel_higher_word_c7) | |
1031 | // ) ; | |
1032 | // | |
1033 | assign data_word3_c7 = {retbuf_ret_data_c7[31:0], retbuf_ret_ecc_c7[6:0]} ; | |
1034 | assign data_word2_c7 = {retbuf_ret_data_c7[63:32], retbuf_ret_ecc_c7[13:7]} ; | |
1035 | ||
1036 | // | |
1037 | //mux_macro mux_rgt_diag_out (width=39,ports=2,mux=aonpe,stack=39r,dmux=8x) | |
1038 | // ( | |
1039 | // .dout (rgt_diag_out_c7[38:0]), | |
1040 | // .din0 (data_word2_c7[38:0]), | |
1041 | // .din1 (data_word3_c7[38:0]), | |
1042 | // .sel0 (deccck_sel_higher_word_c7_n), | |
1043 | // .sel1 (deccck_sel_higher_word_c7) | |
1044 | // ) ; | |
1045 | // | |
1046 | //inv_macro mux_diag_out_inv_slice (width=1) | |
1047 | // ( | |
1048 | // .dout (deccck_sel_higher_dword_c7_n), | |
1049 | // .din (deccck_sel_higher_dword_c7) | |
1050 | // ); | |
1051 | // | |
1052 | //mux_macro mux_diag_out (width=39,ports=2,mux=aonpe,stack=39r,dmux=8x) | |
1053 | // ( | |
1054 | // .dout (decc_ret_diag_data_c7[38:0]), | |
1055 | // .din0 (left_diag_out_c7[38:0]), | |
1056 | // .din1 (rgt_diag_out_c7[38:0]), | |
1057 | // .sel0 (deccck_sel_higher_dword_c7_n), | |
1058 | // .sel1 (deccck_sel_higher_dword_c7) | |
1059 | // ) ; | |
1060 | ||
1061 | l2t_decc_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_39r__width_39 mux_diag_out // ATPG cleanup | |
1062 | ( | |
1063 | .dout (decc_ret_diag_data_c7[38:0]), | |
1064 | .din0 (data_word0_c7[38:0]), | |
1065 | .din1 (data_word1_c7[38:0]), | |
1066 | .din2 (data_word2_c7[38:0]), | |
1067 | .din3 (data_word3_c7[38:0]), | |
1068 | .sel0 (deccck_muxsel_diag_out_c7[0]), | |
1069 | .sel1 (deccck_muxsel_diag_out_c7[1]), | |
1070 | .sel2 (deccck_muxsel_diag_out_c7[2]), | |
1071 | .muxtst(muxtst), | |
1072 | .test(test) | |
1073 | ) ; | |
1074 | ||
1075 | l2t_decc_dp_mux_macro__mux_aope__ports_2__stack_39r__width_39 mux_data_tag_dmo_data | |
1076 | ( | |
1077 | .dout (mbist_dmo_data_out[38:0]), | |
1078 | .din0 ({11'b0,tagd_evict_tag_c3[27:0]}), | |
1079 | .din1 (decc_ret_diag_data_c7[38:0]), | |
1080 | .sel0 (tcu_l2t_tag_or_data_sel) | |
1081 | ); | |
1082 | ||
1083 | l2t_decc_dp_cmp_macro__width_8 cmp_mbist_data0 | |
1084 | ( | |
1085 | .dout (mbist_l2data_fail0), | |
1086 | .din0 ({1'b0,decc_ret_diag_data_c7[38:32]}), | |
1087 | .din1 ({1'b0,mbist_write_data_c6[6:0]}) | |
1088 | ); | |
1089 | ||
1090 | l2t_decc_dp_cmp_macro__width_32 cmp_mbist_data1 | |
1091 | ( | |
1092 | .dout (mbist_l2data_fail1), | |
1093 | .din0 (decc_ret_diag_data_c7[31:0]), | |
1094 | .din1 ({4{mbist_write_data_c6[7:0]}}) | |
1095 | ); | |
1096 | ||
1097 | //assign mbist_l2data_fail = mbist_l2data_fail0 & mbist_l2data_fail1; | |
1098 | ||
1099 | l2t_decc_dp_and_macro__width_1 and_mbist_l2data_fail | |
1100 | ( | |
1101 | .dout (mbist_l2data_fail_fnl), | |
1102 | .din0 (mbist_l2data_fail0), | |
1103 | .din1 (mbist_l2data_fail1) | |
1104 | ); | |
1105 | ||
1106 | l2t_decc_dp_mux_macro__mux_aonpe__stack_2r__width_1 mux_mbist_fail | |
1107 | ( | |
1108 | .dout (mbist_l2data_fail_w), | |
1109 | .din0 (mbist_l2data_fail_fnl), | |
1110 | .din1 (1'b1), | |
1111 | .sel0 (mbist_l2d_write_c6_n), | |
1112 | .sel1 (mbist_l2d_write_c6) | |
1113 | ); | |
1114 | ||
1115 | l2t_decc_dp_inv_macro__dinv_32x__width_1 inv_mbist_l2d_write_c7 | |
1116 | ( | |
1117 | .dout (mbist_l2d_write_c6_n), | |
1118 | .din (mbist_l2d_write_c6) | |
1119 | ); | |
1120 | ||
1121 | l2t_decc_dp_msff_macro__dmsff_32x__stack_38r__width_29 ff_fame_mbist_flops_0 | |
1122 | ( | |
1123 | .scan_in(ff_fame_mbist_flops_0_scanin), | |
1124 | .scan_out(ff_fame_mbist_flops_0_scanout), | |
1125 | .din ({ mbist_write_data_c4[7:0], | |
1126 | mbist_write_data_c5[7:0], | |
1127 | mbist_write_data_c52[7:0], | |
1128 | mbist_l2data_fail_w, | |
1129 | mbist_l2d_write_c3, | |
1130 | mbist_l2d_write_c4, | |
1131 | mbist_l2d_write_c5, | |
1132 | mbist_l2d_write_c52}), | |
1133 | .clk (l2clk), | |
1134 | .dout({ mbist_write_data_c5[7:0], | |
1135 | mbist_write_data_c52[7:0], | |
1136 | mbist_write_data_c6[7:0], | |
1137 | mbist_l2data_fail, | |
1138 | mbist_l2d_write_c4, | |
1139 | mbist_l2d_write_c5, | |
1140 | mbist_l2d_write_c52, | |
1141 | mbist_l2d_write_c6}), | |
1142 | .en(1'b1), | |
1143 | .se(se), | |
1144 | .siclk(siclk), | |
1145 | .soclk(soclk), | |
1146 | .pce_ov(pce_ov), | |
1147 | .stop(stop) | |
1148 | ) ; | |
1149 | ||
1150 | ||
1151 | ||
1152 | l2t_decc_dp_msff_macro__dmsff_32x__stack_39r__width_35 ff_fame_mbist_flops | |
1153 | ( | |
1154 | .scan_in(ff_fame_mbist_flops_scanin), | |
1155 | .scan_out(ff_fame_mbist_flops_scanout), | |
1156 | .din ({ mbist_write_data[7:0], | |
1157 | mbist_write_data_c1[7:0], | |
1158 | mbist_write_data_c2[7:0], | |
1159 | mbist_l2d_write, | |
1160 | mbist_l2d_write_c1, | |
1161 | mbist_l2d_write_c2, | |
1162 | mbist_write_data_c3[7:0]}), | |
1163 | .clk (l2clk), | |
1164 | .dout({ mbist_write_data_c1[7:0], | |
1165 | mbist_write_data_c2[7:0], | |
1166 | mbist_write_data_c3[7:0], | |
1167 | mbist_l2d_write_c1, | |
1168 | mbist_l2d_write_c2, | |
1169 | mbist_l2d_write_c3, | |
1170 | mbist_write_data_c4[7:0]}), | |
1171 | .en(1'b1), | |
1172 | .se(se), | |
1173 | .siclk(siclk), | |
1174 | .soclk(soclk), | |
1175 | .pce_ov(pce_ov), | |
1176 | .stop(stop) | |
1177 | ) ; | |
1178 | ||
1179 | ||
1180 | ||
1181 | ||
1182 | ///////////////////////////////////////////////////////////////////////// | |
1183 | // Added invertors to drive to output que // | |
1184 | ///////////////////////////////////////////////////////////////////////// | |
1185 | assign decc_ret_data_c7[127:0] = corr_data_c7[127:0] ; | |
1186 | ||
1187 | ||
1188 | ||
1189 | //////////////////////////////////////// | |
1190 | ||
1191 | ||
1192 | assign retbuf_ret_data_c7[127:0] = ret_data_c7_buf[127:0]; | |
1193 | assign retbuf_ret_ecc_c7[27:0] = ret_ecc_c7_buf[27:0]; | |
1194 | assign {ret_data_c6[31:0], ret_ecc_c6[6:0]} = l2d_l2t_decc_c6[38:0]; | |
1195 | assign {ret_data_c6[63:32], ret_ecc_c6[13:7]} = l2d_l2t_decc_c6[77:39]; | |
1196 | assign {ret_data_c6[95:64], ret_ecc_c6[20:14]} = l2d_l2t_decc_c6[116:78]; | |
1197 | assign {ret_data_c6[127:96], ret_ecc_c6[27:21]} = l2d_l2t_decc_c6[155:117]; | |
1198 | ||
1199 | // arrange these flops in 16 rows and 10 columns | |
1200 | // row0 ->{ data[2:0],ecc[6:0]} | |
1201 | // row1 ->{ data[12:3]} | |
1202 | // row2 ->{ data[22:13]} | |
1203 | // row3 ->{ data[31:23]} | |
1204 | // and so 0n. Buffer the outputs of each | |
1205 | // bit with a 40x buffer/inverter. | |
1206 | ||
1207 | l2t_decc_dp_msff_macro__dmsff_32x__stack_39r__width_39 ff_data_rtn_c7_1split1 | |
1208 | ( | |
1209 | .scan_in(ff_data_rtn_c7_1split1_scanin), | |
1210 | .scan_out(ff_data_rtn_c7_1split1_scanout), | |
1211 | .dout ({ret_ecc_c7_buf[27:21],ret_data_c7_buf[127:96]}), | |
1212 | .din ({ret_ecc_c6[27:21],ret_data_c6[127:96]}), | |
1213 | .clk (l2clk), | |
1214 | .en (1'b1), | |
1215 | .se(se), | |
1216 | .siclk(siclk), | |
1217 | .soclk(soclk), | |
1218 | .pce_ov(pce_ov), | |
1219 | .stop(stop) | |
1220 | ) ; | |
1221 | ||
1222 | l2t_decc_dp_msff_macro__dmsff_32x__stack_39r__width_39 ff_data_rtn_c7_1split2 | |
1223 | ( | |
1224 | .scan_in(ff_data_rtn_c7_1split2_scanin), | |
1225 | .scan_out(ff_data_rtn_c7_1split2_scanout), | |
1226 | .dout ({ret_ecc_c7_buf[20:14],ret_data_c7_buf[95:64]}), | |
1227 | .din ({ret_ecc_c6[20:14],ret_data_c6[95:64]}), | |
1228 | .clk (l2clk), | |
1229 | .en (1'b1), | |
1230 | .se(se), | |
1231 | .siclk(siclk), | |
1232 | .soclk(soclk), | |
1233 | .pce_ov(pce_ov), | |
1234 | .stop(stop) | |
1235 | ) ; | |
1236 | ||
1237 | l2t_decc_dp_msff_macro__dmsff_32x__stack_39r__width_39 ff_data_rtn_c7_1split3 | |
1238 | ( | |
1239 | .scan_in(ff_data_rtn_c7_1split3_scanin), | |
1240 | .scan_out(ff_data_rtn_c7_1split3_scanout), | |
1241 | .dout ({ret_ecc_c7_buf[13:7],ret_data_c7_buf[63:32]}), | |
1242 | .din ({ret_ecc_c6[13:7],ret_data_c6[63:32]}), | |
1243 | .clk (l2clk), | |
1244 | .en (1'b1), | |
1245 | .se(se), | |
1246 | .siclk(siclk), | |
1247 | .soclk(soclk), | |
1248 | .pce_ov(pce_ov), | |
1249 | .stop(stop) | |
1250 | ) ; | |
1251 | ||
1252 | l2t_decc_dp_msff_macro__dmsff_32x__stack_39r__width_39 ff_data_rtn_c7_1split4 | |
1253 | ( | |
1254 | .scan_in(ff_data_rtn_c7_1split4_scanin), | |
1255 | .scan_out(ff_data_rtn_c7_1split4_scanout), | |
1256 | .dout ({ret_ecc_c7_buf[6:0],ret_data_c7_buf[31:0]}), | |
1257 | .din ({ret_ecc_c6[6:0],ret_data_c6[31:0]}), | |
1258 | .clk (l2clk), | |
1259 | .en (1'b1), | |
1260 | .se(se), | |
1261 | .siclk(siclk), | |
1262 | .soclk(soclk), | |
1263 | .pce_ov(pce_ov), | |
1264 | .stop(stop) | |
1265 | ) ; | |
1266 | ||
1267 | ||
1268 | // fixscan start: | |
1269 | assign ff_data_rtn_c8_127_96_scanin = scan_in ; | |
1270 | assign ff_data_rtn_c8_95_64_scanin = ff_data_rtn_c8_127_96_scanout; | |
1271 | assign ff_data_rtn_c8_63_32_scanin = ff_data_rtn_c8_95_64_scanout; | |
1272 | assign ff_data_rtn_c8_31_0_scanin = ff_data_rtn_c8_63_32_scanout; | |
1273 | assign ff_error_synd_c8_scanin = ff_data_rtn_c8_31_0_scanout; | |
1274 | assign ff_lda_syndrome_c9_scanin = ff_error_synd_c8_scanout ; | |
1275 | assign ff_fame_mbist_flops_0_scanin = ff_lda_syndrome_c9_scanout; | |
1276 | assign ff_fame_mbist_flops_scanin = ff_fame_mbist_flops_0_scanout; | |
1277 | assign ff_data_rtn_c7_1split1_scanin = ff_fame_mbist_flops_scanout; | |
1278 | assign ff_data_rtn_c7_1split2_scanin = ff_data_rtn_c7_1split1_scanout; | |
1279 | assign ff_data_rtn_c7_1split3_scanin = ff_data_rtn_c7_1split2_scanout; | |
1280 | assign ff_data_rtn_c7_1split4_scanin = ff_data_rtn_c7_1split3_scanout; | |
1281 | assign scan_out = ff_data_rtn_c7_1split4_scanout; | |
1282 | // fixscan end: | |
1283 | endmodule | |
1284 | ||
1285 | ||
1286 | // | |
1287 | // invert macro | |
1288 | // | |
1289 | // | |
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | module l2t_decc_dp_inv_macro__dinv_32x__stack_32r__width_24 ( | |
1296 | din, | |
1297 | dout); | |
1298 | input [23:0] din; | |
1299 | output [23:0] dout; | |
1300 | ||
1301 | ||
1302 | ||
1303 | ||
1304 | ||
1305 | ||
1306 | inv #(24) d0_0 ( | |
1307 | .in(din[23:0]), | |
1308 | .out(dout[23:0]) | |
1309 | ); | |
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | ||
1316 | ||
1317 | ||
1318 | ||
1319 | endmodule | |
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | // | |
1326 | // nor macro for ports = 2,3 | |
1327 | // | |
1328 | // | |
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | module l2t_decc_dp_nor_macro__dnor_16x__ports_2__width_3 ( | |
1335 | din0, | |
1336 | din1, | |
1337 | dout); | |
1338 | input [2:0] din0; | |
1339 | input [2:0] din1; | |
1340 | output [2:0] dout; | |
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | nor2 #(3) d0_0 ( | |
1348 | .in0(din0[2:0]), | |
1349 | .in1(din1[2:0]), | |
1350 | .out(dout[2:0]) | |
1351 | ); | |
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | endmodule | |
1360 | ||
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | // | |
1366 | // nand macro for ports = 2,3,4 | |
1367 | // | |
1368 | // | |
1369 | ||
1370 | ||
1371 | ||
1372 | ||
1373 | ||
1374 | module l2t_decc_dp_nand_macro__dnand_24x__ports_3__width_4 ( | |
1375 | din0, | |
1376 | din1, | |
1377 | din2, | |
1378 | dout); | |
1379 | input [3:0] din0; | |
1380 | input [3:0] din1; | |
1381 | input [3:0] din2; | |
1382 | output [3:0] dout; | |
1383 | ||
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | ||
1389 | nand3 #(4) d0_0 ( | |
1390 | .in0(din0[3:0]), | |
1391 | .in1(din1[3:0]), | |
1392 | .in2(din2[3:0]), | |
1393 | .out(dout[3:0]) | |
1394 | ); | |
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | endmodule | |
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | // | |
1411 | // invert macro | |
1412 | // | |
1413 | // | |
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | module l2t_decc_dp_inv_macro__dinv_32x__width_4 ( | |
1420 | din, | |
1421 | dout); | |
1422 | input [3:0] din; | |
1423 | output [3:0] dout; | |
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | ||
1429 | ||
1430 | inv #(4) d0_0 ( | |
1431 | .in(din[3:0]), | |
1432 | .out(dout[3:0]) | |
1433 | ); | |
1434 | ||
1435 | ||
1436 | ||
1437 | ||
1438 | ||
1439 | ||
1440 | ||
1441 | ||
1442 | ||
1443 | endmodule | |
1444 | ||
1445 | ||
1446 | ||
1447 | ||
1448 | ||
1449 | // | |
1450 | // nor macro for ports = 2,3 | |
1451 | // | |
1452 | // | |
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | module l2t_decc_dp_nor_macro__dnor_16x__width_4 ( | |
1459 | din0, | |
1460 | din1, | |
1461 | dout); | |
1462 | input [3:0] din0; | |
1463 | input [3:0] din1; | |
1464 | output [3:0] dout; | |
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | nor2 #(4) d0_0 ( | |
1472 | .in0(din0[3:0]), | |
1473 | .in1(din1[3:0]), | |
1474 | .out(dout[3:0]) | |
1475 | ); | |
1476 | ||
1477 | ||
1478 | ||
1479 | ||
1480 | ||
1481 | ||
1482 | ||
1483 | endmodule | |
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | ||
1489 | // | |
1490 | // buff macro | |
1491 | // | |
1492 | // | |
1493 | ||
1494 | ||
1495 | ||
1496 | ||
1497 | ||
1498 | module l2t_decc_dp_buff_macro__dbuff_32x__width_5 ( | |
1499 | din, | |
1500 | dout); | |
1501 | input [4:0] din; | |
1502 | output [4:0] dout; | |
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | buff #(5) d0_0 ( | |
1510 | .in(din[4:0]), | |
1511 | .out(dout[4:0]) | |
1512 | ); | |
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | endmodule | |
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | // | |
1528 | // nor macro for ports = 2,3 | |
1529 | // | |
1530 | // | |
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | module l2t_decc_dp_nor_macro__dnor_16x__width_2 ( | |
1537 | din0, | |
1538 | din1, | |
1539 | dout); | |
1540 | input [1:0] din0; | |
1541 | input [1:0] din1; | |
1542 | output [1:0] dout; | |
1543 | ||
1544 | ||
1545 | ||
1546 | ||
1547 | ||
1548 | ||
1549 | nor2 #(2) d0_0 ( | |
1550 | .in0(din0[1:0]), | |
1551 | .in1(din1[1:0]), | |
1552 | .out(dout[1:0]) | |
1553 | ); | |
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | ||
1559 | ||
1560 | ||
1561 | endmodule | |
1562 | ||
1563 | ||
1564 | ||
1565 | ||
1566 | ||
1567 | // | |
1568 | // nand macro for ports = 2,3,4 | |
1569 | // | |
1570 | // | |
1571 | ||
1572 | ||
1573 | ||
1574 | ||
1575 | ||
1576 | module l2t_decc_dp_nand_macro__dnand_24x__width_1 ( | |
1577 | din0, | |
1578 | din1, | |
1579 | dout); | |
1580 | input [0:0] din0; | |
1581 | input [0:0] din1; | |
1582 | output [0:0] dout; | |
1583 | ||
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | ||
1589 | nand2 #(1) d0_0 ( | |
1590 | .in0(din0[0:0]), | |
1591 | .in1(din1[0:0]), | |
1592 | .out(dout[0:0]) | |
1593 | ); | |
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | endmodule | |
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | // | |
1610 | // nor macro for ports = 2,3 | |
1611 | // | |
1612 | // | |
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | ||
1618 | module l2t_decc_dp_nor_macro__dnor_16x__ports_2__width_4 ( | |
1619 | din0, | |
1620 | din1, | |
1621 | dout); | |
1622 | input [3:0] din0; | |
1623 | input [3:0] din1; | |
1624 | output [3:0] dout; | |
1625 | ||
1626 | ||
1627 | ||
1628 | ||
1629 | ||
1630 | ||
1631 | nor2 #(4) d0_0 ( | |
1632 | .in0(din0[3:0]), | |
1633 | .in1(din1[3:0]), | |
1634 | .out(dout[3:0]) | |
1635 | ); | |
1636 | ||
1637 | ||
1638 | ||
1639 | ||
1640 | ||
1641 | ||
1642 | ||
1643 | endmodule | |
1644 | ||
1645 | ||
1646 | ||
1647 | ||
1648 | ||
1649 | // | |
1650 | // nand macro for ports = 2,3,4 | |
1651 | // | |
1652 | // | |
1653 | ||
1654 | ||
1655 | ||
1656 | ||
1657 | ||
1658 | module l2t_decc_dp_nand_macro__dnand_16x__ports_3__width_8 ( | |
1659 | din0, | |
1660 | din1, | |
1661 | din2, | |
1662 | dout); | |
1663 | input [7:0] din0; | |
1664 | input [7:0] din1; | |
1665 | input [7:0] din2; | |
1666 | output [7:0] dout; | |
1667 | ||
1668 | ||
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | nand3 #(8) d0_0 ( | |
1674 | .in0(din0[7:0]), | |
1675 | .in1(din1[7:0]), | |
1676 | .in2(din2[7:0]), | |
1677 | .out(dout[7:0]) | |
1678 | ); | |
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | ||
1684 | ||
1685 | ||
1686 | ||
1687 | ||
1688 | endmodule | |
1689 | ||
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | // | |
1695 | // nand macro for ports = 2,3,4 | |
1696 | // | |
1697 | // | |
1698 | ||
1699 | ||
1700 | ||
1701 | ||
1702 | ||
1703 | module l2t_decc_dp_nand_macro__dnand_16x__width_2 ( | |
1704 | din0, | |
1705 | din1, | |
1706 | dout); | |
1707 | input [1:0] din0; | |
1708 | input [1:0] din1; | |
1709 | output [1:0] dout; | |
1710 | ||
1711 | ||
1712 | ||
1713 | ||
1714 | ||
1715 | ||
1716 | nand2 #(2) d0_0 ( | |
1717 | .in0(din0[1:0]), | |
1718 | .in1(din1[1:0]), | |
1719 | .out(dout[1:0]) | |
1720 | ); | |
1721 | ||
1722 | ||
1723 | ||
1724 | ||
1725 | ||
1726 | ||
1727 | ||
1728 | ||
1729 | ||
1730 | endmodule | |
1731 | ||
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | // | |
1737 | // invert macro | |
1738 | // | |
1739 | // | |
1740 | ||
1741 | ||
1742 | ||
1743 | ||
1744 | ||
1745 | module l2t_decc_dp_inv_macro__dinv_24x__stack_2r__width_2 ( | |
1746 | din, | |
1747 | dout); | |
1748 | input [1:0] din; | |
1749 | output [1:0] dout; | |
1750 | ||
1751 | ||
1752 | ||
1753 | ||
1754 | ||
1755 | ||
1756 | inv #(2) d0_0 ( | |
1757 | .in(din[1:0]), | |
1758 | .out(dout[1:0]) | |
1759 | ); | |
1760 | ||
1761 | ||
1762 | ||
1763 | ||
1764 | ||
1765 | ||
1766 | ||
1767 | ||
1768 | ||
1769 | endmodule | |
1770 | ||
1771 | ||
1772 | ||
1773 | ||
1774 | ||
1775 | // | |
1776 | // nand macro for ports = 2,3,4 | |
1777 | // | |
1778 | // | |
1779 | ||
1780 | ||
1781 | ||
1782 | ||
1783 | ||
1784 | module l2t_decc_dp_nand_macro__dnand_32x__width_1 ( | |
1785 | din0, | |
1786 | din1, | |
1787 | dout); | |
1788 | input [0:0] din0; | |
1789 | input [0:0] din1; | |
1790 | output [0:0] dout; | |
1791 | ||
1792 | ||
1793 | ||
1794 | ||
1795 | ||
1796 | ||
1797 | nand2 #(1) d0_0 ( | |
1798 | .in0(din0[0:0]), | |
1799 | .in1(din1[0:0]), | |
1800 | .out(dout[0:0]) | |
1801 | ); | |
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | endmodule | |
1812 | ||
1813 | ||
1814 | ||
1815 | ||
1816 | ||
1817 | // | |
1818 | // nand macro for ports = 2,3,4 | |
1819 | // | |
1820 | // | |
1821 | ||
1822 | ||
1823 | ||
1824 | ||
1825 | ||
1826 | module l2t_decc_dp_nand_macro__ports_3__width_1 ( | |
1827 | din0, | |
1828 | din1, | |
1829 | din2, | |
1830 | dout); | |
1831 | input [0:0] din0; | |
1832 | input [0:0] din1; | |
1833 | input [0:0] din2; | |
1834 | output [0:0] dout; | |
1835 | ||
1836 | ||
1837 | ||
1838 | ||
1839 | ||
1840 | ||
1841 | nand3 #(1) d0_0 ( | |
1842 | .in0(din0[0:0]), | |
1843 | .in1(din1[0:0]), | |
1844 | .in2(din2[0:0]), | |
1845 | .out(dout[0:0]) | |
1846 | ); | |
1847 | ||
1848 | ||
1849 | ||
1850 | ||
1851 | ||
1852 | ||
1853 | ||
1854 | ||
1855 | ||
1856 | endmodule | |
1857 | ||
1858 | ||
1859 | ||
1860 | ||
1861 | ||
1862 | // | |
1863 | // nand macro for ports = 2,3,4 | |
1864 | // | |
1865 | // | |
1866 | ||
1867 | ||
1868 | ||
1869 | ||
1870 | ||
1871 | module l2t_decc_dp_nand_macro__dnand_16x__width_1 ( | |
1872 | din0, | |
1873 | din1, | |
1874 | dout); | |
1875 | input [0:0] din0; | |
1876 | input [0:0] din1; | |
1877 | output [0:0] dout; | |
1878 | ||
1879 | ||
1880 | ||
1881 | ||
1882 | ||
1883 | ||
1884 | nand2 #(1) d0_0 ( | |
1885 | .in0(din0[0:0]), | |
1886 | .in1(din1[0:0]), | |
1887 | .out(dout[0:0]) | |
1888 | ); | |
1889 | ||
1890 | ||
1891 | ||
1892 | ||
1893 | ||
1894 | ||
1895 | ||
1896 | ||
1897 | ||
1898 | endmodule | |
1899 | ||
1900 | ||
1901 | ||
1902 | ||
1903 | ||
1904 | // | |
1905 | // invert macro | |
1906 | // | |
1907 | // | |
1908 | ||
1909 | ||
1910 | ||
1911 | ||
1912 | ||
1913 | module l2t_decc_dp_inv_macro__dinv_32x__width_2 ( | |
1914 | din, | |
1915 | dout); | |
1916 | input [1:0] din; | |
1917 | output [1:0] dout; | |
1918 | ||
1919 | ||
1920 | ||
1921 | ||
1922 | ||
1923 | ||
1924 | inv #(2) d0_0 ( | |
1925 | .in(din[1:0]), | |
1926 | .out(dout[1:0]) | |
1927 | ); | |
1928 | ||
1929 | ||
1930 | ||
1931 | ||
1932 | ||
1933 | ||
1934 | ||
1935 | ||
1936 | ||
1937 | endmodule | |
1938 | ||
1939 | ||
1940 | ||
1941 | ||
1942 | ||
1943 | // | |
1944 | // nand macro for ports = 2,3,4 | |
1945 | // | |
1946 | // | |
1947 | ||
1948 | ||
1949 | ||
1950 | ||
1951 | ||
1952 | module l2t_decc_dp_nand_macro__dnand_16x__ports_3__width_1 ( | |
1953 | din0, | |
1954 | din1, | |
1955 | din2, | |
1956 | dout); | |
1957 | input [0:0] din0; | |
1958 | input [0:0] din1; | |
1959 | input [0:0] din2; | |
1960 | output [0:0] dout; | |
1961 | ||
1962 | ||
1963 | ||
1964 | ||
1965 | ||
1966 | ||
1967 | nand3 #(1) d0_0 ( | |
1968 | .in0(din0[0:0]), | |
1969 | .in1(din1[0:0]), | |
1970 | .in2(din2[0:0]), | |
1971 | .out(dout[0:0]) | |
1972 | ); | |
1973 | ||
1974 | ||
1975 | ||
1976 | ||
1977 | ||
1978 | ||
1979 | ||
1980 | ||
1981 | ||
1982 | endmodule | |
1983 | ||
1984 | ||
1985 | ||
1986 | ||
1987 | ||
1988 | // | |
1989 | // nand macro for ports = 2,3,4 | |
1990 | // | |
1991 | // | |
1992 | ||
1993 | ||
1994 | ||
1995 | ||
1996 | ||
1997 | module l2t_decc_dp_nand_macro__width_1 ( | |
1998 | din0, | |
1999 | din1, | |
2000 | dout); | |
2001 | input [0:0] din0; | |
2002 | input [0:0] din1; | |
2003 | output [0:0] dout; | |
2004 | ||
2005 | ||
2006 | ||
2007 | ||
2008 | ||
2009 | ||
2010 | nand2 #(1) d0_0 ( | |
2011 | .in0(din0[0:0]), | |
2012 | .in1(din1[0:0]), | |
2013 | .out(dout[0:0]) | |
2014 | ); | |
2015 | ||
2016 | ||
2017 | ||
2018 | ||
2019 | ||
2020 | ||
2021 | ||
2022 | ||
2023 | ||
2024 | endmodule | |
2025 | ||
2026 | ||
2027 | ||
2028 | ||
2029 | ||
2030 | // | |
2031 | // nand macro for ports = 2,3,4 | |
2032 | // | |
2033 | // | |
2034 | ||
2035 | ||
2036 | ||
2037 | ||
2038 | ||
2039 | module l2t_decc_dp_nand_macro__dnand_32x__ports_2__width_1 ( | |
2040 | din0, | |
2041 | din1, | |
2042 | dout); | |
2043 | input [0:0] din0; | |
2044 | input [0:0] din1; | |
2045 | output [0:0] dout; | |
2046 | ||
2047 | ||
2048 | ||
2049 | ||
2050 | ||
2051 | ||
2052 | nand2 #(1) d0_0 ( | |
2053 | .in0(din0[0:0]), | |
2054 | .in1(din1[0:0]), | |
2055 | .out(dout[0:0]) | |
2056 | ); | |
2057 | ||
2058 | ||
2059 | ||
2060 | ||
2061 | ||
2062 | ||
2063 | ||
2064 | ||
2065 | ||
2066 | endmodule | |
2067 | ||
2068 | ||
2069 | ||
2070 | ||
2071 | ||
2072 | // | |
2073 | // invert macro | |
2074 | // | |
2075 | // | |
2076 | ||
2077 | ||
2078 | ||
2079 | ||
2080 | ||
2081 | module l2t_decc_dp_inv_macro__dinv_32x__width_1 ( | |
2082 | din, | |
2083 | dout); | |
2084 | input [0:0] din; | |
2085 | output [0:0] dout; | |
2086 | ||
2087 | ||
2088 | ||
2089 | ||
2090 | ||
2091 | ||
2092 | inv #(1) d0_0 ( | |
2093 | .in(din[0:0]), | |
2094 | .out(dout[0:0]) | |
2095 | ); | |
2096 | ||
2097 | ||
2098 | ||
2099 | ||
2100 | ||
2101 | ||
2102 | ||
2103 | ||
2104 | ||
2105 | endmodule | |
2106 | ||
2107 | ||
2108 | ||
2109 | ||
2110 | ||
2111 | // | |
2112 | // nor macro for ports = 2,3 | |
2113 | // | |
2114 | // | |
2115 | ||
2116 | ||
2117 | ||
2118 | ||
2119 | ||
2120 | module l2t_decc_dp_nor_macro__dnor_16x__width_1 ( | |
2121 | din0, | |
2122 | din1, | |
2123 | dout); | |
2124 | input [0:0] din0; | |
2125 | input [0:0] din1; | |
2126 | output [0:0] dout; | |
2127 | ||
2128 | ||
2129 | ||
2130 | ||
2131 | ||
2132 | ||
2133 | nor2 #(1) d0_0 ( | |
2134 | .in0(din0[0:0]), | |
2135 | .in1(din1[0:0]), | |
2136 | .out(dout[0:0]) | |
2137 | ); | |
2138 | ||
2139 | ||
2140 | ||
2141 | ||
2142 | ||
2143 | ||
2144 | ||
2145 | endmodule | |
2146 | ||
2147 | ||
2148 | ||
2149 | ||
2150 | ||
2151 | // | |
2152 | // nand macro for ports = 2,3,4 | |
2153 | // | |
2154 | // | |
2155 | ||
2156 | ||
2157 | ||
2158 | ||
2159 | ||
2160 | module l2t_decc_dp_nand_macro__dnand_24x__ports_3__width_1 ( | |
2161 | din0, | |
2162 | din1, | |
2163 | din2, | |
2164 | dout); | |
2165 | input [0:0] din0; | |
2166 | input [0:0] din1; | |
2167 | input [0:0] din2; | |
2168 | output [0:0] dout; | |
2169 | ||
2170 | ||
2171 | ||
2172 | ||
2173 | ||
2174 | ||
2175 | nand3 #(1) d0_0 ( | |
2176 | .in0(din0[0:0]), | |
2177 | .in1(din1[0:0]), | |
2178 | .in2(din2[0:0]), | |
2179 | .out(dout[0:0]) | |
2180 | ); | |
2181 | ||
2182 | ||
2183 | ||
2184 | ||
2185 | ||
2186 | ||
2187 | ||
2188 | ||
2189 | ||
2190 | endmodule | |
2191 | ||
2192 | ||
2193 | ||
2194 | ||
2195 | ||
2196 | // | |
2197 | // buff macro | |
2198 | // | |
2199 | // | |
2200 | ||
2201 | ||
2202 | ||
2203 | ||
2204 | ||
2205 | module l2t_decc_dp_buff_macro__dbuff_32x__width_1 ( | |
2206 | din, | |
2207 | dout); | |
2208 | input [0:0] din; | |
2209 | output [0:0] dout; | |
2210 | ||
2211 | ||
2212 | ||
2213 | ||
2214 | ||
2215 | ||
2216 | buff #(1) d0_0 ( | |
2217 | .in(din[0:0]), | |
2218 | .out(dout[0:0]) | |
2219 | ); | |
2220 | ||
2221 | ||
2222 | ||
2223 | ||
2224 | ||
2225 | ||
2226 | ||
2227 | ||
2228 | endmodule | |
2229 | ||
2230 | ||
2231 | ||
2232 | // | |
2233 | // xor macro for ports = 2,3 | |
2234 | // | |
2235 | // | |
2236 | ||
2237 | ||
2238 | ||
2239 | ||
2240 | ||
2241 | module l2t_decc_dp_xor_macro__dxor_16x__ports_3__width_1 ( | |
2242 | din0, | |
2243 | din1, | |
2244 | din2, | |
2245 | dout); | |
2246 | input [0:0] din0; | |
2247 | input [0:0] din1; | |
2248 | input [0:0] din2; | |
2249 | output [0:0] dout; | |
2250 | ||
2251 | ||
2252 | ||
2253 | ||
2254 | ||
2255 | xor3 #(1) d0_0 ( | |
2256 | .in0(din0[0:0]), | |
2257 | .in1(din1[0:0]), | |
2258 | .in2(din2[0:0]), | |
2259 | .out(dout[0:0]) | |
2260 | ); | |
2261 | ||
2262 | ||
2263 | ||
2264 | ||
2265 | ||
2266 | ||
2267 | ||
2268 | ||
2269 | endmodule | |
2270 | ||
2271 | ||
2272 | ||
2273 | ||
2274 | ||
2275 | // | |
2276 | // xor macro for ports = 2,3 | |
2277 | // | |
2278 | // | |
2279 | ||
2280 | ||
2281 | ||
2282 | ||
2283 | ||
2284 | module l2t_decc_dp_xor_macro__dxor_16x__ports_2__width_1 ( | |
2285 | din0, | |
2286 | din1, | |
2287 | dout); | |
2288 | input [0:0] din0; | |
2289 | input [0:0] din1; | |
2290 | output [0:0] dout; | |
2291 | ||
2292 | ||
2293 | ||
2294 | ||
2295 | ||
2296 | xor2 #(1) d0_0 ( | |
2297 | .in0(din0[0:0]), | |
2298 | .in1(din1[0:0]), | |
2299 | .out(dout[0:0]) | |
2300 | ); | |
2301 | ||
2302 | ||
2303 | ||
2304 | ||
2305 | ||
2306 | ||
2307 | ||
2308 | ||
2309 | endmodule | |
2310 | ||
2311 | ||
2312 | ||
2313 | ||
2314 | ||
2315 | // | |
2316 | // parity macro (even parity) | |
2317 | // | |
2318 | // | |
2319 | ||
2320 | ||
2321 | ||
2322 | ||
2323 | ||
2324 | module l2t_decc_dp_prty_macro__dprty_8x__width_32 ( | |
2325 | din, | |
2326 | dout); | |
2327 | input [31:0] din; | |
2328 | output dout; | |
2329 | ||
2330 | ||
2331 | ||
2332 | ||
2333 | ||
2334 | ||
2335 | ||
2336 | prty #(32) m0_0 ( | |
2337 | .in(din[31:0]), | |
2338 | .out(dout) | |
2339 | ); | |
2340 | ||
2341 | ||
2342 | ||
2343 | ||
2344 | ||
2345 | ||
2346 | ||
2347 | ||
2348 | ||
2349 | ||
2350 | endmodule | |
2351 | ||
2352 | ||
2353 | ||
2354 | ||
2355 | ||
2356 | // | |
2357 | // parity macro (even parity) | |
2358 | // | |
2359 | // | |
2360 | ||
2361 | ||
2362 | ||
2363 | ||
2364 | ||
2365 | module l2t_decc_dp_prty_macro__dprty_8x__width_8 ( | |
2366 | din, | |
2367 | dout); | |
2368 | input [7:0] din; | |
2369 | output dout; | |
2370 | ||
2371 | ||
2372 | ||
2373 | ||
2374 | ||
2375 | ||
2376 | ||
2377 | prty #(8) m0_0 ( | |
2378 | .in(din[7:0]), | |
2379 | .out(dout) | |
2380 | ); | |
2381 | ||
2382 | ||
2383 | ||
2384 | ||
2385 | ||
2386 | ||
2387 | ||
2388 | ||
2389 | ||
2390 | ||
2391 | endmodule | |
2392 | ||
2393 | ||
2394 | ||
2395 | ||
2396 | ||
2397 | // | |
2398 | // invert macro | |
2399 | // | |
2400 | // | |
2401 | ||
2402 | ||
2403 | ||
2404 | ||
2405 | ||
2406 | module l2t_decc_dp_inv_macro__dinv_8x__width_2 ( | |
2407 | din, | |
2408 | dout); | |
2409 | input [1:0] din; | |
2410 | output [1:0] dout; | |
2411 | ||
2412 | ||
2413 | ||
2414 | ||
2415 | ||
2416 | ||
2417 | inv #(2) d0_0 ( | |
2418 | .in(din[1:0]), | |
2419 | .out(dout[1:0]) | |
2420 | ); | |
2421 | ||
2422 | ||
2423 | ||
2424 | ||
2425 | ||
2426 | ||
2427 | ||
2428 | ||
2429 | ||
2430 | endmodule | |
2431 | ||
2432 | ||
2433 | ||
2434 | ||
2435 | ||
2436 | // | |
2437 | // nand macro for ports = 2,3,4 | |
2438 | // | |
2439 | // | |
2440 | ||
2441 | ||
2442 | ||
2443 | ||
2444 | ||
2445 | module l2t_decc_dp_nand_macro__dnand_32x__width_3 ( | |
2446 | din0, | |
2447 | din1, | |
2448 | dout); | |
2449 | input [2:0] din0; | |
2450 | input [2:0] din1; | |
2451 | output [2:0] dout; | |
2452 | ||
2453 | ||
2454 | ||
2455 | ||
2456 | ||
2457 | ||
2458 | nand2 #(3) d0_0 ( | |
2459 | .in0(din0[2:0]), | |
2460 | .in1(din1[2:0]), | |
2461 | .out(dout[2:0]) | |
2462 | ); | |
2463 | ||
2464 | ||
2465 | ||
2466 | ||
2467 | ||
2468 | ||
2469 | ||
2470 | ||
2471 | ||
2472 | endmodule | |
2473 | ||
2474 | ||
2475 | ||
2476 | ||
2477 | ||
2478 | // | |
2479 | // nor macro for ports = 2,3 | |
2480 | // | |
2481 | // | |
2482 | ||
2483 | ||
2484 | ||
2485 | ||
2486 | ||
2487 | module l2t_decc_dp_nor_macro__ports_2__width_1 ( | |
2488 | din0, | |
2489 | din1, | |
2490 | dout); | |
2491 | input [0:0] din0; | |
2492 | input [0:0] din1; | |
2493 | output [0:0] dout; | |
2494 | ||
2495 | ||
2496 | ||
2497 | ||
2498 | ||
2499 | ||
2500 | nor2 #(1) d0_0 ( | |
2501 | .in0(din0[0:0]), | |
2502 | .in1(din1[0:0]), | |
2503 | .out(dout[0:0]) | |
2504 | ); | |
2505 | ||
2506 | ||
2507 | ||
2508 | ||
2509 | ||
2510 | ||
2511 | ||
2512 | endmodule | |
2513 | ||
2514 | ||
2515 | ||
2516 | ||
2517 | ||
2518 | // | |
2519 | // xor macro for ports = 2,3 | |
2520 | // | |
2521 | // | |
2522 | ||
2523 | ||
2524 | ||
2525 | ||
2526 | ||
2527 | module l2t_decc_dp_xor_macro__dxor_16x__width_32 ( | |
2528 | din0, | |
2529 | din1, | |
2530 | dout); | |
2531 | input [31:0] din0; | |
2532 | input [31:0] din1; | |
2533 | output [31:0] dout; | |
2534 | ||
2535 | ||
2536 | ||
2537 | ||
2538 | ||
2539 | xor2 #(32) d0_0 ( | |
2540 | .in0(din0[31:0]), | |
2541 | .in1(din1[31:0]), | |
2542 | .out(dout[31:0]) | |
2543 | ); | |
2544 | ||
2545 | ||
2546 | ||
2547 | ||
2548 | ||
2549 | ||
2550 | ||
2551 | ||
2552 | endmodule | |
2553 | ||
2554 | ||
2555 | ||
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | ||
2562 | // any PARAMS parms go into naming of macro | |
2563 | ||
2564 | module l2t_decc_dp_msff_macro__dmsff_32x__stack_32r__width_32 ( | |
2565 | din, | |
2566 | clk, | |
2567 | en, | |
2568 | se, | |
2569 | scan_in, | |
2570 | siclk, | |
2571 | soclk, | |
2572 | pce_ov, | |
2573 | stop, | |
2574 | dout, | |
2575 | scan_out); | |
2576 | wire l1clk; | |
2577 | wire siclk_out; | |
2578 | wire soclk_out; | |
2579 | wire [30:0] so; | |
2580 | ||
2581 | input [31:0] din; | |
2582 | ||
2583 | ||
2584 | input clk; | |
2585 | input en; | |
2586 | input se; | |
2587 | input scan_in; | |
2588 | input siclk; | |
2589 | input soclk; | |
2590 | input pce_ov; | |
2591 | input stop; | |
2592 | ||
2593 | ||
2594 | ||
2595 | output [31:0] dout; | |
2596 | ||
2597 | ||
2598 | output scan_out; | |
2599 | ||
2600 | ||
2601 | ||
2602 | ||
2603 | cl_dp1_l1hdr_8x c0_0 ( | |
2604 | .l2clk(clk), | |
2605 | .pce(en), | |
2606 | .aclk(siclk), | |
2607 | .bclk(soclk), | |
2608 | .l1clk(l1clk), | |
2609 | .se(se), | |
2610 | .pce_ov(pce_ov), | |
2611 | .stop(stop), | |
2612 | .siclk_out(siclk_out), | |
2613 | .soclk_out(soclk_out) | |
2614 | ); | |
2615 | dff #(32) d0_0 ( | |
2616 | .l1clk(l1clk), | |
2617 | .siclk(siclk_out), | |
2618 | .soclk(soclk_out), | |
2619 | .d(din[31:0]), | |
2620 | .si({scan_in,so[30:0]}), | |
2621 | .so({so[30:0],scan_out}), | |
2622 | .q(dout[31:0]) | |
2623 | ); | |
2624 | ||
2625 | ||
2626 | ||
2627 | ||
2628 | ||
2629 | ||
2630 | ||
2631 | ||
2632 | ||
2633 | ||
2634 | ||
2635 | ||
2636 | ||
2637 | ||
2638 | ||
2639 | ||
2640 | ||
2641 | ||
2642 | ||
2643 | ||
2644 | endmodule | |
2645 | ||
2646 | ||
2647 | ||
2648 | ||
2649 | ||
2650 | ||
2651 | ||
2652 | ||
2653 | ||
2654 | ||
2655 | ||
2656 | ||
2657 | ||
2658 | // any PARAMS parms go into naming of macro | |
2659 | ||
2660 | module l2t_decc_dp_msff_macro__dmsff_32x__stack_38r__width_38 ( | |
2661 | din, | |
2662 | clk, | |
2663 | en, | |
2664 | se, | |
2665 | scan_in, | |
2666 | siclk, | |
2667 | soclk, | |
2668 | pce_ov, | |
2669 | stop, | |
2670 | dout, | |
2671 | scan_out); | |
2672 | wire l1clk; | |
2673 | wire siclk_out; | |
2674 | wire soclk_out; | |
2675 | wire [36:0] so; | |
2676 | ||
2677 | input [37:0] din; | |
2678 | ||
2679 | ||
2680 | input clk; | |
2681 | input en; | |
2682 | input se; | |
2683 | input scan_in; | |
2684 | input siclk; | |
2685 | input soclk; | |
2686 | input pce_ov; | |
2687 | input stop; | |
2688 | ||
2689 | ||
2690 | ||
2691 | output [37:0] dout; | |
2692 | ||
2693 | ||
2694 | output scan_out; | |
2695 | ||
2696 | ||
2697 | ||
2698 | ||
2699 | cl_dp1_l1hdr_8x c0_0 ( | |
2700 | .l2clk(clk), | |
2701 | .pce(en), | |
2702 | .aclk(siclk), | |
2703 | .bclk(soclk), | |
2704 | .l1clk(l1clk), | |
2705 | .se(se), | |
2706 | .pce_ov(pce_ov), | |
2707 | .stop(stop), | |
2708 | .siclk_out(siclk_out), | |
2709 | .soclk_out(soclk_out) | |
2710 | ); | |
2711 | dff #(38) d0_0 ( | |
2712 | .l1clk(l1clk), | |
2713 | .siclk(siclk_out), | |
2714 | .soclk(soclk_out), | |
2715 | .d(din[37:0]), | |
2716 | .si({scan_in,so[36:0]}), | |
2717 | .so({so[36:0],scan_out}), | |
2718 | .q(dout[37:0]) | |
2719 | ); | |
2720 | ||
2721 | ||
2722 | ||
2723 | ||
2724 | ||
2725 | ||
2726 | ||
2727 | ||
2728 | ||
2729 | ||
2730 | ||
2731 | ||
2732 | ||
2733 | ||
2734 | ||
2735 | ||
2736 | ||
2737 | ||
2738 | ||
2739 | ||
2740 | endmodule | |
2741 | ||
2742 | ||
2743 | ||
2744 | ||
2745 | ||
2746 | ||
2747 | ||
2748 | ||
2749 | ||
2750 | ||
2751 | ||
2752 | ||
2753 | ||
2754 | // any PARAMS parms go into naming of macro | |
2755 | ||
2756 | module l2t_decc_dp_msff_macro__dmsff_32x__dmsff_32x__stack_30r__width_29 ( | |
2757 | din, | |
2758 | clk, | |
2759 | en, | |
2760 | se, | |
2761 | scan_in, | |
2762 | siclk, | |
2763 | soclk, | |
2764 | pce_ov, | |
2765 | stop, | |
2766 | dout, | |
2767 | scan_out); | |
2768 | wire l1clk; | |
2769 | wire siclk_out; | |
2770 | wire soclk_out; | |
2771 | wire [27:0] so; | |
2772 | ||
2773 | input [28:0] din; | |
2774 | ||
2775 | ||
2776 | input clk; | |
2777 | input en; | |
2778 | input se; | |
2779 | input scan_in; | |
2780 | input siclk; | |
2781 | input soclk; | |
2782 | input pce_ov; | |
2783 | input stop; | |
2784 | ||
2785 | ||
2786 | ||
2787 | output [28:0] dout; | |
2788 | ||
2789 | ||
2790 | output scan_out; | |
2791 | ||
2792 | ||
2793 | ||
2794 | ||
2795 | cl_dp1_l1hdr_8x c0_0 ( | |
2796 | .l2clk(clk), | |
2797 | .pce(en), | |
2798 | .aclk(siclk), | |
2799 | .bclk(soclk), | |
2800 | .l1clk(l1clk), | |
2801 | .se(se), | |
2802 | .pce_ov(pce_ov), | |
2803 | .stop(stop), | |
2804 | .siclk_out(siclk_out), | |
2805 | .soclk_out(soclk_out) | |
2806 | ); | |
2807 | dff #(29) d0_0 ( | |
2808 | .l1clk(l1clk), | |
2809 | .siclk(siclk_out), | |
2810 | .soclk(soclk_out), | |
2811 | .d(din[28:0]), | |
2812 | .si({scan_in,so[27:0]}), | |
2813 | .so({so[27:0],scan_out}), | |
2814 | .q(dout[28:0]) | |
2815 | ); | |
2816 | ||
2817 | ||
2818 | ||
2819 | ||
2820 | ||
2821 | ||
2822 | ||
2823 | ||
2824 | ||
2825 | ||
2826 | ||
2827 | ||
2828 | ||
2829 | ||
2830 | ||
2831 | ||
2832 | ||
2833 | ||
2834 | ||
2835 | ||
2836 | endmodule | |
2837 | ||
2838 | ||
2839 | ||
2840 | ||
2841 | ||
2842 | ||
2843 | ||
2844 | ||
2845 | ||
2846 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2847 | // also for pass-gate with decoder | |
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | ||
2853 | // any PARAMS parms go into naming of macro | |
2854 | ||
2855 | module l2t_decc_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_32r__width_32 ( | |
2856 | din0, | |
2857 | din1, | |
2858 | sel0, | |
2859 | dout); | |
2860 | wire psel0_unused; | |
2861 | wire psel1; | |
2862 | ||
2863 | input [31:0] din0; | |
2864 | input [31:0] din1; | |
2865 | input sel0; | |
2866 | output [31:0] dout; | |
2867 | ||
2868 | ||
2869 | ||
2870 | ||
2871 | ||
2872 | cl_dp1_penc2_8x c0_0 ( | |
2873 | .sel0(sel0), | |
2874 | .psel0(psel0_unused), | |
2875 | .psel1(psel1) | |
2876 | ); | |
2877 | ||
2878 | mux2e #(32) d0_0 ( | |
2879 | .sel(psel1), | |
2880 | .in0(din0[31:0]), | |
2881 | .in1(din1[31:0]), | |
2882 | .dout(dout[31:0]) | |
2883 | ); | |
2884 | ||
2885 | ||
2886 | ||
2887 | ||
2888 | ||
2889 | ||
2890 | ||
2891 | ||
2892 | ||
2893 | ||
2894 | ||
2895 | ||
2896 | ||
2897 | endmodule | |
2898 | ||
2899 | ||
2900 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2901 | // also for pass-gate with decoder | |
2902 | ||
2903 | ||
2904 | ||
2905 | ||
2906 | ||
2907 | // any PARAMS parms go into naming of macro | |
2908 | ||
2909 | module l2t_decc_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_39r__width_39 ( | |
2910 | din0, | |
2911 | din1, | |
2912 | din2, | |
2913 | din3, | |
2914 | sel0, | |
2915 | sel1, | |
2916 | sel2, | |
2917 | muxtst, | |
2918 | test, | |
2919 | dout); | |
2920 | wire psel0; | |
2921 | wire psel1; | |
2922 | wire psel2; | |
2923 | wire psel3; | |
2924 | ||
2925 | input [38:0] din0; | |
2926 | input [38:0] din1; | |
2927 | input [38:0] din2; | |
2928 | input [38:0] din3; | |
2929 | input sel0; | |
2930 | input sel1; | |
2931 | input sel2; | |
2932 | input muxtst; | |
2933 | input test; | |
2934 | output [38:0] dout; | |
2935 | ||
2936 | ||
2937 | ||
2938 | ||
2939 | ||
2940 | cl_dp1_penc4_8x c0_0 ( | |
2941 | .sel0(sel0), | |
2942 | .sel1(sel1), | |
2943 | .sel2(sel2), | |
2944 | .psel0(psel0), | |
2945 | .psel1(psel1), | |
2946 | .psel2(psel2), | |
2947 | .psel3(psel3), | |
2948 | .test(test) | |
2949 | ); | |
2950 | ||
2951 | mux4 #(39) d0_0 ( | |
2952 | .sel0(psel0), | |
2953 | .sel1(psel1), | |
2954 | .sel2(psel2), | |
2955 | .sel3(psel3), | |
2956 | .in0(din0[38:0]), | |
2957 | .in1(din1[38:0]), | |
2958 | .in2(din2[38:0]), | |
2959 | .in3(din3[38:0]), | |
2960 | .dout(dout[38:0]), | |
2961 | .muxtst(muxtst) | |
2962 | ); | |
2963 | ||
2964 | ||
2965 | ||
2966 | ||
2967 | ||
2968 | ||
2969 | ||
2970 | ||
2971 | ||
2972 | ||
2973 | ||
2974 | ||
2975 | ||
2976 | endmodule | |
2977 | ||
2978 | ||
2979 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2980 | // also for pass-gate with decoder | |
2981 | ||
2982 | ||
2983 | ||
2984 | ||
2985 | ||
2986 | // any PARAMS parms go into naming of macro | |
2987 | ||
2988 | module l2t_decc_dp_mux_macro__mux_aope__ports_2__stack_39r__width_39 ( | |
2989 | din0, | |
2990 | din1, | |
2991 | sel0, | |
2992 | dout); | |
2993 | wire psel0; | |
2994 | wire psel1; | |
2995 | ||
2996 | input [38:0] din0; | |
2997 | input [38:0] din1; | |
2998 | input sel0; | |
2999 | output [38:0] dout; | |
3000 | ||
3001 | ||
3002 | ||
3003 | ||
3004 | ||
3005 | cl_dp1_penc2_8x c0_0 ( | |
3006 | .sel0(sel0), | |
3007 | .psel0(psel0), | |
3008 | .psel1(psel1) | |
3009 | ); | |
3010 | ||
3011 | mux2s #(39) d0_0 ( | |
3012 | .sel0(psel0), | |
3013 | .sel1(psel1), | |
3014 | .in0(din0[38:0]), | |
3015 | .in1(din1[38:0]), | |
3016 | .dout(dout[38:0]) | |
3017 | ); | |
3018 | ||
3019 | ||
3020 | ||
3021 | ||
3022 | ||
3023 | ||
3024 | ||
3025 | ||
3026 | ||
3027 | ||
3028 | ||
3029 | ||
3030 | ||
3031 | endmodule | |
3032 | ||
3033 | ||
3034 | // | |
3035 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
3036 | // | |
3037 | // | |
3038 | ||
3039 | ||
3040 | ||
3041 | ||
3042 | ||
3043 | module l2t_decc_dp_cmp_macro__width_8 ( | |
3044 | din0, | |
3045 | din1, | |
3046 | dout); | |
3047 | input [7:0] din0; | |
3048 | input [7:0] din1; | |
3049 | output dout; | |
3050 | ||
3051 | ||
3052 | ||
3053 | ||
3054 | ||
3055 | ||
3056 | cmp #(8) m0_0 ( | |
3057 | .in0(din0[7:0]), | |
3058 | .in1(din1[7:0]), | |
3059 | .out(dout) | |
3060 | ); | |
3061 | ||
3062 | ||
3063 | ||
3064 | ||
3065 | ||
3066 | ||
3067 | ||
3068 | ||
3069 | ||
3070 | ||
3071 | endmodule | |
3072 | ||
3073 | ||
3074 | ||
3075 | ||
3076 | ||
3077 | // | |
3078 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
3079 | // | |
3080 | // | |
3081 | ||
3082 | ||
3083 | ||
3084 | ||
3085 | ||
3086 | module l2t_decc_dp_cmp_macro__width_32 ( | |
3087 | din0, | |
3088 | din1, | |
3089 | dout); | |
3090 | input [31:0] din0; | |
3091 | input [31:0] din1; | |
3092 | output dout; | |
3093 | ||
3094 | ||
3095 | ||
3096 | ||
3097 | ||
3098 | ||
3099 | cmp #(32) m0_0 ( | |
3100 | .in0(din0[31:0]), | |
3101 | .in1(din1[31:0]), | |
3102 | .out(dout) | |
3103 | ); | |
3104 | ||
3105 | ||
3106 | ||
3107 | ||
3108 | ||
3109 | ||
3110 | ||
3111 | ||
3112 | ||
3113 | ||
3114 | endmodule | |
3115 | ||
3116 | ||
3117 | ||
3118 | ||
3119 | ||
3120 | // | |
3121 | // and macro for ports = 2,3,4 | |
3122 | // | |
3123 | // | |
3124 | ||
3125 | ||
3126 | ||
3127 | ||
3128 | ||
3129 | module l2t_decc_dp_and_macro__width_1 ( | |
3130 | din0, | |
3131 | din1, | |
3132 | dout); | |
3133 | input [0:0] din0; | |
3134 | input [0:0] din1; | |
3135 | output [0:0] dout; | |
3136 | ||
3137 | ||
3138 | ||
3139 | ||
3140 | ||
3141 | ||
3142 | and2 #(1) d0_0 ( | |
3143 | .in0(din0[0:0]), | |
3144 | .in1(din1[0:0]), | |
3145 | .out(dout[0:0]) | |
3146 | ); | |
3147 | ||
3148 | ||
3149 | ||
3150 | ||
3151 | ||
3152 | ||
3153 | ||
3154 | ||
3155 | ||
3156 | endmodule | |
3157 | ||
3158 | ||
3159 | ||
3160 | ||
3161 | ||
3162 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3163 | // also for pass-gate with decoder | |
3164 | ||
3165 | ||
3166 | ||
3167 | ||
3168 | ||
3169 | // any PARAMS parms go into naming of macro | |
3170 | ||
3171 | module l2t_decc_dp_mux_macro__mux_aonpe__stack_2r__width_1 ( | |
3172 | din0, | |
3173 | sel0, | |
3174 | din1, | |
3175 | sel1, | |
3176 | dout); | |
3177 | wire buffout0; | |
3178 | wire buffout1; | |
3179 | ||
3180 | input [0:0] din0; | |
3181 | input sel0; | |
3182 | input [0:0] din1; | |
3183 | input sel1; | |
3184 | output [0:0] dout; | |
3185 | ||
3186 | ||
3187 | ||
3188 | ||
3189 | ||
3190 | cl_dp1_muxbuff2_8x c0_0 ( | |
3191 | .in0(sel0), | |
3192 | .in1(sel1), | |
3193 | .out0(buffout0), | |
3194 | .out1(buffout1) | |
3195 | ); | |
3196 | mux2s #(1) d0_0 ( | |
3197 | .sel0(buffout0), | |
3198 | .sel1(buffout1), | |
3199 | .in0(din0[0:0]), | |
3200 | .in1(din1[0:0]), | |
3201 | .dout(dout[0:0]) | |
3202 | ); | |
3203 | ||
3204 | ||
3205 | ||
3206 | ||
3207 | ||
3208 | ||
3209 | ||
3210 | ||
3211 | ||
3212 | ||
3213 | ||
3214 | ||
3215 | ||
3216 | endmodule | |
3217 | ||
3218 | ||
3219 | ||
3220 | ||
3221 | ||
3222 | ||
3223 | // any PARAMS parms go into naming of macro | |
3224 | ||
3225 | module l2t_decc_dp_msff_macro__dmsff_32x__stack_38r__width_29 ( | |
3226 | din, | |
3227 | clk, | |
3228 | en, | |
3229 | se, | |
3230 | scan_in, | |
3231 | siclk, | |
3232 | soclk, | |
3233 | pce_ov, | |
3234 | stop, | |
3235 | dout, | |
3236 | scan_out); | |
3237 | wire l1clk; | |
3238 | wire siclk_out; | |
3239 | wire soclk_out; | |
3240 | wire [27:0] so; | |
3241 | ||
3242 | input [28:0] din; | |
3243 | ||
3244 | ||
3245 | input clk; | |
3246 | input en; | |
3247 | input se; | |
3248 | input scan_in; | |
3249 | input siclk; | |
3250 | input soclk; | |
3251 | input pce_ov; | |
3252 | input stop; | |
3253 | ||
3254 | ||
3255 | ||
3256 | output [28:0] dout; | |
3257 | ||
3258 | ||
3259 | output scan_out; | |
3260 | ||
3261 | ||
3262 | ||
3263 | ||
3264 | cl_dp1_l1hdr_8x c0_0 ( | |
3265 | .l2clk(clk), | |
3266 | .pce(en), | |
3267 | .aclk(siclk), | |
3268 | .bclk(soclk), | |
3269 | .l1clk(l1clk), | |
3270 | .se(se), | |
3271 | .pce_ov(pce_ov), | |
3272 | .stop(stop), | |
3273 | .siclk_out(siclk_out), | |
3274 | .soclk_out(soclk_out) | |
3275 | ); | |
3276 | dff #(29) d0_0 ( | |
3277 | .l1clk(l1clk), | |
3278 | .siclk(siclk_out), | |
3279 | .soclk(soclk_out), | |
3280 | .d(din[28:0]), | |
3281 | .si({scan_in,so[27:0]}), | |
3282 | .so({so[27:0],scan_out}), | |
3283 | .q(dout[28:0]) | |
3284 | ); | |
3285 | ||
3286 | ||
3287 | ||
3288 | ||
3289 | ||
3290 | ||
3291 | ||
3292 | ||
3293 | ||
3294 | ||
3295 | ||
3296 | ||
3297 | ||
3298 | ||
3299 | ||
3300 | ||
3301 | ||
3302 | ||
3303 | ||
3304 | ||
3305 | endmodule | |
3306 | ||
3307 | ||
3308 | ||
3309 | ||
3310 | ||
3311 | ||
3312 | ||
3313 | ||
3314 | ||
3315 | ||
3316 | ||
3317 | ||
3318 | ||
3319 | // any PARAMS parms go into naming of macro | |
3320 | ||
3321 | module l2t_decc_dp_msff_macro__dmsff_32x__stack_39r__width_35 ( | |
3322 | din, | |
3323 | clk, | |
3324 | en, | |
3325 | se, | |
3326 | scan_in, | |
3327 | siclk, | |
3328 | soclk, | |
3329 | pce_ov, | |
3330 | stop, | |
3331 | dout, | |
3332 | scan_out); | |
3333 | wire l1clk; | |
3334 | wire siclk_out; | |
3335 | wire soclk_out; | |
3336 | wire [33:0] so; | |
3337 | ||
3338 | input [34:0] din; | |
3339 | ||
3340 | ||
3341 | input clk; | |
3342 | input en; | |
3343 | input se; | |
3344 | input scan_in; | |
3345 | input siclk; | |
3346 | input soclk; | |
3347 | input pce_ov; | |
3348 | input stop; | |
3349 | ||
3350 | ||
3351 | ||
3352 | output [34:0] dout; | |
3353 | ||
3354 | ||
3355 | output scan_out; | |
3356 | ||
3357 | ||
3358 | ||
3359 | ||
3360 | cl_dp1_l1hdr_8x c0_0 ( | |
3361 | .l2clk(clk), | |
3362 | .pce(en), | |
3363 | .aclk(siclk), | |
3364 | .bclk(soclk), | |
3365 | .l1clk(l1clk), | |
3366 | .se(se), | |
3367 | .pce_ov(pce_ov), | |
3368 | .stop(stop), | |
3369 | .siclk_out(siclk_out), | |
3370 | .soclk_out(soclk_out) | |
3371 | ); | |
3372 | dff #(35) d0_0 ( | |
3373 | .l1clk(l1clk), | |
3374 | .siclk(siclk_out), | |
3375 | .soclk(soclk_out), | |
3376 | .d(din[34:0]), | |
3377 | .si({scan_in,so[33:0]}), | |
3378 | .so({so[33:0],scan_out}), | |
3379 | .q(dout[34:0]) | |
3380 | ); | |
3381 | ||
3382 | ||
3383 | ||
3384 | ||
3385 | ||
3386 | ||
3387 | ||
3388 | ||
3389 | ||
3390 | ||
3391 | ||
3392 | ||
3393 | ||
3394 | ||
3395 | ||
3396 | ||
3397 | ||
3398 | ||
3399 | ||
3400 | ||
3401 | endmodule | |
3402 | ||
3403 | ||
3404 | ||
3405 | ||
3406 | ||
3407 | ||
3408 | ||
3409 | ||
3410 | ||
3411 | ||
3412 | ||
3413 | ||
3414 | ||
3415 | // any PARAMS parms go into naming of macro | |
3416 | ||
3417 | module l2t_decc_dp_msff_macro__dmsff_32x__stack_39r__width_39 ( | |
3418 | din, | |
3419 | clk, | |
3420 | en, | |
3421 | se, | |
3422 | scan_in, | |
3423 | siclk, | |
3424 | soclk, | |
3425 | pce_ov, | |
3426 | stop, | |
3427 | dout, | |
3428 | scan_out); | |
3429 | wire l1clk; | |
3430 | wire siclk_out; | |
3431 | wire soclk_out; | |
3432 | wire [37:0] so; | |
3433 | ||
3434 | input [38:0] din; | |
3435 | ||
3436 | ||
3437 | input clk; | |
3438 | input en; | |
3439 | input se; | |
3440 | input scan_in; | |
3441 | input siclk; | |
3442 | input soclk; | |
3443 | input pce_ov; | |
3444 | input stop; | |
3445 | ||
3446 | ||
3447 | ||
3448 | output [38:0] dout; | |
3449 | ||
3450 | ||
3451 | output scan_out; | |
3452 | ||
3453 | ||
3454 | ||
3455 | ||
3456 | cl_dp1_l1hdr_8x c0_0 ( | |
3457 | .l2clk(clk), | |
3458 | .pce(en), | |
3459 | .aclk(siclk), | |
3460 | .bclk(soclk), | |
3461 | .l1clk(l1clk), | |
3462 | .se(se), | |
3463 | .pce_ov(pce_ov), | |
3464 | .stop(stop), | |
3465 | .siclk_out(siclk_out), | |
3466 | .soclk_out(soclk_out) | |
3467 | ); | |
3468 | dff #(39) d0_0 ( | |
3469 | .l1clk(l1clk), | |
3470 | .siclk(siclk_out), | |
3471 | .soclk(soclk_out), | |
3472 | .d(din[38:0]), | |
3473 | .si({scan_in,so[37:0]}), | |
3474 | .so({so[37:0],scan_out}), | |
3475 | .q(dout[38:0]) | |
3476 | ); | |
3477 | ||
3478 | ||
3479 | ||
3480 | ||
3481 | ||
3482 | ||
3483 | ||
3484 | ||
3485 | ||
3486 | ||
3487 | ||
3488 | ||
3489 | ||
3490 | ||
3491 | ||
3492 | ||
3493 | ||
3494 | ||
3495 | ||
3496 | ||
3497 | endmodule | |
3498 | ||
3499 | ||
3500 | ||
3501 | ||
3502 | ||
3503 | ||
3504 | ||
3505 |