projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: l2t_deccck_ctl.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module l2t_deccck_ctl ( | |
| 36 | tcu_pce_ov, | |
| 37 | tcu_aclk, | |
| 38 | tcu_bclk, | |
| 39 | tcu_scan_en, | |
| 40 | tag_deccck_addr3_c7, | |
| 41 | arb_inst_l2data_vld_c6, | |
| 42 | tag_data_ecc_active_c3, | |
| 43 | bist_data_enable_c1, | |
| 44 | bist_data_waddr_c1, | |
| 45 | arbadr_arbdp_addr22_c7, | |
| 46 | arbadr_arbdp_waddr_c6, | |
| 47 | deccck_bscd_corr_err_c8, | |
| 48 | deccck_bscd_uncorr_err_c8, | |
| 49 | deccck_bscd_notdata_err_c8, | |
| 50 | deccck_spcd_corr_err_c8, | |
| 51 | deccck_spcd_uncorr_err_c8, | |
| 52 | deccck_spcd_notdata_err_c8, | |
| 53 | deccck_scrd_corr_err_c8, | |
| 54 | deccck_scrd_uncorr_err_c8, | |
| 55 | deccck_spcfb_corr_err_c8, | |
| 56 | deccck_spcfb_uncorr_err_c8, | |
| 57 | deccck_uncorr_err_c8, | |
| 58 | deccck_corr_err_c8, | |
| 59 | deccck_notdata_err_c8, | |
| 60 | deccdp_decck_uncorr_err_c7, | |
| 61 | deccdp_decck_corr_err_c7, | |
| 62 | tag_spc_rd_vld_c6, | |
| 63 | tag_bsc_rd_vld_c7, | |
| 64 | tag_scrub_rd_vld_c7, | |
| 65 | filbuf_spc_corr_err_c6, | |
| 66 | filbuf_spc_uncorr_err_c6, | |
| 67 | filbuf_spc_rd_vld_c6, | |
| 68 | deccck_dword_sel_c7, | |
| 69 | deccck_muxsel_diag_out_c7, | |
| 70 | arbadr_arbdp_line_addr_c7, | |
| 71 | arbadr_arbdp_line_addr_c6, | |
| 72 | l2clk, | |
| 73 | scan_in, | |
| 74 | scan_out); | |
| 75 | wire pce_ov; | |
| 76 | wire stop; | |
| 77 | wire siclk; | |
| 78 | wire soclk; | |
| 79 | wire se; | |
| 80 | wire l1clk; | |
| 81 | wire spares_scanin; | |
| 82 | wire spares_scanout; | |
| 83 | wire ff_bist_en_c2_scanin; | |
| 84 | wire ff_bist_en_c2_scanout; | |
| 85 | wire ff_bist_en_c3_scanin; | |
| 86 | wire ff_bist_en_c3_scanout; | |
| 87 | wire ff_bist_en_c4_scanin; | |
| 88 | wire ff_bist_en_c4_scanout; | |
| 89 | wire ff_bist_en_c5_scanin; | |
| 90 | wire ff_bist_en_c5_scanout; | |
| 91 | wire ff_bist_en_c52_scanin; | |
| 92 | wire ff_bist_en_c52_scanout; | |
| 93 | wire ff_bist_en_c6_scanin; | |
| 94 | wire ff_bist_en_c6_scanout; | |
| 95 | wire ff_bist_waddr_c2_scanin; | |
| 96 | wire ff_bist_waddr_c2_scanout; | |
| 97 | wire ff_bist_waddr_c3_scanin; | |
| 98 | wire ff_bist_waddr_c3_scanout; | |
| 99 | wire ff_bist_waddr_c4_scanin; | |
| 100 | wire ff_bist_waddr_c4_scanout; | |
| 101 | wire ff_bist_waddr_c5_scanin; | |
| 102 | wire ff_bist_waddr_c5_scanout; | |
| 103 | wire ff_bist_waddr_c52_scanin; | |
| 104 | wire ff_bist_waddr_c52_scanout; | |
| 105 | wire ff_bist_waddr_c6_scanin; | |
| 106 | wire ff_bist_waddr_c6_scanout; | |
| 107 | wire ff_misc_terms_scanin; | |
| 108 | wire ff_misc_terms_scanout; | |
| 109 | wire tag_spc_rd_vld_c7; | |
| 110 | wire filbuf_spc_rd_vld_c7; | |
| 111 | wire filbuf_spc_corr_err_c7; | |
| 112 | wire filbuf_spc_uncorr_err_c7; | |
| 113 | wire ff_spc_rd_vld_c8_scanin; | |
| 114 | wire ff_spc_rd_vld_c8_scanout; | |
| 115 | wire ff_deccck_scrd_corr_err_c8_scanin; | |
| 116 | wire ff_deccck_scrd_corr_err_c8_scanout; | |
| 117 | wire ff_deccck_scrd_uncorr_err_c8_scanin; | |
| 118 | wire ff_deccck_scrd_uncorr_err_c8_scanout; | |
| 119 | wire ff_filbuf_spc_rd_vld_c8_scanin; | |
| 120 | wire ff_filbuf_spc_rd_vld_c8_scanout; | |
| 121 | wire ff_filbuf_spc_corr_err_c8_scanin; | |
| 122 | wire ff_filbuf_spc_corr_err_c8_scanout; | |
| 123 | wire ff_filbuf_spc_uncorr_err_c8_scanin; | |
| 124 | wire ff_filbuf_spc_uncorr_err_c8_scanout; | |
| 125 | wire ff_bsc_rd_vld_c8_scanin; | |
| 126 | wire ff_bsc_rd_vld_c8_scanout; | |
| 127 | wire ff_waddr_c7_scanin; | |
| 128 | wire ff_waddr_c7_scanout; | |
| 129 | wire data_ecc_active_c4; | |
| 130 | wire ff_deccck_active_c4_scanin; | |
| 131 | wire ff_deccck_active_c4_scanout; | |
| 132 | wire data_ecc_active_c5; | |
| 133 | wire ff_deccck_active_c5_scanin; | |
| 134 | wire ff_deccck_active_c5_scanout; | |
| 135 | wire data_ecc_active_c52; | |
| 136 | wire ff_deccck_active_c52_scanin; | |
| 137 | wire ff_deccck_active_c52_scanout; | |
| 138 | wire data_ecc_active_c6; | |
| 139 | wire ff_deccck_active_c6_scanin; | |
| 140 | wire ff_deccck_active_c6_scanout; | |
| 141 | wire data_ecc_active_c7; | |
| 142 | wire ff_deccck_active_c7_scanin; | |
| 143 | wire ff_deccck_active_c7_scanout; | |
| 144 | wire diag_data_vld_c7; | |
| 145 | wire ff_diag_data_vld_c7_scanin; | |
| 146 | wire ff_diag_data_vld_c7_scanout; | |
| 147 | wire [3:0] deccck_muxsel_diag_out_c6; | |
| 148 | wire ff_deccck_muxsel_diag_out_c7_scanin; | |
| 149 | wire ff_deccck_muxsel_diag_out_c7_scanout; | |
| 150 | ||
| 151 | ||
| 152 | input tcu_pce_ov; | |
| 153 | input tcu_aclk; | |
| 154 | input tcu_bclk; | |
| 155 | input tcu_scan_en; | |
| 156 | ||
| 157 | input tag_deccck_addr3_c7; | |
| 158 | input arb_inst_l2data_vld_c6; | |
| 159 | input tag_data_ecc_active_c3; | |
| 160 | ||
| 161 | input bist_data_enable_c1; | |
| 162 | input [1:0] bist_data_waddr_c1; | |
| 163 | input arbadr_arbdp_addr22_c7; | |
| 164 | input [1:0] arbadr_arbdp_waddr_c6; | |
| 165 | ||
| 166 | //input csr_error_ceen ; // Correctable error enables | |
| 167 | //input csr_error_nceen ; // Uncorrectable error enables | |
| 168 | ||
| 169 | ||
| 170 | ||
| 171 | output deccck_bscd_corr_err_c8 ; // siu data | |
| 172 | output deccck_bscd_uncorr_err_c8 ; // siu data | |
| 173 | output deccck_bscd_notdata_err_c8; // siu data | |
| 174 | ||
| 175 | output deccck_spcd_corr_err_c8 ; // spc data | |
| 176 | output deccck_spcd_uncorr_err_c8 ; // spc data | |
| 177 | output deccck_spcd_notdata_err_c8; // spc data | |
| 178 | output deccck_scrd_corr_err_c8 ; // scrub | |
| 179 | output deccck_scrd_uncorr_err_c8 ; // scrub | |
| 180 | output deccck_spcfb_corr_err_c8 ; // spc data from fb | |
| 181 | output deccck_spcfb_uncorr_err_c8 ; // spc data from fb | |
| 182 | ||
| 183 | //output deccck_uncorr_err_c8; // an uncorr err has happenned Unqual | |
| 184 | //output deccck_corr_err_c8; // a correctable err has happened | |
| 185 | //output deccck_notdata_err_c8; // a notdata err has happened | |
| 186 | ||
| 187 | input deccck_uncorr_err_c8; // an uncorr err has happenned Unqual | |
| 188 | input deccck_corr_err_c8; // a correctable err has happened | |
| 189 | input deccck_notdata_err_c8; // a notdata err has happened | |
| 190 | ||
| 191 | //input data_uncorr_err_c7; // an uncorr err has happenned Unqual | |
| 192 | //input data_corr_err_c7; // a correctable err has happened | |
| 193 | //input data_notdata_err_c7; // a notdata err has happened | |
| 194 | ||
| 195 | input [3:0] deccdp_decck_uncorr_err_c7; // an uncorr err has happenned Unqual | |
| 196 | input [3:0] deccdp_decck_corr_err_c7; // a correctable err has happened | |
| 197 | //input [3:0] deccck_notdata_err_c7; // a notdata err has happened | |
| 198 | ||
| 199 | //input tag_spc_rd_vld_c7 ; // input for err classification | |
| 200 | input tag_spc_rd_vld_c6 ; // input for err classification | |
| 201 | input tag_bsc_rd_vld_c7; // NEW_PIN | |
| 202 | input tag_scrub_rd_vld_c7 ; // input for err classification | |
| 203 | ||
| 204 | //input filbuf_spc_corr_err_c7; // indicates that an corr err was | |
| 205 | // // received from the DRAM | |
| 206 | //input filbuf_spc_uncorr_err_c7; // indicates that an uncorr err was | |
| 207 | // // received from the DRAM | |
| 208 | //input filbuf_spc_rd_vld_c7; // indicates that an FB read is active for a | |
| 209 | // // sparc instruction | |
| 210 | ||
| 211 | input filbuf_spc_corr_err_c6; | |
| 212 | input filbuf_spc_uncorr_err_c6; | |
| 213 | input filbuf_spc_rd_vld_c6; | |
| 214 | ||
| 215 | ||
| 216 | //output deccck_sel_higher_dword_c7; | |
| 217 | output deccck_dword_sel_c7; | |
| 218 | ||
| 219 | output [3:0] deccck_muxsel_diag_out_c7; | |
| 220 | ||
| 221 | //output [2:0] deccck_ret_err_c8; | |
| 222 | //output [2:0] deccck_ret_err_c7; | |
| 223 | ||
| 224 | output [5:4] arbadr_arbdp_line_addr_c7; | |
| 225 | input [5:4] arbadr_arbdp_line_addr_c6; | |
| 226 | ||
| 227 | input l2clk; | |
| 228 | input scan_in; | |
| 229 | output scan_out; | |
| 230 | ||
| 231 | // from deccckdp. | |
| 232 | //input [5:0] decc_check0_c7; | |
| 233 | //input [5:0] decc_check1_c7; | |
| 234 | //input [5:0] decc_check2_c7; | |
| 235 | //input [5:0] decc_check3_c7; | |
| 236 | //input decc_parity0_c7; | |
| 237 | //input decc_parity1_c7; | |
| 238 | //input decc_parity2_c7; | |
| 239 | //input decc_parity3_c7; | |
| 240 | ||
| 241 | ||
| 242 | ||
| 243 | ////////////////////////////////////////////////// | |
| 244 | // L1 clk header | |
| 245 | ////////////////////////////////////////////////// | |
| 246 | assign pce_ov = tcu_pce_ov; | |
| 247 | assign stop = 1'b0; | |
| 248 | assign siclk = tcu_aclk; | |
| 249 | assign soclk = tcu_bclk; | |
| 250 | assign se = tcu_scan_en; | |
| 251 | ||
| 252 | l2t_deccck_ctl_l1clkhdr_ctl_macro clkgen ( | |
| 253 | .l2clk(l2clk), | |
| 254 | .l1en(1'b1 ), | |
| 255 | .l1clk(l1clk), | |
| 256 | .pce_ov(pce_ov), | |
| 257 | .stop(stop), | |
| 258 | .se(se)); | |
| 259 | ||
| 260 | ////////////////////////////////////////////////// | |
| 261 | ||
| 262 | ////////////////////////////////////////// | |
| 263 | // Spare gate insertion | |
| 264 | ////////////////////////////////////////// | |
| 265 | l2t_deccck_ctl_spare_ctl_macro__num_4 spares ( | |
| 266 | .scan_in(spares_scanin), | |
| 267 | .scan_out(spares_scanout), | |
| 268 | .l1clk (l1clk), | |
| 269 | .siclk(siclk), | |
| 270 | .soclk(soclk) | |
| 271 | ); | |
| 272 | ////////////////////////////////////////// | |
| 273 | ||
| 274 | ||
| 275 | ||
| 276 | wire [3:0] corr_err_c7; | |
| 277 | wire [3:0] uncorr_err_c7; | |
| 278 | wire data_corr_err_c7; | |
| 279 | wire data_uncorr_err_c7; | |
| 280 | ||
| 281 | wire [1:0] bist_data_waddr_c2; | |
| 282 | wire [1:0] bist_data_waddr_c3; | |
| 283 | wire [1:0] bist_data_waddr_c4; | |
| 284 | wire [1:0] bist_data_waddr_c5; | |
| 285 | wire [1:0] bist_data_waddr_c52; // BS 03/11/04 extra cycle for mem access | |
| 286 | wire [1:0] bist_data_waddr_c6; | |
| 287 | ||
| 288 | wire bist_data_enable_c2; | |
| 289 | wire bist_data_enable_c3; | |
| 290 | wire bist_data_enable_c4; | |
| 291 | wire bist_data_enable_c5; | |
| 292 | wire bist_data_enable_c52; // BS 03/11/04 extra cycle for mem access | |
| 293 | wire bist_data_enable_c6; | |
| 294 | ||
| 295 | wire scr_data_corr_err_c7 ; | |
| 296 | wire scr_data_uncorr_err_c7 ; | |
| 297 | ||
| 298 | ||
| 299 | wire [2:0] ret_err_c7 ; | |
| 300 | wire error_ceen_d1 ; | |
| 301 | wire error_nceen_d1 ; | |
| 302 | ||
| 303 | ||
| 304 | ||
| 305 | wire [1:0] waddr_c7; // 3:2 | |
| 306 | wire [1:0] diag_addr_c7; | |
| 307 | ||
| 308 | wire sel_higher_word_c6; | |
| 309 | wire sel_higher_dword_c6; | |
| 310 | ||
| 311 | wire sel_bist_c6; | |
| 312 | wire sel_diag_c7; | |
| 313 | wire sel_def_c6; | |
| 314 | ||
| 315 | ||
| 316 | wire data_corr_err_c8, filbuf_spc_rd_vld_c8, filbuf_spc_corr_err_c8; | |
| 317 | wire spc_rd_vld_c8, bsc_rd_vld_c8; | |
| 318 | wire filbuf_spc_uncorr_err_c8; | |
| 319 | ||
| 320 | ||
| 321 | ||
| 322 | ||
| 323 | ///////////// | |
| 324 | //// Bug id 91419 | |
| 325 | //// to distinguish not data from CE need to qualify it with | |
| 326 | //// not notdata | |
| 327 | //// | |
| 328 | //// assign corr_err_c7[0] = decc_parity0_c7 ; | |
| 329 | //// assign corr_err_c7[1] = decc_parity1_c7 ; | |
| 330 | //// assign corr_err_c7[2] = decc_parity2_c7 ; | |
| 331 | //// assign corr_err_c7[3] = decc_parity3_c7 ; | |
| 332 | // | |
| 333 | //assign corr_err_c7[0] = decc_parity0_c7 & ~(decc_check0_c7[5:0] == 6'b111111); | |
| 334 | //assign corr_err_c7[1] = decc_parity1_c7 & ~(decc_check1_c7[5:0] == 6'b111111); | |
| 335 | //assign corr_err_c7[2] = decc_parity2_c7 & ~(decc_check2_c7[5:0] == 6'b111111); | |
| 336 | //assign corr_err_c7[3] = decc_parity3_c7 & ~(decc_check3_c7[5:0] == 6'b111111); | |
| 337 | // | |
| 338 | // | |
| 339 | // | |
| 340 | // | |
| 341 | //assign data_corr_err_c7 = |( corr_err_c7[3:0] ) ; | |
| 342 | // | |
| 343 | //// BS 06/13/04 added Notdata logic | |
| 344 | //// detect Notdata if check bits are all 1's on any 4 byte segment, and it is not a sparc | |
| 345 | //// read of the fill buffer before the fill. | |
| 346 | // | |
| 347 | //assign data_notdata_err_c7 = (({decc_parity0_c7,decc_check0_c7[5:0]} == 7'b1111111) | | |
| 348 | // ({decc_parity1_c7,decc_check1_c7[5:0]} == 7'b1111111) | | |
| 349 | // ({decc_parity2_c7,decc_check2_c7[5:0]} == 7'b1111111) | | |
| 350 | // ({decc_parity3_c7,decc_check3_c7[5:0]} == 7'b1111111)) | |
| 351 | // & ~filbuf_spc_rd_vld_c7; | |
| 352 | // | |
| 353 | //// in case the Notdata is detected on a sparc read of the Fill buffer itself, should | |
| 354 | //// treat it as UE . this is because a UE trap has not been issued yet, as the | |
| 355 | //// read of the fill buffer is happening before the fill. | |
| 356 | // | |
| 357 | //assign uncorr_err_c7[0] = (|(decc_check0_c7[5:0]) & ~decc_parity0_c7) | | |
| 358 | // (({decc_parity0_c7,decc_check0_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7) ; | |
| 359 | //assign uncorr_err_c7[1] = (|(decc_check1_c7[5:0]) & ~decc_parity1_c7) | | |
| 360 | // (({decc_parity1_c7,decc_check1_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7); | |
| 361 | //assign uncorr_err_c7[2] = (|(decc_check2_c7[5:0]) & ~decc_parity2_c7) | | |
| 362 | // (({decc_parity2_c7,decc_check2_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7) ; | |
| 363 | //assign uncorr_err_c7[3] = (|(decc_check3_c7[5:0]) & ~decc_parity3_c7) | | |
| 364 | // (({decc_parity3_c7,decc_check3_c7[5:0]} == 7'b1111111) & filbuf_spc_rd_vld_c7) ; | |
| 365 | // | |
| 366 | //assign data_uncorr_err_c7 = |(uncorr_err_c7[3:0]) ; | |
| 367 | // | |
| 368 | // | |
| 369 | ||
| 370 | assign uncorr_err_c7[3:0] = deccdp_decck_uncorr_err_c7[3:0]; | |
| 371 | assign corr_err_c7[3:0] = deccdp_decck_corr_err_c7[3:0]; | |
| 372 | ||
| 373 | ||
| 374 | l2t_deccck_ctl_msff_ctl_macro__width_3 ff_bist_en_c2 | |
| 375 | (.dout ({arbadr_arbdp_line_addr_c7[5:4],bist_data_enable_c2}), | |
| 376 | .scan_in(ff_bist_en_c2_scanin), | |
| 377 | .scan_out(ff_bist_en_c2_scanout), | |
| 378 | .din ({arbadr_arbdp_line_addr_c6[5:4],bist_data_enable_c1}), | |
| 379 | .l1clk (l1clk), | |
| 380 | .siclk(siclk), | |
| 381 | .soclk(soclk) | |
| 382 | ) ; | |
| 383 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_bist_en_c3 | |
| 384 | (.dout (bist_data_enable_c3), .din (bist_data_enable_c2), | |
| 385 | .scan_in(ff_bist_en_c3_scanin), | |
| 386 | .scan_out(ff_bist_en_c3_scanout), | |
| 387 | .l1clk (l1clk), | |
| 388 | .siclk(siclk), | |
| 389 | .soclk(soclk) | |
| 390 | ) ; | |
| 391 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_bist_en_c4 | |
| 392 | (.dout (bist_data_enable_c4), .din (bist_data_enable_c3), | |
| 393 | .scan_in(ff_bist_en_c4_scanin), | |
| 394 | .scan_out(ff_bist_en_c4_scanout), | |
| 395 | .l1clk (l1clk), | |
| 396 | .siclk(siclk), | |
| 397 | .soclk(soclk) | |
| 398 | ) ; | |
| 399 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_bist_en_c5 | |
| 400 | (.dout (bist_data_enable_c5), .din (bist_data_enable_c4), | |
| 401 | .scan_in(ff_bist_en_c5_scanin), | |
| 402 | .scan_out(ff_bist_en_c5_scanout), | |
| 403 | .l1clk (l1clk), | |
| 404 | .siclk(siclk), | |
| 405 | .soclk(soclk) | |
| 406 | ) ; | |
| 407 | ||
| 408 | // BS 03/11/04 extra cycle for mem access | |
| 409 | ||
| 410 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_bist_en_c52 | |
| 411 | (.dout (bist_data_enable_c52), .din (bist_data_enable_c5), | |
| 412 | .scan_in(ff_bist_en_c52_scanin), | |
| 413 | .scan_out(ff_bist_en_c52_scanout), | |
| 414 | .l1clk (l1clk), | |
| 415 | .siclk(siclk), | |
| 416 | .soclk(soclk) | |
| 417 | ) ; | |
| 418 | ||
| 419 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_bist_en_c6 | |
| 420 | (.dout (bist_data_enable_c6), .din (bist_data_enable_c52), | |
| 421 | .scan_in(ff_bist_en_c6_scanin), | |
| 422 | .scan_out(ff_bist_en_c6_scanout), | |
| 423 | .l1clk (l1clk), | |
| 424 | .siclk(siclk), | |
| 425 | .soclk(soclk) | |
| 426 | ) ; | |
| 427 | ||
| 428 | ||
| 429 | l2t_deccck_ctl_msff_ctl_macro__width_2 ff_bist_waddr_c2 | |
| 430 | (.dout (bist_data_waddr_c2[1:0]), .din (bist_data_waddr_c1[1:0]), | |
| 431 | .scan_in(ff_bist_waddr_c2_scanin), | |
| 432 | .scan_out(ff_bist_waddr_c2_scanout), | |
| 433 | .l1clk (l1clk), | |
| 434 | .siclk(siclk), | |
| 435 | .soclk(soclk) | |
| 436 | ) ; | |
| 437 | l2t_deccck_ctl_msff_ctl_macro__width_2 ff_bist_waddr_c3 | |
| 438 | (.dout (bist_data_waddr_c3[1:0]), .din (bist_data_waddr_c2[1:0]), | |
| 439 | .scan_in(ff_bist_waddr_c3_scanin), | |
| 440 | .scan_out(ff_bist_waddr_c3_scanout), | |
| 441 | .l1clk (l1clk), | |
| 442 | .siclk(siclk), | |
| 443 | .soclk(soclk) | |
| 444 | ) ; | |
| 445 | l2t_deccck_ctl_msff_ctl_macro__width_2 ff_bist_waddr_c4 | |
| 446 | (.dout (bist_data_waddr_c4[1:0]), .din (bist_data_waddr_c3[1:0]), | |
| 447 | .scan_in(ff_bist_waddr_c4_scanin), | |
| 448 | .scan_out(ff_bist_waddr_c4_scanout), | |
| 449 | .l1clk (l1clk), | |
| 450 | .siclk(siclk), | |
| 451 | .soclk(soclk) | |
| 452 | ) ; | |
| 453 | l2t_deccck_ctl_msff_ctl_macro__width_2 ff_bist_waddr_c5 | |
| 454 | (.dout (bist_data_waddr_c5[1:0]), .din (bist_data_waddr_c4[1:0]), | |
| 455 | .scan_in(ff_bist_waddr_c5_scanin), | |
| 456 | .scan_out(ff_bist_waddr_c5_scanout), | |
| 457 | .l1clk (l1clk), | |
| 458 | .siclk(siclk), | |
| 459 | .soclk(soclk) | |
| 460 | ) ; | |
| 461 | ||
| 462 | // BS 03/11/04 extra cycle for mem access | |
| 463 | ||
| 464 | l2t_deccck_ctl_msff_ctl_macro__width_2 ff_bist_waddr_c52 | |
| 465 | (.dout (bist_data_waddr_c52[1:0]), .din (bist_data_waddr_c5[1:0]), | |
| 466 | .scan_in(ff_bist_waddr_c52_scanin), | |
| 467 | .scan_out(ff_bist_waddr_c52_scanout), | |
| 468 | .l1clk (l1clk), | |
| 469 | .siclk(siclk), | |
| 470 | .soclk(soclk) | |
| 471 | ) ; | |
| 472 | ||
| 473 | l2t_deccck_ctl_msff_ctl_macro__width_2 ff_bist_waddr_c6 | |
| 474 | (.dout (bist_data_waddr_c6[1:0]), .din (bist_data_waddr_c52[1:0]), | |
| 475 | .scan_in(ff_bist_waddr_c6_scanin), | |
| 476 | .scan_out(ff_bist_waddr_c6_scanout), | |
| 477 | .l1clk (l1clk), | |
| 478 | .siclk(siclk), | |
| 479 | .soclk(soclk) | |
| 480 | ) ; | |
| 481 | ||
| 482 | ||
| 483 | // | |
| 484 | //msff_ctl_macro ff_deccck_uncorr_err_c8 (width=1) | |
| 485 | // (.dout (deccck_uncorr_err_c8), .din (data_uncorr_err_c7), | |
| 486 | // .scan_in(ff_deccck_uncorr_err_c8_scanin), | |
| 487 | // .scan_out(ff_deccck_uncorr_err_c8_scanout), | |
| 488 | // .l1clk (l1clk) | |
| 489 | //) ; | |
| 490 | ||
| 491 | // BS 06/13/04 : added Notdata logic | |
| 492 | // register notdata error bit | |
| 493 | // | |
| 494 | //msff_ctl_macro ff_deccck_notdata_err_c8 (width=1) | |
| 495 | // (.dout (deccck_notdata_err_c8), .din (data_notdata_err_c7), | |
| 496 | // .scan_in(ff_deccck_notdata_err_c8_scanin), | |
| 497 | // .scan_out(ff_deccck_notdata_err_c8_scanout), | |
| 498 | // .l1clk (l1clk) | |
| 499 | //) ; | |
| 500 | // | |
| 501 | // | |
| 502 | //msff_ctl_macro ff_data_corr_err_c8 (width=1) | |
| 503 | // (.dout (data_corr_err_c8), .din (data_corr_err_c7), | |
| 504 | // .scan_in(ff_data_corr_err_c8_scanin), | |
| 505 | // .scan_out(ff_data_corr_err_c8_scanout), | |
| 506 | // .l1clk (l1clk) | |
| 507 | // ) ; | |
| 508 | //// | |
| 509 | //assign deccck_corr_err_c8 = data_corr_err_c8; // BS 03/18/04 : taking out deccck_corr_err_c8 to gate off cas and | |
| 510 | // // swap/ldstub stores updates in case of Correctable Error as part | |
| 511 | // // of new requirment for RAS in N2 to retry the atomics on a CE. | |
| 512 | // // because of the retry, the update for the store should not happen | |
| 513 | // // in L2. | |
| 514 | ||
| 515 | assign data_corr_err_c8 = deccck_corr_err_c8; | |
| 516 | ||
| 517 | ||
| 518 | l2t_deccck_ctl_msff_ctl_macro__width_4 ff_misc_terms | |
| 519 | ( | |
| 520 | .scan_in(ff_misc_terms_scanin), | |
| 521 | .scan_out(ff_misc_terms_scanout), | |
| 522 | .dout ({tag_spc_rd_vld_c7,filbuf_spc_rd_vld_c7,filbuf_spc_corr_err_c7,filbuf_spc_uncorr_err_c7}), | |
| 523 | .din ({tag_spc_rd_vld_c6,filbuf_spc_rd_vld_c6, filbuf_spc_corr_err_c6,filbuf_spc_uncorr_err_c6}), | |
| 524 | .l1clk (l1clk), | |
| 525 | .siclk(siclk), | |
| 526 | .soclk(soclk) | |
| 527 | ); | |
| 528 | ||
| 529 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_spc_rd_vld_c8 | |
| 530 | (.dout (spc_rd_vld_c8), .din (tag_spc_rd_vld_c7), | |
| 531 | .scan_in(ff_spc_rd_vld_c8_scanin), | |
| 532 | .scan_out(ff_spc_rd_vld_c8_scanout), | |
| 533 | .l1clk (l1clk), | |
| 534 | .siclk(siclk), | |
| 535 | .soclk(soclk) | |
| 536 | ||
| 537 | ) ; | |
| 538 | ||
| 539 | assign deccck_spcd_corr_err_c8 = data_corr_err_c8 & spc_rd_vld_c8; | |
| 540 | assign deccck_spcd_uncorr_err_c8 = deccck_uncorr_err_c8 & spc_rd_vld_c8; | |
| 541 | assign deccck_spcd_notdata_err_c8 = deccck_notdata_err_c8 & spc_rd_vld_c8; | |
| 542 | ||
| 543 | assign scr_data_corr_err_c7 = (((corr_err_c7[3] | corr_err_c7[2]) & ~tag_deccck_addr3_c7) | | |
| 544 | ((corr_err_c7[1] | corr_err_c7[0]) & tag_deccck_addr3_c7) | |
| 545 | ) & tag_scrub_rd_vld_c7 ; | |
| 546 | ||
| 547 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_deccck_scrd_corr_err_c8 | |
| 548 | (.dout (deccck_scrd_corr_err_c8), .din (scr_data_corr_err_c7), | |
| 549 | .scan_in(ff_deccck_scrd_corr_err_c8_scanin), | |
| 550 | .scan_out(ff_deccck_scrd_corr_err_c8_scanout), | |
| 551 | .l1clk (l1clk), | |
| 552 | .siclk(siclk), | |
| 553 | .soclk(soclk) | |
| 554 | ||
| 555 | ) ; | |
| 556 | ||
| 557 | assign scr_data_uncorr_err_c7 = (((uncorr_err_c7[3] | uncorr_err_c7[2]) & ~tag_deccck_addr3_c7) | | |
| 558 | ((uncorr_err_c7[1] | uncorr_err_c7[0]) & tag_deccck_addr3_c7) | |
| 559 | ) & tag_scrub_rd_vld_c7 ; | |
| 560 | ||
| 561 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_deccck_scrd_uncorr_err_c8 | |
| 562 | (.dout (deccck_scrd_uncorr_err_c8), .din (scr_data_uncorr_err_c7), | |
| 563 | .scan_in(ff_deccck_scrd_uncorr_err_c8_scanin), | |
| 564 | .scan_out(ff_deccck_scrd_uncorr_err_c8_scanout), | |
| 565 | .l1clk (l1clk), | |
| 566 | .siclk(siclk), | |
| 567 | .soclk(soclk) | |
| 568 | ) ; | |
| 569 | ||
| 570 | ||
| 571 | ||
| 572 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_filbuf_spc_rd_vld_c8 | |
| 573 | (.dout (filbuf_spc_rd_vld_c8), .din (filbuf_spc_rd_vld_c7), | |
| 574 | .scan_in(ff_filbuf_spc_rd_vld_c8_scanin), | |
| 575 | .scan_out(ff_filbuf_spc_rd_vld_c8_scanout), | |
| 576 | .l1clk (l1clk), | |
| 577 | .siclk(siclk), | |
| 578 | .soclk(soclk) | |
| 579 | ||
| 580 | ) ; | |
| 581 | ||
| 582 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_filbuf_spc_corr_err_c8 | |
| 583 | (.dout (filbuf_spc_corr_err_c8), .din (filbuf_spc_corr_err_c7), | |
| 584 | .scan_in(ff_filbuf_spc_corr_err_c8_scanin), | |
| 585 | .scan_out(ff_filbuf_spc_corr_err_c8_scanout), | |
| 586 | .l1clk (l1clk), | |
| 587 | .siclk(siclk), | |
| 588 | .soclk(soclk) | |
| 589 | ||
| 590 | ) ; | |
| 591 | ||
| 592 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_filbuf_spc_uncorr_err_c8 | |
| 593 | (.dout (filbuf_spc_uncorr_err_c8), .din (filbuf_spc_uncorr_err_c7), | |
| 594 | .scan_in(ff_filbuf_spc_uncorr_err_c8_scanin), | |
| 595 | .scan_out(ff_filbuf_spc_uncorr_err_c8_scanout), | |
| 596 | .l1clk (l1clk), | |
| 597 | .siclk(siclk), | |
| 598 | .soclk(soclk) | |
| 599 | ||
| 600 | ) ; | |
| 601 | ||
| 602 | assign deccck_spcfb_corr_err_c8 = (data_corr_err_c8 & filbuf_spc_rd_vld_c8) | | |
| 603 | filbuf_spc_corr_err_c8; | |
| 604 | ||
| 605 | ||
| 606 | assign deccck_spcfb_uncorr_err_c8 = (deccck_uncorr_err_c8 & filbuf_spc_rd_vld_c8) | | |
| 607 | filbuf_spc_uncorr_err_c8; | |
| 608 | ||
| 609 | ||
| 610 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_bsc_rd_vld_c8 | |
| 611 | (.dout (bsc_rd_vld_c8), .din (tag_bsc_rd_vld_c7), | |
| 612 | .scan_in(ff_bsc_rd_vld_c8_scanin), | |
| 613 | .scan_out(ff_bsc_rd_vld_c8_scanout), | |
| 614 | .l1clk (l1clk), | |
| 615 | .siclk(siclk), | |
| 616 | .soclk(soclk) | |
| 617 | ||
| 618 | ) ; | |
| 619 | ||
| 620 | assign deccck_bscd_corr_err_c8 = data_corr_err_c8 & bsc_rd_vld_c8; | |
| 621 | ||
| 622 | assign deccck_bscd_uncorr_err_c8 = deccck_uncorr_err_c8 & bsc_rd_vld_c8; | |
| 623 | ||
| 624 | assign deccck_bscd_notdata_err_c8 = deccck_notdata_err_c8 & bsc_rd_vld_c8; | |
| 625 | ||
| 626 | ||
| 627 | ||
| 628 | ||
| 629 | ||
| 630 | // csr_error_ceen and csr_error_nceen are the register bits for enabling the reporting | |
| 631 | // of the correctable and uncorrectable error respectively. | |
| 632 | // | |
| 633 | //msff_ctl_macro ff_error_ceen_d1 (width=1) | |
| 634 | // (.dout (error_ceen_d1), .din (csr_error_ceen), | |
| 635 | // .scan_in(ff_error_ceen_d1_scanin), | |
| 636 | // .scan_out(ff_error_ceen_d1_scanout), | |
| 637 | // .l1clk (l1clk), | |
| 638 | //) ; | |
| 639 | // | |
| 640 | //msff_ctl_macro ff_error_nceen_d1 (width=1) | |
| 641 | // (.dout (error_nceen_d1), .din (csr_error_nceen), | |
| 642 | // .scan_in(ff_error_nceen_d1_scanin), | |
| 643 | // .scan_out(ff_error_nceen_d1_scanout), | |
| 644 | // .l1clk (l1clk) | |
| 645 | //) ; | |
| 646 | // | |
| 647 | ||
| 648 | // only precise error reporting is handled here. | |
| 649 | // | |
| 650 | //assign ret_err_c7[0] = ((data_corr_err_c7 | filbuf_spc_corr_err_c7) & | |
| 651 | // ( ( tag_spc_rd_vld_c7 | filbuf_spc_rd_vld_c7 | | |
| 652 | // filbuf_spc_corr_err_c7 ) & error_ceen_d1 )) | | |
| 653 | // (data_notdata_err_c7 & tag_spc_rd_vld_c7 & error_nceen_d1); | |
| 654 | // // Notdata encoding is err[1:0] = 2'b11 | |
| 655 | // | |
| 656 | //assign ret_err_c7[1] = ((data_uncorr_err_c7 | filbuf_spc_uncorr_err_c7) & | |
| 657 | // ( ( tag_spc_rd_vld_c7 | filbuf_spc_rd_vld_c7 | | |
| 658 | // filbuf_spc_uncorr_err_c7 ) & error_nceen_d1 )) | | |
| 659 | // (data_notdata_err_c7 & tag_spc_rd_vld_c7 & error_nceen_d1); | |
| 660 | // // Notdata encoding is err[1:0] = 2'b11 | |
| 661 | // | |
| 662 | // | |
| 663 | // | |
| 664 | //assign ret_err_c7_uece[0] = ((data_corr_err_c7 | filbuf_spc_corr_err_c7) & | |
| 665 | // ((tag_spc_rd_vld_c7 | filbuf_spc_rd_vld_c7 | filbuf_spc_corr_err_c7 ) | |
| 666 | // & error_ceen_d1 )); | |
| 667 | // | |
| 668 | //assign ret_err_c7_uece[1] = ((data_uncorr_err_c7 | filbuf_spc_uncorr_err_c7) & | |
| 669 | // ((tag_spc_rd_vld_c7 | filbuf_spc_rd_vld_c7 | filbuf_spc_uncorr_err_c7 ) | |
| 670 | // & error_nceen_d1 )) ; | |
| 671 | // | |
| 672 | //assign ret_err_c7_nd[0] = (data_notdata_err_c7 & tag_spc_rd_vld_c7 & error_nceen_d1); | |
| 673 | //assign ret_err_c7_nd[1] = (data_notdata_err_c7 & tag_spc_rd_vld_c7 & error_nceen_d1); | |
| 674 | // | |
| 675 | //assign ret_err_c7[0] = (ret_err_c7_uece[0] & ~ret_err_c7_uece[1]) | ret_err_c7_nd[0]; | |
| 676 | //assign ret_err_c7[1] = ret_err_c7_uece[1] | ret_err_c7_nd[0]; | |
| 677 | // | |
| 678 | //assign ret_err_c7[2] = 1'b0 ; // RSVD | |
| 679 | // | |
| 680 | //msff_ctl_macro ff_ret_err_c8 (width=3) | |
| 681 | // (.dout (deccck_ret_err_c8[2:0]), .din (ret_err_c7[2:0]), | |
| 682 | // .scan_in(ff_ret_err_c8_scanin), | |
| 683 | // .scan_out(ff_ret_err_c8_scanout), | |
| 684 | // .l1clk (l1clk) | |
| 685 | // | |
| 686 | //) ; | |
| 687 | // | |
| 688 | // | |
| 689 | //assign deccck_ret_err_c7[2:0] = ret_err_c7[2:0] ; | |
| 690 | // | |
| 691 | ||
| 692 | ////////////////////////////////////////////////////////////////////////// | |
| 693 | // | |
| 694 | // data that is xmitted to the arbdat block | |
| 695 | // The following 2-1 mUX is used for psts. | |
| 696 | // In C6, the data is merged with partial dirty data and written into | |
| 697 | // the Miss Buffer. | |
| 698 | // arbadr_arbdp_waddr_c6[1:0] is the Address bit[3:2] of the regular instruction. | |
| 699 | // "arbdp_addr22_c7" is the Address Bit[22] of the Diagnostic access. | |
| 700 | // It is equivalent to the address bit[2] for the diagnostic access and is | |
| 701 | // used for selecting 32 bit out of 128 bit read from the L2$ data array. | |
| 702 | // | |
| 703 | ////////////////////////////////////////////////////////////////////////// | |
| 704 | ||
| 705 | // arbadr_arbdp_waddr_c6[1:0] is the Address bit[3:2] of the regular instruction. | |
| 706 | l2t_deccck_ctl_msff_ctl_macro__width_2 ff_waddr_c7 | |
| 707 | (.dout (waddr_c7[1:0]), | |
| 708 | .scan_in(ff_waddr_c7_scanin), | |
| 709 | .scan_out(ff_waddr_c7_scanout), | |
| 710 | .din (arbadr_arbdp_waddr_c6[1:0]), | |
| 711 | .l1clk (l1clk), | |
| 712 | .siclk(siclk), | |
| 713 | .soclk(soclk) | |
| 714 | ||
| 715 | ||
| 716 | ) ; | |
| 717 | ||
| 718 | assign diag_addr_c7 = {waddr_c7[1], arbadr_arbdp_addr22_c7} ; | |
| 719 | ||
| 720 | ||
| 721 | ||
| 722 | // Address bit[3] of Scrub instruction, used for selecting 64 bit out of | |
| 723 | // 128 bit read from the L2$ data array. | |
| 724 | ||
| 725 | ||
| 726 | ||
| 727 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_deccck_active_c4 | |
| 728 | (.dout (data_ecc_active_c4), | |
| 729 | .scan_in(ff_deccck_active_c4_scanin), | |
| 730 | .scan_out(ff_deccck_active_c4_scanout), | |
| 731 | .din (tag_data_ecc_active_c3), | |
| 732 | .l1clk (l1clk), | |
| 733 | .siclk(siclk), | |
| 734 | .soclk(soclk) | |
| 735 | ||
| 736 | ||
| 737 | ) ; | |
| 738 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_deccck_active_c5 | |
| 739 | (.dout (data_ecc_active_c5), | |
| 740 | .scan_in(ff_deccck_active_c5_scanin), | |
| 741 | .scan_out(ff_deccck_active_c5_scanout), | |
| 742 | .din (data_ecc_active_c4), | |
| 743 | .l1clk (l1clk), | |
| 744 | .siclk(siclk), | |
| 745 | .soclk(soclk) | |
| 746 | ||
| 747 | ||
| 748 | ) ; | |
| 749 | ||
| 750 | // BS 03/11/04 extra cycle for mem access | |
| 751 | ||
| 752 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_deccck_active_c52 | |
| 753 | (.dout (data_ecc_active_c52), | |
| 754 | .scan_in(ff_deccck_active_c52_scanin), | |
| 755 | .scan_out(ff_deccck_active_c52_scanout), | |
| 756 | .din (data_ecc_active_c5), | |
| 757 | .l1clk (l1clk), | |
| 758 | .siclk(siclk), | |
| 759 | .soclk(soclk) | |
| 760 | ||
| 761 | ||
| 762 | ) ; | |
| 763 | ||
| 764 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_deccck_active_c6 | |
| 765 | (.dout (data_ecc_active_c6), | |
| 766 | .scan_in(ff_deccck_active_c6_scanin), | |
| 767 | .scan_out(ff_deccck_active_c6_scanout), | |
| 768 | .din (data_ecc_active_c52), | |
| 769 | .l1clk (l1clk), | |
| 770 | .siclk(siclk), | |
| 771 | .soclk(soclk) | |
| 772 | ||
| 773 | ||
| 774 | ) ; | |
| 775 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_deccck_active_c7 | |
| 776 | (.dout (data_ecc_active_c7), | |
| 777 | .scan_in(ff_deccck_active_c7_scanin), | |
| 778 | .scan_out(ff_deccck_active_c7_scanout), | |
| 779 | .din (data_ecc_active_c6), | |
| 780 | .l1clk (l1clk), | |
| 781 | .siclk(siclk), | |
| 782 | .soclk(soclk) | |
| 783 | ||
| 784 | ||
| 785 | ) ; | |
| 786 | ||
| 787 | assign deccck_dword_sel_c7 = (diag_addr_c7[1] & ~data_ecc_active_c7) | |
| 788 | | tag_deccck_addr3_c7 ; | |
| 789 | ||
| 790 | // the following data muxes are used for | |
| 791 | // 1. diagnostic accesses to l2data | |
| 792 | // 2. tap reads to DRAm addresses. | |
| 793 | // 3. bist accesses to l2data. | |
| 794 | // these operation need 39 bit data out of the 156 bit read from the L2 array, | |
| 795 | // so the data needs to be muxed 4:1. The 4to1 muxing is mbist_done in two stages | |
| 796 | // of 2to1 muxing using the address bit[3:2] as the select signals. | |
| 797 | ||
| 798 | l2t_deccck_ctl_msff_ctl_macro__width_1 ff_diag_data_vld_c7 | |
| 799 | (.dout (diag_data_vld_c7), .din (arb_inst_l2data_vld_c6), | |
| 800 | .scan_in(ff_diag_data_vld_c7_scanin), | |
| 801 | .scan_out(ff_diag_data_vld_c7_scanout), | |
| 802 | .l1clk (l1clk), | |
| 803 | .siclk(siclk), | |
| 804 | .soclk(soclk) | |
| 805 | ) ; | |
| 806 | ||
| 807 | ||
| 808 | assign sel_bist_c6 = bist_data_enable_c6 ; | |
| 809 | assign sel_diag_c7 = diag_data_vld_c7 & ~bist_data_enable_c6 ; | |
| 810 | assign sel_def_c6 = ~diag_data_vld_c7 & ~bist_data_enable_c6 ; | |
| 811 | ||
| 812 | assign sel_higher_word_c6 = (diag_addr_c7[0] & sel_diag_c7) | | |
| 813 | (bist_data_waddr_c6[0] & sel_bist_c6) | | |
| 814 | (arbadr_arbdp_waddr_c6[0] & sel_def_c6) ; | |
| 815 | ||
| 816 | ||
| 817 | ||
| 818 | ||
| 819 | assign sel_higher_dword_c6 = (diag_addr_c7[1] & sel_diag_c7) | | |
| 820 | (bist_data_waddr_c6[1] & sel_bist_c6) | | |
| 821 | (arbadr_arbdp_waddr_c6[1] & sel_def_c6) ; | |
| 822 | ||
| 823 | //msff_ctl_macro ff_sel_higher_dword_c7 (width=1) | |
| 824 | // (.dout (deccck_sel_higher_dword_c7), .din (sel_higher_dword_c6), | |
| 825 | // .scan_in(ff_sel_higher_dword_c7_scanin), | |
| 826 | // .scan_out(ff_sel_higher_dword_c7_scanout), | |
| 827 | // .l1clk (l1clk), | |
| 828 | //) ; | |
| 829 | ||
| 830 | ||
| 831 | ||
| 832 | assign deccck_muxsel_diag_out_c6[0] = ~sel_higher_word_c6 & ~sel_higher_dword_c6; | |
| 833 | assign deccck_muxsel_diag_out_c6[1] = sel_higher_word_c6 & ~sel_higher_dword_c6; | |
| 834 | assign deccck_muxsel_diag_out_c6[2] = ~sel_higher_word_c6 & sel_higher_dword_c6; | |
| 835 | assign deccck_muxsel_diag_out_c6[3] = sel_higher_word_c6 & sel_higher_dword_c6; | |
| 836 | ||
| 837 | ||
| 838 | l2t_deccck_ctl_msff_ctl_macro__width_4 ff_deccck_muxsel_diag_out_c7 | |
| 839 | ( | |
| 840 | .scan_in(ff_deccck_muxsel_diag_out_c7_scanin), | |
| 841 | .scan_out(ff_deccck_muxsel_diag_out_c7_scanout), | |
| 842 | .dout (deccck_muxsel_diag_out_c7[3:0]), | |
| 843 | .din (deccck_muxsel_diag_out_c6[3:0]), | |
| 844 | .l1clk (l1clk), | |
| 845 | .siclk(siclk), | |
| 846 | .soclk(soclk) | |
| 847 | ) ; | |
| 848 | ||
| 849 | ||
| 850 | // fixscan start: | |
| 851 | assign spares_scanin = scan_in ; | |
| 852 | assign ff_bist_en_c2_scanin = spares_scanout ; | |
| 853 | assign ff_bist_en_c3_scanin = ff_bist_en_c2_scanout ; | |
| 854 | assign ff_bist_en_c4_scanin = ff_bist_en_c3_scanout ; | |
| 855 | assign ff_bist_en_c5_scanin = ff_bist_en_c4_scanout ; | |
| 856 | assign ff_bist_en_c52_scanin = ff_bist_en_c5_scanout ; | |
| 857 | assign ff_bist_en_c6_scanin = ff_bist_en_c52_scanout ; | |
| 858 | assign ff_bist_waddr_c2_scanin = ff_bist_en_c6_scanout ; | |
| 859 | assign ff_bist_waddr_c3_scanin = ff_bist_waddr_c2_scanout ; | |
| 860 | assign ff_bist_waddr_c4_scanin = ff_bist_waddr_c3_scanout ; | |
| 861 | assign ff_bist_waddr_c5_scanin = ff_bist_waddr_c4_scanout ; | |
| 862 | assign ff_bist_waddr_c52_scanin = ff_bist_waddr_c5_scanout ; | |
| 863 | assign ff_bist_waddr_c6_scanin = ff_bist_waddr_c52_scanout; | |
| 864 | assign ff_misc_terms_scanin = ff_bist_waddr_c6_scanout ; | |
| 865 | assign ff_spc_rd_vld_c8_scanin = ff_misc_terms_scanout ; | |
| 866 | assign ff_deccck_scrd_corr_err_c8_scanin = ff_spc_rd_vld_c8_scanout ; | |
| 867 | assign ff_deccck_scrd_uncorr_err_c8_scanin = ff_deccck_scrd_corr_err_c8_scanout; | |
| 868 | assign ff_filbuf_spc_rd_vld_c8_scanin = ff_deccck_scrd_uncorr_err_c8_scanout; | |
| 869 | assign ff_filbuf_spc_corr_err_c8_scanin = ff_filbuf_spc_rd_vld_c8_scanout; | |
| 870 | assign ff_filbuf_spc_uncorr_err_c8_scanin = ff_filbuf_spc_corr_err_c8_scanout; | |
| 871 | assign ff_bsc_rd_vld_c8_scanin = ff_filbuf_spc_uncorr_err_c8_scanout; | |
| 872 | assign ff_waddr_c7_scanin = ff_bsc_rd_vld_c8_scanout ; | |
| 873 | assign ff_deccck_active_c4_scanin = ff_waddr_c7_scanout ; | |
| 874 | assign ff_deccck_active_c5_scanin = ff_deccck_active_c4_scanout; | |
| 875 | assign ff_deccck_active_c52_scanin = ff_deccck_active_c5_scanout; | |
| 876 | assign ff_deccck_active_c6_scanin = ff_deccck_active_c52_scanout; | |
| 877 | assign ff_deccck_active_c7_scanin = ff_deccck_active_c6_scanout; | |
| 878 | assign ff_diag_data_vld_c7_scanin = ff_deccck_active_c7_scanout; | |
| 879 | assign ff_deccck_muxsel_diag_out_c7_scanin = ff_diag_data_vld_c7_scanout; | |
| 880 | assign scan_out = ff_deccck_muxsel_diag_out_c7_scanout; | |
| 881 | // fixscan end: | |
| 882 | endmodule | |
| 883 | ||
| 884 | ||
| 885 | ||
| 886 | ||
| 887 | ||
| 888 | ||
| 889 | ||
| 890 | // any PARAMS parms go into naming of macro | |
| 891 | ||
| 892 | module l2t_deccck_ctl_l1clkhdr_ctl_macro ( | |
| 893 | l2clk, | |
| 894 | l1en, | |
| 895 | pce_ov, | |
| 896 | stop, | |
| 897 | se, | |
| 898 | l1clk); | |
| 899 | ||
| 900 | ||
| 901 | input l2clk; | |
| 902 | input l1en; | |
| 903 | input pce_ov; | |
| 904 | input stop; | |
| 905 | input se; | |
| 906 | output l1clk; | |
| 907 | ||
| 908 | ||
| 909 | ||
| 910 | ||
| 911 | ||
| 912 | cl_sc1_l1hdr_8x c_0 ( | |
| 913 | ||
| 914 | ||
| 915 | .l2clk(l2clk), | |
| 916 | .pce(l1en), | |
| 917 | .l1clk(l1clk), | |
| 918 | .se(se), | |
| 919 | .pce_ov(pce_ov), | |
| 920 | .stop(stop) | |
| 921 | ); | |
| 922 | ||
| 923 | ||
| 924 | ||
| 925 | endmodule | |
| 926 | ||
| 927 | ||
| 928 | ||
| 929 | ||
| 930 | ||
| 931 | ||
| 932 | ||
| 933 | ||
| 934 | ||
| 935 | // Description: Spare gate macro for control blocks | |
| 936 | // | |
| 937 | // Param num controls the number of times the macro is added | |
| 938 | // flops=0 can be used to use only combination spare logic | |
| 939 | ||
| 940 | ||
| 941 | module l2t_deccck_ctl_spare_ctl_macro__num_4 ( | |
| 942 | l1clk, | |
| 943 | scan_in, | |
| 944 | siclk, | |
| 945 | soclk, | |
| 946 | scan_out); | |
| 947 | wire si_0; | |
| 948 | wire so_0; | |
| 949 | wire spare0_flop_unused; | |
| 950 | wire spare0_buf_32x_unused; | |
| 951 | wire spare0_nand3_8x_unused; | |
| 952 | wire spare0_inv_8x_unused; | |
| 953 | wire spare0_aoi22_4x_unused; | |
| 954 | wire spare0_buf_8x_unused; | |
| 955 | wire spare0_oai22_4x_unused; | |
| 956 | wire spare0_inv_16x_unused; | |
| 957 | wire spare0_nand2_16x_unused; | |
| 958 | wire spare0_nor3_4x_unused; | |
| 959 | wire spare0_nand2_8x_unused; | |
| 960 | wire spare0_buf_16x_unused; | |
| 961 | wire spare0_nor2_16x_unused; | |
| 962 | wire spare0_inv_32x_unused; | |
| 963 | wire si_1; | |
| 964 | wire so_1; | |
| 965 | wire spare1_flop_unused; | |
| 966 | wire spare1_buf_32x_unused; | |
| 967 | wire spare1_nand3_8x_unused; | |
| 968 | wire spare1_inv_8x_unused; | |
| 969 | wire spare1_aoi22_4x_unused; | |
| 970 | wire spare1_buf_8x_unused; | |
| 971 | wire spare1_oai22_4x_unused; | |
| 972 | wire spare1_inv_16x_unused; | |
| 973 | wire spare1_nand2_16x_unused; | |
| 974 | wire spare1_nor3_4x_unused; | |
| 975 | wire spare1_nand2_8x_unused; | |
| 976 | wire spare1_buf_16x_unused; | |
| 977 | wire spare1_nor2_16x_unused; | |
| 978 | wire spare1_inv_32x_unused; | |
| 979 | wire si_2; | |
| 980 | wire so_2; | |
| 981 | wire spare2_flop_unused; | |
| 982 | wire spare2_buf_32x_unused; | |
| 983 | wire spare2_nand3_8x_unused; | |
| 984 | wire spare2_inv_8x_unused; | |
| 985 | wire spare2_aoi22_4x_unused; | |
| 986 | wire spare2_buf_8x_unused; | |
| 987 | wire spare2_oai22_4x_unused; | |
| 988 | wire spare2_inv_16x_unused; | |
| 989 | wire spare2_nand2_16x_unused; | |
| 990 | wire spare2_nor3_4x_unused; | |
| 991 | wire spare2_nand2_8x_unused; | |
| 992 | wire spare2_buf_16x_unused; | |
| 993 | wire spare2_nor2_16x_unused; | |
| 994 | wire spare2_inv_32x_unused; | |
| 995 | wire si_3; | |
| 996 | wire so_3; | |
| 997 | wire spare3_flop_unused; | |
| 998 | wire spare3_buf_32x_unused; | |
| 999 | wire spare3_nand3_8x_unused; | |
| 1000 | wire spare3_inv_8x_unused; | |
| 1001 | wire spare3_aoi22_4x_unused; | |
| 1002 | wire spare3_buf_8x_unused; | |
| 1003 | wire spare3_oai22_4x_unused; | |
| 1004 | wire spare3_inv_16x_unused; | |
| 1005 | wire spare3_nand2_16x_unused; | |
| 1006 | wire spare3_nor3_4x_unused; | |
| 1007 | wire spare3_nand2_8x_unused; | |
| 1008 | wire spare3_buf_16x_unused; | |
| 1009 | wire spare3_nor2_16x_unused; | |
| 1010 | wire spare3_inv_32x_unused; | |
| 1011 | ||
| 1012 | ||
| 1013 | input l1clk; | |
| 1014 | input scan_in; | |
| 1015 | input siclk; | |
| 1016 | input soclk; | |
| 1017 | output scan_out; | |
| 1018 | ||
| 1019 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
| 1020 | .siclk(siclk), | |
| 1021 | .soclk(soclk), | |
| 1022 | .si(si_0), | |
| 1023 | .so(so_0), | |
| 1024 | .d(1'b0), | |
| 1025 | .q(spare0_flop_unused)); | |
| 1026 | assign si_0 = scan_in; | |
| 1027 | ||
| 1028 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
| 1029 | .out(spare0_buf_32x_unused)); | |
| 1030 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
| 1031 | .in1(1'b1), | |
| 1032 | .in2(1'b1), | |
| 1033 | .out(spare0_nand3_8x_unused)); | |
| 1034 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
| 1035 | .out(spare0_inv_8x_unused)); | |
| 1036 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
| 1037 | .in01(1'b1), | |
| 1038 | .in10(1'b1), | |
| 1039 | .in11(1'b1), | |
| 1040 | .out(spare0_aoi22_4x_unused)); | |
| 1041 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
| 1042 | .out(spare0_buf_8x_unused)); | |
| 1043 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
| 1044 | .in01(1'b1), | |
| 1045 | .in10(1'b1), | |
| 1046 | .in11(1'b1), | |
| 1047 | .out(spare0_oai22_4x_unused)); | |
| 1048 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
| 1049 | .out(spare0_inv_16x_unused)); | |
| 1050 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
| 1051 | .in1(1'b1), | |
| 1052 | .out(spare0_nand2_16x_unused)); | |
| 1053 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
| 1054 | .in1(1'b0), | |
| 1055 | .in2(1'b0), | |
| 1056 | .out(spare0_nor3_4x_unused)); | |
| 1057 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
| 1058 | .in1(1'b1), | |
| 1059 | .out(spare0_nand2_8x_unused)); | |
| 1060 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
| 1061 | .out(spare0_buf_16x_unused)); | |
| 1062 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
| 1063 | .in1(1'b0), | |
| 1064 | .out(spare0_nor2_16x_unused)); | |
| 1065 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
| 1066 | .out(spare0_inv_32x_unused)); | |
| 1067 | ||
| 1068 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
| 1069 | .siclk(siclk), | |
| 1070 | .soclk(soclk), | |
| 1071 | .si(si_1), | |
| 1072 | .so(so_1), | |
| 1073 | .d(1'b0), | |
| 1074 | .q(spare1_flop_unused)); | |
| 1075 | assign si_1 = so_0; | |
| 1076 | ||
| 1077 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
| 1078 | .out(spare1_buf_32x_unused)); | |
| 1079 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
| 1080 | .in1(1'b1), | |
| 1081 | .in2(1'b1), | |
| 1082 | .out(spare1_nand3_8x_unused)); | |
| 1083 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
| 1084 | .out(spare1_inv_8x_unused)); | |
| 1085 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
| 1086 | .in01(1'b1), | |
| 1087 | .in10(1'b1), | |
| 1088 | .in11(1'b1), | |
| 1089 | .out(spare1_aoi22_4x_unused)); | |
| 1090 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
| 1091 | .out(spare1_buf_8x_unused)); | |
| 1092 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
| 1093 | .in01(1'b1), | |
| 1094 | .in10(1'b1), | |
| 1095 | .in11(1'b1), | |
| 1096 | .out(spare1_oai22_4x_unused)); | |
| 1097 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
| 1098 | .out(spare1_inv_16x_unused)); | |
| 1099 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
| 1100 | .in1(1'b1), | |
| 1101 | .out(spare1_nand2_16x_unused)); | |
| 1102 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
| 1103 | .in1(1'b0), | |
| 1104 | .in2(1'b0), | |
| 1105 | .out(spare1_nor3_4x_unused)); | |
| 1106 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
| 1107 | .in1(1'b1), | |
| 1108 | .out(spare1_nand2_8x_unused)); | |
| 1109 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
| 1110 | .out(spare1_buf_16x_unused)); | |
| 1111 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
| 1112 | .in1(1'b0), | |
| 1113 | .out(spare1_nor2_16x_unused)); | |
| 1114 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
| 1115 | .out(spare1_inv_32x_unused)); | |
| 1116 | ||
| 1117 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
| 1118 | .siclk(siclk), | |
| 1119 | .soclk(soclk), | |
| 1120 | .si(si_2), | |
| 1121 | .so(so_2), | |
| 1122 | .d(1'b0), | |
| 1123 | .q(spare2_flop_unused)); | |
| 1124 | assign si_2 = so_1; | |
| 1125 | ||
| 1126 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
| 1127 | .out(spare2_buf_32x_unused)); | |
| 1128 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
| 1129 | .in1(1'b1), | |
| 1130 | .in2(1'b1), | |
| 1131 | .out(spare2_nand3_8x_unused)); | |
| 1132 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
| 1133 | .out(spare2_inv_8x_unused)); | |
| 1134 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
| 1135 | .in01(1'b1), | |
| 1136 | .in10(1'b1), | |
| 1137 | .in11(1'b1), | |
| 1138 | .out(spare2_aoi22_4x_unused)); | |
| 1139 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
| 1140 | .out(spare2_buf_8x_unused)); | |
| 1141 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
| 1142 | .in01(1'b1), | |
| 1143 | .in10(1'b1), | |
| 1144 | .in11(1'b1), | |
| 1145 | .out(spare2_oai22_4x_unused)); | |
| 1146 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
| 1147 | .out(spare2_inv_16x_unused)); | |
| 1148 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
| 1149 | .in1(1'b1), | |
| 1150 | .out(spare2_nand2_16x_unused)); | |
| 1151 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
| 1152 | .in1(1'b0), | |
| 1153 | .in2(1'b0), | |
| 1154 | .out(spare2_nor3_4x_unused)); | |
| 1155 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
| 1156 | .in1(1'b1), | |
| 1157 | .out(spare2_nand2_8x_unused)); | |
| 1158 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
| 1159 | .out(spare2_buf_16x_unused)); | |
| 1160 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
| 1161 | .in1(1'b0), | |
| 1162 | .out(spare2_nor2_16x_unused)); | |
| 1163 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
| 1164 | .out(spare2_inv_32x_unused)); | |
| 1165 | ||
| 1166 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
| 1167 | .siclk(siclk), | |
| 1168 | .soclk(soclk), | |
| 1169 | .si(si_3), | |
| 1170 | .so(so_3), | |
| 1171 | .d(1'b0), | |
| 1172 | .q(spare3_flop_unused)); | |
| 1173 | assign si_3 = so_2; | |
| 1174 | ||
| 1175 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
| 1176 | .out(spare3_buf_32x_unused)); | |
| 1177 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
| 1178 | .in1(1'b1), | |
| 1179 | .in2(1'b1), | |
| 1180 | .out(spare3_nand3_8x_unused)); | |
| 1181 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
| 1182 | .out(spare3_inv_8x_unused)); | |
| 1183 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
| 1184 | .in01(1'b1), | |
| 1185 | .in10(1'b1), | |
| 1186 | .in11(1'b1), | |
| 1187 | .out(spare3_aoi22_4x_unused)); | |
| 1188 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
| 1189 | .out(spare3_buf_8x_unused)); | |
| 1190 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
| 1191 | .in01(1'b1), | |
| 1192 | .in10(1'b1), | |
| 1193 | .in11(1'b1), | |
| 1194 | .out(spare3_oai22_4x_unused)); | |
| 1195 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
| 1196 | .out(spare3_inv_16x_unused)); | |
| 1197 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
| 1198 | .in1(1'b1), | |
| 1199 | .out(spare3_nand2_16x_unused)); | |
| 1200 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
| 1201 | .in1(1'b0), | |
| 1202 | .in2(1'b0), | |
| 1203 | .out(spare3_nor3_4x_unused)); | |
| 1204 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
| 1205 | .in1(1'b1), | |
| 1206 | .out(spare3_nand2_8x_unused)); | |
| 1207 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
| 1208 | .out(spare3_buf_16x_unused)); | |
| 1209 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
| 1210 | .in1(1'b0), | |
| 1211 | .out(spare3_nor2_16x_unused)); | |
| 1212 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
| 1213 | .out(spare3_inv_32x_unused)); | |
| 1214 | assign scan_out = so_3; | |
| 1215 | ||
| 1216 | ||
| 1217 | ||
| 1218 | endmodule | |
| 1219 | ||
| 1220 | ||
| 1221 | ||
| 1222 | ||
| 1223 | ||
| 1224 | ||
| 1225 | // any PARAMS parms go into naming of macro | |
| 1226 | ||
| 1227 | module l2t_deccck_ctl_msff_ctl_macro__width_3 ( | |
| 1228 | din, | |
| 1229 | l1clk, | |
| 1230 | scan_in, | |
| 1231 | siclk, | |
| 1232 | soclk, | |
| 1233 | dout, | |
| 1234 | scan_out); | |
| 1235 | wire [2:0] fdin; | |
| 1236 | wire [1:0] so; | |
| 1237 | ||
| 1238 | input [2:0] din; | |
| 1239 | input l1clk; | |
| 1240 | input scan_in; | |
| 1241 | ||
| 1242 | ||
| 1243 | input siclk; | |
| 1244 | input soclk; | |
| 1245 | ||
| 1246 | output [2:0] dout; | |
| 1247 | output scan_out; | |
| 1248 | assign fdin[2:0] = din[2:0]; | |
| 1249 | ||
| 1250 | ||
| 1251 | ||
| 1252 | ||
| 1253 | ||
| 1254 | ||
| 1255 | dff #(3) d0_0 ( | |
| 1256 | .l1clk(l1clk), | |
| 1257 | .siclk(siclk), | |
| 1258 | .soclk(soclk), | |
| 1259 | .d(fdin[2:0]), | |
| 1260 | .si({scan_in,so[1:0]}), | |
| 1261 | .so({so[1:0],scan_out}), | |
| 1262 | .q(dout[2:0]) | |
| 1263 | ); | |
| 1264 | ||
| 1265 | ||
| 1266 | ||
| 1267 | ||
| 1268 | ||
| 1269 | ||
| 1270 | ||
| 1271 | ||
| 1272 | ||
| 1273 | ||
| 1274 | ||
| 1275 | ||
| 1276 | endmodule | |
| 1277 | ||
| 1278 | ||
| 1279 | ||
| 1280 | ||
| 1281 | ||
| 1282 | ||
| 1283 | ||
| 1284 | ||
| 1285 | ||
| 1286 | ||
| 1287 | ||
| 1288 | ||
| 1289 | ||
| 1290 | // any PARAMS parms go into naming of macro | |
| 1291 | ||
| 1292 | module l2t_deccck_ctl_msff_ctl_macro__width_1 ( | |
| 1293 | din, | |
| 1294 | l1clk, | |
| 1295 | scan_in, | |
| 1296 | siclk, | |
| 1297 | soclk, | |
| 1298 | dout, | |
| 1299 | scan_out); | |
| 1300 | wire [0:0] fdin; | |
| 1301 | ||
| 1302 | input [0:0] din; | |
| 1303 | input l1clk; | |
| 1304 | input scan_in; | |
| 1305 | ||
| 1306 | ||
| 1307 | input siclk; | |
| 1308 | input soclk; | |
| 1309 | ||
| 1310 | output [0:0] dout; | |
| 1311 | output scan_out; | |
| 1312 | assign fdin[0:0] = din[0:0]; | |
| 1313 | ||
| 1314 | ||
| 1315 | ||
| 1316 | ||
| 1317 | ||
| 1318 | ||
| 1319 | dff #(1) d0_0 ( | |
| 1320 | .l1clk(l1clk), | |
| 1321 | .siclk(siclk), | |
| 1322 | .soclk(soclk), | |
| 1323 | .d(fdin[0:0]), | |
| 1324 | .si(scan_in), | |
| 1325 | .so(scan_out), | |
| 1326 | .q(dout[0:0]) | |
| 1327 | ); | |
| 1328 | ||
| 1329 | ||
| 1330 | ||
| 1331 | ||
| 1332 | ||
| 1333 | ||
| 1334 | ||
| 1335 | ||
| 1336 | ||
| 1337 | ||
| 1338 | ||
| 1339 | ||
| 1340 | endmodule | |
| 1341 | ||
| 1342 | ||
| 1343 | ||
| 1344 | ||
| 1345 | ||
| 1346 | ||
| 1347 | ||
| 1348 | ||
| 1349 | ||
| 1350 | ||
| 1351 | ||
| 1352 | ||
| 1353 | ||
| 1354 | // any PARAMS parms go into naming of macro | |
| 1355 | ||
| 1356 | module l2t_deccck_ctl_msff_ctl_macro__width_2 ( | |
| 1357 | din, | |
| 1358 | l1clk, | |
| 1359 | scan_in, | |
| 1360 | siclk, | |
| 1361 | soclk, | |
| 1362 | dout, | |
| 1363 | scan_out); | |
| 1364 | wire [1:0] fdin; | |
| 1365 | wire [0:0] so; | |
| 1366 | ||
| 1367 | input [1:0] din; | |
| 1368 | input l1clk; | |
| 1369 | input scan_in; | |
| 1370 | ||
| 1371 | ||
| 1372 | input siclk; | |
| 1373 | input soclk; | |
| 1374 | ||
| 1375 | output [1:0] dout; | |
| 1376 | output scan_out; | |
| 1377 | assign fdin[1:0] = din[1:0]; | |
| 1378 | ||
| 1379 | ||
| 1380 | ||
| 1381 | ||
| 1382 | ||
| 1383 | ||
| 1384 | dff #(2) d0_0 ( | |
| 1385 | .l1clk(l1clk), | |
| 1386 | .siclk(siclk), | |
| 1387 | .soclk(soclk), | |
| 1388 | .d(fdin[1:0]), | |
| 1389 | .si({scan_in,so[0:0]}), | |
| 1390 | .so({so[0:0],scan_out}), | |
| 1391 | .q(dout[1:0]) | |
| 1392 | ); | |
| 1393 | ||
| 1394 | ||
| 1395 | ||
| 1396 | ||
| 1397 | ||
| 1398 | ||
| 1399 | ||
| 1400 | ||
| 1401 | ||
| 1402 | ||
| 1403 | ||
| 1404 | ||
| 1405 | endmodule | |
| 1406 | ||
| 1407 | ||
| 1408 | ||
| 1409 | ||
| 1410 | ||
| 1411 | ||
| 1412 | ||
| 1413 | ||
| 1414 | ||
| 1415 | ||
| 1416 | ||
| 1417 | ||
| 1418 | ||
| 1419 | // any PARAMS parms go into naming of macro | |
| 1420 | ||
| 1421 | module l2t_deccck_ctl_msff_ctl_macro__width_4 ( | |
| 1422 | din, | |
| 1423 | l1clk, | |
| 1424 | scan_in, | |
| 1425 | siclk, | |
| 1426 | soclk, | |
| 1427 | dout, | |
| 1428 | scan_out); | |
| 1429 | wire [3:0] fdin; | |
| 1430 | wire [2:0] so; | |
| 1431 | ||
| 1432 | input [3:0] din; | |
| 1433 | input l1clk; | |
| 1434 | input scan_in; | |
| 1435 | ||
| 1436 | ||
| 1437 | input siclk; | |
| 1438 | input soclk; | |
| 1439 | ||
| 1440 | output [3:0] dout; | |
| 1441 | output scan_out; | |
| 1442 | assign fdin[3:0] = din[3:0]; | |
| 1443 | ||
| 1444 | ||
| 1445 | ||
| 1446 | ||
| 1447 | ||
| 1448 | ||
| 1449 | dff #(4) d0_0 ( | |
| 1450 | .l1clk(l1clk), | |
| 1451 | .siclk(siclk), | |
| 1452 | .soclk(soclk), | |
| 1453 | .d(fdin[3:0]), | |
| 1454 | .si({scan_in,so[2:0]}), | |
| 1455 | .so({so[2:0],scan_out}), | |
| 1456 | .q(dout[3:0]) | |
| 1457 | ); | |
| 1458 | ||
| 1459 | ||
| 1460 | ||
| 1461 | ||
| 1462 | ||
| 1463 | ||
| 1464 | ||
| 1465 | ||
| 1466 | ||
| 1467 | ||
| 1468 | ||
| 1469 | ||
| 1470 | endmodule | |
| 1471 | ||
| 1472 | ||
| 1473 | ||
| 1474 | ||
| 1475 | ||
| 1476 | ||
| 1477 | ||
| 1478 |