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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_dir_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_dir_ctl ( | |
36 | aclk, | |
37 | bclk, | |
38 | dirlbf_lkup_en_c4_buf, | |
39 | dirlbf_inval_mask_c4_buf, | |
40 | dirlbf_rw_dec_c4_buf, | |
41 | dirlbf_rd_en_c4_buf, | |
42 | dirlbf_wr_en_c4_buf, | |
43 | dirlbf_rw_entry_c4_buf, | |
44 | dirlbf_dir_clear_c4_buf, | |
45 | l1clk, | |
46 | scan_in, | |
47 | scan_out, | |
48 | dir_rd_data_en_c4, | |
49 | dir_wr_data_en_c4, | |
50 | dir_cam_en_c4, | |
51 | dir_rw_entry_c4, | |
52 | dir_inval_mask_c4, | |
53 | dir_warm_rst_c4, | |
54 | select_panel0, | |
55 | select_panel1, | |
56 | select_panel2, | |
57 | select_panel3, | |
58 | l2t_mb0_run); | |
59 | wire siclk; | |
60 | wire soclk; | |
61 | wire spares_scanin; | |
62 | wire spares_scanout; | |
63 | wire l2t_mb0_run_r1; | |
64 | wire ff_rd_data_en_c5_en_scanin; | |
65 | wire ff_rd_data_en_c5_en_scanout; | |
66 | wire ff_rd_data_en_c5_scanin; | |
67 | wire ff_rd_data_en_c5_scanout; | |
68 | wire ff_select_panel0_scanin; | |
69 | wire ff_select_panel0_scanout; | |
70 | ||
71 | ||
72 | input aclk; | |
73 | input bclk; | |
74 | input [3:0] dirlbf_lkup_en_c4_buf ; // Right | |
75 | input [7:0] dirlbf_inval_mask_c4_buf ; // Right | |
76 | input [3:0] dirlbf_rw_dec_c4_buf; // Right | |
77 | input dirlbf_rd_en_c4_buf ; // Right | |
78 | input dirlbf_wr_en_c4_buf ; // Right | |
79 | input [5:0] dirlbf_rw_entry_c4_buf; // BS and SR 11/18/03 Reverse Directory change | |
80 | input dirlbf_dir_clear_c4_buf ; // | |
81 | input l1clk; | |
82 | input scan_in; | |
83 | output scan_out; | |
84 | ||
85 | output [3:0] dir_rd_data_en_c4; //( 0 leftTOp, 1 rightTOp, 2 leftBOttom 3 RightBottom ) | |
86 | output [3:0] dir_wr_data_en_c4; | |
87 | output [3:0] dir_cam_en_c4; //( 0 leftTOp, 1 rightTOp, 2 leftBOttom 3 RightBottom ) | |
88 | ||
89 | // Pins on TOP | |
90 | output [5:0] dir_rw_entry_c4; // BS and SR 11/18/03 Reverse Directory change | |
91 | output [7:0] dir_inval_mask_c4; // one output | |
92 | output dir_warm_rst_c4; | |
93 | output select_panel0 ; | |
94 | output select_panel1 ; | |
95 | output select_panel2 ; | |
96 | output select_panel3 ; | |
97 | input l2t_mb0_run; | |
98 | ||
99 | ||
100 | ////////////////////////////////////////////////// | |
101 | // L1 clk header | |
102 | ////////////////////////////////////////////////// | |
103 | assign siclk = aclk; | |
104 | assign soclk = bclk; | |
105 | ////////////////////////////////////////// | |
106 | // Spare gate insertion | |
107 | ////////////////////////////////////////// | |
108 | l2t_dir_ctl_spare_ctl_macro__num_4 spares ( | |
109 | .scan_in(spares_scanin), | |
110 | .scan_out(spares_scanout), | |
111 | .l1clk (l1clk), | |
112 | .siclk(siclk), | |
113 | .soclk(soclk) | |
114 | ); | |
115 | ////////////////////////////////////////// | |
116 | wire [3:0] rd_data_en_c5; //( 0 leftTOp, 1 rightTOp, 2 leftBOttom 3 RightBottom ) | |
117 | ||
118 | assign dir_warm_rst_c4 = dirlbf_dir_clear_c4_buf ; | |
119 | assign dir_rd_data_en_c4 = {4{dirlbf_rd_en_c4_buf}} & dirlbf_rw_dec_c4_buf ; | |
120 | assign dir_wr_data_en_c4 = l2t_mb0_run_r1 ? ({4{dirlbf_wr_en_c4_buf}} & dirlbf_rw_dec_c4_buf) : | |
121 | ({4{dirlbf_wr_en_c4_buf & ~dir_warm_rst_c4}} & dirlbf_rw_dec_c4_buf); | |
122 | ||
123 | l2t_dir_ctl_msff_ctl_macro__width_3 ff_rd_data_en_c5_en | |
124 | ( | |
125 | .dout ({l2t_mb0_run_r1,rd_data_en_c5[1:0]}), | |
126 | .din ({l2t_mb0_run,dir_rd_data_en_c4[1:0]}), | |
127 | .scan_in(ff_rd_data_en_c5_en_scanin), | |
128 | .scan_out(ff_rd_data_en_c5_en_scanout), | |
129 | .l1clk (l1clk), | |
130 | .siclk(siclk), | |
131 | .soclk(soclk) | |
132 | ); | |
133 | ||
134 | l2t_dir_ctl_msff_ctl_macro__width_2 ff_rd_data_en_c5 | |
135 | (.dout (rd_data_en_c5[3:2]), .din (dir_rd_data_en_c4[3:2]), | |
136 | .scan_in(ff_rd_data_en_c5_scanin), | |
137 | .scan_out(ff_rd_data_en_c5_scanout), | |
138 | .l1clk (l1clk), | |
139 | .siclk(siclk), | |
140 | .soclk(soclk) | |
141 | ); | |
142 | l2t_dir_ctl_msff_ctl_macro__width_4 ff_select_panel0 | |
143 | ( | |
144 | .scan_in(ff_select_panel0_scanin), | |
145 | .scan_out(ff_select_panel0_scanout), | |
146 | .dout ({select_panel3,select_panel2,select_panel1,select_panel0}), | |
147 | .din (rd_data_en_c5[3:0]), | |
148 | .l1clk (l1clk), | |
149 | .siclk(siclk), | |
150 | .soclk(soclk) | |
151 | ); | |
152 | ||
153 | assign dir_cam_en_c4[3:0] = dirlbf_lkup_en_c4_buf[3:0]; | |
154 | assign dir_inval_mask_c4[7:0] = dirlbf_inval_mask_c4_buf[7:0]; | |
155 | assign dir_rw_entry_c4[5:0] = dirlbf_rw_entry_c4_buf[5:0]; | |
156 | ||
157 | // fixscan start: | |
158 | assign spares_scanin = scan_in ; | |
159 | assign ff_rd_data_en_c5_en_scanin = spares_scanout ; | |
160 | assign ff_rd_data_en_c5_scanin = ff_rd_data_en_c5_en_scanout; | |
161 | assign ff_select_panel0_scanin = ff_rd_data_en_c5_scanout ; | |
162 | assign scan_out = ff_select_panel0_scanout ; | |
163 | // fixscan end: | |
164 | endmodule | |
165 | ||
166 | ||
167 | ||
168 | ||
169 | // Description: Spare gate macro for control blocks | |
170 | // | |
171 | // Param num controls the number of times the macro is added | |
172 | // flops=0 can be used to use only combination spare logic | |
173 | ||
174 | ||
175 | module l2t_dir_ctl_spare_ctl_macro__num_4 ( | |
176 | l1clk, | |
177 | scan_in, | |
178 | siclk, | |
179 | soclk, | |
180 | scan_out); | |
181 | wire si_0; | |
182 | wire so_0; | |
183 | wire spare0_flop_unused; | |
184 | wire spare0_buf_32x_unused; | |
185 | wire spare0_nand3_8x_unused; | |
186 | wire spare0_inv_8x_unused; | |
187 | wire spare0_aoi22_4x_unused; | |
188 | wire spare0_buf_8x_unused; | |
189 | wire spare0_oai22_4x_unused; | |
190 | wire spare0_inv_16x_unused; | |
191 | wire spare0_nand2_16x_unused; | |
192 | wire spare0_nor3_4x_unused; | |
193 | wire spare0_nand2_8x_unused; | |
194 | wire spare0_buf_16x_unused; | |
195 | wire spare0_nor2_16x_unused; | |
196 | wire spare0_inv_32x_unused; | |
197 | wire si_1; | |
198 | wire so_1; | |
199 | wire spare1_flop_unused; | |
200 | wire spare1_buf_32x_unused; | |
201 | wire spare1_nand3_8x_unused; | |
202 | wire spare1_inv_8x_unused; | |
203 | wire spare1_aoi22_4x_unused; | |
204 | wire spare1_buf_8x_unused; | |
205 | wire spare1_oai22_4x_unused; | |
206 | wire spare1_inv_16x_unused; | |
207 | wire spare1_nand2_16x_unused; | |
208 | wire spare1_nor3_4x_unused; | |
209 | wire spare1_nand2_8x_unused; | |
210 | wire spare1_buf_16x_unused; | |
211 | wire spare1_nor2_16x_unused; | |
212 | wire spare1_inv_32x_unused; | |
213 | wire si_2; | |
214 | wire so_2; | |
215 | wire spare2_flop_unused; | |
216 | wire spare2_buf_32x_unused; | |
217 | wire spare2_nand3_8x_unused; | |
218 | wire spare2_inv_8x_unused; | |
219 | wire spare2_aoi22_4x_unused; | |
220 | wire spare2_buf_8x_unused; | |
221 | wire spare2_oai22_4x_unused; | |
222 | wire spare2_inv_16x_unused; | |
223 | wire spare2_nand2_16x_unused; | |
224 | wire spare2_nor3_4x_unused; | |
225 | wire spare2_nand2_8x_unused; | |
226 | wire spare2_buf_16x_unused; | |
227 | wire spare2_nor2_16x_unused; | |
228 | wire spare2_inv_32x_unused; | |
229 | wire si_3; | |
230 | wire so_3; | |
231 | wire spare3_flop_unused; | |
232 | wire spare3_buf_32x_unused; | |
233 | wire spare3_nand3_8x_unused; | |
234 | wire spare3_inv_8x_unused; | |
235 | wire spare3_aoi22_4x_unused; | |
236 | wire spare3_buf_8x_unused; | |
237 | wire spare3_oai22_4x_unused; | |
238 | wire spare3_inv_16x_unused; | |
239 | wire spare3_nand2_16x_unused; | |
240 | wire spare3_nor3_4x_unused; | |
241 | wire spare3_nand2_8x_unused; | |
242 | wire spare3_buf_16x_unused; | |
243 | wire spare3_nor2_16x_unused; | |
244 | wire spare3_inv_32x_unused; | |
245 | ||
246 | ||
247 | input l1clk; | |
248 | input scan_in; | |
249 | input siclk; | |
250 | input soclk; | |
251 | output scan_out; | |
252 | ||
253 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
254 | .siclk(siclk), | |
255 | .soclk(soclk), | |
256 | .si(si_0), | |
257 | .so(so_0), | |
258 | .d(1'b0), | |
259 | .q(spare0_flop_unused)); | |
260 | assign si_0 = scan_in; | |
261 | ||
262 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
263 | .out(spare0_buf_32x_unused)); | |
264 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
265 | .in1(1'b1), | |
266 | .in2(1'b1), | |
267 | .out(spare0_nand3_8x_unused)); | |
268 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
269 | .out(spare0_inv_8x_unused)); | |
270 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
271 | .in01(1'b1), | |
272 | .in10(1'b1), | |
273 | .in11(1'b1), | |
274 | .out(spare0_aoi22_4x_unused)); | |
275 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
276 | .out(spare0_buf_8x_unused)); | |
277 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
278 | .in01(1'b1), | |
279 | .in10(1'b1), | |
280 | .in11(1'b1), | |
281 | .out(spare0_oai22_4x_unused)); | |
282 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
283 | .out(spare0_inv_16x_unused)); | |
284 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
285 | .in1(1'b1), | |
286 | .out(spare0_nand2_16x_unused)); | |
287 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
288 | .in1(1'b0), | |
289 | .in2(1'b0), | |
290 | .out(spare0_nor3_4x_unused)); | |
291 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
292 | .in1(1'b1), | |
293 | .out(spare0_nand2_8x_unused)); | |
294 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
295 | .out(spare0_buf_16x_unused)); | |
296 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
297 | .in1(1'b0), | |
298 | .out(spare0_nor2_16x_unused)); | |
299 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
300 | .out(spare0_inv_32x_unused)); | |
301 | ||
302 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
303 | .siclk(siclk), | |
304 | .soclk(soclk), | |
305 | .si(si_1), | |
306 | .so(so_1), | |
307 | .d(1'b0), | |
308 | .q(spare1_flop_unused)); | |
309 | assign si_1 = so_0; | |
310 | ||
311 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
312 | .out(spare1_buf_32x_unused)); | |
313 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
314 | .in1(1'b1), | |
315 | .in2(1'b1), | |
316 | .out(spare1_nand3_8x_unused)); | |
317 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
318 | .out(spare1_inv_8x_unused)); | |
319 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
320 | .in01(1'b1), | |
321 | .in10(1'b1), | |
322 | .in11(1'b1), | |
323 | .out(spare1_aoi22_4x_unused)); | |
324 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
325 | .out(spare1_buf_8x_unused)); | |
326 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
327 | .in01(1'b1), | |
328 | .in10(1'b1), | |
329 | .in11(1'b1), | |
330 | .out(spare1_oai22_4x_unused)); | |
331 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
332 | .out(spare1_inv_16x_unused)); | |
333 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
334 | .in1(1'b1), | |
335 | .out(spare1_nand2_16x_unused)); | |
336 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
337 | .in1(1'b0), | |
338 | .in2(1'b0), | |
339 | .out(spare1_nor3_4x_unused)); | |
340 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
341 | .in1(1'b1), | |
342 | .out(spare1_nand2_8x_unused)); | |
343 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
344 | .out(spare1_buf_16x_unused)); | |
345 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
346 | .in1(1'b0), | |
347 | .out(spare1_nor2_16x_unused)); | |
348 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
349 | .out(spare1_inv_32x_unused)); | |
350 | ||
351 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
352 | .siclk(siclk), | |
353 | .soclk(soclk), | |
354 | .si(si_2), | |
355 | .so(so_2), | |
356 | .d(1'b0), | |
357 | .q(spare2_flop_unused)); | |
358 | assign si_2 = so_1; | |
359 | ||
360 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
361 | .out(spare2_buf_32x_unused)); | |
362 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
363 | .in1(1'b1), | |
364 | .in2(1'b1), | |
365 | .out(spare2_nand3_8x_unused)); | |
366 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
367 | .out(spare2_inv_8x_unused)); | |
368 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
369 | .in01(1'b1), | |
370 | .in10(1'b1), | |
371 | .in11(1'b1), | |
372 | .out(spare2_aoi22_4x_unused)); | |
373 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
374 | .out(spare2_buf_8x_unused)); | |
375 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
376 | .in01(1'b1), | |
377 | .in10(1'b1), | |
378 | .in11(1'b1), | |
379 | .out(spare2_oai22_4x_unused)); | |
380 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
381 | .out(spare2_inv_16x_unused)); | |
382 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
383 | .in1(1'b1), | |
384 | .out(spare2_nand2_16x_unused)); | |
385 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
386 | .in1(1'b0), | |
387 | .in2(1'b0), | |
388 | .out(spare2_nor3_4x_unused)); | |
389 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
390 | .in1(1'b1), | |
391 | .out(spare2_nand2_8x_unused)); | |
392 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
393 | .out(spare2_buf_16x_unused)); | |
394 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
395 | .in1(1'b0), | |
396 | .out(spare2_nor2_16x_unused)); | |
397 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
398 | .out(spare2_inv_32x_unused)); | |
399 | ||
400 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
401 | .siclk(siclk), | |
402 | .soclk(soclk), | |
403 | .si(si_3), | |
404 | .so(so_3), | |
405 | .d(1'b0), | |
406 | .q(spare3_flop_unused)); | |
407 | assign si_3 = so_2; | |
408 | ||
409 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
410 | .out(spare3_buf_32x_unused)); | |
411 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
412 | .in1(1'b1), | |
413 | .in2(1'b1), | |
414 | .out(spare3_nand3_8x_unused)); | |
415 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
416 | .out(spare3_inv_8x_unused)); | |
417 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
418 | .in01(1'b1), | |
419 | .in10(1'b1), | |
420 | .in11(1'b1), | |
421 | .out(spare3_aoi22_4x_unused)); | |
422 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
423 | .out(spare3_buf_8x_unused)); | |
424 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
425 | .in01(1'b1), | |
426 | .in10(1'b1), | |
427 | .in11(1'b1), | |
428 | .out(spare3_oai22_4x_unused)); | |
429 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
430 | .out(spare3_inv_16x_unused)); | |
431 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
432 | .in1(1'b1), | |
433 | .out(spare3_nand2_16x_unused)); | |
434 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
435 | .in1(1'b0), | |
436 | .in2(1'b0), | |
437 | .out(spare3_nor3_4x_unused)); | |
438 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
439 | .in1(1'b1), | |
440 | .out(spare3_nand2_8x_unused)); | |
441 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
442 | .out(spare3_buf_16x_unused)); | |
443 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
444 | .in1(1'b0), | |
445 | .out(spare3_nor2_16x_unused)); | |
446 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
447 | .out(spare3_inv_32x_unused)); | |
448 | assign scan_out = so_3; | |
449 | ||
450 | ||
451 | ||
452 | endmodule | |
453 | ||
454 | ||
455 | ||
456 | ||
457 | ||
458 | ||
459 | // any PARAMS parms go into naming of macro | |
460 | ||
461 | module l2t_dir_ctl_msff_ctl_macro__width_3 ( | |
462 | din, | |
463 | l1clk, | |
464 | scan_in, | |
465 | siclk, | |
466 | soclk, | |
467 | dout, | |
468 | scan_out); | |
469 | wire [2:0] fdin; | |
470 | wire [1:0] so; | |
471 | ||
472 | input [2:0] din; | |
473 | input l1clk; | |
474 | input scan_in; | |
475 | ||
476 | ||
477 | input siclk; | |
478 | input soclk; | |
479 | ||
480 | output [2:0] dout; | |
481 | output scan_out; | |
482 | assign fdin[2:0] = din[2:0]; | |
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | dff #(3) d0_0 ( | |
490 | .l1clk(l1clk), | |
491 | .siclk(siclk), | |
492 | .soclk(soclk), | |
493 | .d(fdin[2:0]), | |
494 | .si({scan_in,so[1:0]}), | |
495 | .so({so[1:0],scan_out}), | |
496 | .q(dout[2:0]) | |
497 | ); | |
498 | ||
499 | ||
500 | ||
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | endmodule | |
511 | ||
512 | ||
513 | ||
514 | ||
515 | ||
516 | ||
517 | ||
518 | ||
519 | ||
520 | ||
521 | ||
522 | ||
523 | ||
524 | // any PARAMS parms go into naming of macro | |
525 | ||
526 | module l2t_dir_ctl_msff_ctl_macro__width_2 ( | |
527 | din, | |
528 | l1clk, | |
529 | scan_in, | |
530 | siclk, | |
531 | soclk, | |
532 | dout, | |
533 | scan_out); | |
534 | wire [1:0] fdin; | |
535 | wire [0:0] so; | |
536 | ||
537 | input [1:0] din; | |
538 | input l1clk; | |
539 | input scan_in; | |
540 | ||
541 | ||
542 | input siclk; | |
543 | input soclk; | |
544 | ||
545 | output [1:0] dout; | |
546 | output scan_out; | |
547 | assign fdin[1:0] = din[1:0]; | |
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | dff #(2) d0_0 ( | |
555 | .l1clk(l1clk), | |
556 | .siclk(siclk), | |
557 | .soclk(soclk), | |
558 | .d(fdin[1:0]), | |
559 | .si({scan_in,so[0:0]}), | |
560 | .so({so[0:0],scan_out}), | |
561 | .q(dout[1:0]) | |
562 | ); | |
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | ||
575 | endmodule | |
576 | ||
577 | ||
578 | ||
579 | ||
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
585 | ||
586 | ||
587 | ||
588 | ||
589 | // any PARAMS parms go into naming of macro | |
590 | ||
591 | module l2t_dir_ctl_msff_ctl_macro__width_4 ( | |
592 | din, | |
593 | l1clk, | |
594 | scan_in, | |
595 | siclk, | |
596 | soclk, | |
597 | dout, | |
598 | scan_out); | |
599 | wire [3:0] fdin; | |
600 | wire [2:0] so; | |
601 | ||
602 | input [3:0] din; | |
603 | input l1clk; | |
604 | input scan_in; | |
605 | ||
606 | ||
607 | input siclk; | |
608 | input soclk; | |
609 | ||
610 | output [3:0] dout; | |
611 | output scan_out; | |
612 | assign fdin[3:0] = din[3:0]; | |
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | dff #(4) d0_0 ( | |
620 | .l1clk(l1clk), | |
621 | .siclk(siclk), | |
622 | .soclk(soclk), | |
623 | .d(fdin[3:0]), | |
624 | .si({scan_in,so[2:0]}), | |
625 | .so({so[2:0],scan_out}), | |
626 | .q(dout[3:0]) | |
627 | ); | |
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | ||
640 | endmodule | |
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | ||
648 |