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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_dirtop_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_dirtop_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | scan_out, | |
39 | tcu_pce_ov, | |
40 | tcu_aclk, | |
41 | tcu_bclk, | |
42 | tcu_scan_en, | |
43 | dir_rd_data_en_c4, | |
44 | dir_wr_data_en_c4, | |
45 | dir_cam_en_c4, | |
46 | dir_rw_entry_c4, | |
47 | dir_inval_mask_c4, | |
48 | dir_warm_rst_c4, | |
49 | dirlbf_lkup_wr_data_c4_buf, | |
50 | dirlbf_force_hit_c4, | |
51 | arb_force_hit_c4, | |
52 | select_panel0, | |
53 | select_panel1, | |
54 | select_panel2, | |
55 | select_panel3, | |
56 | l2t_mb0_run, | |
57 | l2t_mb0_mask, | |
58 | l2t_mb0_addr, | |
59 | l2t_mb0_row_panel_en, | |
60 | l2t_mb0_row_row_en, | |
61 | l2t_mb0_row_lookup_en, | |
62 | l2t_mb0_lookup_wdata, | |
63 | l2t_mb0_row_wr_en, | |
64 | l2t_mb0_row_rd_en, | |
65 | ic_dc_dir, | |
66 | arbadr_arbdp_addr4_c4, | |
67 | dirrep_rd_en_c4, | |
68 | dirrep_wr_en_c4, | |
69 | addr_index_bit5, | |
70 | dirrep_inval_mask_c4, | |
71 | dirrep_rdwr_row_en_c4, | |
72 | dirrep_lkup_row_dec_c4, | |
73 | dirrep_lkup_panel_dec_c4, | |
74 | dirrep_rdwr_panel_dec_c4, | |
75 | dirrep_rw_entry_c4, | |
76 | lkup_wr_data_c4, | |
77 | dir_clear_c4); | |
78 | wire pce_ov; | |
79 | wire stop; | |
80 | wire siclk; | |
81 | wire soclk; | |
82 | wire se; | |
83 | wire l1clk; | |
84 | wire ic_ctl_0145_scanin; | |
85 | wire ic_ctl_0145_scanout; | |
86 | wire [3:0] ic_lkup_en_c4_buf_row0; | |
87 | wire [7:0] ic_inv_mask_c4_buf_row0; | |
88 | wire [3:0] ic_rw_dec_c4_buf_row0; | |
89 | wire ic_rd_en_c4_buf_row0; | |
90 | wire ic_wr_en_c4_buf_row0; | |
91 | wire [5:0] ic_rw_entry_c4_buf_row0; | |
92 | wire ic_dir_clear_c4_buf_row0; | |
93 | wire ic_buf_row0_scanin; | |
94 | wire ic_buf_row0_scanout; | |
95 | ||
96 | ||
97 | input l2clk; | |
98 | input scan_in; | |
99 | output scan_out; | |
100 | ||
101 | input tcu_pce_ov; | |
102 | input tcu_aclk; | |
103 | input tcu_bclk; | |
104 | input tcu_scan_en; | |
105 | ||
106 | output [3:0] dir_rd_data_en_c4; | |
107 | output [3:0] dir_wr_data_en_c4; | |
108 | output [3:0] dir_cam_en_c4; | |
109 | output [5:0] dir_rw_entry_c4; | |
110 | output [7:0] dir_inval_mask_c4; | |
111 | output dir_warm_rst_c4; | |
112 | output [15:0] dirlbf_lkup_wr_data_c4_buf; | |
113 | output dirlbf_force_hit_c4; | |
114 | input arb_force_hit_c4; | |
115 | ||
116 | output select_panel0; | |
117 | output select_panel1; | |
118 | output select_panel2; | |
119 | output select_panel3; | |
120 | ||
121 | ||
122 | input l2t_mb0_run; | |
123 | input [7:0] l2t_mb0_mask; | |
124 | input [5:0] l2t_mb0_addr; | |
125 | input [3:0] l2t_mb0_row_panel_en; | |
126 | input l2t_mb0_row_row_en; | |
127 | input [3:0] l2t_mb0_row_lookup_en; | |
128 | input [15:0] l2t_mb0_lookup_wdata; | |
129 | input l2t_mb0_row_wr_en; | |
130 | input l2t_mb0_row_rd_en; | |
131 | ||
132 | ||
133 | input ic_dc_dir; | |
134 | input arbadr_arbdp_addr4_c4; | |
135 | input dirrep_rd_en_c4; | |
136 | input dirrep_wr_en_c4; | |
137 | input addr_index_bit5; | |
138 | input [7:0] dirrep_inval_mask_c4; | |
139 | input [1:0] dirrep_rdwr_row_en_c4; | |
140 | input [1:0] dirrep_lkup_row_dec_c4; | |
141 | input [3:0] dirrep_lkup_panel_dec_c4; | |
142 | input [3:0] dirrep_rdwr_panel_dec_c4; | |
143 | input [5:0] dirrep_rw_entry_c4; | |
144 | input [14:0] lkup_wr_data_c4; | |
145 | input dir_clear_c4; | |
146 | ||
147 | ||
148 | ////////////////////////////////////////////////// | |
149 | // L1 clk header | |
150 | ////////////////////////////////////////////////// | |
151 | assign pce_ov = tcu_pce_ov; | |
152 | assign stop = 1'b0; | |
153 | assign siclk = tcu_aclk; | |
154 | assign soclk = tcu_bclk; | |
155 | assign se = tcu_scan_en; | |
156 | ||
157 | l2t_dirtop_ctl_l1clkhdr_ctl_macro clkgen ( | |
158 | .l2clk(l2clk), | |
159 | .l1en(1'b1 ), | |
160 | .l1clk(l1clk), | |
161 | .pce_ov(pce_ov), | |
162 | .stop(stop), | |
163 | .se(se)); | |
164 | ||
165 | ////////////////////////////////////////// | |
166 | ||
167 | l2t_dir_ctl dir_ctl_0145( | |
168 | .aclk(siclk), | |
169 | .bclk(soclk), | |
170 | .scan_in(ic_ctl_0145_scanin), | |
171 | .scan_out(ic_ctl_0145_scanout), | |
172 | .l1clk (l1clk), | |
173 | // Outputs | |
174 | .dir_rd_data_en_c4(dir_rd_data_en_c4[3:0]), // to cam | |
175 | .dir_wr_data_en_c4(dir_wr_data_en_c4[3:0]),// to cam | |
176 | .dir_cam_en_c4 (dir_cam_en_c4[3:0]),// to cam | |
177 | .dir_rw_entry_c4 (dir_rw_entry_c4[5:0]),// to cam | |
178 | .dir_inval_mask_c4(dir_inval_mask_c4[7:0]),// to cam | |
179 | .dir_warm_rst_c4 (dir_warm_rst_c4), // to cam | |
180 | .select_panel0(select_panel0), // to dirout | |
181 | .select_panel1(select_panel1),// to dirout | |
182 | .select_panel2(select_panel2),// to dirout | |
183 | .select_panel3(select_panel3),// to dirout | |
184 | // Inputs | |
185 | .dirlbf_lkup_en_c4_buf(ic_lkup_en_c4_buf_row0[3:0]), | |
186 | .dirlbf_inval_mask_c4_buf(ic_inv_mask_c4_buf_row0[7:0]), | |
187 | .dirlbf_rw_dec_c4_buf(ic_rw_dec_c4_buf_row0[3:0]), | |
188 | .dirlbf_rd_en_c4_buf (ic_rd_en_c4_buf_row0), | |
189 | .dirlbf_wr_en_c4_buf (ic_wr_en_c4_buf_row0), | |
190 | .dirlbf_rw_entry_c4_buf(ic_rw_entry_c4_buf_row0[5:0]), | |
191 | .dirlbf_dir_clear_c4_buf(ic_dir_clear_c4_buf_row0), | |
192 | .l2t_mb0_run(l2t_mb0_run)); | |
193 | ||
194 | ||
195 | //l2t_dirlbf_dp ic_buf_row0 ( | |
196 | l2t_dirbuf_ctl buf_row0 ( | |
197 | // Outputs | |
198 | .dirlbf_lkup_wr_data_c4_buf(dirlbf_lkup_wr_data_c4_buf[15:0]), | |
199 | .dirlbf_lkup_en_c4_buf(ic_lkup_en_c4_buf_row0[3:0]), | |
200 | .dirlbf_inval_mask_c4_buf(ic_inv_mask_c4_buf_row0[7:0]), | |
201 | .dirlbf_rw_dec_c4_buf(ic_rw_dec_c4_buf_row0[3:0]), | |
202 | .dirlbf_rd_en_c4_buf(ic_rd_en_c4_buf_row0), | |
203 | .dirlbf_wr_en_c4_buf(ic_wr_en_c4_buf_row0), | |
204 | .dirlbf_rw_entry_c4_buf(ic_rw_entry_c4_buf_row0[5:0]), | |
205 | .dirlbf_dir_clear_c4_buf(ic_dir_clear_c4_buf_row0), | |
206 | .dirlbf_force_hit_c4 (dirlbf_force_hit_c4), | |
207 | // Inputs | |
208 | .aclk(siclk), | |
209 | .bclk(soclk), | |
210 | .scan_in(ic_buf_row0_scanin), | |
211 | .scan_out(ic_buf_row0_scanout), | |
212 | .l1clk (l1clk), | |
213 | .l2t_mb0_run (l2t_mb0_run), | |
214 | .l2t_mb0_mask (l2t_mb0_mask[7:0]), | |
215 | .l2t_mb0_addr (l2t_mb0_addr[5:0]), | |
216 | .l2t_mb0_lookup_wdata (l2t_mb0_lookup_wdata[15:0]), | |
217 | .l2t_mb0_row_wr_en (l2t_mb0_row_wr_en), | |
218 | .l2t_mb0_row_rd_en (l2t_mb0_row_rd_en), | |
219 | .l2t_mb0_row_lookup_en (l2t_mb0_row_lookup_en[3:0]), | |
220 | .l2t_mb0_row_row_en (l2t_mb0_row_row_en), | |
221 | .l2t_mb0_row_panel_en (l2t_mb0_row_panel_en[3:0]), | |
222 | .arb_force_hit_c4 (arb_force_hit_c4), | |
223 | .ic_dc_dir (ic_dc_dir), | |
224 | .arbadr_arbdp_addr4_c4 (arbadr_arbdp_addr4_c4), | |
225 | .rd_en_c4 (dirrep_rd_en_c4), | |
226 | .wr_en_c4 (dirrep_wr_en_c4), | |
227 | .addr_index_bit5 (addr_index_bit5), | |
228 | .dir_inval_mask_c4(dirrep_inval_mask_c4[7:0]), | |
229 | .rw_row_en_c4(dirrep_rdwr_row_en_c4[1:0]), | |
230 | .rw_panel_en_c4(dirrep_rdwr_panel_dec_c4[3:0]), | |
231 | .dir_rw_entry_c4(dirrep_rw_entry_c4[5:0]), | |
232 | .lkup_row_en_c4(dirrep_lkup_row_dec_c4[1:0]), | |
233 | .lkup_panel_en_c4(dirrep_lkup_panel_dec_c4[3:0]), | |
234 | .lkup_wr_data_c4(lkup_wr_data_c4[14:0]), | |
235 | .dir_clear_c4(dir_clear_c4) | |
236 | ); | |
237 | ||
238 | // fixscan start: | |
239 | assign ic_ctl_0145_scanin = scan_in ; | |
240 | assign ic_buf_row0_scanin = ic_ctl_0145_scanout ; | |
241 | assign scan_out = ic_buf_row0_scanout ; | |
242 | // fixscan end: | |
243 | endmodule | |
244 | ||
245 | ||
246 | ||
247 | ||
248 | ||
249 | ||
250 | // any PARAMS parms go into naming of macro | |
251 | ||
252 | module l2t_dirtop_ctl_l1clkhdr_ctl_macro ( | |
253 | l2clk, | |
254 | l1en, | |
255 | pce_ov, | |
256 | stop, | |
257 | se, | |
258 | l1clk); | |
259 | ||
260 | ||
261 | input l2clk; | |
262 | input l1en; | |
263 | input pce_ov; | |
264 | input stop; | |
265 | input se; | |
266 | output l1clk; | |
267 | ||
268 | ||
269 | ||
270 | ||
271 | ||
272 | cl_sc1_l1hdr_8x c_0 ( | |
273 | ||
274 | ||
275 | .l2clk(l2clk), | |
276 | .pce(l1en), | |
277 | .l1clk(l1clk), | |
278 | .se(se), | |
279 | .pce_ov(pce_ov), | |
280 | .stop(stop) | |
281 | ); | |
282 | ||
283 | ||
284 | ||
285 | endmodule | |
286 | ||
287 | ||
288 | ||
289 | ||
290 | ||
291 | ||
292 | // Description: Spare gate macro for control blocks | |
293 | // | |
294 | // Param num controls the number of times the macro is added | |
295 | // flops=0 can be used to use only combination spare logic | |
296 | ||
297 | ||
298 | module l2t_dirtop_ctl_spare_ctl_macro__num_4 ( | |
299 | l1clk, | |
300 | scan_in, | |
301 | siclk, | |
302 | soclk, | |
303 | scan_out); | |
304 | wire si_0; | |
305 | wire so_0; | |
306 | wire spare0_flop_unused; | |
307 | wire spare0_buf_32x_unused; | |
308 | wire spare0_nand3_8x_unused; | |
309 | wire spare0_inv_8x_unused; | |
310 | wire spare0_aoi22_4x_unused; | |
311 | wire spare0_buf_8x_unused; | |
312 | wire spare0_oai22_4x_unused; | |
313 | wire spare0_inv_16x_unused; | |
314 | wire spare0_nand2_16x_unused; | |
315 | wire spare0_nor3_4x_unused; | |
316 | wire spare0_nand2_8x_unused; | |
317 | wire spare0_buf_16x_unused; | |
318 | wire spare0_nor2_16x_unused; | |
319 | wire spare0_inv_32x_unused; | |
320 | wire si_1; | |
321 | wire so_1; | |
322 | wire spare1_flop_unused; | |
323 | wire spare1_buf_32x_unused; | |
324 | wire spare1_nand3_8x_unused; | |
325 | wire spare1_inv_8x_unused; | |
326 | wire spare1_aoi22_4x_unused; | |
327 | wire spare1_buf_8x_unused; | |
328 | wire spare1_oai22_4x_unused; | |
329 | wire spare1_inv_16x_unused; | |
330 | wire spare1_nand2_16x_unused; | |
331 | wire spare1_nor3_4x_unused; | |
332 | wire spare1_nand2_8x_unused; | |
333 | wire spare1_buf_16x_unused; | |
334 | wire spare1_nor2_16x_unused; | |
335 | wire spare1_inv_32x_unused; | |
336 | wire si_2; | |
337 | wire so_2; | |
338 | wire spare2_flop_unused; | |
339 | wire spare2_buf_32x_unused; | |
340 | wire spare2_nand3_8x_unused; | |
341 | wire spare2_inv_8x_unused; | |
342 | wire spare2_aoi22_4x_unused; | |
343 | wire spare2_buf_8x_unused; | |
344 | wire spare2_oai22_4x_unused; | |
345 | wire spare2_inv_16x_unused; | |
346 | wire spare2_nand2_16x_unused; | |
347 | wire spare2_nor3_4x_unused; | |
348 | wire spare2_nand2_8x_unused; | |
349 | wire spare2_buf_16x_unused; | |
350 | wire spare2_nor2_16x_unused; | |
351 | wire spare2_inv_32x_unused; | |
352 | wire si_3; | |
353 | wire so_3; | |
354 | wire spare3_flop_unused; | |
355 | wire spare3_buf_32x_unused; | |
356 | wire spare3_nand3_8x_unused; | |
357 | wire spare3_inv_8x_unused; | |
358 | wire spare3_aoi22_4x_unused; | |
359 | wire spare3_buf_8x_unused; | |
360 | wire spare3_oai22_4x_unused; | |
361 | wire spare3_inv_16x_unused; | |
362 | wire spare3_nand2_16x_unused; | |
363 | wire spare3_nor3_4x_unused; | |
364 | wire spare3_nand2_8x_unused; | |
365 | wire spare3_buf_16x_unused; | |
366 | wire spare3_nor2_16x_unused; | |
367 | wire spare3_inv_32x_unused; | |
368 | ||
369 | ||
370 | input l1clk; | |
371 | input scan_in; | |
372 | input siclk; | |
373 | input soclk; | |
374 | output scan_out; | |
375 | ||
376 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
377 | .siclk(siclk), | |
378 | .soclk(soclk), | |
379 | .si(si_0), | |
380 | .so(so_0), | |
381 | .d(1'b0), | |
382 | .q(spare0_flop_unused)); | |
383 | assign si_0 = scan_in; | |
384 | ||
385 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
386 | .out(spare0_buf_32x_unused)); | |
387 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
388 | .in1(1'b1), | |
389 | .in2(1'b1), | |
390 | .out(spare0_nand3_8x_unused)); | |
391 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
392 | .out(spare0_inv_8x_unused)); | |
393 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
394 | .in01(1'b1), | |
395 | .in10(1'b1), | |
396 | .in11(1'b1), | |
397 | .out(spare0_aoi22_4x_unused)); | |
398 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
399 | .out(spare0_buf_8x_unused)); | |
400 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
401 | .in01(1'b1), | |
402 | .in10(1'b1), | |
403 | .in11(1'b1), | |
404 | .out(spare0_oai22_4x_unused)); | |
405 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
406 | .out(spare0_inv_16x_unused)); | |
407 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
408 | .in1(1'b1), | |
409 | .out(spare0_nand2_16x_unused)); | |
410 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
411 | .in1(1'b0), | |
412 | .in2(1'b0), | |
413 | .out(spare0_nor3_4x_unused)); | |
414 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
415 | .in1(1'b1), | |
416 | .out(spare0_nand2_8x_unused)); | |
417 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
418 | .out(spare0_buf_16x_unused)); | |
419 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
420 | .in1(1'b0), | |
421 | .out(spare0_nor2_16x_unused)); | |
422 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
423 | .out(spare0_inv_32x_unused)); | |
424 | ||
425 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
426 | .siclk(siclk), | |
427 | .soclk(soclk), | |
428 | .si(si_1), | |
429 | .so(so_1), | |
430 | .d(1'b0), | |
431 | .q(spare1_flop_unused)); | |
432 | assign si_1 = so_0; | |
433 | ||
434 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
435 | .out(spare1_buf_32x_unused)); | |
436 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
437 | .in1(1'b1), | |
438 | .in2(1'b1), | |
439 | .out(spare1_nand3_8x_unused)); | |
440 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
441 | .out(spare1_inv_8x_unused)); | |
442 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
443 | .in01(1'b1), | |
444 | .in10(1'b1), | |
445 | .in11(1'b1), | |
446 | .out(spare1_aoi22_4x_unused)); | |
447 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
448 | .out(spare1_buf_8x_unused)); | |
449 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
450 | .in01(1'b1), | |
451 | .in10(1'b1), | |
452 | .in11(1'b1), | |
453 | .out(spare1_oai22_4x_unused)); | |
454 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
455 | .out(spare1_inv_16x_unused)); | |
456 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
457 | .in1(1'b1), | |
458 | .out(spare1_nand2_16x_unused)); | |
459 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
460 | .in1(1'b0), | |
461 | .in2(1'b0), | |
462 | .out(spare1_nor3_4x_unused)); | |
463 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
464 | .in1(1'b1), | |
465 | .out(spare1_nand2_8x_unused)); | |
466 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
467 | .out(spare1_buf_16x_unused)); | |
468 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
469 | .in1(1'b0), | |
470 | .out(spare1_nor2_16x_unused)); | |
471 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
472 | .out(spare1_inv_32x_unused)); | |
473 | ||
474 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
475 | .siclk(siclk), | |
476 | .soclk(soclk), | |
477 | .si(si_2), | |
478 | .so(so_2), | |
479 | .d(1'b0), | |
480 | .q(spare2_flop_unused)); | |
481 | assign si_2 = so_1; | |
482 | ||
483 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
484 | .out(spare2_buf_32x_unused)); | |
485 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
486 | .in1(1'b1), | |
487 | .in2(1'b1), | |
488 | .out(spare2_nand3_8x_unused)); | |
489 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
490 | .out(spare2_inv_8x_unused)); | |
491 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
492 | .in01(1'b1), | |
493 | .in10(1'b1), | |
494 | .in11(1'b1), | |
495 | .out(spare2_aoi22_4x_unused)); | |
496 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
497 | .out(spare2_buf_8x_unused)); | |
498 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
499 | .in01(1'b1), | |
500 | .in10(1'b1), | |
501 | .in11(1'b1), | |
502 | .out(spare2_oai22_4x_unused)); | |
503 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
504 | .out(spare2_inv_16x_unused)); | |
505 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
506 | .in1(1'b1), | |
507 | .out(spare2_nand2_16x_unused)); | |
508 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
509 | .in1(1'b0), | |
510 | .in2(1'b0), | |
511 | .out(spare2_nor3_4x_unused)); | |
512 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
513 | .in1(1'b1), | |
514 | .out(spare2_nand2_8x_unused)); | |
515 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
516 | .out(spare2_buf_16x_unused)); | |
517 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
518 | .in1(1'b0), | |
519 | .out(spare2_nor2_16x_unused)); | |
520 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
521 | .out(spare2_inv_32x_unused)); | |
522 | ||
523 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
524 | .siclk(siclk), | |
525 | .soclk(soclk), | |
526 | .si(si_3), | |
527 | .so(so_3), | |
528 | .d(1'b0), | |
529 | .q(spare3_flop_unused)); | |
530 | assign si_3 = so_2; | |
531 | ||
532 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
533 | .out(spare3_buf_32x_unused)); | |
534 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
535 | .in1(1'b1), | |
536 | .in2(1'b1), | |
537 | .out(spare3_nand3_8x_unused)); | |
538 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
539 | .out(spare3_inv_8x_unused)); | |
540 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
541 | .in01(1'b1), | |
542 | .in10(1'b1), | |
543 | .in11(1'b1), | |
544 | .out(spare3_aoi22_4x_unused)); | |
545 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
546 | .out(spare3_buf_8x_unused)); | |
547 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
548 | .in01(1'b1), | |
549 | .in10(1'b1), | |
550 | .in11(1'b1), | |
551 | .out(spare3_oai22_4x_unused)); | |
552 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
553 | .out(spare3_inv_16x_unused)); | |
554 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
555 | .in1(1'b1), | |
556 | .out(spare3_nand2_16x_unused)); | |
557 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
558 | .in1(1'b0), | |
559 | .in2(1'b0), | |
560 | .out(spare3_nor3_4x_unused)); | |
561 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
562 | .in1(1'b1), | |
563 | .out(spare3_nand2_8x_unused)); | |
564 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
565 | .out(spare3_buf_16x_unused)); | |
566 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
567 | .in1(1'b0), | |
568 | .out(spare3_nor2_16x_unused)); | |
569 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
570 | .out(spare3_inv_32x_unused)); | |
571 | assign scan_out = so_3; | |
572 | ||
573 | ||
574 | ||
575 | endmodule | |
576 | ||
577 | ||
578 | ||
579 | ||
580 | ||
581 | ||
582 | // any PARAMS parms go into naming of macro | |
583 | ||
584 | module l2t_dirtop_ctl_msff_ctl_macro__width_3 ( | |
585 | din, | |
586 | l1clk, | |
587 | scan_in, | |
588 | siclk, | |
589 | soclk, | |
590 | dout, | |
591 | scan_out); | |
592 | wire [2:0] fdin; | |
593 | wire [1:0] so; | |
594 | ||
595 | input [2:0] din; | |
596 | input l1clk; | |
597 | input scan_in; | |
598 | ||
599 | ||
600 | input siclk; | |
601 | input soclk; | |
602 | ||
603 | output [2:0] dout; | |
604 | output scan_out; | |
605 | assign fdin[2:0] = din[2:0]; | |
606 | ||
607 | ||
608 | ||
609 | ||
610 | ||
611 | ||
612 | dff #(3) d0_0 ( | |
613 | .l1clk(l1clk), | |
614 | .siclk(siclk), | |
615 | .soclk(soclk), | |
616 | .d(fdin[2:0]), | |
617 | .si({scan_in,so[1:0]}), | |
618 | .so({so[1:0],scan_out}), | |
619 | .q(dout[2:0]) | |
620 | ); | |
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | endmodule | |
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | // any PARAMS parms go into naming of macro | |
648 | ||
649 | module l2t_dirtop_ctl_msff_ctl_macro__width_2 ( | |
650 | din, | |
651 | l1clk, | |
652 | scan_in, | |
653 | siclk, | |
654 | soclk, | |
655 | dout, | |
656 | scan_out); | |
657 | wire [1:0] fdin; | |
658 | wire [0:0] so; | |
659 | ||
660 | input [1:0] din; | |
661 | input l1clk; | |
662 | input scan_in; | |
663 | ||
664 | ||
665 | input siclk; | |
666 | input soclk; | |
667 | ||
668 | output [1:0] dout; | |
669 | output scan_out; | |
670 | assign fdin[1:0] = din[1:0]; | |
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | dff #(2) d0_0 ( | |
678 | .l1clk(l1clk), | |
679 | .siclk(siclk), | |
680 | .soclk(soclk), | |
681 | .d(fdin[1:0]), | |
682 | .si({scan_in,so[0:0]}), | |
683 | .so({so[0:0],scan_out}), | |
684 | .q(dout[1:0]) | |
685 | ); | |
686 | ||
687 | ||
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | endmodule | |
699 | ||
700 | ||
701 | ||
702 | ||
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | ||
710 | ||
711 | ||
712 | // any PARAMS parms go into naming of macro | |
713 | ||
714 | module l2t_dirtop_ctl_msff_ctl_macro__width_4 ( | |
715 | din, | |
716 | l1clk, | |
717 | scan_in, | |
718 | siclk, | |
719 | soclk, | |
720 | dout, | |
721 | scan_out); | |
722 | wire [3:0] fdin; | |
723 | wire [2:0] so; | |
724 | ||
725 | input [3:0] din; | |
726 | input l1clk; | |
727 | input scan_in; | |
728 | ||
729 | ||
730 | input siclk; | |
731 | input soclk; | |
732 | ||
733 | output [3:0] dout; | |
734 | output scan_out; | |
735 | assign fdin[3:0] = din[3:0]; | |
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | dff #(4) d0_0 ( | |
743 | .l1clk(l1clk), | |
744 | .siclk(siclk), | |
745 | .soclk(soclk), | |
746 | .d(fdin[3:0]), | |
747 | .si({scan_in,so[2:0]}), | |
748 | .so({so[2:0],scan_out}), | |
749 | .q(dout[3:0]) | |
750 | ); | |
751 | ||
752 | ||
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | ||
760 | ||
761 | ||
762 | ||
763 | endmodule | |
764 | ||
765 | ||
766 | ||
767 | ||
768 | ||
769 | // any PARAMS parms go into naming of macro | |
770 | ||
771 | module l2t_dirtop_ctl_msff_ctl_macro__width_1 ( | |
772 | din, | |
773 | l1clk, | |
774 | scan_in, | |
775 | siclk, | |
776 | soclk, | |
777 | dout, | |
778 | scan_out); | |
779 | wire [0:0] fdin; | |
780 | ||
781 | input [0:0] din; | |
782 | input l1clk; | |
783 | input scan_in; | |
784 | ||
785 | ||
786 | input siclk; | |
787 | input soclk; | |
788 | ||
789 | output [0:0] dout; | |
790 | output scan_out; | |
791 | assign fdin[0:0] = din[0:0]; | |
792 | ||
793 | ||
794 | ||
795 | ||
796 | ||
797 | ||
798 | dff #(1) d0_0 ( | |
799 | .l1clk(l1clk), | |
800 | .siclk(siclk), | |
801 | .soclk(soclk), | |
802 | .d(fdin[0:0]), | |
803 | .si(scan_in), | |
804 | .so(scan_out), | |
805 | .q(dout[0:0]) | |
806 | ); | |
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | ||
813 | ||
814 | ||
815 | ||
816 | ||
817 | ||
818 | ||
819 | endmodule | |
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | ||
826 | ||
827 | ||
828 | ||
829 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
830 | // also for pass-gate with decoder | |
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 | // any PARAMS parms go into naming of macro | |
837 | ||
838 | module l2t_dirtop_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 ( | |
839 | din0, | |
840 | sel0, | |
841 | din1, | |
842 | sel1, | |
843 | dout); | |
844 | input [1:0] din0; | |
845 | input sel0; | |
846 | input [1:0] din1; | |
847 | input sel1; | |
848 | output [1:0] dout; | |
849 | ||
850 | ||
851 | ||
852 | ||
853 | ||
854 | assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) | | |
855 | ( {2{sel1}} & din1[1:0]); | |
856 | ||
857 | ||
858 | ||
859 | ||
860 | ||
861 | endmodule | |
862 | ||
863 | ||
864 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
865 | // also for pass-gate with decoder | |
866 | ||
867 | ||
868 | ||
869 | ||
870 | ||
871 | // any PARAMS parms go into naming of macro | |
872 | ||
873 | module l2t_dirtop_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 ( | |
874 | din0, | |
875 | sel0, | |
876 | din1, | |
877 | sel1, | |
878 | dout); | |
879 | input [7:0] din0; | |
880 | input sel0; | |
881 | input [7:0] din1; | |
882 | input sel1; | |
883 | output [7:0] dout; | |
884 | ||
885 | ||
886 | ||
887 | ||
888 | ||
889 | assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) | | |
890 | ( {8{sel1}} & din1[7:0]); | |
891 | ||
892 | ||
893 | ||
894 | ||
895 | ||
896 | endmodule | |
897 | ||
898 | ||
899 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
900 | // also for pass-gate with decoder | |
901 | ||
902 | ||
903 | ||
904 | ||
905 | ||
906 | // any PARAMS parms go into naming of macro | |
907 | ||
908 | module l2t_dirtop_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 ( | |
909 | din0, | |
910 | sel0, | |
911 | din1, | |
912 | sel1, | |
913 | dout); | |
914 | input [5:0] din0; | |
915 | input sel0; | |
916 | input [5:0] din1; | |
917 | input sel1; | |
918 | output [5:0] dout; | |
919 | ||
920 | ||
921 | ||
922 | ||
923 | ||
924 | assign dout[5:0] = ( {6{sel0}} & din0[5:0] ) | | |
925 | ( {6{sel1}} & din1[5:0]); | |
926 | ||
927 | ||
928 | ||
929 | ||
930 | ||
931 | endmodule | |
932 | ||
933 | ||
934 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
935 | // also for pass-gate with decoder | |
936 | ||
937 | ||
938 | ||
939 | ||
940 | ||
941 | // any PARAMS parms go into naming of macro | |
942 | ||
943 | module l2t_dirtop_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 ( | |
944 | din0, | |
945 | sel0, | |
946 | din1, | |
947 | sel1, | |
948 | dout); | |
949 | input [15:0] din0; | |
950 | input sel0; | |
951 | input [15:0] din1; | |
952 | input sel1; | |
953 | output [15:0] dout; | |
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | assign dout[15:0] = ( {16{sel0}} & din0[15:0] ) | | |
960 | ( {16{sel1}} & din1[15:0]); | |
961 | ||
962 | ||
963 | ||
964 | ||
965 | ||
966 | endmodule | |
967 | ||
968 | ||
969 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
970 | // also for pass-gate with decoder | |
971 | ||
972 | ||
973 | ||
974 | ||
975 | ||
976 | // any PARAMS parms go into naming of macro | |
977 | ||
978 | module l2t_dirtop_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 ( | |
979 | din0, | |
980 | sel0, | |
981 | din1, | |
982 | sel1, | |
983 | dout); | |
984 | input [3:0] din0; | |
985 | input sel0; | |
986 | input [3:0] din1; | |
987 | input sel1; | |
988 | output [3:0] dout; | |
989 | ||
990 | ||
991 | ||
992 | ||
993 | ||
994 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | | |
995 | ( {4{sel1}} & din1[3:0]); | |
996 | ||
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | endmodule | |
1002 |