Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_ecc24b_dp.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_ecc24b_dp.v
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35module l2t_ecc24b_dp (
36 din,
37 dout,
38 parity);
39wire p1_10;
40wire p1_11;
41wire p1_12;
42wire p1_13;
43wire p1_14;
44wire p1_20;
45wire p2_10;
46wire p2_11;
47wire p2_12;
48wire p2_13;
49wire p2_20;
50wire p4_10;
51wire p4_11;
52wire p4_12;
53wire p4_13;
54wire p4_20;
55wire p8_10;
56wire p8_11;
57wire p8_12;
58wire p8_13;
59wire p8_20;
60wire p16_10;
61wire p16_11;
62wire p16_12;
63wire p16_13;
64wire p16_20;
65wire p30_10;
66wire p30_11;
67wire p30_12;
68wire p30_13;
69wire p30_14;
70wire p30_20;
71
72
73// Input Ports
74input [23:0] din ;
75
76// Output Ports
77output [23:0] dout ;
78output [5:0] parity ;
79
80wire [23:0] dout ;
81wire [5:0] parity ;
82
83// Local Reg and Wires
84wire p1 ;
85wire p2 ;
86wire p4 ;
87wire p8 ;
88wire p16 ;
89wire p30 ;
90
91
92//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
93// |1 |2 |3 |4 |5 |6 |7 |8 |9 |10|11|12|13|14|15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |
94// |P1|P2|D0|P4|D1|D2|D3|P8|D4|D5|D6|D7|D8|D9|D10|P16|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|P30|
95//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
96//P1 | | |* | |* | |* | |* | |* | |* | | * | | * | | * | | * | | * | | * | | * | | * | |
97//P2 | | |* | | |* |* | | |* |* | | |* | * | | | * | * | | | * | * | | | * | * | | | |
98//P4 | | | | |* |* |* | | | | |* |* |* | * | | | | | * | * | * | * | | | | | * | * | |
99//P8 | | | | | | | | |* |* |* |* |* |* | * | | | | | | | | | * | * | * | * | * | * | |
100//P16 | | | | | | | | | | | | | | | | | * | * | * | * | * | * | * | * | * | * | * | * | * | |
101//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
102//p30 | | |* | |* |* | | |* |* | |* | | | * | | * | * | | * | | | * | * | | | * | | * | |
103//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
104
105//
106//assign p1 = din[0] ^ din[1] ^ din[3] ^ din[4] ^ din[6] ^ din[8] ^
107// din[10] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[19] ^
108// din[21] ^ din[23] ;
109
110l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_10 (
111 .dout (p1_10),
112 .din0 (din[0]),
113 .din1 (din[1]),
114 .din2 (din[3])
115 );
116
117l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_11 (
118 .dout (p1_11),
119 .din0 (din[4]),
120 .din1 (din[6]),
121 .din2 (din[8])
122 );
123
124l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_12 (
125 .dout (p1_12),
126 .din0 (din[10]),
127 .din1 (din[11]),
128 .din2 (din[13])
129 );
130
131l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_13 (
132 .dout (p1_13),
133 .din0 (din[15]),
134 .din1 (din[17]),
135 .din2 (din[19])
136 );
137
138l2t_ecc24b_dp_xor_macro__dxor_8x__ports_2__width_1 p1_slice_14 (
139 .dout (p1_14),
140 .din0 (din[21]),
141 .din1 (din[23])
142 );
143
144l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_20 (
145 .dout (p1_20),
146 .din0 (p1_10),
147 .din1 (p1_11),
148 .din2 (p1_12)
149 );
150
151l2t_ecc24b_dp_xor_macro__dxor_16x__ports_3__width_1 p1_slice (
152 .dout (p1),
153 .din0 (p1_20),
154 .din1 (p1_13),
155 .din2 (p1_14)
156 );
157
158
159
160//assign p2 = din[0] ^ din[2] ^ din[3] ^ din[5] ^ din[6] ^ din[9] ^
161// din[10] ^ din[12] ^ din[13] ^ din[16] ^ din[17] ^ din[20] ^
162// din[21] ;
163
164l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_10 (
165 .dout (p2_10),
166 .din0 (din[0]),
167 .din1 (din[2]),
168 .din2 (din[3])
169 );
170
171l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_11 (
172 .dout (p2_11),
173 .din0 (din[5]),
174 .din1 (din[6]),
175 .din2 (din[9])
176 );
177
178l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_12 (
179 .dout (p2_12),
180 .din0 (din[10]),
181 .din1 (din[12]),
182 .din2 (din[13])
183 );
184
185l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_13 (
186 .dout (p2_13),
187 .din0 (din[16]),
188 .din1 (din[17]),
189 .din2 (din[20])
190 );
191
192l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_20 (
193 .dout (p2_20),
194 .din0 (p2_10),
195 .din1 (p2_11),
196 .din2 (p2_12)
197 );
198
199l2t_ecc24b_dp_xor_macro__dxor_16x__ports_3__width_1 p2_slice (
200 .dout (p2),
201 .din0 (p2_20),
202 .din1 (p2_13),
203 .din2 (din[21])
204 );
205
206
207
208//assign p4 = din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[8] ^ din[9] ^
209// din[10] ^ din[14] ^ din[15] ^ din[16] ^ din[17] ^ din[22] ^
210// din[23] ;
211
212l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_10 (
213 .dout (p4_10),
214 .din0 (din[1]),
215 .din1 (din[2]),
216 .din2 (din[3])
217 );
218
219l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_11 (
220 .dout (p4_11),
221 .din0 (din[7]),
222 .din1 (din[8]),
223 .din2 (din[9])
224 );
225
226l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_12 (
227 .dout (p4_12),
228 .din0 (din[10]),
229 .din1 (din[14]),
230 .din2 (din[15])
231 );
232
233l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_13 (
234 .dout (p4_13),
235 .din0 (din[16]),
236 .din1 (din[17]),
237 .din2 (din[22])
238 );
239
240l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_20 (
241 .dout (p4_20),
242 .din0 (p4_10),
243 .din1 (p4_11),
244 .din2 (p4_12)
245 );
246
247l2t_ecc24b_dp_xor_macro__dxor_16x__ports_3__width_1 p4_slice (
248 .dout (p4),
249 .din0 (p4_20),
250 .din1 (p4_13),
251 .din2 (din[23])
252 );
253
254
255
256//assign p8 = din[4] ^ din[5] ^ din[6] ^ din[7] ^ din[8] ^ din[9] ^
257// din[10] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
258// din[23] ;
259
260l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_10 (
261 .dout (p8_10),
262 .din0 (din[4]),
263 .din1 (din[5]),
264 .din2 (din[6])
265 );
266
267l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_11 (
268 .dout (p8_11),
269 .din0 (din[7]),
270 .din1 (din[8]),
271 .din2 (din[9])
272 );
273
274l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_12 (
275 .dout (p8_12),
276 .din0 (din[10]),
277 .din1 (din[18]),
278 .din2 (din[19])
279 );
280
281l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_13 (
282 .dout (p8_13),
283 .din0 (din[20]),
284 .din1 (din[21]),
285 .din2 (din[22])
286 );
287
288l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_20 (
289 .dout (p8_20),
290 .din0 (p8_10),
291 .din1 (p8_11),
292 .din2 (p8_12)
293 );
294
295l2t_ecc24b_dp_xor_macro__dxor_16x__ports_3__width_1 p8_slice (
296 .dout (p8),
297 .din0 (p8_20),
298 .din1 (p8_13),
299 .din2 (din[23])
300 );
301
302
303
304//assign p16 = din[11] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
305// din[17] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
306// din[23] ;
307
308l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_10 (
309 .dout (p16_10),
310 .din0 (din[11]),
311 .din1 (din[12]),
312 .din2 (din[13])
313 );
314
315l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_11 (
316 .dout (p16_11),
317 .din0 (din[14]),
318 .din1 (din[15]),
319 .din2 (din[16])
320 );
321
322l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_12 (
323 .dout (p16_12),
324 .din0 (din[17]),
325 .din1 (din[18]),
326 .din2 (din[19])
327 );
328
329l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_13 (
330 .dout (p16_13),
331 .din0 (din[20]),
332 .din1 (din[21]),
333 .din2 (din[22])
334 );
335
336l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_20 (
337 .dout (p16_20),
338 .din0 (p16_10),
339 .din1 (p16_11),
340 .din2 (p16_12)
341 );
342
343l2t_ecc24b_dp_xor_macro__dxor_16x__ports_3__width_1 p16_slice (
344 .dout (p16),
345 .din0 (p16_20),
346 .din1 (p16_13),
347 .din2 (din[23])
348 );
349
350
351
352//assign p30 = din[0] ^ din[1] ^ din[2] ^ din[4] ^ din[5] ^
353// din[7] ^ din[10] ^ din[11] ^ din[12] ^ din[14] ^
354// din[17] ^ din[18] ^ din[21] ^ din[23] ;
355
356l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p30_slice_10 (
357 .dout (p30_10),
358 .din0 (din[0]),
359 .din1 (din[1]),
360 .din2 (din[2])
361 );
362
363l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p30_slice_11 (
364 .dout (p30_11),
365 .din0 (din[4]),
366 .din1 (din[5]),
367 .din2 (din[7])
368 );
369
370l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p30_slice_12 (
371 .dout (p30_12),
372 .din0 (din[10]),
373 .din1 (din[11]),
374 .din2 (din[12])
375 );
376
377l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p30_slice_13 (
378 .dout (p30_13),
379 .din0 (din[14]),
380 .din1 (din[17]),
381 .din2 (din[18])
382 );
383
384l2t_ecc24b_dp_xor_macro__dxor_8x__ports_2__width_1 p30_slice_14 (
385 .dout (p30_14),
386 .din0 (din[21]),
387 .din1 (din[23])
388 );
389
390l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 p30_slice_20 (
391 .dout (p30_20),
392 .din0 (p30_10),
393 .din1 (p30_11),
394 .din2 (p30_12)
395 );
396
397l2t_ecc24b_dp_xor_macro__dxor_16x__ports_3__width_1 p30_slice (
398 .dout (p30),
399 .din0 (p30_20),
400 .din1 (p30_13),
401 .din2 (p30_14)
402 );
403
404
405
406assign dout = din[23:0] ;
407
408//buff_macro buff_dout (width=24,stack=24r)
409// (
410// .dout (dout[23:0]),
411// .din (din[23:0])
412// );
413//
414assign parity = {p30, p16, p8, p4, p2, p1} ;
415//
416//buff_macro buff_parity (width=6,stack=6c)
417// (
418// .dout (parity[5:0]),
419// .din ({p30, p16, p8, p4, p2, p1})
420// );
421//
422
423endmodule
424
425
426//
427// xor macro for ports = 2,3
428//
429//
430
431
432
433
434
435module l2t_ecc24b_dp_xor_macro__dxor_8x__ports_3__width_1 (
436 din0,
437 din1,
438 din2,
439 dout);
440 input [0:0] din0;
441 input [0:0] din1;
442 input [0:0] din2;
443 output [0:0] dout;
444
445
446
447
448
449xor3 #(1) d0_0 (
450.in0(din0[0:0]),
451.in1(din1[0:0]),
452.in2(din2[0:0]),
453.out(dout[0:0])
454);
455
456
457
458
459
460
461
462
463endmodule
464
465
466
467
468
469//
470// xor macro for ports = 2,3
471//
472//
473
474
475
476
477
478module l2t_ecc24b_dp_xor_macro__dxor_8x__ports_2__width_1 (
479 din0,
480 din1,
481 dout);
482 input [0:0] din0;
483 input [0:0] din1;
484 output [0:0] dout;
485
486
487
488
489
490xor2 #(1) d0_0 (
491.in0(din0[0:0]),
492.in1(din1[0:0]),
493.out(dout[0:0])
494);
495
496
497
498
499
500
501
502
503endmodule
504
505
506
507
508
509//
510// xor macro for ports = 2,3
511//
512//
513
514
515
516
517
518module l2t_ecc24b_dp_xor_macro__dxor_16x__ports_3__width_1 (
519 din0,
520 din1,
521 din2,
522 dout);
523 input [0:0] din0;
524 input [0:0] din1;
525 input [0:0] din2;
526 output [0:0] dout;
527
528
529
530
531
532xor3 #(1) d0_0 (
533.in0(din0[0:0]),
534.in1(din1[0:0]),
535.in2(din2[0:0]),
536.out(dout[0:0])
537);
538
539
540
541
542
543
544
545
546endmodule
547
548
549
550