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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_ecc39a_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_ecc39a_dp ( | |
36 | dout, | |
37 | cflag, | |
38 | pflag, | |
39 | pflag_n, | |
40 | din, | |
41 | parity); | |
42 | wire c0_10; | |
43 | wire c0_11; | |
44 | wire c0_12; | |
45 | wire c0_13; | |
46 | wire c0_14; | |
47 | wire c0_15; | |
48 | wire c0_20; | |
49 | wire c0_21; | |
50 | wire c0_1; | |
51 | wire c0_2; | |
52 | wire c0_3; | |
53 | wire c1_10; | |
54 | wire c1_11; | |
55 | wire c1_12; | |
56 | wire c1_13; | |
57 | wire c1_14; | |
58 | wire c1_15; | |
59 | wire c1_20; | |
60 | wire c1_21; | |
61 | wire c1_1; | |
62 | wire c1_2; | |
63 | wire c2_10; | |
64 | wire c2_11; | |
65 | wire c2_12; | |
66 | wire c2_13; | |
67 | wire c2_14; | |
68 | wire c2_15; | |
69 | wire c2_20; | |
70 | wire c2_21; | |
71 | wire c2_1; | |
72 | wire c2_2; | |
73 | wire c3_10; | |
74 | wire c3_11; | |
75 | wire c3_12; | |
76 | wire c3_13; | |
77 | wire c3_14; | |
78 | wire c3_20; | |
79 | wire c3_21; | |
80 | wire c3_1; | |
81 | wire c3_2; | |
82 | wire c4_10; | |
83 | wire c4_11; | |
84 | wire c4_12; | |
85 | wire c4_13; | |
86 | wire c4_14; | |
87 | wire c4_20; | |
88 | wire c4_21; | |
89 | wire c4_1; | |
90 | wire c4_2; | |
91 | wire c5_10; | |
92 | wire c5_11; | |
93 | wire pflag_1; | |
94 | wire pflag_2; | |
95 | wire pflag_1_n; | |
96 | wire pflag_2_n; | |
97 | wire pinvterm1; | |
98 | wire pinvterm2; | |
99 | wire pterm1; | |
100 | wire pterm2; | |
101 | wire nc0_1; | |
102 | wire nc0_2; | |
103 | wire nc1_1; | |
104 | wire nc1_2; | |
105 | wire nc2_1; | |
106 | wire nc2_2; | |
107 | wire nc3_1; | |
108 | wire nc3_2; | |
109 | wire nc4_1; | |
110 | wire nc4_2; | |
111 | wire nc5_1; | |
112 | wire nc5_2; | |
113 | wire err_bit0_pos_10a; | |
114 | wire err_bit0_pos_10b; | |
115 | wire err_bit1_pos_10a; | |
116 | wire err_bit1_pos_10b; | |
117 | wire err_bit2_pos_10a; | |
118 | wire err_bit2_pos_10b; | |
119 | wire err_bit3_pos_10a; | |
120 | wire err_bit3_pos_10b; | |
121 | wire err_bit4_pos_10a; | |
122 | wire err_bit4_pos_10b; | |
123 | wire err_bit5_pos_10a; | |
124 | wire err_bit5_pos_10b; | |
125 | wire err_bit6_pos_10a; | |
126 | wire err_bit6_pos_10b; | |
127 | wire err_bit7_pos_10a; | |
128 | wire err_bit7_pos_10b; | |
129 | wire err_bit8_pos_10a; | |
130 | wire err_bit8_pos_10b; | |
131 | wire err_bit9_pos_10a; | |
132 | wire err_bit9_pos_10b; | |
133 | wire err_bit10_pos_10a; | |
134 | wire err_bit10_pos_10b; | |
135 | wire err_bit11_pos_10a; | |
136 | wire err_bit11_pos_10b; | |
137 | wire err_bit12_pos_10a; | |
138 | wire err_bit12_pos_10b; | |
139 | wire err_bit13_pos_10a; | |
140 | wire err_bit13_pos_10b; | |
141 | wire err_bit14_pos_10a; | |
142 | wire err_bit14_pos_10b; | |
143 | wire err_bit15_pos_10a; | |
144 | wire err_bit15_pos_10b; | |
145 | wire err_bit16_pos_10a; | |
146 | wire err_bit16_pos_10b; | |
147 | wire err_bit17_pos_10a; | |
148 | wire err_bit17_pos_10b; | |
149 | wire err_bit18_pos_10a; | |
150 | wire err_bit18_pos_10b; | |
151 | wire err_bit19_pos_10a; | |
152 | wire err_bit19_pos_10b; | |
153 | wire err_bit20_pos_10a; | |
154 | wire err_bit20_pos_10b; | |
155 | wire err_bit21_pos_10a; | |
156 | wire err_bit21_pos_10b; | |
157 | wire err_bit22_pos_10a; | |
158 | wire err_bit22_pos_10b; | |
159 | wire err_bit23_pos_10a; | |
160 | wire err_bit23_pos_10b; | |
161 | wire err_bit24_pos_10a; | |
162 | wire err_bit24_pos_10b; | |
163 | wire err_bit25_pos_10a; | |
164 | wire err_bit25_pos_10b; | |
165 | wire err_bit26_pos_10a; | |
166 | wire err_bit26_pos_10b; | |
167 | wire err_bit27_pos_10a; | |
168 | wire err_bit27_pos_10b; | |
169 | wire err_bit28_pos_10a; | |
170 | wire err_bit28_pos_10b; | |
171 | wire err_bit29_pos_10a; | |
172 | wire err_bit29_pos_10b; | |
173 | wire err_bit30_pos_10a; | |
174 | wire err_bit30_pos_10b; | |
175 | wire err_bit31_pos_10a; | |
176 | wire err_bit31_pos_10b; | |
177 | ||
178 | ||
179 | //Output: 32bit corrected data | |
180 | output[31:0] dout; | |
181 | output [5:0] cflag; | |
182 | output pflag; | |
183 | output pflag_n; | |
184 | ||
185 | //Input: 32bit data din | |
186 | input [31:0] din; | |
187 | input [6:0] parity; | |
188 | ||
189 | wire c0,c1,c2,c3,c4,c5; | |
190 | wire [31:0] err_bit_pos; | |
191 | ||
192 | //refer to the comments in parity_gen_32b.v for the position description | |
193 | // | |
194 | // assign c0= parity[0]^(din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8]) | |
195 | // ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19]) | |
196 | // ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]); | |
197 | ||
198 | ||
199 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_10 ( | |
200 | .dout (c0_10), | |
201 | .din0 (din[0]), | |
202 | .din1 (din[1]), | |
203 | .din2 (din[3]) | |
204 | ); | |
205 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_11 ( | |
206 | .dout (c0_11), | |
207 | .din0 (din[4]), | |
208 | .din1 (din[6]), | |
209 | .din2 (din[8]) | |
210 | ); | |
211 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_12 ( | |
212 | .dout (c0_12), | |
213 | .din0 (din[10]), | |
214 | .din1 (din[11]), | |
215 | .din2 (din[13]) | |
216 | ); | |
217 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_13 ( | |
218 | .dout (c0_13), | |
219 | .din0 (din[15]), | |
220 | .din1 (din[17]), | |
221 | .din2 (din[19]) | |
222 | ); | |
223 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_14 ( | |
224 | .dout (c0_14), | |
225 | .din0 (din[21]), | |
226 | .din1 (din[23]), | |
227 | .din2 (din[25]) | |
228 | ); | |
229 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_15 ( | |
230 | .dout (c0_15), | |
231 | .din0 (din[26]), | |
232 | .din1 (din[28]), | |
233 | .din2 (din[30]) | |
234 | ); | |
235 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_20 ( | |
236 | .dout (c0_20), | |
237 | .din0 (c0_10), | |
238 | .din1 (c0_11), | |
239 | .din2 (c0_12) | |
240 | ); | |
241 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_21 ( | |
242 | .dout (c0_21), | |
243 | .din0 (c0_13), | |
244 | .din1 (c0_14), | |
245 | .din2 (c0_15) | |
246 | ); | |
247 | ||
248 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22a ( | |
249 | .dout (c0_1), | |
250 | .din0 (c0_20), | |
251 | .din1 (c0_21), | |
252 | .din2 (parity[0]) | |
253 | ); | |
254 | ||
255 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22b ( | |
256 | .dout (c0_2), | |
257 | .din0 (c0_20), | |
258 | .din1 (c0_21), | |
259 | .din2 (parity[0]) | |
260 | ); | |
261 | ||
262 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22c ( | |
263 | .dout (c0_3), | |
264 | .din0 (c0_20), | |
265 | .din1 (c0_21), | |
266 | .din2 (parity[0]) | |
267 | ); | |
268 | ||
269 | ||
270 | ||
271 | // assign c1= parity[1]^(din[0]^din[2])^(din[3]^din[5])^(din[6]^din[9]) | |
272 | // ^(din[10]^din[12])^(din[13]^din[16])^(din[17]^din[20]) | |
273 | // ^(din[21]^din[24])^(din[25]^din[27])^(din[28]^din[31]); | |
274 | ||
275 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_10 ( | |
276 | .dout (c1_10), | |
277 | .din0 (din[0]), | |
278 | .din1 (din[2]), | |
279 | .din2 (din[3]) | |
280 | ); | |
281 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_11 ( | |
282 | .dout (c1_11), | |
283 | .din0 (din[5]), | |
284 | .din1 (din[6]), | |
285 | .din2 (din[9]) | |
286 | ); | |
287 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_12 ( | |
288 | .dout (c1_12), | |
289 | .din0 (din[10]), | |
290 | .din1 (din[12]), | |
291 | .din2 (din[13]) | |
292 | ); | |
293 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_13 ( | |
294 | .dout (c1_13), | |
295 | .din0 (din[16]), | |
296 | .din1 (din[17]), | |
297 | .din2 (din[20]) | |
298 | ); | |
299 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_14 ( | |
300 | .dout (c1_14), | |
301 | .din0 (din[21]), | |
302 | .din1 (din[24]), | |
303 | .din2 (din[25]) | |
304 | ); | |
305 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_15 ( | |
306 | .dout (c1_15), | |
307 | .din0 (din[27]), | |
308 | .din1 (din[28]), | |
309 | .din2 (din[31]) | |
310 | ); | |
311 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_20 ( | |
312 | .dout (c1_20), | |
313 | .din0 (c1_10), | |
314 | .din1 (c1_11), | |
315 | .din2 (c1_12) | |
316 | ); | |
317 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_21 ( | |
318 | .dout (c1_21), | |
319 | .din0 (c1_13), | |
320 | .din1 (c1_14), | |
321 | .din2 (c1_15) | |
322 | ); | |
323 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_22a ( | |
324 | .dout (c1_1), | |
325 | .din0 (c1_20), | |
326 | .din1 (c1_21), | |
327 | .din2 (parity[1]) | |
328 | ); | |
329 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_22b ( | |
330 | .dout (c1_2), | |
331 | .din0 (c1_20), | |
332 | .din1 (c1_21), | |
333 | .din2 (parity[1]) | |
334 | ); | |
335 | ||
336 | ||
337 | // assign c2= parity[2]^(din[1]^din[2])^(din[3]^din[7])^(din[8]^din[9]) | |
338 | // ^(din[10]^din[14])^(din[15]^din[16])^(din[17]^din[22]) | |
339 | // ^(din[23]^din[24])^(din[25]^din[29])^(din[30]^din[31]); | |
340 | ||
341 | ||
342 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_10 ( | |
343 | .dout (c2_10), | |
344 | .din0 (din[1]), | |
345 | .din1 (din[2]), | |
346 | .din2 (din[3]) | |
347 | ); | |
348 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_11 ( | |
349 | .dout (c2_11), | |
350 | .din0 (din[7]), | |
351 | .din1 (din[8]), | |
352 | .din2 (din[9]) | |
353 | ); | |
354 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_12 ( | |
355 | .dout (c2_12), | |
356 | .din0 (din[10]), | |
357 | .din1 (din[14]), | |
358 | .din2 (din[15]) | |
359 | ); | |
360 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_13 ( | |
361 | .dout (c2_13), | |
362 | .din0 (din[16]), | |
363 | .din1 (din[17]), | |
364 | .din2 (din[22]) | |
365 | ); | |
366 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_14 ( | |
367 | .dout (c2_14), | |
368 | .din0 (din[23]), | |
369 | .din1 (din[24]), | |
370 | .din2 (din[25]) | |
371 | ); | |
372 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_15 ( | |
373 | .dout (c2_15), | |
374 | .din0 (din[29]), | |
375 | .din1 (din[30]), | |
376 | .din2 (din[31]) | |
377 | ); | |
378 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_20 ( | |
379 | .dout (c2_20), | |
380 | .din0 (c2_10), | |
381 | .din1 (c2_11), | |
382 | .din2 (c2_12) | |
383 | ); | |
384 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_21 ( | |
385 | .dout (c2_21), | |
386 | .din0 (c2_13), | |
387 | .din1 (c2_14), | |
388 | .din2 (c2_15) | |
389 | ); | |
390 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_22a ( | |
391 | .dout (c2_1), | |
392 | .din0 (c2_20), | |
393 | .din1 (c2_21), | |
394 | .din2 (parity[2]) | |
395 | ); | |
396 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_22b ( | |
397 | .dout (c2_2), | |
398 | .din0 (c2_20), | |
399 | .din1 (c2_21), | |
400 | .din2 (parity[2]) | |
401 | ); | |
402 | ||
403 | ||
404 | ||
405 | ||
406 | // assign c3= parity[3]^(din[4]^din[5])^(din[6]^din[7])^(din[8]^din[9]) | |
407 | // ^(din[10]^din[18])^(din[19]^din[20])^(din[21]^din[22]) | |
408 | // ^(din[23]^din[24])^din[25]; | |
409 | ||
410 | ||
411 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_10 ( | |
412 | .dout (c3_10), | |
413 | .din0 (din[4]), | |
414 | .din1 (din[5]), | |
415 | .din2 (din[6]) | |
416 | ); | |
417 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_11 ( | |
418 | .dout (c3_11), | |
419 | .din0 (din[7]), | |
420 | .din1 (din[8]), | |
421 | .din2 (din[9]) | |
422 | ); | |
423 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_12 ( | |
424 | .dout (c3_12), | |
425 | .din0 (din[10]), | |
426 | .din1 (din[18]), | |
427 | .din2 (din[19]) | |
428 | ); | |
429 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_13 ( | |
430 | .dout (c3_13), | |
431 | .din0 (din[20]), | |
432 | .din1 (din[21]), | |
433 | .din2 (din[22]) | |
434 | ); | |
435 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_14 ( | |
436 | .dout (c3_14), | |
437 | .din0 (din[23]), | |
438 | .din1 (din[24]), | |
439 | .din2 (din[25]) | |
440 | ); | |
441 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_20 ( | |
442 | .dout (c3_20), | |
443 | .din0 (c3_10), | |
444 | .din1 (c3_11), | |
445 | .din2 (c3_12) | |
446 | ); | |
447 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_21 ( | |
448 | .dout (c3_21), | |
449 | .din0 (c3_13), | |
450 | .din1 (c3_14), | |
451 | .din2 (parity[3]) | |
452 | ); | |
453 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c3_slice_22a ( | |
454 | .dout (c3_1), | |
455 | .din0 (c3_20), | |
456 | .din1 (c3_21) | |
457 | ); | |
458 | ||
459 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c3_slice_22b ( | |
460 | .dout (c3_2), | |
461 | .din0 (c3_20), | |
462 | .din1 (c3_21) | |
463 | ); | |
464 | ||
465 | ||
466 | // assign c4= parity[4]^(din[11]^din[12])^(din[13]^din[14])^ | |
467 | // (din[15]^din[16])^(din[17]^din[18])^(din[19]^din[20])^ | |
468 | // (din[21]^din[22])^(din[23]^din[24])^din[25]; | |
469 | ||
470 | ||
471 | ||
472 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_10 ( | |
473 | .dout (c4_10), | |
474 | .din0 (din[11]), | |
475 | .din1 (din[12]), | |
476 | .din2 (din[13]) | |
477 | ); | |
478 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_11 ( | |
479 | .dout (c4_11), | |
480 | .din0 (din[14]), | |
481 | .din1 (din[15]), | |
482 | .din2 (din[16]) | |
483 | ); | |
484 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_12 ( | |
485 | .dout (c4_12), | |
486 | .din0 (din[17]), | |
487 | .din1 (din[18]), | |
488 | .din2 (din[19]) | |
489 | ); | |
490 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_13 ( | |
491 | .dout (c4_13), | |
492 | .din0 (din[20]), | |
493 | .din1 (din[21]), | |
494 | .din2 (din[22]) | |
495 | ); | |
496 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_14 ( | |
497 | .dout (c4_14), | |
498 | .din0 (din[23]), | |
499 | .din1 (din[24]), | |
500 | .din2 (din[25]) | |
501 | ); | |
502 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_20 ( | |
503 | .dout (c4_20), | |
504 | .din0 (c4_10), | |
505 | .din1 (c4_11), | |
506 | .din2 (c4_12) | |
507 | ); | |
508 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_21 ( | |
509 | .dout (c4_21), | |
510 | .din0 (c4_13), | |
511 | .din1 (c4_14), | |
512 | .din2 (parity[4]) | |
513 | ); | |
514 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c4_slice_22a ( | |
515 | .dout (c4_1), | |
516 | .din0 (c4_20), | |
517 | .din1 (c4_21) | |
518 | ); | |
519 | ||
520 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c4_slice_22b ( | |
521 | .dout (c4_2), | |
522 | .din0 (c4_20), | |
523 | .din1 (c4_21) | |
524 | ); | |
525 | ||
526 | ||
527 | ||
528 | // assign c5= parity[5]^(din[26]^din[27])^(din[28]^din[29])^ | |
529 | // (din[30]^din[31]); | |
530 | ||
531 | ||
532 | ||
533 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c5_slice_10 ( | |
534 | .dout (c5_10), | |
535 | .din0 (din[26]), | |
536 | .din1 (din[27]), | |
537 | .din2 (din[28]) | |
538 | ); | |
539 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c5_slice_11 ( | |
540 | .dout (c5_11), | |
541 | .din0 (din[29]), | |
542 | .din1 (din[30]), | |
543 | .din2 (din[31]) | |
544 | ); | |
545 | l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c5_slice_20 ( | |
546 | .dout (c5), | |
547 | .din0 (c5_10), | |
548 | .din1 (c5_11), | |
549 | .din2 (parity[5]) | |
550 | ); | |
551 | ||
552 | ||
553 | // //generate total parity flag | |
554 | // | |
555 | //assign c0_intern= parity[0]^(din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8]) | |
556 | // ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19]) | |
557 | // ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]); | |
558 | // | |
559 | //assign pflag= c0_intern ^ | |
560 | // (( (((parity[1]^parity[2])^(parity[3]^parity[4])) ^ | |
561 | // ((parity[5]^parity[6])^(din[2]^din[5]))) ^ | |
562 | // (((din[7]^din[9])^(din[12]^din[14])) ^ | |
563 | // ((din[16]^din[18])^(din[20]^din[22]))) ) ^ | |
564 | // ((din[24]^din[27])^(din[29]^din[31])) ); | |
565 | ||
566 | l2t_ecc39a_dp_prty_macro__dprty_8x__width_32 prty1_macro | |
567 | ( | |
568 | .dout (pflag_1), | |
569 | .din (din[31:0]) | |
570 | ); | |
571 | ||
572 | ||
573 | l2t_ecc39a_dp_prty_macro__dprty_8x__width_8 prty2_macro | |
574 | ( | |
575 | .dout (pflag_2), | |
576 | .din ({1'b0,parity[6:0]}) | |
577 | ); | |
578 | ||
579 | l2t_ecc39a_dp_inv_macro__dinv_8x__width_2 inv_int_pflags | |
580 | ( | |
581 | .dout ({pflag_1_n,pflag_2_n}), | |
582 | .din ({pflag_1,pflag_2}) | |
583 | ); | |
584 | ||
585 | ||
586 | l2t_ecc39a_dp_nand_macro__dnand_32x__width_3 nand_pflag_n | |
587 | ( | |
588 | .dout ({pinvterm1,pinvterm2,pflag_n}), | |
589 | .din0 ({pflag_1_n,pflag_1,pinvterm1}), | |
590 | .din1 ({pflag_2_n,pflag_2,pinvterm2}) | |
591 | ); | |
592 | ||
593 | ||
594 | ||
595 | l2t_ecc39a_dp_nand_macro__dnand_32x__width_3 nand_pflag | |
596 | ( | |
597 | .dout ({pterm1,pterm2,pflag}), | |
598 | .din0 ({pflag_1,pflag_1_n,pterm1}), | |
599 | .din1 ({pflag_2_n,pflag_2,pterm2}) | |
600 | ); | |
601 | ||
602 | ||
603 | ||
604 | assign cflag= {c5,c4_1,c3_1,c2_1,c1_1,c0_1}; | |
605 | ||
606 | ||
607 | //6 to 32 decoder | |
608 | ||
609 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c0_inv_slice_1 | |
610 | ( | |
611 | .din (c0_1), | |
612 | .dout (nc0_1) | |
613 | ); | |
614 | ||
615 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c0_inv_slice_2 | |
616 | ( | |
617 | .din (c0_3), | |
618 | .dout (nc0_2) | |
619 | ); | |
620 | ||
621 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c1_inv_slice_1 | |
622 | ( | |
623 | .din (c1_1), | |
624 | .dout (nc1_1) | |
625 | ); | |
626 | ||
627 | ||
628 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c1_inv_slice_2 | |
629 | ( | |
630 | .din (c1_2), | |
631 | .dout (nc1_2) | |
632 | ); | |
633 | ||
634 | ||
635 | ||
636 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c2_inv_slice_1 | |
637 | ( | |
638 | .din (c2_1), | |
639 | .dout (nc2_1) | |
640 | ); | |
641 | ||
642 | ||
643 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c2_inv_slice_2 | |
644 | ( | |
645 | .din (c2_2), | |
646 | .dout (nc2_2) | |
647 | ); | |
648 | ||
649 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c3_inv_slice_1 | |
650 | ( | |
651 | .din (c3_1), | |
652 | .dout (nc3_1) | |
653 | ); | |
654 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c3_inv_slice_2 | |
655 | ( | |
656 | .din (c3_1), | |
657 | .dout (nc3_2) | |
658 | ); | |
659 | ||
660 | ||
661 | ||
662 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c4_inv_slice_1 | |
663 | ( | |
664 | .din (c4_1), | |
665 | .dout (nc4_1) | |
666 | ); | |
667 | ||
668 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c4_inv_slice_2 | |
669 | ( | |
670 | .din (c4_2), | |
671 | .dout (nc4_2) | |
672 | ); | |
673 | ||
674 | ||
675 | ||
676 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c5_inv_slice_1 | |
677 | ( | |
678 | .din (c5), | |
679 | .dout (nc5_1) | |
680 | ); | |
681 | ||
682 | ||
683 | l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c5_inv_slice_2 | |
684 | ( | |
685 | .din (c5), | |
686 | .dout (nc5_2) | |
687 | ); | |
688 | ||
689 | ||
690 | // bit 0 | |
691 | ||
692 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit0_pos_slice_10a ( | |
693 | .dout (err_bit0_pos_10a), | |
694 | .din0 (c0_2), | |
695 | .din1 (c1_1), | |
696 | .din2 (nc2_1) | |
697 | ); | |
698 | ||
699 | ||
700 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit0_pos_slice_10b ( | |
701 | .dout (err_bit0_pos_10b), | |
702 | .din0 (nc3_1), | |
703 | .din1 (nc4_1), | |
704 | .din2 (nc5_1) | |
705 | ); | |
706 | ||
707 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit0_pos_slice_10c ( | |
708 | .dout (err_bit_pos[0]), | |
709 | .din0 (err_bit0_pos_10a), | |
710 | .din1 (err_bit0_pos_10b) | |
711 | ); | |
712 | ||
713 | // bit 1 | |
714 | ||
715 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit1_pos_slice_10a ( | |
716 | .dout (err_bit1_pos_10a), | |
717 | .din0 (c0_2), | |
718 | .din1 (nc1_1), | |
719 | .din2 (c2_1) | |
720 | ); | |
721 | ||
722 | ||
723 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit1_pos_slice_10b ( | |
724 | .dout (err_bit1_pos_10b), | |
725 | .din0 (nc3_1), | |
726 | .din1 (nc4_1), | |
727 | .din2 (nc5_1) | |
728 | ); | |
729 | ||
730 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit1_pos_slice_10c ( | |
731 | .dout (err_bit_pos[1]), | |
732 | .din0 (err_bit1_pos_10a), | |
733 | .din1 (err_bit1_pos_10b) | |
734 | ); | |
735 | ||
736 | // bit 2 | |
737 | ||
738 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit2_pos_slice_10a ( | |
739 | .dout (err_bit2_pos_10a), | |
740 | .din0 (nc0_1), | |
741 | .din1 (c1_1), | |
742 | .din2 (c2_1) | |
743 | ); | |
744 | ||
745 | ||
746 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit2_pos_slice_10b ( | |
747 | .dout (err_bit2_pos_10b), | |
748 | .din0 (nc3_1), | |
749 | .din1 (nc4_1), | |
750 | .din2 (nc5_1) | |
751 | ); | |
752 | ||
753 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit2_pos_slice_10c ( | |
754 | .dout (err_bit_pos[2]), | |
755 | .din0 (err_bit2_pos_10a), | |
756 | .din1 (err_bit2_pos_10b) | |
757 | ); | |
758 | ||
759 | ||
760 | // bit 3 | |
761 | ||
762 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit3_pos_slice_10a ( | |
763 | .dout (err_bit3_pos_10a), | |
764 | .din0 (c0_2), | |
765 | .din1 (c1_1), | |
766 | .din2 (c2_1) | |
767 | ); | |
768 | ||
769 | ||
770 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit3_pos_slice_10b ( | |
771 | .dout (err_bit3_pos_10b), | |
772 | .din0 (nc3_1), | |
773 | .din1 (nc4_1), | |
774 | .din2 (nc5_1) | |
775 | ); | |
776 | ||
777 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit3_pos_slice_10c ( | |
778 | .dout (err_bit_pos[3]), | |
779 | .din0 (err_bit3_pos_10a), | |
780 | .din1 (err_bit3_pos_10b) | |
781 | ); | |
782 | ||
783 | ||
784 | // bit 4 | |
785 | ||
786 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit4_pos_slice_10a ( | |
787 | .dout (err_bit4_pos_10a), | |
788 | .din0 (c0_2), | |
789 | .din1 (nc1_1), | |
790 | .din2 (nc2_1) | |
791 | ); | |
792 | ||
793 | ||
794 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit4_pos_slice_10b ( | |
795 | .dout (err_bit4_pos_10b), | |
796 | .din0 (c3_1), | |
797 | .din1 (nc4_1), | |
798 | .din2 (nc5_1) | |
799 | ); | |
800 | ||
801 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit4_pos_slice_10c ( | |
802 | .dout (err_bit_pos[4]), | |
803 | .din0 (err_bit4_pos_10a), | |
804 | .din1 (err_bit4_pos_10b) | |
805 | ); | |
806 | ||
807 | // bit 5 | |
808 | ||
809 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit5_pos_slice_10a ( | |
810 | .dout (err_bit5_pos_10a), | |
811 | .din0 (nc0_1), | |
812 | .din1 (c1_1), | |
813 | .din2 (nc2_1) | |
814 | ); | |
815 | ||
816 | ||
817 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit5_pos_slice_10b ( | |
818 | .dout (err_bit5_pos_10b), | |
819 | .din0 (c3_1), | |
820 | .din1 (nc4_2), | |
821 | .din2 (nc5_1) | |
822 | ); | |
823 | ||
824 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit5_pos_slice_10c ( | |
825 | .dout (err_bit_pos[5]), | |
826 | .din0 (err_bit5_pos_10a), | |
827 | .din1 (err_bit5_pos_10b) | |
828 | ); | |
829 | ||
830 | // bit 6 | |
831 | ||
832 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit6_pos_slice_10a ( | |
833 | .dout (err_bit6_pos_10a), | |
834 | .din0 (c0_1), | |
835 | .din1 (c1_1), | |
836 | .din2 (nc2_1) | |
837 | ); | |
838 | ||
839 | ||
840 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit6_pos_slice_10b ( | |
841 | .dout (err_bit6_pos_10b), | |
842 | .din0 (c3_1), | |
843 | .din1 (nc4_2), | |
844 | .din2 (nc5_1) | |
845 | ); | |
846 | ||
847 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit6_pos_slice_10c ( | |
848 | .dout (err_bit_pos[6]), | |
849 | .din0 (err_bit6_pos_10a), | |
850 | .din1 (err_bit6_pos_10b) | |
851 | ); | |
852 | ||
853 | // bit 7 | |
854 | ||
855 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit7_pos_slice_10a ( | |
856 | .dout (err_bit7_pos_10a), | |
857 | .din0 (nc0_1), | |
858 | .din1 (nc1_1), | |
859 | .din2 (c2_1) | |
860 | ); | |
861 | ||
862 | ||
863 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit7_pos_slice_10b ( | |
864 | .dout (err_bit7_pos_10b), | |
865 | .din0 (c3_1), | |
866 | .din1 (nc4_2), | |
867 | .din2 (nc5_1) | |
868 | ); | |
869 | ||
870 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit7_pos_slice_10c ( | |
871 | .dout (err_bit_pos[7]), | |
872 | .din0 (err_bit7_pos_10a), | |
873 | .din1 (err_bit7_pos_10b) | |
874 | ); | |
875 | ||
876 | // bit 8 | |
877 | ||
878 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit8_pos_slice_10a ( | |
879 | .dout (err_bit8_pos_10a), | |
880 | .din0 (c0_2), | |
881 | .din1 (nc1_1), | |
882 | .din2 (c2_1) | |
883 | ); | |
884 | ||
885 | ||
886 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit8_pos_slice_10b ( | |
887 | .dout (err_bit8_pos_10b), | |
888 | .din0 (c3_1), | |
889 | .din1 (nc4_2), | |
890 | .din2 (nc5_2) | |
891 | ); | |
892 | ||
893 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit8_pos_slice_10c ( | |
894 | .dout (err_bit_pos[8]), | |
895 | .din0 (err_bit8_pos_10a), | |
896 | .din1 (err_bit8_pos_10b) | |
897 | ); | |
898 | ||
899 | // bit 9 | |
900 | ||
901 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit9_pos_slice_10a ( | |
902 | .dout (err_bit9_pos_10a), | |
903 | .din0 (nc0_1), | |
904 | .din1 (c1_1), | |
905 | .din2 (c2_1) | |
906 | ); | |
907 | ||
908 | ||
909 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit9_pos_slice_10b ( | |
910 | .dout (err_bit9_pos_10b), | |
911 | .din0 (c3_1), | |
912 | .din1 (nc4_2), | |
913 | .din2 (nc5_2) | |
914 | ); | |
915 | ||
916 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit9_pos_slice_10c ( | |
917 | .dout (err_bit_pos[9]), | |
918 | .din0 (err_bit9_pos_10a), | |
919 | .din1 (err_bit9_pos_10b) | |
920 | ); | |
921 | ||
922 | // bit 10 | |
923 | ||
924 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit10_pos_slice_10a ( | |
925 | .dout (err_bit10_pos_10a), | |
926 | .din0 (c0_1), | |
927 | .din1 (c1_1), | |
928 | .din2 (c2_2) | |
929 | ); | |
930 | ||
931 | ||
932 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit10_pos_slice_10b ( | |
933 | .dout (err_bit10_pos_10b), | |
934 | .din0 (c3_1), | |
935 | .din1 (nc4_1), | |
936 | .din2 (nc5_2) | |
937 | ); | |
938 | ||
939 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit10_pos_slice_10c ( | |
940 | .dout (err_bit_pos[10]), | |
941 | .din0 (err_bit10_pos_10a), | |
942 | .din1 (err_bit10_pos_10b) | |
943 | ); | |
944 | ||
945 | // bit 11 | |
946 | ||
947 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit11_pos_slice_10a ( | |
948 | .dout (err_bit11_pos_10a), | |
949 | .din0 (c0_2), | |
950 | .din1 (nc1_1), | |
951 | .din2 (nc2_1) | |
952 | ); | |
953 | ||
954 | ||
955 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit11_pos_slice_10b ( | |
956 | .dout (err_bit11_pos_10b), | |
957 | .din0 (nc3_1), | |
958 | .din1 (c4_1), | |
959 | .din2 (nc5_2) | |
960 | ); | |
961 | ||
962 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit11_pos_slice_10c ( | |
963 | .dout (err_bit_pos[11]), | |
964 | .din0 (err_bit11_pos_10a), | |
965 | .din1 (err_bit11_pos_10b) | |
966 | ); | |
967 | ||
968 | // bit 12 | |
969 | ||
970 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit12_pos_slice_10a ( | |
971 | .dout (err_bit12_pos_10a), | |
972 | .din0 (nc0_1), | |
973 | .din1 (c1_1), | |
974 | .din2 (nc2_2) | |
975 | ); | |
976 | ||
977 | ||
978 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit12_pos_slice_10b ( | |
979 | .dout (err_bit12_pos_10b), | |
980 | .din0 (nc3_2), | |
981 | .din1 (c4_1), | |
982 | .din2 (nc5_2) | |
983 | ); | |
984 | ||
985 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit12_pos_slice_10c ( | |
986 | .dout (err_bit_pos[12]), | |
987 | .din0 (err_bit12_pos_10a), | |
988 | .din1 (err_bit12_pos_10b) | |
989 | ); | |
990 | ||
991 | // bit 13 | |
992 | ||
993 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit13_pos_slice_10a ( | |
994 | .dout (err_bit13_pos_10a), | |
995 | .din0 (c0_2), | |
996 | .din1 (c1_1), | |
997 | .din2 (nc2_2) | |
998 | ); | |
999 | ||
1000 | ||
1001 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit13_pos_slice_10b ( | |
1002 | .dout (err_bit13_pos_10b), | |
1003 | .din0 (nc3_2), | |
1004 | .din1 (c4_1), | |
1005 | .din2 (nc5_2) | |
1006 | ); | |
1007 | ||
1008 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit13_pos_slice_10c ( | |
1009 | .dout (err_bit_pos[13]), | |
1010 | .din0 (err_bit13_pos_10a), | |
1011 | .din1 (err_bit13_pos_10b) | |
1012 | ); | |
1013 | ||
1014 | // bit 14 | |
1015 | ||
1016 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit14_pos_slice_10a ( | |
1017 | .dout (err_bit14_pos_10a), | |
1018 | .din0 (nc0_1), | |
1019 | .din1 (nc1_2), | |
1020 | .din2 (c2_2) | |
1021 | ); | |
1022 | ||
1023 | ||
1024 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit14_pos_slice_10b ( | |
1025 | .dout (err_bit14_pos_10b), | |
1026 | .din0 (nc3_2), | |
1027 | .din1 (c4_1), | |
1028 | .din2 (nc5_2) | |
1029 | ); | |
1030 | ||
1031 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit14_pos_slice_10c ( | |
1032 | .dout (err_bit_pos[14]), | |
1033 | .din0 (err_bit14_pos_10a), | |
1034 | .din1 (err_bit14_pos_10b) | |
1035 | ); | |
1036 | ||
1037 | // bit 15 | |
1038 | ||
1039 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit15_pos_slice_10a ( | |
1040 | .dout (err_bit15_pos_10a), | |
1041 | .din0 (c0_2), | |
1042 | .din1 (nc1_2), | |
1043 | .din2 (c2_2) | |
1044 | ); | |
1045 | ||
1046 | ||
1047 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit15_pos_slice_10b ( | |
1048 | .dout (err_bit15_pos_10b), | |
1049 | .din0 (nc3_2), | |
1050 | .din1 (c4_2), | |
1051 | .din2 (nc5_2) | |
1052 | ); | |
1053 | ||
1054 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit15_pos_slice_10c ( | |
1055 | .dout (err_bit_pos[15]), | |
1056 | .din0 (err_bit15_pos_10a), | |
1057 | .din1 (err_bit15_pos_10b) | |
1058 | ); | |
1059 | ||
1060 | // bit 16 | |
1061 | ||
1062 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit16_pos_slice_10a ( | |
1063 | .dout (err_bit16_pos_10a), | |
1064 | .din0 (nc0_2), | |
1065 | .din1 (c1_2), | |
1066 | .din2 (c2_2) | |
1067 | ); | |
1068 | ||
1069 | ||
1070 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit16_pos_slice_10b ( | |
1071 | .dout (err_bit16_pos_10b), | |
1072 | .din0 (nc3_2), | |
1073 | .din1 (c4_2), | |
1074 | .din2 (nc5_2) | |
1075 | ); | |
1076 | ||
1077 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit16_pos_slice_10c ( | |
1078 | .dout (err_bit_pos[16]), | |
1079 | .din0 (err_bit16_pos_10a), | |
1080 | .din1 (err_bit16_pos_10b) | |
1081 | ); | |
1082 | ||
1083 | // bit 17 | |
1084 | ||
1085 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit17_pos_slice_10a ( | |
1086 | .dout (err_bit17_pos_10a), | |
1087 | .din0 (c0_3), | |
1088 | .din1 (c1_2), | |
1089 | .din2 (c2_2) | |
1090 | ); | |
1091 | ||
1092 | ||
1093 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit17_pos_slice_10b ( | |
1094 | .dout (err_bit17_pos_10b), | |
1095 | .din0 (nc3_2), | |
1096 | .din1 (c4_2), | |
1097 | .din2 (nc5_2) | |
1098 | ); | |
1099 | ||
1100 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit17_pos_slice_10c ( | |
1101 | .dout (err_bit_pos[17]), | |
1102 | .din0 (err_bit17_pos_10a), | |
1103 | .din1 (err_bit17_pos_10b) | |
1104 | ); | |
1105 | ||
1106 | // bit 18 | |
1107 | ||
1108 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit18_pos_slice_10a ( | |
1109 | .dout (err_bit18_pos_10a), | |
1110 | .din0 (nc0_2), | |
1111 | .din1 (nc1_2), | |
1112 | .din2 (nc2_2) | |
1113 | ); | |
1114 | ||
1115 | ||
1116 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit18_pos_slice_10b ( | |
1117 | .dout (err_bit18_pos_10b), | |
1118 | .din0 (c3_2), | |
1119 | .din1 (c4_2), | |
1120 | .din2 (nc5_1) | |
1121 | ); | |
1122 | ||
1123 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit18_pos_slice_10c ( | |
1124 | .dout (err_bit_pos[18]), | |
1125 | .din0 (err_bit18_pos_10a), | |
1126 | .din1 (err_bit18_pos_10b) | |
1127 | ); | |
1128 | ||
1129 | // bit 19 | |
1130 | ||
1131 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit19_pos_slice_10a ( | |
1132 | .dout (err_bit19_pos_10a), | |
1133 | .din0 (c0_3), | |
1134 | .din1 (nc1_2), | |
1135 | .din2 (nc2_2) | |
1136 | ); | |
1137 | ||
1138 | ||
1139 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit19_pos_slice_10b ( | |
1140 | .dout (err_bit19_pos_10b), | |
1141 | .din0 (c3_2), | |
1142 | .din1 (c4_1), | |
1143 | .din2 (nc5_1) | |
1144 | ); | |
1145 | ||
1146 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit19_pos_slice_10c ( | |
1147 | .dout (err_bit_pos[19]), | |
1148 | .din0 (err_bit19_pos_10a), | |
1149 | .din1 (err_bit19_pos_10b) | |
1150 | ); | |
1151 | ||
1152 | // bit 20 | |
1153 | ||
1154 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit20_pos_slice_10a ( | |
1155 | .dout (err_bit20_pos_10a), | |
1156 | .din0 (nc0_2), | |
1157 | .din1 (c1_2), | |
1158 | .din2 (nc2_2) | |
1159 | ); | |
1160 | ||
1161 | ||
1162 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit20_pos_slice_10b ( | |
1163 | .dout (err_bit20_pos_10b), | |
1164 | .din0 (c3_2), | |
1165 | .din1 (c4_2), | |
1166 | .din2 (nc5_1) | |
1167 | ); | |
1168 | ||
1169 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit20_pos_slice_10c ( | |
1170 | .dout (err_bit_pos[20]), | |
1171 | .din0 (err_bit20_pos_10a), | |
1172 | .din1 (err_bit20_pos_10b) | |
1173 | ); | |
1174 | ||
1175 | // bit 21 | |
1176 | ||
1177 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit21_pos_slice_10a ( | |
1178 | .dout (err_bit21_pos_10a), | |
1179 | .din0 (c0_3), | |
1180 | .din1 (c1_2), | |
1181 | .din2 (nc2_2) | |
1182 | ); | |
1183 | ||
1184 | ||
1185 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit21_pos_slice_10b ( | |
1186 | .dout (err_bit21_pos_10b), | |
1187 | .din0 (c3_2), | |
1188 | .din1 (c4_1), | |
1189 | .din2 (nc5_2) | |
1190 | ); | |
1191 | ||
1192 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit21_pos_slice_10c ( | |
1193 | .dout (err_bit_pos[21]), | |
1194 | .din0 (err_bit21_pos_10a), | |
1195 | .din1 (err_bit21_pos_10b) | |
1196 | ); | |
1197 | ||
1198 | // bit 22 | |
1199 | ||
1200 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit22_pos_slice_10a ( | |
1201 | .dout (err_bit22_pos_10a), | |
1202 | .din0 (nc0_2), | |
1203 | .din1 (nc1_2), | |
1204 | .din2 (c2_2) | |
1205 | ); | |
1206 | ||
1207 | ||
1208 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit22_pos_slice_10b ( | |
1209 | .dout (err_bit22_pos_10b), | |
1210 | .din0 (c3_2), | |
1211 | .din1 (c4_2), | |
1212 | .din2 (nc5_2) | |
1213 | ); | |
1214 | ||
1215 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit22_pos_slice_10c ( | |
1216 | .dout (err_bit_pos[22]), | |
1217 | .din0 (err_bit22_pos_10a), | |
1218 | .din1 (err_bit22_pos_10b) | |
1219 | ); | |
1220 | ||
1221 | // bit 23 | |
1222 | ||
1223 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit23_pos_slice_10a ( | |
1224 | .dout (err_bit23_pos_10a), | |
1225 | .din0 (c0_3), | |
1226 | .din1 (nc1_2), | |
1227 | .din2 (c2_2) | |
1228 | ); | |
1229 | ||
1230 | ||
1231 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit23_pos_slice_10b ( | |
1232 | .dout (err_bit23_pos_10b), | |
1233 | .din0 (c3_2), | |
1234 | .din1 (c4_1), | |
1235 | .din2 (nc5_2) | |
1236 | ); | |
1237 | ||
1238 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit23_pos_slice_10c ( | |
1239 | .dout (err_bit_pos[23]), | |
1240 | .din0 (err_bit23_pos_10a), | |
1241 | .din1 (err_bit23_pos_10b) | |
1242 | ); | |
1243 | ||
1244 | // bit 24 | |
1245 | ||
1246 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit24_pos_slice_10a ( | |
1247 | .dout (err_bit24_pos_10a), | |
1248 | .din0 (nc0_2), | |
1249 | .din1 (c1_2), | |
1250 | .din2 (c2_2) | |
1251 | ); | |
1252 | ||
1253 | ||
1254 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit24_pos_slice_10b ( | |
1255 | .dout (err_bit24_pos_10b), | |
1256 | .din0 (c3_2), | |
1257 | .din1 (c4_2), | |
1258 | .din2 (nc5_2) | |
1259 | ); | |
1260 | ||
1261 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit24_pos_slice_10c ( | |
1262 | .dout (err_bit_pos[24]), | |
1263 | .din0 (err_bit24_pos_10a), | |
1264 | .din1 (err_bit24_pos_10b) | |
1265 | ); | |
1266 | ||
1267 | // bit 25 | |
1268 | ||
1269 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit25_pos_slice_10a ( | |
1270 | .dout (err_bit25_pos_10a), | |
1271 | .din0 (c0_3), | |
1272 | .din1 (c1_2), | |
1273 | .din2 (c2_2) | |
1274 | ); | |
1275 | ||
1276 | ||
1277 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit25_pos_slice_10b ( | |
1278 | .dout (err_bit25_pos_10b), | |
1279 | .din0 (c3_2), | |
1280 | .din1 (c4_2), | |
1281 | .din2 (nc5_1) | |
1282 | ); | |
1283 | ||
1284 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit25_pos_slice_10c ( | |
1285 | .dout (err_bit_pos[25]), | |
1286 | .din0 (err_bit25_pos_10a), | |
1287 | .din1 (err_bit25_pos_10b) | |
1288 | ); | |
1289 | ||
1290 | // bit 26 | |
1291 | ||
1292 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit26_pos_slice_10a ( | |
1293 | .dout (err_bit26_pos_10a), | |
1294 | .din0 (c0_3), | |
1295 | .din1 (nc1_1), | |
1296 | .din2 (nc2_1) | |
1297 | ); | |
1298 | ||
1299 | ||
1300 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit26_pos_slice_10b ( | |
1301 | .dout (err_bit26_pos_10b), | |
1302 | .din0 (nc3_2), | |
1303 | .din1 (nc4_1), | |
1304 | .din2 (c5) | |
1305 | ); | |
1306 | ||
1307 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit26_pos_slice_10c ( | |
1308 | .dout (err_bit_pos[26]), | |
1309 | .din0 (err_bit26_pos_10a), | |
1310 | .din1 (err_bit26_pos_10b) | |
1311 | ); | |
1312 | ||
1313 | // bit 27 | |
1314 | ||
1315 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit27_pos_slice_10a ( | |
1316 | .dout (err_bit27_pos_10a), | |
1317 | .din0 (nc0_2), | |
1318 | .din1 (c1_2), | |
1319 | .din2 (nc2_1) | |
1320 | ); | |
1321 | ||
1322 | ||
1323 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit27_pos_slice_10b ( | |
1324 | .dout (err_bit27_pos_10b), | |
1325 | .din0 (nc3_2), | |
1326 | .din1 (nc4_1), | |
1327 | .din2 (c5) | |
1328 | ); | |
1329 | ||
1330 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit27_pos_slice_10c ( | |
1331 | .dout (err_bit_pos[27]), | |
1332 | .din0 (err_bit27_pos_10a), | |
1333 | .din1 (err_bit27_pos_10b) | |
1334 | ); | |
1335 | ||
1336 | // bit 28 | |
1337 | ||
1338 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit28_pos_slice_10a ( | |
1339 | .dout (err_bit28_pos_10a), | |
1340 | .din0 (c0_3), | |
1341 | .din1 (c1_2), | |
1342 | .din2 (nc2_1) | |
1343 | ); | |
1344 | ||
1345 | ||
1346 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit28_pos_slice_10b ( | |
1347 | .dout (err_bit28_pos_10b), | |
1348 | .din0 (nc3_1), | |
1349 | .din1 (nc4_1), | |
1350 | .din2 (c5) | |
1351 | ); | |
1352 | ||
1353 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit28_pos_slice_10c ( | |
1354 | .dout (err_bit_pos[28]), | |
1355 | .din0 (err_bit28_pos_10a), | |
1356 | .din1 (err_bit28_pos_10b) | |
1357 | ); | |
1358 | ||
1359 | // bit 29 | |
1360 | ||
1361 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit29_pos_slice_10a ( | |
1362 | .dout (err_bit29_pos_10a), | |
1363 | .din0 (nc0_2), | |
1364 | .din1 (nc1_1), | |
1365 | .din2 (c2_2) | |
1366 | ); | |
1367 | ||
1368 | ||
1369 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit29_pos_slice_10b ( | |
1370 | .dout (err_bit29_pos_10b), | |
1371 | .din0 (nc3_1), | |
1372 | .din1 (nc4_1), | |
1373 | .din2 (c5) | |
1374 | ); | |
1375 | ||
1376 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit29_pos_slice_10c ( | |
1377 | .dout (err_bit_pos[29]), | |
1378 | .din0 (err_bit29_pos_10a), | |
1379 | .din1 (err_bit29_pos_10b) | |
1380 | ); | |
1381 | ||
1382 | // bit 30 | |
1383 | ||
1384 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit30_pos_slice_10a ( | |
1385 | .dout (err_bit30_pos_10a), | |
1386 | .din0 (c0_3), | |
1387 | .din1 (nc1_1), | |
1388 | .din2 (c2_1) | |
1389 | ); | |
1390 | ||
1391 | ||
1392 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit30_pos_slice_10b ( | |
1393 | .dout (err_bit30_pos_10b), | |
1394 | .din0 (nc3_1), | |
1395 | .din1 (nc4_2), | |
1396 | .din2 (c5) | |
1397 | ); | |
1398 | ||
1399 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit30_pos_slice_10c ( | |
1400 | .dout (err_bit_pos[30]), | |
1401 | .din0 (err_bit30_pos_10a), | |
1402 | .din1 (err_bit30_pos_10b) | |
1403 | ); | |
1404 | ||
1405 | // bit 31 | |
1406 | ||
1407 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit31_pos_slice_10a ( | |
1408 | .dout (err_bit31_pos_10a), | |
1409 | .din0 (nc0_2), | |
1410 | .din1 (c1_2), | |
1411 | .din2 (c2_1) | |
1412 | ); | |
1413 | ||
1414 | ||
1415 | l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit31_pos_slice_10b ( | |
1416 | .dout (err_bit31_pos_10b), | |
1417 | .din0 (nc3_1), | |
1418 | .din1 (nc4_2), | |
1419 | .din2 (c5) | |
1420 | ); | |
1421 | ||
1422 | l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit31_pos_slice_10c ( | |
1423 | .dout (err_bit_pos[31]), | |
1424 | .din0 (err_bit31_pos_10a), | |
1425 | .din1 (err_bit31_pos_10b) | |
1426 | ); | |
1427 | ||
1428 | ||
1429 | // correct the error bit, it can only correct one error bit. | |
1430 | // assign dout = din ^ err_bit_pos; | |
1431 | ||
1432 | l2t_ecc39a_dp_xor_macro__dxor_16x__width_32 dout_slice | |
1433 | ( | |
1434 | .dout (dout[31:0]), | |
1435 | .din0 (din[31:0]), | |
1436 | .din1 (err_bit_pos[31:0]) | |
1437 | ); | |
1438 | ||
1439 | ||
1440 | endmodule | |
1441 | ||
1442 | ||
1443 | // | |
1444 | // xor macro for ports = 2,3 | |
1445 | // | |
1446 | // | |
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | ||
1452 | module l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 ( | |
1453 | din0, | |
1454 | din1, | |
1455 | din2, | |
1456 | dout); | |
1457 | input [0:0] din0; | |
1458 | input [0:0] din1; | |
1459 | input [0:0] din2; | |
1460 | output [0:0] dout; | |
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | xor3 #(1) d0_0 ( | |
1467 | .in0(din0[0:0]), | |
1468 | .in1(din1[0:0]), | |
1469 | .in2(din2[0:0]), | |
1470 | .out(dout[0:0]) | |
1471 | ); | |
1472 | ||
1473 | ||
1474 | ||
1475 | ||
1476 | ||
1477 | ||
1478 | ||
1479 | ||
1480 | endmodule | |
1481 | ||
1482 | ||
1483 | ||
1484 | ||
1485 | ||
1486 | // | |
1487 | // xor macro for ports = 2,3 | |
1488 | // | |
1489 | // | |
1490 | ||
1491 | ||
1492 | ||
1493 | ||
1494 | ||
1495 | module l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 ( | |
1496 | din0, | |
1497 | din1, | |
1498 | dout); | |
1499 | input [0:0] din0; | |
1500 | input [0:0] din1; | |
1501 | output [0:0] dout; | |
1502 | ||
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | xor2 #(1) d0_0 ( | |
1508 | .in0(din0[0:0]), | |
1509 | .in1(din1[0:0]), | |
1510 | .out(dout[0:0]) | |
1511 | ); | |
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | endmodule | |
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | // | |
1527 | // parity macro (even parity) | |
1528 | // | |
1529 | // | |
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | module l2t_ecc39a_dp_prty_macro__dprty_8x__width_32 ( | |
1536 | din, | |
1537 | dout); | |
1538 | input [31:0] din; | |
1539 | output dout; | |
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | ||
1547 | prty #(32) m0_0 ( | |
1548 | .in(din[31:0]), | |
1549 | .out(dout) | |
1550 | ); | |
1551 | ||
1552 | ||
1553 | ||
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | ||
1559 | ||
1560 | ||
1561 | endmodule | |
1562 | ||
1563 | ||
1564 | ||
1565 | ||
1566 | ||
1567 | // | |
1568 | // parity macro (even parity) | |
1569 | // | |
1570 | // | |
1571 | ||
1572 | ||
1573 | ||
1574 | ||
1575 | ||
1576 | module l2t_ecc39a_dp_prty_macro__dprty_8x__width_8 ( | |
1577 | din, | |
1578 | dout); | |
1579 | input [7:0] din; | |
1580 | output dout; | |
1581 | ||
1582 | ||
1583 | ||
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | prty #(8) m0_0 ( | |
1589 | .in(din[7:0]), | |
1590 | .out(dout) | |
1591 | ); | |
1592 | ||
1593 | ||
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | endmodule | |
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | // | |
1609 | // invert macro | |
1610 | // | |
1611 | // | |
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | module l2t_ecc39a_dp_inv_macro__dinv_8x__width_2 ( | |
1618 | din, | |
1619 | dout); | |
1620 | input [1:0] din; | |
1621 | output [1:0] dout; | |
1622 | ||
1623 | ||
1624 | ||
1625 | ||
1626 | ||
1627 | ||
1628 | inv #(2) d0_0 ( | |
1629 | .in(din[1:0]), | |
1630 | .out(dout[1:0]) | |
1631 | ); | |
1632 | ||
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | ||
1638 | ||
1639 | ||
1640 | ||
1641 | endmodule | |
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | // | |
1648 | // nand macro for ports = 2,3,4 | |
1649 | // | |
1650 | // | |
1651 | ||
1652 | ||
1653 | ||
1654 | ||
1655 | ||
1656 | module l2t_ecc39a_dp_nand_macro__dnand_32x__width_3 ( | |
1657 | din0, | |
1658 | din1, | |
1659 | dout); | |
1660 | input [2:0] din0; | |
1661 | input [2:0] din1; | |
1662 | output [2:0] dout; | |
1663 | ||
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | ||
1669 | nand2 #(3) d0_0 ( | |
1670 | .in0(din0[2:0]), | |
1671 | .in1(din1[2:0]), | |
1672 | .out(dout[2:0]) | |
1673 | ); | |
1674 | ||
1675 | ||
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | endmodule | |
1684 | ||
1685 | ||
1686 | ||
1687 | ||
1688 | ||
1689 | // | |
1690 | // invert macro | |
1691 | // | |
1692 | // | |
1693 | ||
1694 | ||
1695 | ||
1696 | ||
1697 | ||
1698 | module l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 ( | |
1699 | din, | |
1700 | dout); | |
1701 | input [0:0] din; | |
1702 | output [0:0] dout; | |
1703 | ||
1704 | ||
1705 | ||
1706 | ||
1707 | ||
1708 | ||
1709 | inv #(1) d0_0 ( | |
1710 | .in(din[0:0]), | |
1711 | .out(dout[0:0]) | |
1712 | ); | |
1713 | ||
1714 | ||
1715 | ||
1716 | ||
1717 | ||
1718 | ||
1719 | ||
1720 | ||
1721 | ||
1722 | endmodule | |
1723 | ||
1724 | ||
1725 | ||
1726 | ||
1727 | ||
1728 | // | |
1729 | // nand macro for ports = 2,3,4 | |
1730 | // | |
1731 | // | |
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | module l2t_ecc39a_dp_nand_macro__ports_3__width_1 ( | |
1738 | din0, | |
1739 | din1, | |
1740 | din2, | |
1741 | dout); | |
1742 | input [0:0] din0; | |
1743 | input [0:0] din1; | |
1744 | input [0:0] din2; | |
1745 | output [0:0] dout; | |
1746 | ||
1747 | ||
1748 | ||
1749 | ||
1750 | ||
1751 | ||
1752 | nand3 #(1) d0_0 ( | |
1753 | .in0(din0[0:0]), | |
1754 | .in1(din1[0:0]), | |
1755 | .in2(din2[0:0]), | |
1756 | .out(dout[0:0]) | |
1757 | ); | |
1758 | ||
1759 | ||
1760 | ||
1761 | ||
1762 | ||
1763 | ||
1764 | ||
1765 | ||
1766 | ||
1767 | endmodule | |
1768 | ||
1769 | ||
1770 | ||
1771 | ||
1772 | ||
1773 | // | |
1774 | // nor macro for ports = 2,3 | |
1775 | // | |
1776 | // | |
1777 | ||
1778 | ||
1779 | ||
1780 | ||
1781 | ||
1782 | module l2t_ecc39a_dp_nor_macro__ports_2__width_1 ( | |
1783 | din0, | |
1784 | din1, | |
1785 | dout); | |
1786 | input [0:0] din0; | |
1787 | input [0:0] din1; | |
1788 | output [0:0] dout; | |
1789 | ||
1790 | ||
1791 | ||
1792 | ||
1793 | ||
1794 | ||
1795 | nor2 #(1) d0_0 ( | |
1796 | .in0(din0[0:0]), | |
1797 | .in1(din1[0:0]), | |
1798 | .out(dout[0:0]) | |
1799 | ); | |
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | endmodule | |
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | // | |
1814 | // xor macro for ports = 2,3 | |
1815 | // | |
1816 | // | |
1817 | ||
1818 | ||
1819 | ||
1820 | ||
1821 | ||
1822 | module l2t_ecc39a_dp_xor_macro__dxor_16x__width_32 ( | |
1823 | din0, | |
1824 | din1, | |
1825 | dout); | |
1826 | input [31:0] din0; | |
1827 | input [31:0] din1; | |
1828 | output [31:0] dout; | |
1829 | ||
1830 | ||
1831 | ||
1832 | ||
1833 | ||
1834 | xor2 #(32) d0_0 ( | |
1835 | .in0(din0[31:0]), | |
1836 | .in1(din1[31:0]), | |
1837 | .out(dout[31:0]) | |
1838 | ); | |
1839 | ||
1840 | ||
1841 | ||
1842 | ||
1843 | ||
1844 | ||
1845 | ||
1846 | ||
1847 | endmodule | |
1848 | ||
1849 | ||
1850 | ||
1851 |