projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: l2t_iqu_ctl.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module l2t_iqu_ctl ( | |
| 36 | tcu_pce_ov, | |
| 37 | tcu_aclk, | |
| 38 | tcu_bclk, | |
| 39 | tcu_scan_en, | |
| 40 | l2clk, | |
| 41 | wmr_l, | |
| 42 | scan_in, | |
| 43 | pcx_l2t_data_rdy_px1, | |
| 44 | pcx_l2t_atm_px1, | |
| 45 | arb_iqsel_px2, | |
| 46 | arb_iqsel_px2_v1, | |
| 47 | l2t_mb2_run, | |
| 48 | l2t_mb2_iqarray_wr_en, | |
| 49 | l2t_mb2_iqarray_rd_en, | |
| 50 | l2t_mb2_addr, | |
| 51 | scan_out, | |
| 52 | iqu_iq_array_wr_en, | |
| 53 | iqu_iq_array_wr_wl, | |
| 54 | iqu_iq_array_rd_en, | |
| 55 | iqu_iq_array_rd_wl, | |
| 56 | l2t_pcx_stall_pq, | |
| 57 | iqu_iq_arb_vld_px2, | |
| 58 | iqu_iq_arb_vld_px2_v1, | |
| 59 | iqu_pcx_l2t_atm_px2_p, | |
| 60 | iqu_sel_pcx, | |
| 61 | iqu_sel_c1, | |
| 62 | iqu_hold_rd_n, | |
| 63 | iqu_sel_c1reg_over_iqarray); | |
| 64 | wire reset_flop_scanin; | |
| 65 | wire reset_flop_scanout; | |
| 66 | wire l1clk; | |
| 67 | wire pce_ov; | |
| 68 | wire stop; | |
| 69 | wire siclk; | |
| 70 | wire soclk; | |
| 71 | wire se; | |
| 72 | wire spares_scanin; | |
| 73 | wire spares_scanout; | |
| 74 | wire pcx_l2t_data_rdy_px1_fnl; | |
| 75 | wire ff_pcx_l2t_data_rdy_px1_fnl_scanin; | |
| 76 | wire ff_pcx_l2t_data_rdy_px1_fnl_scanout; | |
| 77 | wire ff_pcx_l2t_data_rdy_px2_scanin; | |
| 78 | wire ff_pcx_l2t_data_rdy_px2_scanout; | |
| 79 | wire pcx_l2t_data_rdy_px2_for_ext; | |
| 80 | wire ff_pcx_l2t_data_rdy_px2_1_scanin; | |
| 81 | wire ff_pcx_l2t_data_rdy_px2_1_scanout; | |
| 82 | wire ff_pcx_l2t_data_rdy_px2_d1_scanin; | |
| 83 | wire ff_pcx_l2t_data_rdy_px2_d1_scanout; | |
| 84 | wire ff_pcx_l2t_atm_px2_p_scanin; | |
| 85 | wire ff_pcx_l2t_atm_px2_p_scanout; | |
| 86 | wire pcx_l2t_atm_px1_fnl; | |
| 87 | wire ff_pcx_l2t_atm_px1_p_fnl_scanin; | |
| 88 | wire ff_pcx_l2t_atm_px1_p_fnl_scanout; | |
| 89 | wire ff_arb_iqsel_px2_d1_scanin; | |
| 90 | wire ff_arb_iqsel_px2_d1_scanout; | |
| 91 | wire ff_pcx_inst_vld_c1_scanin; | |
| 92 | wire ff_pcx_inst_vld_c1_scanout; | |
| 93 | wire c1_reg_inst_vld_cloned; | |
| 94 | wire ff_pcx_inst_vld_c1_1_scanin; | |
| 95 | wire ff_pcx_inst_vld_c1_1_scanout; | |
| 96 | wire ff_inc_wr_ptr_c1_scanin; | |
| 97 | wire ff_inc_wr_ptr_c1_scanout; | |
| 98 | wire ff_array_wr_ptr_plus1_scanin; | |
| 99 | wire ff_array_wr_ptr_plus1_scanout; | |
| 100 | wire ff_array_wr_ptr_scanin; | |
| 101 | wire ff_array_wr_ptr_scanout; | |
| 102 | wire ff_l2t_mb2_run_r1_scanin; | |
| 103 | wire ff_l2t_mb2_run_r1_scanout; | |
| 104 | wire l2t_mb2_run_r1; | |
| 105 | wire iqu_iq_arb_vld_px2_internal; | |
| 106 | wire ff_array_rd_ptr_scanin; | |
| 107 | wire ff_array_rd_ptr_scanout; | |
| 108 | wire ff_que_cnt_scanin; | |
| 109 | wire ff_que_cnt_scanout; | |
| 110 | wire que_cnt_9_p; | |
| 111 | wire que_cnt_10_p; | |
| 112 | wire que_cnt_10_plus_p; | |
| 113 | wire que_cnt_10_n; | |
| 114 | wire que_cnt_10_plus_n; | |
| 115 | wire ff_que_cnt_0_scanin; | |
| 116 | wire ff_que_cnt_0_scanout; | |
| 117 | wire ff_que_cnt_1_scanin; | |
| 118 | wire ff_que_cnt_1_scanout; | |
| 119 | wire ff_que_cnt_1_plus_scanin; | |
| 120 | wire ff_que_cnt_1_plus_scanout; | |
| 121 | wire ff_que_cnt_2_scanin; | |
| 122 | wire ff_que_cnt_2_scanout; | |
| 123 | wire que_cnt_10; | |
| 124 | wire ff_que_cnt_10_scanin; | |
| 125 | wire ff_que_cnt_10_scanout; | |
| 126 | wire que_cnt_10_plus; | |
| 127 | wire ff_que_cnt_10_plus_scanin; | |
| 128 | wire ff_que_cnt_10_plus_scanout; | |
| 129 | wire ff_iqu_sel_iq_scanin; | |
| 130 | wire ff_iqu_sel_iq_scanout; | |
| 131 | wire ff_iqu_sel_c1_scanin; | |
| 132 | wire ff_iqu_sel_c1_scanout; | |
| 133 | wire ff_iqu_sel_pcx_scanin; | |
| 134 | wire ff_iqu_sel_pcx_scanout; | |
| 135 | wire ff_iqu_sel_iq_d1_scanin; | |
| 136 | wire ff_iqu_sel_iq_d1_scanout; | |
| 137 | wire iqu_sel_iq_n; | |
| 138 | wire arb_iqsel_px2_v1_n; | |
| 139 | wire iqu_sel_iq_fe_n; | |
| 140 | ||
| 141 | ||
| 142 | input tcu_pce_ov; | |
| 143 | input tcu_aclk; | |
| 144 | input tcu_bclk; | |
| 145 | input tcu_scan_en; | |
| 146 | ||
| 147 | input l2clk; | |
| 148 | input wmr_l; | |
| 149 | input scan_in; | |
| 150 | input pcx_l2t_data_rdy_px1; | |
| 151 | input pcx_l2t_atm_px1; | |
| 152 | input arb_iqsel_px2; | |
| 153 | input arb_iqsel_px2_v1; | |
| 154 | ||
| 155 | input l2t_mb2_run; | |
| 156 | input l2t_mb2_iqarray_wr_en; | |
| 157 | input l2t_mb2_iqarray_rd_en; | |
| 158 | input [3:0] l2t_mb2_addr; | |
| 159 | ||
| 160 | output scan_out; | |
| 161 | output iqu_iq_array_wr_en; | |
| 162 | output [3:0] iqu_iq_array_wr_wl; | |
| 163 | output iqu_iq_array_rd_en; | |
| 164 | output [3:0] iqu_iq_array_rd_wl; | |
| 165 | ||
| 166 | output l2t_pcx_stall_pq; | |
| 167 | ||
| 168 | output iqu_iq_arb_vld_px2; | |
| 169 | output iqu_iq_arb_vld_px2_v1; | |
| 170 | output iqu_pcx_l2t_atm_px2_p; | |
| 171 | ||
| 172 | output iqu_sel_pcx; | |
| 173 | output iqu_sel_c1; | |
| 174 | //output iqu_hold_rd; | |
| 175 | output iqu_hold_rd_n; | |
| 176 | ||
| 177 | output iqu_sel_c1reg_over_iqarray; | |
| 178 | ||
| 179 | ||
| 180 | //////////////////////////////////////////////////////////////////////////////// | |
| 181 | // Local Wires declaration | |
| 182 | //////////////////////////////////////////////////////////////////////////////// | |
| 183 | wire pcx_l2t_data_rdy_px2 ; | |
| 184 | wire pcx_l2t_data_rdy_px2_d1 ; | |
| 185 | wire arb_iqsel_px2_d1 ; | |
| 186 | ||
| 187 | wire set_c1_reg_inst_vld ; | |
| 188 | wire c1_reg_inst_vld ; | |
| 189 | ||
| 190 | wire inc_wr_ptr_px2 ; | |
| 191 | wire inc_wr_ptr_c1 ; | |
| 192 | wire sel_wrptr_same, sel_wrptr_plus1 ; | |
| 193 | wire [3:0] wrptr, wrptr_plus1 ; | |
| 194 | wire [3:0] wrptr_d1, wrptr_plus1_d1 ; | |
| 195 | ||
| 196 | wire inc_rd_ptr_px2 ; | |
| 197 | wire [3:0] rdptr, rdptr_plus1 ; | |
| 198 | wire [3:0] rdptr_d1 ; | |
| 199 | ||
| 200 | wire sel_qcount_plus1 ; | |
| 201 | wire sel_qcount_minus1 ; | |
| 202 | wire sel_qcount_same ; | |
| 203 | wire [4:0] que_cnt, que_cnt_plus1, que_cnt_minus1 ; | |
| 204 | wire [4:0] next_que_cnt ; | |
| 205 | wire que_cnt_0, que_cnt_0_p, que_cnt_0_n ; | |
| 206 | wire que_cnt_1, que_cnt_1_p, que_cnt_1_n ; | |
| 207 | wire que_cnt_1_plus, que_cnt_1_plus_p, que_cnt_1_plus_n ; | |
| 208 | wire que_cnt_2, que_cnt_2_p, que_cnt_2_n ; | |
| 209 | wire que_cnt_2_plus_p ; | |
| 210 | wire que_cnt_3_p ; | |
| 211 | wire que_cnt_11_p ; | |
| 212 | wire que_cnt_12, que_cnt_12_p, que_cnt_12_n ; | |
| 213 | wire que_cnt_12_plus, que_cnt_12_plus_p, que_cnt_12_plus_n ; | |
| 214 | ||
| 215 | wire set_iqu_sel_iq ; | |
| 216 | wire set_iqu_sel_pcx ; | |
| 217 | wire iqu_sel_iq; | |
| 218 | wire iqu_sel_iq_d1; | |
| 219 | wire iqu_sel_iq_fe; | |
| 220 | ||
| 221 | wire dbb_rst_l; | |
| 222 | /////////////////////////////////////////////////////////////////// | |
| 223 | // Reset flop | |
| 224 | /////////////////////////////////////////////////////////////////// | |
| 225 | ||
| 226 | l2t_iqu_ctl_msff_ctl_macro__width_1 reset_flop | |
| 227 | ( | |
| 228 | .scan_in(reset_flop_scanin), | |
| 229 | .scan_out(reset_flop_scanout), | |
| 230 | .dout(dbb_rst_l), | |
| 231 | .l1clk(l1clk), | |
| 232 | .din(wmr_l), | |
| 233 | .siclk(siclk), | |
| 234 | .soclk(soclk) | |
| 235 | ); | |
| 236 | ||
| 237 | ||
| 238 | ////////////////////////////////////////////////// | |
| 239 | // L1 clk header | |
| 240 | ////////////////////////////////////////////////// | |
| 241 | assign pce_ov = tcu_pce_ov; | |
| 242 | assign stop = 1'b0; | |
| 243 | assign siclk = tcu_aclk; | |
| 244 | assign soclk = tcu_bclk; | |
| 245 | assign se = tcu_scan_en; | |
| 246 | ||
| 247 | l2t_iqu_ctl_l1clkhdr_ctl_macro clkgen ( | |
| 248 | .l2clk(l2clk), | |
| 249 | .l1en(1'b1 ), | |
| 250 | .l1clk(l1clk), | |
| 251 | .pce_ov(pce_ov), | |
| 252 | .stop(stop), | |
| 253 | .se(se)); | |
| 254 | ||
| 255 | ////////////////////////////////////////////////// | |
| 256 | ||
| 257 | ////////////////////////////////////////// | |
| 258 | // Spare gate insertion | |
| 259 | ////////////////////////////////////////// | |
| 260 | l2t_iqu_ctl_spare_ctl_macro__num_4 spares ( | |
| 261 | .scan_in(spares_scanin), | |
| 262 | .scan_out(spares_scanout), | |
| 263 | .l1clk (l1clk), | |
| 264 | .siclk(siclk), | |
| 265 | .soclk(soclk) | |
| 266 | ); | |
| 267 | ////////////////////////////////////////// | |
| 268 | ||
| 269 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_pcx_l2t_data_rdy_px1_fnl | |
| 270 | (.dout (pcx_l2t_data_rdy_px1_fnl), | |
| 271 | .scan_in(ff_pcx_l2t_data_rdy_px1_fnl_scanin), | |
| 272 | .scan_out(ff_pcx_l2t_data_rdy_px1_fnl_scanout), | |
| 273 | .din (pcx_l2t_data_rdy_px1), | |
| 274 | .l1clk (l1clk), | |
| 275 | .siclk(siclk), | |
| 276 | .soclk(soclk) | |
| 277 | ||
| 278 | ||
| 279 | ) ; | |
| 280 | ||
| 281 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_pcx_l2t_data_rdy_px2 | |
| 282 | (.dout (pcx_l2t_data_rdy_px2), | |
| 283 | .scan_in(ff_pcx_l2t_data_rdy_px2_scanin), | |
| 284 | .scan_out(ff_pcx_l2t_data_rdy_px2_scanout), | |
| 285 | .din (pcx_l2t_data_rdy_px1_fnl), | |
| 286 | .l1clk (l1clk), | |
| 287 | .siclk(siclk), | |
| 288 | .soclk(soclk) | |
| 289 | ) ; | |
| 290 | ||
| 291 | ||
| 292 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_pcx_l2t_data_rdy_px2_1 | |
| 293 | (.dout (pcx_l2t_data_rdy_px2_for_ext), | |
| 294 | .scan_in(ff_pcx_l2t_data_rdy_px2_1_scanin), | |
| 295 | .scan_out(ff_pcx_l2t_data_rdy_px2_1_scanout), | |
| 296 | .din (pcx_l2t_data_rdy_px1_fnl), | |
| 297 | .l1clk (l1clk), | |
| 298 | .siclk(siclk), | |
| 299 | .soclk(soclk) | |
| 300 | ) ; | |
| 301 | ||
| 302 | ||
| 303 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_pcx_l2t_data_rdy_px2_d1 | |
| 304 | (.dout (pcx_l2t_data_rdy_px2_d1), | |
| 305 | .scan_in(ff_pcx_l2t_data_rdy_px2_d1_scanin), | |
| 306 | .scan_out(ff_pcx_l2t_data_rdy_px2_d1_scanout), | |
| 307 | .din (pcx_l2t_data_rdy_px2), | |
| 308 | .l1clk (l1clk), | |
| 309 | .siclk(siclk), | |
| 310 | .soclk(soclk) | |
| 311 | ||
| 312 | ||
| 313 | ) ; | |
| 314 | ||
| 315 | l2t_iqu_ctl_msff_ctl_macro__dmsff_32x__width_1 ff_pcx_l2t_atm_px2_p | |
| 316 | (.dout (iqu_pcx_l2t_atm_px2_p), | |
| 317 | .scan_in(ff_pcx_l2t_atm_px2_p_scanin), | |
| 318 | .scan_out(ff_pcx_l2t_atm_px2_p_scanout), | |
| 319 | .din (pcx_l2t_atm_px1_fnl), | |
| 320 | .l1clk (l1clk), | |
| 321 | .siclk(siclk), | |
| 322 | .soclk(soclk) | |
| 323 | ||
| 324 | ||
| 325 | ) ; | |
| 326 | ||
| 327 | ||
| 328 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_pcx_l2t_atm_px1_p_fnl | |
| 329 | (.dout (pcx_l2t_atm_px1_fnl), | |
| 330 | .scan_in(ff_pcx_l2t_atm_px1_p_fnl_scanin), | |
| 331 | .scan_out(ff_pcx_l2t_atm_px1_p_fnl_scanout), | |
| 332 | .din (pcx_l2t_atm_px1), | |
| 333 | .l1clk (l1clk), | |
| 334 | .siclk(siclk), | |
| 335 | .soclk(soclk) | |
| 336 | ||
| 337 | ||
| 338 | ) ; | |
| 339 | ||
| 340 | ||
| 341 | ||
| 342 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_arb_iqsel_px2_d1 | |
| 343 | (.dout (arb_iqsel_px2_d1), | |
| 344 | .scan_in(ff_arb_iqsel_px2_d1_scanin), | |
| 345 | .scan_out(ff_arb_iqsel_px2_d1_scanout), | |
| 346 | .din (arb_iqsel_px2), | |
| 347 | .l1clk (l1clk), | |
| 348 | .siclk(siclk), | |
| 349 | .soclk(soclk) | |
| 350 | ||
| 351 | ||
| 352 | ) ; | |
| 353 | ||
| 354 | ||
| 355 | //////////////////////////////////////////////////////////////////////////////// | |
| 356 | // "c1_reg_inst_vld" signal will be used to indicate that there is a valid | |
| 357 | // instructon in the C1 Flop. C1 flop instruction is only valid if the queue is | |
| 358 | // empty and the instruction issued by the pcx is not selected in the same cycle | |
| 359 | // by the arbiter. C1 flop is used to store the instruction for only one cycle | |
| 360 | // in the case queue is empty and instruction issued by pcx is not selected by | |
| 361 | // arbiter in the same cycle. | |
| 362 | //////////////////////////////////////////////////////////////////////////////// | |
| 363 | ||
| 364 | assign set_c1_reg_inst_vld = ((que_cnt_0 | (que_cnt_1 & sel_qcount_minus1)) & | |
| 365 | ~c1_reg_inst_vld & pcx_l2t_data_rdy_px2 & ~arb_iqsel_px2) | | |
| 366 | (((c1_reg_inst_vld) | | |
| 367 | (que_cnt_1 & ~sel_qcount_minus1 & ~sel_qcount_plus1) | | |
| 368 | (que_cnt_2 & sel_qcount_minus1)) & | |
| 369 | pcx_l2t_data_rdy_px2 & arb_iqsel_px2) ; | |
| 370 | ||
| 371 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_pcx_inst_vld_c1 | |
| 372 | (.dout (c1_reg_inst_vld), | |
| 373 | .scan_in(ff_pcx_inst_vld_c1_scanin), | |
| 374 | .scan_out(ff_pcx_inst_vld_c1_scanout), | |
| 375 | .din (set_c1_reg_inst_vld), | |
| 376 | .l1clk (l1clk), | |
| 377 | .siclk(siclk), | |
| 378 | .soclk(soclk) | |
| 379 | ) ; | |
| 380 | ||
| 381 | ||
| 382 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_pcx_inst_vld_c1_1 | |
| 383 | (.dout (c1_reg_inst_vld_cloned), | |
| 384 | .scan_in(ff_pcx_inst_vld_c1_1_scanin), | |
| 385 | .scan_out(ff_pcx_inst_vld_c1_1_scanout), | |
| 386 | .din (set_c1_reg_inst_vld), | |
| 387 | .l1clk (l1clk), | |
| 388 | .siclk(siclk), | |
| 389 | .soclk(soclk) | |
| 390 | ) ; | |
| 391 | ||
| 392 | ||
| 393 | ||
| 394 | ||
| 395 | //////////////////////////////////////////////////////////////////////////////// | |
| 396 | // Pipeline for Write Enable and Write Pointer generation for PH2 write | |
| 397 | // | |
| 398 | //=================================================== | |
| 399 | // PX2 | C1 | | |
| 400 | //=================================================== | |
| 401 | // write into | write into | | |
| 402 | // IQ array | IQ array | | |
| 403 | // | | | |
| 404 | // gen wrt en | gen wrt en | | |
| 405 | // | | | |
| 406 | // gen inc wrt | Mux select new gen inc wrt | | |
| 407 | // ptr signal | wrt pointer ptr signal | | |
| 408 | // | | | |
| 409 | // gen wrt ptr | gen wrt ptr | | |
| 410 | // plus 1 | plus 1 | | |
| 411 | //=================================================== | |
| 412 | //////////////////////////////////////////////////////////////////////////////// | |
| 413 | ||
| 414 | assign inc_wr_ptr_px2 = pcx_l2t_data_rdy_px2 & (~arb_iqsel_px2 | | |
| 415 | ((~que_cnt_0 & ~(que_cnt_1 & sel_qcount_minus1)) | | |
| 416 | c1_reg_inst_vld)) ; | |
| 417 | ||
| 418 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_inc_wr_ptr_c1 | |
| 419 | (.dout (inc_wr_ptr_c1), | |
| 420 | .scan_in(ff_inc_wr_ptr_c1_scanin), | |
| 421 | .scan_out(ff_inc_wr_ptr_c1_scanout), | |
| 422 | .din (inc_wr_ptr_px2), | |
| 423 | .l1clk (l1clk), | |
| 424 | .siclk(siclk), | |
| 425 | .soclk(soclk) | |
| 426 | ||
| 427 | ||
| 428 | ) ; | |
| 429 | ||
| 430 | assign sel_wrptr_plus1 = dbb_rst_l & inc_wr_ptr_c1 ; | |
| 431 | assign sel_wrptr_same = dbb_rst_l & ~inc_wr_ptr_c1 ; | |
| 432 | ||
| 433 | assign wrptr_plus1 = wrptr + 4'b1 ; | |
| 434 | ||
| 435 | l2t_iqu_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_wrptr | |
| 436 | (.dout (wrptr[3:0]), | |
| 437 | .din0 (4'b0), .sel0 (~dbb_rst_l), | |
| 438 | .din1 (wrptr_plus1_d1[3:0]), .sel1 (sel_wrptr_plus1), | |
| 439 | .din2 (wrptr_d1[3:0]), .sel2 (sel_wrptr_same) | |
| 440 | ) ; | |
| 441 | ||
| 442 | ||
| 443 | l2t_iqu_ctl_msff_ctl_macro__width_4 ff_array_wr_ptr_plus1 | |
| 444 | (.dout (wrptr_plus1_d1[3:0]), | |
| 445 | .scan_in(ff_array_wr_ptr_plus1_scanin), | |
| 446 | .scan_out(ff_array_wr_ptr_plus1_scanout), | |
| 447 | .din (wrptr_plus1[3:0]), | |
| 448 | .l1clk (l1clk), | |
| 449 | .siclk(siclk), | |
| 450 | .soclk(soclk) | |
| 451 | ||
| 452 | ||
| 453 | ) ; | |
| 454 | ||
| 455 | l2t_iqu_ctl_msff_ctl_macro__width_4 ff_array_wr_ptr | |
| 456 | (.dout (wrptr_d1[3:0]), | |
| 457 | .scan_in(ff_array_wr_ptr_scanin), | |
| 458 | .scan_out(ff_array_wr_ptr_scanout), | |
| 459 | .din (wrptr[3:0]), | |
| 460 | .l1clk (l1clk), | |
| 461 | .siclk(siclk), | |
| 462 | .soclk(soclk) | |
| 463 | ||
| 464 | ||
| 465 | ) ; | |
| 466 | ||
| 467 | ||
| 468 | ||
| 469 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_l2t_mb2_run_r1 | |
| 470 | (.din(l2t_mb2_run), .l1clk(l1clk), | |
| 471 | .scan_in(ff_l2t_mb2_run_r1_scanin), | |
| 472 | .scan_out(ff_l2t_mb2_run_r1_scanout), | |
| 473 | .dout(l2t_mb2_run_r1), | |
| 474 | .siclk(siclk), | |
| 475 | .soclk(soclk) | |
| 476 | ); | |
| 477 | ||
| 478 | ||
| 479 | assign iqu_iq_array_wr_en = l2t_mb2_run_r1 ? l2t_mb2_iqarray_wr_en : pcx_l2t_data_rdy_px2; | |
| 480 | assign iqu_iq_array_wr_wl = l2t_mb2_run_r1 ? l2t_mb2_addr : wrptr ; | |
| 481 | ||
| 482 | ||
| 483 | //////////////////////////////////////////////////////////////////////////////// | |
| 484 | //================================================== | |
| 485 | // PX2 | C1 | | |
| 486 | //================================================== | |
| 487 | // gen rd en | gen rd en | | |
| 488 | // | | | |
| 489 | // mux slect new | gen rd ptr mux slect new | | |
| 490 | // rd ptr | plus 1 rd ptr | | |
| 491 | //================================================== | |
| 492 | // | |
| 493 | // Generation of Mux select for selecting between Read Pointer and it's | |
| 494 | // Incremented value depends on the 'arb_iqsel_px2' signal. New value of | |
| 495 | // write pointer is selected and transmitted to the IQ array for reading the | |
| 496 | // array. Since 'arb_iqsel_px2' signal arrives late in the cycle this may | |
| 497 | // create timing problem. | |
| 498 | // | |
| 499 | //////////////////////////////////////////////////////////////////////////////// | |
| 500 | ||
| 501 | assign iqu_iq_array_rd_en = l2t_mb2_run_r1 ? l2t_mb2_iqarray_rd_en : iqu_iq_arb_vld_px2_internal ; | |
| 502 | assign iqu_iq_array_rd_wl = l2t_mb2_run_r1 ? l2t_mb2_addr: rdptr ; | |
| 503 | ||
| 504 | assign inc_rd_ptr_px2 = c1_reg_inst_vld | | |
| 505 | (que_cnt_1 & sel_qcount_plus1 & arb_iqsel_px2) | | |
| 506 | (que_cnt_1_plus & ~(que_cnt_2 & sel_qcount_minus1) & | |
| 507 | arb_iqsel_px2 ); | |
| 508 | ||
| 509 | ||
| 510 | assign rdptr_plus1 = rdptr_d1 + 4'b1 ; | |
| 511 | ||
| 512 | l2t_iqu_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_rdptr | |
| 513 | (.dout (rdptr[3:0]), | |
| 514 | .din0 (rdptr_d1[3:0]), .sel0 (~inc_rd_ptr_px2), | |
| 515 | .din1 (rdptr_plus1[3:0]), .sel1 (inc_rd_ptr_px2) | |
| 516 | ) ; | |
| 517 | ||
| 518 | ||
| 519 | l2t_iqu_ctl_msff_ctl_macro__clr_1__width_4 ff_array_rd_ptr // sync reset active low | |
| 520 | (.dout (rdptr_d1[3:0]), | |
| 521 | .scan_in(ff_array_rd_ptr_scanin), | |
| 522 | .scan_out(ff_array_rd_ptr_scanout), | |
| 523 | .din (rdptr[3:0]), | |
| 524 | .l1clk (l1clk), .clr(~dbb_rst_l), | |
| 525 | .siclk(siclk), | |
| 526 | .soclk(soclk) | |
| 527 | ||
| 528 | ||
| 529 | ) ; | |
| 530 | ||
| 531 | ||
| 532 | //////////////////////////////////////////////////////////////////////////////// | |
| 533 | //============================================================================== | |
| 534 | // PX2 | C1 | C2 | |
| 535 | //============================================================================== | |
| 536 | // latch pcx rdy | gen qcount inc, dec or | new Qcount vlue | |
| 537 | // & iqsel signals | same sig. | | |
| 538 | // | | | |
| 539 | // | gen next compare values | new compare values | |
| 540 | // | based on current qcount | | |
| 541 | // | & inc, dec or same signal | | |
| 542 | // | | | |
| 543 | // | latch pcx rdy | gen qcount inc, dec or | |
| 544 | // | & iqsel signals | same sig. | |
| 545 | // | | | |
| 546 | // | | gen next compare values | |
| 547 | // | | based on current qcount | |
| 548 | // | | & inc, dec or same signal | |
| 549 | // | | | |
| 550 | // | | latch pcx rdy | |
| 551 | // | | & iqsel signals | |
| 552 | //////////////////////////////////////////////////////////////////////////////// | |
| 553 | ||
| 554 | assign sel_qcount_plus1 = pcx_l2t_data_rdy_px2_d1 & ~arb_iqsel_px2_d1 ; | |
| 555 | assign sel_qcount_minus1 = ~pcx_l2t_data_rdy_px2_d1 & arb_iqsel_px2_d1 ; | |
| 556 | assign sel_qcount_same = ~(sel_qcount_plus1 | sel_qcount_minus1) ; | |
| 557 | ||
| 558 | assign que_cnt_plus1 = que_cnt + 5'b1 ; | |
| 559 | assign que_cnt_minus1 = que_cnt - 5'b1 ; | |
| 560 | ||
| 561 | l2t_iqu_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_5 mux_que_cnt | |
| 562 | (.dout (next_que_cnt[4:0]), | |
| 563 | .din0 (que_cnt_plus1[4:0]), .sel0 (sel_qcount_plus1), | |
| 564 | .din1 (que_cnt_minus1[4:0]), .sel1 (sel_qcount_minus1), | |
| 565 | .din2 (que_cnt[4:0]), .sel2 (sel_qcount_same) | |
| 566 | ) ; | |
| 567 | l2t_iqu_ctl_msff_ctl_macro__clr_1__width_5 ff_que_cnt // sync reset active low | |
| 568 | (.dout (que_cnt[4:0]), | |
| 569 | .scan_in(ff_que_cnt_scanin), | |
| 570 | .scan_out(ff_que_cnt_scanout), | |
| 571 | .din (next_que_cnt[4:0]), | |
| 572 | .l1clk (l1clk), .clr(~dbb_rst_l), | |
| 573 | .siclk(siclk), | |
| 574 | .soclk(soclk) | |
| 575 | ||
| 576 | ||
| 577 | ) ; | |
| 578 | ||
| 579 | ||
| 580 | ||
| 581 | assign que_cnt_0_p = ~(|que_cnt[4:0]) ; | |
| 582 | assign que_cnt_1_p = (~que_cnt_1_plus & que_cnt[0]) ; | |
| 583 | assign que_cnt_1_plus_p = |(que_cnt[4:1]) ; | |
| 584 | assign que_cnt_2_p = ~(|que_cnt[4:2] | que_cnt[0]) & que_cnt[1] ; | |
| 585 | assign que_cnt_2_plus_p = (|que_cnt[4:2]) | (&que_cnt[1:0]) ; | |
| 586 | assign que_cnt_3_p = ~(|que_cnt[4:2]) & (&que_cnt[1:0]) ; | |
| 587 | ||
| 588 | assign que_cnt_9_p = (que_cnt == 5'd9) ; | |
| 589 | assign que_cnt_10_p = (que_cnt == 5'd10) ; | |
| 590 | assign que_cnt_10_plus_p = (que_cnt > 5'd10) ; | |
| 591 | ||
| 592 | ||
| 593 | ||
| 594 | assign que_cnt_11_p = (que_cnt == 5'd11) ; | |
| 595 | //assign que_cnt_11_plus_p = (que_cnt > 5'd11) ; | |
| 596 | //assign que_cnt_12_p = (que_cnt == 5'd12) ; | |
| 597 | //assign que_cnt_12_plus_p = (que_cnt > 5'd12) ; | |
| 598 | //assign que_cnt_13_p = (que_cnt == 5'd13) ; | |
| 599 | //assign que_cnt_13_plus_p = (que_cnt > 5'd13) ; | |
| 600 | ||
| 601 | ||
| 602 | assign que_cnt_0_n = (que_cnt_0_p & sel_qcount_same) | | |
| 603 | (que_cnt_1_p & sel_qcount_minus1) ; | |
| 604 | assign que_cnt_1_n = (que_cnt_1_p & sel_qcount_same) | | |
| 605 | (que_cnt_0_p & sel_qcount_plus1) | | |
| 606 | (que_cnt_2_p & sel_qcount_minus1) ; | |
| 607 | assign que_cnt_1_plus_n = (que_cnt_1_plus_p & (sel_qcount_same | sel_qcount_plus1)) | | |
| 608 | (que_cnt_1_p & sel_qcount_plus1) | | |
| 609 | (que_cnt_2_plus_p & sel_qcount_minus1) ; | |
| 610 | assign que_cnt_2_n = (que_cnt_2_p & sel_qcount_same) | | |
| 611 | (que_cnt_1_p & sel_qcount_plus1) | | |
| 612 | (que_cnt_3_p & sel_qcount_minus1) ; | |
| 613 | ||
| 614 | //assign que_cnt_12_n = (que_cnt_12_p & sel_qcount_same) | | |
| 615 | // (que_cnt_11_p & sel_qcount_plus1) | | |
| 616 | // (que_cnt_13_p & sel_qcount_minus1) ; | |
| 617 | //assign que_cnt_12_plus_n = (que_cnt_12_plus_p & (sel_qcount_same | sel_qcount_plus1)) | | |
| 618 | // (que_cnt_12_p & sel_qcount_plus1) | | |
| 619 | // (que_cnt_13_plus_p & sel_qcount_minus1) ; | |
| 620 | // | |
| 621 | // | |
| 622 | //assign que_cnt_11_n = (que_cnt_11_p & sel_qcount_same) | | |
| 623 | // (que_cnt_10_p & sel_qcount_plus1) | | |
| 624 | // (que_cnt_12_p & sel_qcount_minus1) ; | |
| 625 | //assign que_cnt_11_plus_n = (que_cnt_11_plus_p & (sel_qcount_same | sel_qcount_plus1)) | | |
| 626 | // (que_cnt_11_p & sel_qcount_plus1) | | |
| 627 | // (que_cnt_12_plus_p & sel_qcount_minus1) ; | |
| 628 | // | |
| 629 | ||
| 630 | assign que_cnt_10_n = (que_cnt_10_p & sel_qcount_same) | | |
| 631 | (que_cnt_9_p & sel_qcount_plus1) | | |
| 632 | (que_cnt_11_p & sel_qcount_minus1) ; | |
| 633 | ||
| 634 | assign que_cnt_10_plus_n = (que_cnt_10_plus_p & (sel_qcount_same | sel_qcount_plus1)) | | |
| 635 | (que_cnt_10_p & sel_qcount_plus1) | | |
| 636 | (que_cnt_10_plus_p & sel_qcount_minus1) ; | |
| 637 | ||
| 638 | ||
| 639 | ||
| 640 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_que_cnt_0 | |
| 641 | (.dout (que_cnt_0), | |
| 642 | .scan_in(ff_que_cnt_0_scanin), | |
| 643 | .scan_out(ff_que_cnt_0_scanout), | |
| 644 | .din (que_cnt_0_n), | |
| 645 | .l1clk (l1clk), | |
| 646 | .siclk(siclk), | |
| 647 | .soclk(soclk) | |
| 648 | ||
| 649 | ||
| 650 | ) ; | |
| 651 | ||
| 652 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_que_cnt_1 | |
| 653 | (.dout (que_cnt_1), | |
| 654 | .scan_in(ff_que_cnt_1_scanin), | |
| 655 | .scan_out(ff_que_cnt_1_scanout), | |
| 656 | .din (que_cnt_1_n), | |
| 657 | .l1clk (l1clk), | |
| 658 | .siclk(siclk), | |
| 659 | .soclk(soclk) | |
| 660 | ||
| 661 | ||
| 662 | ) ; | |
| 663 | ||
| 664 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_que_cnt_1_plus | |
| 665 | (.dout (que_cnt_1_plus), | |
| 666 | .scan_in(ff_que_cnt_1_plus_scanin), | |
| 667 | .scan_out(ff_que_cnt_1_plus_scanout), | |
| 668 | .din (que_cnt_1_plus_n), | |
| 669 | .l1clk (l1clk), | |
| 670 | .siclk(siclk), | |
| 671 | .soclk(soclk) | |
| 672 | ||
| 673 | ||
| 674 | ) ; | |
| 675 | ||
| 676 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_que_cnt_2 | |
| 677 | (.dout (que_cnt_2), | |
| 678 | .scan_in(ff_que_cnt_2_scanin), | |
| 679 | .scan_out(ff_que_cnt_2_scanout), | |
| 680 | .din (que_cnt_2_n), | |
| 681 | .l1clk (l1clk), | |
| 682 | .siclk(siclk), | |
| 683 | .soclk(soclk) | |
| 684 | ||
| 685 | ||
| 686 | ) ; | |
| 687 | ||
| 688 | //msff_ctl_macro ff_que_cnt_12 (width=1) | |
| 689 | // (.dout (que_cnt_11), | |
| 690 | // .scan_in(ff_que_cnt_12_scanin), | |
| 691 | // .scan_out(ff_que_cnt_12_scanout), | |
| 692 | // .din (que_cnt_11_n), | |
| 693 | // .l1clk (l1clk), | |
| 694 | // | |
| 695 | // | |
| 696 | // ) ; | |
| 697 | // | |
| 698 | //msff_ctl_macro ff_que_cnt_12_plus (width=1) | |
| 699 | // (.dout (que_cnt_11_plus), | |
| 700 | // .scan_in(ff_que_cnt_12_plus_scanin), | |
| 701 | // .scan_out(ff_que_cnt_12_plus_scanout), | |
| 702 | // .din (que_cnt_11_plus_n), | |
| 703 | // .l1clk (l1clk), | |
| 704 | // | |
| 705 | // | |
| 706 | // ) ; | |
| 707 | // | |
| 708 | ||
| 709 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_que_cnt_10 | |
| 710 | (.dout (que_cnt_10), | |
| 711 | .scan_in(ff_que_cnt_10_scanin), | |
| 712 | .scan_out(ff_que_cnt_10_scanout), | |
| 713 | .din (que_cnt_10_n), | |
| 714 | .l1clk (l1clk), | |
| 715 | .siclk(siclk), | |
| 716 | .soclk(soclk) | |
| 717 | ||
| 718 | ||
| 719 | ) ; | |
| 720 | ||
| 721 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_que_cnt_10_plus | |
| 722 | (.dout (que_cnt_10_plus), | |
| 723 | .scan_in(ff_que_cnt_10_plus_scanin), | |
| 724 | .scan_out(ff_que_cnt_10_plus_scanout), | |
| 725 | .din (que_cnt_10_plus_n), | |
| 726 | .l1clk (l1clk), | |
| 727 | .siclk(siclk), | |
| 728 | .soclk(soclk) | |
| 729 | ||
| 730 | ||
| 731 | ) ; | |
| 732 | ||
| 733 | ||
| 734 | //////////////////////////////////////////////////////////////////////////////// | |
| 735 | ||
| 736 | assign iqu_sel_c1reg_over_iqarray = (wrptr_d1 == rdptr_d1); | |
| 737 | ||
| 738 | ||
| 739 | //////////////////////////////////////////////////////////////////////////////// | |
| 740 | // MUX sel generation for IQ dp. | |
| 741 | //////////////////////////////////////////////////////////////////////////////// | |
| 742 | ||
| 743 | //assign iqu_sel_iq = ~c1_reg_inst_vld & | |
| 744 | // (que_cnt_1_plus | (que_cnt_1 & ~arb_iqsel_px2_d1)) ; | |
| 745 | assign set_iqu_sel_iq = ~set_c1_reg_inst_vld & | |
| 746 | (que_cnt_1_plus_n | (que_cnt_1_n & ~arb_iqsel_px2)) ; | |
| 747 | l2t_iqu_ctl_msff_ctl_macro__width_1 ff_iqu_sel_iq | |
| 748 | (.dout (iqu_sel_iq), | |
| 749 | .scan_in(ff_iqu_sel_iq_scanin), | |
| 750 | .scan_out(ff_iqu_sel_iq_scanout), | |
| 751 | .din (set_iqu_sel_iq), | |
| 752 | .l1clk (l1clk), | |
| 753 | .siclk(siclk), | |
| 754 | .soclk(soclk) | |
| 755 | ||
| 756 | ||
| 757 | ) ; | |
| 758 | ||
| 759 | ||
| 760 | //assign iqu_sel_c1 = c1_reg_inst_vld ; | |
| 761 | l2t_iqu_ctl_msff_ctl_macro__dmsff_32x__width_1 ff_iqu_sel_c1 | |
| 762 | (.dout (iqu_sel_c1), | |
| 763 | .scan_in(ff_iqu_sel_c1_scanin), | |
| 764 | .scan_out(ff_iqu_sel_c1_scanout), | |
| 765 | .din (set_c1_reg_inst_vld), | |
| 766 | .l1clk (l1clk), | |
| 767 | .siclk(siclk), | |
| 768 | .soclk(soclk) | |
| 769 | ) ; | |
| 770 | ||
| 771 | ||
| 772 | //assign iqu_sel_pcx = ~iqu_sel_iq & ~iqu_sel_c1 ; | |
| 773 | assign set_iqu_sel_pcx = ~set_iqu_sel_iq & ~set_c1_reg_inst_vld ; | |
| 774 | ||
| 775 | l2t_iqu_ctl_msff_ctl_macro__dmsff_32x__width_1 ff_iqu_sel_pcx | |
| 776 | (.dout (iqu_sel_pcx), | |
| 777 | .scan_in(ff_iqu_sel_pcx_scanin), | |
| 778 | .scan_out(ff_iqu_sel_pcx_scanout), | |
| 779 | .din (set_iqu_sel_pcx), | |
| 780 | .l1clk (l1clk), | |
| 781 | .siclk(siclk), | |
| 782 | .soclk(soclk) | |
| 783 | ) ; | |
| 784 | ||
| 785 | l2t_iqu_ctl_msff_ctl_macro__dmsff_32x__width_1 ff_iqu_sel_iq_d1 | |
| 786 | (.dout (iqu_sel_iq_d1), | |
| 787 | .scan_in(ff_iqu_sel_iq_d1_scanin), | |
| 788 | .scan_out(ff_iqu_sel_iq_d1_scanout), | |
| 789 | .din (iqu_sel_iq), | |
| 790 | .l1clk (l1clk), | |
| 791 | .siclk(siclk), | |
| 792 | .soclk(soclk) | |
| 793 | ) ; | |
| 794 | ||
| 795 | //assign iqu_sel_iq_fe = iqu_sel_iq_d1 & ~iqu_sel_iq ; | |
| 796 | //assign iqu_hold_rd = iqu_sel_iq & ~arb_iqsel_px2 & ~iqu_sel_iq_fe ; | |
| 797 | //assign iqu_hold_rd_n = ~iqu_hold_rd; | |
| 798 | ||
| 799 | cl_u1_inv_16x inv_iqu_sel_iq | |
| 800 | ( | |
| 801 | .in (iqu_sel_iq), | |
| 802 | .out (iqu_sel_iq_n) | |
| 803 | ); | |
| 804 | ||
| 805 | cl_u1_inv_16x inv_arb_iqsel_px2 | |
| 806 | ( | |
| 807 | .in (arb_iqsel_px2_v1), | |
| 808 | .out (arb_iqsel_px2_v1_n) | |
| 809 | ); | |
| 810 | ||
| 811 | ||
| 812 | cl_u1_nand2_16x nand_iqu_sel_iq_fe | |
| 813 | ( | |
| 814 | .in0 (iqu_sel_iq_d1), | |
| 815 | .in1 (iqu_sel_iq_n), | |
| 816 | .out (iqu_sel_iq_fe_n) | |
| 817 | ); | |
| 818 | ||
| 819 | cl_u1_nand3_16x nand_iqu_hold_rd_n | |
| 820 | ( | |
| 821 | .in0 (iqu_sel_iq_fe_n), | |
| 822 | .in1 (arb_iqsel_px2_v1_n), | |
| 823 | .in2 (iqu_sel_iq), | |
| 824 | .out (iqu_hold_rd_n) | |
| 825 | ); | |
| 826 | ||
| 827 | //////////////////////////////////////////////////////////////////////////////// | |
| 828 | // IQ COUNT | |
| 829 | // | |
| 830 | // MUX here | |
| 831 | // PQ PA PX1 PX2 C1 C2(counter update for pckt in PX2) | |
| 832 | // PQ PA PX1 PX2 C1 C2 | |
| 833 | // PQ PA PX1 PX2 C1 C2 | |
| 834 | // PQ PA PX1 PX2 C1 | |
| 835 | // PQ PA PX1 PX2 C1 C2 | |
| 836 | // PQ PA PX1 PX2 C1 | |
| 837 | // | |
| 838 | // When the stall is signalled, there can potentially be 5 packets in C1, | |
| 839 | // PX2, Px1, PA and PQ that need to be queued in the IQ. The packet in PQ may | |
| 840 | // be an atomic hence, the high water mark is 11. | |
| 841 | //////////////////////////////////////////////////////////////////////////////// | |
| 842 | ||
| 843 | //assign l2t_pcx_stall_pq = que_cnt_12_plus | | |
| 844 | // (que_cnt_12 & (pcx_l2t_data_rdy_px2_d1 & | |
| 845 | // ~arb_iqsel_px2_d1)) ; | |
| 846 | ||
| 847 | // assign l2t_pcx_stall_pq = que_cnt_11_plus | | |
| 848 | // (que_cnt_11 & (pcx_l2t_data_rdy_px2_d1 & ~arb_iqsel_px2_d1)) ; | |
| 849 | ||
| 850 | assign l2t_pcx_stall_pq = que_cnt_10_plus | | |
| 851 | (que_cnt_10 & (pcx_l2t_data_rdy_px2_d1 & ~arb_iqsel_px2_d1)) ; | |
| 852 | ||
| 853 | ||
| 854 | assign iqu_iq_arb_vld_px2_internal = (pcx_l2t_data_rdy_px2 | c1_reg_inst_vld | | |
| 855 | (que_cnt_1_plus | (que_cnt_1 & ~sel_qcount_minus1))) ; | |
| 856 | ||
| 857 | assign iqu_iq_arb_vld_px2 = (pcx_l2t_data_rdy_px2_for_ext | c1_reg_inst_vld_cloned | | |
| 858 | (que_cnt_1_plus | (que_cnt_1 & ~sel_qcount_minus1))) ; | |
| 859 | ||
| 860 | assign iqu_iq_arb_vld_px2_v1 = (pcx_l2t_data_rdy_px2_for_ext | c1_reg_inst_vld_cloned | | |
| 861 | (que_cnt_1_plus | (que_cnt_1 & ~sel_qcount_minus1))) ; | |
| 862 | ||
| 863 | // fixscan start: | |
| 864 | assign reset_flop_scanin = scan_in ; | |
| 865 | assign spares_scanin = reset_flop_scanout ; | |
| 866 | assign ff_pcx_l2t_data_rdy_px1_fnl_scanin = spares_scanout ; | |
| 867 | assign ff_pcx_l2t_data_rdy_px2_scanin = ff_pcx_l2t_data_rdy_px1_fnl_scanout; | |
| 868 | assign ff_pcx_l2t_data_rdy_px2_1_scanin = ff_pcx_l2t_data_rdy_px2_scanout; | |
| 869 | assign ff_pcx_l2t_data_rdy_px2_d1_scanin = ff_pcx_l2t_data_rdy_px2_1_scanout; | |
| 870 | assign ff_pcx_l2t_atm_px2_p_scanin = ff_pcx_l2t_data_rdy_px2_d1_scanout; | |
| 871 | assign ff_pcx_l2t_atm_px1_p_fnl_scanin = ff_pcx_l2t_atm_px2_p_scanout; | |
| 872 | assign ff_arb_iqsel_px2_d1_scanin = ff_pcx_l2t_atm_px1_p_fnl_scanout; | |
| 873 | assign ff_pcx_inst_vld_c1_scanin = ff_arb_iqsel_px2_d1_scanout; | |
| 874 | assign ff_pcx_inst_vld_c1_1_scanin = ff_pcx_inst_vld_c1_scanout; | |
| 875 | assign ff_inc_wr_ptr_c1_scanin = ff_pcx_inst_vld_c1_1_scanout; | |
| 876 | assign ff_array_wr_ptr_plus1_scanin = ff_inc_wr_ptr_c1_scanout ; | |
| 877 | assign ff_array_wr_ptr_scanin = ff_array_wr_ptr_plus1_scanout; | |
| 878 | assign ff_l2t_mb2_run_r1_scanin = ff_array_wr_ptr_scanout ; | |
| 879 | assign ff_array_rd_ptr_scanin = ff_l2t_mb2_run_r1_scanout; | |
| 880 | assign ff_que_cnt_scanin = ff_array_rd_ptr_scanout ; | |
| 881 | assign ff_que_cnt_0_scanin = ff_que_cnt_scanout ; | |
| 882 | assign ff_que_cnt_1_scanin = ff_que_cnt_0_scanout ; | |
| 883 | assign ff_que_cnt_1_plus_scanin = ff_que_cnt_1_scanout ; | |
| 884 | assign ff_que_cnt_2_scanin = ff_que_cnt_1_plus_scanout; | |
| 885 | assign ff_que_cnt_10_scanin = ff_que_cnt_2_scanout ; | |
| 886 | assign ff_que_cnt_10_plus_scanin = ff_que_cnt_10_scanout ; | |
| 887 | assign ff_iqu_sel_iq_scanin = ff_que_cnt_10_plus_scanout; | |
| 888 | assign ff_iqu_sel_c1_scanin = ff_iqu_sel_iq_scanout ; | |
| 889 | assign ff_iqu_sel_pcx_scanin = ff_iqu_sel_c1_scanout ; | |
| 890 | assign ff_iqu_sel_iq_d1_scanin = ff_iqu_sel_pcx_scanout ; | |
| 891 | assign scan_out = ff_iqu_sel_iq_d1_scanout ; | |
| 892 | // fixscan end: | |
| 893 | endmodule | |
| 894 | ||
| 895 | ||
| 896 | ||
| 897 | ||
| 898 | ||
| 899 | ||
| 900 | // any PARAMS parms go into naming of macro | |
| 901 | ||
| 902 | module l2t_iqu_ctl_msff_ctl_macro__width_1 ( | |
| 903 | din, | |
| 904 | l1clk, | |
| 905 | scan_in, | |
| 906 | siclk, | |
| 907 | soclk, | |
| 908 | dout, | |
| 909 | scan_out); | |
| 910 | wire [0:0] fdin; | |
| 911 | ||
| 912 | input [0:0] din; | |
| 913 | input l1clk; | |
| 914 | input scan_in; | |
| 915 | ||
| 916 | ||
| 917 | input siclk; | |
| 918 | input soclk; | |
| 919 | ||
| 920 | output [0:0] dout; | |
| 921 | output scan_out; | |
| 922 | assign fdin[0:0] = din[0:0]; | |
| 923 | ||
| 924 | ||
| 925 | ||
| 926 | ||
| 927 | ||
| 928 | ||
| 929 | dff #(1) d0_0 ( | |
| 930 | .l1clk(l1clk), | |
| 931 | .siclk(siclk), | |
| 932 | .soclk(soclk), | |
| 933 | .d(fdin[0:0]), | |
| 934 | .si(scan_in), | |
| 935 | .so(scan_out), | |
| 936 | .q(dout[0:0]) | |
| 937 | ); | |
| 938 | ||
| 939 | ||
| 940 | ||
| 941 | ||
| 942 | ||
| 943 | ||
| 944 | ||
| 945 | ||
| 946 | ||
| 947 | ||
| 948 | ||
| 949 | ||
| 950 | endmodule | |
| 951 | ||
| 952 | ||
| 953 | ||
| 954 | ||
| 955 | ||
| 956 | ||
| 957 | ||
| 958 | ||
| 959 | ||
| 960 | ||
| 961 | ||
| 962 | ||
| 963 | ||
| 964 | // any PARAMS parms go into naming of macro | |
| 965 | ||
| 966 | module l2t_iqu_ctl_l1clkhdr_ctl_macro ( | |
| 967 | l2clk, | |
| 968 | l1en, | |
| 969 | pce_ov, | |
| 970 | stop, | |
| 971 | se, | |
| 972 | l1clk); | |
| 973 | ||
| 974 | ||
| 975 | input l2clk; | |
| 976 | input l1en; | |
| 977 | input pce_ov; | |
| 978 | input stop; | |
| 979 | input se; | |
| 980 | output l1clk; | |
| 981 | ||
| 982 | ||
| 983 | ||
| 984 | ||
| 985 | ||
| 986 | cl_sc1_l1hdr_8x c_0 ( | |
| 987 | ||
| 988 | ||
| 989 | .l2clk(l2clk), | |
| 990 | .pce(l1en), | |
| 991 | .l1clk(l1clk), | |
| 992 | .se(se), | |
| 993 | .pce_ov(pce_ov), | |
| 994 | .stop(stop) | |
| 995 | ); | |
| 996 | ||
| 997 | ||
| 998 | ||
| 999 | endmodule | |
| 1000 | ||
| 1001 | ||
| 1002 | ||
| 1003 | ||
| 1004 | ||
| 1005 | ||
| 1006 | ||
| 1007 | ||
| 1008 | ||
| 1009 | // Description: Spare gate macro for control blocks | |
| 1010 | // | |
| 1011 | // Param num controls the number of times the macro is added | |
| 1012 | // flops=0 can be used to use only combination spare logic | |
| 1013 | ||
| 1014 | ||
| 1015 | module l2t_iqu_ctl_spare_ctl_macro__num_4 ( | |
| 1016 | l1clk, | |
| 1017 | scan_in, | |
| 1018 | siclk, | |
| 1019 | soclk, | |
| 1020 | scan_out); | |
| 1021 | wire si_0; | |
| 1022 | wire so_0; | |
| 1023 | wire spare0_flop_unused; | |
| 1024 | wire spare0_buf_32x_unused; | |
| 1025 | wire spare0_nand3_8x_unused; | |
| 1026 | wire spare0_inv_8x_unused; | |
| 1027 | wire spare0_aoi22_4x_unused; | |
| 1028 | wire spare0_buf_8x_unused; | |
| 1029 | wire spare0_oai22_4x_unused; | |
| 1030 | wire spare0_inv_16x_unused; | |
| 1031 | wire spare0_nand2_16x_unused; | |
| 1032 | wire spare0_nor3_4x_unused; | |
| 1033 | wire spare0_nand2_8x_unused; | |
| 1034 | wire spare0_buf_16x_unused; | |
| 1035 | wire spare0_nor2_16x_unused; | |
| 1036 | wire spare0_inv_32x_unused; | |
| 1037 | wire si_1; | |
| 1038 | wire so_1; | |
| 1039 | wire spare1_flop_unused; | |
| 1040 | wire spare1_buf_32x_unused; | |
| 1041 | wire spare1_nand3_8x_unused; | |
| 1042 | wire spare1_inv_8x_unused; | |
| 1043 | wire spare1_aoi22_4x_unused; | |
| 1044 | wire spare1_buf_8x_unused; | |
| 1045 | wire spare1_oai22_4x_unused; | |
| 1046 | wire spare1_inv_16x_unused; | |
| 1047 | wire spare1_nand2_16x_unused; | |
| 1048 | wire spare1_nor3_4x_unused; | |
| 1049 | wire spare1_nand2_8x_unused; | |
| 1050 | wire spare1_buf_16x_unused; | |
| 1051 | wire spare1_nor2_16x_unused; | |
| 1052 | wire spare1_inv_32x_unused; | |
| 1053 | wire si_2; | |
| 1054 | wire so_2; | |
| 1055 | wire spare2_flop_unused; | |
| 1056 | wire spare2_buf_32x_unused; | |
| 1057 | wire spare2_nand3_8x_unused; | |
| 1058 | wire spare2_inv_8x_unused; | |
| 1059 | wire spare2_aoi22_4x_unused; | |
| 1060 | wire spare2_buf_8x_unused; | |
| 1061 | wire spare2_oai22_4x_unused; | |
| 1062 | wire spare2_inv_16x_unused; | |
| 1063 | wire spare2_nand2_16x_unused; | |
| 1064 | wire spare2_nor3_4x_unused; | |
| 1065 | wire spare2_nand2_8x_unused; | |
| 1066 | wire spare2_buf_16x_unused; | |
| 1067 | wire spare2_nor2_16x_unused; | |
| 1068 | wire spare2_inv_32x_unused; | |
| 1069 | wire si_3; | |
| 1070 | wire so_3; | |
| 1071 | wire spare3_flop_unused; | |
| 1072 | wire spare3_buf_32x_unused; | |
| 1073 | wire spare3_nand3_8x_unused; | |
| 1074 | wire spare3_inv_8x_unused; | |
| 1075 | wire spare3_aoi22_4x_unused; | |
| 1076 | wire spare3_buf_8x_unused; | |
| 1077 | wire spare3_oai22_4x_unused; | |
| 1078 | wire spare3_inv_16x_unused; | |
| 1079 | wire spare3_nand2_16x_unused; | |
| 1080 | wire spare3_nor3_4x_unused; | |
| 1081 | wire spare3_nand2_8x_unused; | |
| 1082 | wire spare3_buf_16x_unused; | |
| 1083 | wire spare3_nor2_16x_unused; | |
| 1084 | wire spare3_inv_32x_unused; | |
| 1085 | ||
| 1086 | ||
| 1087 | input l1clk; | |
| 1088 | input scan_in; | |
| 1089 | input siclk; | |
| 1090 | input soclk; | |
| 1091 | output scan_out; | |
| 1092 | ||
| 1093 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
| 1094 | .siclk(siclk), | |
| 1095 | .soclk(soclk), | |
| 1096 | .si(si_0), | |
| 1097 | .so(so_0), | |
| 1098 | .d(1'b0), | |
| 1099 | .q(spare0_flop_unused)); | |
| 1100 | assign si_0 = scan_in; | |
| 1101 | ||
| 1102 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
| 1103 | .out(spare0_buf_32x_unused)); | |
| 1104 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
| 1105 | .in1(1'b1), | |
| 1106 | .in2(1'b1), | |
| 1107 | .out(spare0_nand3_8x_unused)); | |
| 1108 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
| 1109 | .out(spare0_inv_8x_unused)); | |
| 1110 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
| 1111 | .in01(1'b1), | |
| 1112 | .in10(1'b1), | |
| 1113 | .in11(1'b1), | |
| 1114 | .out(spare0_aoi22_4x_unused)); | |
| 1115 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
| 1116 | .out(spare0_buf_8x_unused)); | |
| 1117 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
| 1118 | .in01(1'b1), | |
| 1119 | .in10(1'b1), | |
| 1120 | .in11(1'b1), | |
| 1121 | .out(spare0_oai22_4x_unused)); | |
| 1122 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
| 1123 | .out(spare0_inv_16x_unused)); | |
| 1124 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
| 1125 | .in1(1'b1), | |
| 1126 | .out(spare0_nand2_16x_unused)); | |
| 1127 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
| 1128 | .in1(1'b0), | |
| 1129 | .in2(1'b0), | |
| 1130 | .out(spare0_nor3_4x_unused)); | |
| 1131 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
| 1132 | .in1(1'b1), | |
| 1133 | .out(spare0_nand2_8x_unused)); | |
| 1134 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
| 1135 | .out(spare0_buf_16x_unused)); | |
| 1136 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
| 1137 | .in1(1'b0), | |
| 1138 | .out(spare0_nor2_16x_unused)); | |
| 1139 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
| 1140 | .out(spare0_inv_32x_unused)); | |
| 1141 | ||
| 1142 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
| 1143 | .siclk(siclk), | |
| 1144 | .soclk(soclk), | |
| 1145 | .si(si_1), | |
| 1146 | .so(so_1), | |
| 1147 | .d(1'b0), | |
| 1148 | .q(spare1_flop_unused)); | |
| 1149 | assign si_1 = so_0; | |
| 1150 | ||
| 1151 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
| 1152 | .out(spare1_buf_32x_unused)); | |
| 1153 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
| 1154 | .in1(1'b1), | |
| 1155 | .in2(1'b1), | |
| 1156 | .out(spare1_nand3_8x_unused)); | |
| 1157 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
| 1158 | .out(spare1_inv_8x_unused)); | |
| 1159 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
| 1160 | .in01(1'b1), | |
| 1161 | .in10(1'b1), | |
| 1162 | .in11(1'b1), | |
| 1163 | .out(spare1_aoi22_4x_unused)); | |
| 1164 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
| 1165 | .out(spare1_buf_8x_unused)); | |
| 1166 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
| 1167 | .in01(1'b1), | |
| 1168 | .in10(1'b1), | |
| 1169 | .in11(1'b1), | |
| 1170 | .out(spare1_oai22_4x_unused)); | |
| 1171 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
| 1172 | .out(spare1_inv_16x_unused)); | |
| 1173 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
| 1174 | .in1(1'b1), | |
| 1175 | .out(spare1_nand2_16x_unused)); | |
| 1176 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
| 1177 | .in1(1'b0), | |
| 1178 | .in2(1'b0), | |
| 1179 | .out(spare1_nor3_4x_unused)); | |
| 1180 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
| 1181 | .in1(1'b1), | |
| 1182 | .out(spare1_nand2_8x_unused)); | |
| 1183 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
| 1184 | .out(spare1_buf_16x_unused)); | |
| 1185 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
| 1186 | .in1(1'b0), | |
| 1187 | .out(spare1_nor2_16x_unused)); | |
| 1188 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
| 1189 | .out(spare1_inv_32x_unused)); | |
| 1190 | ||
| 1191 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
| 1192 | .siclk(siclk), | |
| 1193 | .soclk(soclk), | |
| 1194 | .si(si_2), | |
| 1195 | .so(so_2), | |
| 1196 | .d(1'b0), | |
| 1197 | .q(spare2_flop_unused)); | |
| 1198 | assign si_2 = so_1; | |
| 1199 | ||
| 1200 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
| 1201 | .out(spare2_buf_32x_unused)); | |
| 1202 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
| 1203 | .in1(1'b1), | |
| 1204 | .in2(1'b1), | |
| 1205 | .out(spare2_nand3_8x_unused)); | |
| 1206 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
| 1207 | .out(spare2_inv_8x_unused)); | |
| 1208 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
| 1209 | .in01(1'b1), | |
| 1210 | .in10(1'b1), | |
| 1211 | .in11(1'b1), | |
| 1212 | .out(spare2_aoi22_4x_unused)); | |
| 1213 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
| 1214 | .out(spare2_buf_8x_unused)); | |
| 1215 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
| 1216 | .in01(1'b1), | |
| 1217 | .in10(1'b1), | |
| 1218 | .in11(1'b1), | |
| 1219 | .out(spare2_oai22_4x_unused)); | |
| 1220 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
| 1221 | .out(spare2_inv_16x_unused)); | |
| 1222 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
| 1223 | .in1(1'b1), | |
| 1224 | .out(spare2_nand2_16x_unused)); | |
| 1225 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
| 1226 | .in1(1'b0), | |
| 1227 | .in2(1'b0), | |
| 1228 | .out(spare2_nor3_4x_unused)); | |
| 1229 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
| 1230 | .in1(1'b1), | |
| 1231 | .out(spare2_nand2_8x_unused)); | |
| 1232 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
| 1233 | .out(spare2_buf_16x_unused)); | |
| 1234 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
| 1235 | .in1(1'b0), | |
| 1236 | .out(spare2_nor2_16x_unused)); | |
| 1237 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
| 1238 | .out(spare2_inv_32x_unused)); | |
| 1239 | ||
| 1240 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
| 1241 | .siclk(siclk), | |
| 1242 | .soclk(soclk), | |
| 1243 | .si(si_3), | |
| 1244 | .so(so_3), | |
| 1245 | .d(1'b0), | |
| 1246 | .q(spare3_flop_unused)); | |
| 1247 | assign si_3 = so_2; | |
| 1248 | ||
| 1249 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
| 1250 | .out(spare3_buf_32x_unused)); | |
| 1251 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
| 1252 | .in1(1'b1), | |
| 1253 | .in2(1'b1), | |
| 1254 | .out(spare3_nand3_8x_unused)); | |
| 1255 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
| 1256 | .out(spare3_inv_8x_unused)); | |
| 1257 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
| 1258 | .in01(1'b1), | |
| 1259 | .in10(1'b1), | |
| 1260 | .in11(1'b1), | |
| 1261 | .out(spare3_aoi22_4x_unused)); | |
| 1262 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
| 1263 | .out(spare3_buf_8x_unused)); | |
| 1264 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
| 1265 | .in01(1'b1), | |
| 1266 | .in10(1'b1), | |
| 1267 | .in11(1'b1), | |
| 1268 | .out(spare3_oai22_4x_unused)); | |
| 1269 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
| 1270 | .out(spare3_inv_16x_unused)); | |
| 1271 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
| 1272 | .in1(1'b1), | |
| 1273 | .out(spare3_nand2_16x_unused)); | |
| 1274 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
| 1275 | .in1(1'b0), | |
| 1276 | .in2(1'b0), | |
| 1277 | .out(spare3_nor3_4x_unused)); | |
| 1278 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
| 1279 | .in1(1'b1), | |
| 1280 | .out(spare3_nand2_8x_unused)); | |
| 1281 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
| 1282 | .out(spare3_buf_16x_unused)); | |
| 1283 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
| 1284 | .in1(1'b0), | |
| 1285 | .out(spare3_nor2_16x_unused)); | |
| 1286 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
| 1287 | .out(spare3_inv_32x_unused)); | |
| 1288 | assign scan_out = so_3; | |
| 1289 | ||
| 1290 | ||
| 1291 | ||
| 1292 | endmodule | |
| 1293 | ||
| 1294 | ||
| 1295 | ||
| 1296 | ||
| 1297 | ||
| 1298 | ||
| 1299 | // any PARAMS parms go into naming of macro | |
| 1300 | ||
| 1301 | module l2t_iqu_ctl_msff_ctl_macro__dmsff_32x__width_1 ( | |
| 1302 | din, | |
| 1303 | l1clk, | |
| 1304 | scan_in, | |
| 1305 | siclk, | |
| 1306 | soclk, | |
| 1307 | dout, | |
| 1308 | scan_out); | |
| 1309 | wire [0:0] fdin; | |
| 1310 | ||
| 1311 | input [0:0] din; | |
| 1312 | input l1clk; | |
| 1313 | input scan_in; | |
| 1314 | ||
| 1315 | ||
| 1316 | input siclk; | |
| 1317 | input soclk; | |
| 1318 | ||
| 1319 | output [0:0] dout; | |
| 1320 | output scan_out; | |
| 1321 | assign fdin[0:0] = din[0:0]; | |
| 1322 | ||
| 1323 | ||
| 1324 | ||
| 1325 | ||
| 1326 | ||
| 1327 | ||
| 1328 | dff #(1) d0_0 ( | |
| 1329 | .l1clk(l1clk), | |
| 1330 | .siclk(siclk), | |
| 1331 | .soclk(soclk), | |
| 1332 | .d(fdin[0:0]), | |
| 1333 | .si(scan_in), | |
| 1334 | .so(scan_out), | |
| 1335 | .q(dout[0:0]) | |
| 1336 | ); | |
| 1337 | ||
| 1338 | ||
| 1339 | ||
| 1340 | ||
| 1341 | ||
| 1342 | ||
| 1343 | ||
| 1344 | ||
| 1345 | ||
| 1346 | ||
| 1347 | ||
| 1348 | ||
| 1349 | endmodule | |
| 1350 | ||
| 1351 | ||
| 1352 | ||
| 1353 | ||
| 1354 | ||
| 1355 | ||
| 1356 | ||
| 1357 | ||
| 1358 | ||
| 1359 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 1360 | // also for pass-gate with decoder | |
| 1361 | ||
| 1362 | ||
| 1363 | ||
| 1364 | ||
| 1365 | ||
| 1366 | // any PARAMS parms go into naming of macro | |
| 1367 | ||
| 1368 | module l2t_iqu_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 ( | |
| 1369 | din0, | |
| 1370 | sel0, | |
| 1371 | din1, | |
| 1372 | sel1, | |
| 1373 | din2, | |
| 1374 | sel2, | |
| 1375 | dout); | |
| 1376 | input [3:0] din0; | |
| 1377 | input sel0; | |
| 1378 | input [3:0] din1; | |
| 1379 | input sel1; | |
| 1380 | input [3:0] din2; | |
| 1381 | input sel2; | |
| 1382 | output [3:0] dout; | |
| 1383 | ||
| 1384 | ||
| 1385 | ||
| 1386 | ||
| 1387 | ||
| 1388 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | | |
| 1389 | ( {4{sel1}} & din1[3:0]) | | |
| 1390 | ( {4{sel2}} & din2[3:0]); | |
| 1391 | ||
| 1392 | ||
| 1393 | ||
| 1394 | ||
| 1395 | ||
| 1396 | endmodule | |
| 1397 | ||
| 1398 | ||
| 1399 | ||
| 1400 | ||
| 1401 | ||
| 1402 | ||
| 1403 | // any PARAMS parms go into naming of macro | |
| 1404 | ||
| 1405 | module l2t_iqu_ctl_msff_ctl_macro__width_4 ( | |
| 1406 | din, | |
| 1407 | l1clk, | |
| 1408 | scan_in, | |
| 1409 | siclk, | |
| 1410 | soclk, | |
| 1411 | dout, | |
| 1412 | scan_out); | |
| 1413 | wire [3:0] fdin; | |
| 1414 | wire [2:0] so; | |
| 1415 | ||
| 1416 | input [3:0] din; | |
| 1417 | input l1clk; | |
| 1418 | input scan_in; | |
| 1419 | ||
| 1420 | ||
| 1421 | input siclk; | |
| 1422 | input soclk; | |
| 1423 | ||
| 1424 | output [3:0] dout; | |
| 1425 | output scan_out; | |
| 1426 | assign fdin[3:0] = din[3:0]; | |
| 1427 | ||
| 1428 | ||
| 1429 | ||
| 1430 | ||
| 1431 | ||
| 1432 | ||
| 1433 | dff #(4) d0_0 ( | |
| 1434 | .l1clk(l1clk), | |
| 1435 | .siclk(siclk), | |
| 1436 | .soclk(soclk), | |
| 1437 | .d(fdin[3:0]), | |
| 1438 | .si({scan_in,so[2:0]}), | |
| 1439 | .so({so[2:0],scan_out}), | |
| 1440 | .q(dout[3:0]) | |
| 1441 | ); | |
| 1442 | ||
| 1443 | ||
| 1444 | ||
| 1445 | ||
| 1446 | ||
| 1447 | ||
| 1448 | ||
| 1449 | ||
| 1450 | ||
| 1451 | ||
| 1452 | ||
| 1453 | ||
| 1454 | endmodule | |
| 1455 | ||
| 1456 | ||
| 1457 | ||
| 1458 | ||
| 1459 | ||
| 1460 | ||
| 1461 | ||
| 1462 | ||
| 1463 | ||
| 1464 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 1465 | // also for pass-gate with decoder | |
| 1466 | ||
| 1467 | ||
| 1468 | ||
| 1469 | ||
| 1470 | ||
| 1471 | // any PARAMS parms go into naming of macro | |
| 1472 | ||
| 1473 | module l2t_iqu_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 ( | |
| 1474 | din0, | |
| 1475 | sel0, | |
| 1476 | din1, | |
| 1477 | sel1, | |
| 1478 | dout); | |
| 1479 | input [3:0] din0; | |
| 1480 | input sel0; | |
| 1481 | input [3:0] din1; | |
| 1482 | input sel1; | |
| 1483 | output [3:0] dout; | |
| 1484 | ||
| 1485 | ||
| 1486 | ||
| 1487 | ||
| 1488 | ||
| 1489 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | | |
| 1490 | ( {4{sel1}} & din1[3:0]); | |
| 1491 | ||
| 1492 | ||
| 1493 | ||
| 1494 | ||
| 1495 | ||
| 1496 | endmodule | |
| 1497 | ||
| 1498 | ||
| 1499 | ||
| 1500 | ||
| 1501 | ||
| 1502 | ||
| 1503 | // any PARAMS parms go into naming of macro | |
| 1504 | ||
| 1505 | module l2t_iqu_ctl_msff_ctl_macro__clr_1__width_4 ( | |
| 1506 | din, | |
| 1507 | clr, | |
| 1508 | l1clk, | |
| 1509 | scan_in, | |
| 1510 | siclk, | |
| 1511 | soclk, | |
| 1512 | dout, | |
| 1513 | scan_out); | |
| 1514 | wire [3:0] fdin; | |
| 1515 | wire [2:0] so; | |
| 1516 | ||
| 1517 | input [3:0] din; | |
| 1518 | input clr; | |
| 1519 | input l1clk; | |
| 1520 | input scan_in; | |
| 1521 | ||
| 1522 | ||
| 1523 | input siclk; | |
| 1524 | input soclk; | |
| 1525 | ||
| 1526 | output [3:0] dout; | |
| 1527 | output scan_out; | |
| 1528 | assign fdin[3:0] = din[3:0] & ~{4{clr}}; | |
| 1529 | ||
| 1530 | ||
| 1531 | ||
| 1532 | ||
| 1533 | ||
| 1534 | ||
| 1535 | dff #(4) d0_0 ( | |
| 1536 | .l1clk(l1clk), | |
| 1537 | .siclk(siclk), | |
| 1538 | .soclk(soclk), | |
| 1539 | .d(fdin[3:0]), | |
| 1540 | .si({scan_in,so[2:0]}), | |
| 1541 | .so({so[2:0],scan_out}), | |
| 1542 | .q(dout[3:0]) | |
| 1543 | ); | |
| 1544 | ||
| 1545 | ||
| 1546 | ||
| 1547 | ||
| 1548 | ||
| 1549 | ||
| 1550 | ||
| 1551 | ||
| 1552 | ||
| 1553 | ||
| 1554 | ||
| 1555 | ||
| 1556 | endmodule | |
| 1557 | ||
| 1558 | ||
| 1559 | ||
| 1560 | ||
| 1561 | ||
| 1562 | ||
| 1563 | ||
| 1564 | ||
| 1565 | ||
| 1566 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 1567 | // also for pass-gate with decoder | |
| 1568 | ||
| 1569 | ||
| 1570 | ||
| 1571 | ||
| 1572 | ||
| 1573 | // any PARAMS parms go into naming of macro | |
| 1574 | ||
| 1575 | module l2t_iqu_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_5 ( | |
| 1576 | din0, | |
| 1577 | sel0, | |
| 1578 | din1, | |
| 1579 | sel1, | |
| 1580 | din2, | |
| 1581 | sel2, | |
| 1582 | dout); | |
| 1583 | input [4:0] din0; | |
| 1584 | input sel0; | |
| 1585 | input [4:0] din1; | |
| 1586 | input sel1; | |
| 1587 | input [4:0] din2; | |
| 1588 | input sel2; | |
| 1589 | output [4:0] dout; | |
| 1590 | ||
| 1591 | ||
| 1592 | ||
| 1593 | ||
| 1594 | ||
| 1595 | assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) | | |
| 1596 | ( {5{sel1}} & din1[4:0]) | | |
| 1597 | ( {5{sel2}} & din2[4:0]); | |
| 1598 | ||
| 1599 | ||
| 1600 | ||
| 1601 | ||
| 1602 | ||
| 1603 | endmodule | |
| 1604 | ||
| 1605 | ||
| 1606 | ||
| 1607 | ||
| 1608 | ||
| 1609 | ||
| 1610 | // any PARAMS parms go into naming of macro | |
| 1611 | ||
| 1612 | module l2t_iqu_ctl_msff_ctl_macro__clr_1__width_5 ( | |
| 1613 | din, | |
| 1614 | clr, | |
| 1615 | l1clk, | |
| 1616 | scan_in, | |
| 1617 | siclk, | |
| 1618 | soclk, | |
| 1619 | dout, | |
| 1620 | scan_out); | |
| 1621 | wire [4:0] fdin; | |
| 1622 | wire [3:0] so; | |
| 1623 | ||
| 1624 | input [4:0] din; | |
| 1625 | input clr; | |
| 1626 | input l1clk; | |
| 1627 | input scan_in; | |
| 1628 | ||
| 1629 | ||
| 1630 | input siclk; | |
| 1631 | input soclk; | |
| 1632 | ||
| 1633 | output [4:0] dout; | |
| 1634 | output scan_out; | |
| 1635 | assign fdin[4:0] = din[4:0] & ~{5{clr}}; | |
| 1636 | ||
| 1637 | ||
| 1638 | ||
| 1639 | ||
| 1640 | ||
| 1641 | ||
| 1642 | dff #(5) d0_0 ( | |
| 1643 | .l1clk(l1clk), | |
| 1644 | .siclk(siclk), | |
| 1645 | .soclk(soclk), | |
| 1646 | .d(fdin[4:0]), | |
| 1647 | .si({scan_in,so[3:0]}), | |
| 1648 | .so({so[3:0],scan_out}), | |
| 1649 | .q(dout[4:0]) | |
| 1650 | ); | |
| 1651 | ||
| 1652 | ||
| 1653 | ||
| 1654 | ||
| 1655 | ||
| 1656 | ||
| 1657 | ||
| 1658 | ||
| 1659 | ||
| 1660 | ||
| 1661 | ||
| 1662 | ||
| 1663 | endmodule | |
| 1664 | ||
| 1665 | ||
| 1666 | ||
| 1667 | ||
| 1668 | ||
| 1669 | ||
| 1670 | ||
| 1671 |