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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_ique_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define ADDR_MAP_HI 39 | |
36 | `define ADDR_MAP_LO 32 | |
37 | `define IO_ADDR_BIT 39 | |
38 | ||
39 | // CMP space | |
40 | `define DRAM_DATA_LO 8'h00 | |
41 | `define DRAM_DATA_HI 8'h7f | |
42 | ||
43 | // IOP space | |
44 | `define JBUS1 8'h80 | |
45 | `define HASH_TBL_NRAM_CSR 8'h81 | |
46 | `define RESERVED_1 8'h82 | |
47 | `define ENET_MAC_CSR 8'h83 | |
48 | `define ENET_ING_CSR 8'h84 | |
49 | `define ENET_EGR_CMD_CSR 8'h85 | |
50 | `define ENET_EGR_DP_CSR 8'h86 | |
51 | `define RESERVED_2_LO 8'h87 | |
52 | `define RESERVED_2_HI 8'h92 | |
53 | `define BSC_CSR 8'h93 | |
54 | `define RESERVED_3 8'h94 | |
55 | `define RAND_GEN_CSR 8'h95 | |
56 | `define CLOCK_UNIT_CSR 8'h96 | |
57 | `define DRAM_CSR 8'h97 | |
58 | `define IOB_MAN_CSR 8'h98 | |
59 | `define TAP_CSR 8'h99 | |
60 | `define RESERVED_4_L0 8'h9a | |
61 | `define RESERVED_4_HI 8'h9d | |
62 | `define CPU_ASI 8'h9e | |
63 | `define IOB_INT_CSR 8'h9f | |
64 | ||
65 | // L2 space | |
66 | `define L2C_CSR_LO 8'ha0 | |
67 | `define L2C_CSR_HI 8'hbf | |
68 | ||
69 | // More IOP space | |
70 | `define JBUS2_LO 8'hc0 | |
71 | `define JBUS2_HI 8'hfe | |
72 | `define SPI_CSR 8'hff | |
73 | ||
74 | ||
75 | //Cache Crossbar Width and Field Defines | |
76 | //====================================== | |
77 | `define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change | |
78 | `define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change | |
79 | `define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change | |
80 | `define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change | |
81 | `define CPX_WIDTH11 134 | |
82 | `define CPX_WIDTH11c 134c | |
83 | `define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change | |
84 | ||
85 | `define PCX_VLD 123 //PCX packet valid | |
86 | `define PCX_RQ_HI 122 //PCX request type field | |
87 | `define PCX_RQ_LO 118 | |
88 | `define PCX_NC 117 //PCX non-cacheable bit | |
89 | `define PCX_R 117 //PCX read/!write bit | |
90 | `define PCX_CP_HI 116 //PCX cpu_id field | |
91 | `define PCX_CP_LO 114 | |
92 | `define PCX_TH_HI 113 //PCX Thread field | |
93 | `define PCX_TH_LO 112 | |
94 | `define PCX_BF_HI 111 //PCX buffer id field | |
95 | `define PCX_INVALL 111 | |
96 | `define PCX_BF_LO 109 | |
97 | `define PCX_WY_HI 108 //PCX replaced L1 way field | |
98 | `define PCX_WY_LO 107 | |
99 | `define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01 | |
100 | `define PCX_P_LO 107 | |
101 | `define PCX_SZ_HI 106 //PCX load/store size field | |
102 | `define PCX_SZ_LO 104 | |
103 | `define PCX_ERR_HI 106 //PCX error field | |
104 | `define PCX_ERR_LO 104 | |
105 | `define PCX_AD_HI 103 //PCX address field | |
106 | `define PCX_AD_LO 64 | |
107 | `define PCX_DA_HI 63 //PCX Store data | |
108 | `define PCX_DA_LO 0 | |
109 | ||
110 | `define PCX_SZ_1B 3'b000 // encoding for 1B access | |
111 | `define PCX_SZ_2B 3'b001 // encoding for 2B access | |
112 | `define PCX_SZ_4B 3'b010 // encoding for 4B access | |
113 | `define PCX_SZ_8B 3'b011 // encoding for 8B access | |
114 | `define PCX_SZ_16B 3'b100 // encoding for 16B access | |
115 | ||
116 | `define CPX_VLD 145 //CPX payload packet valid | |
117 | ||
118 | `define CPX_RQ_HI 144 //CPX Request type | |
119 | `define CPX_RQ_LO 141 | |
120 | `define CPX_L2MISS 140 | |
121 | `define CPX_ERR_HI 140 //CPX error field | |
122 | `define CPX_ERR_LO 138 | |
123 | `define CPX_NC 137 //CPX non-cacheable | |
124 | `define CPX_R 137 //CPX read/!write bit | |
125 | `define CPX_TH_HI 136 //CPX thread ID field | |
126 | `define CPX_TH_LO 134 | |
127 | ||
128 | //bits 133:128 are shared by different fields | |
129 | //for different packet types. | |
130 | ||
131 | `define CPX_IN_HI 133 //CPX Interrupt source | |
132 | `define CPX_IN_LO 128 | |
133 | ||
134 | `define CPX_WYVLD 133 //CPX replaced way valid | |
135 | `define CPX_WY_HI 132 //CPX replaced I$/D$ way | |
136 | `define CPX_WY_LO 131 | |
137 | `define CPX_BF_HI 130 //CPX buffer ID field - 3 bits | |
138 | `define CPX_BF_LO 128 | |
139 | ||
140 | `define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits | |
141 | `define CPX_SI_LO 128 //used for invalidates | |
142 | ||
143 | `define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01 | |
144 | `define CPX_P_LO 130 | |
145 | ||
146 | `define CPX_ASI 130 //CPX forward request to ASI | |
147 | `define CPX_IF4B 130 | |
148 | `define CPX_IINV 124 | |
149 | `define CPX_DINV 123 | |
150 | `define CPX_INVPA5 122 | |
151 | `define CPX_INVPA4 121 | |
152 | `define CPX_CPUID_HI 120 | |
153 | `define CPX_CPUID_LO 118 | |
154 | `define CPX_INV_PA_HI 116 | |
155 | `define CPX_INV_PA_LO 112 | |
156 | `define CPX_INV_IDX_HI 117 | |
157 | `define CPX_INV_IDX_LO 112 | |
158 | ||
159 | `define CPX_DA_HI 127 //CPX data payload | |
160 | `define CPX_DA_LO 0 | |
161 | ||
162 | `define LOAD_RQ 5'b00000 | |
163 | `define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change | |
164 | `define IMISS_RQ 5'b10000 | |
165 | `define STORE_RQ 5'b00001 | |
166 | `define CAS1_RQ 5'b00010 | |
167 | `define CAS2_RQ 5'b00011 | |
168 | `define SWAP_RQ 5'b00111 | |
169 | `define STRLOAD_RQ 5'b00100 | |
170 | `define STRST_RQ 5'b00101 | |
171 | `define STQ_RQ 5'b00111 | |
172 | `define INT_RQ 5'b01001 | |
173 | `define FWD_RQ 5'b01101 | |
174 | `define FWD_RPY 5'b01110 | |
175 | `define RSVD_RQ 5'b11111 | |
176 | ||
177 | `define LOAD_RET 4'b0000 | |
178 | `define INV_RET 4'b0011 | |
179 | `define ST_ACK 4'b0100 | |
180 | `define AT_ACK 4'b0011 | |
181 | `define INT_RET 4'b0111 | |
182 | `define TEST_RET 4'b0101 | |
183 | `define FP_RET 4'b1000 | |
184 | `define IFILL_RET 4'b0001 | |
185 | `define EVICT_REQ 4'b0011 | |
186 | //`define INVAL_ACK 4'b1000 | |
187 | `define INVAL_ACK 4'b0100 | |
188 | `define ERR_RET 4'b1100 | |
189 | `define STRLOAD_RET 4'b0010 | |
190 | `define STRST_ACK 4'b0110 | |
191 | `define FWD_RQ_RET 4'b1010 | |
192 | `define FWD_RPY_RET 4'b1011 | |
193 | `define RSVD_RET 4'b1111 | |
194 | ||
195 | //End cache crossbar defines | |
196 | ||
197 | ||
198 | // Number of COS supported by EECU | |
199 | `define EECU_COS_NUM 2 | |
200 | ||
201 | ||
202 | // | |
203 | // BSC bus sizes | |
204 | // ============= | |
205 | // | |
206 | ||
207 | // General | |
208 | `define BSC_ADDRESS 40 | |
209 | `define MAX_XFER_LEN 7'b0 | |
210 | `define XFER_LEN_WIDTH 6 | |
211 | ||
212 | // CTags | |
213 | `define BSC_CTAG_SZ 12 | |
214 | `define EICU_CTAG_PRE 5'b11101 | |
215 | `define EICU_CTAG_REM 7 | |
216 | `define EIPU_CTAG_PRE 3'b011 | |
217 | `define EIPU_CTAG_REM 9 | |
218 | `define EECU_CTAG_PRE 8'b11010000 | |
219 | `define EECU_CTAG_REM 4 | |
220 | `define EEPU_CTAG_PRE 6'b010000 | |
221 | `define EEPU_CTAG_REM 6 | |
222 | `define L2C_CTAG_PRE 2'b00 | |
223 | `define L2C_CTAG_REM 10 | |
224 | `define JBI_CTAG_PRE 2'b10 | |
225 | `define JBI_CTAG_REM 10 | |
226 | // reinstated temporarily | |
227 | `define PCI_CTAG_PRE 7'b1101100 | |
228 | `define PCI_CTAG_REM 5 | |
229 | ||
230 | ||
231 | // CoS | |
232 | `define EICU_COS 1'b0 | |
233 | `define EIPU_COS 1'b1 | |
234 | `define EECU_COS 1'b0 | |
235 | `define EEPU_COS 1'b1 | |
236 | `define PCI_COS 1'b0 | |
237 | ||
238 | // L2$ Bank | |
239 | `define BSC_L2_BNK_HI 8 | |
240 | `define BSC_L2_BNK_LO 6 | |
241 | ||
242 | // L2$ Req | |
243 | `define BSC_L2_REQ_SZ 62 | |
244 | `define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code | |
245 | `define BSC_L2_BUS 64 | |
246 | `define BSC_L2_CTAG_HI 61 | |
247 | `define BSC_L2_CTAG_LO 50 | |
248 | `define BSC_L2_ADD_HI 49 | |
249 | `define BSC_L2_ADD_LO 10 | |
250 | `define BSC_L2_LEN_HI 9 | |
251 | `define BSC_L2_LEN_LO 3 | |
252 | `define BSC_L2_ALLOC 2 | |
253 | `define BSC_L2_COS 1 | |
254 | `define BSC_L2_READ 0 | |
255 | ||
256 | // L2$ Ack | |
257 | `define L2_BSC_ACK_SZ 16 | |
258 | `define L2_BSC_BUS 64 | |
259 | `define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address | |
260 | `define L2_BSC_CBA_LO 13 | |
261 | `define L2_BSC_READ 12 | |
262 | `define L2_BSC_CTAG_HI 11 | |
263 | `define L2_BSC_CTAG_LO 0 | |
264 | ||
265 | // Enet Egress Command Unit | |
266 | `define EECU_REQ_BUS 44 | |
267 | `define EECU_REQ_SZ 44 | |
268 | `define EECU_R_QID_HI 43 | |
269 | `define EECU_R_QID_LO 40 | |
270 | `define EECU_R_ADD_HI 39 | |
271 | `define EECU_R_ADD_LO 0 | |
272 | ||
273 | `define EECU_ACK_BUS 64 | |
274 | `define EECU_ACK_SZ 5 | |
275 | `define EECU_A_NACK 4 | |
276 | `define EECU_A_QID_HI 3 | |
277 | `define EECU_A_QID_LO 0 | |
278 | ||
279 | ||
280 | // Enet Egress Packet Unit | |
281 | `define EEPU_REQ_BUS 55 | |
282 | `define EEPU_REQ_SZ 55 | |
283 | `define EEPU_R_TLEN_HI 54 | |
284 | `define EEPU_R_TLEN_LO 48 | |
285 | `define EEPU_R_SOF 47 | |
286 | `define EEPU_R_EOF 46 | |
287 | `define EEPU_R_PORT_HI 45 | |
288 | `define EEPU_R_PORT_LO 44 | |
289 | `define EEPU_R_QID_HI 43 | |
290 | `define EEPU_R_QID_LO 40 | |
291 | `define EEPU_R_ADD_HI 39 | |
292 | `define EEPU_R_ADD_LO 0 | |
293 | ||
294 | // This is cleaved in between Egress Datapath Ack's | |
295 | `define EEPU_ACK_BUS 6 | |
296 | `define EEPU_ACK_SZ 6 | |
297 | `define EEPU_A_EOF 5 | |
298 | `define EEPU_A_NACK 4 | |
299 | `define EEPU_A_QID_HI 3 | |
300 | `define EEPU_A_QID_LO 0 | |
301 | ||
302 | ||
303 | // Enet Egress Datapath | |
304 | `define EEDP_ACK_BUS 128 | |
305 | `define EEDP_ACK_SZ 28 | |
306 | `define EEDP_A_NACK 27 | |
307 | `define EEDP_A_QID_HI 26 | |
308 | `define EEDP_A_QID_LO 21 | |
309 | `define EEDP_A_SOF 20 | |
310 | `define EEDP_A_EOF 19 | |
311 | `define EEDP_A_LEN_HI 18 | |
312 | `define EEDP_A_LEN_LO 12 | |
313 | `define EEDP_A_TAG_HI 11 | |
314 | `define EEDP_A_TAG_LO 0 | |
315 | `define EEDP_A_PORT_HI 5 | |
316 | `define EEDP_A_PORT_LO 4 | |
317 | `define EEDP_A_PORT_WIDTH 2 | |
318 | ||
319 | ||
320 | // In-Order / Ordered Queue: EEPU | |
321 | // Tag is: TLEN, SOF, EOF, QID = 15 | |
322 | `define EEPU_TAG_ARY (7+1+1+6) | |
323 | `define EEPU_ENTRIES 16 | |
324 | `define EEPU_E_IDX 4 | |
325 | `define EEPU_PORTS 4 | |
326 | `define EEPU_P_IDX 2 | |
327 | ||
328 | // Nack + Tag Info + CTag | |
329 | `define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12) | |
330 | `define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX) | |
331 | ||
332 | ||
333 | // ENET Ingress Queue Management Req | |
334 | `define EICU_REQ_BUS 64 | |
335 | `define EICU_REQ_SZ 62 | |
336 | `define EICU_R_CTAG_HI 61 | |
337 | `define EICU_R_CTAG_LO 50 | |
338 | `define EICU_R_ADD_HI 49 | |
339 | `define EICU_R_ADD_LO 10 | |
340 | `define EICU_R_LEN_HI 9 | |
341 | `define EICU_R_LEN_LO 3 | |
342 | `define EICU_R_COS 1 | |
343 | `define EICU_R_READ 0 | |
344 | ||
345 | ||
346 | // ENET Ingress Queue Management Ack | |
347 | `define EICU_ACK_BUS 64 | |
348 | `define EICU_ACK_SZ 14 | |
349 | `define EICU_A_NACK 13 | |
350 | `define EICU_A_READ 12 | |
351 | `define EICU_A_CTAG_HI 11 | |
352 | `define EICU_A_CTAG_LO 0 | |
353 | ||
354 | ||
355 | // Enet Ingress Packet Unit | |
356 | `define EIPU_REQ_BUS 128 | |
357 | `define EIPU_REQ_SZ 59 | |
358 | `define EIPU_R_CTAG_HI 58 | |
359 | `define EIPU_R_CTAG_LO 50 | |
360 | `define EIPU_R_ADD_HI 49 | |
361 | `define EIPU_R_ADD_LO 10 | |
362 | `define EIPU_R_LEN_HI 9 | |
363 | `define EIPU_R_LEN_LO 3 | |
364 | `define EIPU_R_COS 1 | |
365 | `define EIPU_R_READ 0 | |
366 | ||
367 | ||
368 | // ENET Ingress Packet Unit Ack | |
369 | `define EIPU_ACK_BUS 10 | |
370 | `define EIPU_ACK_SZ 10 | |
371 | `define EIPU_A_NACK 9 | |
372 | `define EIPU_A_CTAG_HI 8 | |
373 | `define EIPU_A_CTAG_LO 0 | |
374 | ||
375 | ||
376 | // In-Order / Ordered Queue: PCI | |
377 | // Tag is: CTAG | |
378 | `define PCI_TAG_ARY 12 | |
379 | `define PCI_ENTRIES 16 | |
380 | `define PCI_E_IDX 4 | |
381 | `define PCI_PORTS 2 | |
382 | ||
383 | // PCI-X Request | |
384 | `define PCI_REQ_BUS 64 | |
385 | `define PCI_REQ_SZ 62 | |
386 | `define PCI_R_CTAG_HI 61 | |
387 | `define PCI_R_CTAG_LO 50 | |
388 | `define PCI_R_ADD_HI 49 | |
389 | `define PCI_R_ADD_LO 10 | |
390 | `define PCI_R_LEN_HI 9 | |
391 | `define PCI_R_LEN_LO 3 | |
392 | `define PCI_R_COS 1 | |
393 | `define PCI_R_READ 0 | |
394 | ||
395 | // PCI_X Acknowledge | |
396 | `define PCI_ACK_BUS 64 | |
397 | `define PCI_ACK_SZ 14 | |
398 | `define PCI_A_NACK 13 | |
399 | `define PCI_A_READ 12 | |
400 | `define PCI_A_CTAG_HI 11 | |
401 | `define PCI_A_CTAG_LO 0 | |
402 | ||
403 | ||
404 | `define BSC_MAX_REQ_SZ 62 | |
405 | ||
406 | ||
407 | // | |
408 | // BSC array sizes | |
409 | //================ | |
410 | // | |
411 | `define BSC_REQ_ARY_INDEX 6 | |
412 | `define BSC_REQ_ARY_DEPTH 64 | |
413 | `define BSC_REQ_ARY_WIDTH 62 | |
414 | `define BSC_REQ_NXT_WIDTH 12 | |
415 | `define BSC_ACK_ARY_INDEX 6 | |
416 | `define BSC_ACK_ARY_DEPTH 64 | |
417 | `define BSC_ACK_ARY_WIDTH 14 | |
418 | `define BSC_ACK_NXT_WIDTH 12 | |
419 | `define BSC_PAY_ARY_INDEX 6 | |
420 | `define BSC_PAY_ARY_DEPTH 64 | |
421 | `define BSC_PAY_ARY_WIDTH 256 | |
422 | ||
423 | // ECC syndrome bits per memory element | |
424 | `define BSC_PAY_ECC 10 | |
425 | `define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH) | |
426 | ||
427 | ||
428 | // | |
429 | // BSC Port Definitions | |
430 | // ==================== | |
431 | // | |
432 | // Bits 7 to 4 of curr_port_id | |
433 | `define BSC_PORT_NULL 4'h0 | |
434 | `define BSC_PORT_SC 4'h1 | |
435 | `define BSC_PORT_EICU 4'h2 | |
436 | `define BSC_PORT_EIPU 4'h3 | |
437 | `define BSC_PORT_EECU 4'h4 | |
438 | `define BSC_PORT_EEPU 4'h8 | |
439 | `define BSC_PORT_PCI 4'h9 | |
440 | ||
441 | // Number of ports of each type | |
442 | `define BSC_PORT_SC_CNT 8 | |
443 | ||
444 | // Bits needed to represent above | |
445 | `define BSC_PORT_SC_IDX 3 | |
446 | ||
447 | // How wide the linked list pointers are | |
448 | // 60b for no payload (2CoS) | |
449 | // 80b for payload (2CoS) | |
450 | ||
451 | //`define BSC_OBJ_PTR 80 | |
452 | //`define BSC_HD1_HI 69 | |
453 | //`define BSC_HD1_LO 60 | |
454 | //`define BSC_TL1_HI 59 | |
455 | //`define BSC_TL1_LO 50 | |
456 | //`define BSC_CT1_HI 49 | |
457 | //`define BSC_CT1_LO 40 | |
458 | //`define BSC_HD0_HI 29 | |
459 | //`define BSC_HD0_LO 20 | |
460 | //`define BSC_TL0_HI 19 | |
461 | //`define BSC_TL0_LO 10 | |
462 | //`define BSC_CT0_HI 9 | |
463 | //`define BSC_CT0_LO 0 | |
464 | ||
465 | `define BSC_OBJP_PTR 48 | |
466 | `define BSC_PYP1_HI 47 | |
467 | `define BSC_PYP1_LO 42 | |
468 | `define BSC_HDP1_HI 41 | |
469 | `define BSC_HDP1_LO 36 | |
470 | `define BSC_TLP1_HI 35 | |
471 | `define BSC_TLP1_LO 30 | |
472 | `define BSC_CTP1_HI 29 | |
473 | `define BSC_CTP1_LO 24 | |
474 | `define BSC_PYP0_HI 23 | |
475 | `define BSC_PYP0_LO 18 | |
476 | `define BSC_HDP0_HI 17 | |
477 | `define BSC_HDP0_LO 12 | |
478 | `define BSC_TLP0_HI 11 | |
479 | `define BSC_TLP0_LO 6 | |
480 | `define BSC_CTP0_HI 5 | |
481 | `define BSC_CTP0_LO 0 | |
482 | ||
483 | `define BSC_PTR_WIDTH 192 | |
484 | `define BSC_PTR_REQ_HI 191 | |
485 | `define BSC_PTR_REQ_LO 144 | |
486 | `define BSC_PTR_REQP_HI 143 | |
487 | `define BSC_PTR_REQP_LO 96 | |
488 | `define BSC_PTR_ACK_HI 95 | |
489 | `define BSC_PTR_ACK_LO 48 | |
490 | `define BSC_PTR_ACKP_HI 47 | |
491 | `define BSC_PTR_ACKP_LO 0 | |
492 | ||
493 | `define BSC_PORT_SC_PTR 96 // R, R+P | |
494 | `define BSC_PORT_EECU_PTR 48 // A+P | |
495 | `define BSC_PORT_EICU_PTR 96 // A, A+P | |
496 | `define BSC_PORT_EIPU_PTR 48 // A | |
497 | ||
498 | // I2C STATES in DRAMctl | |
499 | `define I2C_CMD_NOP 4'b0000 | |
500 | `define I2C_CMD_START 4'b0001 | |
501 | `define I2C_CMD_STOP 4'b0010 | |
502 | `define I2C_CMD_WRITE 4'b0100 | |
503 | `define I2C_CMD_READ 4'b1000 | |
504 | ||
505 | ||
506 | // | |
507 | // IOB defines | |
508 | // =========== | |
509 | // | |
510 | `define IOB_ADDR_WIDTH 40 | |
511 | `define IOB_LOCAL_ADDR_WIDTH 32 | |
512 | ||
513 | `define IOB_CPU_INDEX 3 | |
514 | `define IOB_CPU_WIDTH 8 | |
515 | `define IOB_THR_INDEX 2 | |
516 | `define IOB_THR_WIDTH 4 | |
517 | `define IOB_CPUTHR_INDEX 5 | |
518 | `define IOB_CPUTHR_WIDTH 32 | |
519 | ||
520 | `define IOB_MONDO_DATA_INDEX 5 | |
521 | `define IOB_MONDO_DATA_DEPTH 32 | |
522 | `define IOB_MONDO_DATA_WIDTH 64 | |
523 | `define IOB_MONDO_SRC_WIDTH 5 | |
524 | `define IOB_MONDO_BUSY 5 | |
525 | ||
526 | `define IOB_INT_TAB_INDEX 6 | |
527 | `define IOB_INT_TAB_DEPTH 64 | |
528 | ||
529 | `define IOB_INT_STAT_WIDTH 32 | |
530 | `define IOB_INT_STAT_HI 31 | |
531 | `define IOB_INT_STAT_LO 0 | |
532 | ||
533 | `define IOB_INT_VEC_WIDTH 6 | |
534 | `define IOB_INT_VEC_HI 5 | |
535 | `define IOB_INT_VEC_LO 0 | |
536 | ||
537 | `define IOB_INT_CPU_WIDTH 5 | |
538 | `define IOB_INT_CPU_HI 12 | |
539 | `define IOB_INT_CPU_LO 8 | |
540 | ||
541 | `define IOB_INT_MASK 2 | |
542 | `define IOB_INT_CLEAR 1 | |
543 | `define IOB_INT_PEND 0 | |
544 | ||
545 | `define IOB_DISP_TYPE_HI 17 | |
546 | `define IOB_DISP_TYPE_LO 16 | |
547 | `define IOB_DISP_THR_HI 12 | |
548 | `define IOB_DISP_THR_LO 8 | |
549 | `define IOB_DISP_VEC_HI 5 | |
550 | `define IOB_DISP_VEC_LO 0 | |
551 | ||
552 | `define IOB_JBI_RESET 1 | |
553 | `define IOB_ENET_RESET 0 | |
554 | ||
555 | `define IOB_RESET_STAT_WIDTH 3 | |
556 | `define IOB_RESET_STAT_HI 3 | |
557 | `define IOB_RESET_STAT_LO 1 | |
558 | ||
559 | `define IOB_SERNUM_WIDTH 64 | |
560 | ||
561 | `define IOB_FUSE_WIDTH 22 | |
562 | ||
563 | `define IOB_TMSTAT_THERM 63 | |
564 | ||
565 | `define IOB_POR_TT 6'b01 // power-on-reset trap type | |
566 | ||
567 | `define IOB_CPU_BUF_INDEX 4 | |
568 | ||
569 | `define IOB_INT_BUF_INDEX 4 | |
570 | `define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width | |
571 | ||
572 | `define IOB_IO_BUF_INDEX 4 | |
573 | `define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width | |
574 | ||
575 | `define IOB_L2_VIS_BUF_INDEX 5 | |
576 | `define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width | |
577 | ||
578 | `define IOB_INT_AVEC_WIDTH 16 // availibility vector width | |
579 | `define IOB_ACK_AVEC_WIDTH 16 // availibility vector width | |
580 | ||
581 | // fixme - double check address mapping | |
582 | // CREG in `IOB_INT_CSR space | |
583 | `define IOB_DEV_ADDR_MASK 32'hfffffe07 | |
584 | `define IOB_CREG_INTSTAT 32'h00000000 | |
585 | `define IOB_CREG_MDATA0 32'h00000400 | |
586 | `define IOB_CREG_MDATA1 32'h00000500 | |
587 | `define IOB_CREG_MBUSY 32'h00000900 | |
588 | `define IOB_THR_ADDR_MASK 32'hffffff07 | |
589 | `define IOB_CREG_MDATA0_ALIAS 32'h00000600 | |
590 | `define IOB_CREG_MDATA1_ALIAS 32'h00000700 | |
591 | `define IOB_CREG_MBUSY_ALIAS 32'h00000b00 | |
592 | ||
593 | // CREG in `IOB_MAN_CSR space | |
594 | `define IOB_CREG_INTMAN 32'h00000000 | |
595 | `define IOB_CREG_INTCTL 32'h00000400 | |
596 | `define IOB_CREG_INTVECDISP 32'h00000800 | |
597 | `define IOB_CREG_RESETSTAT 32'h00000810 | |
598 | `define IOB_CREG_SERNUM 32'h00000820 | |
599 | `define IOB_CREG_TMSTATCTRL 32'h00000828 | |
600 | `define IOB_CREG_COREAVAIL 32'h00000830 | |
601 | `define IOB_CREG_SSYSRESET 32'h00000838 | |
602 | `define IOB_CREG_FUSESTAT 32'h00000840 | |
603 | `define IOB_CREG_JINTV 32'h00000a00 | |
604 | ||
605 | `define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800 | |
606 | `define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820 | |
607 | `define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828 | |
608 | `define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830 | |
609 | `define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838 | |
610 | `define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840 | |
611 | `define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000 | |
612 | `define IOB_CREG_DBG_ENET_CTRL 32'h00002000 | |
613 | `define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008 | |
614 | `define IOB_CREG_DBG_JBUS_CTRL 32'h00002100 | |
615 | `define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140 | |
616 | `define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160 | |
617 | `define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148 | |
618 | `define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168 | |
619 | `define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150 | |
620 | `define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170 | |
621 | `define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180 | |
622 | `define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0 | |
623 | `define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188 | |
624 | `define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8 | |
625 | `define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190 | |
626 | `define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0 | |
627 | ||
628 | `define IOB_CREG_TESTSTUB 32'h80000000 | |
629 | ||
630 | // Address map for TAP access of SPARC ASI | |
631 | `define IOB_ASI_PC 4'b0000 | |
632 | `define IOB_ASI_BIST 4'b0001 | |
633 | `define IOB_ASI_MARGIN 4'b0010 | |
634 | `define IOB_ASI_DEFEATURE 4'b0011 | |
635 | `define IOB_ASI_L1DD 4'b0100 | |
636 | `define IOB_ASI_L1ID 4'b0101 | |
637 | `define IOB_ASI_L1DT 4'b0110 | |
638 | ||
639 | `define IOB_INT 2'b00 | |
640 | `define IOB_RESET 2'b01 | |
641 | `define IOB_IDLE 2'b10 | |
642 | `define IOB_RESUME 2'b11 | |
643 | ||
644 | // | |
645 | // CIOP UCB Bus Width | |
646 | // ================== | |
647 | // | |
648 | `define IOB_EECU_WIDTH 16 // ethernet egress command | |
649 | `define EECU_IOB_WIDTH 16 | |
650 | ||
651 | `define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously) | |
652 | `define NRAM_IOB_WIDTH 4 | |
653 | ||
654 | `define IOB_JBI_WIDTH 16 // JBI | |
655 | `define JBI_IOB_WIDTH 16 | |
656 | ||
657 | `define IOB_ENET_ING_WIDTH 32 // ethernet ingress | |
658 | `define ENET_ING_IOB_WIDTH 8 | |
659 | ||
660 | `define IOB_ENET_EGR_WIDTH 4 // ethernet egress | |
661 | `define ENET_EGR_IOB_WIDTH 4 | |
662 | ||
663 | `define IOB_ENET_MAC_WIDTH 4 // ethernet MAC | |
664 | `define ENET_MAC_IOB_WIDTH 4 | |
665 | ||
666 | `define IOB_DRAM_WIDTH 4 // DRAM controller | |
667 | `define DRAM_IOB_WIDTH 4 | |
668 | ||
669 | `define IOB_BSC_WIDTH 4 // BSC | |
670 | `define BSC_IOB_WIDTH 4 | |
671 | ||
672 | `define IOB_SPI_WIDTH 4 // SPI (Boot ROM) | |
673 | `define SPI_IOB_WIDTH 4 | |
674 | ||
675 | `define IOB_CLK_WIDTH 4 // clk unit | |
676 | `define CLK_IOB_WIDTH 4 | |
677 | ||
678 | `define IOB_CLSP_WIDTH 4 // clk spine unit | |
679 | `define CLSP_IOB_WIDTH 4 | |
680 | ||
681 | `define IOB_TAP_WIDTH 8 // TAP | |
682 | `define TAP_IOB_WIDTH 8 | |
683 | ||
684 | ||
685 | // | |
686 | // CIOP UCB Buf ID Type | |
687 | // ==================== | |
688 | // | |
689 | `define UCB_BID_CMP 2'b00 | |
690 | `define UCB_BID_TAP 2'b01 | |
691 | ||
692 | // | |
693 | // Interrupt Device ID | |
694 | // =================== | |
695 | // | |
696 | // Caution: DUMMY_DEV_ID has to be 9 bit wide | |
697 | // for fields to line up properly in the IOB. | |
698 | `define DUMMY_DEV_ID 9'h10 // 16 | |
699 | `define UNCOR_ECC_DEV_ID 7'd17 // 17 | |
700 | ||
701 | // | |
702 | // Soft Error related definitions | |
703 | // ============================== | |
704 | // | |
705 | `define COR_ECC_CNT_WIDTH 16 | |
706 | ||
707 | ||
708 | // | |
709 | // CMP clock | |
710 | // ========= | |
711 | // | |
712 | ||
713 | `define CMP_CLK_PERIOD 1333 | |
714 | ||
715 | ||
716 | // | |
717 | // NRAM/IO Interface | |
718 | // ================= | |
719 | // | |
720 | ||
721 | `define DRAM_CLK_PERIOD 6000 | |
722 | ||
723 | `define NRAM_IO_DQ_WIDTH 32 | |
724 | `define IO_NRAM_DQ_WIDTH 32 | |
725 | ||
726 | `define NRAM_IO_ADDR_WIDTH 15 | |
727 | `define NRAM_IO_BA_WIDTH 2 | |
728 | ||
729 | ||
730 | // | |
731 | // NRAM/ENET Interface | |
732 | // =================== | |
733 | // | |
734 | ||
735 | `define NRAM_ENET_DATA_WIDTH 64 | |
736 | `define ENET_NRAM_ADDR_WIDTH 20 | |
737 | ||
738 | `define NRAM_DBG_DATA_WIDTH 40 | |
739 | ||
740 | ||
741 | // | |
742 | // IO/FCRAM Interface | |
743 | // ================== | |
744 | // | |
745 | ||
746 | `define FCRAM_DATA1_HI 63 | |
747 | `define FCRAM_DATA1_LO 32 | |
748 | `define FCRAM_DATA0_HI 31 | |
749 | `define FCRAM_DATA0_LO 0 | |
750 | ||
751 | // | |
752 | // PCI Interface | |
753 | // ================== | |
754 | // Load/store size encodings | |
755 | // ------------------------- | |
756 | // Size encoding | |
757 | // 000 - byte | |
758 | // 001 - half-word | |
759 | // 010 - word | |
760 | // 011 - double-word | |
761 | // 100 - quad | |
762 | `define LDST_SZ_BYTE 3'b000 | |
763 | `define LDST_SZ_HALF_WORD 3'b001 | |
764 | `define LDST_SZ_WORD 3'b010 | |
765 | `define LDST_SZ_DOUBLE_WORD 3'b011 | |
766 | `define LDST_SZ_QUAD 3'b100 | |
767 | ||
768 | // | |
769 | // JBI<->SCTAG Interface | |
770 | // ======================= | |
771 | // Outbound Header Format | |
772 | `define JBI_BTU_OUT_ADDR_LO 0 | |
773 | `define JBI_BTU_OUT_ADDR_HI 42 | |
774 | `define JBI_BTU_OUT_RSV0_LO 43 | |
775 | `define JBI_BTU_OUT_RSV0_HI 43 | |
776 | `define JBI_BTU_OUT_TYPE_LO 44 | |
777 | `define JBI_BTU_OUT_TYPE_HI 48 | |
778 | `define JBI_BTU_OUT_RSV1_LO 49 | |
779 | `define JBI_BTU_OUT_RSV1_HI 51 | |
780 | `define JBI_BTU_OUT_REPLACE_LO 52 | |
781 | `define JBI_BTU_OUT_REPLACE_HI 56 | |
782 | `define JBI_BTU_OUT_RSV2_LO 57 | |
783 | `define JBI_BTU_OUT_RSV2_HI 59 | |
784 | `define JBI_BTU_OUT_BTU_ID_LO 60 | |
785 | `define JBI_BTU_OUT_BTU_ID_HI 71 | |
786 | `define JBI_BTU_OUT_DATA_RTN 72 | |
787 | `define JBI_BTU_OUT_RSV3_LO 73 | |
788 | `define JBI_BTU_OUT_RSV3_HI 75 | |
789 | `define JBI_BTU_OUT_CE 76 | |
790 | `define JBI_BTU_OUT_RSV4_LO 77 | |
791 | `define JBI_BTU_OUT_RSV4_HI 79 | |
792 | `define JBI_BTU_OUT_UE 80 | |
793 | `define JBI_BTU_OUT_RSV5_LO 81 | |
794 | `define JBI_BTU_OUT_RSV5_HI 83 | |
795 | `define JBI_BTU_OUT_DRAM 84 | |
796 | `define JBI_BTU_OUT_RSV6_LO 85 | |
797 | `define JBI_BTU_OUT_RSV6_HI 127 | |
798 | ||
799 | // Inbound Header Format | |
800 | `define JBI_SCTAG_IN_ADDR_LO 0 | |
801 | `define JBI_SCTAG_IN_ADDR_HI 39 | |
802 | `define JBI_SCTAG_IN_SZ_LO 40 | |
803 | `define JBI_SCTAG_IN_SZ_HI 42 | |
804 | `define JBI_SCTAG_IN_RSV0 43 | |
805 | `define JBI_SCTAG_IN_TAG_LO 44 | |
806 | `define JBI_SCTAG_IN_TAG_HI 55 | |
807 | `define JBI_SCTAG_IN_REQ_LO 56 | |
808 | `define JBI_SCTAG_IN_REQ_HI 58 | |
809 | `define JBI_SCTAG_IN_POISON 59 | |
810 | `define JBI_SCTAG_IN_RSV1_LO 60 | |
811 | `define JBI_SCTAG_IN_RSV1_HI 63 | |
812 | ||
813 | `define JBI_SCTAG_REQ_WRI 3'b100 | |
814 | `define JBI_SCTAG_REQ_WR8 3'b010 | |
815 | `define JBI_SCTAG_REQ_RDD 3'b001 | |
816 | `define JBI_SCTAG_REQ_WRI_BIT 2 | |
817 | `define JBI_SCTAG_REQ_WR8_BIT 1 | |
818 | `define JBI_SCTAG_REQ_RDD_BIT 0 | |
819 | ||
820 | // | |
821 | // JBI->IOB Mondo Header Format | |
822 | // ============================ | |
823 | // | |
824 | `define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1 | |
825 | `define JBI_IOB_MONDO_RSV1_LO 13 | |
826 | `define JBI_IOB_MONDO_TRG_HI 12 // interrupt target | |
827 | `define JBI_IOB_MONDO_TRG_LO 8 | |
828 | `define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0 | |
829 | `define JBI_IOB_MONDO_RSV0_LO 5 | |
830 | `define JBI_IOB_MONDO_SRC_HI 4 // interrupt source | |
831 | `define JBI_IOB_MONDO_SRC_LO 0 | |
832 | ||
833 | `define JBI_IOB_MONDO_RSV1_WIDTH 3 | |
834 | `define JBI_IOB_MONDO_TRG_WIDTH 5 | |
835 | `define JBI_IOB_MONDO_RSV0_WIDTH 3 | |
836 | `define JBI_IOB_MONDO_SRC_WIDTH 5 | |
837 | ||
838 | // JBI->IOB Mondo Bus Width/Cycle | |
839 | // ============================== | |
840 | // Cycle 1 Header[15:8] | |
841 | // Cycle 2 Header[ 7:0] | |
842 | // Cycle 3 J_AD[127:120] | |
843 | // Cycle 4 J_AD[119:112] | |
844 | // ..... | |
845 | // Cycle 18 J_AD[ 7: 0] | |
846 | `define JBI_IOB_MONDO_BUS_WIDTH 8 | |
847 | `define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data | |
848 | ||
849 | ||
850 | ||
851 | module l2t_ique_dp ( | |
852 | tcu_pce_ov, | |
853 | tcu_aclk, | |
854 | tcu_bclk, | |
855 | tcu_scan_en, | |
856 | tcu_clk_stop, | |
857 | tcu_muxtest, | |
858 | tcu_dectest, | |
859 | l2clk, | |
860 | scan_in, | |
861 | pcx_l2t_data_px2, | |
862 | iqu_pcx_l2t_atm_px2_p, | |
863 | iq_array_rd_data_c1, | |
864 | iqu_sel_pcx, | |
865 | iqu_sel_c1, | |
866 | iqu_hold_rd_n, | |
867 | iqu_sel_c1reg_over_iqarray, | |
868 | l2t_mb2_wdata, | |
869 | mbdata_cmp_sel, | |
870 | iq_array_rd_en, | |
871 | scan_out, | |
872 | ique_iq_arbdp_data_px2, | |
873 | ique_iq_arbdp_addr_px2, | |
874 | ique_iq_arbdp_inst_px2, | |
875 | ique_iq_arb_atm_px2, | |
876 | ique_iq_arb_csr_px2, | |
877 | ique_iq_arb_st_px2, | |
878 | ique_iq_arb_vbit_px2, | |
879 | ique_pcx_l2t_data_103_px2, | |
880 | pcx_l2t_data_px2_fnl, | |
881 | ique_arb_pf_ice_px2, | |
882 | iqu_fail_reg); | |
883 | wire stop; | |
884 | wire pce_ov; | |
885 | wire siclk; | |
886 | wire soclk; | |
887 | wire se; | |
888 | wire muxtst; | |
889 | wire test; | |
890 | wire ff_pcx_l2t_data_c1_1_fnl_scanin; | |
891 | wire ff_pcx_l2t_data_c1_1_fnl_scanout; | |
892 | wire ff_pcx_l2t_data_c1_2_fnl_scanin; | |
893 | wire ff_pcx_l2t_data_c1_2_fnl_scanout; | |
894 | wire ique_pf_ice_px2; | |
895 | wire pcx_l2t_data_103_px2_fnl; | |
896 | wire ff_pcx_l2t_data_c1_1_scanin; | |
897 | wire ff_pcx_l2t_data_c1_1_scanout; | |
898 | wire ff_pcx_l2t_data_c1_2_scanin; | |
899 | wire ff_pcx_l2t_data_c1_2_scanout; | |
900 | wire iqu_fail; | |
901 | wire iq_array_rd_en_r2_n; | |
902 | wire iq_array_rd_en_r2; | |
903 | wire iqu_sel_c1reg_over_iqarray_n; | |
904 | wire [4:0] unused; | |
905 | wire ff_iq_array_rd_data_c2_1_scanin; | |
906 | wire ff_iq_array_rd_data_c2_1_scanout; | |
907 | wire ff_iq_array_rd_data_c2_2_scanin; | |
908 | wire ff_iq_array_rd_data_c2_2_scanout; | |
909 | wire iqu_sel_c1_n; | |
910 | wire iqu_sel_pcx_n; | |
911 | wire csr_eq1_out; | |
912 | wire inst_99_is_1; | |
913 | wire store_check1_out; | |
914 | wire store_check2_out; | |
915 | wire bit_123_n; | |
916 | wire store_eqn_2; | |
917 | wire [31:0] iqu_rd_data; | |
918 | wire ff_l2t_mb2_wdata_scanin; | |
919 | wire ff_l2t_mb2_wdata_scanout; | |
920 | wire [31:0] iqu_rd_data_reg; | |
921 | wire [7:0] l2t_mb2_wdata_r2; | |
922 | wire [7:0] l2t_mb2_wdata_r1; | |
923 | wire iq_array_rd_en_r1; | |
924 | wire iqu_fail_raw; | |
925 | ||
926 | ||
927 | input tcu_pce_ov; | |
928 | input tcu_aclk; | |
929 | input tcu_bclk; | |
930 | input tcu_scan_en; | |
931 | input tcu_clk_stop; | |
932 | input tcu_muxtest; | |
933 | input tcu_dectest; | |
934 | ||
935 | input l2clk; | |
936 | input scan_in; | |
937 | input [129:0] pcx_l2t_data_px2; // BS and SR 11/12/03 N2 Xbar Packet format change | |
938 | input iqu_pcx_l2t_atm_px2_p; | |
939 | input [130:0] iq_array_rd_data_c1; // BS and SR 11/12/03 N2 Xbar Packet format change | |
940 | input iqu_sel_pcx; | |
941 | input iqu_sel_c1; | |
942 | input iqu_hold_rd_n; | |
943 | input iqu_sel_c1reg_over_iqarray; | |
944 | input [7:0] l2t_mb2_wdata; | |
945 | input [3:0] mbdata_cmp_sel; | |
946 | input iq_array_rd_en; | |
947 | ||
948 | output scan_out; | |
949 | output [63:0] ique_iq_arbdp_data_px2; | |
950 | output [39:0] ique_iq_arbdp_addr_px2; | |
951 | output [24:0] ique_iq_arbdp_inst_px2; // BS and SR 11/12/03 N2 Xbar Packet format change | |
952 | output ique_iq_arb_atm_px2; | |
953 | output ique_iq_arb_csr_px2; | |
954 | output ique_iq_arb_st_px2; | |
955 | output ique_iq_arb_vbit_px2; | |
956 | output ique_pcx_l2t_data_103_px2; | |
957 | output [129:0] pcx_l2t_data_px2_fnl; // | |
958 | ||
959 | //output ique_pf_ice_px2; | |
960 | output ique_arb_pf_ice_px2; | |
961 | output iqu_fail_reg; | |
962 | ||
963 | assign stop = tcu_clk_stop; | |
964 | assign pce_ov = tcu_pce_ov; | |
965 | assign siclk = tcu_aclk; | |
966 | assign soclk = tcu_bclk; | |
967 | assign se = tcu_scan_en; | |
968 | assign muxtst = tcu_muxtest; | |
969 | assign test = tcu_dectest; | |
970 | ||
971 | ||
972 | //assign scan_out = 1'b0; | |
973 | ||
974 | wire [130:0] pcx_l2t_data_c1; // BS and SR 11/12/03 N2 Xbar Packet format change | |
975 | wire [130:0] tmp_iq_array_rd_data_c1; // BS and SR 11/12/03 N2 Xbar Packet format change | |
976 | wire [130:0] iq_array_rd_data_c2; // BS and SR 11/12/03 N2 Xbar Packet format change | |
977 | wire [130:0] mux_c1c2_rd_data; // BS and SR 11/12/03 N2 Xbar Packet format change | |
978 | wire [130:0] inst; // BS and SR 11/12/03 N2 Xbar Packet format change | |
979 | ||
980 | // BS 06/24/04 : Support for Prefetch ICE | |
981 | // In case PF and INV bits in pcx packet are both 1's , it is a Prefetch ICE packet. | |
982 | // Have to force PA[39] or bit 103 of pcx packet to 1 in that case. | |
983 | // PA[38:37] will be forced to 2'b11 by software itself. So overall PA[39:37] will be | |
984 | // all 1's and Prefetch ICE will always miss in L2 tags irrespective of 8/4/2 bank | |
985 | // mode of operation of N2. | |
986 | // PA[39:37] being all 1's means it wont be decoded as a CSR access also by L2. | |
987 | // L2 decodes csr accesses only for PA[39:37] = 3'b101 | |
988 | ||
989 | //assign ique_pf_ice_px2 = (ique_iq_arbdp_inst_px2[24:20] == `LOAD_RQ) & | |
990 | // ique_iq_arbdp_inst_px2[12] & ique_iq_arbdp_inst_px2[11] ; | |
991 | ||
992 | ||
993 | l2t_ique_dp_msff_macro__stack_66c__width_66 ff_pcx_l2t_data_c1_1_fnl | |
994 | ( | |
995 | .scan_in(ff_pcx_l2t_data_c1_1_fnl_scanin), | |
996 | .scan_out(ff_pcx_l2t_data_c1_1_fnl_scanout), | |
997 | .dout ({pcx_l2t_data_px2_fnl[65:0]}), | |
998 | .din ({pcx_l2t_data_px2[65:0]}), | |
999 | .clk (l2clk), | |
1000 | .en (1'b1), | |
1001 | .se(se), | |
1002 | .siclk(siclk), | |
1003 | .soclk(soclk), | |
1004 | .pce_ov(pce_ov), | |
1005 | .stop(stop) | |
1006 | ); | |
1007 | ||
1008 | l2t_ique_dp_msff_macro__stack_66c__width_64 ff_pcx_l2t_data_c1_2_fnl | |
1009 | ( | |
1010 | .scan_in(ff_pcx_l2t_data_c1_2_fnl_scanin), | |
1011 | .scan_out(ff_pcx_l2t_data_c1_2_fnl_scanout), | |
1012 | .dout (pcx_l2t_data_px2_fnl[129:66]), | |
1013 | .din (pcx_l2t_data_px2[129:66]), | |
1014 | .clk (l2clk), | |
1015 | .en (1'b1), | |
1016 | .se(se), | |
1017 | .siclk(siclk), | |
1018 | .soclk(soclk), | |
1019 | .pce_ov(pce_ov), | |
1020 | .stop(stop) | |
1021 | ); | |
1022 | ||
1023 | ||
1024 | l2t_ique_dp_cmp_macro__dcmp_8x__width_8 cmp_ique_pf_ice_px2 | |
1025 | ( | |
1026 | .dout (ique_pf_ice_px2), | |
1027 | .din0 ({pcx_l2t_data_px2_fnl[128:124],pcx_l2t_data_px2_fnl[116:115],1'b0}), | |
1028 | .din1 (8'b00000110) | |
1029 | ); | |
1030 | ||
1031 | l2t_ique_dp_or_macro__ports_2__width_1 or_pa39_prf_ice | |
1032 | ( | |
1033 | .dout (pcx_l2t_data_103_px2_fnl), | |
1034 | .din0 (pcx_l2t_data_px2_fnl[103]), | |
1035 | .din1 (ique_pf_ice_px2) | |
1036 | ); | |
1037 | ||
1038 | ||
1039 | l2t_ique_dp_buff_macro__dbuff_16x__width_1 buff_ique_pcx_l2t_data_103_px2 | |
1040 | ( | |
1041 | .dout ( ique_pcx_l2t_data_103_px2 ), | |
1042 | .din ( pcx_l2t_data_103_px2_fnl) | |
1043 | ); | |
1044 | ||
1045 | l2t_ique_dp_msff_macro__stack_66c__width_66 ff_pcx_l2t_data_c1_1 | |
1046 | ( | |
1047 | .scan_in(ff_pcx_l2t_data_c1_1_scanin), | |
1048 | .scan_out(ff_pcx_l2t_data_c1_1_scanout), | |
1049 | .dout ({pcx_l2t_data_c1[65:0]}), | |
1050 | .din ({pcx_l2t_data_px2_fnl[65:0]}), | |
1051 | .clk (l2clk), | |
1052 | .en (1'b1), | |
1053 | .se(se), | |
1054 | .siclk(siclk), | |
1055 | .soclk(soclk), | |
1056 | .pce_ov(pce_ov), | |
1057 | .stop(stop) | |
1058 | ); | |
1059 | ||
1060 | l2t_ique_dp_msff_macro__stack_66c__width_66 ff_pcx_l2t_data_c1_2 | |
1061 | ( | |
1062 | .scan_in(ff_pcx_l2t_data_c1_2_scanin), | |
1063 | .scan_out(ff_pcx_l2t_data_c1_2_scanout), | |
1064 | .dout ({iqu_fail_reg,pcx_l2t_data_c1[130:66]}), | |
1065 | .din ({iqu_fail,iqu_pcx_l2t_atm_px2_p,pcx_l2t_data_px2_fnl[129:128], | |
1066 | pcx_l2t_data_px2_fnl[127:104],pcx_l2t_data_103_px2_fnl,pcx_l2t_data_px2_fnl[102:66]}), | |
1067 | .clk (l2clk), | |
1068 | .en (1'b1), | |
1069 | .se(se), | |
1070 | .siclk(siclk), | |
1071 | .soclk(soclk), | |
1072 | .pce_ov(pce_ov), | |
1073 | .stop(stop) | |
1074 | ); | |
1075 | ||
1076 | ||
1077 | l2t_ique_dp_inv_macro__dinv_16x__width_1 iqu_hold_rd_invert | |
1078 | ( | |
1079 | .dout (iq_array_rd_en_r2_n), | |
1080 | .din (iq_array_rd_en_r2) | |
1081 | ); | |
1082 | ||
1083 | ||
1084 | l2t_ique_dp_inv_macro__dinv_16x__width_1 mux_iq_array_rd_data_c1_sel_invert | |
1085 | ( | |
1086 | .dout (iqu_sel_c1reg_over_iqarray_n), | |
1087 | .din (iqu_sel_c1reg_over_iqarray ) | |
1088 | ); | |
1089 | ||
1090 | l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_66c__width_66 mux_iq_array_rd_data_c1_1 | |
1091 | ( | |
1092 | .dout (tmp_iq_array_rd_data_c1[65:0]), | |
1093 | .din0 (iq_array_rd_data_c1[65:0]), | |
1094 | .din1 (pcx_l2t_data_c1[65:0]), | |
1095 | .sel0 (iqu_sel_c1reg_over_iqarray_n), | |
1096 | .sel1 (iqu_sel_c1reg_over_iqarray) | |
1097 | ); | |
1098 | ||
1099 | l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_66c__width_66 mux_iq_array_rd_data_c1_2 // BS and SR 11/12/03 N2 Xbar Packet format change | |
1100 | ( | |
1101 | .dout ({unused[0],tmp_iq_array_rd_data_c1[130:66]}), | |
1102 | .din0 ({1'b0,iq_array_rd_data_c1[130:66]}), | |
1103 | .din1 ({1'b0,pcx_l2t_data_c1[130:66]}), | |
1104 | .sel0 (iqu_sel_c1reg_over_iqarray_n), | |
1105 | .sel1 (iqu_sel_c1reg_over_iqarray) | |
1106 | ) ; | |
1107 | ||
1108 | ||
1109 | l2t_ique_dp_msff_macro__stack_66c__width_66 ff_iq_array_rd_data_c2_1 | |
1110 | ( | |
1111 | .scan_in(ff_iq_array_rd_data_c2_1_scanin), | |
1112 | .scan_out(ff_iq_array_rd_data_c2_1_scanout), | |
1113 | .dout (iq_array_rd_data_c2[65:0]), | |
1114 | .din (tmp_iq_array_rd_data_c1[65:0]), | |
1115 | .clk (l2clk), | |
1116 | .en (iqu_hold_rd_n), | |
1117 | .se(se), | |
1118 | .siclk(siclk), | |
1119 | .soclk(soclk), | |
1120 | .pce_ov(pce_ov), | |
1121 | .stop(stop) | |
1122 | ) ; | |
1123 | ||
1124 | l2t_ique_dp_msff_macro__stack_66c__width_66 ff_iq_array_rd_data_c2_2 | |
1125 | ( | |
1126 | .scan_in(ff_iq_array_rd_data_c2_2_scanin), | |
1127 | .scan_out(ff_iq_array_rd_data_c2_2_scanout), | |
1128 | .dout ({unused[1],iq_array_rd_data_c2[130:66]}), | |
1129 | .din ({1'b0,tmp_iq_array_rd_data_c1[130:66]}), | |
1130 | .clk (l2clk), | |
1131 | .en (iqu_hold_rd_n), | |
1132 | .se(se), | |
1133 | .siclk(siclk), | |
1134 | .soclk(soclk), | |
1135 | .pce_ov(pce_ov), | |
1136 | .stop(stop) | |
1137 | ); | |
1138 | ||
1139 | ||
1140 | l2t_ique_dp_inv_macro__dinv_16x__width_1 u_mux_c1c2_rd_data_sel_invert | |
1141 | ( | |
1142 | .dout (iqu_sel_c1_n), | |
1143 | .din (iqu_sel_c1 ) | |
1144 | ); | |
1145 | ||
1146 | l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_66c__width_66 u_mux_c1c2_rd_data_1 | |
1147 | ( | |
1148 | .dout (mux_c1c2_rd_data[65:0]), | |
1149 | .din0 (pcx_l2t_data_c1[65:0]), | |
1150 | .din1 (iq_array_rd_data_c2[65:0]), | |
1151 | .sel0 (iqu_sel_c1), | |
1152 | .sel1 (iqu_sel_c1_n) | |
1153 | ) ; | |
1154 | ||
1155 | l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_66c__width_66 u_mux_c1c2_rd_data_2 // BS and SR 11/12/03 N2 Xbar Packet format change | |
1156 | ( | |
1157 | .dout ({unused[2],mux_c1c2_rd_data[130:66]}), | |
1158 | .din0 ({1'b0,pcx_l2t_data_c1[130:66]}), | |
1159 | .din1 ({1'b0,iq_array_rd_data_c2[130:66]}), | |
1160 | .sel0 (iqu_sel_c1), | |
1161 | .sel1 (iqu_sel_c1_n) | |
1162 | ) ; | |
1163 | ||
1164 | l2t_ique_dp_inv_macro__width_1 mux_inst_sel_invert | |
1165 | ( | |
1166 | .dout (iqu_sel_pcx_n), | |
1167 | .din (iqu_sel_pcx ) | |
1168 | ); | |
1169 | ||
1170 | ||
1171 | l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_66c__width_66 mux_inst_1 | |
1172 | ( | |
1173 | .dout (inst[65:0]), | |
1174 | .din0 (pcx_l2t_data_px2_fnl[65:0]), | |
1175 | .din1 (mux_c1c2_rd_data[65:0]), | |
1176 | .sel0 (iqu_sel_pcx), | |
1177 | .sel1 (iqu_sel_pcx_n) | |
1178 | ); | |
1179 | ||
1180 | l2t_ique_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_66c__width_66 mux_inst_2 | |
1181 | ( | |
1182 | .dout ({unused[3],inst[130:66]}), | |
1183 | .din0 ({1'b0,iqu_pcx_l2t_atm_px2_p,pcx_l2t_data_px2_fnl[129:104], | |
1184 | pcx_l2t_data_103_px2_fnl,pcx_l2t_data_px2_fnl[102:66]}), | |
1185 | .din1 ({1'b0,mux_c1c2_rd_data[130:66]}), | |
1186 | .sel0 (iqu_sel_pcx) | |
1187 | ) ; | |
1188 | ||
1189 | l2t_ique_dp_cmp_macro__dcmp_8x__width_8 cmp_ique_pf_ice_fnl | |
1190 | ( | |
1191 | .dout (ique_arb_pf_ice_px2), | |
1192 | .din0 ({inst[128:124],inst[116:115],1'b0}), | |
1193 | .din1 (8'b00000110) | |
1194 | ); | |
1195 | ||
1196 | ||
1197 | //assign ique_iq_arbdp_data_px2 = inst[63:0] ; | |
1198 | //assign ique_iq_arbdp_addr_px2 = inst[103:64] ; | |
1199 | //assign ique_iq_arbdp_inst_px2 = inst[128:104] ; // BS and SR 11/12/03 N2 Xbar Packet format change | |
1200 | //assign ique_iq_arb_vbit_px2 = inst[129]; // BS and SR 11/12/03 N2 Xbar Packet format change | |
1201 | //assign ique_iq_arb_atm_px2 = inst[130] ; // BS and SR 11/12/03 N2 Xbar Packet format change | |
1202 | //assign ique_iq_arb_csr_px2 = (inst[103:101] == 5'b101) & (inst[99] == 1'b1) ; | |
1203 | // BS and SR 11/12/03 N2 Xbar Packet format change : | |
1204 | //assign ique_iq_arb_st_px2 = ( (inst[128:124] == 5'b00001) | // Store | |
1205 | // (( inst[128:124] == 5'b01101) & | |
1206 | // ~inst[123]) ) ; // FWD_REQ with | |
1207 | // // R/Wbar == 0 | |
1208 | // | |
1209 | ||
1210 | l2t_ique_dp_buff_macro__dbuff_32x__stack_66c__width_66 ique_arbdp_slice0 | |
1211 | ( | |
1212 | .dout ({ique_iq_arbdp_addr_px2[1:0],ique_iq_arbdp_data_px2[63:0]}), | |
1213 | .din (inst[65:0]) | |
1214 | ); | |
1215 | ||
1216 | // | |
1217 | //buff_macro ique_arbdp_slice1 (width=66,stack=66c,dbuff=32x) | |
1218 | // ( | |
1219 | // .dout ({unused_6,ique_iq_arb_atm_px2,ique_iq_arb_vbit_px2, | |
1220 | // ique_iq_arbdp_inst_px2[24:0],ique_iq_arbdp_addr_px2[39:2]}), | |
1221 | // .din ({1'b0,inst[130:66]}) | |
1222 | // ); | |
1223 | ||
1224 | ||
1225 | assign {unused[4],ique_iq_arb_atm_px2,ique_iq_arb_vbit_px2, | |
1226 | ique_iq_arbdp_inst_px2[24:0],ique_iq_arbdp_addr_px2[39:2]} = {1'b0,inst[130:66]}; | |
1227 | ||
1228 | ||
1229 | l2t_ique_dp_cmp_macro__dcmp_8x__width_8 csr_check_eq1 | |
1230 | ( | |
1231 | .din0 ({3'b0,5'b101}), | |
1232 | .din1 ({5'b0,inst[103:101]}), | |
1233 | .dout (csr_eq1_out) | |
1234 | ); | |
1235 | ||
1236 | l2t_ique_dp_and_macro__width_1 inst_99_1 | |
1237 | ( | |
1238 | .dout (inst_99_is_1), | |
1239 | .din0 (inst[99]), | |
1240 | .din1 (1'b1) | |
1241 | ); | |
1242 | ||
1243 | l2t_ique_dp_and_macro__width_1 csr_inst_decode | |
1244 | ( | |
1245 | .dout (ique_iq_arb_csr_px2), | |
1246 | .din0 (inst_99_is_1), | |
1247 | .din1 (csr_eq1_out) | |
1248 | ); | |
1249 | ||
1250 | l2t_ique_dp_cmp_macro__dcmp_8x__width_8 store_check_1 | |
1251 | ( | |
1252 | .din0 ({3'b0,5'b00001}), | |
1253 | .din1 ({3'b0,inst[128:124]}), // BS and SR 11/12/03 N2 Xbar Packet format change | |
1254 | .dout (store_check1_out) | |
1255 | ); | |
1256 | ||
1257 | l2t_ique_dp_cmp_macro__dcmp_8x__width_8 store_check_2 | |
1258 | ( | |
1259 | .din0 ({3'b0,5'b01101}), | |
1260 | .din1 ({3'b0,inst[128:124]}), // BS and SR 11/12/03 N2 Xbar Packet format change | |
1261 | .dout (store_check2_out) | |
1262 | ); | |
1263 | ||
1264 | l2t_ique_dp_inv_macro__dinv_16x__width_1 invert_bit_inst_123 // BS and SR 11/12/03 N2 Xbar Packet format change | |
1265 | ( | |
1266 | .dout (bit_123_n), | |
1267 | .din (inst[123] ) | |
1268 | ); | |
1269 | ||
1270 | l2t_ique_dp_and_macro__width_1 store_2_slice ( | |
1271 | .dout (store_eqn_2), | |
1272 | .din0 (bit_123_n), // BS and SR 11/12/03 N2 Xbar Packet format change | |
1273 | .din1 (store_check2_out) | |
1274 | ); | |
1275 | ||
1276 | l2t_ique_dp_or_macro__width_1 store2_slice ( | |
1277 | .dout (ique_iq_arb_st_px2), | |
1278 | .din0 (store_eqn_2), | |
1279 | .din1 (store_check1_out) | |
1280 | ); | |
1281 | ||
1282 | /////// MBIST ////// | |
1283 | ||
1284 | ||
1285 | l2t_ique_dp_mux_macro__dmux_16x__mux_pgpe__ports_4__width_32 mux_iq_array_rd_data_c1 // ATPG Clean up | |
1286 | ( | |
1287 | .dout (iqu_rd_data[31:0]), | |
1288 | .din0 (iq_array_rd_data_c1[31:0]), | |
1289 | .din1 (iq_array_rd_data_c1[63:32]), | |
1290 | .din2 (iq_array_rd_data_c1[95:64]), | |
1291 | .din3 (iq_array_rd_data_c1[127:96]), | |
1292 | .sel0 (mbdata_cmp_sel[0]), | |
1293 | .sel1 (mbdata_cmp_sel[1]), | |
1294 | .sel2 (mbdata_cmp_sel[2]), | |
1295 | .muxtst(muxtst), | |
1296 | .test(test) | |
1297 | ); | |
1298 | ||
1299 | l2t_ique_dp_msff_macro__dmsff_32x__stack_66c__width_50 ff_l2t_mb2_wdata | |
1300 | ( | |
1301 | .scan_in(ff_l2t_mb2_wdata_scanin), | |
1302 | .scan_out(ff_l2t_mb2_wdata_scanout), | |
1303 | .dout ({iqu_rd_data_reg[31:0], | |
1304 | l2t_mb2_wdata_r2[7:0], | |
1305 | l2t_mb2_wdata_r1[7:0], | |
1306 | iq_array_rd_en_r1, | |
1307 | iq_array_rd_en_r2}), | |
1308 | .din ({iqu_rd_data[31:0], | |
1309 | l2t_mb2_wdata_r1[7:0], | |
1310 | l2t_mb2_wdata[7:0], | |
1311 | iq_array_rd_en, | |
1312 | iq_array_rd_en_r1}), | |
1313 | .clk (l2clk), | |
1314 | .en (1'b1), | |
1315 | .se(se), | |
1316 | .siclk(siclk), | |
1317 | .soclk(soclk), | |
1318 | .pce_ov(pce_ov), | |
1319 | .stop(stop) | |
1320 | ); | |
1321 | ||
1322 | l2t_ique_dp_cmp_macro__dcmp_8x__width_32 cmp_iqu_data | |
1323 | ( | |
1324 | .dout (iqu_fail_raw), | |
1325 | .din0 ({4{l2t_mb2_wdata_r2[7:0]}}), | |
1326 | .din1 (iqu_rd_data_reg[31:0]) | |
1327 | ); | |
1328 | ||
1329 | l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 mux_iqu_fail | |
1330 | ( | |
1331 | .dout (iqu_fail), | |
1332 | .din0 (iqu_fail_raw), | |
1333 | .din1 (1'b1), | |
1334 | .sel0 (iq_array_rd_en_r2), | |
1335 | .sel1 (iq_array_rd_en_r2_n) | |
1336 | ); | |
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | // fixscan start: | |
1342 | assign ff_pcx_l2t_data_c1_1_fnl_scanin = scan_in ; | |
1343 | assign ff_pcx_l2t_data_c1_2_fnl_scanin = ff_pcx_l2t_data_c1_1_fnl_scanout; | |
1344 | assign ff_pcx_l2t_data_c1_1_scanin = ff_pcx_l2t_data_c1_2_fnl_scanout; | |
1345 | assign ff_pcx_l2t_data_c1_2_scanin = ff_pcx_l2t_data_c1_1_scanout; | |
1346 | assign ff_iq_array_rd_data_c2_1_scanin = ff_pcx_l2t_data_c1_2_scanout; | |
1347 | assign ff_iq_array_rd_data_c2_2_scanin = ff_iq_array_rd_data_c2_1_scanout; | |
1348 | assign ff_l2t_mb2_wdata_scanin = ff_iq_array_rd_data_c2_2_scanout; | |
1349 | assign scan_out = ff_l2t_mb2_wdata_scanout ; | |
1350 | // fixscan end: | |
1351 | endmodule | |
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | // any PARAMS parms go into naming of macro | |
1359 | ||
1360 | module l2t_ique_dp_msff_macro__stack_66c__width_66 ( | |
1361 | din, | |
1362 | clk, | |
1363 | en, | |
1364 | se, | |
1365 | scan_in, | |
1366 | siclk, | |
1367 | soclk, | |
1368 | pce_ov, | |
1369 | stop, | |
1370 | dout, | |
1371 | scan_out); | |
1372 | wire l1clk; | |
1373 | wire siclk_out; | |
1374 | wire soclk_out; | |
1375 | wire [64:0] so; | |
1376 | ||
1377 | input [65:0] din; | |
1378 | ||
1379 | ||
1380 | input clk; | |
1381 | input en; | |
1382 | input se; | |
1383 | input scan_in; | |
1384 | input siclk; | |
1385 | input soclk; | |
1386 | input pce_ov; | |
1387 | input stop; | |
1388 | ||
1389 | ||
1390 | ||
1391 | output [65:0] dout; | |
1392 | ||
1393 | ||
1394 | output scan_out; | |
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | cl_dp1_l1hdr_8x c0_0 ( | |
1400 | .l2clk(clk), | |
1401 | .pce(en), | |
1402 | .aclk(siclk), | |
1403 | .bclk(soclk), | |
1404 | .l1clk(l1clk), | |
1405 | .se(se), | |
1406 | .pce_ov(pce_ov), | |
1407 | .stop(stop), | |
1408 | .siclk_out(siclk_out), | |
1409 | .soclk_out(soclk_out) | |
1410 | ); | |
1411 | dff #(66) d0_0 ( | |
1412 | .l1clk(l1clk), | |
1413 | .siclk(siclk_out), | |
1414 | .soclk(soclk_out), | |
1415 | .d(din[65:0]), | |
1416 | .si({scan_in,so[64:0]}), | |
1417 | .so({so[64:0],scan_out}), | |
1418 | .q(dout[65:0]) | |
1419 | ); | |
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | ||
1435 | ||
1436 | ||
1437 | ||
1438 | ||
1439 | ||
1440 | endmodule | |
1441 | ||
1442 | ||
1443 | ||
1444 | ||
1445 | ||
1446 | ||
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | // any PARAMS parms go into naming of macro | |
1455 | ||
1456 | module l2t_ique_dp_msff_macro__stack_66c__width_64 ( | |
1457 | din, | |
1458 | clk, | |
1459 | en, | |
1460 | se, | |
1461 | scan_in, | |
1462 | siclk, | |
1463 | soclk, | |
1464 | pce_ov, | |
1465 | stop, | |
1466 | dout, | |
1467 | scan_out); | |
1468 | wire l1clk; | |
1469 | wire siclk_out; | |
1470 | wire soclk_out; | |
1471 | wire [62:0] so; | |
1472 | ||
1473 | input [63:0] din; | |
1474 | ||
1475 | ||
1476 | input clk; | |
1477 | input en; | |
1478 | input se; | |
1479 | input scan_in; | |
1480 | input siclk; | |
1481 | input soclk; | |
1482 | input pce_ov; | |
1483 | input stop; | |
1484 | ||
1485 | ||
1486 | ||
1487 | output [63:0] dout; | |
1488 | ||
1489 | ||
1490 | output scan_out; | |
1491 | ||
1492 | ||
1493 | ||
1494 | ||
1495 | cl_dp1_l1hdr_8x c0_0 ( | |
1496 | .l2clk(clk), | |
1497 | .pce(en), | |
1498 | .aclk(siclk), | |
1499 | .bclk(soclk), | |
1500 | .l1clk(l1clk), | |
1501 | .se(se), | |
1502 | .pce_ov(pce_ov), | |
1503 | .stop(stop), | |
1504 | .siclk_out(siclk_out), | |
1505 | .soclk_out(soclk_out) | |
1506 | ); | |
1507 | dff #(64) d0_0 ( | |
1508 | .l1clk(l1clk), | |
1509 | .siclk(siclk_out), | |
1510 | .soclk(soclk_out), | |
1511 | .d(din[63:0]), | |
1512 | .si({scan_in,so[62:0]}), | |
1513 | .so({so[62:0],scan_out}), | |
1514 | .q(dout[63:0]) | |
1515 | ); | |
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | endmodule | |
1537 | ||
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | // | |
1547 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
1548 | // | |
1549 | // | |
1550 | ||
1551 | ||
1552 | ||
1553 | ||
1554 | ||
1555 | module l2t_ique_dp_cmp_macro__dcmp_8x__width_8 ( | |
1556 | din0, | |
1557 | din1, | |
1558 | dout); | |
1559 | input [7:0] din0; | |
1560 | input [7:0] din1; | |
1561 | output dout; | |
1562 | ||
1563 | ||
1564 | ||
1565 | ||
1566 | ||
1567 | ||
1568 | cmp #(8) m0_0 ( | |
1569 | .in0(din0[7:0]), | |
1570 | .in1(din1[7:0]), | |
1571 | .out(dout) | |
1572 | ); | |
1573 | ||
1574 | ||
1575 | ||
1576 | ||
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | endmodule | |
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | ||
1589 | // | |
1590 | // or macro for ports = 2,3 | |
1591 | // | |
1592 | // | |
1593 | ||
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | module l2t_ique_dp_or_macro__ports_2__width_1 ( | |
1599 | din0, | |
1600 | din1, | |
1601 | dout); | |
1602 | input [0:0] din0; | |
1603 | input [0:0] din1; | |
1604 | output [0:0] dout; | |
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | ||
1610 | ||
1611 | or2 #(1) d0_0 ( | |
1612 | .in0(din0[0:0]), | |
1613 | .in1(din1[0:0]), | |
1614 | .out(dout[0:0]) | |
1615 | ); | |
1616 | ||
1617 | ||
1618 | ||
1619 | ||
1620 | ||
1621 | ||
1622 | ||
1623 | ||
1624 | ||
1625 | endmodule | |
1626 | ||
1627 | ||
1628 | ||
1629 | ||
1630 | ||
1631 | // | |
1632 | // buff macro | |
1633 | // | |
1634 | // | |
1635 | ||
1636 | ||
1637 | ||
1638 | ||
1639 | ||
1640 | module l2t_ique_dp_buff_macro__dbuff_16x__width_1 ( | |
1641 | din, | |
1642 | dout); | |
1643 | input [0:0] din; | |
1644 | output [0:0] dout; | |
1645 | ||
1646 | ||
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | buff #(1) d0_0 ( | |
1652 | .in(din[0:0]), | |
1653 | .out(dout[0:0]) | |
1654 | ); | |
1655 | ||
1656 | ||
1657 | ||
1658 | ||
1659 | ||
1660 | ||
1661 | ||
1662 | ||
1663 | endmodule | |
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | ||
1669 | // | |
1670 | // invert macro | |
1671 | // | |
1672 | // | |
1673 | ||
1674 | ||
1675 | ||
1676 | ||
1677 | ||
1678 | module l2t_ique_dp_inv_macro__dinv_16x__width_1 ( | |
1679 | din, | |
1680 | dout); | |
1681 | input [0:0] din; | |
1682 | output [0:0] dout; | |
1683 | ||
1684 | ||
1685 | ||
1686 | ||
1687 | ||
1688 | ||
1689 | inv #(1) d0_0 ( | |
1690 | .in(din[0:0]), | |
1691 | .out(dout[0:0]) | |
1692 | ); | |
1693 | ||
1694 | ||
1695 | ||
1696 | ||
1697 | ||
1698 | ||
1699 | ||
1700 | ||
1701 | ||
1702 | endmodule | |
1703 | ||
1704 | ||
1705 | ||
1706 | ||
1707 | ||
1708 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1709 | // also for pass-gate with decoder | |
1710 | ||
1711 | ||
1712 | ||
1713 | ||
1714 | ||
1715 | // any PARAMS parms go into naming of macro | |
1716 | ||
1717 | module l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_66c__width_66 ( | |
1718 | din0, | |
1719 | sel0, | |
1720 | din1, | |
1721 | sel1, | |
1722 | dout); | |
1723 | wire buffout0; | |
1724 | wire buffout1; | |
1725 | ||
1726 | input [65:0] din0; | |
1727 | input sel0; | |
1728 | input [65:0] din1; | |
1729 | input sel1; | |
1730 | output [65:0] dout; | |
1731 | ||
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | cl_dp1_muxbuff2_8x c0_0 ( | |
1737 | .in0(sel0), | |
1738 | .in1(sel1), | |
1739 | .out0(buffout0), | |
1740 | .out1(buffout1) | |
1741 | ); | |
1742 | mux2s #(66) d0_0 ( | |
1743 | .sel0(buffout0), | |
1744 | .sel1(buffout1), | |
1745 | .in0(din0[65:0]), | |
1746 | .in1(din1[65:0]), | |
1747 | .dout(dout[65:0]) | |
1748 | ); | |
1749 | ||
1750 | ||
1751 | ||
1752 | ||
1753 | ||
1754 | ||
1755 | ||
1756 | ||
1757 | ||
1758 | ||
1759 | ||
1760 | ||
1761 | ||
1762 | endmodule | |
1763 | ||
1764 | ||
1765 | // | |
1766 | // invert macro | |
1767 | // | |
1768 | // | |
1769 | ||
1770 | ||
1771 | ||
1772 | ||
1773 | ||
1774 | module l2t_ique_dp_inv_macro__width_1 ( | |
1775 | din, | |
1776 | dout); | |
1777 | input [0:0] din; | |
1778 | output [0:0] dout; | |
1779 | ||
1780 | ||
1781 | ||
1782 | ||
1783 | ||
1784 | ||
1785 | inv #(1) d0_0 ( | |
1786 | .in(din[0:0]), | |
1787 | .out(dout[0:0]) | |
1788 | ); | |
1789 | ||
1790 | ||
1791 | ||
1792 | ||
1793 | ||
1794 | ||
1795 | ||
1796 | ||
1797 | ||
1798 | endmodule | |
1799 | ||
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1805 | // also for pass-gate with decoder | |
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | // any PARAMS parms go into naming of macro | |
1812 | ||
1813 | module l2t_ique_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_66c__width_66 ( | |
1814 | din0, | |
1815 | din1, | |
1816 | sel0, | |
1817 | dout); | |
1818 | wire psel0_unused; | |
1819 | wire psel1; | |
1820 | ||
1821 | input [65:0] din0; | |
1822 | input [65:0] din1; | |
1823 | input sel0; | |
1824 | output [65:0] dout; | |
1825 | ||
1826 | ||
1827 | ||
1828 | ||
1829 | ||
1830 | cl_dp1_penc2_8x c0_0 ( | |
1831 | .sel0(sel0), | |
1832 | .psel0(psel0_unused), | |
1833 | .psel1(psel1) | |
1834 | ); | |
1835 | ||
1836 | mux2e #(66) d0_0 ( | |
1837 | .sel(psel1), | |
1838 | .in0(din0[65:0]), | |
1839 | .in1(din1[65:0]), | |
1840 | .dout(dout[65:0]) | |
1841 | ); | |
1842 | ||
1843 | ||
1844 | ||
1845 | ||
1846 | ||
1847 | ||
1848 | ||
1849 | ||
1850 | ||
1851 | ||
1852 | ||
1853 | ||
1854 | ||
1855 | endmodule | |
1856 | ||
1857 | ||
1858 | // | |
1859 | // buff macro | |
1860 | // | |
1861 | // | |
1862 | ||
1863 | ||
1864 | ||
1865 | ||
1866 | ||
1867 | module l2t_ique_dp_buff_macro__dbuff_32x__stack_66c__width_66 ( | |
1868 | din, | |
1869 | dout); | |
1870 | input [65:0] din; | |
1871 | output [65:0] dout; | |
1872 | ||
1873 | ||
1874 | ||
1875 | ||
1876 | ||
1877 | ||
1878 | buff #(66) d0_0 ( | |
1879 | .in(din[65:0]), | |
1880 | .out(dout[65:0]) | |
1881 | ); | |
1882 | ||
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | ||
1890 | endmodule | |
1891 | ||
1892 | ||
1893 | ||
1894 | ||
1895 | ||
1896 | // | |
1897 | // and macro for ports = 2,3,4 | |
1898 | // | |
1899 | // | |
1900 | ||
1901 | ||
1902 | ||
1903 | ||
1904 | ||
1905 | module l2t_ique_dp_and_macro__width_1 ( | |
1906 | din0, | |
1907 | din1, | |
1908 | dout); | |
1909 | input [0:0] din0; | |
1910 | input [0:0] din1; | |
1911 | output [0:0] dout; | |
1912 | ||
1913 | ||
1914 | ||
1915 | ||
1916 | ||
1917 | ||
1918 | and2 #(1) d0_0 ( | |
1919 | .in0(din0[0:0]), | |
1920 | .in1(din1[0:0]), | |
1921 | .out(dout[0:0]) | |
1922 | ); | |
1923 | ||
1924 | ||
1925 | ||
1926 | ||
1927 | ||
1928 | ||
1929 | ||
1930 | ||
1931 | ||
1932 | endmodule | |
1933 | ||
1934 | ||
1935 | ||
1936 | ||
1937 | ||
1938 | // | |
1939 | // or macro for ports = 2,3 | |
1940 | // | |
1941 | // | |
1942 | ||
1943 | ||
1944 | ||
1945 | ||
1946 | ||
1947 | module l2t_ique_dp_or_macro__width_1 ( | |
1948 | din0, | |
1949 | din1, | |
1950 | dout); | |
1951 | input [0:0] din0; | |
1952 | input [0:0] din1; | |
1953 | output [0:0] dout; | |
1954 | ||
1955 | ||
1956 | ||
1957 | ||
1958 | ||
1959 | ||
1960 | or2 #(1) d0_0 ( | |
1961 | .in0(din0[0:0]), | |
1962 | .in1(din1[0:0]), | |
1963 | .out(dout[0:0]) | |
1964 | ); | |
1965 | ||
1966 | ||
1967 | ||
1968 | ||
1969 | ||
1970 | ||
1971 | ||
1972 | ||
1973 | ||
1974 | endmodule | |
1975 | ||
1976 | ||
1977 | ||
1978 | ||
1979 | ||
1980 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1981 | // also for pass-gate with decoder | |
1982 | ||
1983 | ||
1984 | ||
1985 | ||
1986 | ||
1987 | // any PARAMS parms go into naming of macro | |
1988 | ||
1989 | module l2t_ique_dp_mux_macro__dmux_16x__mux_pgpe__ports_4__width_32 ( | |
1990 | din0, | |
1991 | din1, | |
1992 | din2, | |
1993 | din3, | |
1994 | sel0, | |
1995 | sel1, | |
1996 | sel2, | |
1997 | muxtst, | |
1998 | test, | |
1999 | dout); | |
2000 | wire psel0; | |
2001 | wire psel1; | |
2002 | wire psel2; | |
2003 | wire psel3; | |
2004 | ||
2005 | input [31:0] din0; | |
2006 | input [31:0] din1; | |
2007 | input [31:0] din2; | |
2008 | input [31:0] din3; | |
2009 | input sel0; | |
2010 | input sel1; | |
2011 | input sel2; | |
2012 | input muxtst; | |
2013 | input test; | |
2014 | output [31:0] dout; | |
2015 | ||
2016 | ||
2017 | ||
2018 | ||
2019 | ||
2020 | cl_dp1_penc4_8x c0_0 ( | |
2021 | .sel0(sel0), | |
2022 | .sel1(sel1), | |
2023 | .sel2(sel2), | |
2024 | .psel0(psel0), | |
2025 | .psel1(psel1), | |
2026 | .psel2(psel2), | |
2027 | .psel3(psel3), | |
2028 | .test(test) | |
2029 | ); | |
2030 | ||
2031 | mux4 #(32) d0_0 ( | |
2032 | .sel0(psel0), | |
2033 | .sel1(psel1), | |
2034 | .sel2(psel2), | |
2035 | .sel3(psel3), | |
2036 | .in0(din0[31:0]), | |
2037 | .in1(din1[31:0]), | |
2038 | .in2(din2[31:0]), | |
2039 | .in3(din3[31:0]), | |
2040 | .dout(dout[31:0]), | |
2041 | .muxtst(muxtst) | |
2042 | ); | |
2043 | ||
2044 | ||
2045 | ||
2046 | ||
2047 | ||
2048 | ||
2049 | ||
2050 | ||
2051 | ||
2052 | ||
2053 | ||
2054 | ||
2055 | ||
2056 | endmodule | |
2057 | ||
2058 | ||
2059 | ||
2060 | ||
2061 | ||
2062 | ||
2063 | // any PARAMS parms go into naming of macro | |
2064 | ||
2065 | module l2t_ique_dp_msff_macro__dmsff_32x__stack_66c__width_50 ( | |
2066 | din, | |
2067 | clk, | |
2068 | en, | |
2069 | se, | |
2070 | scan_in, | |
2071 | siclk, | |
2072 | soclk, | |
2073 | pce_ov, | |
2074 | stop, | |
2075 | dout, | |
2076 | scan_out); | |
2077 | wire l1clk; | |
2078 | wire siclk_out; | |
2079 | wire soclk_out; | |
2080 | wire [48:0] so; | |
2081 | ||
2082 | input [49:0] din; | |
2083 | ||
2084 | ||
2085 | input clk; | |
2086 | input en; | |
2087 | input se; | |
2088 | input scan_in; | |
2089 | input siclk; | |
2090 | input soclk; | |
2091 | input pce_ov; | |
2092 | input stop; | |
2093 | ||
2094 | ||
2095 | ||
2096 | output [49:0] dout; | |
2097 | ||
2098 | ||
2099 | output scan_out; | |
2100 | ||
2101 | ||
2102 | ||
2103 | ||
2104 | cl_dp1_l1hdr_8x c0_0 ( | |
2105 | .l2clk(clk), | |
2106 | .pce(en), | |
2107 | .aclk(siclk), | |
2108 | .bclk(soclk), | |
2109 | .l1clk(l1clk), | |
2110 | .se(se), | |
2111 | .pce_ov(pce_ov), | |
2112 | .stop(stop), | |
2113 | .siclk_out(siclk_out), | |
2114 | .soclk_out(soclk_out) | |
2115 | ); | |
2116 | dff #(50) d0_0 ( | |
2117 | .l1clk(l1clk), | |
2118 | .siclk(siclk_out), | |
2119 | .soclk(soclk_out), | |
2120 | .d(din[49:0]), | |
2121 | .si({scan_in,so[48:0]}), | |
2122 | .so({so[48:0],scan_out}), | |
2123 | .q(dout[49:0]) | |
2124 | ); | |
2125 | ||
2126 | ||
2127 | ||
2128 | ||
2129 | ||
2130 | ||
2131 | ||
2132 | ||
2133 | ||
2134 | ||
2135 | ||
2136 | ||
2137 | ||
2138 | ||
2139 | ||
2140 | ||
2141 | ||
2142 | ||
2143 | ||
2144 | ||
2145 | endmodule | |
2146 | ||
2147 | ||
2148 | ||
2149 | ||
2150 | ||
2151 | ||
2152 | ||
2153 | ||
2154 | ||
2155 | // | |
2156 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
2157 | // | |
2158 | // | |
2159 | ||
2160 | ||
2161 | ||
2162 | ||
2163 | ||
2164 | module l2t_ique_dp_cmp_macro__dcmp_8x__width_32 ( | |
2165 | din0, | |
2166 | din1, | |
2167 | dout); | |
2168 | input [31:0] din0; | |
2169 | input [31:0] din1; | |
2170 | output dout; | |
2171 | ||
2172 | ||
2173 | ||
2174 | ||
2175 | ||
2176 | ||
2177 | cmp #(32) m0_0 ( | |
2178 | .in0(din0[31:0]), | |
2179 | .in1(din1[31:0]), | |
2180 | .out(dout) | |
2181 | ); | |
2182 | ||
2183 | ||
2184 | ||
2185 | ||
2186 | ||
2187 | ||
2188 | ||
2189 | ||
2190 | ||
2191 | ||
2192 | endmodule | |
2193 | ||
2194 | ||
2195 | ||
2196 | ||
2197 | ||
2198 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2199 | // also for pass-gate with decoder | |
2200 | ||
2201 | ||
2202 | ||
2203 | ||
2204 | ||
2205 | // any PARAMS parms go into naming of macro | |
2206 | ||
2207 | module l2t_ique_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 ( | |
2208 | din0, | |
2209 | sel0, | |
2210 | din1, | |
2211 | sel1, | |
2212 | dout); | |
2213 | wire buffout0; | |
2214 | wire buffout1; | |
2215 | ||
2216 | input [0:0] din0; | |
2217 | input sel0; | |
2218 | input [0:0] din1; | |
2219 | input sel1; | |
2220 | output [0:0] dout; | |
2221 | ||
2222 | ||
2223 | ||
2224 | ||
2225 | ||
2226 | cl_dp1_muxbuff2_8x c0_0 ( | |
2227 | .in0(sel0), | |
2228 | .in1(sel1), | |
2229 | .out0(buffout0), | |
2230 | .out1(buffout1) | |
2231 | ); | |
2232 | mux2s #(1) d0_0 ( | |
2233 | .sel0(buffout0), | |
2234 | .sel1(buffout1), | |
2235 | .in0(din0[0:0]), | |
2236 | .in1(din1[0:0]), | |
2237 | .dout(dout[0:0]) | |
2238 | ); | |
2239 | ||
2240 | ||
2241 | ||
2242 | ||
2243 | ||
2244 | ||
2245 | ||
2246 | ||
2247 | ||
2248 | ||
2249 | ||
2250 | ||
2251 | ||
2252 | endmodule | |
2253 |