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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_mb2_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_mb2_ctl ( | |
36 | mb2_l2t_run, | |
37 | mb2_l2t_addr, | |
38 | mb2_l2t_wdata, | |
39 | mb2_l2t_mbtag_wr_en, | |
40 | mb2_l2t_mbtag_rd_en, | |
41 | mb2_l2t_mbtag_lookup_en, | |
42 | mb2_l2t_fbtag_wr_en, | |
43 | mb2_l2t_fbtag_rd_en, | |
44 | mb2_l2t_fbtag_lookup_en, | |
45 | mb2_l2t_wbtag_wr_en, | |
46 | mb2_l2t_wbtag_rd_en, | |
47 | mb2_l2t_wbtag_lookup_en, | |
48 | mb2_l2t_rdmatag_wr_en, | |
49 | mb2_l2t_rdmatag_rd_en, | |
50 | mb2_l2t_rdmatag_lookup_en, | |
51 | cam_mb2_rw_fail, | |
52 | cam_mb2_cam_fail, | |
53 | mbist_cam_sel, | |
54 | mb2_cmp_sel, | |
55 | mb2_l2t_wk1_cam_init, | |
56 | mb2_l2t_wk1_cam_shift, | |
57 | mbdata_mb2_rw_fail, | |
58 | mb2_l2t_mbdata_wr_en, | |
59 | mb2_l2t_mbdata_rd_en, | |
60 | iqarray_mb2_rw_fail, | |
61 | mb2_l2t_iqarray_wr_en, | |
62 | mb2_l2t_iqarray_rd_en, | |
63 | scan_out, | |
64 | l2t_mb2_done, | |
65 | l2t_mb2_fail, | |
66 | l2clk, | |
67 | scan_in, | |
68 | tcu_pce_ov, | |
69 | tcu_aclk, | |
70 | tcu_bclk, | |
71 | tcu_scan_en, | |
72 | tcu_clk_stop, | |
73 | mbist_start, | |
74 | mbist_bisi_mode, | |
75 | mbist_user_mode); | |
76 | wire pce_ov; | |
77 | wire stop; | |
78 | wire siclk; | |
79 | wire soclk; | |
80 | wire se; | |
81 | wire l1clk; | |
82 | wire clock_enable; | |
83 | wire start_in; | |
84 | wire l1clk_pm1; | |
85 | wire array_usr_reg_scanin; | |
86 | wire array_usr_reg_scanout; | |
87 | wire [3:0] user_array_sel_in; | |
88 | wire [3:0] user_array_sel; | |
89 | wire user_addr_mode_reg_scanin; | |
90 | wire user_addr_mode_reg_scanout; | |
91 | wire user_addr_mode_in; | |
92 | wire user_addr_mode; | |
93 | wire user_start_addr_reg_scanin; | |
94 | wire user_start_addr_reg_scanout; | |
95 | wire [4:0] user_start_addr_in; | |
96 | wire [4:0] user_start_addr; | |
97 | wire user_stop_addr_reg_scanin; | |
98 | wire user_stop_addr_reg_scanout; | |
99 | wire [4:0] user_stop_addr_in; | |
100 | wire [4:0] user_stop_addr; | |
101 | wire user_incr_addr_reg_scanin; | |
102 | wire user_incr_addr_reg_scanout; | |
103 | wire [4:0] user_incr_addr_in; | |
104 | wire [4:0] user_incr_addr; | |
105 | wire user_data_mode_reg_scanin; | |
106 | wire user_data_mode_reg_scanout; | |
107 | wire user_data_mode_in; | |
108 | wire user_data_mode; | |
109 | wire user_data_reg_scanin; | |
110 | wire user_data_reg_scanout; | |
111 | wire [7:0] user_data_in; | |
112 | wire [7:0] user_data; | |
113 | wire user_cmpsel_hold_reg_scanin; | |
114 | wire user_cmpsel_hold_reg_scanout; | |
115 | wire user_cmpsel_hold_in; | |
116 | wire user_cmpsel_hold; | |
117 | wire user_cmpsel_reg_scanin; | |
118 | wire user_cmpsel_reg_scanout; | |
119 | wire [3:0] user_cmpsel_in; | |
120 | wire [3:0] user_cmpsel; | |
121 | wire user_loop_mode_reg_scanin; | |
122 | wire user_loop_mode_reg_scanout; | |
123 | wire user_loop_mode_in; | |
124 | wire user_loop_mode; | |
125 | wire ten_n_mode_reg_scanin; | |
126 | wire ten_n_mode_reg_scanout; | |
127 | wire ten_n_mode_in; | |
128 | wire ten_n_mode; | |
129 | wire user_cam_mode_reg_scanin; | |
130 | wire user_cam_mode_reg_scanout; | |
131 | wire user_cam_mode_in; | |
132 | wire user_cam_mode; | |
133 | wire user_cam_select_reg_scanin; | |
134 | wire user_cam_select_reg_scanout; | |
135 | wire [1:0] user_cam_sel_in; | |
136 | wire [1:0] user_cam_sel; | |
137 | wire user_cam_test_select_reg_scanin; | |
138 | wire user_cam_test_select_reg_scanout; | |
139 | wire [1:0] user_cam_test_sel_in; | |
140 | wire [1:0] user_cam_test_sel; | |
141 | wire input_signals_reg_scanin; | |
142 | wire input_signals_reg_scanout; | |
143 | wire bisi_mode; | |
144 | wire user_mode; | |
145 | wire mb_enable_reg_scanin; | |
146 | wire mb_enable_reg_scanout; | |
147 | wire mb_enable; | |
148 | wire mb_enable_out; | |
149 | wire start; | |
150 | wire config_reg_scanin; | |
151 | wire config_reg_scanout; | |
152 | wire [1:0] config_in; | |
153 | wire [1:0] config_out; | |
154 | wire start_transition; | |
155 | wire end_transition; | |
156 | wire reset_engine; | |
157 | wire loop_again; | |
158 | wire run; | |
159 | wire loop_again_reg_scanin; | |
160 | wire loop_again_reg_scanout; | |
161 | wire stop_engine_l; | |
162 | wire stop_engine_l_q; | |
163 | wire cam_cntl_reg_scanin; | |
164 | wire cam_cntl_reg_scanout; | |
165 | wire [14:0] cam_in; | |
166 | wire [14:0] cam_out; | |
167 | wire cam_shift_reg_scanin; | |
168 | wire cam_shift_reg_scanout; | |
169 | wire cam_shift_val; | |
170 | wire cam_shift; | |
171 | wire cam_shift_d1; | |
172 | wire cam_msb; | |
173 | wire [1:0] cam_array_sel; | |
174 | wire last_cam; | |
175 | wire [1:0] ctest; | |
176 | wire mb_user_cam_mode; | |
177 | wire [1:0] cam_cseq; | |
178 | wire sel_cseq_pass; | |
179 | wire [5:0] cam_addr; | |
180 | wire ctest2_out; | |
181 | wire cseq0_out; | |
182 | wire cam_0; | |
183 | wire cam_1; | |
184 | wire cam_2; | |
185 | wire cam_3; | |
186 | wire [1:0] cam_crw; | |
187 | wire sel_crw_pass; | |
188 | wire [1:0] crw; | |
189 | wire ctest0; | |
190 | wire ctest1; | |
191 | wire cseq1; | |
192 | wire ctest2; | |
193 | wire ctest3; | |
194 | wire cseq0; | |
195 | wire cambist; | |
196 | wire [1:0] ctest_sel; | |
197 | wire [1:0] cseq; | |
198 | wire cseq2; | |
199 | wire crw0; | |
200 | wire crw1; | |
201 | wire crw2; | |
202 | wire cam_wr_en; | |
203 | wire run3; | |
204 | wire cam_en; | |
205 | wire cam_zero; | |
206 | wire end_shift_d1; | |
207 | wire [7:0] cam_data; | |
208 | wire cam_walk1; | |
209 | wire end_shift; | |
210 | wire end_shift_delay_reg_scanin; | |
211 | wire end_shift_delay_reg_scanout; | |
212 | wire [14:0] qual_cam; | |
213 | wire mb_cam0_hit; | |
214 | wire [3:0] mb_cam_sel_d3; | |
215 | wire mb_cam1_hit; | |
216 | wire mb_cam2_hit; | |
217 | wire mb_cam3_hit; | |
218 | wire cam_hit_reg_scanin; | |
219 | wire cam_hit_reg_scanout; | |
220 | wire cam0_hit; | |
221 | wire cam1_hit; | |
222 | wire cam2_hit; | |
223 | wire cam3_hit; | |
224 | wire exp_cam_hit_delay_reg_scanin; | |
225 | wire exp_cam_hit_delay_reg_scanout; | |
226 | wire cam_hit_cmp; | |
227 | wire cam_hit_cmp_d1; | |
228 | wire cam_hit_cmp_d2; | |
229 | wire cam_hit_cmp_d3; | |
230 | wire cam_hit_cmp_d4; | |
231 | wire cam_hit_cmp_d5; | |
232 | wire cam_hit_cmp_d6; | |
233 | wire cam_hit_cmp_d7; | |
234 | wire cam_hit_cmp_d8; | |
235 | wire exp_cam_exp_delay_reg_scanin; | |
236 | wire exp_cam_exp_delay_reg_scanout; | |
237 | wire cam_hit_exp; | |
238 | wire cam_hit_exp_d1; | |
239 | wire cam_hit_exp_d2; | |
240 | wire cam_hit_exp_d3; | |
241 | wire cam_hit_exp_d4; | |
242 | wire cam_hit_exp_d5; | |
243 | wire cam_hit_exp_d6; | |
244 | wire cam_hit_exp_d7; | |
245 | wire cam_hit_exp_d8; | |
246 | wire cam0_pass; | |
247 | wire cam1_pass; | |
248 | wire cam2_pass; | |
249 | wire cam3_pass; | |
250 | wire cam0_fail; | |
251 | wire [3:0] mb_cam_sel_d4; | |
252 | wire cam1_fail; | |
253 | wire cam2_fail; | |
254 | wire cam3_fail; | |
255 | wire cam_sel_delay_reg_scanin; | |
256 | wire cam_sel_delay_reg_scanout; | |
257 | wire [3:0] mb_cam_sel_d1; | |
258 | wire [3:0] mb_cam_sel_d2; | |
259 | wire cntl_msb; | |
260 | wire mb_user_ram_mode; | |
261 | wire valid_fail; | |
262 | wire [1:0] cam_sel; | |
263 | wire d_mbtag_lookup_en; | |
264 | wire d_fbtag_lookup_en; | |
265 | wire d_wbtag_lookup_en; | |
266 | wire d_rdmatag_lookup_en; | |
267 | wire [3:0] d_mbist_cam_sel; | |
268 | wire array_0; | |
269 | wire array_1; | |
270 | wire array_2; | |
271 | wire array_3; | |
272 | wire mbist_output_reg_scanin; | |
273 | wire mbist_output_reg_scanout; | |
274 | wire [3:0] d_cam_sel_delay1; | |
275 | wire mbist_output_delay1_reg_scanin; | |
276 | wire mbist_output_delay1_reg_scanout; | |
277 | wire cntl_reg_scanin; | |
278 | wire cntl_reg_scanout; | |
279 | wire [35:0] cntl_in; | |
280 | wire [35:0] cntl_out; | |
281 | wire [16:0] cntl_algr; | |
282 | wire [16:0] next_algr; | |
283 | wire sel_nextaddr_reset; | |
284 | wire sel_nextaddr_restart; | |
285 | wire overflow; | |
286 | wire sel_nextaddr_incred; | |
287 | wire cout_rw; | |
288 | wire sel_nextaddr_same; | |
289 | wire [4:0] start_addr; | |
290 | wire [4:0] restart_addr; | |
291 | wire [4:0] incred_addr; | |
292 | wire [4:0] cntl_addr; | |
293 | wire [2:0] cntl_rw; | |
294 | wire [2:0] next_rw; | |
295 | wire cntl_bisi; | |
296 | wire mb_default_bisi; | |
297 | wire mb_user_bisi_rw_mode; | |
298 | wire [3:0] cntl_array_sel; | |
299 | wire last_array; | |
300 | wire [3:0] cntl_cmp_sel; | |
301 | wire sel_cmp_pass; | |
302 | wire [1:0] cntl_data_sel; | |
303 | wire mb_user_data_mode; | |
304 | wire cntl_addr_mix; | |
305 | wire mb_user_addr_mode; | |
306 | wire [3:0] cntl_march_element; | |
307 | wire sel_march_1_pass; | |
308 | wire addr_mix; | |
309 | wire cout_addr; | |
310 | wire upaddr; | |
311 | wire march_0; | |
312 | wire march_1; | |
313 | wire march_2; | |
314 | wire march_6; | |
315 | wire march_7; | |
316 | wire [3:0] march_element_pre; | |
317 | wire march_pre_0; | |
318 | wire march_pre_1; | |
319 | wire march_pre_2; | |
320 | wire march_pre_6; | |
321 | wire march_pre_7; | |
322 | wire upaddr_pre; | |
323 | wire [4:0] incr_addr; | |
324 | wire [4:0] stop_addr; | |
325 | wire sel_rw_pass; | |
326 | wire one_cycle_march; | |
327 | wire march_5; | |
328 | wire five_cycle_march; | |
329 | wire march_8; | |
330 | wire two_cycle_march; | |
331 | wire mem_wr_pbi; | |
332 | wire march_3; | |
333 | wire march_4; | |
334 | wire rw_1; | |
335 | wire rw_0; | |
336 | wire rw_4; | |
337 | wire mem_wr; | |
338 | wire bisi_wr_mode; | |
339 | wire bisi_rd_mode; | |
340 | wire mem_rd_pbi; | |
341 | wire mem_rd; | |
342 | wire [4:0] adj_addr; | |
343 | wire rw_3; | |
344 | wire [4:0] mem_addr1; | |
345 | wire true_data_l; | |
346 | wire rw_2; | |
347 | wire true_data; | |
348 | wire [7:0] data_pat_sel; | |
349 | wire [7:0] mem_data; | |
350 | wire array_4; | |
351 | wire array_5; | |
352 | wire [4:0] mem_addr; | |
353 | wire [3:0] array_sel; | |
354 | wire cmp_0; | |
355 | wire [3:0] cmp_sel; | |
356 | wire cmp_3; | |
357 | wire [3:0] march_element; | |
358 | wire [2:0] rw; | |
359 | wire [1:0] cam_sel_cntl_out; | |
360 | wire [1:0] ctest_sel_cntl_out; | |
361 | wire [1:0] cseq_cntl_out; | |
362 | wire cseq_reg_scanin; | |
363 | wire cseq_reg_scanout; | |
364 | wire [1:0] cseq_out; | |
365 | wire [3:0] array_sel_cntl_out; | |
366 | wire array_sel_reg_scanin; | |
367 | wire array_sel_reg_scanout; | |
368 | wire [3:0] array_sel_out; | |
369 | wire [3:0] cmp_sel_cntl_out; | |
370 | wire cmp_sel_reg_scanin; | |
371 | wire cmp_sel_reg_scanout; | |
372 | wire [3:0] cmp_sel_out; | |
373 | wire mb_user_cmpsel_hold; | |
374 | wire [3:0] march_element_cntl_out; | |
375 | wire marche_element_reg_scanin; | |
376 | wire marche_element_reg_scanout; | |
377 | wire [3:0] march_element_out; | |
378 | wire mb_user_bisi_wr_mode; | |
379 | wire mb_user_bisi_rd_mode; | |
380 | wire sel_rw_1_pass; | |
381 | wire sel_rw_2_pass; | |
382 | wire sel_rw_5_pass; | |
383 | wire user_bisi_wr_mode_reg_scanin; | |
384 | wire user_bisi_wr_mode_reg_scanout; | |
385 | wire user_bisi_wr_mode_in; | |
386 | wire user_bisi_wr_mode; | |
387 | wire user_bisi_rd_mode_reg_scanin; | |
388 | wire user_bisi_rd_mode_reg_scanout; | |
389 | wire user_bisi_rd_mode_in; | |
390 | wire user_bisi_rd_mode; | |
391 | wire mb_user_loop_mode; | |
392 | wire [3:0] mb_cmp_sel; | |
393 | wire [4:0] mb_addr; | |
394 | wire [7:0] mb_write_data; | |
395 | wire mb_array_0_rd; | |
396 | wire mb_array_1_rd; | |
397 | wire mb_array_2_rd; | |
398 | wire mb_array_3_rd; | |
399 | wire mb_array_4_rd; | |
400 | wire mb_array_5_rd; | |
401 | wire mb_array_0_wr; | |
402 | wire mb_array_1_wr; | |
403 | wire mb_array_2_wr; | |
404 | wire mb_array_3_wr; | |
405 | wire mb_array_4_wr; | |
406 | wire mb_array_5_wr; | |
407 | wire mb_run; | |
408 | wire [4:0] done_delay; | |
409 | wire msb_latch_scanin; | |
410 | wire msb_latch_scanout; | |
411 | wire msb_in; | |
412 | wire msb_out; | |
413 | wire mb_done; | |
414 | wire run3_transition_reg_scanin; | |
415 | wire run3_transition_reg_scanout; | |
416 | wire run3_out; | |
417 | wire run3_transition; | |
418 | wire done_delay_reg_scanin; | |
419 | wire done_delay_reg_scanout; | |
420 | wire [4:0] done_delay_in; | |
421 | wire mb_mbdata_mb2_rw_fail; | |
422 | wire mb_iqarray_mb2_rw_fail; | |
423 | wire mb_mb_fb_wb_rdma_mb2_rw_fail; | |
424 | wire mb_fb_wb_rdma_fail_d; | |
425 | wire mb_fb_wb_rdma_mb2_rw_fail_sticky; | |
426 | wire mbdata_fail_d; | |
427 | wire mbdata_mb2_rw_fail_sticky; | |
428 | wire iqarray_fail_d; | |
429 | wire iqarray_mb2_rw_fail_sticky; | |
430 | wire cam0_fail_d; | |
431 | wire cam0_fail_sticky; | |
432 | wire cam1_fail_d; | |
433 | wire cam1_fail_sticky; | |
434 | wire cam2_fail_d; | |
435 | wire cam2_fail_sticky; | |
436 | wire cam3_fail_d; | |
437 | wire cam3_fail_sticky; | |
438 | wire mbist_fail_input_reg_scanin; | |
439 | wire mbist_fail_input_reg_scanout; | |
440 | wire mbist_fail_sticky; | |
441 | wire mbist_fail_array; | |
442 | wire mb_fail; | |
443 | wire out_mb_tcu_done_reg_scanin; | |
444 | wire out_mb_tcu_done_reg_scanout; | |
445 | wire mb_done_out; | |
446 | wire out_mb_tcu_fail_reg_scanin; | |
447 | wire out_mb_tcu_fail_reg_scanout; | |
448 | wire mb_fail_out; | |
449 | wire out_cmp_sel_reg_scanin; | |
450 | wire out_cmp_sel_reg_scanout; | |
451 | wire [3:0] mb_cmpsel_out; | |
452 | wire out_run_mb_arrays_reg_scanin; | |
453 | wire out_run_mb_arrays_reg_scanout; | |
454 | wire mb_run_out; | |
455 | wire out_data_mb_arrays_reg_scanin; | |
456 | wire out_data_mb_arrays_reg_scanout; | |
457 | wire [7:0] mb_write_data_out; | |
458 | wire out_addr_mb_arrays_reg_scanin; | |
459 | wire out_addr_mb_arrays_reg_scanout; | |
460 | wire [4:0] mb_addr_out; | |
461 | wire out_wr_mb_arrays_reg_scanin; | |
462 | wire out_wr_mb_arrays_reg_scanout; | |
463 | wire mb_array_0_wr_out; | |
464 | wire mb_array_1_wr_out; | |
465 | wire mb_array_2_wr_out; | |
466 | wire mb_array_3_wr_out; | |
467 | wire mb_array_4_wr_out; | |
468 | wire mb_array_5_wr_out; | |
469 | wire out_rd_mb_arrays_reg_scanin; | |
470 | wire out_rd_mb_arrays_reg_scanout; | |
471 | wire mb_array_0_rd_out; | |
472 | wire mb_array_1_rd_out; | |
473 | wire mb_array_2_rd_out; | |
474 | wire mb_array_3_rd_out; | |
475 | wire mb_array_4_rd_out; | |
476 | wire mb_array_5_rd_out; | |
477 | wire spares_scanin; | |
478 | wire spares_scanout; | |
479 | ||
480 | ||
481 | // There are 4 cams and 2 RF's serviced bt this engine. | |
482 | // CAMs: mbtag (32x42bits), fbtag and wbtag (8x40bits), and rdmatag(4x40bits) | |
483 | // Reg Files: mbdata (32x128bits) and iqarray (16x160bits) | |
484 | // The outputs of the 4 CAMs get muxed and the resultant 42 bits get flopped | |
485 | // and routed to the mbist engine. | |
486 | // The read outputs of the mbdata and iqarray all come to mbist engine and | |
487 | // get flopped there. | |
488 | // The current plan is to flop the outputs of mbdata and iqarray inside the | |
489 | // mbist and then mux them with the cam_read_data and generate a 40 bit | |
490 | // read_data to be compared. read_data gets flopped before compare. | |
491 | // ///////////////////////////////////////////////////////////////////////////// | |
492 | // Outputs | |
493 | // ///////////////////////////////////////////////////////////////////////////// | |
494 | ||
495 | ||
496 | ||
497 | ||
498 | output mb2_l2t_run; | |
499 | // output mb2_l2t_cambist; | |
500 | output [4:0] mb2_l2t_addr; | |
501 | output [7:0] mb2_l2t_wdata; | |
502 | output mb2_l2t_mbtag_wr_en; | |
503 | output mb2_l2t_mbtag_rd_en; | |
504 | output mb2_l2t_mbtag_lookup_en; | |
505 | output mb2_l2t_fbtag_wr_en; | |
506 | output mb2_l2t_fbtag_rd_en; | |
507 | output mb2_l2t_fbtag_lookup_en; | |
508 | output mb2_l2t_wbtag_wr_en; | |
509 | output mb2_l2t_wbtag_rd_en; | |
510 | output mb2_l2t_wbtag_lookup_en; | |
511 | output mb2_l2t_rdmatag_wr_en; | |
512 | output mb2_l2t_rdmatag_rd_en; | |
513 | output mb2_l2t_rdmatag_lookup_en; | |
514 | ||
515 | input cam_mb2_rw_fail; | |
516 | input [3:0] cam_mb2_cam_fail; // change signal name to "cam_hit" | |
517 | ||
518 | output [3:0] mbist_cam_sel; // select read data for 0=mb 1=fb 2=wb 3=rdma | |
519 | output [3:0] mb2_cmp_sel; // mux select to pick 1/4 piece of data | |
520 | ||
521 | output mb2_l2t_wk1_cam_init; | |
522 | output mb2_l2t_wk1_cam_shift; | |
523 | ||
524 | // 32x128 and 16x160 rf | |
525 | input mbdata_mb2_rw_fail; | |
526 | output mb2_l2t_mbdata_wr_en; | |
527 | output mb2_l2t_mbdata_rd_en; | |
528 | input iqarray_mb2_rw_fail; | |
529 | output mb2_l2t_iqarray_wr_en; | |
530 | output mb2_l2t_iqarray_rd_en; | |
531 | output scan_out; | |
532 | output l2t_mb2_done; | |
533 | output l2t_mb2_fail; | |
534 | ||
535 | ||
536 | // ///////////////////////////////////////////////////////////////////////////// | |
537 | // Inputs | |
538 | // ///////////////////////////////////////////////////////////////////////////// | |
539 | ||
540 | input l2clk; | |
541 | input scan_in; | |
542 | input tcu_pce_ov; // scan signals | |
543 | input tcu_aclk; | |
544 | input tcu_bclk; | |
545 | input tcu_scan_en; | |
546 | input tcu_clk_stop; | |
547 | ||
548 | input mbist_start; | |
549 | input mbist_bisi_mode; | |
550 | input mbist_user_mode; | |
551 | ||
552 | /////////////////////////////////////////////////////////////////////////////// | |
553 | // Scan Renames | |
554 | /////////////////////////////////////////////////////////////////////////////// | |
555 | ||
556 | assign pce_ov = tcu_pce_ov; | |
557 | assign stop = tcu_clk_stop; | |
558 | assign siclk = tcu_aclk; | |
559 | assign soclk = tcu_bclk; | |
560 | assign se = tcu_scan_en; | |
561 | ||
562 | ||
563 | // TEMP | |
564 | ||
565 | //assign cam_mb2_cam_fail_qual = | |
566 | ||
567 | //////////////////////////////////////////////////////////////////////////////// | |
568 | // Clock header | |
569 | ||
570 | l2t_l1clkhdr_ctl_macro clkgen_freeclk ( | |
571 | .l2clk (l2clk ), | |
572 | .l1en (1'b1 ), | |
573 | .l1clk (l1clk ), | |
574 | .pce_ov(pce_ov), | |
575 | .stop(stop), | |
576 | .se(se)); | |
577 | ||
578 | ||
579 | ||
580 | assign clock_enable = start_in | l2t_mb2_done | mb2_l2t_run | l2t_mb2_fail ; | |
581 | ||
582 | l2t_l1clkhdr_ctl_macro clkgen ( | |
583 | .l2clk (l2clk ), | |
584 | .l1en (clock_enable ), | |
585 | .l1clk (l1clk_pm1 ), | |
586 | .pce_ov(pce_ov), | |
587 | .stop(stop), | |
588 | .se(se) | |
589 | ); | |
590 | ||
591 | ||
592 | ||
593 | // ///////////////////////////////////////////////////////////////////////////// | |
594 | // | |
595 | // user mode resgisters | |
596 | // MBIST PGM Control Register | |
597 | // | |
598 | // ///////////////////////////////////////////////////////////////////////////// | |
599 | // ///////////////////////////////////////////////////////////////////////////// | |
600 | ||
601 | ||
602 | //////////////////////////////////////////////////////////////////////////////// | |
603 | // user control registers | |
604 | // size | |
605 | // - user_array_sel 4 | |
606 | // - user_addr_mode 1 | |
607 | // - user_start_addr 15 | |
608 | // - user_stop_addr 15 | |
609 | // - user_inc_addr 15 | |
610 | // - user_data_mode 1 | |
611 | // - user_data 8 | |
612 | // - user_cmpsel_hold 1 | |
613 | // - user_cmpsel 3 | |
614 | // - user_loop_mode 1 | |
615 | ||
616 | l2t_msff_ctl_macro__width_4 array_usr_reg ( | |
617 | .scan_in(array_usr_reg_scanin), | |
618 | .scan_out(array_usr_reg_scanout), | |
619 | .l1clk ( l1clk_pm1 ), | |
620 | .din ( user_array_sel_in[3:0] ), | |
621 | .dout ( user_array_sel[3:0] ), | |
622 | .siclk(siclk), | |
623 | .soclk(soclk)); | |
624 | ||
625 | assign user_array_sel_in[3:0]=user_array_sel[3:0]; | |
626 | ||
627 | ||
628 | // user address mode | |
629 | ||
630 | l2t_msff_ctl_macro__width_1 user_addr_mode_reg ( | |
631 | .scan_in(user_addr_mode_reg_scanin), | |
632 | .scan_out(user_addr_mode_reg_scanout), | |
633 | .l1clk ( l1clk_pm1 ), | |
634 | .din ( user_addr_mode_in ), | |
635 | .dout ( user_addr_mode ), | |
636 | .siclk(siclk), | |
637 | .soclk(soclk)); | |
638 | ||
639 | assign user_addr_mode_in=user_addr_mode; | |
640 | ||
641 | ||
642 | // user start address | |
643 | ||
644 | l2t_msff_ctl_macro__width_5 user_start_addr_reg ( | |
645 | .scan_in(user_start_addr_reg_scanin), | |
646 | .scan_out(user_start_addr_reg_scanout), | |
647 | .l1clk ( l1clk_pm1 ), | |
648 | .din ( user_start_addr_in[4:0] ), | |
649 | .dout ( user_start_addr[4:0] ), | |
650 | .siclk(siclk), | |
651 | .soclk(soclk)); | |
652 | ||
653 | ||
654 | assign user_start_addr_in[4:0]=user_start_addr[4:0]; | |
655 | ||
656 | // user stop address | |
657 | ||
658 | l2t_msff_ctl_macro__width_5 user_stop_addr_reg ( | |
659 | .scan_in(user_stop_addr_reg_scanin), | |
660 | .scan_out(user_stop_addr_reg_scanout), | |
661 | .l1clk ( l1clk_pm1 ), | |
662 | .din ( user_stop_addr_in[4:0] ), | |
663 | .dout ( user_stop_addr[4:0] ), | |
664 | .siclk(siclk), | |
665 | .soclk(soclk)); | |
666 | ||
667 | ||
668 | assign user_stop_addr_in[4:0]=user_stop_addr[4:0]; | |
669 | ||
670 | ||
671 | // user increment address | |
672 | ||
673 | l2t_msff_ctl_macro__width_5 user_incr_addr_reg ( | |
674 | .scan_in(user_incr_addr_reg_scanin), | |
675 | .scan_out(user_incr_addr_reg_scanout), | |
676 | .l1clk ( l1clk_pm1 ), | |
677 | .din ( user_incr_addr_in[4:0] ), | |
678 | .dout ( user_incr_addr[4:0] ), | |
679 | .siclk(siclk), | |
680 | .soclk(soclk)); | |
681 | ||
682 | ||
683 | assign user_incr_addr_in[4:0]=user_incr_addr[4:0]; | |
684 | ||
685 | // user data mode | |
686 | ||
687 | l2t_msff_ctl_macro__width_1 user_data_mode_reg ( | |
688 | .scan_in(user_data_mode_reg_scanin), | |
689 | .scan_out(user_data_mode_reg_scanout), | |
690 | .l1clk ( l1clk_pm1 ), | |
691 | .din ( user_data_mode_in ), | |
692 | .dout ( user_data_mode ), | |
693 | .siclk(siclk), | |
694 | .soclk(soclk)); | |
695 | ||
696 | ||
697 | assign user_data_mode_in=user_data_mode; | |
698 | ||
699 | // user data select | |
700 | ||
701 | l2t_msff_ctl_macro__width_8 user_data_reg ( | |
702 | .scan_in(user_data_reg_scanin), | |
703 | .scan_out(user_data_reg_scanout), | |
704 | .l1clk ( l1clk_pm1 ), | |
705 | .din ( user_data_in[7:0] ), | |
706 | .dout ( user_data[7:0] ), | |
707 | .siclk(siclk), | |
708 | .soclk(soclk)); | |
709 | ||
710 | ||
711 | assign user_data_in[7:0] = user_data[7:0]; | |
712 | ||
713 | // user cmp sel inc | |
714 | // if its one, user need to program the cmpselinc register | |
715 | // otherwise it will loop all cmpsel | |
716 | ||
717 | l2t_msff_ctl_macro__width_1 user_cmpsel_hold_reg ( | |
718 | .scan_in(user_cmpsel_hold_reg_scanin), | |
719 | .scan_out(user_cmpsel_hold_reg_scanout), | |
720 | .l1clk ( l1clk_pm1 ), | |
721 | .din ( user_cmpsel_hold_in ), | |
722 | .dout ( user_cmpsel_hold ), | |
723 | .siclk(siclk), | |
724 | .soclk(soclk)); | |
725 | ||
726 | ||
727 | assign user_cmpsel_hold_in=user_cmpsel_hold; | |
728 | ||
729 | ||
730 | ||
731 | // user cmp sel reg | |
732 | ||
733 | l2t_msff_ctl_macro__width_4 user_cmpsel_reg ( | |
734 | .scan_in(user_cmpsel_reg_scanin), | |
735 | .scan_out(user_cmpsel_reg_scanout), | |
736 | .l1clk ( l1clk_pm1 ), | |
737 | .din ( user_cmpsel_in[3:0] ), | |
738 | .dout ( user_cmpsel[3:0] ), | |
739 | .siclk(siclk), | |
740 | .soclk(soclk)); | |
741 | ||
742 | assign user_cmpsel_in[3:0]=user_cmpsel[3:0]; | |
743 | ||
744 | ||
745 | // user loop mode | |
746 | ||
747 | l2t_msff_ctl_macro__width_1 user_loop_mode_reg ( | |
748 | .scan_in(user_loop_mode_reg_scanin), | |
749 | .scan_out(user_loop_mode_reg_scanout), | |
750 | .l1clk ( l1clk_pm1 ), | |
751 | .din ( user_loop_mode_in ), | |
752 | .dout ( user_loop_mode ), | |
753 | .siclk(siclk), | |
754 | .soclk(soclk)); | |
755 | ||
756 | ||
757 | assign user_loop_mode_in=user_loop_mode; | |
758 | ||
759 | ||
760 | ||
761 | // 10N Algorithm for bit mapping | |
762 | ||
763 | l2t_msff_ctl_macro__width_1 ten_n_mode_reg ( | |
764 | .scan_in(ten_n_mode_reg_scanin), | |
765 | .scan_out(ten_n_mode_reg_scanout), | |
766 | .l1clk ( l1clk_pm1 ), | |
767 | .din ( ten_n_mode_in ), | |
768 | .dout ( ten_n_mode ), | |
769 | .siclk(siclk), | |
770 | .soclk(soclk)); | |
771 | ||
772 | ||
773 | assign ten_n_mode_in=ten_n_mode; | |
774 | ||
775 | ||
776 | ||
777 | // cambist: user cam select | |
778 | ||
779 | ||
780 | l2t_msff_ctl_macro__width_1 user_cam_mode_reg ( | |
781 | .scan_in(user_cam_mode_reg_scanin), | |
782 | .scan_out(user_cam_mode_reg_scanout), | |
783 | .l1clk ( l1clk_pm1 ), | |
784 | .din ( user_cam_mode_in ), | |
785 | .dout ( user_cam_mode ), | |
786 | .siclk(siclk), | |
787 | .soclk(soclk)); | |
788 | ||
789 | assign user_cam_mode_in=user_cam_mode; | |
790 | ||
791 | ||
792 | l2t_msff_ctl_macro__width_2 user_cam_select_reg ( | |
793 | .scan_in(user_cam_select_reg_scanin), | |
794 | .scan_out(user_cam_select_reg_scanout), | |
795 | .l1clk ( l1clk_pm1 ), | |
796 | .din ( user_cam_sel_in[1:0] ), | |
797 | .dout ( user_cam_sel[1:0] ), | |
798 | .siclk(siclk), | |
799 | .soclk(soclk)); | |
800 | ||
801 | assign user_cam_sel_in[1:0]=user_cam_sel[1:0]; | |
802 | ||
803 | ||
804 | l2t_msff_ctl_macro__width_2 user_cam_test_select_reg ( | |
805 | .scan_in(user_cam_test_select_reg_scanin), | |
806 | .scan_out(user_cam_test_select_reg_scanout), | |
807 | .l1clk ( l1clk_pm1 ), | |
808 | .din ( user_cam_test_sel_in[1:0] ), | |
809 | .dout ( user_cam_test_sel[1:0] ), | |
810 | .siclk(siclk), | |
811 | .soclk(soclk)); | |
812 | ||
813 | assign user_cam_test_sel_in[1:0]=user_cam_test_sel[1:0]; | |
814 | ||
815 | ||
816 | ||
817 | ||
818 | // ///////////////////////////////////////////////////////////////////////////// | |
819 | // | |
820 | // MBIST Config Register | |
821 | // | |
822 | // ///////////////////////////////////////////////////////////////////////////// | |
823 | // | |
824 | // A low to high transition on mbist_start will reset and start the engine. | |
825 | // mbist_start must remain active high for the duration of MBIST. | |
826 | // If mbist_start deasserts the engine will stop but not reset. | |
827 | // Once MBIST has completed mb0_done will assert and the fail status | |
828 | // signals will be valid. | |
829 | // To run MBIST again the mbist_start signal must transition low then high. | |
830 | // | |
831 | // Loop on Address will disable the address mix function. | |
832 | // | |
833 | // ///////////////////////////////////////////////////////////////////////////// | |
834 | ||
835 | ||
836 | // flop incoming signals: | |
837 | ||
838 | l2t_msff_ctl_macro__width_3 input_signals_reg ( | |
839 | .scan_in(input_signals_reg_scanin), | |
840 | .scan_out(input_signals_reg_scanout), | |
841 | .l1clk ( l1clk ), | |
842 | .din ( {mbist_start,mbist_bisi_mode,mbist_user_mode} ), | |
843 | .dout ( {start_in,bisi_mode,user_mode} ), | |
844 | .siclk(siclk), | |
845 | .soclk(soclk)); | |
846 | ||
847 | ||
848 | ||
849 | ||
850 | // default : mb_enable=0 | |
851 | // bisi : mb_enable=0 | |
852 | // user_mode : mb_enable=depend on programmed value | |
853 | ||
854 | l2t_msff_ctl_macro__width_1 mb_enable_reg ( | |
855 | .scan_in(mb_enable_reg_scanin), | |
856 | .scan_out(mb_enable_reg_scanout), | |
857 | .l1clk ( l1clk_pm1 ), | |
858 | .din ( mb_enable ), | |
859 | .dout ( mb_enable_out ), | |
860 | .siclk(siclk), | |
861 | .soclk(soclk)); | |
862 | ||
863 | ||
864 | assign mb_enable = user_mode ? mb_enable_out : 1'b0; | |
865 | ||
866 | ||
867 | assign start = user_mode ? (mb_enable_out & start_in) : | |
868 | (start_in); | |
869 | ||
870 | ||
871 | ||
872 | // 5 cycle delay for the run signal | |
873 | ||
874 | ||
875 | ||
876 | ||
877 | l2t_msff_ctl_macro__width_2 config_reg ( | |
878 | .scan_in(config_reg_scanin), | |
879 | .scan_out(config_reg_scanout), | |
880 | .l1clk ( l1clk_pm1 ), | |
881 | .din ( config_in[1:0] ), | |
882 | .dout ( config_out[1:0] ), | |
883 | .siclk(siclk), | |
884 | .soclk(soclk)); | |
885 | ||
886 | ||
887 | assign config_in[0] = start; | |
888 | assign config_in[1] = config_out[0]; | |
889 | assign start_transition = config_out[0] & ~config_out[1]; | |
890 | assign end_transition = ~config_out[0] & config_out[1]; | |
891 | assign reset_engine = start_transition | loop_again | end_transition; | |
892 | assign run = config_out[1] ; | |
893 | ||
894 | ||
895 | l2t_msff_ctl_macro__width_1 loop_again_reg ( | |
896 | .scan_in(loop_again_reg_scanin), | |
897 | .scan_out(loop_again_reg_scanout), | |
898 | .l1clk ( l1clk_pm1 ), | |
899 | .din ( stop_engine_l ), | |
900 | .dout ( stop_engine_l_q ), | |
901 | .siclk(siclk), | |
902 | .soclk(soclk)); | |
903 | ||
904 | ||
905 | assign loop_again=user_loop_mode ? stop_engine_l & ~stop_engine_l_q: 1'b0; | |
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | // ///////////////////////////////////////////////////////////////////////////// | |
912 | // | |
913 | // CAM BIST: | |
914 | // | |
915 | // ///////////////////////////////////////////////////////////////////////////// | |
916 | ||
917 | // cambistwork: | |
918 | ||
919 | ||
920 | // there are 3 basic tests for the cambist - match0, match1, and walking1 | |
921 | // there are 5 cam register for cambist tests | |
922 | // - cam_msb, cam_array_sel,ctest, cseq, cam_addr, crw | |
923 | // - cam_msb, when this bit is one, it completes the camtest | |
924 | // - cam_array_sel, this register indicates what cam you are testing | |
925 | // - ctest, indicates which 1/3 tests | |
926 | // - cseq, | |
927 | // - cam_addr, | |
928 | // - crw, | |
929 | ||
930 | ||
931 | // - ctest 0: match camdata 0 | |
932 | // - write data 0 ^(W0); | |
933 | // - cam data 0 ^(W0C0RxW1); | |
934 | // this requires (cseq0, cseq1, cseq2, cseq3) | |
935 | // - ctest 1: match camdata 1 | |
936 | // - write data 1 ^(W1); | |
937 | // - camdata 1 ^(W1C1RxW0); | |
938 | // this requires (cseq0, cseq1, cseq2, cseq3) | |
939 | // - ctest 2: walking1 mismatch | |
940 | // - write 0 | |
941 | // - walking 1 | |
942 | // | |
943 | ||
944 | l2t_msff_ctl_macro__width_15 cam_cntl_reg ( | |
945 | .scan_in(cam_cntl_reg_scanin), | |
946 | .scan_out(cam_cntl_reg_scanout), | |
947 | .l1clk ( l1clk_pm1 ), | |
948 | .din ( cam_in[14:0] ), | |
949 | .dout ( cam_out[14:0] ), | |
950 | .siclk(siclk), | |
951 | .soclk(soclk)); | |
952 | ||
953 | ||
954 | l2t_msff_ctl_macro__width_2 cam_shift_reg ( | |
955 | .scan_in(cam_shift_reg_scanin), | |
956 | .scan_out(cam_shift_reg_scanout), | |
957 | .l1clk ( l1clk_pm1 ), | |
958 | .din ( {cam_shift_val,cam_shift}), | |
959 | .dout ( {cam_shift, cam_shift_d1} ), | |
960 | .siclk(siclk), | |
961 | .soclk(soclk)); | |
962 | ||
963 | ||
964 | assign cam_msb = start_in & cam_out[14]; // | |
965 | ||
966 | assign cam_array_sel[1:0] = (last_cam | user_mode) ? 2'b11: | |
967 | cam_out[13:12]; // 2 bits | |
968 | ||
969 | assign ctest[1:0] = mb_user_cam_mode ? 2'b11 : | |
970 | cam_out[11:10]; // | |
971 | ||
972 | assign cam_cseq[1:0] = sel_cseq_pass ? 2'b11 : cam_out[9:8]; | |
973 | ||
974 | // assign cseq[1:0] = cam_out[9:8]; | |
975 | ||
976 | ||
977 | assign cam_addr[5:0] = (ctest2_out & ~cseq0_out) ? cam_out[7:2]: | |
978 | cam_0 ? {1'b1, cam_out[6:2]} : | |
979 | cam_1 ? {3'b111, cam_out[4:2]} : | |
980 | cam_2 ? {3'b111, cam_out[4:2]} : | |
981 | cam_3 ? {4'b1111, cam_out[3:2]} : | |
982 | cam_out[7:2]; | |
983 | ||
984 | // assign cam_crw[1:0] = (cseq0_out) ? 2'b11: | |
985 | // (ctest3_out) ? 2'b11: | |
986 | // cam_out[1:0]; // read write control | |
987 | ||
988 | ||
989 | assign cam_crw[1:0] = sel_crw_pass ? 2'b11: | |
990 | cam_out[1:0]; // read write control | |
991 | ||
992 | ||
993 | // ctest0: | |
994 | // cseq0: camdata | |
995 | // crw0 write 0 | |
996 | // cseq1: | |
997 | // crw0 write 1 | |
998 | // crw1 cam 1 | |
999 | // crw2 write1 0 | |
1000 | // crw3 dead cycle 0 | |
1001 | ||
1002 | // ctest1: | |
1003 | // cseq0: camdata | |
1004 | // crw0 write 1 | |
1005 | // cseq1: | |
1006 | // crw0 write 0 | |
1007 | // crw1 cam 0 | |
1008 | // crw2 write1 1 | |
1009 | // crw3 dead cycle 0 | |
1010 | ||
1011 | ||
1012 | // ctest2: camdata | |
1013 | // cseq0: write 0 | |
1014 | // cseq1-2: walkin1 N/A | |
1015 | // cam_zer0 | |
1016 | // cam_walk1 | |
1017 | ||
1018 | assign crw[1:0]=cam_out[1:0]; | |
1019 | ||
1020 | assign cseq0_out = cam_out[9:8]==2'b00; | |
1021 | assign sel_cseq_pass = ((ctest0 | ctest1) & cseq1) | | |
1022 | (ctest2 & cseq1)| | |
1023 | (ctest3 & cseq1); | |
1024 | ||
1025 | assign sel_crw_pass = ((cseq0 | (ctest2 & cseq1) | (ctest3 & cseq1)) & cambist); | |
1026 | ||
1027 | assign ctest2_out=mb_user_cam_mode ? (ctest_sel[1:0]==2'b10 | ctest_sel[1:0]==2'b11) : | |
1028 | (cam_out[11:10]==2'b10 | cam_out[11:10]==2'b11); | |
1029 | // assign cseq1_out=cam_out[9:8]==2'b01; | |
1030 | ||
1031 | assign ctest0 = ctest_sel[1:0]==2'b00 & cambist; | |
1032 | assign ctest1 = ctest_sel[1:0]==2'b01 & cambist; | |
1033 | assign ctest2 = ctest_sel[1:0]==2'b10 & cambist; | |
1034 | assign ctest3 = ctest_sel[1:0]==2'b11 & cambist; | |
1035 | ||
1036 | assign cseq0 = ~( cseq[1] | cseq[0]); | |
1037 | assign cseq1 = ~( cseq[1] | ~cseq[0]); | |
1038 | assign cseq2 = ~(~cseq[1] | cseq[0]); | |
1039 | // assign cseq3 = ~(~cseq[1] | ~cseq[0]); | |
1040 | ||
1041 | assign crw0 = ~( crw[1] | crw[0]); | |
1042 | assign crw1 = ~( crw[1] | ~crw[0]); | |
1043 | assign crw2 = ~(~crw[1] | crw[0]); | |
1044 | // assign crw3 = ~(~crw[1] | ~crw[0]); | |
1045 | ||
1046 | ||
1047 | // assign cam_wr_en = (ctest1 & cseq0) ? crw3 : | |
1048 | // (ctest1 & cseq1) ? (crw0 | crw2) : | |
1049 | // (ctest2 & cseq0) ? crw3 : | |
1050 | // (ctest2 & cseq1) ? (crw0 | crw2) : | |
1051 | // (ctest3 & cseq0) ? crw3 : | |
1052 | // 1'b0; | |
1053 | ||
1054 | assign cam_wr_en = (cambist & run3) & ((ctest0 & cseq0 & crw0) | | |
1055 | (ctest0 & cseq1 & (crw0 | crw2)) | | |
1056 | (ctest1 & cseq0 & crw0) | | |
1057 | (ctest1 & cseq1 & (crw0 | crw2)) | | |
1058 | (ctest2 & cseq0 & crw0) | | |
1059 | (ctest3 & cseq2 ) | | |
1060 | (ctest3 & cseq0 & crw0)) ; | |
1061 | ||
1062 | // assign cam_en = (ctest1 & cseq1) ? crw1 : | |
1063 | // (ctest2 & cseq1) ? crw1 : | |
1064 | // 1'b0; | |
1065 | ||
1066 | assign cam_en = (ctest0 & cseq1 & crw1) | | |
1067 | (ctest1 & cseq1 & crw1) | | |
1068 | (cam_0 & (cam_shift | cam_zero)) | | |
1069 | ((cam_1 | cam_2 | cam_3) & cam_shift_d1 & ~mb2_l2t_wk1_cam_init & ~end_shift_d1); | |
1070 | ||
1071 | ||
1072 | ||
1073 | // using only the cam_data[0] | |
1074 | ||
1075 | ||
1076 | assign cam_data[7:0] = (ctest0 & cseq1 & (crw0 | crw1)) | | |
1077 | (ctest1 & cseq0) | | |
1078 | (ctest1 & (cseq1 & crw2)) | | |
1079 | (ctest2 & cseq0 ) | | |
1080 | (ctest3 & cseq1 ) ? 8'hFF : 8'h00; | |
1081 | ||
1082 | ||
1083 | assign cam_walk1 = (ctest2 | ctest3); | |
1084 | ||
1085 | // assign end_shift = cam_walk1 & (tlb_addr[6] & tlb_addr[5] & ~tlb_addr[4] & tlb_addr[3] & ~tlb_addr[2] & ~tlb_addr[1] & ~tlb_addr[0]); | |
1086 | ||
1087 | assign cam_zero = ~|cam_addr[5:0] & cam_walk1 & cseq1; | |
1088 | ||
1089 | assign end_shift = cam_0 ? cam_walk1 & ( cam_addr[5:0]==6'd34): | |
1090 | (cam_1 | cam_2 | cam_3) ? cam_walk1 & ( cam_addr[5:0]==6'd34): // width=33 | |
1091 | 1'b0; | |
1092 | ||
1093 | l2t_msff_ctl_macro__width_1 end_shift_delay_reg ( | |
1094 | .scan_in(end_shift_delay_reg_scanin), | |
1095 | .scan_out(end_shift_delay_reg_scanout), | |
1096 | .l1clk ( l1clk_pm1 ), | |
1097 | .din ( end_shift ), | |
1098 | .dout ( end_shift_d1 ), | |
1099 | .siclk(siclk), | |
1100 | .soclk(soclk)); | |
1101 | ||
1102 | ||
1103 | assign cam_shift_val = ~cambist | end_shift ? 1'b0 : | |
1104 | cam_zero & cseq1 ? 1'b1 : | |
1105 | cam_shift; | |
1106 | ||
1107 | ||
1108 | assign qual_cam[14:0]={cam_msb, | |
1109 | cam_array_sel[1:0], | |
1110 | ctest[1:0], | |
1111 | cam_cseq[1:0], | |
1112 | cam_addr[5:0], | |
1113 | cam_crw[1:0]}; | |
1114 | ||
1115 | assign cam_in[14:0]=reset_engine ? 15'b0: // set zero | |
1116 | ~run3 | ~cambist ? qual_cam[14:0]: // save value | |
1117 | qual_cam[14:0]+15'h1; // increment | |
1118 | ||
1119 | ||
1120 | ||
1121 | ||
1122 | assign mb_cam0_hit= cam_mb2_cam_fail[0] & mb_cam_sel_d3[0]; | |
1123 | assign mb_cam1_hit= cam_mb2_cam_fail[1] & mb_cam_sel_d3[1]; | |
1124 | assign mb_cam2_hit= cam_mb2_cam_fail[2] & mb_cam_sel_d3[2]; | |
1125 | assign mb_cam3_hit= cam_mb2_cam_fail[3] & mb_cam_sel_d3[3]; | |
1126 | ||
1127 | ||
1128 | ||
1129 | l2t_msff_ctl_macro__width_4 cam_hit_reg ( | |
1130 | .scan_in(cam_hit_reg_scanin), | |
1131 | .scan_out(cam_hit_reg_scanout), | |
1132 | .l1clk ( l1clk_pm1 ), | |
1133 | .din ( {mb_cam0_hit, mb_cam1_hit, mb_cam2_hit, mb_cam3_hit} ), | |
1134 | .dout ( {cam0_hit, cam1_hit, cam2_hit, cam3_hit} ), | |
1135 | .siclk(siclk), | |
1136 | .soclk(soclk)); | |
1137 | ||
1138 | ||
1139 | l2t_msff_ctl_macro__width_8 exp_cam_hit_delay_reg ( | |
1140 | .scan_in(exp_cam_hit_delay_reg_scanin), | |
1141 | .scan_out(exp_cam_hit_delay_reg_scanout), | |
1142 | .l1clk ( l1clk_pm1 ), | |
1143 | .din ( {cam_hit_cmp, | |
1144 | cam_hit_cmp_d1, | |
1145 | cam_hit_cmp_d2, | |
1146 | cam_hit_cmp_d3, | |
1147 | cam_hit_cmp_d4, | |
1148 | cam_hit_cmp_d5, | |
1149 | cam_hit_cmp_d6, | |
1150 | cam_hit_cmp_d7}), | |
1151 | .dout ( {cam_hit_cmp_d1, | |
1152 | cam_hit_cmp_d2, | |
1153 | cam_hit_cmp_d3, | |
1154 | cam_hit_cmp_d4, | |
1155 | cam_hit_cmp_d5, | |
1156 | cam_hit_cmp_d6, | |
1157 | cam_hit_cmp_d7, | |
1158 | cam_hit_cmp_d8}), | |
1159 | .siclk(siclk), | |
1160 | .soclk(soclk)); | |
1161 | ||
1162 | ||
1163 | l2t_msff_ctl_macro__width_8 exp_cam_exp_delay_reg ( | |
1164 | .scan_in(exp_cam_exp_delay_reg_scanin), | |
1165 | .scan_out(exp_cam_exp_delay_reg_scanout), | |
1166 | .l1clk ( l1clk_pm1 ), | |
1167 | .din ( {cam_hit_exp, | |
1168 | cam_hit_exp_d1, | |
1169 | cam_hit_exp_d2, | |
1170 | cam_hit_exp_d3, | |
1171 | cam_hit_exp_d4, | |
1172 | cam_hit_exp_d5, | |
1173 | cam_hit_exp_d6, | |
1174 | cam_hit_exp_d7}), | |
1175 | .dout ( {cam_hit_exp_d1, | |
1176 | cam_hit_exp_d2, | |
1177 | cam_hit_exp_d3, | |
1178 | cam_hit_exp_d4, | |
1179 | cam_hit_exp_d5, | |
1180 | cam_hit_exp_d6, | |
1181 | cam_hit_exp_d7, | |
1182 | cam_hit_exp_d8}), | |
1183 | .siclk(siclk), | |
1184 | .soclk(soclk)); | |
1185 | ||
1186 | ||
1187 | ||
1188 | assign cam_hit_cmp =cam_en; | |
1189 | ||
1190 | assign cam_hit_exp =(ctest0 & cseq1 & crw1) | | |
1191 | (ctest1 & cseq1 & crw1) ; | |
1192 | ||
1193 | ||
1194 | ||
1195 | ||
1196 | assign cam0_pass = (~cam_hit_cmp_d7) | (cam_hit_cmp_d7 & (cam_hit_exp_d7 == cam0_hit)); | |
1197 | assign cam1_pass = (~cam_hit_cmp_d8) | (cam_hit_cmp_d8 & (cam_hit_exp_d8 == cam1_hit)); | |
1198 | assign cam2_pass = (~cam_hit_cmp_d8) | (cam_hit_cmp_d8 & (cam_hit_exp_d8 == cam2_hit)); | |
1199 | assign cam3_pass = (~cam_hit_cmp_d8) | (cam_hit_cmp_d8 & (cam_hit_exp_d8 == cam3_hit)); | |
1200 | ||
1201 | ||
1202 | assign cam0_fail = ~cam0_pass & mb_cam_sel_d4[0]; | |
1203 | assign cam1_fail = ~cam1_pass & mb_cam_sel_d4[1]; | |
1204 | assign cam2_fail = ~cam2_pass & mb_cam_sel_d4[2]; | |
1205 | assign cam3_fail = ~cam3_pass & mb_cam_sel_d4[3]; | |
1206 | ||
1207 | ||
1208 | l2t_msff_ctl_macro__width_16 cam_sel_delay_reg ( | |
1209 | .scan_in(cam_sel_delay_reg_scanin), | |
1210 | .scan_out(cam_sel_delay_reg_scanout), | |
1211 | .l1clk ( l1clk_pm1 ), | |
1212 | .din ( {mbist_cam_sel[3:0],mb_cam_sel_d1[3:0],mb_cam_sel_d2[3:0],mb_cam_sel_d3[3:0]}), | |
1213 | .dout ( {mb_cam_sel_d1[3:0],mb_cam_sel_d2[3:0],mb_cam_sel_d3[3:0],mb_cam_sel_d4[3:0]}), | |
1214 | .siclk(siclk), | |
1215 | .soclk(soclk)); | |
1216 | ||
1217 | ||
1218 | // don't know that this logic is for ?? | |
1219 | // | |
1220 | // assign mb2_cam_fail=|(cam_mb2_cam_fail[3:0]); | |
1221 | // assign cam_pass = (mb2_cam_fail & (ctest0 | ctest1) & (cseq1 & crw1)) | | |
1222 | // ~((ctest2|ctest3) & cam_shift); | |
1223 | ||
1224 | // assign cam_fail= ~cam_pass; | |
1225 | ||
1226 | ||
1227 | //////////////////////////////////////////////////////////////////////////////// | |
1228 | // array selection | |
1229 | //////////////////////////////////////////////////////////////////////////////// | |
1230 | ||
1231 | ||
1232 | assign cambist = ((mb_user_cam_mode | (cntl_msb & ~bisi_mode)) & (~mb_user_ram_mode & valid_fail)); | |
1233 | ||
1234 | assign cam_0 = ~( cam_sel[1] | cam_sel[0]) & cambist; | |
1235 | assign cam_1 = ~( cam_sel[1] | ~cam_sel[0]) & cambist; | |
1236 | assign cam_2 = ~( ~cam_sel[1] | cam_sel[0]) & cambist; | |
1237 | assign cam_3 = ~( ~cam_sel[1] | ~cam_sel[0]) & cambist; | |
1238 | assign last_cam = cam_3; | |
1239 | ||
1240 | ||
1241 | ||
1242 | //assign d_mbtag_lookup_en = cam_0 & (cam_en | cam_shift); | |
1243 | //assign d_fbtag_lookup_en = cam_1 & (cam_en | cam_shift); | |
1244 | //assign d_wbtag_lookup_en = cam_2 & (cam_en | cam_shift); | |
1245 | //assign d_rdmatag_lookup_en= cam_3 & (cam_en | cam_shift); | |
1246 | ||
1247 | ||
1248 | assign d_mbtag_lookup_en = cam_0 & cam_en; | |
1249 | assign d_fbtag_lookup_en = cam_1 & cam_en; | |
1250 | assign d_wbtag_lookup_en = cam_2 & cam_en; | |
1251 | assign d_rdmatag_lookup_en= cam_3 & cam_en; | |
1252 | ||
1253 | ||
1254 | assign d_mbist_cam_sel[0]=array_0 | cam_0; // mbtag | |
1255 | assign d_mbist_cam_sel[1]=array_1 | cam_1; // fbtag | |
1256 | assign d_mbist_cam_sel[2]=array_2 | cam_2; // wbtag | |
1257 | assign d_mbist_cam_sel[3]=array_3 | cam_3; // rdma | |
1258 | ||
1259 | ||
1260 | // CAM | |
1261 | // removed the mb2_l2t_cambist signal | |
1262 | ||
1263 | l2t_msff_ctl_macro__width_10 mbist_output_reg ( | |
1264 | .scan_in(mbist_output_reg_scanin), | |
1265 | .scan_out(mbist_output_reg_scanout), | |
1266 | .l1clk ( l1clk_pm1 ), | |
1267 | .din ({ | |
1268 | // cambist, | |
1269 | d_mbtag_lookup_en, | |
1270 | d_fbtag_lookup_en, | |
1271 | d_wbtag_lookup_en, | |
1272 | d_rdmatag_lookup_en, | |
1273 | d_mbist_cam_sel[3:0], | |
1274 | cam_zero, | |
1275 | cam_shift | |
1276 | }), // done | |
1277 | .dout ({ | |
1278 | // mb2_l2t_cambist, | |
1279 | mb2_l2t_mbtag_lookup_en, | |
1280 | mb2_l2t_fbtag_lookup_en, | |
1281 | mb2_l2t_wbtag_lookup_en, | |
1282 | mb2_l2t_rdmatag_lookup_en, | |
1283 | d_cam_sel_delay1[3:0], | |
1284 | mb2_l2t_wk1_cam_init, | |
1285 | mb2_l2t_wk1_cam_shift | |
1286 | }), | |
1287 | .siclk(siclk), | |
1288 | .soclk(soclk)); | |
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | // CAM | |
1294 | l2t_msff_ctl_macro__width_4 mbist_output_delay1_reg ( | |
1295 | .scan_in(mbist_output_delay1_reg_scanin), | |
1296 | .scan_out(mbist_output_delay1_reg_scanout), | |
1297 | .l1clk ( l1clk_pm1 ), | |
1298 | .din ( | |
1299 | d_cam_sel_delay1[3:0] | |
1300 | ), // done | |
1301 | .dout ( | |
1302 | mbist_cam_sel[3:0] | |
1303 | ), | |
1304 | .siclk(siclk), | |
1305 | .soclk(soclk)); | |
1306 | ||
1307 | ||
1308 | ||
1309 | ||
1310 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
1311 | //////////////////////////////////// //////////////////////////////////// | |
1312 | // CONTROL REG: | |
1313 | //////////////////////////////////// //////////////////////////////////// | |
1314 | ||
1315 | ||
1316 | l2t_msff_ctl_macro__width_36 cntl_reg ( | |
1317 | .scan_in(cntl_reg_scanin), | |
1318 | .scan_out(cntl_reg_scanout), | |
1319 | .l1clk ( l1clk_pm1 ), | |
1320 | .din ( cntl_in[35:0] ), | |
1321 | .dout ( cntl_out[35:0] ), | |
1322 | .siclk(siclk), | |
1323 | .soclk(soclk)); | |
1324 | ||
1325 | ||
1326 | assign cntl_in[35:19] = reset_engine ? {17'b00000_0000000000}: | |
1327 | (~run3 | cambist) ? cntl_algr[16:0]: | |
1328 | next_algr[16:0]; | |
1329 | ||
1330 | ||
1331 | // assign cntl_in[12:3] = reset_engine ? start_addr[7:0]: | |
1332 | // ~run3 ? cntl_addr[7:0]: | |
1333 | // next_addr[7:0]; | |
1334 | ||
1335 | // reset_engine run3 overflow cout_rw output | |
1336 | // --------------------------------------------------------- | |
1337 | // 1 x x x start_addr | |
1338 | // 0 0 x x cntl_addr | |
1339 | // 0 1 1 x restart_addr | |
1340 | // 0 1 0 1 incred_addr | |
1341 | // 0 1 0 0 cntl_addr | |
1342 | ||
1343 | ||
1344 | assign sel_nextaddr_reset = reset_engine; | |
1345 | assign sel_nextaddr_restart = ~reset_engine & run3 & overflow; | |
1346 | assign sel_nextaddr_incred = ~reset_engine & run3 & ~overflow & cout_rw; | |
1347 | assign sel_nextaddr_same = ~(sel_nextaddr_reset | sel_nextaddr_restart | sel_nextaddr_incred) | cambist; | |
1348 | ||
1349 | assign cntl_in[7:3] = ({5{sel_nextaddr_reset}} & start_addr[4:0]) | | |
1350 | ({5{sel_nextaddr_restart}} & restart_addr[4:0]) | | |
1351 | ({5{sel_nextaddr_incred}} & incred_addr[4:0]) | | |
1352 | ({5{sel_nextaddr_same}} & cntl_addr[4:0]); | |
1353 | ||
1354 | ||
1355 | ||
1356 | assign cntl_in[18:8] = 11'b00000000000; | |
1357 | ||
1358 | ||
1359 | assign cntl_in[2:0] = reset_engine ? 3'b000 : | |
1360 | (~run3 | cambist) ? cntl_rw[2:0]: | |
1361 | next_rw[2:0]; | |
1362 | ||
1363 | ||
1364 | ||
1365 | //////////////////////////////////// //////////////////////////////////// | |
1366 | // NEXT ALGR | |
1367 | //////////////////////////////////// //////////////////////////////////// | |
1368 | ||
1369 | // msb | |
1370 | assign cntl_msb = start_in & cntl_out[ 35]; // done selection | |
1371 | ||
1372 | ||
1373 | assign cntl_bisi = mb_default_bisi | mb_user_bisi_rw_mode ? cntl_out[34] : | |
1374 | 1'b1; | |
1375 | ||
1376 | ||
1377 | // array | |
1378 | assign cntl_array_sel[3:0] = (user_mode | last_array) ? 4'b1111: | |
1379 | cntl_out[33:30]; // array selection | |
1380 | // cmp | |
1381 | assign cntl_cmp_sel[3:0] = sel_cmp_pass ? {4'b1111} : | |
1382 | cntl_out[29:26]; | |
1383 | ||
1384 | // data | |
1385 | assign cntl_data_sel[1:0] = (bisi_mode | mb_user_data_mode) ? 2'b11 : cntl_out[25:24]; // data selection | |
1386 | ||
1387 | // address mix | |
1388 | assign cntl_addr_mix = (mb_user_addr_mode | bisi_mode) ? 1'b1 : cntl_out[ 23]; // address mix | |
1389 | ||
1390 | assign cntl_march_element[3:0] = sel_march_1_pass ? 4'b1111: | |
1391 | cntl_out[22:19]; // march element | |
1392 | ||
1393 | ||
1394 | ||
1395 | assign addr_mix = (bisi_mode | mb_user_addr_mode) ? 1'b0 : | |
1396 | cntl_addr_mix; | |
1397 | ||
1398 | assign cntl_algr[16:0] = {cntl_msb, | |
1399 | cntl_bisi, | |
1400 | cntl_array_sel[3:0], | |
1401 | cntl_cmp_sel[3:0], | |
1402 | cntl_data_sel[1:0], | |
1403 | cntl_addr_mix, | |
1404 | cntl_march_element[3:0]}; | |
1405 | ||
1406 | assign next_algr[16:0] = cout_addr ? cntl_algr[16:0] + 17'h1 : cntl_algr[16:0]; // mbist control | |
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | //////////////////////////////////// //////////////////////////////////// | |
1412 | // NEXT ADDR | |
1413 | //////////////////////////////////// //////////////////////////////////// | |
1414 | ||
1415 | ||
1416 | ///////////////////////// | |
1417 | // address engine | |
1418 | ///////////////////////// | |
1419 | ||
1420 | ||
1421 | assign upaddr = march_0 | march_1 | march_2 | march_6 | march_7 | bisi_mode ; | |
1422 | ||
1423 | ||
1424 | assign march_element_pre[3:0]=next_algr[3:0]; | |
1425 | ||
1426 | assign march_pre_0 = march_element_pre[3:0]==4'h0; | |
1427 | assign march_pre_1 = march_element_pre[3:0]==4'h1; | |
1428 | assign march_pre_2 = march_element_pre[3:0]==4'h2; | |
1429 | assign march_pre_6 = march_element_pre[3:0]==4'h6; | |
1430 | assign march_pre_7 = march_element_pre[3:0]==4'h7; | |
1431 | ||
1432 | assign upaddr_pre = march_pre_0 | march_pre_1 | march_pre_2 | march_pre_6 | march_pre_7; | |
1433 | ||
1434 | ||
1435 | assign incr_addr[4:0] = mb_user_addr_mode ? user_incr_addr[4:0] : 5'h01; | |
1436 | ||
1437 | assign start_addr[4:0] = mb_user_addr_mode ? user_start_addr[4:0] : 5'h00; | |
1438 | ||
1439 | ||
1440 | // assign next_addr_out[8:0] = cout_rw ? cntl_addr[8:0] + incr_addr[8:0] : cntl_addr[8:0]; // next address | |
1441 | ||
1442 | ||
1443 | assign incred_addr[4:0] = cntl_addr[4:0] + incr_addr[4:0]; | |
1444 | ||
1445 | ||
1446 | assign overflow = upaddr ? ( cntl_addr[4:0] == stop_addr[4:0]) & (cntl_rw[2:0]==3'b111): | |
1447 | (~cntl_addr[4:0] == start_addr[4:0]) & (cntl_rw[2:0]==3'b111); | |
1448 | ||
1449 | ||
1450 | // assign next_addr[4:0]= overflow ? restart_addr[4:0] : next_addr_out[4:0]; | |
1451 | ||
1452 | assign restart_addr[4:0] = upaddr_pre ? start_addr[4:0] : ~stop_addr[4:0]; | |
1453 | ||
1454 | assign cout_addr = overflow; | |
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | //////////////////////////////////// //////////////////////////////////// | |
1460 | // NEXT RW | |
1461 | //////////////////////////////////// //////////////////////////////////// | |
1462 | ||
1463 | ||
1464 | assign cntl_rw[2:0] = sel_rw_pass ? 3'b111: | |
1465 | cntl_out[ 2: 0]; // read write control | |
1466 | ||
1467 | assign next_rw[2:0] = cntl_rw[2:0]+3'b001 ; | |
1468 | ||
1469 | assign cout_rw = &cntl_rw[2:0]; // carry over for rw | |
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | //////////////////////////////////// //////////////////////////////////// | |
1476 | // MBIST CONTROL SIGNAL | |
1477 | // - mem_wr | |
1478 | //////////////////////////////////// //////////////////////////////////// | |
1479 | ||
1480 | ||
1481 | assign one_cycle_march = march_0 | march_5 | march_7; | |
1482 | assign five_cycle_march = march_6 | march_8; | |
1483 | assign two_cycle_march = ~(one_cycle_march | five_cycle_march); | |
1484 | ||
1485 | ||
1486 | ///////////////////////// | |
1487 | // membist write enable | |
1488 | ///////////////////////// | |
1489 | ||
1490 | ||
1491 | assign mem_wr_pbi = run3 & ( | |
1492 | march_0 | | |
1493 | ((march_1 | march_2 | march_3 | march_4 ) & rw_1) | | |
1494 | (march_6 & (rw_0 | rw_1 | rw_4)) | | |
1495 | march_7 | | |
1496 | (march_8 & (rw_0 | rw_1 | rw_4)) | |
1497 | ); | |
1498 | ||
1499 | ||
1500 | assign mem_wr = bisi_wr_mode ? 1'b1 : | |
1501 | bisi_rd_mode ? 1'b0 : | |
1502 | mem_wr_pbi; | |
1503 | ||
1504 | ///////////////////////// | |
1505 | // membist read enable | |
1506 | ///////////////////////// | |
1507 | ||
1508 | ||
1509 | ||
1510 | assign mem_rd_pbi = run3 & ~mem_wr; | |
1511 | ||
1512 | assign mem_rd= bisi_rd_mode ? 1'b1 : mem_rd_pbi; | |
1513 | ||
1514 | ///////////////////// | |
1515 | // membist address: | |
1516 | //////////////////// | |
1517 | ||
1518 | assign cntl_addr[4:0] = cntl_out[7:3]; | |
1519 | ||
1520 | assign adj_addr = (five_cycle_march & (rw_1 | rw_3)) ? {cntl_addr[4:2],~cntl_addr[1],cntl_addr[0]}: | |
1521 | cntl_addr[4:0] ; | |
1522 | ||
1523 | assign mem_addr1[4:0] = upaddr ? adj_addr[4:0]: ~adj_addr[4:0]; | |
1524 | ||
1525 | ||
1526 | ||
1527 | ///////////////////// | |
1528 | // true data | |
1529 | //////////////////// | |
1530 | ||
1531 | assign true_data_l = bisi_mode | | |
1532 | march_0 | | |
1533 | (march_1 & rw_0) | | |
1534 | (march_2 & rw_1) | | |
1535 | (march_3 & rw_0) | | |
1536 | (march_4 & rw_1) | | |
1537 | (march_5) | | |
1538 | (march_6 & (rw_1 | rw_3 | rw_4)) | | |
1539 | (march_8 & (rw_0 | rw_2)); | |
1540 | ||
1541 | assign true_data=~true_data_l; | |
1542 | ||
1543 | ///////////////////// | |
1544 | // membist data: | |
1545 | //////////////////// | |
1546 | ||
1547 | assign data_pat_sel[7:0] = (mb_user_data_mode & bisi_mode) ? ~user_data[7:0]: | |
1548 | (mb_user_data_mode) ? user_data[7:0]: | |
1549 | bisi_mode ? 8'hFF: | |
1550 | (cntl_data_sel[1:0] == 2'h0) ? 8'hAA: | |
1551 | (cntl_data_sel[1:0] == 2'h1) ? 8'h99: | |
1552 | (cntl_data_sel[1:0] == 2'h2) ? 8'hCC: | |
1553 | 8'h00; | |
1554 | assign mem_data[7:0] = true_data ? data_pat_sel[7:0] : ~data_pat_sel[7:0]; | |
1555 | ||
1556 | ||
1557 | //////////////////////////////////// //////////////////////////////////// | |
1558 | // STOP ADDR | |
1559 | //////////////////////////////////// //////////////////////////////////// | |
1560 | ||
1561 | ||
1562 | assign stop_addr[4:0] = mb_user_addr_mode ? user_stop_addr[4:0] : | |
1563 | array_0 ? 5'b11111: // mbtag 32 | |
1564 | array_1 ? 5'b00111: // fbtag 8 | |
1565 | array_2 ? 5'b00111: // wbtag 8 | |
1566 | array_3 ? 5'b00011: // rdmatag 4 | |
1567 | array_4 ? 5'b11111: // mbdata 32 | |
1568 | array_5 ? 5'b01111: // iqarray 16 | |
1569 | 5'b11111; | |
1570 | ||
1571 | //////////////////////////////////// //////////////////////////////////// | |
1572 | // ADDR MIX | |
1573 | //////////////////////////////////// //////////////////////////////////// | |
1574 | ||
1575 | ||
1576 | assign mem_addr[4:0] = (addr_mix & array_0) ? { mem_addr1[0],mem_addr1[4:1] } : | |
1577 | (addr_mix & (array_1|array_2)) ? { mem_addr1[4],mem_addr1[3],mem_addr1[0],mem_addr1[2],mem_addr1[1] } : | |
1578 | (addr_mix & array_3) ? { mem_addr1[4],mem_addr1[3],mem_addr1[2],mem_addr1[0],mem_addr1[1] } : | |
1579 | (addr_mix & array_4) ? { mem_addr1[0],mem_addr1[4],mem_addr1[3],mem_addr1[2],mem_addr1[1] } : | |
1580 | (addr_mix & array_5) ? { mem_addr1[4],mem_addr1[0],mem_addr1[3],mem_addr1[2],mem_addr1[1] } : | |
1581 | mem_addr1[4:0]; | |
1582 | ||
1583 | ||
1584 | ||
1585 | ||
1586 | //////////////////////////////////// //////////////////////////////////// | |
1587 | // SEQ selection | |
1588 | //////////////////////////////////// //////////////////////////////////// | |
1589 | ||
1590 | // array | |
1591 | ||
1592 | assign array_0 = array_sel[3:0]==4'h0 & ~cambist & run3; | |
1593 | assign array_1 = array_sel[3:0]==4'h1 & ~cambist & run3; | |
1594 | assign array_2 = array_sel[3:0]==4'h2 & ~cambist & run3; | |
1595 | assign array_3 = array_sel[3:0]==4'h3 & ~cambist & run3; | |
1596 | assign array_4 = array_sel[3:0]==4'h4 & ~cambist & run3; | |
1597 | assign array_5 = array_sel[3:0]==4'h5 & ~cambist & run3; | |
1598 | ||
1599 | assign last_array = array_5; | |
1600 | // cmp | |
1601 | assign cmp_0 = cmp_sel[3:0]==4'b0000; | |
1602 | // assign cmp_1 = cmp_sel[3:0]==4'b0001; | |
1603 | // assign cmp_2 = cmp_sel[3:0]==4'b0010; | |
1604 | assign cmp_3 = cmp_sel[3:0]==4'b0011; | |
1605 | // assign cmp_4 = cmp_sel[3:0]==4'b0100; | |
1606 | // assign cmp_5 = cmp_sel[3:0]==4'b0101; | |
1607 | // assign cmp_6 = cmp_sel[3:0]==4'b0110; | |
1608 | // assign cmp_7 = cmp_sel[3:0]==4'b0111; | |
1609 | // assign cmp_15 = cmp_sel[3:0]==4'b1111; | |
1610 | ||
1611 | // march | |
1612 | ||
1613 | assign march_0 = (march_element[3:0]==4'h0); | |
1614 | assign march_1 = (march_element[3:0]==4'h1); | |
1615 | assign march_2 = (march_element[3:0]==4'h2); | |
1616 | assign march_3 = (march_element[3:0]==4'h3); | |
1617 | assign march_4 = (march_element[3:0]==4'h4); | |
1618 | assign march_5 = (march_element[3:0]==4'h5); | |
1619 | assign march_6 = (march_element[3:0]==4'h6); | |
1620 | assign march_7 = (march_element[3:0]==4'h7); | |
1621 | assign march_8 = (march_element[3:0]==4'h8); | |
1622 | ||
1623 | // rw | |
1624 | ||
1625 | assign rw_0 = (rw[2:0]==3'b000); | |
1626 | assign rw_1 = (rw[2:0]==3'b001); | |
1627 | assign rw_2 = (rw[2:0]==3'b010); | |
1628 | assign rw_3 = (rw[2:0]==3'b011); | |
1629 | assign rw_4 = (rw[2:0]==3'b100); | |
1630 | // assign rw_5 = (rw[2:0]==3'b101); | |
1631 | // assign rw_6 = (rw[2:0]==3'b110); | |
1632 | // assign rw_7 = (rw[2:0]==3'b111); | |
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | ||
1638 | //////////////////////////////////// //////////////////////////////////// | |
1639 | // SEQ logic | |
1640 | //////////////////////////////////// //////////////////////////////////// | |
1641 | ||
1642 | // cam select logic | |
1643 | ||
1644 | ||
1645 | ||
1646 | assign cam_sel_cntl_out[1:0]=cam_out[13:12]; | |
1647 | ||
1648 | ||
1649 | assign cam_sel[1:0]= mb_user_cam_mode ? user_cam_sel[1:0] : | |
1650 | cam_sel_cntl_out[1:0]; | |
1651 | ||
1652 | ||
1653 | // ctest select logic | |
1654 | ||
1655 | assign ctest_sel_cntl_out[1:0]=cam_out[11:10]; | |
1656 | ||
1657 | ||
1658 | assign ctest_sel[1:0]= mb_user_cam_mode ? user_cam_test_sel[1:0] : | |
1659 | ctest_sel_cntl_out[1:0]; | |
1660 | ||
1661 | ||
1662 | ||
1663 | assign cseq_cntl_out[1:0]=cam_out[9:8]; | |
1664 | ||
1665 | ||
1666 | l2t_msff_ctl_macro__width_2 cseq_reg ( | |
1667 | .scan_in(cseq_reg_scanin), | |
1668 | .scan_out(cseq_reg_scanout), | |
1669 | .l1clk ( l1clk_pm1 ), | |
1670 | .din ( cseq[1:0] ), | |
1671 | .dout ( cseq_out[1:0] ), | |
1672 | .siclk(siclk), | |
1673 | .soclk(soclk)); | |
1674 | ||
1675 | assign cseq[1:0]=(&cseq_cntl_out[1:0] ) ? cseq_out[1:0] : | |
1676 | cseq_cntl_out[1:0]; | |
1677 | ||
1678 | ||
1679 | // array logic | |
1680 | ||
1681 | assign array_sel_cntl_out[3:0]=cntl_out[33:30]; | |
1682 | ||
1683 | ||
1684 | l2t_msff_ctl_macro__width_4 array_sel_reg ( | |
1685 | .scan_in(array_sel_reg_scanin), | |
1686 | .scan_out(array_sel_reg_scanout), | |
1687 | .l1clk ( l1clk_pm1 ), | |
1688 | .din ( array_sel[3:0] ), | |
1689 | .dout ( array_sel_out[3:0] ), | |
1690 | .siclk(siclk), | |
1691 | .soclk(soclk)); | |
1692 | ||
1693 | assign array_sel[3:0]=(&array_sel_cntl_out[3:0]) ? array_sel_out[3:0] : | |
1694 | user_mode ? user_array_sel[3:0] : | |
1695 | array_sel_cntl_out[3:0]; | |
1696 | ||
1697 | ||
1698 | ||
1699 | // cmp logic | |
1700 | ||
1701 | assign cmp_sel_cntl_out[3:0] = cntl_out[29:26]; | |
1702 | ||
1703 | l2t_msff_ctl_macro__width_4 cmp_sel_reg ( | |
1704 | .scan_in(cmp_sel_reg_scanin), | |
1705 | .scan_out(cmp_sel_reg_scanout), | |
1706 | .l1clk ( l1clk_pm1 ), | |
1707 | .din ( cmp_sel[3:0] ), | |
1708 | .dout ( cmp_sel_out[3:0] ), | |
1709 | .siclk(siclk), | |
1710 | .soclk(soclk)); | |
1711 | ||
1712 | // assign cmp_sel[3:0]= (&cmp_sel_cntl_out[3:0] & ~(array_5)) ? cmp_sel_out[3:0] : | |
1713 | assign cmp_sel[3:0]= (&cmp_sel_cntl_out[3:0] ) ? cmp_sel_out[3:0] : | |
1714 | mb_user_cmpsel_hold ? user_cmpsel[3:0] : | |
1715 | cmp_sel_cntl_out[3:0]; | |
1716 | ||
1717 | ||
1718 | // march logic | |
1719 | ||
1720 | assign march_element_cntl_out[3:0]=cntl_out[22:19]; | |
1721 | ||
1722 | ||
1723 | l2t_msff_ctl_macro__width_4 marche_element_reg ( | |
1724 | .scan_in(marche_element_reg_scanin), | |
1725 | .scan_out(marche_element_reg_scanout), | |
1726 | .l1clk ( l1clk_pm1 ), | |
1727 | .din ( march_element[3:0] ), | |
1728 | .dout ( march_element_out ), | |
1729 | .siclk(siclk), | |
1730 | .soclk(soclk)); | |
1731 | ||
1732 | assign march_element[3:0]=(&march_element_cntl_out[3:0]) ? march_element_out[3:0] : | |
1733 | march_element_cntl_out[3:0]; | |
1734 | ||
1735 | ||
1736 | // rw | |
1737 | assign rw[2:0]=cntl_out[2:0]; | |
1738 | ||
1739 | ||
1740 | ||
1741 | ||
1742 | ////////////////////////////////////////////////////////////////// | |
1743 | // SEL_PASS LOGIC | |
1744 | ////////////////////////////////////////////////////////////////// | |
1745 | ||
1746 | ||
1747 | ||
1748 | ||
1749 | // pass logic: | |
1750 | ||
1751 | // march | |
1752 | assign sel_march_1_pass = bisi_mode | (ten_n_mode & march_5) | march_8 ; | |
1753 | ||
1754 | // cmp | |
1755 | ||
1756 | assign bisi_wr_mode = mb_default_bisi | mb_user_bisi_rw_mode ? ~cntl_bisi & run3 : | |
1757 | mb_user_bisi_wr_mode & run3; | |
1758 | ||
1759 | assign bisi_rd_mode =mb_default_bisi | mb_user_bisi_rw_mode ? cntl_bisi & run3 : | |
1760 | mb_user_bisi_rd_mode & run3; | |
1761 | ||
1762 | ||
1763 | ||
1764 | // cmp | |
1765 | ||
1766 | assign sel_cmp_pass= (mb_user_cmpsel_hold | bisi_wr_mode) | | |
1767 | (array_0 & cmp_0) | | |
1768 | (array_1 & cmp_0) | | |
1769 | (array_2 & cmp_0) | | |
1770 | (array_3 & cmp_0) | | |
1771 | (array_4 & cmp_3) | // mbdata requires 4 pass | |
1772 | (array_5 & cmp_3) ; | |
1773 | ||
1774 | ||
1775 | ||
1776 | // rw | |
1777 | assign sel_rw_1_pass = bisi_mode | one_cycle_march ; | |
1778 | ||
1779 | assign sel_rw_2_pass = two_cycle_march; | |
1780 | assign sel_rw_5_pass = five_cycle_march; | |
1781 | ||
1782 | assign sel_rw_pass = (run3 & sel_rw_1_pass & rw_0) | | |
1783 | (run3 & sel_rw_2_pass & rw_1) | | |
1784 | (run3 & sel_rw_5_pass & rw_4) ; | |
1785 | ||
1786 | ||
1787 | ||
1788 | l2t_msff_ctl_macro__width_1 user_bisi_wr_mode_reg ( | |
1789 | .scan_in(user_bisi_wr_mode_reg_scanin), | |
1790 | .scan_out(user_bisi_wr_mode_reg_scanout), | |
1791 | .l1clk ( l1clk_pm1 ), | |
1792 | .din ( user_bisi_wr_mode_in ), | |
1793 | .dout ( user_bisi_wr_mode ), | |
1794 | .siclk(siclk), | |
1795 | .soclk(soclk)); | |
1796 | ||
1797 | assign user_bisi_wr_mode_in=user_bisi_wr_mode; | |
1798 | ||
1799 | l2t_msff_ctl_macro__width_1 user_bisi_rd_mode_reg ( | |
1800 | .scan_in(user_bisi_rd_mode_reg_scanin), | |
1801 | .scan_out(user_bisi_rd_mode_reg_scanout), | |
1802 | .l1clk ( l1clk_pm1 ), | |
1803 | .din ( user_bisi_rd_mode_in ), | |
1804 | .dout ( user_bisi_rd_mode ), | |
1805 | .siclk(siclk), | |
1806 | .soclk(soclk)); | |
1807 | ||
1808 | assign user_bisi_rd_mode_in=user_bisi_rd_mode; | |
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | assign mb_user_data_mode = user_mode & user_data_mode; | |
1814 | assign mb_user_addr_mode = user_mode & user_addr_mode; | |
1815 | assign mb_user_cmpsel_hold = user_mode & user_cmpsel_hold; | |
1816 | assign mb_user_cam_mode = user_mode & user_cam_mode; | |
1817 | assign mb_user_ram_mode = user_mode & ~user_cam_mode; | |
1818 | assign mb_user_loop_mode = user_mode & user_loop_mode; | |
1819 | ||
1820 | ||
1821 | ||
1822 | assign mb_user_bisi_wr_mode = user_mode & user_bisi_wr_mode & bisi_mode; | |
1823 | assign mb_user_bisi_rd_mode = user_mode & user_bisi_rd_mode & bisi_mode; | |
1824 | ||
1825 | assign mb_user_bisi_rw_mode = ((~user_bisi_wr_mode & ~user_bisi_rd_mode) | (user_bisi_wr_mode & user_bisi_rd_mode)) & bisi_mode; | |
1826 | ||
1827 | assign mb_default_bisi = bisi_mode & ~user_mode; | |
1828 | ||
1829 | ||
1830 | ||
1831 | //////////////////////////////////// //////////////////////////////////// | |
1832 | // membist control assignment | |
1833 | //////////////////////////////////// //////////////////////////////////// | |
1834 | ||
1835 | ||
1836 | // assign mb_cmp_sel[3:0] = cmp_sel[3:0]; | |
1837 | ||
1838 | ||
1839 | assign mb_cmp_sel[0] = (cmp_sel[1:0]==2'b00 & (array_4 | array_5)) | (cmp_sel[0] & ~(array_4 | array_5)); | |
1840 | assign mb_cmp_sel[1] = (cmp_sel[1:0]==2'b01 & (array_4 | array_5)) | (cmp_sel[1] & ~(array_4 | array_5)); | |
1841 | assign mb_cmp_sel[2] = (cmp_sel[1:0]==2'b10 & (array_4 | array_5)) | (cmp_sel[2] & ~(array_4 | array_5)); | |
1842 | assign mb_cmp_sel[3] = (cmp_sel[1:0]==2'b11 & (array_4 | array_5)) | (cmp_sel[3] & ~(array_4 | array_5)); | |
1843 | ||
1844 | ||
1845 | ||
1846 | assign mb_addr[4:0]=cambist ? cam_addr[4:0]: mem_addr[4:0]; | |
1847 | assign mb_write_data[7:0]=cambist ? cam_data[7:0] : mem_data[7:0]; | |
1848 | ||
1849 | ||
1850 | ||
1851 | ||
1852 | // only one array read signal should be active | |
1853 | ||
1854 | assign mb_array_0_rd = array_0 & mem_rd; | |
1855 | assign mb_array_1_rd = array_1 & mem_rd; | |
1856 | assign mb_array_2_rd = array_2 & mem_rd; | |
1857 | assign mb_array_3_rd = array_3 & mem_rd; | |
1858 | assign mb_array_4_rd = array_4 & mem_rd; | |
1859 | assign mb_array_5_rd = array_5 & mem_rd; | |
1860 | ||
1861 | ||
1862 | assign mb_array_0_wr = (array_0 & mem_wr) | (cam_0 & cam_wr_en); | |
1863 | assign mb_array_1_wr = (array_1 & mem_wr) | (cam_1 & cam_wr_en); | |
1864 | assign mb_array_2_wr = (array_2 & mem_wr) | (cam_2 & cam_wr_en); | |
1865 | assign mb_array_3_wr = (array_3 & mem_wr) | (cam_3 & cam_wr_en); | |
1866 | assign mb_array_4_wr = array_4 & mem_wr; | |
1867 | assign mb_array_5_wr = array_5 & mem_wr; | |
1868 | ||
1869 | ||
1870 | // assign mb_run = run; | |
1871 | assign mb_run = run | ((cntl_msb | cam_msb) & ~&done_delay[2:1]); | |
1872 | ||
1873 | //////////////////////////////////// //////////////////////////////////// | |
1874 | // DONE LOGIC | |
1875 | //////////////////////////////////// //////////////////////////////////// | |
1876 | ||
1877 | ||
1878 | ||
1879 | ||
1880 | ||
1881 | ||
1882 | l2t_msff_ctl_macro__width_1 msb_latch ( | |
1883 | .scan_in(msb_latch_scanin), | |
1884 | .scan_out(msb_latch_scanout), | |
1885 | .l1clk ( l1clk_pm1 ), | |
1886 | .din ( msb_in ), | |
1887 | .dout ( msb_out ), | |
1888 | .siclk(siclk), | |
1889 | .soclk(soclk)); | |
1890 | ||
1891 | assign msb_in= (~start_in ) | (mb_user_loop_mode & mb_done) ? 1'b0 : | |
1892 | (cntl_msb | cam_msb) ? 1'b1 : | |
1893 | msb_out; | |
1894 | ||
1895 | assign stop_engine_l = ~start_in ? 1'b0 : | |
1896 | mb_user_cam_mode ? cam_msb : | |
1897 | mb_user_loop_mode ? cntl_msb : | |
1898 | (mb_user_ram_mode | bisi_mode) ? cntl_msb : | |
1899 | cam_msb; | |
1900 | ||
1901 | assign mb_done= ~start_in ? 1'b0 : | |
1902 | bisi_mode | mb_user_loop_mode | mb_user_ram_mode ? msb_out & (done_delay[4:0]==5'b11110): | |
1903 | cam_msb & (done_delay[4:0]==5'b11110) ; | |
1904 | ||
1905 | assign run3 = &done_delay[4:1] & ~stop_engine_l & start_in; | |
1906 | ||
1907 | ||
1908 | l2t_msff_ctl_macro__width_1 run3_transition_reg ( | |
1909 | .scan_in(run3_transition_reg_scanin), | |
1910 | .scan_out(run3_transition_reg_scanout), | |
1911 | .l1clk ( l1clk_pm1 ), | |
1912 | .din ( run3 ), | |
1913 | .dout ( run3_out ), | |
1914 | .siclk(siclk), | |
1915 | .soclk(soclk)); | |
1916 | ||
1917 | assign run3_transition = run3 & ~run3_out; | |
1918 | ||
1919 | l2t_msff_ctl_macro__width_5 done_delay_reg ( | |
1920 | .scan_in(done_delay_reg_scanin), | |
1921 | .scan_out(done_delay_reg_scanout), | |
1922 | .l1clk ( l1clk_pm1 ), | |
1923 | .din ( done_delay_in[4:0] ), | |
1924 | .dout ( done_delay[4:0] ), | |
1925 | .siclk(siclk), | |
1926 | .soclk(soclk)); | |
1927 | ||
1928 | ||
1929 | assign done_delay_in[4:0] = run3 ? 5'b11111 : | |
1930 | mb_done ? 5'b11110 : | |
1931 | (run & ~run3) ? done_delay[4:0] + 5'b00001 : | |
1932 | 5'b00000; | |
1933 | ||
1934 | ||
1935 | ||
1936 | ||
1937 | ||
1938 | //////////////////////////////////// //////////////////////////////////// | |
1939 | // FAIL LOGIC | |
1940 | //////////////////////////////////// //////////////////////////////////// | |
1941 | ||
1942 | assign mb_mbdata_mb2_rw_fail = ~mbdata_mb2_rw_fail; | |
1943 | assign mb_iqarray_mb2_rw_fail = ~iqarray_mb2_rw_fail; | |
1944 | assign mb_mb_fb_wb_rdma_mb2_rw_fail = ~cam_mb2_rw_fail ; | |
1945 | ||
1946 | assign mb_fb_wb_rdma_fail_d = run3_transition ? 1'b0 : mb_mb_fb_wb_rdma_mb2_rw_fail | mb_fb_wb_rdma_mb2_rw_fail_sticky; | |
1947 | assign mbdata_fail_d = run3_transition ? 1'b0 : mb_mbdata_mb2_rw_fail | mbdata_mb2_rw_fail_sticky; | |
1948 | assign iqarray_fail_d = run3_transition ? 1'b0 : mb_iqarray_mb2_rw_fail | iqarray_mb2_rw_fail_sticky; | |
1949 | ||
1950 | assign cam0_fail_d = run3_transition ? 1'b0 : cam0_fail | cam0_fail_sticky; | |
1951 | assign cam1_fail_d = run3_transition ? 1'b0 : cam1_fail | cam1_fail_sticky; | |
1952 | assign cam2_fail_d = run3_transition ? 1'b0 : cam2_fail | cam2_fail_sticky; | |
1953 | assign cam3_fail_d = run3_transition ? 1'b0 : cam3_fail | cam3_fail_sticky; | |
1954 | ||
1955 | ||
1956 | ||
1957 | l2t_msff_ctl_macro__width_7 mbist_fail_input_reg ( | |
1958 | .scan_in(mbist_fail_input_reg_scanin), | |
1959 | .scan_out(mbist_fail_input_reg_scanout), | |
1960 | .l1clk ( l1clk_pm1 ), | |
1961 | .din ({ mb_fb_wb_rdma_fail_d, | |
1962 | mbdata_fail_d, | |
1963 | iqarray_fail_d, | |
1964 | cam0_fail_d, | |
1965 | cam1_fail_d, | |
1966 | cam2_fail_d, | |
1967 | cam3_fail_d | |
1968 | }), | |
1969 | .dout ({ mb_fb_wb_rdma_mb2_rw_fail_sticky, | |
1970 | mbdata_mb2_rw_fail_sticky, | |
1971 | iqarray_mb2_rw_fail_sticky, | |
1972 | cam0_fail_sticky, | |
1973 | cam1_fail_sticky, | |
1974 | cam2_fail_sticky, | |
1975 | cam3_fail_sticky | |
1976 | }), | |
1977 | .siclk(siclk), | |
1978 | .soclk(soclk)); | |
1979 | ||
1980 | ||
1981 | ||
1982 | ||
1983 | ||
1984 | assign mbist_fail_sticky = mb_fb_wb_rdma_mb2_rw_fail_sticky | | |
1985 | mbdata_mb2_rw_fail_sticky | | |
1986 | iqarray_mb2_rw_fail_sticky | | |
1987 | cam0_fail_sticky | | |
1988 | cam1_fail_sticky | | |
1989 | cam2_fail_sticky | | |
1990 | cam3_fail_sticky ; | |
1991 | ||
1992 | ||
1993 | assign mbist_fail_array = mb_mb_fb_wb_rdma_mb2_rw_fail | | |
1994 | mb_mbdata_mb2_rw_fail | | |
1995 | mb_iqarray_mb2_rw_fail | | |
1996 | cam0_fail | | |
1997 | cam1_fail | | |
1998 | cam2_fail | | |
1999 | cam3_fail ; | |
2000 | ||
2001 | ||
2002 | ||
2003 | ||
2004 | ||
2005 | assign valid_fail=run3 | (stop_engine_l & ~mb_done); | |
2006 | ||
2007 | ||
2008 | assign mb_fail = mb_done ? mbist_fail_sticky : mbist_fail_array & valid_fail; | |
2009 | ||
2010 | ||
2011 | ||
2012 | ||
2013 | ////////////////////////////////////////////////////////////////// | |
2014 | // OUTPUT FLOP: | |
2015 | ////////////////////////////////////////////////////////////////// | |
2016 | ||
2017 | // mb_done | |
2018 | ||
2019 | ||
2020 | l2t_msff_ctl_macro__width_1 out_mb_tcu_done_reg ( | |
2021 | .scan_in(out_mb_tcu_done_reg_scanin), | |
2022 | .scan_out(out_mb_tcu_done_reg_scanout), | |
2023 | .l1clk ( l1clk_pm1 ), | |
2024 | .din ( mb_done ), | |
2025 | .dout ( mb_done_out ), | |
2026 | .siclk(siclk), | |
2027 | .soclk(soclk)); | |
2028 | ||
2029 | ||
2030 | // mb_fail | |
2031 | ||
2032 | ||
2033 | l2t_msff_ctl_macro__width_1 out_mb_tcu_fail_reg ( | |
2034 | .scan_in(out_mb_tcu_fail_reg_scanin), | |
2035 | .scan_out(out_mb_tcu_fail_reg_scanout), | |
2036 | .l1clk ( l1clk_pm1 ), | |
2037 | .din ( mb_fail ), | |
2038 | .dout ( mb_fail_out ), | |
2039 | .siclk(siclk), | |
2040 | .soclk(soclk)); | |
2041 | ||
2042 | ||
2043 | ||
2044 | ||
2045 | // out cmpsel | |
2046 | ||
2047 | l2t_msff_ctl_macro__width_4 out_cmp_sel_reg ( | |
2048 | .scan_in(out_cmp_sel_reg_scanin), | |
2049 | .scan_out(out_cmp_sel_reg_scanout), | |
2050 | .l1clk ( l1clk_pm1 ), | |
2051 | .din ({ | |
2052 | mb_cmp_sel[3:0] } ), | |
2053 | .dout ({ | |
2054 | mb_cmpsel_out[3:0]} ), | |
2055 | .siclk(siclk), | |
2056 | .soclk(soclk)); | |
2057 | ||
2058 | ||
2059 | ||
2060 | // thes are all the output flops to arrays | |
2061 | // for the following signals: | |
2062 | // | |
2063 | // - run | |
2064 | // - data | |
2065 | // - address | |
2066 | ||
2067 | ||
2068 | l2t_msff_ctl_macro__width_1 out_run_mb_arrays_reg ( | |
2069 | .scan_in(out_run_mb_arrays_reg_scanin), | |
2070 | .scan_out(out_run_mb_arrays_reg_scanout), | |
2071 | .l1clk ( l1clk_pm1 ), | |
2072 | .din ( mb_run), | |
2073 | .dout ( mb_run_out), | |
2074 | .siclk(siclk), | |
2075 | .soclk(soclk)); | |
2076 | ||
2077 | // data 8 bits | |
2078 | ||
2079 | l2t_msff_ctl_macro__width_8 out_data_mb_arrays_reg ( | |
2080 | .scan_in(out_data_mb_arrays_reg_scanin), | |
2081 | .scan_out(out_data_mb_arrays_reg_scanout), | |
2082 | .l1clk ( l1clk_pm1 ), | |
2083 | .din ( mb_write_data[7:0]), | |
2084 | .dout ( mb_write_data_out[7:0]), | |
2085 | .siclk(siclk), | |
2086 | .soclk(soclk)); | |
2087 | ||
2088 | ||
2089 | // address 16 bits | |
2090 | ||
2091 | ||
2092 | l2t_msff_ctl_macro__width_5 out_addr_mb_arrays_reg ( | |
2093 | .scan_in(out_addr_mb_arrays_reg_scanin), | |
2094 | .scan_out(out_addr_mb_arrays_reg_scanout), | |
2095 | .l1clk ( l1clk_pm1 ), | |
2096 | .din ( mb_addr[4:0]), | |
2097 | .dout ( mb_addr_out[4:0]), | |
2098 | .siclk(siclk), | |
2099 | .soclk(soclk)); | |
2100 | ||
2101 | ||
2102 | ||
2103 | // | |
2104 | // write enable | |
2105 | ||
2106 | l2t_msff_ctl_macro__width_6 out_wr_mb_arrays_reg ( | |
2107 | .scan_in(out_wr_mb_arrays_reg_scanin), | |
2108 | .scan_out(out_wr_mb_arrays_reg_scanout), | |
2109 | .l1clk ( l1clk_pm1 ), | |
2110 | .din ( { | |
2111 | mb_array_0_wr, | |
2112 | mb_array_1_wr, | |
2113 | mb_array_2_wr, | |
2114 | mb_array_3_wr, | |
2115 | mb_array_4_wr, | |
2116 | mb_array_5_wr | |
2117 | } ), | |
2118 | .dout ({ | |
2119 | mb_array_0_wr_out, | |
2120 | mb_array_1_wr_out, | |
2121 | mb_array_2_wr_out, | |
2122 | mb_array_3_wr_out, | |
2123 | mb_array_4_wr_out, | |
2124 | mb_array_5_wr_out | |
2125 | } ), | |
2126 | .siclk(siclk), | |
2127 | .soclk(soclk)); | |
2128 | ||
2129 | ||
2130 | ||
2131 | // read enable | |
2132 | ||
2133 | l2t_msff_ctl_macro__width_6 out_rd_mb_arrays_reg ( | |
2134 | .scan_in(out_rd_mb_arrays_reg_scanin), | |
2135 | .scan_out(out_rd_mb_arrays_reg_scanout), | |
2136 | .l1clk ( l1clk_pm1 ), | |
2137 | .din ( { | |
2138 | mb_array_0_rd, | |
2139 | mb_array_1_rd, | |
2140 | mb_array_2_rd, | |
2141 | mb_array_3_rd, | |
2142 | mb_array_4_rd, | |
2143 | mb_array_5_rd | |
2144 | } ), | |
2145 | .dout ({ | |
2146 | mb_array_0_rd_out, | |
2147 | mb_array_1_rd_out, | |
2148 | mb_array_2_rd_out, | |
2149 | mb_array_3_rd_out, | |
2150 | mb_array_4_rd_out, | |
2151 | mb_array_5_rd_out | |
2152 | } ), | |
2153 | .siclk(siclk), | |
2154 | .soclk(soclk)); | |
2155 | ||
2156 | ||
2157 | ||
2158 | // port name re-assignment | |
2159 | ||
2160 | ||
2161 | assign mb2_l2t_run =mb_run_out; | |
2162 | assign mb2_l2t_wdata[7:0] =mb_write_data_out[7:0]; | |
2163 | assign mb2_l2t_addr[4:0] =mb_addr_out[4:0]; | |
2164 | assign mb2_cmp_sel[3:0] =mb_cmpsel_out[3:0]; | |
2165 | assign l2t_mb2_fail =mb_fail_out; | |
2166 | assign l2t_mb2_done =mb_done_out; | |
2167 | ||
2168 | assign mb2_l2t_mbtag_wr_en =mb_array_0_wr_out; | |
2169 | assign mb2_l2t_fbtag_wr_en =mb_array_1_wr_out; | |
2170 | assign mb2_l2t_wbtag_wr_en =mb_array_2_wr_out; | |
2171 | assign mb2_l2t_rdmatag_wr_en =mb_array_3_wr_out; | |
2172 | assign mb2_l2t_mbdata_wr_en =mb_array_4_wr_out; | |
2173 | assign mb2_l2t_iqarray_wr_en =mb_array_5_wr_out; | |
2174 | ||
2175 | ||
2176 | assign mb2_l2t_mbtag_rd_en =mb_array_0_rd_out; | |
2177 | assign mb2_l2t_fbtag_rd_en =mb_array_1_rd_out; | |
2178 | assign mb2_l2t_wbtag_rd_en =mb_array_2_rd_out; | |
2179 | assign mb2_l2t_rdmatag_rd_en =mb_array_3_rd_out; | |
2180 | assign mb2_l2t_mbdata_rd_en =mb_array_4_rd_out; | |
2181 | assign mb2_l2t_iqarray_rd_en =mb_array_5_rd_out; | |
2182 | ||
2183 | ||
2184 | // spare gates: | |
2185 | ||
2186 | l2t_spare_ctl_macro__num_2 spares ( | |
2187 | .scan_in(spares_scanin), | |
2188 | .scan_out(spares_scanout), | |
2189 | .l1clk (l1clk_pm1), | |
2190 | .siclk(siclk), | |
2191 | .soclk(soclk) | |
2192 | ); | |
2193 | ||
2194 | ||
2195 | ||
2196 | supply0 vss; // <- port for ground | |
2197 | supply1 vdd; // <- port for power | |
2198 | // ///////////////////////////////////////////////////////////////////////////// | |
2199 | ||
2200 | // fixscan start: | |
2201 | assign array_usr_reg_scanin = scan_in ; | |
2202 | assign user_addr_mode_reg_scanin = array_usr_reg_scanout ; | |
2203 | assign user_start_addr_reg_scanin = user_addr_mode_reg_scanout; | |
2204 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
2205 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
2206 | assign user_data_mode_reg_scanin = user_incr_addr_reg_scanout; | |
2207 | assign user_data_reg_scanin = user_data_mode_reg_scanout; | |
2208 | assign user_cmpsel_hold_reg_scanin = user_data_reg_scanout ; | |
2209 | assign user_cmpsel_reg_scanin = user_cmpsel_hold_reg_scanout; | |
2210 | assign user_loop_mode_reg_scanin = user_cmpsel_reg_scanout ; | |
2211 | assign ten_n_mode_reg_scanin = user_loop_mode_reg_scanout; | |
2212 | assign user_cam_mode_reg_scanin = ten_n_mode_reg_scanout ; | |
2213 | assign user_cam_select_reg_scanin = user_cam_mode_reg_scanout; | |
2214 | assign user_cam_test_select_reg_scanin = user_cam_select_reg_scanout; | |
2215 | assign input_signals_reg_scanin = user_cam_test_select_reg_scanout; | |
2216 | assign mb_enable_reg_scanin = input_signals_reg_scanout; | |
2217 | assign config_reg_scanin = mb_enable_reg_scanout ; | |
2218 | assign loop_again_reg_scanin = config_reg_scanout ; | |
2219 | assign cam_cntl_reg_scanin = loop_again_reg_scanout ; | |
2220 | assign cam_shift_reg_scanin = cam_cntl_reg_scanout ; | |
2221 | assign end_shift_delay_reg_scanin = cam_shift_reg_scanout ; | |
2222 | assign cam_hit_reg_scanin = end_shift_delay_reg_scanout; | |
2223 | assign exp_cam_hit_delay_reg_scanin = cam_hit_reg_scanout ; | |
2224 | assign exp_cam_exp_delay_reg_scanin = exp_cam_hit_delay_reg_scanout; | |
2225 | assign cam_sel_delay_reg_scanin = exp_cam_exp_delay_reg_scanout; | |
2226 | assign mbist_output_reg_scanin = cam_sel_delay_reg_scanout; | |
2227 | assign mbist_output_delay1_reg_scanin = mbist_output_reg_scanout ; | |
2228 | assign cntl_reg_scanin = mbist_output_delay1_reg_scanout; | |
2229 | assign cseq_reg_scanin = cntl_reg_scanout ; | |
2230 | assign array_sel_reg_scanin = cseq_reg_scanout ; | |
2231 | assign cmp_sel_reg_scanin = array_sel_reg_scanout ; | |
2232 | assign marche_element_reg_scanin = cmp_sel_reg_scanout ; | |
2233 | assign user_bisi_wr_mode_reg_scanin = marche_element_reg_scanout; | |
2234 | assign user_bisi_rd_mode_reg_scanin = user_bisi_wr_mode_reg_scanout; | |
2235 | assign msb_latch_scanin = user_bisi_rd_mode_reg_scanout; | |
2236 | assign run3_transition_reg_scanin = msb_latch_scanout ; | |
2237 | assign done_delay_reg_scanin = run3_transition_reg_scanout; | |
2238 | assign mbist_fail_input_reg_scanin = done_delay_reg_scanout ; | |
2239 | assign out_mb_tcu_done_reg_scanin = mbist_fail_input_reg_scanout; | |
2240 | assign out_mb_tcu_fail_reg_scanin = out_mb_tcu_done_reg_scanout; | |
2241 | assign out_cmp_sel_reg_scanin = out_mb_tcu_fail_reg_scanout; | |
2242 | assign out_run_mb_arrays_reg_scanin = out_cmp_sel_reg_scanout ; | |
2243 | assign out_data_mb_arrays_reg_scanin = out_run_mb_arrays_reg_scanout; | |
2244 | assign out_addr_mb_arrays_reg_scanin = out_data_mb_arrays_reg_scanout; | |
2245 | assign out_wr_mb_arrays_reg_scanin = out_addr_mb_arrays_reg_scanout; | |
2246 | assign out_rd_mb_arrays_reg_scanin = out_wr_mb_arrays_reg_scanout; | |
2247 | assign spares_scanin = out_rd_mb_arrays_reg_scanout; | |
2248 | assign scan_out = spares_scanout ; | |
2249 | // fixscan end: | |
2250 | endmodule | |
2251 | ||
2252 | ||
2253 | ||
2254 | ||
2255 | ||
2256 | // any PARAMS parms go into naming of macro | |
2257 | ||
2258 | module l2t_msff_ctl_macro__width_10 ( | |
2259 | din, | |
2260 | l1clk, | |
2261 | scan_in, | |
2262 | siclk, | |
2263 | soclk, | |
2264 | dout, | |
2265 | scan_out); | |
2266 | wire [9:0] fdin; | |
2267 | wire [8:0] so; | |
2268 | ||
2269 | input [9:0] din; | |
2270 | input l1clk; | |
2271 | input scan_in; | |
2272 | ||
2273 | ||
2274 | input siclk; | |
2275 | input soclk; | |
2276 | ||
2277 | output [9:0] dout; | |
2278 | output scan_out; | |
2279 | assign fdin[9:0] = din[9:0]; | |
2280 | ||
2281 | ||
2282 | ||
2283 | ||
2284 | ||
2285 | ||
2286 | dff #(10) d0_0 ( | |
2287 | .l1clk(l1clk), | |
2288 | .siclk(siclk), | |
2289 | .soclk(soclk), | |
2290 | .d(fdin[9:0]), | |
2291 | .si({scan_in,so[8:0]}), | |
2292 | .so({so[8:0],scan_out}), | |
2293 | .q(dout[9:0]) | |
2294 | ); | |
2295 | ||
2296 | ||
2297 | ||
2298 | ||
2299 | ||
2300 | ||
2301 | ||
2302 | ||
2303 | ||
2304 | ||
2305 | ||
2306 | ||
2307 | endmodule | |
2308 | ||
2309 | ||
2310 | ||
2311 | ||
2312 | ||
2313 | ||
2314 | ||
2315 | // any PARAMS parms go into naming of macro | |
2316 | ||
2317 | module l2t_msff_ctl_macro__width_15 ( | |
2318 | din, | |
2319 | l1clk, | |
2320 | scan_in, | |
2321 | siclk, | |
2322 | soclk, | |
2323 | dout, | |
2324 | scan_out); | |
2325 | wire [14:0] fdin; | |
2326 | wire [13:0] so; | |
2327 | ||
2328 | input [14:0] din; | |
2329 | input l1clk; | |
2330 | input scan_in; | |
2331 | ||
2332 | ||
2333 | input siclk; | |
2334 | input soclk; | |
2335 | ||
2336 | output [14:0] dout; | |
2337 | output scan_out; | |
2338 | assign fdin[14:0] = din[14:0]; | |
2339 | ||
2340 | ||
2341 | ||
2342 | ||
2343 | ||
2344 | ||
2345 | dff #(15) d0_0 ( | |
2346 | .l1clk(l1clk), | |
2347 | .siclk(siclk), | |
2348 | .soclk(soclk), | |
2349 | .d(fdin[14:0]), | |
2350 | .si({scan_in,so[13:0]}), | |
2351 | .so({so[13:0],scan_out}), | |
2352 | .q(dout[14:0]) | |
2353 | ); | |
2354 | ||
2355 | ||
2356 | ||
2357 | ||
2358 | ||
2359 | ||
2360 | ||
2361 | ||
2362 | ||
2363 | ||
2364 | ||
2365 | ||
2366 | endmodule | |
2367 | ||
2368 | ||
2369 | ||
2370 | ||
2371 | // any PARAMS parms go into naming of macro | |
2372 | ||
2373 | module l2t_msff_ctl_macro__width_16 ( | |
2374 | din, | |
2375 | l1clk, | |
2376 | scan_in, | |
2377 | siclk, | |
2378 | soclk, | |
2379 | dout, | |
2380 | scan_out); | |
2381 | wire [15:0] fdin; | |
2382 | wire [14:0] so; | |
2383 | ||
2384 | input [15:0] din; | |
2385 | input l1clk; | |
2386 | input scan_in; | |
2387 | ||
2388 | ||
2389 | input siclk; | |
2390 | input soclk; | |
2391 | ||
2392 | output [15:0] dout; | |
2393 | output scan_out; | |
2394 | assign fdin[15:0] = din[15:0]; | |
2395 | ||
2396 | ||
2397 | ||
2398 | ||
2399 | ||
2400 | ||
2401 | dff #(16) d0_0 ( | |
2402 | .l1clk(l1clk), | |
2403 | .siclk(siclk), | |
2404 | .soclk(soclk), | |
2405 | .d(fdin[15:0]), | |
2406 | .si({scan_in,so[14:0]}), | |
2407 | .so({so[14:0],scan_out}), | |
2408 | .q(dout[15:0]) | |
2409 | ); | |
2410 | ||
2411 | ||
2412 | ||
2413 | ||
2414 | ||
2415 | ||
2416 | ||
2417 | ||
2418 | ||
2419 | ||
2420 | ||
2421 | ||
2422 | endmodule | |
2423 | ||
2424 | ||
2425 | ||
2426 | ||
2427 | ||
2428 | ||
2429 | ||
2430 | ||
2431 | // any PARAMS parms go into naming of macro | |
2432 | ||
2433 | module l2t_msff_ctl_macro__width_36 ( | |
2434 | din, | |
2435 | l1clk, | |
2436 | scan_in, | |
2437 | siclk, | |
2438 | soclk, | |
2439 | dout, | |
2440 | scan_out); | |
2441 | wire [35:0] fdin; | |
2442 | wire [34:0] so; | |
2443 | ||
2444 | input [35:0] din; | |
2445 | input l1clk; | |
2446 | input scan_in; | |
2447 | ||
2448 | ||
2449 | input siclk; | |
2450 | input soclk; | |
2451 | ||
2452 | output [35:0] dout; | |
2453 | output scan_out; | |
2454 | assign fdin[35:0] = din[35:0]; | |
2455 | ||
2456 | ||
2457 | ||
2458 | ||
2459 | ||
2460 | ||
2461 | dff #(36) d0_0 ( | |
2462 | .l1clk(l1clk), | |
2463 | .siclk(siclk), | |
2464 | .soclk(soclk), | |
2465 | .d(fdin[35:0]), | |
2466 | .si({scan_in,so[34:0]}), | |
2467 | .so({so[34:0],scan_out}), | |
2468 | .q(dout[35:0]) | |
2469 | ); | |
2470 | ||
2471 | ||
2472 | ||
2473 | ||
2474 | ||
2475 | ||
2476 | ||
2477 | ||
2478 | ||
2479 | ||
2480 | ||
2481 | ||
2482 | endmodule | |
2483 | ||
2484 | ||
2485 | ||
2486 | ||
2487 | ||
2488 | ||
2489 | // any PARAMS parms go into naming of macro | |
2490 | ||
2491 | module l2t_l1clkhdr_ctl_macro ( | |
2492 | l2clk, | |
2493 | l1en, | |
2494 | pce_ov, | |
2495 | stop, | |
2496 | se, | |
2497 | l1clk); | |
2498 | ||
2499 | ||
2500 | input l2clk; | |
2501 | input l1en; | |
2502 | input pce_ov; | |
2503 | input stop; | |
2504 | input se; | |
2505 | output l1clk; | |
2506 | ||
2507 | ||
2508 | ||
2509 | ||
2510 | ||
2511 | cl_sc1_l1hdr_8x c_0 ( | |
2512 | ||
2513 | ||
2514 | .l2clk(l2clk), | |
2515 | .pce(l1en), | |
2516 | .l1clk(l1clk), | |
2517 | .se(se), | |
2518 | .pce_ov(pce_ov), | |
2519 | .stop(stop) | |
2520 | ); | |
2521 | ||
2522 | ||
2523 | ||
2524 | endmodule | |
2525 | ||
2526 | ||
2527 | ||
2528 | ||
2529 | ||
2530 | ||
2531 | // any PARAMS parms go into naming of macro | |
2532 | ||
2533 | module l2t_msff_ctl_macro__width_4 ( | |
2534 | din, | |
2535 | l1clk, | |
2536 | scan_in, | |
2537 | siclk, | |
2538 | soclk, | |
2539 | dout, | |
2540 | scan_out); | |
2541 | wire [3:0] fdin; | |
2542 | wire [2:0] so; | |
2543 | ||
2544 | input [3:0] din; | |
2545 | input l1clk; | |
2546 | input scan_in; | |
2547 | ||
2548 | ||
2549 | input siclk; | |
2550 | input soclk; | |
2551 | ||
2552 | output [3:0] dout; | |
2553 | output scan_out; | |
2554 | assign fdin[3:0] = din[3:0]; | |
2555 | ||
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | dff #(4) d0_0 ( | |
2562 | .l1clk(l1clk), | |
2563 | .siclk(siclk), | |
2564 | .soclk(soclk), | |
2565 | .d(fdin[3:0]), | |
2566 | .si({scan_in,so[2:0]}), | |
2567 | .so({so[2:0],scan_out}), | |
2568 | .q(dout[3:0]) | |
2569 | ); | |
2570 | ||
2571 | ||
2572 | ||
2573 | ||
2574 | ||
2575 | ||
2576 | ||
2577 | ||
2578 | ||
2579 | ||
2580 | ||
2581 | ||
2582 | endmodule | |
2583 | ||
2584 | ||
2585 | ||
2586 | ||
2587 | ||
2588 | ||
2589 | // Description: Spare gate macro for control blocks | |
2590 | // | |
2591 | // Param num controls the number of times the macro is added | |
2592 | // flops=0 can be used to use only combination spare logic | |
2593 | ||
2594 | ||
2595 | module l2t_spare_ctl_macro__num_2 ( | |
2596 | l1clk, | |
2597 | scan_in, | |
2598 | siclk, | |
2599 | soclk, | |
2600 | scan_out); | |
2601 | wire si_0; | |
2602 | wire so_0; | |
2603 | wire spare0_flop_unused; | |
2604 | wire spare0_buf_32x_unused; | |
2605 | wire spare0_nand3_8x_unused; | |
2606 | wire spare0_inv_8x_unused; | |
2607 | wire spare0_aoi22_4x_unused; | |
2608 | wire spare0_buf_8x_unused; | |
2609 | wire spare0_oai22_4x_unused; | |
2610 | wire spare0_inv_16x_unused; | |
2611 | wire spare0_nand2_16x_unused; | |
2612 | wire spare0_nor3_4x_unused; | |
2613 | wire spare0_nand2_8x_unused; | |
2614 | wire spare0_buf_16x_unused; | |
2615 | wire spare0_nor2_16x_unused; | |
2616 | wire spare0_inv_32x_unused; | |
2617 | wire si_1; | |
2618 | wire so_1; | |
2619 | wire spare1_flop_unused; | |
2620 | wire spare1_buf_32x_unused; | |
2621 | wire spare1_nand3_8x_unused; | |
2622 | wire spare1_inv_8x_unused; | |
2623 | wire spare1_aoi22_4x_unused; | |
2624 | wire spare1_buf_8x_unused; | |
2625 | wire spare1_oai22_4x_unused; | |
2626 | wire spare1_inv_16x_unused; | |
2627 | wire spare1_nand2_16x_unused; | |
2628 | wire spare1_nor3_4x_unused; | |
2629 | wire spare1_nand2_8x_unused; | |
2630 | wire spare1_buf_16x_unused; | |
2631 | wire spare1_nor2_16x_unused; | |
2632 | wire spare1_inv_32x_unused; | |
2633 | ||
2634 | ||
2635 | input l1clk; | |
2636 | input scan_in; | |
2637 | input siclk; | |
2638 | input soclk; | |
2639 | output scan_out; | |
2640 | ||
2641 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
2642 | .siclk(siclk), | |
2643 | .soclk(soclk), | |
2644 | .si(si_0), | |
2645 | .so(so_0), | |
2646 | .d(1'b0), | |
2647 | .q(spare0_flop_unused)); | |
2648 | assign si_0 = scan_in; | |
2649 | ||
2650 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
2651 | .out(spare0_buf_32x_unused)); | |
2652 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
2653 | .in1(1'b1), | |
2654 | .in2(1'b1), | |
2655 | .out(spare0_nand3_8x_unused)); | |
2656 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
2657 | .out(spare0_inv_8x_unused)); | |
2658 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
2659 | .in01(1'b1), | |
2660 | .in10(1'b1), | |
2661 | .in11(1'b1), | |
2662 | .out(spare0_aoi22_4x_unused)); | |
2663 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
2664 | .out(spare0_buf_8x_unused)); | |
2665 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
2666 | .in01(1'b1), | |
2667 | .in10(1'b1), | |
2668 | .in11(1'b1), | |
2669 | .out(spare0_oai22_4x_unused)); | |
2670 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
2671 | .out(spare0_inv_16x_unused)); | |
2672 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
2673 | .in1(1'b1), | |
2674 | .out(spare0_nand2_16x_unused)); | |
2675 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
2676 | .in1(1'b0), | |
2677 | .in2(1'b0), | |
2678 | .out(spare0_nor3_4x_unused)); | |
2679 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
2680 | .in1(1'b1), | |
2681 | .out(spare0_nand2_8x_unused)); | |
2682 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
2683 | .out(spare0_buf_16x_unused)); | |
2684 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
2685 | .in1(1'b0), | |
2686 | .out(spare0_nor2_16x_unused)); | |
2687 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
2688 | .out(spare0_inv_32x_unused)); | |
2689 | ||
2690 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
2691 | .siclk(siclk), | |
2692 | .soclk(soclk), | |
2693 | .si(si_1), | |
2694 | .so(so_1), | |
2695 | .d(1'b0), | |
2696 | .q(spare1_flop_unused)); | |
2697 | assign si_1 = so_0; | |
2698 | ||
2699 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
2700 | .out(spare1_buf_32x_unused)); | |
2701 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
2702 | .in1(1'b1), | |
2703 | .in2(1'b1), | |
2704 | .out(spare1_nand3_8x_unused)); | |
2705 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
2706 | .out(spare1_inv_8x_unused)); | |
2707 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
2708 | .in01(1'b1), | |
2709 | .in10(1'b1), | |
2710 | .in11(1'b1), | |
2711 | .out(spare1_aoi22_4x_unused)); | |
2712 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
2713 | .out(spare1_buf_8x_unused)); | |
2714 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
2715 | .in01(1'b1), | |
2716 | .in10(1'b1), | |
2717 | .in11(1'b1), | |
2718 | .out(spare1_oai22_4x_unused)); | |
2719 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
2720 | .out(spare1_inv_16x_unused)); | |
2721 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
2722 | .in1(1'b1), | |
2723 | .out(spare1_nand2_16x_unused)); | |
2724 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
2725 | .in1(1'b0), | |
2726 | .in2(1'b0), | |
2727 | .out(spare1_nor3_4x_unused)); | |
2728 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
2729 | .in1(1'b1), | |
2730 | .out(spare1_nand2_8x_unused)); | |
2731 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
2732 | .out(spare1_buf_16x_unused)); | |
2733 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
2734 | .in1(1'b0), | |
2735 | .out(spare1_nor2_16x_unused)); | |
2736 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
2737 | .out(spare1_inv_32x_unused)); | |
2738 | assign scan_out = so_1; | |
2739 | ||
2740 | ||
2741 | ||
2742 | endmodule | |
2743 | ||
2744 | ||
2745 | ||
2746 | // any PARAMS parms go into naming of macro | |
2747 | ||
2748 | module l2t_msff_ctl_macro__width_1 ( | |
2749 | din, | |
2750 | l1clk, | |
2751 | scan_in, | |
2752 | siclk, | |
2753 | soclk, | |
2754 | dout, | |
2755 | scan_out); | |
2756 | wire [0:0] fdin; | |
2757 | ||
2758 | input [0:0] din; | |
2759 | input l1clk; | |
2760 | input scan_in; | |
2761 | ||
2762 | ||
2763 | input siclk; | |
2764 | input soclk; | |
2765 | ||
2766 | output [0:0] dout; | |
2767 | output scan_out; | |
2768 | assign fdin[0:0] = din[0:0]; | |
2769 | ||
2770 | ||
2771 | ||
2772 | ||
2773 | ||
2774 | ||
2775 | dff #(1) d0_0 ( | |
2776 | .l1clk(l1clk), | |
2777 | .siclk(siclk), | |
2778 | .soclk(soclk), | |
2779 | .d(fdin[0:0]), | |
2780 | .si(scan_in), | |
2781 | .so(scan_out), | |
2782 | .q(dout[0:0]) | |
2783 | ); | |
2784 | ||
2785 | ||
2786 | ||
2787 | ||
2788 | ||
2789 | ||
2790 | ||
2791 | ||
2792 | ||
2793 | ||
2794 | ||
2795 | ||
2796 | endmodule | |
2797 | ||
2798 | ||
2799 | ||
2800 | ||
2801 | // any PARAMS parms go into naming of macro | |
2802 | ||
2803 | module l2t_msff_ctl_macro__width_2 ( | |
2804 | din, | |
2805 | l1clk, | |
2806 | scan_in, | |
2807 | siclk, | |
2808 | soclk, | |
2809 | dout, | |
2810 | scan_out); | |
2811 | wire [1:0] fdin; | |
2812 | wire [0:0] so; | |
2813 | ||
2814 | input [1:0] din; | |
2815 | input l1clk; | |
2816 | input scan_in; | |
2817 | ||
2818 | ||
2819 | input siclk; | |
2820 | input soclk; | |
2821 | ||
2822 | output [1:0] dout; | |
2823 | output scan_out; | |
2824 | assign fdin[1:0] = din[1:0]; | |
2825 | ||
2826 | ||
2827 | ||
2828 | ||
2829 | ||
2830 | ||
2831 | dff #(2) d0_0 ( | |
2832 | .l1clk(l1clk), | |
2833 | .siclk(siclk), | |
2834 | .soclk(soclk), | |
2835 | .d(fdin[1:0]), | |
2836 | .si({scan_in,so[0:0]}), | |
2837 | .so({so[0:0],scan_out}), | |
2838 | .q(dout[1:0]) | |
2839 | ); | |
2840 | ||
2841 | ||
2842 | ||
2843 | ||
2844 | ||
2845 | ||
2846 | ||
2847 | ||
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | endmodule | |
2853 | ||
2854 | ||
2855 | ||
2856 | // any PARAMS parms go into naming of macro | |
2857 | ||
2858 | module l2t_msff_ctl_macro__width_39 ( | |
2859 | din, | |
2860 | l1clk, | |
2861 | scan_in, | |
2862 | siclk, | |
2863 | soclk, | |
2864 | dout, | |
2865 | scan_out); | |
2866 | wire [38:0] fdin; | |
2867 | wire [37:0] so; | |
2868 | ||
2869 | input [38:0] din; | |
2870 | input l1clk; | |
2871 | input scan_in; | |
2872 | ||
2873 | ||
2874 | input siclk; | |
2875 | input soclk; | |
2876 | ||
2877 | output [38:0] dout; | |
2878 | output scan_out; | |
2879 | assign fdin[38:0] = din[38:0]; | |
2880 | ||
2881 | ||
2882 | ||
2883 | ||
2884 | ||
2885 | ||
2886 | dff #(39) d0_0 ( | |
2887 | .l1clk(l1clk), | |
2888 | .siclk(siclk), | |
2889 | .soclk(soclk), | |
2890 | .d(fdin[38:0]), | |
2891 | .si({scan_in,so[37:0]}), | |
2892 | .so({so[37:0],scan_out}), | |
2893 | .q(dout[38:0]) | |
2894 | ); | |
2895 | ||
2896 | ||
2897 | ||
2898 | ||
2899 | ||
2900 | ||
2901 | ||
2902 | ||
2903 | ||
2904 | ||
2905 | ||
2906 | ||
2907 | endmodule | |
2908 | ||
2909 | ||
2910 | ||
2911 | // any PARAMS parms go into naming of macro | |
2912 | ||
2913 | module l2t_msff_ctl_macro__width_50 ( | |
2914 | din, | |
2915 | l1clk, | |
2916 | scan_in, | |
2917 | siclk, | |
2918 | soclk, | |
2919 | dout, | |
2920 | scan_out); | |
2921 | wire [49:0] fdin; | |
2922 | wire [48:0] so; | |
2923 | ||
2924 | input [49:0] din; | |
2925 | input l1clk; | |
2926 | input scan_in; | |
2927 | ||
2928 | ||
2929 | input siclk; | |
2930 | input soclk; | |
2931 | ||
2932 | output [49:0] dout; | |
2933 | output scan_out; | |
2934 | assign fdin[49:0] = din[49:0]; | |
2935 | ||
2936 | ||
2937 | ||
2938 | ||
2939 | ||
2940 | ||
2941 | dff #(50) d0_0 ( | |
2942 | .l1clk(l1clk), | |
2943 | .siclk(siclk), | |
2944 | .soclk(soclk), | |
2945 | .d(fdin[49:0]), | |
2946 | .si({scan_in,so[48:0]}), | |
2947 | .so({so[48:0],scan_out}), | |
2948 | .q(dout[49:0]) | |
2949 | ); | |
2950 | ||
2951 | ||
2952 | ||
2953 | ||
2954 | ||
2955 | ||
2956 | ||
2957 | ||
2958 | ||
2959 | ||
2960 | ||
2961 | ||
2962 | endmodule | |
2963 | ||
2964 | ||
2965 | ||
2966 | ||
2967 | ||
2968 | ||
2969 | // any PARAMS parms go into naming of macro | |
2970 | ||
2971 | module l2t_msff_ctl_macro__width_65 ( | |
2972 | din, | |
2973 | l1clk, | |
2974 | scan_in, | |
2975 | siclk, | |
2976 | soclk, | |
2977 | dout, | |
2978 | scan_out); | |
2979 | wire [64:0] fdin; | |
2980 | wire [63:0] so; | |
2981 | ||
2982 | input [64:0] din; | |
2983 | input l1clk; | |
2984 | input scan_in; | |
2985 | ||
2986 | ||
2987 | input siclk; | |
2988 | input soclk; | |
2989 | ||
2990 | output [64:0] dout; | |
2991 | output scan_out; | |
2992 | assign fdin[64:0] = din[64:0]; | |
2993 | ||
2994 | ||
2995 | ||
2996 | ||
2997 | ||
2998 | ||
2999 | dff #(65) d0_0 ( | |
3000 | .l1clk(l1clk), | |
3001 | .siclk(siclk), | |
3002 | .soclk(soclk), | |
3003 | .d(fdin[64:0]), | |
3004 | .si({scan_in,so[63:0]}), | |
3005 | .so({so[63:0],scan_out}), | |
3006 | .q(dout[64:0]) | |
3007 | ); | |
3008 | ||
3009 | ||
3010 | ||
3011 | ||
3012 | ||
3013 | ||
3014 | ||
3015 | ||
3016 | ||
3017 | ||
3018 | ||
3019 | ||
3020 | endmodule | |
3021 | ||
3022 | ||
3023 | ||
3024 | ||
3025 | ||
3026 | // any PARAMS parms go into naming of macro | |
3027 | ||
3028 | module l2t_msff_ctl_macro__width_7 ( | |
3029 | din, | |
3030 | l1clk, | |
3031 | scan_in, | |
3032 | siclk, | |
3033 | soclk, | |
3034 | dout, | |
3035 | scan_out); | |
3036 | wire [6:0] fdin; | |
3037 | wire [5:0] so; | |
3038 | ||
3039 | input [6:0] din; | |
3040 | input l1clk; | |
3041 | input scan_in; | |
3042 | ||
3043 | ||
3044 | input siclk; | |
3045 | input soclk; | |
3046 | ||
3047 | output [6:0] dout; | |
3048 | output scan_out; | |
3049 | assign fdin[6:0] = din[6:0]; | |
3050 | ||
3051 | ||
3052 | ||
3053 | ||
3054 | ||
3055 | ||
3056 | dff #(7) d0_0 ( | |
3057 | .l1clk(l1clk), | |
3058 | .siclk(siclk), | |
3059 | .soclk(soclk), | |
3060 | .d(fdin[6:0]), | |
3061 | .si({scan_in,so[5:0]}), | |
3062 | .so({so[5:0],scan_out}), | |
3063 | .q(dout[6:0]) | |
3064 | ); | |
3065 | ||
3066 | ||
3067 | ||
3068 | ||
3069 | ||
3070 | ||
3071 | ||
3072 | ||
3073 | ||
3074 | ||
3075 | ||
3076 | ||
3077 | endmodule | |
3078 | ||
3079 | ||
3080 | ||
3081 | ||
3082 | ||
3083 | // any PARAMS parms go into naming of macro | |
3084 | ||
3085 | module l2t_msff_ctl_macro__width_8 ( | |
3086 | din, | |
3087 | l1clk, | |
3088 | scan_in, | |
3089 | siclk, | |
3090 | soclk, | |
3091 | dout, | |
3092 | scan_out); | |
3093 | wire [7:0] fdin; | |
3094 | wire [6:0] so; | |
3095 | ||
3096 | input [7:0] din; | |
3097 | input l1clk; | |
3098 | input scan_in; | |
3099 | ||
3100 | ||
3101 | input siclk; | |
3102 | input soclk; | |
3103 | ||
3104 | output [7:0] dout; | |
3105 | output scan_out; | |
3106 | assign fdin[7:0] = din[7:0]; | |
3107 | ||
3108 | ||
3109 | ||
3110 | ||
3111 | ||
3112 | ||
3113 | dff #(8) d0_0 ( | |
3114 | .l1clk(l1clk), | |
3115 | .siclk(siclk), | |
3116 | .soclk(soclk), | |
3117 | .d(fdin[7:0]), | |
3118 | .si({scan_in,so[6:0]}), | |
3119 | .so({so[6:0],scan_out}), | |
3120 | .q(dout[7:0]) | |
3121 | ); | |
3122 | ||
3123 | ||
3124 | ||
3125 | ||
3126 | ||
3127 | ||
3128 | ||
3129 | ||
3130 | ||
3131 | ||
3132 | ||
3133 | ||
3134 | endmodule | |
3135 | ||
3136 | ||
3137 | ||
3138 | // any PARAMS parms go into naming of macro | |
3139 | ||
3140 | module l2t_msff_ctl_macro__width_5 ( | |
3141 | din, | |
3142 | l1clk, | |
3143 | scan_in, | |
3144 | siclk, | |
3145 | soclk, | |
3146 | dout, | |
3147 | scan_out); | |
3148 | wire [4:0] fdin; | |
3149 | wire [3:0] so; | |
3150 | ||
3151 | input [4:0] din; | |
3152 | input l1clk; | |
3153 | input scan_in; | |
3154 | ||
3155 | ||
3156 | input siclk; | |
3157 | input soclk; | |
3158 | ||
3159 | output [4:0] dout; | |
3160 | output scan_out; | |
3161 | assign fdin[4:0] = din[4:0]; | |
3162 | ||
3163 | ||
3164 | ||
3165 | ||
3166 | ||
3167 | ||
3168 | dff #(5) d0_0 ( | |
3169 | .l1clk(l1clk), | |
3170 | .siclk(siclk), | |
3171 | .soclk(soclk), | |
3172 | .d(fdin[4:0]), | |
3173 | .si({scan_in,so[3:0]}), | |
3174 | .so({so[3:0],scan_out}), | |
3175 | .q(dout[4:0]) | |
3176 | ); | |
3177 | ||
3178 | ||
3179 | ||
3180 | ||
3181 | ||
3182 | ||
3183 | ||
3184 | ||
3185 | ||
3186 | ||
3187 | ||
3188 | ||
3189 | endmodule | |
3190 | ||
3191 | ||
3192 | ||
3193 | ||
3194 | ||
3195 | ||
3196 | ||
3197 | // any PARAMS parms go into naming of macro | |
3198 | ||
3199 | module l2t_msff_ctl_macro__width_6 ( | |
3200 | din, | |
3201 | l1clk, | |
3202 | scan_in, | |
3203 | siclk, | |
3204 | soclk, | |
3205 | dout, | |
3206 | scan_out); | |
3207 | wire [5:0] fdin; | |
3208 | wire [4:0] so; | |
3209 | ||
3210 | input [5:0] din; | |
3211 | input l1clk; | |
3212 | input scan_in; | |
3213 | ||
3214 | ||
3215 | input siclk; | |
3216 | input soclk; | |
3217 | ||
3218 | output [5:0] dout; | |
3219 | output scan_out; | |
3220 | assign fdin[5:0] = din[5:0]; | |
3221 | ||
3222 | ||
3223 | ||
3224 | ||
3225 | ||
3226 | ||
3227 | dff #(6) d0_0 ( | |
3228 | .l1clk(l1clk), | |
3229 | .siclk(siclk), | |
3230 | .soclk(soclk), | |
3231 | .d(fdin[5:0]), | |
3232 | .si({scan_in,so[4:0]}), | |
3233 | .so({so[4:0],scan_out}), | |
3234 | .q(dout[5:0]) | |
3235 | ); | |
3236 | ||
3237 | ||
3238 | ||
3239 | ||
3240 | ||
3241 | ||
3242 | ||
3243 | ||
3244 | ||
3245 | ||
3246 | ||
3247 | ||
3248 | endmodule | |
3249 | ||
3250 | ||
3251 | ||
3252 | ||
3253 | // any PARAMS parms go into naming of macro | |
3254 | ||
3255 | module l2t_msff_ctl_macro__width_3 ( | |
3256 | din, | |
3257 | l1clk, | |
3258 | scan_in, | |
3259 | siclk, | |
3260 | soclk, | |
3261 | dout, | |
3262 | scan_out); | |
3263 | wire [2:0] fdin; | |
3264 | wire [1:0] so; | |
3265 | ||
3266 | input [2:0] din; | |
3267 | input l1clk; | |
3268 | input scan_in; | |
3269 | ||
3270 | ||
3271 | input siclk; | |
3272 | input soclk; | |
3273 | ||
3274 | output [2:0] dout; | |
3275 | output scan_out; | |
3276 | assign fdin[2:0] = din[2:0]; | |
3277 | ||
3278 | ||
3279 | ||
3280 | ||
3281 | ||
3282 | ||
3283 | dff #(3) d0_0 ( | |
3284 | .l1clk(l1clk), | |
3285 | .siclk(siclk), | |
3286 | .soclk(soclk), | |
3287 | .d(fdin[2:0]), | |
3288 | .si({scan_in,so[1:0]}), | |
3289 | .so({so[1:0],scan_out}), | |
3290 | .q(dout[2:0]) | |
3291 | ); | |
3292 | ||
3293 | ||
3294 | ||
3295 | ||
3296 | ||
3297 | ||
3298 | ||
3299 | ||
3300 | ||
3301 | ||
3302 | ||
3303 | ||
3304 | endmodule | |
3305 | ||
3306 | ||
3307 |