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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_misbuf_ctl.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_misbuf_ctl.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016
1017////////////////////////////////////////////////////////////////////////
1018// Local header file includes / local defines
1019// Update on 3/10/2003: Added a gate_off_par_err_c2 signal to gate off
1020// par error insertion when an instruction actually
1021// hits the $ or FB. However if an instruction is inserted
1022// due to another reason, then tagd_par_err_c2 is used
1023// for all other purposes.
1024////////////////////////////////////////////////////////////////////////
1025
1026module l2t_misbuf_ctl (
1027 tcu_pce_ov,
1028 tcu_aclk,
1029 tcu_bclk,
1030 tcu_scan_en,
1031 tag_miss_unqual_c2,
1032 tag_store_inst_c3,
1033 tag_hit_unqual_c2,
1034 tag_hit_c3,
1035 tag_lru_way_c4,
1036 tag_rdma_vld_px0_p,
1037 tag_misbuf_rdma_reg_vld_c2,
1038 tag_hit_not_comp_c3,
1039 tag_alt_tag_miss_unqual_c3,
1040 tag_misbuf_int_ack_c3,
1041 arb_pf_ice_inst_c2,
1042 arbdec_pf_ice_inst_c1,
1043 arb_inst_vld_c2,
1044 arb_pf_ice_inst_c7,
1045 arb_decdp_ld_inst_c2,
1046 arb_decdp_imiss_inst_c2,
1047 arb_decdp_swap_inst_c2,
1048 arb_arbdp_pst_with_ctrue_c2,
1049 arb_arbdp_misbuf_pst_no_ctrue_c2,
1050 arb_decdp_cas2_inst_c2,
1051 arbdec_arbdp_inst_mb_c2,
1052 arb_decdp_pst_inst_c2,
1053 arb_decdp_cas1_inst_c2,
1054 arbdec_arbdp_inst_mb_entry_c1,
1055 arb_arbdp_tecc_inst_mb_c8,
1056 arbdec_arbdp_rdma_inst_c1,
1057 arb_decdp_ld64_inst_c2,
1058 arb_decdp_wr64_inst_c2,
1059 arb_decdp_bis_inst_c3,
1060 arbdec_arbdp_inst_bufidhi_c8,
1061 arb_decdp_wr8_inst_c2,
1062 arb_csr_st_c2,
1063 arb_evict_vld_c2,
1064 arb_misbuf_inst_vld_c2,
1065 arb_pst_ctrue_en_c8,
1066 arb_misbuf_hit_off_c1,
1067 arb_evict_tecc_vld_c2,
1068 arbdec_arbdp_inst_dep_c2,
1069 arb_vuad_ce_err_c2,
1070 usaloc_ua_ce_c2,
1071 vlddir_vd_ce_c2,
1072 misbuf_vuad_ce_err_c6,
1073 misbuf_vuad_ce_instr_c2,
1074 misbuf_vuad_ce_instr_ack_c2,
1075 arb_decdp_cas2_from_mb_c2,
1076 arbadr_arbdp_addr_c1c2comp_c1,
1077 arbadr_arbdp_addr_c1c3comp_c1,
1078 arbadr_idx_c1c2comp_c1,
1079 arbadr_idx_c1c3comp_c1,
1080 arb_misbuf_cas1_hit_c8,
1081 arb_misbuf_ctrue_c9,
1082 arb_misbuf_mbsel_c1,
1083 mb_cam_match,
1084 mb_cam_match_idx,
1085 deccck_uncorr_err_c8,
1086 deccck_notdata_err_c8,
1087 deccck_spcd_corr_err_c8,
1088 deccck_spcfb_corr_err_c8,
1089 filbuf_misbuf_match_c2,
1090 filbuf_misbuf_stinst_match_c2,
1091 filbuf_misbuf_entry_avail,
1092 filbuf_fbf_ready_miss_r1,
1093 filbuf_fbf_enc_ld_mbid_r1,
1094 filbuf_fbf_st_or_dep_rdy_c4,
1095 filbuf_fbf_enc_dep_mbid_c4,
1096 filbuf_fb_count_eq_0,
1097 filbuf_misbuf_fbid_d2,
1098 filbuf_misbuf_nofill_d2,
1099 filbuf_misbuf_ue_offmode_c7,
1100 filbuf_misbuf_ce_offmode_c7,
1101 wbuf_hit_unqual_c2,
1102 wbuf_misbuf_dep_rdy_en,
1103 wbuf_misbuf_dep_mbid,
1104 rdmat_hit_unqual_c2,
1105 rdmat_misbuf_dep_mbid,
1106 rdmat_misbuf_dep_rdy_en,
1107 tag_misbuf_par_err_c3,
1108 mcu_l2t_rd_ack,
1109 csr_l2_bypass_mode_on,
1110 csr_l2_dir_map_on,
1111 l2clk,
1112 wmr_l,
1113 scan_in,
1114 arb_tecc_c2,
1115 scan_out,
1116 misbuf_hit_st_dep_zero,
1117 misbuf_arb_cnt28_px2_prev,
1118 misbuf_arb_snp_cnt8_px1,
1119 misbuf_arb_vld_px1,
1120 misbuf_nondep_fbhit_c3,
1121 misbuf_hit_c3,
1122 misbuf_arb_hit_c3,
1123 arb_misbuf_inval_inst_c2,
1124 filbuf_match_c3,
1125 misbuf_arbdp_ctrue_px2,
1126 misbuf_arb_l2rd_en,
1127 misbuf_arb_mcurd_en,
1128 misbuf_tag_hit_unqual_c2,
1129 misbuf_corr_err_c2,
1130 misbuf_uncorr_err_c2,
1131 misbuf_notdata_err_c2,
1132 misbuf_wr64_miss_comp_c3,
1133 misbuf_wbuf_mbid_c4,
1134 misbuf_mbf_insert_mbid_c4,
1135 misbuf_mbf_insert_c4,
1136 misbuf_hit_c4,
1137 misbuf_mbf_delete_c4,
1138 misbuf_filbuf_next_vld_c4,
1139 misbuf_filbuf_next_link_c4,
1140 misbuf_filbuf_mcu_pick,
1141 misbuf_filbuf_fbid,
1142 misbuf_filbuf_way,
1143 misbuf_filbuf_way_fbid_vld,
1144 filbuf_tag_hit_frm_mb_c2,
1145 misbuf_mbtag_wr_en_c2,
1146 misbuf_mb_write_wl,
1147 misbuf_buf_rd_en,
1148 misbuf_mb_read_wl,
1149 misbuf_dep_c8,
1150 misbuf_mb_data_write_wl,
1151 misbuf_evict_c8,
1152 misbuf_tecc_c8,
1153 misbuf_mbentry_c8,
1154 misbuf_mbdata_wr_en_c8,
1155 misbuf_notdata_err_c1,
1156 misbuf_uncorr_err_c1,
1157 l2t_mcu_rd_req,
1158 l2t_mcu_rd_dummy_req,
1159 l2t_mb2_mbdata_wr_en,
1160 l2t_mb2_run,
1161 l2t_mb2_mbdata_rd_en,
1162 l2t_mb2_mbtag_rd_en,
1163 l2t_mb2_mbtag_wr_en,
1164 l2t_mb2_addr,
1165 mb_mbist_cam_hit,
1166 mbtag_mbist_cam_sel,
1167 misbuf_vuad_ce_err_c8);
1168wire pce_ov;
1169wire siclk;
1170wire soclk;
1171wire stop;
1172wire se;
1173wire l1clk;
1174wire vuad_err_true_c2;
1175wire vuad_err_true_c3;
1176wire spares_scanout;
1177wire dbginit_l;
1178wire reset_flop_scanin;
1179wire reset_flop_scanout;
1180wire arb_vuad_ce_err_c2_qual;
1181wire ff_l2t_mbist_r1_scanin;
1182wire ff_l2t_mbist_r1_scanout;
1183wire l2t_mb2_mbdata_wr_en_r1;
1184wire l2t_mb2_mbtag_rd_en_r1;
1185wire l2t_mb2_mbtag_wr_en_r1;
1186wire l2t_mb2_mbdata_rd_en_r1;
1187wire [4:0] l2t_mb2_addr_r1;
1188wire l2t_mb2_mbdata_wr_en_r2;
1189wire mbtag_mbist_cam_sel_r1;
1190wire l2t_mb2_run_r1;
1191wire l2t_mb2_mbtag_rd_en_r2;
1192wire l2t_mb2_mbtag_wr_en_r2;
1193wire l2t_mb2_mbdata_rd_en_r2;
1194wire [4:0] l2t_mb2_addr_r2;
1195wire misbuf_vuad_ce_err_log_c2;
1196wire ff_loggingerr_scanin;
1197wire ff_loggingerr_scanout;
1198wire misbuf_vuad_ce_err_log_c3;
1199wire misbuf_vuad_ce_err_log_c4;
1200wire misbuf_vuad_ce_err_log_c5;
1201wire misbuf_vuad_ce_err_log_c52;
1202wire misbuf_vuad_ce_err_log_c6;
1203wire misbuf_vuad_ce_err_log_c7;
1204wire ff_tag_hit_unqual_c3_scanin;
1205wire ff_tag_hit_unqual_c3_scanout;
1206wire ff_mbf_insert_c3_scanin;
1207wire ff_mbf_insert_c3_scanout;
1208wire ff_mbf_insert_c3_1_scanin;
1209wire ff_mbf_insert_c3_1_scanout;
1210wire mbf_insert_c3_tmp_1_clone;
1211wire ff_inst_mb_c3_1_scanin;
1212wire ff_inst_mb_c3_1_scanout;
1213wire ff_arb_vuad_ce_err_c3_scanin;
1214wire ff_arb_vuad_ce_err_c3_scanout;
1215wire arb_vuad_ce_err_c3;
1216wire ff_mbf_delete_c3_scanin;
1217wire ff_mbf_delete_c3_scanout;
1218wire mbf_delete_c3_tmp;
1219wire ff_mbf_delete_c3_1_scanin;
1220wire ff_mbf_delete_c3_1_scanout;
1221wire mbf_delete_c3_tmp_1_clone;
1222wire arb_pf_ice_inst_c3;
1223wire misbuf_tag_hit_unqual_c2_internal;
1224wire ff_mbctl_nondep_fbhit_c3_scanin;
1225wire ff_mbctl_nondep_fbhit_c3_scanout;
1226wire [31:0] mbtag_write_ptr;
1227wire ff_mb_count_c4_scanin;
1228wire ff_mb_count_c4_scanout;
1229wire ff_rdma_inst_c2_scanin;
1230wire ff_rdma_inst_c2_scanout;
1231wire ff_rdma_inst_c3_scanin;
1232wire ff_rdma_inst_c3_scanout;
1233wire ff_mb_rdma_count_c4_scanin;
1234wire ff_mb_rdma_count_c4_scanout;
1235wire ff_inst_mb_entry_c2_scanin;
1236wire ff_inst_mb_entry_c2_scanout;
1237wire mb_mbist_cam_hit_unreg;
1238wire ff_mb_mbist_cam_match_scanin;
1239wire ff_mb_mbist_cam_match_scanout;
1240wire [31:0] mb_cam_match_reg;
1241wire ff_l2_dir_map_on_d1_scanin;
1242wire ff_l2_dir_map_on_d1_scanout;
1243wire ff_tmp_cam_hit_vec_c2_scanin;
1244wire ff_tmp_cam_hit_vec_c2_scanout;
1245wire ff_tmp_idx_hit_vec_c2_scanin;
1246wire ff_tmp_idx_hit_vec_c2_scanout;
1247wire ff_misbuf_c1c2_match_c1_d1_scanin;
1248wire ff_misbuf_c1c2_match_c1_d1_scanout;
1249wire ff_misbuf_c1c2_match_c1_d1_1_scanin;
1250wire ff_misbuf_c1c2_match_c1_d1_1_scanout;
1251wire misbuf_c1c2_match_c1_d1_1_clone;
1252wire ff_mb_hit_off_c1_d1_scanin;
1253wire ff_mb_hit_off_c1_d1_scanout;
1254wire mb_hit_off_c1_d1_clone;
1255wire ff_misbuf_hit_vec_c3_scanin;
1256wire ff_misbuf_hit_vec_c3_scanout;
1257wire tmp_cam_hit_c2_or_all;
1258wire tmp_hit_unqual_c2_cloned;
1259wire inst_mb_c3_2_clone;
1260wire mb_inst_vld_c3_2_clone;
1261wire tmp_cam_hit_c2_clone;
1262wire ff_idx_c1c2comp_c1_d1_scanin;
1263wire ff_idx_c1c2comp_c1_d1_scanout;
1264wire arbadr_idx_c1c2comp_c1_d1;
1265wire ff_misbuf_idx_hit_vec_c3_scanin;
1266wire ff_misbuf_idx_hit_vec_c3_scanout;
1267wire [1:0] cout6;
1268wire [1:0] cout7;
1269wire [1:0] cout8;
1270wire [1:0] cout9;
1271wire [1:0] cout10;
1272wire ff_hit_count_c4_scanin;
1273wire ff_hit_count_c4_scanout;
1274wire ff_mb_idx_count_full_c5_scanin;
1275wire ff_mb_idx_count_full_c5_scanout;
1276wire ff_inst_mb_c3_scanin;
1277wire ff_inst_mb_c3_scanout;
1278wire ff_inst_mb_c3_2_scanin;
1279wire ff_inst_mb_c3_2_scanout;
1280wire ff_mb_inst_vld_c3_scanin;
1281wire ff_mb_inst_vld_c3_scanout;
1282wire ff_mb_inst_vld_c3_1_scanin;
1283wire ff_mb_inst_vld_c3_1_scanout;
1284wire ff_mb_inst_vld_staging_scanin;
1285wire ff_mb_inst_vld_staging_scanout;
1286wire misbuf_inst_c4;
1287wire misbuf_inst_c5;
1288wire misbuf_inst_c52;
1289wire misbuf_inst_c6;
1290wire misbuf_inst_c7;
1291wire misbuf_inst_c8;
1292wire ff_mb_inst_vld_c3_2_scanin;
1293wire ff_mb_inst_vld_c3_2_scanout;
1294wire ff_mb_rewrite_en_c4_scanin;
1295wire ff_mb_rewrite_en_c4_scanout;
1296wire ff_mb_rewrite_en_c5_scanin;
1297wire ff_mb_rewrite_en_c5_scanout;
1298wire ff_mb_rewrite_en_c52_scanin;
1299wire ff_mb_rewrite_en_c52_scanout;
1300wire mb_rewrite_en_c52;
1301wire ff_mb_rewrite_en_c6_scanin;
1302wire ff_mb_rewrite_en_c6_scanout;
1303wire ff_mb_rewrite_en_c7_scanin;
1304wire ff_mb_rewrite_en_c7_scanout;
1305wire ff_mb_rewrite_en_c8_scanin;
1306wire ff_mb_rewrite_en_c8_scanout;
1307wire ff_mbdata_wr_en_c4_scanin;
1308wire ff_mbdata_wr_en_c4_scanout;
1309wire ff_mbdata_wr_en_c5_scanin;
1310wire ff_mbdata_wr_en_c5_scanout;
1311wire ff_mbdata_wr_en_c52_scanin;
1312wire ff_mbdata_wr_en_c52_scanout;
1313wire ff_mbdata_wr_en_c6_scanin;
1314wire ff_mbdata_wr_en_c6_scanout;
1315wire ff_mbdata_wr_en_c7_scanin;
1316wire ff_mbdata_wr_en_c7_scanout;
1317wire ff_mbdata_wr_en_c8_scanin;
1318wire ff_mbdata_wr_en_c8_scanout;
1319wire misbuf_mbdata_wr_en_c8_fnl;
1320wire ff_enc_tag_wr_wl_c3_scanin;
1321wire ff_enc_tag_wr_wl_c3_scanout;
1322wire ff_enc_data_wr_wl_c4_scanin;
1323wire ff_enc_data_wr_wl_c4_scanout;
1324wire ff_enc_data_wr_wl_c5_scanin;
1325wire ff_enc_data_wr_wl_c5_scanout;
1326wire ff_enc_data_wr_wl_c52_scanin;
1327wire ff_enc_data_wr_wl_c52_scanout;
1328wire ff_enc_data_wr_wl_c6_scanin;
1329wire ff_enc_data_wr_wl_c6_scanout;
1330wire ff_enc_data_wr_wl_c7_scanin;
1331wire ff_enc_data_wr_wl_c7_scanout;
1332wire ff_enc_data_wr_wl_c8_scanin;
1333wire ff_enc_data_wr_wl_c8_scanout;
1334wire ff_enc_data_wr_wl_c9_scanin;
1335wire ff_enc_data_wr_wl_c9_scanout;
1336wire ff_mbf_dep_c3_scanin;
1337wire ff_mbf_dep_c3_scanout;
1338wire misbuf_dep_inst_c3_tmp;
1339wire ff_dep_inst_c3_scanin;
1340wire ff_dep_inst_c3_scanout;
1341wire ff_tecc_c3_scanin;
1342wire ff_tecc_c3_scanout;
1343wire ff_set_dep_c2_ldifetch_miss_c2_scanin;
1344wire ff_set_dep_c2_ldifetch_miss_c2_scanout;
1345wire arb_decdp_cas2_inst_c3;
1346wire arb_decdp_swap_inst_c3;
1347wire ff_mbf_dep_c4_scanin;
1348wire ff_mbf_dep_c4_scanout;
1349wire ff_dep_bit_scanin;
1350wire ff_dep_bit_scanout;
1351wire ff_mbf_dep_c5_scanin;
1352wire ff_mbf_dep_c5_scanout;
1353wire ff_mbf_dep_c52_scanin;
1354wire ff_mbf_dep_c52_scanout;
1355wire ff_mbf_dep_c6_scanin;
1356wire ff_mbf_dep_c6_scanout;
1357wire ff_mbf_dep_c7_scanin;
1358wire ff_mbf_dep_c7_scanout;
1359wire ff_mbf_dep_c8_scanin;
1360wire ff_mbf_dep_c8_scanout;
1361wire ff_misbuf_mark_evict_tmp_c3_scanin;
1362wire ff_misbuf_mark_evict_tmp_c3_scanout;
1363wire ff_evict_vld_unqual_c3_scanin;
1364wire ff_evict_vld_unqual_c3_scanout;
1365wire ff_decdp_wr64_inst_c3_scanin;
1366wire ff_decdp_wr64_inst_c3_scanout;
1367wire ff_decdp_ld64_inst_c3_scanin;
1368wire ff_decdp_ld64_inst_c3_scanout;
1369wire ff_ld64_inst_c4_scanin;
1370wire ff_ld64_inst_c4_scanout;
1371wire ff_ld64_inst_c5_scanin;
1372wire ff_ld64_inst_c5_scanout;
1373wire ff_ld64_inst_c52_scanin;
1374wire ff_ld64_inst_c52_scanout;
1375wire ff_ld64_inst_c6_scanin;
1376wire ff_ld64_inst_c6_scanout;
1377wire ff_ld64_inst_c7_scanin;
1378wire ff_ld64_inst_c7_scanout;
1379wire arb_decdp_cas2_from_mb_c3;
1380wire ff_mcu_rdy_c4_scanin;
1381wire ff_mcu_rdy_c4_scanout;
1382wire ff_mcu_rdy_c5_scanin;
1383wire ff_mcu_rdy_c5_scanout;
1384wire ff_mcu_rdy_c52_scanin;
1385wire ff_mcu_rdy_c52_scanout;
1386wire ff_mcu_rdy_c6_scanin;
1387wire ff_mcu_rdy_c6_scanout;
1388wire ff_mcu_rdy_c7_scanin;
1389wire ff_mcu_rdy_c7_scanout;
1390wire ff_mcu_rdy_c8_scanin;
1391wire ff_mcu_rdy_c8_scanout;
1392wire ff_evict_par_err_c3_scanin;
1393wire ff_evict_par_err_c3_scanout;
1394wire evict_par_vuad_ce_err_c3;
1395wire ff_evict_par_err_c4_scanin;
1396wire ff_evict_par_err_c4_scanout;
1397wire ff_evict_par_err_c5_scanin;
1398wire ff_evict_par_err_c5_scanout;
1399wire ff_evict_par_err_c52_scanin;
1400wire ff_evict_par_err_c52_scanout;
1401wire ff_evict_par_err_c6_scanin;
1402wire ff_evict_par_err_c6_scanout;
1403wire ff_evict_par_err_c7_scanin;
1404wire ff_evict_par_err_c7_scanout;
1405wire misbuf_evict_nopfice_c7;
1406wire ff_misbuf_evict_c8_scanin;
1407wire ff_misbuf_evict_c8_scanout;
1408wire buffer_miss_vld_c4;
1409wire buffer_miss_vld_c5;
1410wire buffer_miss_vld_c52;
1411wire buffer_miss_vld_c6;
1412wire buffer_miss_vld_c7;
1413wire ff_buffer_miss_vld_c3_scanin;
1414wire ff_buffer_miss_vld_c3_scanout;
1415wire buffer_miss_vld_c8;
1416wire ff_rdma_reg_vld_c3_scanin;
1417wire ff_rdma_reg_vld_c3_scanout;
1418wire ff_rdma_comp_rdy_c4_scanin;
1419wire ff_rdma_comp_rdy_c4_scanout;
1420wire ff_rdma_comp_rdy_c5_scanin;
1421wire ff_rdma_comp_rdy_c5_scanout;
1422wire ff_rdma_comp_rdy_c52_scanin;
1423wire ff_rdma_comp_rdy_c52_scanout;
1424wire ff_rdma_comp_rdy_c6_scanin;
1425wire ff_rdma_comp_rdy_c6_scanout;
1426wire ff_rdma_comp_rdy_c7_scanin;
1427wire ff_rdma_comp_rdy_c7_scanout;
1428wire ff_rdma_comp_rdy_c8_scanin;
1429wire ff_rdma_comp_rdy_c8_scanout;
1430wire ff_misbuf_tecc_c4_scanin;
1431wire ff_misbuf_tecc_c4_scanout;
1432wire ff_misbuf_tecc_c5_scanin;
1433wire ff_misbuf_tecc_c5_scanout;
1434wire ff_misbuf_tecc_c52_scanin;
1435wire ff_misbuf_tecc_c52_scanout;
1436wire ff_misbuf_tecc_c6_scanin;
1437wire ff_misbuf_tecc_c6_scanout;
1438wire ff_misbuf_tecc_c7_scanin;
1439wire ff_misbuf_tecc_c7_scanout;
1440wire ff_misbuf_tecc_c8_scanin;
1441wire ff_misbuf_tecc_c8_scanout;
1442wire ff_mb_write_ptr_c3_scanin;
1443wire ff_mb_write_ptr_c3_scanout;
1444wire ff_mb_entry_c3_scanin;
1445wire ff_mb_entry_c3_scanout;
1446wire ff_mb_entry_c3_1_scanin;
1447wire ff_mb_entry_c3_1_scanout;
1448wire ff_valid_bit_scanin;
1449wire ff_valid_bit_scanout;
1450wire ff_rdma_bit_scanin;
1451wire ff_rdma_bit_scanout;
1452wire ff_bis_bit_scanin;
1453wire ff_bis_bit_scanout;
1454wire ff_arb_pf_ice_inst_c8_scanin;
1455wire ff_arb_pf_ice_inst_c8_scanout;
1456wire arb_pf_ice_inst_c8;
1457wire arb_vuad_ce_err_c3_tmp;
1458wire arb_vuad_ce_err_c4;
1459wire arb_vuad_ce_err_c5;
1460wire arb_vuad_ce_err_c52;
1461wire arb_vuad_ce_err_c6;
1462wire arb_vuad_ce_err_c7;
1463wire ff_arb_vuad_ce_err_slice_scanin;
1464wire ff_arb_vuad_ce_err_slice_scanout;
1465wire arb_vuad_ce_err_c8;
1466wire misbuf_hit_unqual_c3;
1467wire [31:0] reset_vuad_ce_replay;
1468wire tag_misbuf_ack_c3;
1469wire [31:0] vuad_ce_replay_in;
1470wire [31:0] vuad_ack_pending_in;
1471wire ff_vuad_ce_replay_scanin;
1472wire ff_vuad_ce_replay_scanout;
1473wire ff_mcu_ready_bit_scanin;
1474wire ff_mcu_ready_bit_scanout;
1475wire ff_young_bit_scanin;
1476wire ff_young_bit_scanout;
1477wire ff_next_link0_scanin;
1478wire ff_next_link0_scanout;
1479wire ff_next_link1_scanin;
1480wire ff_next_link1_scanout;
1481wire ff_next_link2_scanin;
1482wire ff_next_link2_scanout;
1483wire ff_next_link3_scanin;
1484wire ff_next_link3_scanout;
1485wire ff_next_link4_scanin;
1486wire ff_next_link4_scanout;
1487wire ff_next_link5_scanin;
1488wire ff_next_link5_scanout;
1489wire ff_next_link6_scanin;
1490wire ff_next_link6_scanout;
1491wire ff_next_link7_scanin;
1492wire ff_next_link7_scanout;
1493wire ff_next_link8_scanin;
1494wire ff_next_link8_scanout;
1495wire ff_next_link9_scanin;
1496wire ff_next_link9_scanout;
1497wire ff_next_link10_scanin;
1498wire ff_next_link10_scanout;
1499wire ff_next_link11_scanin;
1500wire ff_next_link11_scanout;
1501wire ff_next_link12_scanin;
1502wire ff_next_link12_scanout;
1503wire ff_next_link13_scanin;
1504wire ff_next_link13_scanout;
1505wire ff_next_link14_scanin;
1506wire ff_next_link14_scanout;
1507wire ff_next_link15_scanin;
1508wire ff_next_link15_scanout;
1509wire ff_next_link16_scanin;
1510wire ff_next_link16_scanout;
1511wire ff_next_link17_scanin;
1512wire ff_next_link17_scanout;
1513wire ff_next_link18_scanin;
1514wire ff_next_link18_scanout;
1515wire ff_next_link19_scanin;
1516wire ff_next_link19_scanout;
1517wire ff_next_link20_scanin;
1518wire ff_next_link20_scanout;
1519wire ff_next_link21_scanin;
1520wire ff_next_link21_scanout;
1521wire ff_next_link22_scanin;
1522wire ff_next_link22_scanout;
1523wire ff_next_link23_scanin;
1524wire ff_next_link23_scanout;
1525wire ff_next_link24_scanin;
1526wire ff_next_link24_scanout;
1527wire ff_next_link25_scanin;
1528wire ff_next_link25_scanout;
1529wire ff_next_link26_scanin;
1530wire ff_next_link26_scanout;
1531wire ff_next_link27_scanin;
1532wire ff_next_link27_scanout;
1533wire ff_next_link28_scanin;
1534wire ff_next_link28_scanout;
1535wire ff_next_link29_scanin;
1536wire ff_next_link29_scanout;
1537wire ff_next_link30_scanin;
1538wire ff_next_link30_scanout;
1539wire ff_next_link31_scanin;
1540wire ff_next_link31_scanout;
1541wire ff_inst_mb_c4_scanin;
1542wire ff_inst_mb_c4_scanout;
1543wire ff_inst_mb_c5_scanin;
1544wire ff_inst_mb_c5_scanout;
1545wire ff_inst_mb_c52_scanin;
1546wire ff_inst_mb_c52_scanout;
1547wire tag_inst_mb_c52;
1548wire ff_inst_mb_c6_scanin;
1549wire ff_inst_mb_c6_scanout;
1550wire ff_inst_mb_c7_scanin;
1551wire ff_inst_mb_c7_scanout;
1552wire ff_inst_mb_c8_scanin;
1553wire ff_inst_mb_c8_scanout;
1554wire ff_inst_mb_c9_scanin;
1555wire ff_inst_mb_c9_scanout;
1556wire ff_enc_data_wr_wl_c7_1_scanin;
1557wire ff_enc_data_wr_wl_c7_1_scanout;
1558wire set_arb_misbuf_cas1_hit_c8;
1559wire ff_cas1_hit_c9_scanin;
1560wire ff_cas1_hit_c9_scanout;
1561wire ff_uncorr_err_c9_scanin;
1562wire ff_uncorr_err_c9_scanout;
1563wire ff_notdata_err_c9_scanin;
1564wire ff_notdata_err_c9_scanout;
1565wire notdata_err_c9;
1566wire ff_corr_err_c9_scanin;
1567wire ff_corr_err_c9_scanout;
1568wire corr_err_c9;
1569wire ff_inst_bufidhi_c9_scanin;
1570wire ff_inst_bufidhi_c9_scanout;
1571wire arbdec_arbdp_inst_bufidhi_c9;
1572wire ff_ctrue_bit_scanin;
1573wire ff_ctrue_bit_scanout;
1574wire ff_mbf_insert_mbid_c4_scanin;
1575wire ff_mbf_insert_mbid_c4_scanout;
1576wire ff_mbf_insert_c4_scanin;
1577wire ff_mbf_insert_c4_scanout;
1578wire ff_misbuf_hit_c3_scanin;
1579wire ff_misbuf_hit_c3_scanout;
1580wire ff_misbuf_arb_hit_c3_scanin;
1581wire ff_misbuf_arb_hit_c3_scanout;
1582wire ff_misbuf_hit_c4_scanin;
1583wire ff_misbuf_hit_c4_scanout;
1584wire ff_misbuf_filbuf_next_vld_c4_scanin;
1585wire ff_misbuf_filbuf_next_vld_c4_scanout;
1586wire ff_mbf_delete_c4_scanin;
1587wire ff_mbf_delete_c4_scanout;
1588wire [4:0] nextlink_ida0123;
1589wire [4:0] nextlink_ida4567;
1590wire [4:0] nextlink_ida89ab;
1591wire [4:0] nextlink_idacdef;
1592wire ff_misbuf_filbuf_next_link_c4_scanin;
1593wire ff_misbuf_filbuf_next_link_c4_scanout;
1594wire ff_mb_data_vld_scanin;
1595wire ff_mb_data_vld_scanout;
1596wire misbuf_evict_qual_c7;
1597wire ff_gate_evict_set_staging_scanin;
1598wire ff_gate_evict_set_staging_scanout;
1599wire misbuf_evict_c8_pfice_qual;
1600wire [31:0] pfice_inst_rdy;
1601wire ff_mb_evict_ready_scanin;
1602wire ff_mb_evict_ready_scanout;
1603wire ff_mb_tecc_ready_scanin;
1604wire ff_mb_tecc_ready_scanout;
1605wire ff_ready_miss_r2_scanin;
1606wire ff_ready_miss_r2_scanout;
1607wire ff_fbf_enc_ld_mbid_r1_scanin;
1608wire ff_fbf_enc_ld_mbid_r1_scanout;
1609wire ff_fbf_st_or_dep_rdy_c5_scanin;
1610wire ff_fbf_st_or_dep_rdy_c5_scanout;
1611wire ff_fbf_enc_dep_mbid_c5_scanin;
1612wire ff_fbf_enc_dep_mbid_c5_scanout;
1613wire ff_decdp_cas1_inst_c2_scanin;
1614wire ff_decdp_cas1_inst_c2_scanout;
1615wire ff_l2_bypass_mode_on_d1_scanin;
1616wire ff_l2_bypass_mode_on_d1_scanout;
1617wire ff_filbuf_match_c3_scanin;
1618wire ff_filbuf_match_c3_scanout;
1619wire ff_filbuf_stinst_match_c3_scanin;
1620wire ff_filbuf_stinst_match_c3_scanout;
1621wire ff_misbuf_inval_inst_c3_scanin;
1622wire ff_misbuf_inval_inst_c3_scanout;
1623wire ff_mb_dep_rdy_en_c4_scanin;
1624wire ff_mb_dep_rdy_en_c4_scanout;
1625wire ff_wbb_dep_rdy_en_d1_scanin;
1626wire ff_wbb_dep_rdy_en_d1_scanout;
1627wire ff_dep_mbid_d1_scanin;
1628wire ff_dep_mbid_d1_scanout;
1629wire ff_rdmatb_dep_rdy_en_d1_scanin;
1630wire ff_rdmatb_dep_rdy_en_d1_scanout;
1631wire ff_dep_rdmat_mbid_d1_scanin;
1632wire ff_dep_rdmat_mbid_d1_scanout;
1633wire ff_set_mbid_vld_scanin;
1634wire ff_set_mbid_vld_scanout;
1635wire ff_mbid_vld_scanin;
1636wire ff_mbid_vld_scanout;
1637wire ff_mbid_scanin;
1638wire ff_mbid_scanout;
1639wire set_mbid_vld_pfice_prev;
1640wire ff_set_mbid_vld_pfice_prev_scanin;
1641wire ff_set_mbid_vld_pfice_prev_scanout;
1642wire set_mbid_vld_pfice;
1643wire ready_pf_ice_instr;
1644wire pf_ice_mbid_vld_in;
1645wire pf_ice_mbid_vld;
1646wire ff_pfice_mbid_vld_scanin;
1647wire ff_pfice_mbid_vld_scanout;
1648wire pf_ice_rdy_inst_en;
1649wire ff_pfice_mbid_scanin;
1650wire ff_pfice_mbid_scanout;
1651wire [4:0] pf_ice_csr_mbid;
1652wire ff_vuad_ce_err_ready_scanin;
1653wire ff_vuad_ce_err_ready_scanout;
1654wire nonmisbuf_inst_c8;
1655wire misbuf_inst_with_vuaderr_c8;
1656wire ff_mb_l2_ready_scanin;
1657wire ff_mb_l2_ready_scanout;
1658wire ff_l2_pick_d1_scanin;
1659wire ff_l2_pick_d1_scanout;
1660wire ff_l2_wait_scanin;
1661wire ff_l2_wait_scanout;
1662wire ff_read_reg_ctrue_in_scanin;
1663wire ff_read_reg_ctrue_in_scanout;
1664wire ff_mcu_l2t_rd_ack_d1_scanin;
1665wire ff_mcu_l2t_rd_ack_d1_scanout;
1666wire ff_misbuf_filbuf_mcu_pick_scanin;
1667wire ff_misbuf_filbuf_mcu_pick_scanout;
1668wire ff_mcu_pick_scanin;
1669wire ff_mcu_pick_scanout;
1670wire ff_mcu_pick_2_scanin;
1671wire ff_mcu_pick_2_scanout;
1672wire ff_mcu_pick_d1_scanin;
1673wire ff_mcu_pick_d1_scanout;
1674wire mcu_pick_d1;
1675wire ff_mcu_pick_d2_scanin;
1676wire ff_mcu_pick_d2_scanout;
1677wire mcu_pick_d2;
1678wire ff_dummy_req_d2_scanin;
1679wire ff_dummy_req_d2_scanout;
1680wire ff_mcu_ack_pend_state_scanin;
1681wire ff_mcu_ack_pend_state_scanout;
1682wire ff_evict_vld_c4_scanin;
1683wire ff_evict_vld_c4_scanout;
1684wire ff_way0_scanin;
1685wire ff_way0_scanout;
1686wire ff_way1_scanin;
1687wire ff_way1_scanout;
1688wire ff_way2_scanin;
1689wire ff_way2_scanout;
1690wire ff_way3_scanin;
1691wire ff_way3_scanout;
1692wire ff_way4_scanin;
1693wire ff_way4_scanout;
1694wire ff_way5_scanin;
1695wire ff_way5_scanout;
1696wire ff_way6_scanin;
1697wire ff_way6_scanout;
1698wire ff_way7_scanin;
1699wire ff_way7_scanout;
1700wire ff_way8_scanin;
1701wire ff_way8_scanout;
1702wire ff_way9_scanin;
1703wire ff_way9_scanout;
1704wire ff_way10_scanin;
1705wire ff_way10_scanout;
1706wire ff_way11_scanin;
1707wire ff_way11_scanout;
1708wire ff_way12_scanin;
1709wire ff_way12_scanout;
1710wire ff_way13_scanin;
1711wire ff_way13_scanout;
1712wire ff_way14_scanin;
1713wire ff_way14_scanout;
1714wire ff_way15_scanin;
1715wire ff_way15_scanout;
1716wire ff_way16_scanin;
1717wire ff_way16_scanout;
1718wire ff_way17_scanin;
1719wire ff_way17_scanout;
1720wire ff_way18_scanin;
1721wire ff_way18_scanout;
1722wire ff_way19_scanin;
1723wire ff_way19_scanout;
1724wire ff_way20_scanin;
1725wire ff_way20_scanout;
1726wire ff_way21_scanin;
1727wire ff_way21_scanout;
1728wire ff_way22_scanin;
1729wire ff_way22_scanout;
1730wire ff_way23_scanin;
1731wire ff_way23_scanout;
1732wire ff_way24_scanin;
1733wire ff_way24_scanout;
1734wire ff_way25_scanin;
1735wire ff_way25_scanout;
1736wire ff_way26_scanin;
1737wire ff_way26_scanout;
1738wire ff_way27_scanin;
1739wire ff_way27_scanout;
1740wire ff_way28_scanin;
1741wire ff_way28_scanout;
1742wire ff_way29_scanin;
1743wire ff_way29_scanout;
1744wire ff_way30_scanin;
1745wire ff_way30_scanout;
1746wire ff_way31_scanin;
1747wire ff_way31_scanout;
1748wire ff_arb_pf_ice_inst_c4_scanin;
1749wire ff_arb_pf_ice_inst_c4_scanout;
1750wire ff_mb_way_vld_scanin;
1751wire ff_mb_way_vld_scanout;
1752wire ff_fbid0_scanin;
1753wire ff_fbid0_scanout;
1754wire ff_fbid1_scanin;
1755wire ff_fbid1_scanout;
1756wire ff_fbid2_scanin;
1757wire ff_fbid2_scanout;
1758wire ff_fbid3_scanin;
1759wire ff_fbid3_scanout;
1760wire ff_fbid4_scanin;
1761wire ff_fbid4_scanout;
1762wire ff_fbid5_scanin;
1763wire ff_fbid5_scanout;
1764wire ff_fbid6_scanin;
1765wire ff_fbid6_scanout;
1766wire ff_fbid7_scanin;
1767wire ff_fbid7_scanout;
1768wire ff_fbid8_scanin;
1769wire ff_fbid8_scanout;
1770wire ff_fbid9_scanin;
1771wire ff_fbid9_scanout;
1772wire ff_fbid10_scanin;
1773wire ff_fbid10_scanout;
1774wire ff_fbid11_scanin;
1775wire ff_fbid11_scanout;
1776wire ff_fbid12_scanin;
1777wire ff_fbid12_scanout;
1778wire ff_fbid13_scanin;
1779wire ff_fbid13_scanout;
1780wire ff_fbid14_scanin;
1781wire ff_fbid14_scanout;
1782wire ff_fbid15_scanin;
1783wire ff_fbid15_scanout;
1784wire ff_fbid16_scanin;
1785wire ff_fbid16_scanout;
1786wire ff_fbid17_scanin;
1787wire ff_fbid17_scanout;
1788wire ff_fbid18_scanin;
1789wire ff_fbid18_scanout;
1790wire ff_fbid19_scanin;
1791wire ff_fbid19_scanout;
1792wire ff_fbid20_scanin;
1793wire ff_fbid20_scanout;
1794wire ff_fbid21_scanin;
1795wire ff_fbid21_scanout;
1796wire ff_fbid22_scanin;
1797wire ff_fbid22_scanout;
1798wire ff_fbid23_scanin;
1799wire ff_fbid23_scanout;
1800wire ff_fbid24_scanin;
1801wire ff_fbid24_scanout;
1802wire ff_fbid25_scanin;
1803wire ff_fbid25_scanout;
1804wire ff_fbid26_scanin;
1805wire ff_fbid26_scanout;
1806wire ff_fbid27_scanin;
1807wire ff_fbid27_scanout;
1808wire ff_fbid28_scanin;
1809wire ff_fbid28_scanout;
1810wire ff_fbid29_scanin;
1811wire ff_fbid29_scanout;
1812wire ff_fbid30_scanin;
1813wire ff_fbid30_scanout;
1814wire ff_fbid31_scanin;
1815wire ff_fbid31_scanout;
1816wire ff_mb_fbid_vld_scanin;
1817wire ff_mb_fbid_vld_scanout;
1818wire ff_misbuf_filbuf_way_fbid_vld_scanin;
1819wire ff_misbuf_filbuf_way_fbid_vld_scanout;
1820wire fbsel_23to20;
1821wire ff_fbsel_0to3_d1_scanin;
1822wire ff_fbsel_0to3_d1_scanout;
1823wire ff_fbsel_4to7_d1_scanin;
1824wire ff_fbsel_4to7_d1_scanout;
1825wire ff_fbsel_8tob_d1_scanin;
1826wire ff_fbsel_8tob_d1_scanout;
1827wire ff_fbsel_15to12_d1_scanin;
1828wire ff_fbsel_15to12_d1_scanout;
1829wire ff_fbsel_a_0to3_d1_scanin;
1830wire ff_fbsel_a_0to3_d1_scanout;
1831wire ff_fbsel_a_4to7_d1_scanin;
1832wire ff_fbsel_a_4to7_d1_scanout;
1833wire ff_fbsel_a_8tob_d1_scanin;
1834wire ff_fbsel_a_8tob_d1_scanout;
1835wire ff_fbsel_def_vld_d1_scanin;
1836wire ff_fbsel_def_vld_d1_scanout;
1837wire ff_misbuf_filbuf_way_0123_scanin;
1838wire ff_misbuf_filbuf_way_0123_scanout;
1839wire ff_misbuf_filbuf_way_4567_scanin;
1840wire ff_misbuf_filbuf_way_4567_scanout;
1841wire ff_misbuf_filbuf_way_89ab_scanin;
1842wire ff_misbuf_filbuf_way_89ab_scanout;
1843wire ff_misbuf_filbuf_way_cdef_scanin;
1844wire ff_misbuf_filbuf_way_cdef_scanout;
1845wire ff_misbuf_filbuf_way_a0123_scanin;
1846wire ff_misbuf_filbuf_way_a0123_scanout;
1847wire ff_misbuf_filbuf_way_a4567_scanin;
1848wire ff_misbuf_filbuf_way_a4567_scanout;
1849wire ff_misbuf_filbuf_way_a89ab_scanin;
1850wire ff_misbuf_filbuf_way_a89ab_scanout;
1851wire ff_misbuf_filbuf_way_acdef_scanin;
1852wire ff_misbuf_filbuf_way_acdef_scanout;
1853wire [3:0] misbuf_filbuf_a_way;
1854wire [3:0] misbuf_filbuf_b_way;
1855wire [2:0] fbida0123;
1856wire [2:0] fbida4567;
1857wire [2:0] fbida89ab;
1858wire [2:0] fbidacdef;
1859wire ff_misbuf_filbuf_fbid_0123_scanin;
1860wire ff_misbuf_filbuf_fbid_0123_scanout;
1861wire ff_misbuf_filbuf_fbid_4567_scanin;
1862wire ff_misbuf_filbuf_fbid_4567_scanout;
1863wire ff_misbuf_filbuf_fbid_89ab_scanin;
1864wire ff_misbuf_filbuf_fbid_89ab_scanout;
1865wire ff_misbuf_filbuf_fbid_cdef_scanin;
1866wire ff_misbuf_filbuf_fbid_cdef_scanout;
1867wire ff_misbuf_filbuf_fbid_a0123_scanin;
1868wire ff_misbuf_filbuf_fbid_a0123_scanout;
1869wire ff_misbuf_filbuf_fbid_a4567_scanin;
1870wire ff_misbuf_filbuf_fbid_a4567_scanout;
1871wire ff_misbuf_filbuf_fbid_a89ab_scanin;
1872wire ff_misbuf_filbuf_fbid_a89ab_scanout;
1873wire ff_misbuf_filbuf_fbid_acdef_scanin;
1874wire ff_misbuf_filbuf_fbid_acdef_scanout;
1875wire partial_st_wr8_inst_c2;
1876wire ff_wr8_piped_scanin;
1877wire ff_wr8_piped_scanout;
1878wire partial_st_wr8_inst_c3;
1879wire partial_st_wr8_inst_c4;
1880wire partial_st_wr8_inst_c5;
1881wire partial_st_wr8_inst_c52;
1882wire partial_st_wr8_inst_c6;
1883wire partial_st_wr8_inst_c7;
1884wire filbuf_misbuf_ue_offmode_c8;
1885wire filbuf_misbuf_ce_offmode_c8;
1886wire partial_st_wr8_inst_c8;
1887wire filbuf_misbuf_ue_offmode_c9;
1888wire filbuf_misbuf_ce_offmode_c9;
1889wire ff_mb_corr_err_scanin;
1890wire ff_mb_corr_err_scanout;
1891wire ff_mb_uncorr_err_scanin;
1892wire ff_mb_uncorr_err_scanout;
1893wire [31:0] mb_nderr_in;
1894wire [31:0] mb_nderr;
1895wire ff_mb_nderr_in_scanin;
1896wire ff_mb_nderr_in_scanout;
1897wire ff_misbuf_corr_err_c2_scanin;
1898wire ff_misbuf_corr_err_c2_scanout;
1899wire ff_misbuf_uncorr_err_c2_scanin;
1900wire ff_misbuf_uncorr_err_c2_scanout;
1901wire ff_misbuf_nderr_unqual_c2_scanin;
1902wire ff_misbuf_nderr_unqual_c2_scanout;
1903wire misbuf_nderr_unqual_c2;
1904wire ff_mb_l2_ready_qual_scanin;
1905wire ff_mb_l2_ready_qual_scanout;
1906wire ff_mcu_pick_1_scanin;
1907wire ff_mcu_pick_1_scanout;
1908wire ff_mcu_pick_2_l_scanin;
1909wire ff_mcu_pick_2_l_scanout;
1910wire ff_mcu_state_scanin;
1911wire ff_mcu_state_scanout;
1912wire ff_mcu_state_quad0_scanin;
1913wire ff_mcu_state_quad0_scanout;
1914wire ff_mcu_state_quad1_scanin;
1915wire ff_mcu_state_quad1_scanout;
1916wire ff_mcu_state_quad2_scanin;
1917wire ff_mcu_state_quad2_scanout;
1918wire ff_mcu_state_quad3_scanin;
1919wire ff_mcu_state_quad3_scanout;
1920wire ff_mcu_state_quad4_scanin;
1921wire ff_mcu_state_quad4_scanout;
1922wire ff_mcu_state_quad5_scanin;
1923wire ff_mcu_state_quad5_scanout;
1924wire ff_mcu_state_quad6_scanin;
1925wire ff_mcu_state_quad6_scanout;
1926wire ff_mcu_state_quad7_scanin;
1927wire ff_mcu_state_quad7_scanout;
1928wire ff_l2_state_scanin;
1929wire ff_l2_state_scanout;
1930wire ff_l2_state_quad0_scanin;
1931wire ff_l2_state_quad0_scanout;
1932wire ff_l2_state_quad1_scanin;
1933wire ff_l2_state_quad1_scanout;
1934wire ff_l2_state_quad2_scanin;
1935wire ff_l2_state_quad2_scanout;
1936wire ff_l2_state_quad3_scanin;
1937wire ff_l2_state_quad3_scanout;
1938wire sel_l2_lshift_quad4;
1939wire sel_l2_same_quad4;
1940wire ff_l2_state_quad4_scanin;
1941wire ff_l2_state_quad4_scanout;
1942wire sel_l2_lshift_quad5;
1943wire sel_l2_same_quad5;
1944wire ff_l2_state_quad5_scanin;
1945wire ff_l2_state_quad5_scanout;
1946wire sel_l2_lshift_quad6;
1947wire sel_l2_same_quad6;
1948wire ff_l2_state_quad6_scanin;
1949wire ff_l2_state_quad6_scanout;
1950wire sel_l2_lshift_quad7;
1951wire sel_l2_same_quad7;
1952wire ff_l2_state_quad7_scanin;
1953wire ff_l2_state_quad7_scanout;
1954wire [3:0] pick_state_quad4;
1955wire [3:0] pick_state_quad5;
1956wire [3:0] pick_state_quad6;
1957wire [3:0] pick_state_quad7;
1958wire pick_s4;
1959wire pick_s5;
1960wire pick_s6;
1961wire pick_s7;
1962wire pick_s0_quad4;
1963wire pick_s1_quad4;
1964wire pick_s2_quad4;
1965wire pick_s3_quad4;
1966wire pick_s0_quad5;
1967wire pick_s1_quad5;
1968wire pick_s2_quad5;
1969wire pick_s3_quad5;
1970wire pick_s0_quad6;
1971wire pick_s1_quad6;
1972wire pick_s2_quad6;
1973wire pick_s3_quad6;
1974wire pick_s0_quad7;
1975wire pick_s1_quad7;
1976wire pick_s2_quad7;
1977wire pick_s3_quad7;
1978wire ff_picker_out_d1_scanin;
1979wire ff_picker_out_d1_scanout;
1980wire ff_picker_out_d2_scanin;
1981wire ff_picker_out_d2_scanout;
1982
1983
1984 input tcu_pce_ov;
1985 input tcu_aclk;
1986 input tcu_bclk;
1987 input tcu_scan_en;
1988
1989// from tag
1990input tag_miss_unqual_c2; // Miss not qualified with inst vld or misbuf_hit_c2
1991input tag_store_inst_c3; //BS and SR 11/07/03, store pipelining support
1992input tag_hit_unqual_c2;
1993input tag_hit_c3 ; // from tag.
1994input [3:0] tag_lru_way_c4; // encoded way from tag.
1995
1996input tag_rdma_vld_px0_p; // used in misbuf for l2 pick logic.
1997input tag_misbuf_rdma_reg_vld_c2; // used by misbuf to insert instructions.
1998input tag_hit_not_comp_c3; // indicates that hit completion was gated off
1999input tag_alt_tag_miss_unqual_c3; // indicates a tag mismatch unqualled.
2000input tag_misbuf_int_ack_c3; // initiates a ack condition true in c3
2001
2002
2003// from arb
2004input arb_pf_ice_inst_c2; // BS 06/24/04 : Prefetch ICE in c2 stage
2005input arbdec_pf_ice_inst_c1;
2006input arb_inst_vld_c2; // valid instruction in C2
2007input arb_pf_ice_inst_c7; // BS 06/24/04 : Prefetch ICE in c7 stage
2008input arb_decdp_ld_inst_c2; // BS and SR 11/07/03, store pipelining support
2009input arb_decdp_imiss_inst_c2; // BS and SR 11/07/03, store pipelining support
2010input arb_decdp_swap_inst_c2; // BS and SR 11/07/03, store pipelining support
2011input arb_arbdp_pst_with_ctrue_c2 ; // from arbdec.
2012input arb_arbdp_misbuf_pst_no_ctrue_c2 ; // from arbdec. includes LDSTUB/SWAPs pin on TOP
2013input arb_decdp_cas2_inst_c2; // from arbdec.
2014input arbdec_arbdp_inst_mb_c2;
2015input arb_decdp_pst_inst_c2;
2016input arb_decdp_cas1_inst_c2;
2017input [4:0] arbdec_arbdp_inst_mb_entry_c1; // BS & SR 11/04/03, MB grows to 32
2018input arb_arbdp_tecc_inst_mb_c8; // indicates a tecc instruction from mbf
2019
2020input arbdec_arbdp_rdma_inst_c1; // POST_3.0 pin replaces arbdec_arbdp_rdma_inst_c2
2021input arb_decdp_ld64_inst_c2; // this signal indicates an rdma rd.
2022input arb_decdp_wr64_inst_c2;
2023input arb_decdp_bis_inst_c3; // NEW_PIN from arbdec. indicating a Block INIT store.
2024input arbdec_arbdp_inst_bufidhi_c8; // NEW_PIN from arbdec
2025input arb_decdp_wr8_inst_c2;
2026
2027// from arb
2028input arb_csr_st_c2;
2029input arb_evict_vld_c2 ; // from arb.
2030input arb_misbuf_inst_vld_c2;
2031input arb_pst_ctrue_en_c8; // from arb. PST ctrue only.
2032input arb_misbuf_hit_off_c1; // frm arb used to turn off hits.
2033input arb_evict_tecc_vld_c2; // POST_2.0 pin.
2034input arbdec_arbdp_inst_dep_c2 ; // POST_2.0 pin.
2035
2036input arb_vuad_ce_err_c2; // vuad ecc change
2037input usaloc_ua_ce_c2; // used alloc CE
2038input vlddir_vd_ce_c2; // valid dirty CE
2039
2040output misbuf_vuad_ce_err_c6; // vuad ecc change
2041output misbuf_vuad_ce_instr_c2; // vuad ecc change
2042output misbuf_vuad_ce_instr_ack_c2; // vuad ecc change
2043
2044input arb_decdp_cas2_from_mb_c2;
2045
2046// input arb_addr_c1eqc2_c1 ; // from arb ( 32b address compare ) OLD_PIN
2047// input arb_addr_c1eqc3_c1 ; // from arb ( 32b address compare ) OLD_PIN
2048
2049input arbadr_arbdp_addr_c1c2comp_c1; // NEW_PIN
2050input arbadr_arbdp_addr_c1c3comp_c1; // NEW_PIN
2051input arbadr_idx_c1c2comp_c1; // NEW_PIN
2052input arbadr_idx_c1c3comp_c1; // NEW_PIN
2053
2054input arb_misbuf_cas1_hit_c8;// CAS1 hit.
2055input arb_misbuf_ctrue_c9 ; // compare result for CAS1
2056input arb_misbuf_mbsel_c1;
2057
2058// from mbtag
2059input [31:0] mb_cam_match ; // from mbtag. BS & SR 11/04/03, MB grows to 32
2060input [31:0] mb_cam_match_idx ; // NEW_PIN replacing mb_cam_match14 BS & SR 11/04/03, MB grows to 32
2061
2062// from decc
2063input deccck_uncorr_err_c8 ; // UE ecc result for CAS1
2064//input deccck_corr_err_c8; // CE ecc result on CAS1
2065input deccck_notdata_err_c8; // Notdata on CAS1
2066input deccck_spcd_corr_err_c8;
2067input deccck_spcfb_corr_err_c8 ;
2068
2069// from filbuf.
2070input filbuf_misbuf_match_c2 ; // from filbuf.
2071input filbuf_misbuf_stinst_match_c2 ; // NEW_PIN
2072input filbuf_misbuf_entry_avail; // from filbuf.
2073input filbuf_fbf_ready_miss_r1; // miss ready
2074input [4:0] filbuf_fbf_enc_ld_mbid_r1 ; // miss entry BS & SR 11/04/03, MB grows to 32
2075input filbuf_fbf_st_or_dep_rdy_c4;// st or dep rdy enable
2076input [4:0] filbuf_fbf_enc_dep_mbid_c4; // st or dep entry mbid BS & SR 11/04/03, MB grows to 32
2077input filbuf_fb_count_eq_0; // from filbuf.
2078input [2:0] filbuf_misbuf_fbid_d2 ; // inserting fbid
2079input filbuf_misbuf_nofill_d2;// for no fills.
2080input filbuf_misbuf_ue_offmode_c7;
2081input filbuf_misbuf_ce_offmode_c7;
2082
2083
2084// wbuf
2085input wbuf_hit_unqual_c2 ; // from wbuf.
2086input wbuf_misbuf_dep_rdy_en ; // rdy wbb dependents
2087input [4:0] wbuf_misbuf_dep_mbid; // wbb dependent mbid. BS & SR 11/04/03, MB grows to 32
2088
2089// rdmat.
2090input rdmat_hit_unqual_c2; // from rdmat
2091input [4:0] rdmat_misbuf_dep_mbid; // from rdmat BS & SR 11/04/03, MB grows to 32
2092input rdmat_misbuf_dep_rdy_en;
2093
2094
2095input tag_misbuf_par_err_c3 ; // parity err from tagd.
2096
2097// mcu interface
2098input mcu_l2t_rd_ack;
2099
2100// from csr
2101input csr_l2_bypass_mode_on;
2102input csr_l2_dir_map_on; // NEW_PIN
2103
2104
2105
2106
2107input l2clk;
2108input wmr_l;
2109input scan_in;
2110
2111input arb_tecc_c2; // POST_3.0 PIN
2112
2113output scan_out;
2114
2115
2116// to arb
2117output misbuf_hit_st_dep_zero; // BS and SR 11/07/03, store pipelining support
2118output misbuf_arb_cnt28_px2_prev ;
2119output misbuf_arb_snp_cnt8_px1;
2120output misbuf_arb_vld_px1 ;
2121output misbuf_nondep_fbhit_c3; // to arb for dir CAM input generation.
2122
2123// to iqu
2124//output mb_valid_stall_pfice_c3;
2125
2126// to tagd
2127output misbuf_hit_c3; // POST_2.0 pin
2128
2129output misbuf_arb_hit_c3; // int 5.0 changes
2130input arb_misbuf_inval_inst_c2; // int 5.0 changes
2131
2132output filbuf_match_c3; // bg fix 84674
2133
2134// to arbaddr and arbdec.
2135output misbuf_arbdp_ctrue_px2; // instruction CTRUE bit.
2136output misbuf_arb_l2rd_en; // rd flop en to arbaddr and arbdec.
2137output misbuf_arb_mcurd_en; // rd flop en to arbaddr and arbdec
2138
2139// to tag.
2140output misbuf_tag_hit_unqual_c2;
2141output misbuf_corr_err_c2;
2142output misbuf_uncorr_err_c2;
2143output misbuf_notdata_err_c2;
2144output misbuf_wr64_miss_comp_c3; // to tag for setting rdma reg vld.
2145
2146// to wbuf.
2147output [4:0] misbuf_wbuf_mbid_c4; // write mbid to RDY in WBB after write to DRAM.
2148 // BS & SR 11/04/03, MB grows to 32
2149
2150// to filbuf.
2151output [4:0] misbuf_mbf_insert_mbid_c4; // BS & SR 11/04/03, MB grows to 32
2152output misbuf_mbf_insert_c4;
2153output misbuf_hit_c4;
2154output misbuf_mbf_delete_c4;
2155output misbuf_filbuf_next_vld_c4;
2156output [4:0] misbuf_filbuf_next_link_c4; // BS & SR 11/04/03, MB grows to 32
2157output misbuf_filbuf_mcu_pick ;
2158
2159output [2:0] misbuf_filbuf_fbid;
2160output [3:0] misbuf_filbuf_way ;
2161output misbuf_filbuf_way_fbid_vld ;
2162
2163
2164input filbuf_tag_hit_frm_mb_c2;
2165
2166// to mbtag
2167output misbuf_mbtag_wr_en_c2 ;// output to mbtag only
2168output [31:0] misbuf_mb_write_wl ; // output to mbtag , BS & SR 11/04/03,MB grows to 32
2169output misbuf_buf_rd_en; // output to mbtag and mbdata
2170output [31:0] misbuf_mb_read_wl ; // output to mbtag and mbdata. , MB grows to 32
2171
2172// to mbdata.
2173output misbuf_dep_c8; // to mbdata.
2174output [31:0] misbuf_mb_data_write_wl; // to mbdata , BS & SR 11/04/03, MB grows to 32
2175output misbuf_evict_c8; // to mbdata
2176output misbuf_tecc_c8 ; // to mbdata
2177output [4:0] misbuf_mbentry_c8 ; // to mbdata , BS & SR 11/04/03, MB grows to 32
2178output misbuf_mbdata_wr_en_c8 ;
2179
2180output misbuf_notdata_err_c1;
2181output misbuf_uncorr_err_c1;
2182// to BTU
2183output l2t_mcu_rd_req ;
2184output l2t_mcu_rd_dummy_req;
2185
2186// to l2t_csreg_ctl, l2t_filbuf_ctl
2187
2188input l2t_mb2_mbdata_wr_en;
2189input l2t_mb2_run;
2190input l2t_mb2_mbdata_rd_en;
2191input l2t_mb2_mbtag_rd_en;
2192input l2t_mb2_mbtag_wr_en;
2193input [4:0] l2t_mb2_addr;
2194output mb_mbist_cam_hit;
2195input mbtag_mbist_cam_sel;
2196
2197output misbuf_vuad_ce_err_c8;
2198
2199assign pce_ov = tcu_pce_ov;
2200assign siclk = tcu_aclk;
2201assign soclk = tcu_bclk;
2202assign stop = 1'b0;
2203assign se = tcu_scan_en;
2204
2205l2t_misbuf_ctl_l1clkhdr_ctl_macro clkgen (
2206 .l2clk(l2clk),
2207 .l1en(1'b1 ),
2208 .l1clk(l1clk),
2209 .pce_ov(pce_ov),
2210 .stop(stop),
2211 .se(se));
2212
2213//////////////////////////////////////////
2214// Spare gate insertion
2215//////////////////////////////////////////
2216//spare_ctl_macro spares (num=15) (
2217// .scan_in(spares_scanin),
2218// .scan_out(spares_scanout),
2219// .l1clk (l1clk)
2220//);
2221
2222wire si_0;
2223wire so_0;
2224wire spare0_flop_unused;
2225wire spare0_buf_32x_unused;
2226wire spare0_nand3_8x_unused;
2227wire spare0_inv_8x_unused;
2228wire spare0_aoi22_4x_unused;
2229wire spare0_buf_8x_unused;
2230wire spare0_oai22_4x_unused;
2231wire spare0_inv_16x_unused;
2232wire spare0_nand2_16x_unused;
2233wire spare0_nor3_4x_unused;
2234wire spare0_nand2_8x_unused;
2235wire spare0_buf_16x_unused;
2236wire spare0_nor2_16x_unused;
2237wire spare0_inv_32x_unused;
2238wire si_1;
2239wire so_1;
2240wire spare1_flop_unused;
2241wire spare1_buf_32x_unused;
2242wire spare1_nand3_8x_unused;
2243wire spare1_inv_8x_unused;
2244wire spare1_aoi22_4x_unused;
2245wire spare1_buf_8x_unused;
2246wire spare1_oai22_4x_unused;
2247wire spare1_inv_16x_unused;
2248wire spare1_nand2_16x_unused;
2249wire spare1_nor3_4x_unused;
2250wire spare1_nand2_8x_unused;
2251wire spare1_buf_16x_unused;
2252wire spare1_nor2_16x_unused;
2253wire spare1_inv_32x_unused;
2254wire si_2;
2255wire so_2;
2256wire spare2_flop_unused;
2257wire spare2_buf_32x_unused;
2258wire spare2_nand3_8x_unused;
2259wire spare2_inv_8x_unused;
2260wire spare2_aoi22_4x_unused;
2261wire spare2_buf_8x_unused;
2262wire spare2_oai22_4x_unused;
2263wire spare2_inv_16x_unused;
2264wire spare2_nand2_16x_unused;
2265wire spare2_nor3_4x_unused;
2266wire spare2_nand2_8x_unused;
2267wire spare2_buf_16x_unused;
2268wire spare2_nor2_16x_unused;
2269wire spare2_inv_32x_unused;
2270wire si_3;
2271wire so_3;
2272wire spare3_flop_unused;
2273wire spare3_buf_32x_unused;
2274wire spare3_nand3_8x_unused;
2275wire spare3_inv_8x_unused;
2276wire spare3_aoi22_4x_unused;
2277wire spare3_buf_8x_unused;
2278wire spare3_oai22_4x_unused;
2279wire spare3_inv_16x_unused;
2280wire spare3_nand2_16x_unused;
2281wire spare3_nor3_4x_unused;
2282wire spare3_nand2_8x_unused;
2283wire spare3_buf_16x_unused;
2284wire spare3_nor2_16x_unused;
2285wire spare3_inv_32x_unused;
2286wire si_4;
2287wire so_4;
2288wire spare4_flop_unused;
2289wire spare4_buf_32x_unused;
2290wire spare4_nand3_8x_unused;
2291wire spare4_inv_8x_unused;
2292wire spare4_aoi22_4x_unused;
2293wire spare4_buf_8x_unused;
2294wire spare4_oai22_4x_unused;
2295wire spare4_inv_16x_unused;
2296wire spare4_nand2_16x_unused;
2297wire spare4_nor3_4x_unused;
2298wire spare4_nand2_8x_unused;
2299wire spare4_buf_16x_unused;
2300wire spare4_nor2_16x_unused;
2301wire spare4_inv_32x_unused;
2302wire si_5;
2303wire so_5;
2304wire spare5_flop_unused;
2305wire spare5_buf_32x_unused;
2306wire spare5_nand3_8x_unused;
2307wire spare5_inv_8x_unused;
2308wire spare5_aoi22_4x_unused;
2309wire spare5_buf_8x_unused;
2310wire spare5_oai22_4x_unused;
2311wire spare5_inv_16x_unused;
2312wire spare5_nand2_16x_unused;
2313wire spare5_nor3_4x_unused;
2314wire spare5_nand2_8x_unused;
2315wire spare5_buf_16x_unused;
2316wire spare5_nor2_16x_unused;
2317wire spare5_inv_32x_unused;
2318wire si_6;
2319wire so_6;
2320wire spare6_flop_unused;
2321wire spare6_buf_32x_unused;
2322wire spare6_nand3_8x_unused;
2323wire spare6_inv_8x_unused;
2324wire spare6_aoi22_4x_unused;
2325wire spare6_buf_8x_unused;
2326wire spare6_oai22_4x_unused;
2327wire spare6_inv_16x_unused;
2328wire spare6_nand2_16x_unused;
2329wire spare6_nor3_4x_unused;
2330wire spare6_nand2_8x_unused;
2331wire spare6_buf_16x_unused;
2332wire spare6_nor2_16x_unused;
2333wire spare6_inv_32x_unused;
2334wire si_7;
2335wire so_7;
2336wire spare7_buf_32x_unused;
2337wire spare7_nand3_8x_unused;
2338wire spare7_inv_8x_unused;
2339wire spare7_aoi22_4x_unused;
2340wire spare7_buf_8x_unused;
2341wire spare7_oai22_4x_unused;
2342wire spare7_inv_16x_unused;
2343wire spare7_nand2_16x_unused;
2344wire spare7_nor3_4x_unused;
2345wire spare7_nand2_8x_unused;
2346wire spare7_buf_16x_unused;
2347wire spare7_nor2_16x_unused;
2348wire spare7_inv_32x_unused;
2349wire si_8;
2350wire so_8;
2351wire spare8_flop_unused;
2352wire spare8_buf_32x_unused;
2353wire spare8_nand3_8x_unused;
2354wire spare8_inv_8x_unused;
2355wire spare8_aoi22_4x_unused;
2356wire spare8_buf_8x_unused;
2357wire spare8_oai22_4x_unused;
2358wire spare8_inv_16x_unused;
2359wire spare8_nand2_16x_unused;
2360wire spare8_nor3_4x_unused;
2361wire spare8_nand2_8x_unused;
2362wire spare8_buf_16x_unused;
2363wire spare8_nor2_16x_unused;
2364wire spare8_inv_32x_unused;
2365wire si_9;
2366wire so_9;
2367wire spare9_flop_unused;
2368wire spare9_buf_32x_unused;
2369wire spare9_nand3_8x_unused;
2370wire spare9_inv_8x_unused;
2371wire spare9_aoi22_4x_unused;
2372wire spare9_buf_8x_unused;
2373wire spare9_oai22_4x_unused;
2374wire spare9_inv_16x_unused;
2375wire spare9_nand2_16x_unused;
2376wire spare9_nor3_4x_unused;
2377wire spare9_nand2_8x_unused;
2378wire spare9_buf_16x_unused;
2379wire spare9_nor2_16x_unused;
2380wire spare9_inv_32x_unused;
2381wire si_10;
2382wire so_10;
2383wire spare10_flop_unused;
2384wire spare10_buf_32x_unused;
2385wire spare10_nand3_8x_unused;
2386wire spare10_inv_8x_unused;
2387wire spare10_aoi22_4x_unused;
2388wire spare10_buf_8x_unused;
2389wire spare10_oai22_4x_unused;
2390wire spare10_inv_16x_unused;
2391wire spare10_nand2_16x_unused;
2392wire spare10_nor3_4x_unused;
2393wire spare10_nand2_8x_unused;
2394wire spare10_buf_16x_unused;
2395wire spare10_nor2_16x_unused;
2396wire spare10_inv_32x_unused;
2397wire si_11;
2398wire so_11;
2399wire spare11_flop_unused;
2400wire spare11_buf_32x_unused;
2401wire spare11_nand3_8x_unused;
2402wire spare11_inv_8x_unused;
2403wire spare11_aoi22_4x_unused;
2404wire spare11_buf_8x_unused;
2405wire spare11_oai22_4x_unused;
2406wire spare11_inv_16x_unused;
2407wire spare11_nand2_16x_unused;
2408wire spare11_nor3_4x_unused;
2409wire spare11_nand2_8x_unused;
2410wire spare11_buf_16x_unused;
2411wire spare11_nor2_16x_unused;
2412wire spare11_inv_32x_unused;
2413wire si_12;
2414wire so_12;
2415wire spare12_flop_unused;
2416wire spare12_buf_32x_unused;
2417wire spare12_nand3_8x_unused;
2418wire spare12_inv_8x_unused;
2419wire spare12_aoi22_4x_unused;
2420wire spare12_buf_8x_unused;
2421wire spare12_oai22_4x_unused;
2422wire spare12_inv_16x_unused;
2423wire spare12_nand2_16x_unused;
2424wire spare12_nor3_4x_unused;
2425wire spare12_nand2_8x_unused;
2426wire spare12_buf_16x_unused;
2427wire spare12_nor2_16x_unused;
2428wire spare12_inv_32x_unused;
2429wire si_13;
2430wire so_13;
2431wire spare13_flop_unused;
2432wire spare13_buf_32x_unused;
2433wire spare13_nand3_8x_unused;
2434wire spare13_inv_8x_unused;
2435wire spare13_aoi22_4x_unused;
2436wire spare13_buf_8x_unused;
2437wire spare13_oai22_4x_unused;
2438wire spare13_inv_16x_unused;
2439wire spare13_nand2_16x_unused;
2440wire spare13_nor3_4x_unused;
2441wire spare13_nand2_8x_unused;
2442wire spare13_buf_16x_unused;
2443wire spare13_nor2_16x_unused;
2444wire spare13_inv_32x_unused;
2445wire si_14;
2446wire so_14;
2447wire spare14_flop_unused;
2448wire spare14_buf_32x_unused;
2449wire spare14_nand3_8x_unused;
2450wire spare14_inv_8x_unused;
2451wire spare14_aoi22_4x_unused;
2452wire spare14_buf_8x_unused;
2453wire spare14_oai22_4x_unused;
2454wire spare14_inv_16x_unused;
2455wire spare14_nand2_16x_unused;
2456wire spare14_nor3_4x_unused;
2457wire spare14_nand2_8x_unused;
2458wire spare14_buf_16x_unused;
2459wire spare14_nor2_16x_unused;
2460wire spare14_inv_32x_unused;
2461
2462cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
2463 .siclk(siclk),
2464 .soclk(soclk),
2465 .si(si_0),
2466 .so(so_0),
2467 .d(1'b0),
2468 .q(spare0_flop_unused));
2469assign si_0 = scan_in;
2470
2471cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
2472 .out(spare0_buf_32x_unused));
2473cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
2474 .in1(1'b1),
2475 .in2(1'b1),
2476 .out(spare0_nand3_8x_unused));
2477cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
2478 .out(spare0_inv_8x_unused));
2479cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
2480 .in01(1'b1),
2481 .in10(1'b1),
2482 .in11(1'b1),
2483 .out(spare0_aoi22_4x_unused));
2484cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
2485 .out(spare0_buf_8x_unused));
2486cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
2487 .in01(1'b1),
2488 .in10(1'b1),
2489 .in11(1'b1),
2490 .out(spare0_oai22_4x_unused));
2491cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
2492 .out(spare0_inv_16x_unused));
2493cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
2494 .in1(1'b1),
2495 .out(spare0_nand2_16x_unused));
2496cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
2497 .in1(1'b0),
2498 .in2(1'b0),
2499 .out(spare0_nor3_4x_unused));
2500cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
2501 .in1(1'b1),
2502 .out(spare0_nand2_8x_unused));
2503cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
2504 .out(spare0_buf_16x_unused));
2505cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
2506 .in1(1'b0),
2507 .out(spare0_nor2_16x_unused));
2508cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
2509 .out(spare0_inv_32x_unused));
2510
2511cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
2512 .siclk(siclk),
2513 .soclk(soclk),
2514 .si(si_1),
2515 .so(so_1),
2516 .d(1'b0),
2517 .q(spare1_flop_unused));
2518assign si_1 = so_0;
2519
2520cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
2521 .out(spare1_buf_32x_unused));
2522cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
2523 .in1(1'b1),
2524 .in2(1'b1),
2525 .out(spare1_nand3_8x_unused));
2526cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
2527 .out(spare1_inv_8x_unused));
2528cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
2529 .in01(1'b1),
2530 .in10(1'b1),
2531 .in11(1'b1),
2532 .out(spare1_aoi22_4x_unused));
2533cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
2534 .out(spare1_buf_8x_unused));
2535cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
2536 .in01(1'b1),
2537 .in10(1'b1),
2538 .in11(1'b1),
2539 .out(spare1_oai22_4x_unused));
2540cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
2541 .out(spare1_inv_16x_unused));
2542cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
2543 .in1(1'b1),
2544 .out(spare1_nand2_16x_unused));
2545cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
2546 .in1(1'b0),
2547 .in2(1'b0),
2548 .out(spare1_nor3_4x_unused));
2549cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
2550 .in1(1'b1),
2551 .out(spare1_nand2_8x_unused));
2552cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
2553 .out(spare1_buf_16x_unused));
2554cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
2555 .in1(1'b0),
2556 .out(spare1_nor2_16x_unused));
2557cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
2558 .out(spare1_inv_32x_unused));
2559
2560cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
2561 .siclk(siclk),
2562 .soclk(soclk),
2563 .si(si_2),
2564 .so(so_2),
2565 .d(1'b0),
2566 .q(spare2_flop_unused));
2567assign si_2 = so_1;
2568
2569cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
2570 .out(spare2_buf_32x_unused));
2571cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
2572 .in1(1'b1),
2573 .in2(1'b1),
2574 .out(spare2_nand3_8x_unused));
2575cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
2576 .out(spare2_inv_8x_unused));
2577cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
2578 .in01(1'b1),
2579 .in10(1'b1),
2580 .in11(1'b1),
2581 .out(spare2_aoi22_4x_unused));
2582cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
2583 .out(spare2_buf_8x_unused));
2584cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
2585 .in01(1'b1),
2586 .in10(1'b1),
2587 .in11(1'b1),
2588 .out(spare2_oai22_4x_unused));
2589cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
2590 .out(spare2_inv_16x_unused));
2591cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
2592 .in1(1'b1),
2593 .out(spare2_nand2_16x_unused));
2594cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
2595 .in1(1'b0),
2596 .in2(1'b0),
2597 .out(spare2_nor3_4x_unused));
2598cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
2599 .in1(1'b1),
2600 .out(spare2_nand2_8x_unused));
2601cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
2602 .out(spare2_buf_16x_unused));
2603cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
2604 .in1(1'b0),
2605 .out(spare2_nor2_16x_unused));
2606cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
2607 .out(spare2_inv_32x_unused));
2608
2609cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
2610 .siclk(siclk),
2611 .soclk(soclk),
2612 .si(si_3),
2613 .so(so_3),
2614 .d(1'b0),
2615 .q(spare3_flop_unused));
2616assign si_3 = so_2;
2617
2618cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
2619 .out(spare3_buf_32x_unused));
2620cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
2621 .in1(1'b1),
2622 .in2(1'b1),
2623 .out(spare3_nand3_8x_unused));
2624cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
2625 .out(spare3_inv_8x_unused));
2626cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
2627 .in01(1'b1),
2628 .in10(1'b1),
2629 .in11(1'b1),
2630 .out(spare3_aoi22_4x_unused));
2631cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
2632 .out(spare3_buf_8x_unused));
2633cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
2634 .in01(1'b1),
2635 .in10(1'b1),
2636 .in11(1'b1),
2637 .out(spare3_oai22_4x_unused));
2638cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
2639 .out(spare3_inv_16x_unused));
2640cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
2641 .in1(1'b1),
2642 .out(spare3_nand2_16x_unused));
2643cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
2644 .in1(1'b0),
2645 .in2(1'b0),
2646 .out(spare3_nor3_4x_unused));
2647cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
2648 .in1(1'b1),
2649 .out(spare3_nand2_8x_unused));
2650cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
2651 .out(spare3_buf_16x_unused));
2652cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
2653 .in1(1'b0),
2654 .out(spare3_nor2_16x_unused));
2655cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
2656 .out(spare3_inv_32x_unused));
2657
2658cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
2659 .siclk(siclk),
2660 .soclk(soclk),
2661 .si(si_4),
2662 .so(so_4),
2663 .d(1'b0),
2664 .q(spare4_flop_unused));
2665assign si_4 = so_3;
2666
2667cl_u1_buf_32x spare4_buf_32x (.in(1'b1),
2668 .out(spare4_buf_32x_unused));
2669cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
2670 .in1(1'b1),
2671 .in2(1'b1),
2672 .out(spare4_nand3_8x_unused));
2673cl_u1_inv_8x spare4_inv_8x (.in(1'b1),
2674 .out(spare4_inv_8x_unused));
2675cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
2676 .in01(1'b1),
2677 .in10(1'b1),
2678 .in11(1'b1),
2679 .out(spare4_aoi22_4x_unused));
2680cl_u1_buf_8x spare4_buf_8x (.in(1'b1),
2681 .out(spare4_buf_8x_unused));
2682cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
2683 .in01(1'b1),
2684 .in10(1'b1),
2685 .in11(1'b1),
2686 .out(spare4_oai22_4x_unused));
2687cl_u1_inv_16x spare4_inv_16x (.in(1'b1),
2688 .out(spare4_inv_16x_unused));
2689cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
2690 .in1(1'b1),
2691 .out(spare4_nand2_16x_unused));
2692cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
2693 .in1(1'b0),
2694 .in2(1'b0),
2695 .out(spare4_nor3_4x_unused));
2696cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
2697 .in1(1'b1),
2698 .out(spare4_nand2_8x_unused));
2699cl_u1_buf_16x spare4_buf_16x (.in(1'b1),
2700 .out(spare4_buf_16x_unused));
2701cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
2702 .in1(1'b0),
2703 .out(spare4_nor2_16x_unused));
2704cl_u1_inv_32x spare4_inv_32x (.in(1'b1),
2705 .out(spare4_inv_32x_unused));
2706
2707cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
2708 .siclk(siclk),
2709 .soclk(soclk),
2710 .si(si_5),
2711 .so(so_5),
2712 .d(1'b0),
2713 .q(spare5_flop_unused));
2714assign si_5 = so_4;
2715
2716cl_u1_buf_32x spare5_buf_32x (.in(1'b1),
2717 .out(spare5_buf_32x_unused));
2718cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
2719 .in1(1'b1),
2720 .in2(1'b1),
2721 .out(spare5_nand3_8x_unused));
2722cl_u1_inv_8x spare5_inv_8x (.in(1'b1),
2723 .out(spare5_inv_8x_unused));
2724cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
2725 .in01(1'b1),
2726 .in10(1'b1),
2727 .in11(1'b1),
2728 .out(spare5_aoi22_4x_unused));
2729cl_u1_buf_8x spare5_buf_8x (.in(1'b1),
2730 .out(spare5_buf_8x_unused));
2731cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
2732 .in01(1'b1),
2733 .in10(1'b1),
2734 .in11(1'b1),
2735 .out(spare5_oai22_4x_unused));
2736cl_u1_inv_16x spare5_inv_16x (.in(1'b1),
2737 .out(spare5_inv_16x_unused));
2738cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
2739 .in1(1'b1),
2740 .out(spare5_nand2_16x_unused));
2741cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
2742 .in1(1'b0),
2743 .in2(1'b0),
2744 .out(spare5_nor3_4x_unused));
2745cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
2746 .in1(1'b1),
2747 .out(spare5_nand2_8x_unused));
2748cl_u1_buf_16x spare5_buf_16x (.in(1'b1),
2749 .out(spare5_buf_16x_unused));
2750cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
2751 .in1(1'b0),
2752 .out(spare5_nor2_16x_unused));
2753cl_u1_inv_32x spare5_inv_32x (.in(1'b1),
2754 .out(spare5_inv_32x_unused));
2755
2756cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
2757 .siclk(siclk),
2758 .soclk(soclk),
2759 .si(si_6),
2760 .so(so_6),
2761 .d(1'b0),
2762 .q(spare6_flop_unused));
2763assign si_6 = so_5;
2764
2765cl_u1_buf_32x spare6_buf_32x (.in(1'b1),
2766 .out(spare6_buf_32x_unused));
2767cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
2768 .in1(1'b1),
2769 .in2(1'b1),
2770 .out(spare6_nand3_8x_unused));
2771cl_u1_inv_8x spare6_inv_8x (.in(1'b1),
2772 .out(spare6_inv_8x_unused));
2773cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
2774 .in01(1'b1),
2775 .in10(1'b1),
2776 .in11(1'b1),
2777 .out(spare6_aoi22_4x_unused));
2778cl_u1_buf_8x spare6_buf_8x (.in(1'b1),
2779 .out(spare6_buf_8x_unused));
2780cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
2781 .in01(1'b1),
2782 .in10(1'b1),
2783 .in11(1'b1),
2784 .out(spare6_oai22_4x_unused));
2785cl_u1_inv_16x spare6_inv_16x (.in(1'b1),
2786 .out(spare6_inv_16x_unused));
2787cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
2788 .in1(1'b1),
2789 .out(spare6_nand2_16x_unused));
2790cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
2791 .in1(1'b0),
2792 .in2(1'b0),
2793 .out(spare6_nor3_4x_unused));
2794cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
2795 .in1(1'b1),
2796 .out(spare6_nand2_8x_unused));
2797cl_u1_buf_16x spare6_buf_16x (.in(1'b1),
2798 .out(spare6_buf_16x_unused));
2799cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
2800 .in1(1'b0),
2801 .out(spare6_nor2_16x_unused));
2802cl_u1_inv_32x spare6_inv_32x (.in(1'b1),
2803 .out(spare6_inv_32x_unused));
2804
2805cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
2806 .siclk(siclk),
2807 .soclk(soclk),
2808 .si(si_7),
2809 .so(so_7),
2810 .d(vuad_err_true_c2),
2811 .q(vuad_err_true_c3));
2812assign si_7 = so_6;
2813
2814cl_u1_buf_32x spare7_buf_32x (.in(1'b1),
2815 .out(spare7_buf_32x_unused));
2816cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
2817 .in1(1'b1),
2818 .in2(1'b1),
2819 .out(spare7_nand3_8x_unused));
2820cl_u1_inv_8x spare7_inv_8x (.in(1'b1),
2821 .out(spare7_inv_8x_unused));
2822cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
2823 .in01(1'b1),
2824 .in10(1'b1),
2825 .in11(1'b1),
2826 .out(spare7_aoi22_4x_unused));
2827cl_u1_buf_8x spare7_buf_8x (.in(1'b1),
2828 .out(spare7_buf_8x_unused));
2829cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
2830 .in01(1'b1),
2831 .in10(1'b1),
2832 .in11(1'b1),
2833 .out(spare7_oai22_4x_unused));
2834cl_u1_inv_16x spare7_inv_16x (.in(1'b1),
2835 .out(spare7_inv_16x_unused));
2836cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
2837 .in1(1'b1),
2838 .out(spare7_nand2_16x_unused));
2839cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
2840 .in1(1'b0),
2841 .in2(1'b0),
2842 .out(spare7_nor3_4x_unused));
2843cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
2844 .in1(1'b1),
2845 .out(spare7_nand2_8x_unused));
2846cl_u1_buf_16x spare7_buf_16x (.in(1'b1),
2847 .out(spare7_buf_16x_unused));
2848cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
2849 .in1(1'b0),
2850 .out(spare7_nor2_16x_unused));
2851cl_u1_inv_32x spare7_inv_32x (.in(1'b1),
2852 .out(spare7_inv_32x_unused));
2853
2854cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
2855 .siclk(siclk),
2856 .soclk(soclk),
2857 .si(si_8),
2858 .so(so_8),
2859 .d(1'b0),
2860 .q(spare8_flop_unused));
2861assign si_8 = so_7;
2862
2863cl_u1_buf_32x spare8_buf_32x (.in(1'b1),
2864 .out(spare8_buf_32x_unused));
2865cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
2866 .in1(1'b1),
2867 .in2(1'b1),
2868 .out(spare8_nand3_8x_unused));
2869cl_u1_inv_8x spare8_inv_8x (.in(1'b1),
2870 .out(spare8_inv_8x_unused));
2871cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
2872 .in01(1'b1),
2873 .in10(1'b1),
2874 .in11(1'b1),
2875 .out(spare8_aoi22_4x_unused));
2876cl_u1_buf_8x spare8_buf_8x (.in(1'b1),
2877 .out(spare8_buf_8x_unused));
2878cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
2879 .in01(1'b1),
2880 .in10(1'b1),
2881 .in11(1'b1),
2882 .out(spare8_oai22_4x_unused));
2883cl_u1_inv_16x spare8_inv_16x (.in(1'b1),
2884 .out(spare8_inv_16x_unused));
2885cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
2886 .in1(1'b1),
2887 .out(spare8_nand2_16x_unused));
2888cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
2889 .in1(1'b0),
2890 .in2(1'b0),
2891 .out(spare8_nor3_4x_unused));
2892cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
2893 .in1(1'b1),
2894 .out(spare8_nand2_8x_unused));
2895cl_u1_buf_16x spare8_buf_16x (.in(1'b1),
2896 .out(spare8_buf_16x_unused));
2897cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
2898 .in1(1'b0),
2899 .out(spare8_nor2_16x_unused));
2900cl_u1_inv_32x spare8_inv_32x (.in(1'b1),
2901 .out(spare8_inv_32x_unused));
2902
2903cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
2904 .siclk(siclk),
2905 .soclk(soclk),
2906 .si(si_9),
2907 .so(so_9),
2908 .d(1'b0),
2909 .q(spare9_flop_unused));
2910assign si_9 = so_8;
2911
2912cl_u1_buf_32x spare9_buf_32x (.in(1'b1),
2913 .out(spare9_buf_32x_unused));
2914cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
2915 .in1(1'b1),
2916 .in2(1'b1),
2917 .out(spare9_nand3_8x_unused));
2918cl_u1_inv_8x spare9_inv_8x (.in(1'b1),
2919 .out(spare9_inv_8x_unused));
2920cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
2921 .in01(1'b1),
2922 .in10(1'b1),
2923 .in11(1'b1),
2924 .out(spare9_aoi22_4x_unused));
2925cl_u1_buf_8x spare9_buf_8x (.in(1'b1),
2926 .out(spare9_buf_8x_unused));
2927cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
2928 .in01(1'b1),
2929 .in10(1'b1),
2930 .in11(1'b1),
2931 .out(spare9_oai22_4x_unused));
2932cl_u1_inv_16x spare9_inv_16x (.in(1'b1),
2933 .out(spare9_inv_16x_unused));
2934cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
2935 .in1(1'b1),
2936 .out(spare9_nand2_16x_unused));
2937cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
2938 .in1(1'b0),
2939 .in2(1'b0),
2940 .out(spare9_nor3_4x_unused));
2941cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
2942 .in1(1'b1),
2943 .out(spare9_nand2_8x_unused));
2944cl_u1_buf_16x spare9_buf_16x (.in(1'b1),
2945 .out(spare9_buf_16x_unused));
2946cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
2947 .in1(1'b0),
2948 .out(spare9_nor2_16x_unused));
2949cl_u1_inv_32x spare9_inv_32x (.in(1'b1),
2950 .out(spare9_inv_32x_unused));
2951
2952cl_sc1_msff_8x spare10_flop (.l1clk(l1clk),
2953 .siclk(siclk),
2954 .soclk(soclk),
2955 .si(si_10),
2956 .so(so_10),
2957 .d(1'b0),
2958 .q(spare10_flop_unused));
2959assign si_10 = so_9;
2960
2961cl_u1_buf_32x spare10_buf_32x (.in(1'b1),
2962 .out(spare10_buf_32x_unused));
2963cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1),
2964 .in1(1'b1),
2965 .in2(1'b1),
2966 .out(spare10_nand3_8x_unused));
2967cl_u1_inv_8x spare10_inv_8x (.in(1'b1),
2968 .out(spare10_inv_8x_unused));
2969cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1),
2970 .in01(1'b1),
2971 .in10(1'b1),
2972 .in11(1'b1),
2973 .out(spare10_aoi22_4x_unused));
2974cl_u1_buf_8x spare10_buf_8x (.in(1'b1),
2975 .out(spare10_buf_8x_unused));
2976cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1),
2977 .in01(1'b1),
2978 .in10(1'b1),
2979 .in11(1'b1),
2980 .out(spare10_oai22_4x_unused));
2981cl_u1_inv_16x spare10_inv_16x (.in(1'b1),
2982 .out(spare10_inv_16x_unused));
2983cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1),
2984 .in1(1'b1),
2985 .out(spare10_nand2_16x_unused));
2986cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0),
2987 .in1(1'b0),
2988 .in2(1'b0),
2989 .out(spare10_nor3_4x_unused));
2990cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1),
2991 .in1(1'b1),
2992 .out(spare10_nand2_8x_unused));
2993cl_u1_buf_16x spare10_buf_16x (.in(1'b1),
2994 .out(spare10_buf_16x_unused));
2995cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0),
2996 .in1(1'b0),
2997 .out(spare10_nor2_16x_unused));
2998cl_u1_inv_32x spare10_inv_32x (.in(1'b1),
2999 .out(spare10_inv_32x_unused));
3000
3001cl_sc1_msff_8x spare11_flop (.l1clk(l1clk),
3002 .siclk(siclk),
3003 .soclk(soclk),
3004 .si(si_11),
3005 .so(so_11),
3006 .d(1'b0),
3007 .q(spare11_flop_unused));
3008assign si_11 = so_10;
3009
3010cl_u1_buf_32x spare11_buf_32x (.in(1'b1),
3011 .out(spare11_buf_32x_unused));
3012cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1),
3013 .in1(1'b1),
3014 .in2(1'b1),
3015 .out(spare11_nand3_8x_unused));
3016cl_u1_inv_8x spare11_inv_8x (.in(1'b1),
3017 .out(spare11_inv_8x_unused));
3018cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1),
3019 .in01(1'b1),
3020 .in10(1'b1),
3021 .in11(1'b1),
3022 .out(spare11_aoi22_4x_unused));
3023cl_u1_buf_8x spare11_buf_8x (.in(1'b1),
3024 .out(spare11_buf_8x_unused));
3025cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1),
3026 .in01(1'b1),
3027 .in10(1'b1),
3028 .in11(1'b1),
3029 .out(spare11_oai22_4x_unused));
3030cl_u1_inv_16x spare11_inv_16x (.in(1'b1),
3031 .out(spare11_inv_16x_unused));
3032cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1),
3033 .in1(1'b1),
3034 .out(spare11_nand2_16x_unused));
3035cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0),
3036 .in1(1'b0),
3037 .in2(1'b0),
3038 .out(spare11_nor3_4x_unused));
3039cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1),
3040 .in1(1'b1),
3041 .out(spare11_nand2_8x_unused));
3042cl_u1_buf_16x spare11_buf_16x (.in(1'b1),
3043 .out(spare11_buf_16x_unused));
3044cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0),
3045 .in1(1'b0),
3046 .out(spare11_nor2_16x_unused));
3047cl_u1_inv_32x spare11_inv_32x (.in(1'b1),
3048 .out(spare11_inv_32x_unused));
3049
3050cl_sc1_msff_8x spare12_flop (.l1clk(l1clk),
3051 .siclk(siclk),
3052 .soclk(soclk),
3053 .si(si_12),
3054 .so(so_12),
3055 .d(1'b0),
3056 .q(spare12_flop_unused));
3057assign si_12 = so_11;
3058
3059cl_u1_buf_32x spare12_buf_32x (.in(1'b1),
3060 .out(spare12_buf_32x_unused));
3061cl_u1_nand3_8x spare12_nand3_8x (.in0(1'b1),
3062 .in1(1'b1),
3063 .in2(1'b1),
3064 .out(spare12_nand3_8x_unused));
3065cl_u1_inv_8x spare12_inv_8x (.in(1'b1),
3066 .out(spare12_inv_8x_unused));
3067cl_u1_aoi22_4x spare12_aoi22_4x (.in00(1'b1),
3068 .in01(1'b1),
3069 .in10(1'b1),
3070 .in11(1'b1),
3071 .out(spare12_aoi22_4x_unused));
3072cl_u1_buf_8x spare12_buf_8x (.in(1'b1),
3073 .out(spare12_buf_8x_unused));
3074cl_u1_oai22_4x spare12_oai22_4x (.in00(1'b1),
3075 .in01(1'b1),
3076 .in10(1'b1),
3077 .in11(1'b1),
3078 .out(spare12_oai22_4x_unused));
3079cl_u1_inv_16x spare12_inv_16x (.in(1'b1),
3080 .out(spare12_inv_16x_unused));
3081cl_u1_nand2_16x spare12_nand2_16x (.in0(1'b1),
3082 .in1(1'b1),
3083 .out(spare12_nand2_16x_unused));
3084cl_u1_nor3_4x spare12_nor3_4x (.in0(1'b0),
3085 .in1(1'b0),
3086 .in2(1'b0),
3087 .out(spare12_nor3_4x_unused));
3088cl_u1_nand2_8x spare12_nand2_8x (.in0(1'b1),
3089 .in1(1'b1),
3090 .out(spare12_nand2_8x_unused));
3091cl_u1_buf_16x spare12_buf_16x (.in(1'b1),
3092 .out(spare12_buf_16x_unused));
3093cl_u1_nor2_16x spare12_nor2_16x (.in0(1'b0),
3094 .in1(1'b0),
3095 .out(spare12_nor2_16x_unused));
3096cl_u1_inv_32x spare12_inv_32x (.in(1'b1),
3097 .out(spare12_inv_32x_unused));
3098
3099cl_sc1_msff_8x spare13_flop (.l1clk(l1clk),
3100 .siclk(siclk),
3101 .soclk(soclk),
3102 .si(si_13),
3103 .so(so_13),
3104 .d(1'b0),
3105 .q(spare13_flop_unused));
3106assign si_13 = so_12;
3107
3108cl_u1_buf_32x spare13_buf_32x (.in(1'b1),
3109 .out(spare13_buf_32x_unused));
3110cl_u1_nand3_8x spare13_nand3_8x (.in0(1'b1),
3111 .in1(1'b1),
3112 .in2(1'b1),
3113 .out(spare13_nand3_8x_unused));
3114cl_u1_inv_8x spare13_inv_8x (.in(1'b1),
3115 .out(spare13_inv_8x_unused));
3116cl_u1_aoi22_4x spare13_aoi22_4x (.in00(1'b1),
3117 .in01(1'b1),
3118 .in10(1'b1),
3119 .in11(1'b1),
3120 .out(spare13_aoi22_4x_unused));
3121cl_u1_buf_8x spare13_buf_8x (.in(1'b1),
3122 .out(spare13_buf_8x_unused));
3123cl_u1_oai22_4x spare13_oai22_4x (.in00(1'b1),
3124 .in01(1'b1),
3125 .in10(1'b1),
3126 .in11(1'b1),
3127 .out(spare13_oai22_4x_unused));
3128cl_u1_inv_16x spare13_inv_16x (.in(1'b1),
3129 .out(spare13_inv_16x_unused));
3130cl_u1_nand2_16x spare13_nand2_16x (.in0(1'b1),
3131 .in1(1'b1),
3132 .out(spare13_nand2_16x_unused));
3133cl_u1_nor3_4x spare13_nor3_4x (.in0(1'b0),
3134 .in1(1'b0),
3135 .in2(1'b0),
3136 .out(spare13_nor3_4x_unused));
3137cl_u1_nand2_8x spare13_nand2_8x (.in0(1'b1),
3138 .in1(1'b1),
3139 .out(spare13_nand2_8x_unused));
3140cl_u1_buf_16x spare13_buf_16x (.in(1'b1),
3141 .out(spare13_buf_16x_unused));
3142cl_u1_nor2_16x spare13_nor2_16x (.in0(1'b0),
3143 .in1(1'b0),
3144 .out(spare13_nor2_16x_unused));
3145cl_u1_inv_32x spare13_inv_32x (.in(1'b1),
3146 .out(spare13_inv_32x_unused));
3147
3148cl_sc1_msff_8x spare14_flop (.l1clk(l1clk),
3149 .siclk(siclk),
3150 .soclk(soclk),
3151 .si(si_14),
3152 .so(so_14),
3153 .d(1'b0),
3154 .q(spare14_flop_unused));
3155assign si_14 = so_13;
3156
3157cl_u1_buf_32x spare14_buf_32x (.in(1'b1),
3158 .out(spare14_buf_32x_unused));
3159cl_u1_nand3_8x spare14_nand3_8x (.in0(1'b1),
3160 .in1(1'b1),
3161 .in2(1'b1),
3162 .out(spare14_nand3_8x_unused));
3163cl_u1_inv_8x spare14_inv_8x (.in(1'b1),
3164 .out(spare14_inv_8x_unused));
3165cl_u1_aoi22_4x spare14_aoi22_4x (.in00(1'b1),
3166 .in01(1'b1),
3167 .in10(1'b1),
3168 .in11(1'b1),
3169 .out(spare14_aoi22_4x_unused));
3170cl_u1_buf_8x spare14_buf_8x (.in(1'b1),
3171 .out(spare14_buf_8x_unused));
3172cl_u1_oai22_4x spare14_oai22_4x (.in00(1'b1),
3173 .in01(1'b1),
3174 .in10(1'b1),
3175 .in11(1'b1),
3176 .out(spare14_oai22_4x_unused));
3177cl_u1_inv_16x spare14_inv_16x (.in(1'b1),
3178 .out(spare14_inv_16x_unused));
3179cl_u1_nand2_16x spare14_nand2_16x (.in0(1'b1),
3180 .in1(1'b1),
3181 .out(spare14_nand2_16x_unused));
3182cl_u1_nor3_4x spare14_nor3_4x (.in0(1'b0),
3183 .in1(1'b0),
3184 .in2(1'b0),
3185 .out(spare14_nor3_4x_unused));
3186cl_u1_nand2_8x spare14_nand2_8x (.in0(1'b1),
3187 .in1(1'b1),
3188 .out(spare14_nand2_8x_unused));
3189cl_u1_buf_16x spare14_buf_16x (.in(1'b1),
3190 .out(spare14_buf_16x_unused));
3191cl_u1_nor2_16x spare14_nor2_16x (.in0(1'b0),
3192 .in1(1'b0),
3193 .out(spare14_nor2_16x_unused));
3194cl_u1_inv_32x spare14_inv_32x (.in(1'b1),
3195 .out(spare14_inv_32x_unused));
3196assign spares_scanout = so_14;
3197
3198assign dbginit_l = 1'b1;
3199
3200wire [31:0] cas_ctrue_set_preerror_c9;
3201wire [31:0] clr_mb_l2_rdy_pfice;
3202wire [31:0] vuad_ack_pending, vuad_ce_replay;
3203
3204wire set_dep_ldifetch_miss_c2; // BS and SR 11/07/03, store pipelining support
3205wire set_dep_ldifetch_miss_c3; // BS and SR 11/07/03, store pipelining support
3206wire mb_hit_dep_one; // BS and SR 11/07/03, store pipelining support
3207wire [31:0] mb_dep_prev; // BS and SR 11/07/03, store pipelining support
3208wire [31:0] mb_dep; // BS and SR 11/07/03, store pipelining support
3209wire misbuf_hit_st_dep_zero; // BS and SR 11/07/03, store pipelining support
3210wire mbf_insert_c2;
3211wire mbf_delete_miss_c2;
3212wire mbf_delete_c2, mbf_delete_c3;
3213wire [31:0] reset_valid_bit_c3; // BS & SR 11/04/03, MB grows to 32
3214wire [31:0] mb_write_ptr_c2, mb_write_ptr_c3 ; // BS & SR 11/04/03, MB grows to 32
3215wire [4:0] mb_entry_c3;// BS & SR 11/04/03, MB grows to 32
3216wire [31:0] dec_mb_entry_c3; // BS & SR 11/04/03, MB grows to 32
3217
3218wire [5:0] mb_count_prev; // BS & SR 11/04/03, MB grows to 32
3219wire [5:0] mb_count_c4; // Actual count. // BS & SR 11/04/03, MB grows to 32
3220wire [5:0] mb_count_plus1; // BS & SR 11/04/03, MB grows to 32
3221wire [5:0] mb_count_minus1; // BS & SR 11/04/03, MB grows to 32
3222wire cnt_reset, mb_count_en ;
3223wire [31:0] mb_tag_wr_wl_c3; // BS & SR 11/04/03, MB grows to 32
3224
3225wire [4:0] inst_mb_entry_c2; // BS & SR 11/04/03, MB grows to 32
3226wire [31:0] cam_hit_vec_c1 ; // BS & SR 11/04/03, MB grows to 32
3227wire [31:0] hit_off_bypass_vec_c1 ; // BS & SR 11/04/03, MB grows to 32
3228wire [31:0] hit_on_bypass_vec_c1 ; // BS & SR 11/04/03, MB grows to 32
3229wire [31:0] tmp_cam_hit_vec_c1, tmp_cam_hit_vec_c2 ;// BS & SR 11/04/03, MB grows to 32
3230wire tmp_cam_hit_c2;
3231wire misbuf_hit_c2;
3232wire [31:0] misbuf_hit_vec_c2, misbuf_hit_vec_c3; // BS & SR 11/04/03, MB grows to 32
3233wire [31:0] dec_mb_entry_c2; // BS & SR 11/04/03, MB grows to 32
3234
3235wire inst_mb_c3;
3236wire mb_inst_vld_c3;
3237wire mb_rewrite_en_c3;
3238wire mbdata_wr_en_c3, mbdata_wr_en_c4;
3239wire mbdata_wr_en_c5, mbdata_wr_en_c52, mbdata_wr_en_c6; // BS 03/11/04 extra cycle for mem access
3240wire mbdata_wr_en_c7 ;
3241
3242wire [4:0] enc_tag_wr_wl_c2, enc_tag_wr_wl_c3; // BS & SR 11/04/03, MB grows to 32
3243wire [31:0] insert_ptr_c8 ; // BS & SR 11/04/03, MB grows to 32
3244wire [31:0] mb_data_wr_wl_c8 ; // BS & SR 11/04/03, MB grows to 32
3245
3246wire [4:0] enc_data_wr_wl_c4, enc_data_wr_wl_c5; // BS & SR 11/04/03, MB grows to 32
3247wire [4:0] enc_data_wr_wl_c52; // BS 03/11/04 extra cycle for mem access
3248wire [4:0] enc_data_wr_wl_c6, enc_data_wr_wl_c7; // BS & SR 11/04/03, MB grows to 32
3249wire [4:0] enc_data_wr_wl_c8 ; // BS & SR 11/04/03, MB grows to 32
3250
3251// Control Bits.
3252wire [31:0] mb_valid_prev, mb_valid; // BS & SR 11/04/03, MB grows to 32
3253wire [31:0] mb_bis_prev, mb_bis; // BS & SR 11/04/03, MB grows to 32
3254wire [31:0] mb_rdma_prev, mb_rdma; // BS & SR 11/04/03, MB grows to 32
3255wire [31:0] mb_young_prev, mb_young ; // BS & SR 11/04/03, MB grows to 32
3256wire [31:0] mb_ctrue_prev, mb_ctrue ; // BS & SR 11/04/03, MB grows to 32
3257wire [31:0] mb_mcu_ready, mb_mcu_ready_in; // BS & SR 11/04/03, MB grows to 32
3258wire [31:0] mb_evict_ready, mb_evict_ready_in ; // BS & SR 11/04/03, MB grows to 32
3259wire [31:0] mb_tecc_ready, mb_tecc_ready_in ; // BS & SR 11/04/03, MB grows to 32
3260wire [31:0] mb_data_vld_in, mb_data_vld; // BS & SR 11/04/03, MB grows to 32
3261wire [31:0] mb_l2_ready_in, mb_l2_ready; // BS & SR 11/04/03, MB grows to 32
3262wire [31:0] mb_way_vld_in , mb_way_vld ; // BS & SR 11/04/03, MB grows to 32
3263wire [31:0] mb_fbid_vld_in , mb_fbid_vld ; // BS & SR 11/04/03, MB grows to 32
3264wire [31:0] mb_corr_err_in, mb_corr_err ; // BS & SR 11/04/03, MB grows to 32
3265wire [31:0] mb_uncorr_err_in, mb_uncorr_err ; // BS & SR 11/04/03, MB grows to 32
3266
3267wire [3:0] way0, way1, way2, way3 ;
3268wire [3:0] way4, way5, way6, way7 ;
3269wire [3:0] way8, way9, way10, way11 ;
3270wire [3:0] way12, way13, way14, way15 ;
3271wire [3:0] way16, way17, way18, way19;
3272wire [3:0] way20, way21, way23 , way22 ;
3273wire [3:0] way24, way25, way26 , way27 ;
3274wire [3:0] way28, way29, way30 , way31 ;
3275
3276
3277
3278wire [4:0] next_link_entry0, next_link_entry1, next_link_entry2, next_link_entry3;
3279// BS & SR 11/04/03, MB grows to 32
3280wire [4:0] next_link_entry4, next_link_entry5, next_link_entry6, next_link_entry7;
3281// BS & SR 11/04/03, MB grows to 32
3282wire [4:0] next_link_entry8, next_link_entry9, next_link_entry10, next_link_entry11;
3283// BS & SR 11/04/03, MB grows to 32
3284wire [4:0] next_link_entry12, next_link_entry13, next_link_entry14, next_link_entry15;
3285wire [4:0] next_link_entry16, next_link_entry17, next_link_entry18, next_link_entry19;
3286wire [4:0] next_link_entry20, next_link_entry21, next_link_entry22, next_link_entry23;
3287wire [4:0] next_link_entry24, next_link_entry25, next_link_entry26, next_link_entry27;
3288wire [4:0] next_link_entry28, next_link_entry29, next_link_entry30, next_link_entry31;
3289// BS & SR 11/04/03, MB grows to 32
3290wire [2:0] fbid0, fbid1, fbid2, fbid3 ;
3291wire [2:0] fbid4, fbid5, fbid6, fbid7 ;
3292wire [2:0] fbid8, fbid9, fbid10, fbid11 ;
3293wire [2:0] fbid12, fbid13, fbid14, fbid15 ;
3294wire [2:0] fbid16, fbid17, fbid18, fbid19 ;
3295wire [2:0] fbid20, fbid21, fbid22, fbid23 ;
3296wire [2:0] fbid24, fbid25, fbid26, fbid27 ;
3297wire [2:0] fbid28, fbid29, fbid30, fbid31 ;
3298
3299
3300
3301wire [31:0] mb_way_fb_vld_reset ; // BS & SR 11/04/03, MB grows to 32
3302wire [31:0] way_fbid_vld; // BS & SR 11/04/03, MB grows to 32
3303
3304// Mux selects for muxing out the next link field
3305wire sel_0to3, sel_4to7, sel_8to11, sel_12to15 ;
3306wire sel_19to16, sel_23to20, sel_27to24, sel_31to28;
3307wire sel_default_0123, sel_default_4567 ;
3308wire sel_default_89ab, sel_default_cdef ;
3309wire sel_default_a_0123, sel_default_a_4567, sel_default_a_89ab, sel_default_a_cdef;
3310wire sel_default_0to15; // BS & SR 11/04/03, MB grows to 32
3311wire sel_default_16to31; // BS & SR 11/04/03, MB grows to 32
3312
3313wire misbuf_next_vld_c3;
3314wire [4:0] misbuf_next_link_c3; // BS & SR 11/04/03, MB grows to 32
3315wire [4:0] misbuf_next_link_a_c3; // BS & SR 11/04/03, MB grows to 32
3316wire [4:0] misbuf_next_link_b_c3; // BS & SR 11/04/03, MB grows to 32
3317
3318
3319wire inst_mb_c4, tag_inst_mb_c5, inst_mb_c6;
3320wire inst_mb_c7, inst_mb_c8;
3321wire [31:0] cas_rdy_set_c9; // BS & SR 11/04/03, MB grows to 32
3322wire [31:0] cas_ctrue_set_c9; // BS & SR 11/04/03, MB grows to 32
3323wire [4:0] misbuf_ctrue_rdy_entry; // BS & SR 11/04/03, MB grows to 32
3324wire [4:0] nextlink_id0123, nextlink_id4567 ; // BS & SR 11/04/03, MB grows to 32
3325wire [4:0] nextlink_id89ab, nextlink_idcdef ; // BS & SR 11/04/03, MB grows to 32
3326wire [31:0] next_link_wr_en_c3 ; // BS & SR 11/04/03, MB grows to 32
3327wire [4:0] enc_data_wr_wl_c3; // BS & SR 11/04/03, MB grows to 32
3328
3329wire mb_hit_off_c1_d1;
3330
3331wire misbuf_dep_inst_c3, misbuf_dep_inst_c4;
3332wire misbuf_dep_inst_c5, misbuf_dep_inst_c52, misbuf_dep_inst_c6; // BS 03/11/04 extra cycle for mem access
3333wire misbuf_dep_inst_c7;
3334
3335
3336wire misbuf_mark_evict_tmp_c2;
3337wire misbuf_mark_evict_tmp_c3;
3338wire misbuf_mark_mcu_rdy_c3;
3339wire mcu_rdy_c4, mcu_rdy_c5 , mcu_rdy_c52; // BS 03/11/04 extra cycle for mem access
3340wire mcu_rdy_c6, mcu_rdy_c7, mcu_rdy_c8 ;
3341wire misbuf_evict_c7;
3342
3343wire misbuf_tecc_c4, misbuf_tecc_c5 , misbuf_tecc_c52; // BS 03/11/04 extra cycle for mem access
3344wire misbuf_tecc_c6, misbuf_tecc_c7 ;
3345
3346wire [31:0] mcu_ready_set_c8, reset_mcu_ready ; // BS & SR 11/04/03, MB grows to 32
3347wire mcu_pick;
3348
3349wire mcu_ack_pending_in;
3350wire mcu_ack_pend_state;
3351wire mcu_l2t_rd_ack_d1;
3352
3353wire ready_miss_r2;
3354wire [4:0] ld_mbid_r2 ; // BS & SR 11/04/03, MB grows to 32
3355wire [31:0] mb_miss_rdy_r2 ; // BS & SR 11/04/03, MB grows to 32
3356wire st_or_dep_rdy_c5;
3357wire [4:0] dep_mbid_c5; // BS & SR 11/04/03, MB grows to 32
3358wire [31:0] fb_dep_rdy_c5; // BS & SR 11/04/03, MB grows to 32
3359wire cas1_inst_c3;
3360wire mb_dep_rdy_en_c3, mb_dep_rdy_en_c4;
3361wire [31:0] mb_dep_rdy_c4; // BS & SR 11/04/03, MB grows to 32
3362wire [4:0] wbb_dep_mbid_d1; // BS & SR 11/04/03, MB grows to 32
3363wire wbb_dep_rdy_en_d1;
3364wire [31:0] wbb_dep_rdy_d1; // BS & SR 11/04/03, MB grows to 32
3365wire rdmat_dep_rdy_en_d1;
3366wire [4:0] rdmat_dep_mbid_d1; // BS & SR 11/04/03, MB grows to 32
3367wire [31:0] rdmat_dep_rdy_d1; // BS & SR 11/04/03, MB grows to 32
3368
3369wire mbid_vld_in, mbid_vld;
3370wire set_mbid_vld, reset_mbid_vld, set_mbid_vld_prev;
3371wire rdy_csr_inst_en;
3372wire [4:0] csr_mbid; // BS & SR 11/04/03, MB grows to 32
3373wire [31:0] csr_inst_rdy ; // BS & SR 11/04/03, MB grows to 32
3374wire [31:0] cas2_or_pst_rdy_c8; // BS & SR 11/04/03, MB grows to 32
3375wire mcu_pick_prev;
3376
3377wire [31:0] l2_pick_vec, mcu_pick_vec, mb_read_pick_vec ; // BS & SR 11/04/03, MB grows to 32
3378wire [3:0] pick_quad0_in, pick_quad1_in, pick_quad2_in, pick_quad3_in;
3379wire [3:0] pick_quad4_in, pick_quad5_in, pick_quad6_in, pick_quad7_in;
3380wire [7:0] pick_quad_in; // BS & SR 11/04/03, MB grows to 32
3381
3382wire sel_mcu_lshift, sel_mcu_same ;
3383wire [7:0] mcu_pick_state_lshift, mcu_pick_state,mcu_pick_state_prev ; // BS & SR 11/04/03, MB grows to 32
3384
3385wire sel_mcu_lshift_quad0, sel_mcu_same_quad0 ;
3386wire [3:0] mcu_pick_state_lshift_quad0, mcu_pick_state_quad0;
3387wire [3:0] mcu_pick_state_prev_quad0 ;
3388
3389wire sel_mcu_lshift_quad1, sel_mcu_same_quad1 ;
3390wire [3:0] mcu_pick_state_lshift_quad1, mcu_pick_state_quad1;
3391wire [3:0] mcu_pick_state_prev_quad1 ;
3392
3393wire sel_mcu_lshift_quad2, sel_mcu_same_quad2 ;
3394wire [3:0] mcu_pick_state_lshift_quad2, mcu_pick_state_quad2;
3395wire [3:0] mcu_pick_state_prev_quad2 ;
3396
3397wire sel_mcu_lshift_quad3, sel_mcu_same_quad3 ;
3398wire [3:0] mcu_pick_state_lshift_quad3, mcu_pick_state_quad3;
3399wire [3:0] mcu_pick_state_prev_quad3 ;
3400
3401wire sel_mcu_lshift_quad4, sel_mcu_same_quad4 ;
3402wire [3:0] mcu_pick_state_lshift_quad4, mcu_pick_state_quad4;
3403wire [3:0] mcu_pick_state_prev_quad4 ;
3404
3405wire sel_mcu_lshift_quad5, sel_mcu_same_quad5 ;
3406wire [3:0] mcu_pick_state_lshift_quad5, mcu_pick_state_quad5;
3407wire [3:0] mcu_pick_state_prev_quad5 ;
3408
3409wire sel_mcu_lshift_quad6, sel_mcu_same_quad6 ;
3410wire [3:0] mcu_pick_state_lshift_quad6, mcu_pick_state_quad6;
3411wire [3:0] mcu_pick_state_prev_quad6 ;
3412
3413wire sel_mcu_lshift_quad7, sel_mcu_same_quad7 ;
3414wire [3:0] mcu_pick_state_lshift_quad7, mcu_pick_state_quad7;
3415wire [3:0] mcu_pick_state_prev_quad7 ;
3416
3417
3418wire sel_l2_lshift, sel_l2_same, init_pick_state;
3419wire [7:0] l2_pick_state_prev, l2_pick_state_lshift; // BS & SR 11/04/03, MB grows to 32
3420wire [7:0] l2_pick_state; // BS & SR 11/04/03, MB grows to 32
3421wire sel_l2_lshift_quad0, sel_l2_same_quad0, init_pick_state_quad0;
3422wire [3:0] l2_pick_state_prev_quad0, l2_pick_state_lshift_quad0;
3423wire [3:0] l2_pick_state_quad0;
3424wire sel_l2_lshift_quad1, sel_l2_same_quad1, init_pick_state_quad1;
3425wire [3:0] l2_pick_state_prev_quad1, l2_pick_state_lshift_quad1;
3426wire [3:0] l2_pick_state_quad1;
3427wire sel_l2_lshift_quad2, sel_l2_same_quad2, init_pick_state_quad2;
3428wire [3:0] l2_pick_state_prev_quad2, l2_pick_state_lshift_quad2;
3429wire [3:0] l2_pick_state_quad2;
3430wire sel_l2_lshift_quad3, sel_l2_same_quad3, init_pick_state_quad3;
3431wire [3:0] l2_pick_state_prev_quad3, l2_pick_state_lshift_quad3;
3432wire [3:0] l2_pick_state_quad3;
3433wire [3:0] l2_pick_state_prev_quad4, l2_pick_state_lshift_quad4; // BS & SR 11/04/03, MB grows to 32
3434wire [3:0] l2_pick_state_quad4; // BS & SR 11/04/03, MB grows to 32
3435wire [3:0] l2_pick_state_prev_quad5, l2_pick_state_lshift_quad5; // BS & SR 11/04/03, MB grows to 32
3436wire [3:0] l2_pick_state_quad5; // BS & SR 11/04/03, MB grows to 32
3437wire [3:0] l2_pick_state_prev_quad6, l2_pick_state_lshift_quad6; // BS & SR 11/04/03, MB grows to 32
3438wire [3:0] l2_pick_state_quad6; // BS & SR 11/04/03, MB grows to 32
3439wire [3:0] l2_pick_state_prev_quad7, l2_pick_state_lshift_quad7; // BS & SR 11/04/03, MB grows to 32
3440wire [3:0] l2_pick_state_quad7; // BS & SR 11/04/03, MB grows to 32
3441wire [7:0] pick_state;
3442wire [3:0] pick_state_quad0, pick_state_quad1;
3443wire [3:0] pick_state_quad2, pick_state_quad3;
3444wire pick_s0_quad0, pick_s1_quad0, pick_s2_quad0, pick_s3_quad0;
3445wire pick_s0_quad1, pick_s1_quad1, pick_s2_quad1, pick_s3_quad1;
3446wire pick_s0_quad2, pick_s1_quad2, pick_s2_quad2, pick_s3_quad2;
3447wire pick_s0_quad3, pick_s1_quad3, pick_s2_quad3, pick_s3_quad3;
3448wire pick_s0, pick_s1, pick_s2, pick_s3 ;
3449wire [3:0] pick_quad0_sel, pick_quad1_sel ;
3450wire [3:0] pick_quad2_sel, pick_quad3_sel ;
3451wire [3:0] pick_quad4_sel, pick_quad5_sel ; // BS & SR 11/04/03, MB grows to 32
3452wire [3:0] pick_quad6_sel, pick_quad7_sel ; // BS & SR 11/04/03, MB grows to 32
3453
3454wire [7:0] pick_oct_sel; // BS & SR 11/04/03, MB grows to 32
3455wire [31:0] picker_out, picker_out_d1, picker_out_d2 ; // BS & SR 11/04/03, MB grows to 32
3456wire picker_out_qual;
3457
3458wire l2_pick, l2_pick_d1;
3459wire l2_wait_set, l2_wait_reset ;
3460wire l2_wait_in, l2_wait ;
3461wire l2_pick_read_ctrue;
3462wire evict_vld_unqual_c3;
3463
3464wire evict_vld_c3, evict_vld_c4;
3465wire [31:0] dec_wr_wl_c4; // BS & SR 11/04/03, MB grows to 32
3466 wire [31:0] dec_mcu_pick_d2 ; // BS & SR 11/04/03, MB grows to 32
3467
3468wire way_fbid_rd_vld_prev;
3469wire fbsel_0to3, fbsel_4to7, fbsel_8to11;
3470wire fbsel_def_0123, fbsel_def_4567, fbsel_def_89ab, fbsel_def_cdef ;
3471wire fbsel_def_vld ;
3472wire fbsel_15to12 , fbsel_19to16 , fbsel_27to24, fbsel_31to28;
3473wire [3:0] way0123, way4567, way89ab, waycdef;
3474wire [3:0] waya89ab, waya4567, waya0123, wayacdef;
3475wire [2:0] fbid0123, fbid4567, fbid89ab, fbidcdef;
3476
3477wire [31:0] mb_entry_dec_c1; // BS & SR 11/04/03, MB grows to 32
3478wire misbuf_corr_err_unqual_c2, misbuf_uncorr_err_unqual_c2;
3479wire misbuf_corr_err_c1, misbuf_uncorr_err_c1 ;
3480wire [4:0] mbf_insert_mbid_c3; // BS & SR 11/04/03, MB grows to 32
3481wire mbf_insert_c3;
3482wire nondep_fbhit_c2_unqual;
3483wire rdma_inst_c3;
3484wire [31:0] mb_l2_ready_qual_in, mb_l2_ready_qual ; // BS & SR 11/04/03, MB grows to 32
3485
3486wire mbf_insert_c3_tmp, inst_mb_c3_1;
3487wire wr64_inst_c3;
3488
3489wire mb_rdma_count_en;
3490wire [3:0] mb_rdma_count_c4, mb_rdma_count_plus1;
3491wire [3:0] mb_rdma_count_prev, mb_rdma_count_minus1;
3492wire inc_rdma_cnt_c3;
3493
3494wire buffer_miss_vld_c2, buffer_miss_vld_c3;
3495wire rdma_comp_rdy_c3, rdma_comp_rdy_c4, rdma_comp_rdy_c5, rdma_comp_rdy_c52; // BS 03/11/04 extra cycle for mem access
3496wire rdma_comp_rdy_c6, rdma_comp_rdy_c7, rdma_comp_rdy_c8 ;
3497wire wr64_miss_not_comp_c3;
3498wire ld64_inst_c3, ld64_inst_c4, ld64_inst_c5 , ld64_inst_c52; // BS 03/11/04 extra cycle for mem access
3499wire ld64_inst_c6, ld64_inst_c7 ;
3500
3501wire filbuf_match_c3, filbuf_match_c3_unqual ;
3502wire l2_bypass_mode_on_d1;
3503
3504wire misbuf_rdma_gate_off_c2;
3505wire rdma_reg_vld_c3;
3506wire filbuf_stinst_match_c3;
3507wire dummy_req_d1, dummy_req_d2 ;
3508
3509wire [31:0] mb_cam_hit_vec_c1 ; // BS & SR 11/04/03, MB grows to 32
3510
3511wire tmp_cam_hit_c1_3to0, tmp_cam_hit_c1_7to4;
3512wire tmp_cam_hit_c1_11to8, tmp_cam_hit_c1_15to12;
3513wire tmp_cam_hit_c2_3to0, tmp_cam_hit_c2_7to4;
3514wire tmp_cam_hit_c2_11to8, tmp_cam_hit_c2_15to12;
3515// BS & SR 11/04/03, MB grows to 32
3516wire tmp_cam_hit_c1_19to16, tmp_cam_hit_c1_23to20, tmp_cam_hit_c1_27to24;
3517wire tmp_cam_hit_c1_31to28;
3518wire tmp_cam_hit_c2_19to16, tmp_cam_hit_c2_23to20, tmp_cam_hit_c2_27to24;
3519wire tmp_cam_hit_c2_31to28;
3520
3521wire l2_dir_map_on_d1;
3522wire misbuf_c1c3_match_c1;
3523wire misbuf_c1c2_match_c1, misbuf_c1c2_match_c1_d1;
3524wire [31:0] mb_valid_ifin; // BS & SR 11/04/03, MB grows to 32
3525wire mcu_pick_1, mcu_pick_2_l ;
3526
3527wire evict_par_err_c3, evict_par_err_c4;
3528wire evict_par_err_c5, evict_par_err_c52; // BS 03/11/04 extra cycle for mem access
3529wire evict_par_err_c6, evict_par_err_c7;
3530wire [31:0] mb_tag_wr_wl_c3_tmp; // BS & SR 11/04/03, MB grows to 32
3531
3532wire [31:0] cam_idx_hit_vec_c1, idx_on_bypass_vec_c1;
3533wire [31:0] tmp_idx_hit_vec_c1, tmp_idx_hit_vec_c2;
3534wire [31:0] misbuf_idx_hit_vec_c2, misbuf_idx_hit_vec_c3, misbuf_idx_hit_vec_c3_fnl ;
3535wire tmp_hit_unqual_c2 ;
3536wire nondep_fbhit_c3_unqual;
3537wire hit_vec_qual, idx_hit_vec_qual;
3538wire mbissue_inst_vld_c2;
3539wire mbissue_inst_vld_c3;
3540
3541wire [1:0] cout1;
3542wire [1:0] cout2;
3543wire [1:0] cout3;
3544wire [1:0] cout4;
3545wire [1:0] cout5;
3546
3547wire [2:0] cout2_1;
3548wire [2:0] cout2_2;
3549wire [2:0] cout2_3;
3550wire [2:0] cout2_4; // BS & SR 11/04/03, MB grows to 32
3551wire [2:0] cout2_5; // BS & SR 11/04/03, MB grows to 32
3552
3553
3554wire [3:0] cout3_1, cout3_2; // BS & SR 11/04/03, MB grows to 32
3555wire [4:0] cout4_1 ; // BS & SR 11/04/03, MB grows to 32
3556wire [5:0] cout5_1; // BS & SR 11/04/03, MB grows to 32
3557
3558wire set_mb_idx_full_c4, reset_mb_idx_full_c4 ;
3559wire mb_idx_count_full_c4, mb_idx_count_full_c5;
3560wire [5:0] hit_count_c4;
3561
3562wire mb_rewrite_en_c4;
3563wire mb_rewrite_en_c5, mb_rwrite_en_c52, mb_rewrite_en_c6; // BS 03/11/04 extra cycle for mem access
3564wire mb_rewrite_en_c7, mb_rewrite_en_c8;
3565
3566wire [3:0] dec_low_insert_ptr;
3567wire [7:0] dec_hi_insert_ptr;
3568wire mb_inst_vld_c3_1;
3569wire [31:0] mb_way_fb_vld_tmp; // BS & SR 11/04/03, MB grows to 32
3570wire mb_way_fb_vld_tmp_0to3;
3571wire mb_way_fb_vld_tmp_4to7;
3572wire mb_way_fb_vld_tmp_8to11;
3573wire mb_way_fb_vld_tmp_12to15;
3574wire mb_way_fb_vld_tmp_16to19, mb_way_fb_vld_tmp_20to23;
3575wire mb_way_fb_vld_tmp_24to27, mb_way_fb_vld_tmp_28to31;
3576wire dbb_rst_l;
3577wire misbuf_tecc_c3;
3578wire tag_hit_unqual_c3;
3579wire mb_inst_vld_c3_2;
3580wire misbuf_c1c2_match_c1_d1_1;
3581wire mbf_insert_c3_tmp_1, mbf_delete_c3_tmp_1 ;
3582wire inst_mb_c3_2;
3583wire mcu_pick_2;
3584wire evict_tecc_vld_c3;
3585wire misbuf_dep_inst_c2;
3586wire dep_inst_c3, tecc_c3 ;
3587wire inst_mb_c9;
3588wire [4:0] enc_data_wr_wl_c9; // BS & SR 11/04/03, MB grows to 32
3589wire cas1_hit_c9;
3590wire uncorr_err_c9;
3591wire [31:0] pst_ctrue_set_c8; // BS & SR 11/04/03, MB grows to 32
3592wire misbuf_corr_err_c8;
3593
3594wire rdma_inst_c2;
3595wire fbsel_0to3_d1, fbsel_4to7_d1;
3596wire fbsel_8to11_d1, fbsel_def_vld_d1;
3597wire fbsel_15to12_d1, fbsel_19to16_d1, fbsel_23to20_d1, fbsel_27to24_d1;
3598wire fbsel_def_a_0123, fbsel_def_a_4567, fbsel_def_a_89ab, fbsel_def_a_cdef;
3599wire sel_mux0, sel_mux1;
3600wire sel_mux0123, sel_mux4567;
3601wire sel_mux2, sel_mux3;
3602wire sel_mux4, sel_mux5;
3603wire sel_mux6, sel_mux7;
3604wire [3:0] way0123_d1, way4567_d1 ;
3605wire [3:0] way89ab_d1, waycdef_d1 ;
3606wire [3:0] wayacdef_d1, waya89ab_d1, waya4567_d1, waya0123_d1;
3607wire [2:0] fbid0123_d1, fbid4567_d1;
3608wire [2:0] fbida0123_d1, fbida4567_d1, fbida89ab_d1, fbidacdef_d1;
3609wire [2:0] misbuf_filbuf_fbid_a, misbuf_filbuf_fbid_b;
3610wire [2:0] fbid89ab_d1, fbidcdef_d1;
3611wire [4:0] enc_data_wr_wl_c7_1; // BS & SR 11/04/03, MB grows to 32
3612wire [4:0] mb_entry_c3_1; // BS & SR 11/04/03, MB grows to 32
3613
3614// VUAD ecc change
3615wire [31:0] vuad_ce_err_rdy;
3616wire [4:0] enc_tag_wr_wl_c4;
3617wire [4:0] enc_tag_wr_wl_c5;
3618wire [4:0] enc_tag_wr_wl_c52;
3619wire [4:0] enc_tag_wr_wl_c6;
3620wire [4:0] enc_tag_wr_wl_c7;
3621wire [4:0] enc_tag_wr_wl_c8;
3622
3623wire misbuf_inval_inst_c3; // int 5.0 changes
3624
3625/////////////////////////////////////////////////////////////////
3626//
3627// OFF mode exceptions in misbuf:
3628//
3629// 1) In the L2 off mode, a mbf dependent is readied on a
3630// fill buffer hit unless, the fill buffer entry has fb_stinst=1
3631// or the instruction hitting the FIll Buffer is a CAS1
3632//
3633// 2) Eviction pass is turned off by preventing the setting of
3634// the EVICT bit. Remember to not turn off the mcu request.
3635// ( Look at the expression for misbuf_evict_c7 )
3636//
3637/////////////////////////////////////////////////////////////////
3638
3639
3640///////////////////////////////////////////////////////////////////
3641 // Reset flop
3642 ///////////////////////////////////////////////////////////////////
3643
3644l2t_misbuf_ctl_msff_ctl_macro__width_1 reset_flop
3645 (.dout(dbb_rst_l),
3646 .scan_in(reset_flop_scanin),
3647 .scan_out(reset_flop_scanout),
3648 .l1clk(l1clk),
3649 .din(wmr_l),
3650 .siclk(siclk),
3651 .soclk(soclk)
3652
3653);
3654
3655
3656
3657/////////////////////////////////////////////////////////////////
3658// An RDMA instruction that is not a PST will not access the
3659// $ or the FB if the rdma reg vld is asserted.
3660//
3661// This signal is used for gating off completions becuase of
3662// FB hits.
3663/////////////////////////////////////////////////////////////////
3664
3665assign misbuf_rdma_gate_off_c2 = ( tag_misbuf_rdma_reg_vld_c2
3666 //~arb_arbdp_misbuf_pst_no_ctrue_c2 not needed since we use this for completions only
3667 & rdma_inst_c2 );
3668
3669
3670///////////////////////////////////////////////////////////////////////////
3671// MISS BUFFER INSERTION : An entry is inserted into the Miss Buffer under
3672// the following conditions
3673// * Valid instruction has to be a non Miss Buffer
3674// instruction AND
3675// * An L2 tag miss with the following exceptions
3676// - Tecc instruction
3677// - diagnostic instruction
3678// - interrupt instruction.
3679// - inval instruction.
3680// - cas2 instruction.
3681// - wr64 instruction not hitting the fill Buffer
3682// * A Pst with no ctrue ( INcludes LDSTUB/SWAPS)
3683// * An rdma instrution that encounters rdma_reg_vld.
3684// * A CAS2 instruction
3685// * Miss Buffer hit.
3686// * WB or RDMAt hit.
3687// * CSR store.
3688// **** A non Allocating instruction that encounters a Parity error.
3689//
3690// MISS BUFFER DELETION : An entry is deleted from the Miss Buffer if
3691// * It is issued from the Miss Buffer
3692// AND
3693// * a non-partial store $ or FB hit.
3694// * Pst with ctrue $ or FB hit.
3695// * CSR store from the Miss Buffer.
3696//
3697// MISS BUFFER INSERTION PIPELINE:
3698//---------------------------------------------------------------------
3699// C1 C2 C3 C4
3700//---------------------------------------------------------------------
3701// Cam generate write valid=1
3702// mbf wr ptr mbf tag
3703// mb_count[4:0]
3704// mb_count>5
3705// mb_count>12
3706// insertion
3707// condition
3708// counter
3709// logic
3710//---------------------------------------------------------------------
3711// TIMING tag_miss_unqual_c2 is the most critical condition for insertion.
3712// It takes ~17 gates to arrive at misbuf.
3713// If parity has to be factored into the insertion equation, it would have
3714// to be Ored in C3.
3715//
3716//
3717//////////////////////////////////////////////////////////////////////////
3718
3719//
3720// for timing reasons filbuf_tag_hit_frm_mb_c2 is brought in directly and qualified.
3721//
3722
3723assign arb_vuad_ce_err_c2_qual = (usaloc_ua_ce_c2 | vlddir_vd_ce_c2) &
3724 (arb_vuad_ce_err_c2 & ~filbuf_tag_hit_frm_mb_c2);
3725
3726
3727l2t_misbuf_ctl_msff_ctl_macro__width_20 ff_l2t_mbist_r1
3728 (
3729 .scan_in(ff_l2t_mbist_r1_scanin),
3730 .scan_out(ff_l2t_mbist_r1_scanout),
3731 .din({l2t_mb2_mbdata_wr_en,l2t_mb2_mbdata_wr_en_r1,mbtag_mbist_cam_sel,
3732 l2t_mb2_run,l2t_mb2_mbtag_rd_en,l2t_mb2_mbtag_rd_en_r1,
3733 l2t_mb2_mbtag_wr_en,l2t_mb2_mbtag_wr_en_r1,l2t_mb2_mbdata_rd_en,
3734 l2t_mb2_mbdata_rd_en_r1,l2t_mb2_addr[4:0],l2t_mb2_addr_r1[4:0]}),
3735 .l1clk(l1clk),
3736 .dout({l2t_mb2_mbdata_wr_en_r1,l2t_mb2_mbdata_wr_en_r2,mbtag_mbist_cam_sel_r1,
3737 l2t_mb2_run_r1,l2t_mb2_mbtag_rd_en_r1,l2t_mb2_mbtag_rd_en_r2,
3738 l2t_mb2_mbtag_wr_en_r1,l2t_mb2_mbtag_wr_en_r2,l2t_mb2_mbdata_rd_en_r1,
3739 l2t_mb2_mbdata_rd_en_r2,l2t_mb2_addr_r1[4:0],l2t_mb2_addr_r2[4:0]}),
3740 .siclk(siclk),
3741 .soclk(soclk)
3742 );
3743
3744//assign misbuf_vuad_ce_err_log_c2 = (usaloc_ua_ce_c2 | vlddir_vd_ce_c2) & arb_vuad_ce_err_c2;
3745assign misbuf_vuad_ce_err_log_c2 = (usaloc_ua_ce_c2 | vlddir_vd_ce_c2)
3746 & (arb_vuad_ce_err_c2 & ~filbuf_tag_hit_frm_mb_c2);
3747
3748
3749l2t_misbuf_ctl_msff_ctl_macro__width_7 ff_loggingerr
3750 (
3751 .scan_in(ff_loggingerr_scanin),
3752 .scan_out(ff_loggingerr_scanout),
3753 .din({misbuf_vuad_ce_err_log_c2,misbuf_vuad_ce_err_log_c3,
3754 misbuf_vuad_ce_err_log_c4,misbuf_vuad_ce_err_log_c5,
3755 misbuf_vuad_ce_err_log_c52, misbuf_vuad_ce_err_log_c6,
3756 misbuf_vuad_ce_err_log_c7}),
3757 .l1clk(l1clk),
3758 .dout({misbuf_vuad_ce_err_log_c3,misbuf_vuad_ce_err_log_c4,
3759 misbuf_vuad_ce_err_log_c5, misbuf_vuad_ce_err_log_c52,
3760 misbuf_vuad_ce_err_log_c6, misbuf_vuad_ce_err_log_c7,
3761 misbuf_vuad_ce_err_c8}),
3762 .siclk(siclk),
3763 .soclk(soclk)
3764 );
3765
3766assign misbuf_mbtag_wr_en_c2 = l2t_mb2_run_r1 ? l2t_mb2_mbtag_wr_en_r2 :
3767 (~arbdec_arbdp_inst_mb_c2 & arb_misbuf_inst_vld_c2) ;
3768
3769assign mbf_insert_c2 = (((arb_arbdp_misbuf_pst_no_ctrue_c2 | // pst no ctrue
3770 arb_decdp_cas2_inst_c2 | // cas2
3771 arb_csr_st_c2 ) | // csr store c2
3772 wbuf_hit_unqual_c2 | // wb tag match
3773 rdmat_hit_unqual_c2 | // rdma tag match
3774 misbuf_rdma_gate_off_c2 ) & // rdma reg vld.
3775 misbuf_mbtag_wr_en_c2 ) |
3776 misbuf_hit_c2 | // dependent insertion.
3777 (arb_pf_ice_inst_c2 & arb_inst_vld_c2 & ~arbdec_arbdp_inst_mb_c2) | // prefetch ICE first pass
3778 (arb_vuad_ce_err_c2_qual & ~arbdec_arbdp_inst_mb_c2) |
3779 ( tag_miss_unqual_c2 &
3780 ~(arb_decdp_wr64_inst_c2 & ~filbuf_misbuf_match_c2) & // not an RDMA 64B write that misses FB
3781 misbuf_mbtag_wr_en_c2 );
3782
3783// fix for bug 116974
3784
3785assign vuad_err_true_c2 = (usaloc_ua_ce_c2 | vlddir_vd_ce_c2);
3786
3787// Parity error insertion is turned off for a tag hit
3788l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_tag_hit_unqual_c3
3789 (.din(tag_hit_unqual_c2), .l1clk(l1clk),
3790 .scan_in(ff_tag_hit_unqual_c3_scanin),
3791 .scan_out(ff_tag_hit_unqual_c3_scanout),
3792 .dout(tag_hit_unqual_c3),
3793 .siclk(siclk),
3794 .soclk(soclk)
3795);
3796
3797//assign misbuf_tag_hit_unqual_c3 = tag_hit_unqual_c3 ;
3798
3799
3800
3801l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_insert_c3
3802 (.din(mbf_insert_c2), .l1clk(l1clk),
3803 .scan_in(ff_mbf_insert_c3_scanin),
3804 .scan_out(ff_mbf_insert_c3_scanout),
3805 .dout(mbf_insert_c3_tmp),
3806 .siclk(siclk),
3807 .soclk(soclk)
3808);
3809
3810l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_mbf_insert_c3_1
3811 (.din({2{mbf_insert_c2}}), .l1clk(l1clk),
3812 .scan_in(ff_mbf_insert_c3_1_scanin),
3813 .scan_out(ff_mbf_insert_c3_1_scanout),
3814 .dout({mbf_insert_c3_tmp_1_clone,mbf_insert_c3_tmp_1}),
3815 .siclk(siclk),
3816 .soclk(soclk)
3817);
3818
3819l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c3_1
3820 (.din(arbdec_arbdp_inst_mb_c2), .l1clk(l1clk),
3821 .scan_in(ff_inst_mb_c3_1_scanin),
3822 .scan_out(ff_inst_mb_c3_1_scanout),
3823 .dout(inst_mb_c3_1),
3824 .siclk(siclk),
3825 .soclk(soclk)
3826);
3827
3828l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_arb_vuad_ce_err_c3
3829 (
3830 .scan_in(ff_arb_vuad_ce_err_c3_scanin),
3831 .scan_out(ff_arb_vuad_ce_err_c3_scanout),
3832 .din(arb_vuad_ce_err_c2_qual),
3833 .l1clk(l1clk),
3834 .dout(arb_vuad_ce_err_c3),
3835 .siclk(siclk),
3836 .soclk(soclk)
3837 );
3838
3839
3840
3841
3842
3843
3844
3845
3846// Force insertion of instruction into MB in case of arb_vuad_ce_err_c3 = 1
3847// No need to gate arb_vuad_ce_err_c3 with inst_mb_c3_1 because
3848// CE can only be found on an instruction that is not issued from MB
3849// When the instruction gets written to MB, the error gets corrected
3850// in the same pass. So the replayed instruction can never find a CE.
3851//
3852//assign mbf_insert_c3 = mbf_insert_c3_tmp | ( ~inst_mb_c3_1 & // VUAD ecc change
3853// tag_misbuf_par_err_c3 &
3854// ~tag_hit_unqual_c3 ) | arb_vuad_ce_err_c3 ; // tecc insert is
3855// // the most critical
3856// // insertion condition.
3857//
3858
3859assign mbf_insert_c3 = mbf_insert_c3_tmp | ( ~inst_mb_c3_1 & // VUAD ecc change
3860 tag_misbuf_par_err_c3 & ~tag_hit_unqual_c3 ) | (~inst_mb_c3_1 & arb_vuad_ce_err_c3);
3861
3862
3863
3864assign mbf_delete_miss_c2 = ( ~arb_decdp_pst_inst_c2 | // non partial store inst
3865 arb_arbdp_pst_with_ctrue_c2 ) & // pst with ctrue
3866 mbissue_inst_vld_c2 &
3867 ( tag_hit_unqual_c2 |
3868 (filbuf_misbuf_match_c2 &
3869 ~misbuf_rdma_gate_off_c2 )) & ~arb_vuad_ce_err_c2_qual ;
3870// int 5.0 changes
3871//-----\/ FIX for bug #4619 --\/-----
3872// inval/csr instructions will get deleted from the miss buffer
3873// when they are issued out of there unless there is a vuad err for which the
3874// instruction will be replayed.
3875// Prefetch ICE and wr64 get deleted unless there is a vuad ce or tag parity
3876// Error, or a tecc instruction , for which they get replayed.
3877//-----\/ FIX for bug #4619 --\/-----
3878
3879
3880assign mbf_delete_c2 = (( arb_csr_st_c2 | arb_misbuf_inval_inst_c2 )
3881 // delete a miss after it hits $ or FB
3882 & mbissue_inst_vld_c2 & ~arb_vuad_ce_err_c2_qual ) | mbf_delete_miss_c2 ;
3883
3884
3885l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_delete_c3
3886 (.din(mbf_delete_c2), .l1clk(l1clk),
3887 .scan_in(ff_mbf_delete_c3_scanin),
3888 .scan_out(ff_mbf_delete_c3_scanout),
3889 .dout(mbf_delete_c3_tmp),
3890 .siclk(siclk),
3891 .soclk(soclk)
3892);
3893
3894l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_mbf_delete_c3_1
3895 (.din({2{mbf_delete_c2}}), .l1clk(l1clk),
3896 .scan_in(ff_mbf_delete_c3_1_scanin),
3897 .scan_out(ff_mbf_delete_c3_1_scanout),
3898 .dout({mbf_delete_c3_tmp_1,mbf_delete_c3_tmp_1_clone}),
3899 .siclk(siclk),
3900 .soclk(soclk)
3901);
3902
3903assign mbf_delete_c3 = ( inst_mb_c3 & misbuf_wr64_miss_comp_c3 & ~tag_misbuf_par_err_c3 & ~arb_vuad_ce_err_c3)
3904 | (mbissue_inst_vld_c3 & arb_pf_ice_inst_c3 & ~evict_tecc_vld_c3 & ~arb_vuad_ce_err_c3 & ~tag_misbuf_par_err_c3)
3905 | mbf_delete_c3_tmp ; // int 5.0 changes
3906
3907
3908///////////////////////////////////////////////////////////////////////
3909// misbuf_nondep_fbhit_c3: This signal indicates an FB tag match
3910// for an instruction that is not a miss buffer dependent.
3911//
3912// A store instruction issued from the Xbar that misses the Miss Buffer
3913// but hits the Fill Buffer should CAM the directory and invalidate
3914// the L1s that share the line.
3915// If we simply look at tag_hitl2orfb_c3, we will miss the above
3916// case.
3917//
3918// However, for all tag miss cases encountering a parity error, the
3919// store is inserted into the Miss Buffer and replayed for sending an ACK
3920//
3921// misbuf_nondep_fbhit_c3 should be low when a tag parity error occurs.
3922// This is because we don't want to CAM the directory for the case when
3923// a tag miss but a fb hit is encountered for a non miss buffer instruction.
3924///////////////////////////////////////////////////////////////////////
3925
3926
3927assign nondep_fbhit_c2_unqual = filbuf_misbuf_match_c2 &
3928 ~misbuf_tag_hit_unqual_c2_internal ;
3929// int 5.0 change
3930//msff_ctl_macro ff_misbuf_nondep_fbhit_c3 (width=1)
3931// (.din(nondep_fbhit_c2_unqual), .l1clk(l1clk),
3932// .dout(nondep_fbhit_c3_unqual),
3933// .scan_in(),
3934// .scan_out()
3935//);
3936//
3937//assign misbuf_nondep_fbhit_c3 = nondep_fbhit_c3_unqual &
3938// ~tag_misbuf_par_err_c3 &
3939// mb_inst_vld_c3 ;
3940// -------------\/ FIX for int_5.0 \/-------------------------------
3941// mbctl_nondep_fbhit_c3 is no longer qualfied with mb_inst_vld_c3
3942// or tag_misbuf_par_err_c3 since it is a critical signal.
3943// -----------------------------------------------------------------
3944
3945l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbctl_nondep_fbhit_c3
3946 (
3947 .scan_in(ff_mbctl_nondep_fbhit_c3_scanin),
3948 .scan_out(ff_mbctl_nondep_fbhit_c3_scanout),
3949 .din(nondep_fbhit_c2_unqual),
3950 .dout(misbuf_nondep_fbhit_c3),
3951 .l1clk(l1clk),
3952 .siclk(siclk),
3953 .soclk(soclk)
3954
3955
3956
3957 );
3958
3959
3960//////////////////////////////////////////////////////////////////////////////
3961// mbf Insertion pointer.
3962// The Insertion pointer is determined in C2 based on the
3963// valid bit written by the C4 instruction. One cycle of
3964// forwarding is required to prevent overwriting a valid
3965// entry as shown in the following pipeline.
3966//-----------------------------------------------------
3967// C2 C3 C4
3968//-----------------------------------------------------
3969// calc. write valid=1
3970// wr ptr.
3971//-----------------------------------------------------
3972// C2 C3
3973//-----------------------------------------------------
3974// calc
3975// wr ptr.
3976//
3977// Timing optimization: The wr ptr in C2 can assume that the
3978// operation in C3 is going to insert. This will not affect the
3979// insertion of the C2 op even if the assumption turns out to
3980// be incorrect.
3981/////////////////////////////////////////////////////////////////////////////////
3982
3983
3984
3985
3986
3987assign mb_valid_ifin = ( mb_valid | (mb_write_ptr_c3 &
3988 {32{mb_inst_vld_c3_1}} )); // BS & SR 11/04/03, MB grows to 32
3989
3990assign mb_write_ptr_c2[0] = ~mb_valid_ifin[0];
3991assign mb_write_ptr_c2[1] = ~mb_valid_ifin[1] & (mb_valid_ifin[0]) ;
3992assign mb_write_ptr_c2[2] = ~mb_valid_ifin[2] & (&(mb_valid_ifin[1:0])) ;
3993assign mb_write_ptr_c2[3] = ~mb_valid_ifin[3] & (&(mb_valid_ifin[2:0])) ;
3994assign mb_write_ptr_c2[4] = ~mb_valid_ifin[4] & (&(mb_valid_ifin[3:0])) ;
3995assign mb_write_ptr_c2[5] = ~mb_valid_ifin[5] & (&(mb_valid_ifin[4:0])) ;
3996assign mb_write_ptr_c2[6] = ~mb_valid_ifin[6] & (&(mb_valid_ifin[5:0])) ;
3997assign mb_write_ptr_c2[7] = ~mb_valid_ifin[7] & (&(mb_valid_ifin[6:0])) ;
3998assign mb_write_ptr_c2[8] = ~mb_valid_ifin[8] & (&(mb_valid_ifin[7:0])) ;
3999assign mb_write_ptr_c2[9] = ~mb_valid_ifin[9] & (&(mb_valid_ifin[8:0])) ;
4000assign mb_write_ptr_c2[10] = ~mb_valid_ifin[10] & (&(mb_valid_ifin[9:0])) ;
4001assign mb_write_ptr_c2[11] = ~mb_valid_ifin[11] & (&(mb_valid_ifin[10:0])) ;
4002assign mb_write_ptr_c2[12] = ~mb_valid_ifin[12] & (&(mb_valid_ifin[11:0])) ;
4003assign mb_write_ptr_c2[13] = ~mb_valid_ifin[13] & (&(mb_valid_ifin[12:0])) ;
4004assign mb_write_ptr_c2[14] = ~mb_valid_ifin[14] & (&(mb_valid_ifin[13:0])) ;
4005assign mb_write_ptr_c2[15] = ~mb_valid_ifin[15] & (&(mb_valid_ifin[14:0])) ;
4006// BS & SR 11/04/03, MB grows to 32
4007assign mb_write_ptr_c2[16] = ~mb_valid_ifin[16] & (&(mb_valid_ifin[15:0])) ;
4008assign mb_write_ptr_c2[17] = ~mb_valid_ifin[17] & (&(mb_valid_ifin[16:0])) ;
4009assign mb_write_ptr_c2[18] = ~mb_valid_ifin[18] & (&(mb_valid_ifin[17:0])) ;
4010assign mb_write_ptr_c2[19] = ~mb_valid_ifin[19] & (&(mb_valid_ifin[18:0])) ;
4011assign mb_write_ptr_c2[20] = ~mb_valid_ifin[20] & (&(mb_valid_ifin[19:0])) ;
4012assign mb_write_ptr_c2[21] = ~mb_valid_ifin[21] & (&(mb_valid_ifin[20:0])) ;
4013assign mb_write_ptr_c2[22] = ~mb_valid_ifin[22] & (&(mb_valid_ifin[21:0])) ;
4014assign mb_write_ptr_c2[23] = ~mb_valid_ifin[23] & (&(mb_valid_ifin[22:0])) ;
4015assign mb_write_ptr_c2[24] = ~mb_valid_ifin[24] & (&(mb_valid_ifin[23:0])) ;
4016assign mb_write_ptr_c2[25] = ~mb_valid_ifin[25] & (&(mb_valid_ifin[24:0])) ;
4017assign mb_write_ptr_c2[26] = ~mb_valid_ifin[26] & (&(mb_valid_ifin[25:0])) ;
4018assign mb_write_ptr_c2[27] = ~mb_valid_ifin[27] & (&(mb_valid_ifin[26:0])) ;
4019assign mb_write_ptr_c2[28] = ~mb_valid_ifin[28] & (&(mb_valid_ifin[27:0])) ;
4020assign mb_write_ptr_c2[29] = ~mb_valid_ifin[29] & (&(mb_valid_ifin[28:0])) ;
4021assign mb_write_ptr_c2[30] = ~mb_valid_ifin[30] & (&(mb_valid_ifin[29:0])) ;
4022assign mb_write_ptr_c2[31] = ~mb_valid_ifin[31] & (&(mb_valid_ifin[30:0])) ;
4023
4024
4025assign mbtag_write_ptr[0] = (l2t_mb2_addr_r2[4:0]==5'd0);
4026assign mbtag_write_ptr[1] = (l2t_mb2_addr_r2[4:0]==5'd1);
4027assign mbtag_write_ptr[2] = (l2t_mb2_addr_r2[4:0]==5'd2);
4028assign mbtag_write_ptr[3] = (l2t_mb2_addr_r2[4:0]==5'd3);
4029assign mbtag_write_ptr[4] = (l2t_mb2_addr_r2[4:0]==5'd4);
4030assign mbtag_write_ptr[5] = (l2t_mb2_addr_r2[4:0]==5'd5);
4031assign mbtag_write_ptr[6] = (l2t_mb2_addr_r2[4:0]==5'd6);
4032assign mbtag_write_ptr[7] = (l2t_mb2_addr_r2[4:0]==5'd7);
4033assign mbtag_write_ptr[8] = (l2t_mb2_addr_r2[4:0]==5'd8);
4034assign mbtag_write_ptr[9] = (l2t_mb2_addr_r2[4:0]==5'd9);
4035assign mbtag_write_ptr[10] = (l2t_mb2_addr_r2[4:0]==5'd10);
4036assign mbtag_write_ptr[11] = (l2t_mb2_addr_r2[4:0]==5'd11);
4037assign mbtag_write_ptr[12] = (l2t_mb2_addr_r2[4:0]==5'd12);
4038assign mbtag_write_ptr[13] = (l2t_mb2_addr_r2[4:0]==5'd13);
4039assign mbtag_write_ptr[14] = (l2t_mb2_addr_r2[4:0]==5'd14);
4040assign mbtag_write_ptr[15] = (l2t_mb2_addr_r2[4:0]==5'd15);
4041assign mbtag_write_ptr[16] = (l2t_mb2_addr_r2[4:0]==5'd16);
4042assign mbtag_write_ptr[17] = (l2t_mb2_addr_r2[4:0]==5'd17);
4043assign mbtag_write_ptr[18] = (l2t_mb2_addr_r2[4:0]==5'd18);
4044assign mbtag_write_ptr[19] = (l2t_mb2_addr_r2[4:0]==5'd19);
4045assign mbtag_write_ptr[20] = (l2t_mb2_addr_r2[4:0]==5'd20);
4046assign mbtag_write_ptr[21] = (l2t_mb2_addr_r2[4:0]==5'd21);
4047assign mbtag_write_ptr[22] = (l2t_mb2_addr_r2[4:0]==5'd22);
4048assign mbtag_write_ptr[23] = (l2t_mb2_addr_r2[4:0]==5'd23);
4049assign mbtag_write_ptr[24] = (l2t_mb2_addr_r2[4:0]==5'd24);
4050assign mbtag_write_ptr[25] = (l2t_mb2_addr_r2[4:0]==5'd25);
4051assign mbtag_write_ptr[26] = (l2t_mb2_addr_r2[4:0]==5'd26);
4052assign mbtag_write_ptr[27] = (l2t_mb2_addr_r2[4:0]==5'd27);
4053assign mbtag_write_ptr[28] = (l2t_mb2_addr_r2[4:0]==5'd28);
4054assign mbtag_write_ptr[29] = (l2t_mb2_addr_r2[4:0]==5'd29);
4055assign mbtag_write_ptr[30] = (l2t_mb2_addr_r2[4:0]==5'd30);
4056assign mbtag_write_ptr[31] = (l2t_mb2_addr_r2[4:0]==5'd31);
4057
4058
4059assign misbuf_mb_write_wl = l2t_mb2_run_r1 ? mbtag_write_ptr : mb_write_ptr_c2 ; // wordline for mbtag write
4060
4061
4062
4063
4064
4065//////////////////////////////////////////////////////////////
4066// Generate 2 signals :
4067// mb_count,
4068// misbuf_arb_cnt28_px2 count >= 28
4069//
4070// The cnt12 condition is calculated in C3 and staged to C4.
4071// The inflight instructions that need to be accounted for are
4072// PX2*, C1, C2 C3,
4073//
4074// ( The PX2 instruction is not stalled if it is the 2nd packet
4075// of a CAS instruction and if the first one has gone through.)
4076// Hence the high water mark is asserted when there are 12 or
4077// more instructions in the Miss Buffer.
4078//
4079// Timing notes:
4080// The mb_cnt28_px2_prev is calculated in the C3 stage
4081// every "valid" C3 op is presumed to insert if it is not issued
4082// from the Miss Buffer. If this is the case, the Miss Buffer will
4083// have to accomodate the ops in C2, C1, PX2 and PX1. Hence this
4084// signal is asserted when the miss buffer counter is at 11
4085// and the C3 op is not from the miss buffer. OR
4086// if the miss buffer counter > 11
4087//
4088//////////////////////////////////////////////////////////////
4089
4090assign cnt_reset = ( ~dbb_rst_l ) ;
4091
4092// insertion and deletion cannot happen at the same time.
4093assign mb_count_en = ( mbf_insert_c3 | mbf_delete_c3 ) ;
4094
4095
4096assign mb_count_plus1 = mb_count_c4+ 6'b1 ; // BS & SR 11/04/03, MB grows to 32
4097assign mb_count_minus1 = mb_count_c4- 6'b1 ; // BS & SR 11/04/03, MB grows to 32
4098
4099l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 mux_mbf_count // BS & SR 11/04/03, MB grows to 32
4100 (.dout (mb_count_prev[5:0]),
4101 .din0(mb_count_plus1[5:0]), .din1(mb_count_minus1[5:0]),
4102 .sel0(mbf_insert_c3), .sel1(~mbf_insert_c3));
4103
4104l2t_misbuf_ctl_msff_ctl_macro__clr_1__en_1__width_6 ff_mb_count_c4 // sync reset active high // BS & SR 11/04/03, MB grows to 32
4105 (.din(mb_count_prev[5:0]),
4106 .scan_in(ff_mb_count_c4_scanin),
4107 .scan_out(ff_mb_count_c4_scanout),
4108 .en(mb_count_en), .l1clk(l1clk), .clr(cnt_reset),
4109 .dout(mb_count_c4[5:0]),
4110 .siclk(siclk),
4111 .soclk(soclk)
4112);
4113
4114assign misbuf_arb_cnt28_px2_prev = // BS & SR 11/04/03, MB grows to 32
4115 mb_idx_count_full_c4 | // indicates 11 or more entries with
4116 // the same index in the mIss buffer.
4117 (( mb_count_c4== 6'd27 )
4118 & mb_inst_vld_c3 & ~inst_mb_c3 ) | // assume that
4119 ( mb_count_c4 > 6'd27 ) ;
4120
4121
4122////FIXME synopsys translate_off FIXME fix sunv
4123//always @(mb_count_c4 ) begin // BS & SR 11/04/03, MB grows to 32
4124// if( mb_count_c4 > 6'd32 ) begin
4125// $error("MB_COUNT", "illegal mb insertion with mb_count 33");
4126// end
4127// else begin end // do nothing, int 5.0 changes
4128//end
4129////FIXME synopsys translate_on FIXME fix sunv
4130
4131
4132
4133l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_inst_c2
4134 (.din(arbdec_arbdp_rdma_inst_c1), .l1clk(l1clk),
4135 .scan_in(ff_rdma_inst_c2_scanin),
4136 .scan_out(ff_rdma_inst_c2_scanout),
4137 .dout(rdma_inst_c2),
4138 .siclk(siclk),
4139 .soclk(soclk)
4140);
4141
4142l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_inst_c3
4143 (.din(rdma_inst_c2), .l1clk(l1clk),
4144 .scan_in(ff_rdma_inst_c3_scanin),
4145 .scan_out(ff_rdma_inst_c3_scanout),
4146 .dout(rdma_inst_c3),
4147 .siclk(siclk),
4148 .soclk(soclk)
4149);
4150
4151
4152//////////////////////////////////////////////////////////////////////
4153// PREVENTION of LIVELOCK
4154// RDMA instructions in the Miss Buffer have a high water mark of
4155// 8 for the following reason.
4156// When the interface to the siu frees up, an instruction from the
4157// snoop/siu interface will have a higher priority to issue than
4158// the miss Buffer. It is possible to construct a livelock case
4159// where, entries from the snpq always get selected over older
4160// miss buffer snoops. If the miss Buffer is filled with snoops,
4161// it will cause the pipeline to be completely hogged by snoops.
4162//
4163// To prevent this livelock, we maintain a snoop instruction counter
4164// in the Miss Buffer. Whenever this counter reaches 8. it disallows
4165// any instruction from the snoop Q from issuing to the pipeline until
4166// the counter value drops below 8.
4167//////////////////////////////////////////////////////////////////////
4168
4169assign mb_rdma_count_en = ( mbf_insert_c3 | mbf_delete_c3 ) & rdma_inst_c3 ;
4170assign mb_rdma_count_plus1 = mb_rdma_count_c4+ 4'b1 ;
4171assign mb_rdma_count_minus1 = mb_rdma_count_c4- 4'b1 ;
4172
4173assign inc_rdma_cnt_c3 = mbf_insert_c3 & rdma_inst_c3;
4174
4175
4176l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_mbf_rdma_count
4177 (.dout (mb_rdma_count_prev[3:0]),
4178 .din0(mb_rdma_count_plus1[3:0]),
4179 .din1(mb_rdma_count_minus1[3:0]),
4180 .sel0(inc_rdma_cnt_c3),
4181 .sel1(~inc_rdma_cnt_c3));
4182
4183l2t_misbuf_ctl_msff_ctl_macro__clr_1__en_1__width_4 ff_mb_rdma_count_c4 // sync reset active high
4184 (.din(mb_rdma_count_prev[3:0]),
4185 .scan_in(ff_mb_rdma_count_c4_scanin),
4186 .scan_out(ff_mb_rdma_count_c4_scanout),
4187 .en(mb_rdma_count_en), .l1clk(l1clk), .clr(cnt_reset),
4188 .dout(mb_rdma_count_c4[3:0]),
4189 .siclk(siclk),
4190 .soclk(soclk)
4191);
4192
4193assign misbuf_arb_snp_cnt8_px1 = ( mb_rdma_count_c4 >= 4'd8 );
4194
4195//////////////////////////////////////////////////////////////
4196//MB_CAM_EN logic in arb.
4197// mbcam is asserted for the following conditions
4198// * PX2 instruction from the IQ is valid
4199// * PX2 instruction from the snoop Q is valid.
4200// * C1 instruction is stalled
4201// In case 1 and 2 it is possible that the instruction never got issued
4202// because of a mbf full condition or a copyback Q full condition.
4203// However, the miss buffer cam is still asserted speculatively for
4204// timing reasons.
4205//
4206// The Hit vector generated by the cam operation is appropriately
4207// qualified in misbuf to gate off any false hits due to speculative
4208// camming.
4209////////////////////////////////////////////////////////////////////////
4210
4211///////////////////////////////////////////////////////////////////////////////
4212// CAM hit generation: This operation requires forwarding due to
4213// the offset between insertion and CAMMING.
4214//-----------------------------------------------------------------------------
4215// op A C1(cam) C2 C3(enqueue/dequeue) C4(valid=1/0)
4216// op B C1 C2 C3
4217// op C C1 C2
4218// op D C1
4219//-----------------------------------------------------------------------------
4220// The earliest operation that can see the effects of OP A is OP D.
4221// If we want OP B and OP C to see the effects of OP A, we need to forward
4222// that information while generating mb Hit.
4223//
4224// forwarding all the information from a C2 op to a C1 op presents
4225// a timing problem. Performing the bypassing in C2 will cause misbuf_hit_c2 to be
4226// the critical component of the hit_way_vld_c2 signal. One way of solving these
4227// two problems is to decouple hit_vec_c2 and misbuf_hit_c2 logic cones.
4228//
4229//
4230// Bypass Logic for hit_vec and hit in C1 and C2.
4231//
4232// C1:
4233// - Bypass all information from C3 to the C1 operation.
4234// - If the C2 operation is from the Miss Buffer, turn off hit for the
4235// entry of the C2 operation.
4236//
4237// C2:
4238// - If C3 operation inserts, use address match and entry to OR with the result
4239// from C1.
4240// - If C3 operation from the miss buffer, does not delete, use address match
4241// and entry to OR with the result from C1.
4242//
4243////////////////////////////////////////////////////////////////////////////////
4244
4245l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_inst_mb_entry_c2
4246 (.din(arbdec_arbdp_inst_mb_entry_c1[4:0]), .l1clk(l1clk),
4247 .scan_in(ff_inst_mb_entry_c2_scanin),
4248 .scan_out(ff_inst_mb_entry_c2_scanout),
4249 .dout(inst_mb_entry_c2[4:0]),
4250 .siclk(siclk),
4251 .soclk(soclk)
4252);
4253
4254assign dec_mb_entry_c2[0] = ( inst_mb_entry_c2 == 5'd0 ) ;
4255assign dec_mb_entry_c2[1] = ( inst_mb_entry_c2 == 5'd1 ) ;
4256assign dec_mb_entry_c2[2] = ( inst_mb_entry_c2 == 5'd2 ) ;
4257assign dec_mb_entry_c2[3] = ( inst_mb_entry_c2 == 5'd3 ) ;
4258assign dec_mb_entry_c2[4] = ( inst_mb_entry_c2 == 5'd4 ) ;
4259assign dec_mb_entry_c2[5] = ( inst_mb_entry_c2 == 5'd5 ) ;
4260assign dec_mb_entry_c2[6] = ( inst_mb_entry_c2 == 5'd6 ) ;
4261assign dec_mb_entry_c2[7] = ( inst_mb_entry_c2 == 5'd7 ) ;
4262assign dec_mb_entry_c2[8] = ( inst_mb_entry_c2 == 5'd8 ) ;
4263assign dec_mb_entry_c2[9] = ( inst_mb_entry_c2 == 5'd9 ) ;
4264assign dec_mb_entry_c2[10] = ( inst_mb_entry_c2 == 5'd10 ) ;
4265assign dec_mb_entry_c2[11] = ( inst_mb_entry_c2 == 5'd11 ) ;
4266assign dec_mb_entry_c2[12] = ( inst_mb_entry_c2 == 5'd12 ) ;
4267assign dec_mb_entry_c2[13] = ( inst_mb_entry_c2 == 5'd13 ) ;
4268assign dec_mb_entry_c2[14] = ( inst_mb_entry_c2 == 5'd14 ) ;
4269assign dec_mb_entry_c2[15] = ( inst_mb_entry_c2 == 5'd15 ) ;
4270assign dec_mb_entry_c2[16] = ( inst_mb_entry_c2 == 5'd16 ) ; // BS & SR 11/04/03, MB grows to 32
4271assign dec_mb_entry_c2[17] = ( inst_mb_entry_c2 == 5'd17 ) ;
4272assign dec_mb_entry_c2[18] = ( inst_mb_entry_c2 == 5'd18 ) ;
4273assign dec_mb_entry_c2[19] = ( inst_mb_entry_c2 == 5'd19 ) ;
4274assign dec_mb_entry_c2[20] = ( inst_mb_entry_c2 == 5'd20 ) ;
4275assign dec_mb_entry_c2[21] = ( inst_mb_entry_c2 == 5'd21 ) ;
4276assign dec_mb_entry_c2[22] = ( inst_mb_entry_c2 == 5'd22 ) ;
4277assign dec_mb_entry_c2[23] = ( inst_mb_entry_c2 == 5'd23 ) ;
4278assign dec_mb_entry_c2[24] = ( inst_mb_entry_c2 == 5'd24 ) ;
4279assign dec_mb_entry_c2[25] = ( inst_mb_entry_c2 == 5'd25 ) ;
4280assign dec_mb_entry_c2[26] = ( inst_mb_entry_c2 == 5'd26 ) ;
4281assign dec_mb_entry_c2[27] = ( inst_mb_entry_c2 == 5'd27 ) ;
4282assign dec_mb_entry_c2[28] = ( inst_mb_entry_c2 == 5'd28 ) ;
4283assign dec_mb_entry_c2[29] = ( inst_mb_entry_c2 == 5'd29 ) ;
4284assign dec_mb_entry_c2[30] = ( inst_mb_entry_c2 == 5'd30 ) ;
4285assign dec_mb_entry_c2[31] = ( inst_mb_entry_c2 == 5'd31 ) ;
4286
4287
4288//// mbist//////
4289
4290
4291l2t_misbuf_ctl_msff_ctl_macro__width_33 ff_mb_mbist_cam_match
4292 (.din({mb_mbist_cam_hit_unreg,mb_cam_match[31:0]}), .l1clk(l1clk),
4293 .scan_in(ff_mb_mbist_cam_match_scanin),
4294 .scan_out(ff_mb_mbist_cam_match_scanout),
4295 .dout({mb_mbist_cam_hit,mb_cam_match_reg[31:0]}),
4296 .siclk(siclk),
4297 .soclk(soclk)
4298);
4299
4300
4301assign mb_mbist_cam_hit_unreg = mbtag_mbist_cam_sel_r1 ? |(mb_cam_match_reg[31:0]) : 1'b0;
4302
4303
4304
4305
4306
4307/////////////////////////
4308// HIt vector generation
4309/////////////////////////
4310
4311l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_l2_dir_map_on_d1
4312 (.din(csr_l2_dir_map_on), .l1clk(l1clk),
4313 .scan_in(ff_l2_dir_map_on_d1_scanin),
4314 .scan_out(ff_l2_dir_map_on_d1_scanout),
4315 .dout(l2_dir_map_on_d1),
4316 .siclk(siclk),
4317 .soclk(soclk)
4318);
4319
4320
4321
4322
4323// miss buffer cam match
4324assign mb_cam_hit_vec_c1 = ( mb_cam_match_idx & // BS & SR 11/04/03, MB grows to 32
4325 {32{(l2_dir_map_on_d1 & ~arbdec_pf_ice_inst_c1)}} ) |
4326 // dont look at mb_cam_match_idx for prefetch ICE in dmap mode
4327 // fix for bug 103065
4328 mb_cam_match ;
4329
4330// C1-C3 addr match.
4331assign misbuf_c1c3_match_c1 = ( arbadr_idx_c1c3comp_c1 &
4332 l2_dir_map_on_d1 & ~arbdec_pf_ice_inst_c1 ) |
4333 // dont look at mb_cam_match_idx for prefetch ICE in dmap mode
4334 arbadr_arbdp_addr_c1c3comp_c1 ;
4335
4336
4337// C1-c2 addr match.
4338assign misbuf_c1c2_match_c1 = ( arbadr_idx_c1c2comp_c1 &
4339 l2_dir_map_on_d1 & ~arbdec_pf_ice_inst_c1) |
4340 // dont look at mb_cam_match_idx for prefetch ICE in dmap mode
4341 arbadr_arbdp_addr_c1c2comp_c1 ;
4342
4343assign cam_hit_vec_c1 = ( mb_cam_hit_vec_c1 & mb_valid ); // addr or idx match
4344assign cam_idx_hit_vec_c1 = ( mb_cam_match_idx & mb_valid ); // idx match only
4345
4346// turn off hits for a C3 delete and a C2
4347// inst from the miss buffer ( speculating that it will cause
4348// a deletion ).
4349
4350assign mbissue_inst_vld_c2 = ( arbdec_arbdp_inst_mb_c2 &
4351 arb_misbuf_inst_vld_c2 ) ;
4352
4353assign hit_off_bypass_vec_c1 =
4354 ( dec_mb_entry_c3 & {32{mbf_delete_c3_tmp}} ) | // entry dequeued in C3 // BS & SR 11/04/03, MB grows to 32
4355 ( dec_mb_entry_c2 & {32{mbissue_inst_vld_c2}}) ; // entry from C2 if from mb
4356
4357// turn on hits for a insert in C3.
4358
4359assign hit_on_bypass_vec_c1 = ( {32{misbuf_c1c3_match_c1}} // not qualified with inst vlds.
4360 & mb_tag_wr_wl_c3_tmp ) ; // BS & SR 11/04/03, MB grows to 32
4361
4362assign idx_on_bypass_vec_c1 = ({32{arbadr_idx_c1c3comp_c1 }}
4363 & mb_tag_wr_wl_c3_tmp ) ; // BS & SR 11/04/03, MB grows to 32
4364
4365assign tmp_cam_hit_vec_c1 = ( cam_hit_vec_c1 |
4366 hit_on_bypass_vec_c1 ) &
4367 ~hit_off_bypass_vec_c1 ;
4368
4369assign tmp_idx_hit_vec_c1 = ( cam_idx_hit_vec_c1 |
4370 idx_on_bypass_vec_c1 ) &
4371 ~hit_off_bypass_vec_c1 ;
4372
4373
4374//assign tmp_cam_hit_c1_3to0 = |( tmp_cam_hit_vec_c1[3:0] ) ;
4375//assign tmp_cam_hit_c1_7to4 = |( tmp_cam_hit_vec_c1[7:4] ) ;
4376//assign tmp_cam_hit_c1_11to8 = |( tmp_cam_hit_vec_c1[11:8] ) ;
4377//assign tmp_cam_hit_c1_15to12 = |( tmp_cam_hit_vec_c1[15:12] ) ;
4378//// BS & SR 11/04/03, MB grows to 32
4379//assign tmp_cam_hit_c1_19to16 = |( tmp_cam_hit_vec_c1[19:16] ) ;
4380//assign tmp_cam_hit_c1_23to20 = |( tmp_cam_hit_vec_c1[23:20] ) ;
4381//assign tmp_cam_hit_c1_27to24 = |( tmp_cam_hit_vec_c1[27:24] ) ;
4382//assign tmp_cam_hit_c1_31to28 = |( tmp_cam_hit_vec_c1[31:28] ) ;
4383//
4384//
4385//msff_ctl_macro ff_tmp_cam_hit_c2_3to0 (width=1)
4386// (.din(tmp_cam_hit_c1_3to0),
4387// .scan_in(ff_tmp_cam_hit_c2_3to0_scanin),
4388// .scan_out(ff_tmp_cam_hit_c2_3to0_scanout),
4389// .l1clk(l1clk),
4390// .dout(tmp_cam_hit_c2_3to0),
4391//);
4392//
4393//msff_ctl_macro ff_tmp_cam_hit_c1_7to4 (width=1)
4394// (.din(tmp_cam_hit_c1_7to4),
4395// .scan_in(ff_tmp_cam_hit_c1_7to4_scanin),
4396// .scan_out(ff_tmp_cam_hit_c1_7to4_scanout),
4397// .l1clk(l1clk),
4398// .dout(tmp_cam_hit_c2_7to4),
4399//);
4400//
4401//msff_ctl_macro ff_tmp_cam_hit_c2_11to8 (width=1)
4402// (.din(tmp_cam_hit_c1_11to8),
4403// .scan_in(ff_tmp_cam_hit_c2_11to8_scanin),
4404// .scan_out(ff_tmp_cam_hit_c2_11to8_scanout),
4405// .l1clk(l1clk),
4406// .dout(tmp_cam_hit_c2_11to8),
4407//);
4408//
4409//msff_ctl_macro ff_tmp_cam_hit_c2_15to12 (width=1)
4410// (.din(tmp_cam_hit_c1_15to12),
4411// .scan_in(ff_tmp_cam_hit_c2_15to12_scanin),
4412// .scan_out(ff_tmp_cam_hit_c2_15to12_scanout),
4413// .l1clk(l1clk),
4414// .dout(tmp_cam_hit_c2_15to12),
4415//);
4416//
4417//// BS & SR 11/04/03, MB grows to 32
4418//msff_ctl_macro ff_tmp_cam_hit_c2_19to16 (width=1)
4419// (
4420// .scan_in(ff_tmp_cam_hit_c2_19to16_scanin),
4421// .scan_out(ff_tmp_cam_hit_c2_19to16_scanout),
4422// .din(tmp_cam_hit_c1_19to16),
4423// .l1clk(l1clk),
4424// .dout(tmp_cam_hit_c2_19to16),
4425//
4426//);
4427//
4428//msff_ctl_macro ff_tmp_cam_hit_c2_23to20 (width=1)
4429// (
4430// .scan_in(ff_tmp_cam_hit_c2_23to20_scanin),
4431// .scan_out(ff_tmp_cam_hit_c2_23to20_scanout),
4432// .din(tmp_cam_hit_c1_23to20),
4433// .l1clk(l1clk),
4434// .dout(tmp_cam_hit_c2_23to20),
4435//
4436//);
4437//
4438//msff_ctl_macro ff_tmp_cam_hit_c2_27to24 (width=1)
4439// (
4440// .scan_in(ff_tmp_cam_hit_c2_27to24_scanin),
4441// .scan_out(ff_tmp_cam_hit_c2_27to24_scanout),
4442// .din(tmp_cam_hit_c1_27to24),
4443// .l1clk(l1clk),
4444// .dout(tmp_cam_hit_c2_27to24),
4445//
4446//);
4447//
4448//
4449//msff_ctl_macro ff_tmp_cam_hit_c2_31to28 (width=1)
4450// (
4451// .scan_in(ff_tmp_cam_hit_c2_31to28_scanin),
4452// .scan_out(ff_tmp_cam_hit_c2_31to28_scanout),
4453// .din(tmp_cam_hit_c1_31to28),
4454// .l1clk(l1clk),
4455// .dout(tmp_cam_hit_c2_31to28),
4456//
4457//);
4458
4459
4460l2t_misbuf_ctl_msff_ctl_macro__width_32 ff_tmp_cam_hit_vec_c2 // BS & SR 11/04/03, MB grows to 32
4461 (.din(tmp_cam_hit_vec_c1[31:0]),
4462 .scan_in(ff_tmp_cam_hit_vec_c2_scanin),
4463 .scan_out(ff_tmp_cam_hit_vec_c2_scanout),
4464 .l1clk(l1clk),
4465 .dout(tmp_cam_hit_vec_c2[31:0]),
4466 .siclk(siclk),
4467 .soclk(soclk)
4468
4469);
4470
4471l2t_misbuf_ctl_msff_ctl_macro__width_32 ff_tmp_idx_hit_vec_c2 // BS & SR 11/04/03, MB grows to 32
4472 (.din(tmp_idx_hit_vec_c1[31:0]),
4473 .scan_in(ff_tmp_idx_hit_vec_c2_scanin),
4474 .scan_out(ff_tmp_idx_hit_vec_c2_scanout),
4475 .l1clk(l1clk),
4476 .dout(tmp_idx_hit_vec_c2[31:0]),
4477 .siclk(siclk),
4478 .soclk(soclk)
4479
4480);
4481
4482l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_c1c2_match_c1_d1
4483 (.din(misbuf_c1c2_match_c1),
4484 .scan_in(ff_misbuf_c1c2_match_c1_d1_scanin),
4485 .scan_out(ff_misbuf_c1c2_match_c1_d1_scanout),
4486 .l1clk(l1clk),
4487 .dout(misbuf_c1c2_match_c1_d1),
4488 .siclk(siclk),
4489 .soclk(soclk)
4490
4491);
4492
4493l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_misbuf_c1c2_match_c1_d1_1
4494 (.din({2{misbuf_c1c2_match_c1}}),
4495 .scan_in(ff_misbuf_c1c2_match_c1_d1_1_scanin),
4496 .scan_out(ff_misbuf_c1c2_match_c1_d1_1_scanout),
4497 .l1clk(l1clk),
4498 .dout({misbuf_c1c2_match_c1_d1_1_clone,misbuf_c1c2_match_c1_d1_1}),
4499 .siclk(siclk),
4500 .soclk(soclk)
4501
4502);
4503
4504
4505l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_mb_hit_off_c1_d1
4506 (.din({2{arb_misbuf_hit_off_c1}}), .l1clk(l1clk),
4507 .scan_in(ff_mb_hit_off_c1_d1_scanin),
4508 .scan_out(ff_mb_hit_off_c1_d1_scanout),
4509 .dout({mb_hit_off_c1_d1_clone,mb_hit_off_c1_d1}),
4510 .siclk(siclk),
4511 .soclk(soclk)
4512);
4513
4514/////////////////////////
4515// HIt generation
4516/////////////////////////
4517
4518assign hit_vec_qual = ~mb_hit_off_c1_d1 & arb_misbuf_inst_vld_c2 ;
4519
4520assign misbuf_hit_vec_c2 = {32{hit_vec_qual}} & // BS & SR 11/04/03, MB grows to 32
4521 ( tmp_cam_hit_vec_c2 | // cam hit + c3 byp
4522 ( {32{misbuf_c1c2_match_c1_d1}} & mb_tag_wr_wl_c3_tmp )| // C2 insert byp
4523 ( {32{misbuf_c1c2_match_c1_d1 & mb_inst_vld_c3_1 &
4524 inst_mb_c3 & ~mbf_delete_c3_tmp}} & dec_mb_entry_c3 ) ) ; // C2 not delete bypass.
4525
4526l2t_misbuf_ctl_msff_ctl_macro__width_32 ff_misbuf_hit_vec_c3 // BS & SR 11/04/03, MB grows to 32
4527 (.din(misbuf_hit_vec_c2[31:0]), .l1clk(l1clk),
4528 .scan_in(ff_misbuf_hit_vec_c3_scanin),
4529 .scan_out(ff_misbuf_hit_vec_c3_scanout),
4530 .dout(misbuf_hit_vec_c3[31:0]),
4531 .siclk(siclk),
4532 .soclk(soclk)
4533);
4534
4535
4536 // BS & SR 11/04/03, MB grows to 32
4537//assign tmp_cam_hit_c2 = ( tmp_cam_hit_c2_3to0 | tmp_cam_hit_c2_7to4 |
4538// tmp_cam_hit_c2_11to8 | tmp_cam_hit_c2_15to12 |
4539// tmp_cam_hit_c2_19to16 | tmp_cam_hit_c2_23to20 |
4540// tmp_cam_hit_c2_27to24 | tmp_cam_hit_c2_31to28);
4541//
4542
4543 assign tmp_cam_hit_c2_or_all = |(tmp_cam_hit_vec_c1[31:0]);
4544
4545// this signal is going to be critical.
4546assign tmp_hit_unqual_c2 =
4547 ( misbuf_c1c2_match_c1_d1_1 & mbf_insert_c3_tmp_1 ) | // C2 insert bypass
4548 ( misbuf_c1c2_match_c1_d1_1 & inst_mb_c3_2 & mb_inst_vld_c3_2 &
4549 ~mbf_delete_c3_tmp_1 ) ; // C2 not delete bypass
4550
4551// LOGIC CLONED comPletely do not tap it off
4552
4553assign tmp_hit_unqual_c2_cloned =
4554 ( misbuf_c1c2_match_c1_d1_1_clone & mbf_insert_c3_tmp_1_clone ) | // C2 insert bypass
4555 ( misbuf_c1c2_match_c1_d1_1_clone & inst_mb_c3_2_clone & mb_inst_vld_c3_2_clone &
4556 ~mbf_delete_c3_tmp_1_clone ) ; // C2 not delete bypass
4557
4558// Isolated load for this.
4559assign misbuf_tag_hit_unqual_c2 = ( tmp_hit_unqual_c2_cloned | tmp_cam_hit_c2_clone ) & ~mb_hit_off_c1_d1_clone ; // cam hit + c3 bypass
4560
4561assign misbuf_tag_hit_unqual_c2_internal = ( tmp_hit_unqual_c2 | tmp_cam_hit_c2 ) & ~mb_hit_off_c1_d1 ; // cam hit + c3 bypass
4562
4563assign misbuf_hit_c2 = misbuf_tag_hit_unqual_c2_internal & arb_misbuf_inst_vld_c2 ;
4564
4565/////////////////////////
4566// IDX HIt generation
4567// used for generating mbfull
4568/////////////////////////
4569
4570l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_3 ff_idx_c1c2comp_c1_d1
4571 (
4572 .scan_in(ff_idx_c1c2comp_c1_d1_scanin),
4573 .scan_out(ff_idx_c1c2comp_c1_d1_scanout),
4574 .din({tmp_cam_hit_c2_or_all,tmp_cam_hit_c2_or_all,arbadr_idx_c1c2comp_c1}),
4575 .l1clk(l1clk),
4576 .dout({tmp_cam_hit_c2_clone,tmp_cam_hit_c2,arbadr_idx_c1c2comp_c1_d1}),
4577 .siclk(siclk),
4578 .soclk(soclk)
4579 );
4580
4581
4582
4583
4584assign idx_hit_vec_qual = ~mb_hit_off_c1_d1 & arb_misbuf_inst_vld_c2 ;
4585
4586assign misbuf_idx_hit_vec_c2 = {32{idx_hit_vec_qual}} & // BS & SR 11/04/03, MB grows to 32
4587 ( tmp_idx_hit_vec_c2 | // cam hit + c3 byp
4588 ( {32{arbadr_idx_c1c2comp_c1_d1}} & mb_tag_wr_wl_c3_tmp )| // C2 insert byp
4589 ( {32{arbadr_idx_c1c2comp_c1_d1 & mb_inst_vld_c3_1 &
4590 inst_mb_c3 & ~mbf_delete_c3_tmp}} & dec_mb_entry_c3 )) ;// C2 not delete bypass.
4591
4592l2t_misbuf_ctl_msff_ctl_macro__width_32 ff_misbuf_idx_hit_vec_c3
4593 (.din(misbuf_idx_hit_vec_c2[31:0]), .l1clk(l1clk),
4594 .scan_in(ff_misbuf_idx_hit_vec_c3_scanin),
4595 .scan_out(ff_misbuf_idx_hit_vec_c3_scanout),
4596 .dout(misbuf_idx_hit_vec_c3[31:0]),
4597 .siclk(siclk),
4598 .soclk(soclk)
4599);
4600
4601assign misbuf_idx_hit_vec_c3_fnl = misbuf_idx_hit_vec_c3 & mb_young;
4602
4603/////////////////////////
4604// Adder to add 32 bits from
4605// hit_vec_c3
4606/////////////////////////
4607
4608
4609
4610/////////////////////////////
4611// STAGE1
4612////////////////////////////
4613adder_1b bit0_2(
4614 // Outputs
4615 .cout (cout1[1]),
4616 .sum (cout1[0]),
4617 // Inputs
4618 .oper1 (misbuf_idx_hit_vec_c3_fnl[0]),
4619 .oper2 (misbuf_idx_hit_vec_c3_fnl[1]),
4620 .cin (misbuf_idx_hit_vec_c3_fnl[2]));
4621
4622adder_1b bit3_5(
4623 // Outputs
4624 .cout (cout2[1]),
4625 .sum (cout2[0]),
4626 // Inputs
4627 .oper1 (misbuf_idx_hit_vec_c3_fnl[3]),
4628 .oper2 (misbuf_idx_hit_vec_c3_fnl[4]),
4629 .cin (misbuf_idx_hit_vec_c3_fnl[5]));
4630
4631adder_1b bit6_8(
4632 // Outputs
4633 .cout (cout3[1]),
4634 .sum (cout3[0]),
4635 // Inputs
4636 .oper1 (misbuf_idx_hit_vec_c3_fnl[6]),
4637 .oper2 (misbuf_idx_hit_vec_c3_fnl[7]),
4638 .cin (misbuf_idx_hit_vec_c3_fnl[8]));
4639
4640adder_1b bit9_11(
4641 // Outputs
4642 .cout (cout4[1]),
4643 .sum (cout4[0]),
4644 // Inputs
4645 .oper1 (misbuf_idx_hit_vec_c3_fnl[9]),
4646 .oper2 (misbuf_idx_hit_vec_c3_fnl[10]),
4647 .cin (misbuf_idx_hit_vec_c3_fnl[11]));
4648
4649adder_1b bit12_14(
4650 // Outputs
4651 .cout (cout5[1]),
4652 .sum (cout5[0]),
4653 // Inputs
4654 .oper1 (misbuf_idx_hit_vec_c3_fnl[12]),
4655 .oper2 (misbuf_idx_hit_vec_c3_fnl[13]),
4656 .cin (misbuf_idx_hit_vec_c3_fnl[14]));
4657
4658// BS & SR 11/04/03, MB grows to 32
4659
4660adder_1b bit15_17(
4661 // Outputs
4662 .cout (cout6[1]),
4663 .sum (cout6[0]),
4664 // Inputs
4665 .oper1 (misbuf_idx_hit_vec_c3_fnl[15]),
4666 .oper2 (misbuf_idx_hit_vec_c3_fnl[16]),
4667 .cin (misbuf_idx_hit_vec_c3_fnl[17]));
4668
4669adder_1b bit18_20(
4670 // Outputs
4671 .cout (cout7[1]),
4672 .sum (cout7[0]),
4673 // Inputs
4674 .oper1 (misbuf_idx_hit_vec_c3_fnl[18]),
4675 .oper2 (misbuf_idx_hit_vec_c3_fnl[19]),
4676 .cin (misbuf_idx_hit_vec_c3_fnl[20]));
4677
4678adder_1b bit21_23(
4679 // Outputs
4680 .cout (cout8[1]),
4681 .sum (cout8[0]),
4682 // Inputs
4683 .oper1 (misbuf_idx_hit_vec_c3_fnl[21]),
4684 .oper2 (misbuf_idx_hit_vec_c3_fnl[22]),
4685 .cin (misbuf_idx_hit_vec_c3_fnl[23]));
4686
4687adder_1b bit24_26(
4688 // Outputs
4689 .cout (cout9[1]),
4690 .sum (cout9[0]),
4691 // Inputs
4692 .oper1 (misbuf_idx_hit_vec_c3_fnl[24]),
4693 .oper2 (misbuf_idx_hit_vec_c3_fnl[25]),
4694 .cin (misbuf_idx_hit_vec_c3_fnl[26]));
4695
4696adder_1b bit27_29(
4697 // Outputs
4698 .cout (cout10[1]),
4699 .sum (cout10[0]),
4700 // Inputs
4701 .oper1 (misbuf_idx_hit_vec_c3_fnl[27]),
4702 .oper2 (misbuf_idx_hit_vec_c3_fnl[28]),
4703 .cin (misbuf_idx_hit_vec_c3_fnl[29]));
4704
4705
4706
4707/////////////////////////////
4708// STAGE2
4709////////////////////////////
4710
4711
4712adder_2b bits0_5(
4713 // Outputs
4714 .sum (cout2_1[1:0]),
4715 .cout (cout2_1[2]),
4716 // Inputs
4717 .oper1 (cout1[1:0]),
4718 .oper2 (cout2[1:0]),
4719 .cin (1'b0));
4720
4721
4722adder_2b bits6_11(
4723 // Outputs
4724 .sum (cout2_2[1:0]),
4725 .cout (cout2_2[2]),
4726 // Inputs
4727 .oper1 (cout3[1:0]),
4728 .oper2 (cout4[1:0]),
4729 .cin (1'b0));
4730
4731// BS & SR 11/04/03, MB grows to 32
4732
4733adder_2b bits12_17(
4734 // Outputs
4735 .sum (cout2_3[1:0]),
4736 .cout (cout2_3[2]),
4737 // Inputs
4738 .oper1 (cout5[1:0]),
4739 .oper2 (cout6[1:0]),
4740 .cin (1'b0));
4741
4742adder_2b bits18_23(
4743 // Outputs
4744 .sum (cout2_4[1:0]),
4745 .cout (cout2_4[2]),
4746 // Inputs
4747 .oper1 (cout7[1:0]),
4748 .oper2 (cout8[1:0]),
4749 .cin (misbuf_idx_hit_vec_c3_fnl[30]));
4750
4751adder_2b bits24_29(
4752 // Outputs
4753 .sum (cout2_5[1:0]),
4754 .cout (cout2_5[2]),
4755 // Inputs
4756 .oper1 (cout9[1:0]),
4757 .oper2 (cout10[1:0]),
4758 .cin (misbuf_idx_hit_vec_c3_fnl[31]));
4759
4760
4761/////////////////////////////
4762// STAGE3
4763////////////////////////////
4764
4765
4766adder_3b bits0_11(
4767 // Outputs
4768 .sum (cout3_1[2:0]),
4769 .cout (cout3_1[3]),
4770 // Inputs
4771 .oper1 (cout2_1[2:0]),
4772 .oper2 (cout2_2[2:0]),
4773 .cin (1'b0));
4774
4775adder_3b bits12_23(
4776 // Outputs
4777 .sum (cout3_2[2:0]),
4778 .cout (cout3_2[3]),
4779 // Inputs
4780 .oper1 (cout2_3[2:0]),
4781 .oper2 (cout2_4[2:0]),
4782 .cin (1'b0));
4783
4784
4785/////////////////////////////
4786// STAGE4
4787////////////////////////////
4788
4789adder_4b bits0_23(
4790 // Outputs
4791 .sum (cout4_1[3:0]),
4792 .cout (cout4_1[4]),
4793 // Inputs
4794 .oper1 (cout3_1[3:0]),
4795 .oper2 (cout3_2[3:0]),
4796 .cin (1'b0));
4797
4798/////////////////////////////
4799// STAGE5
4800////////////////////////////
4801
4802adder_5b bits0_31(
4803 // Outputs
4804 .sum (cout5_1[4:0]),
4805 .cout (cout5_1[5]),
4806 // Inputs
4807 .oper1 (cout4_1[4:0]),
4808 .oper2 ({2'b0,cout2_5[2:0]}),
4809 .cin (1'b0));
4810
4811
4812//////////////////////////////////////////////////////////////////////////////
4813// If an instruction encounters 11 or more hits in the Miss buffer to the
4814// same index, the pipe is stalled and miss buffer full is asserted by
4815// arb until the miss buffer count drops to 11
4816//////////////////////////////////////////////////////////////////////////////
4817
4818l2t_misbuf_ctl_msff_ctl_macro__width_6 ff_hit_count_c4
4819 (.din(cout5_1[5:0]), .l1clk(l1clk),
4820 .scan_in(ff_hit_count_c4_scanin),
4821 .scan_out(ff_hit_count_c4_scanout),
4822 .dout(hit_count_c4[5:0]),
4823 .siclk(siclk),
4824 .soclk(soclk)
4825);
4826
4827// hit count = 11 or greater
4828// BS & SR 11/04/03, MB grows to 32
4829assign set_mb_idx_full_c4 = hit_count_c4[5] | hit_count_c4[4] | (hit_count_c4[3] & hit_count_c4[2]) |
4830 (hit_count_c4[3] & ~hit_count_c4[2] & hit_count_c4[1] & hit_count_c4[0] );
4831
4832// miss buffer count is 11 or less
4833assign reset_mb_idx_full_c4 = ~mb_count_c4[4] & ~mb_count_c4[5] & // BS & SR 11/04/03, MB grows to 32
4834 ~(mb_count_c4[3] & mb_count_c4[2]); // BS & SR 11/04/03, MB grows to 32
4835
4836
4837assign mb_idx_count_full_c4 = ( mb_idx_count_full_c5 |
4838 set_mb_idx_full_c4 )
4839 & ~reset_mb_idx_full_c4 ;
4840
4841l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_mb_idx_count_full_c5 // sync reset active low
4842 (.din(mb_idx_count_full_c4), .l1clk(l1clk),
4843 .scan_in(ff_mb_idx_count_full_c5_scanin),
4844 .scan_out(ff_mb_idx_count_full_c5_scanout),
4845 .dout(mb_idx_count_full_c5),
4846 .clr(~dbb_rst_l),
4847 .siclk(siclk),
4848 .soclk(soclk));
4849
4850
4851
4852
4853//////////////////////////////////////////////////////////////////////////////
4854// mbdata Insertion
4855// Write the miss Buffer data array in the C9 cycle of the following types of
4856// instructions:
4857// 1) Miss Buffer instruction that is not deleted in C3
4858// 2) Iq instr instruction that is inserted in the Miss Buffer.
4859//////////////////////////////////////////////////////////////////////////////
4860
4861l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c3
4862 (.din(arbdec_arbdp_inst_mb_c2), .l1clk(l1clk),
4863 .scan_in(ff_inst_mb_c3_scanin),
4864 .scan_out(ff_inst_mb_c3_scanout),
4865 .dout(inst_mb_c3),
4866 .siclk(siclk),
4867 .soclk(soclk)
4868);
4869
4870l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_inst_mb_c3_2
4871 (.din({2{arbdec_arbdp_inst_mb_c2}}), .l1clk(l1clk),
4872 .scan_in(ff_inst_mb_c3_2_scanin),
4873 .scan_out(ff_inst_mb_c3_2_scanout),
4874 .dout({inst_mb_c3_2_clone,inst_mb_c3_2}),
4875 .siclk(siclk),
4876 .soclk(soclk)
4877);
4878
4879l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_inst_vld_c3
4880 (.din(arb_misbuf_inst_vld_c2), .l1clk(l1clk),
4881 .scan_in(ff_mb_inst_vld_c3_scanin),
4882 .scan_out(ff_mb_inst_vld_c3_scanout),
4883 .dout(mb_inst_vld_c3),
4884 .siclk(siclk),
4885 .soclk(soclk)
4886);
4887
4888l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_inst_vld_c3_1
4889 (.din(arb_misbuf_inst_vld_c2), .l1clk(l1clk),
4890 .scan_in(ff_mb_inst_vld_c3_1_scanin),
4891 .scan_out(ff_mb_inst_vld_c3_1_scanout),
4892 .dout(mb_inst_vld_c3_1),
4893 .siclk(siclk),
4894 .soclk(soclk)
4895);
4896
4897
4898l2t_misbuf_ctl_msff_ctl_macro__width_6 ff_mb_inst_vld_staging
4899 (
4900 .scan_in(ff_mb_inst_vld_staging_scanin),
4901 .scan_out(ff_mb_inst_vld_staging_scanout),
4902 .dout ({misbuf_inst_c4,misbuf_inst_c5,misbuf_inst_c52,misbuf_inst_c6,misbuf_inst_c7,misbuf_inst_c8}),
4903 .din ({inst_mb_c3,misbuf_inst_c4,misbuf_inst_c5,misbuf_inst_c52,misbuf_inst_c6,misbuf_inst_c7}),
4904 .l1clk (l1clk),
4905 .siclk(siclk),
4906 .soclk(soclk)
4907 );
4908
4909
4910
4911l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_mb_inst_vld_c3_2
4912 (
4913 .scan_in(ff_mb_inst_vld_c3_2_scanin),
4914 .scan_out(ff_mb_inst_vld_c3_2_scanout),
4915 .din({2{arb_misbuf_inst_vld_c2}}), .l1clk(l1clk),
4916 .dout({mb_inst_vld_c3_2_clone,mb_inst_vld_c3_2}),
4917 .siclk(siclk),
4918 .soclk(soclk)
4919);
4920
4921
4922assign mb_rewrite_en_c3 = ( inst_mb_c3 &
4923 ~mbf_delete_c3 &
4924 mb_inst_vld_c3_1 ) ;
4925
4926l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_rewrite_en_c4
4927 (.din(mb_rewrite_en_c3), .l1clk(l1clk),
4928 .scan_in(ff_mb_rewrite_en_c4_scanin),
4929 .scan_out(ff_mb_rewrite_en_c4_scanout),
4930 .dout(mb_rewrite_en_c4),
4931 .siclk(siclk),
4932 .soclk(soclk)
4933);
4934
4935l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_rewrite_en_c5
4936 (.din(mb_rewrite_en_c4), .l1clk(l1clk),
4937 .scan_in(ff_mb_rewrite_en_c5_scanin),
4938 .scan_out(ff_mb_rewrite_en_c5_scanout),
4939 .dout(mb_rewrite_en_c5),
4940 .siclk(siclk),
4941 .soclk(soclk)
4942);
4943
4944// BS 03/11/04 extra cycle for mem access
4945
4946l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_rewrite_en_c52
4947 (.din(mb_rewrite_en_c5), .l1clk(l1clk),
4948 .scan_in(ff_mb_rewrite_en_c52_scanin),
4949 .scan_out(ff_mb_rewrite_en_c52_scanout),
4950 .dout(mb_rewrite_en_c52),
4951 .siclk(siclk),
4952 .soclk(soclk)
4953);
4954
4955
4956l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_rewrite_en_c6
4957 (.din(mb_rewrite_en_c52), .l1clk(l1clk),
4958 .scan_in(ff_mb_rewrite_en_c6_scanin),
4959 .scan_out(ff_mb_rewrite_en_c6_scanout),
4960 .dout(mb_rewrite_en_c6),
4961 .siclk(siclk),
4962 .soclk(soclk)
4963);
4964
4965l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_rewrite_en_c7
4966 (.din(mb_rewrite_en_c6), .l1clk(l1clk),
4967 .scan_in(ff_mb_rewrite_en_c7_scanin),
4968 .scan_out(ff_mb_rewrite_en_c7_scanout),
4969 .dout(mb_rewrite_en_c7),
4970 .siclk(siclk),
4971 .soclk(soclk)
4972);
4973
4974l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_rewrite_en_c8
4975 (.din(mb_rewrite_en_c7), .l1clk(l1clk),
4976 .scan_in(ff_mb_rewrite_en_c8_scanin),
4977 .scan_out(ff_mb_rewrite_en_c8_scanout),
4978 .dout(mb_rewrite_en_c8),
4979 .siclk(siclk),
4980 .soclk(soclk)
4981);
4982
4983
4984assign mbdata_wr_en_c3 = ( mbf_insert_c3 | mb_rewrite_en_c3 ) ;
4985
4986l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbdata_wr_en_c4
4987 (.din(mbdata_wr_en_c3), .l1clk(l1clk),
4988 .scan_in(ff_mbdata_wr_en_c4_scanin),
4989 .scan_out(ff_mbdata_wr_en_c4_scanout),
4990 .dout(mbdata_wr_en_c4),
4991 .siclk(siclk),
4992 .soclk(soclk)
4993);
4994
4995l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbdata_wr_en_c5
4996 (.din(mbdata_wr_en_c4), .l1clk(l1clk),
4997 .scan_in(ff_mbdata_wr_en_c5_scanin),
4998 .scan_out(ff_mbdata_wr_en_c5_scanout),
4999 .dout(mbdata_wr_en_c5),
5000 .siclk(siclk),
5001 .soclk(soclk)
5002);
5003
5004// BS 03/11/04 extra cycle for mem access
5005
5006l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbdata_wr_en_c52
5007 (.din(mbdata_wr_en_c5), .l1clk(l1clk),
5008 .scan_in(ff_mbdata_wr_en_c52_scanin),
5009 .scan_out(ff_mbdata_wr_en_c52_scanout),
5010 .dout(mbdata_wr_en_c52),
5011 .siclk(siclk),
5012 .soclk(soclk)
5013);
5014
5015
5016l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbdata_wr_en_c6
5017 (.din(mbdata_wr_en_c52), .l1clk(l1clk),
5018 .scan_in(ff_mbdata_wr_en_c6_scanin),
5019 .scan_out(ff_mbdata_wr_en_c6_scanout),
5020 .dout(mbdata_wr_en_c6),
5021 .siclk(siclk),
5022 .soclk(soclk)
5023);
5024
5025l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbdata_wr_en_c7
5026 (.din(mbdata_wr_en_c6), .l1clk(l1clk),
5027 .scan_in(ff_mbdata_wr_en_c7_scanin),
5028 .scan_out(ff_mbdata_wr_en_c7_scanout),
5029 .dout(mbdata_wr_en_c7),
5030 .siclk(siclk),
5031 .soclk(soclk)
5032);
5033
5034l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbdata_wr_en_c8
5035 (.din(mbdata_wr_en_c7), .l1clk(l1clk),
5036 .scan_in(ff_mbdata_wr_en_c8_scanin),
5037 .scan_out(ff_mbdata_wr_en_c8_scanout),
5038 .dout(misbuf_mbdata_wr_en_c8_fnl),
5039 .siclk(siclk),
5040 .soclk(soclk)
5041);
5042
5043assign misbuf_mbdata_wr_en_c8 = l2t_mb2_run_r1 ? l2t_mb2_mbdata_wr_en_r2 : misbuf_mbdata_wr_en_c8_fnl;
5044
5045
5046//////////////////////////////////////////////////////////////////////////////
5047// mbdata wr wordline
5048// The wordline chosen for a write into MBDATA is either of the following
5049// * wordline that just got inserted.
5050// * wordline that just got reinserted
5051// * Wordline of the dependent instruction ( Used only to RDY a CAS2 instruction
5052// and not to write into mbdata )
5053//////////////////////////////////////////////////////////////////////////////
5054
5055// BS & SR 11/04/03, MB grows to 32
5056assign enc_tag_wr_wl_c2[0] = ( mb_write_ptr_c2[1] | mb_write_ptr_c2[3] |
5057 mb_write_ptr_c2[5] | mb_write_ptr_c2[7] |
5058 mb_write_ptr_c2[9] | mb_write_ptr_c2[11] |
5059 mb_write_ptr_c2[13] | mb_write_ptr_c2[15] |
5060 mb_write_ptr_c2[17] | mb_write_ptr_c2[19] |
5061 mb_write_ptr_c2[21] | mb_write_ptr_c2[23] |
5062 mb_write_ptr_c2[25] | mb_write_ptr_c2[27] |
5063 mb_write_ptr_c2[27] | mb_write_ptr_c2[29]|
5064 mb_write_ptr_c2[31]
5065 );
5066
5067assign enc_tag_wr_wl_c2[1] = ( mb_write_ptr_c2[2] | mb_write_ptr_c2[3] |
5068 mb_write_ptr_c2[6] | mb_write_ptr_c2[7] |
5069 mb_write_ptr_c2[10] | mb_write_ptr_c2[11] |
5070 mb_write_ptr_c2[14] | mb_write_ptr_c2[15] |
5071 mb_write_ptr_c2[18] | mb_write_ptr_c2[19] |
5072 mb_write_ptr_c2[22] | mb_write_ptr_c2[23] |
5073 mb_write_ptr_c2[26] | mb_write_ptr_c2[27] |
5074 mb_write_ptr_c2[30] | mb_write_ptr_c2[31]
5075 );
5076
5077assign enc_tag_wr_wl_c2[2] = ( mb_write_ptr_c2[4] | mb_write_ptr_c2[5] |
5078 mb_write_ptr_c2[6] | mb_write_ptr_c2[7] |
5079 mb_write_ptr_c2[12] | mb_write_ptr_c2[13] |
5080 mb_write_ptr_c2[14] | mb_write_ptr_c2[15] |
5081 mb_write_ptr_c2[20] | mb_write_ptr_c2[21] |
5082 mb_write_ptr_c2[22] | mb_write_ptr_c2[23] |
5083 mb_write_ptr_c2[28] | mb_write_ptr_c2[29] |
5084 mb_write_ptr_c2[30] | mb_write_ptr_c2[31]
5085 );
5086
5087assign enc_tag_wr_wl_c2[3] = ( mb_write_ptr_c2[8] | mb_write_ptr_c2[9] |
5088 mb_write_ptr_c2[10] | mb_write_ptr_c2[11] |
5089 mb_write_ptr_c2[12] | mb_write_ptr_c2[13] |
5090 mb_write_ptr_c2[14] | mb_write_ptr_c2[15] |
5091 mb_write_ptr_c2[24] | mb_write_ptr_c2[25] |
5092 mb_write_ptr_c2[26] | mb_write_ptr_c2[27] |
5093 mb_write_ptr_c2[28] | mb_write_ptr_c2[29] |
5094 mb_write_ptr_c2[30] | mb_write_ptr_c2[31]);
5095
5096assign enc_tag_wr_wl_c2[4] = ( mb_write_ptr_c2[16] | mb_write_ptr_c2[17] |
5097 mb_write_ptr_c2[18] | mb_write_ptr_c2[19] |
5098 mb_write_ptr_c2[20] | mb_write_ptr_c2[21] |
5099 mb_write_ptr_c2[22] | mb_write_ptr_c2[23] |
5100 mb_write_ptr_c2[24] | mb_write_ptr_c2[25] |
5101 mb_write_ptr_c2[26] | mb_write_ptr_c2[27] |
5102 mb_write_ptr_c2[28] | mb_write_ptr_c2[29] |
5103 mb_write_ptr_c2[30] | mb_write_ptr_c2[31]);
5104
5105
5106l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_tag_wr_wl_c3 // BS & SR 11/04/03, MB grows to 32
5107 (.din(enc_tag_wr_wl_c2[4:0]), .l1clk(l1clk),
5108 .scan_in(ff_enc_tag_wr_wl_c3_scanin),
5109 .scan_out(ff_enc_tag_wr_wl_c3_scanout),
5110 .dout(enc_tag_wr_wl_c3[4:0]),
5111 .siclk(siclk),
5112 .soclk(soclk)
5113);
5114
5115l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_5 mux_enc_data_wr_wl_c3 // BS & SR 11/04/03, MB grows to 32
5116 (.dout(enc_data_wr_wl_c3[4:0]),
5117 .din0(enc_tag_wr_wl_c3[4:0]), // inserting entry in C3
5118 .din1(mb_entry_c3[4:0]), // reinserting entry in C3
5119 .din2(misbuf_next_link_c3[4:0]),// depdendent of C3 instruction
5120 .sel0(mbf_insert_c3),
5121 .sel1(mb_rewrite_en_c3),
5122 .sel2(~mbdata_wr_en_c3));
5123
5124
5125assign misbuf_wbuf_mbid_c4 = enc_data_wr_wl_c4 ;
5126
5127l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c4 // BS & SR 11/04/03, MB grows to 32
5128 (.din(enc_data_wr_wl_c3[4:0]), .l1clk(l1clk),
5129 .scan_in(ff_enc_data_wr_wl_c4_scanin),
5130 .scan_out(ff_enc_data_wr_wl_c4_scanout),
5131 .dout(enc_data_wr_wl_c4[4:0]),
5132 .siclk(siclk),
5133 .soclk(soclk)
5134);
5135
5136l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c5 // BS & SR 11/04/03, MB grows to 32
5137 (.din(enc_data_wr_wl_c4[4:0]), .l1clk(l1clk),
5138 .scan_in(ff_enc_data_wr_wl_c5_scanin),
5139 .scan_out(ff_enc_data_wr_wl_c5_scanout),
5140 .dout(enc_data_wr_wl_c5[4:0]),
5141 .siclk(siclk),
5142 .soclk(soclk)
5143);
5144
5145// BS 03/11/04 extra cycle for mem access
5146
5147l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c52 // BS & SR 11/04/03, MB grows to 32
5148 (.din(enc_data_wr_wl_c5[4:0]), .l1clk(l1clk),
5149 .scan_in(ff_enc_data_wr_wl_c52_scanin),
5150 .scan_out(ff_enc_data_wr_wl_c52_scanout),
5151 .dout(enc_data_wr_wl_c52[4:0]),
5152 .siclk(siclk),
5153 .soclk(soclk)
5154);
5155
5156
5157l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c6 // BS & SR 11/04/03, MB grows to 32
5158 (.din(enc_data_wr_wl_c52[4:0]), .l1clk(l1clk),
5159 .scan_in(ff_enc_data_wr_wl_c6_scanin),
5160 .scan_out(ff_enc_data_wr_wl_c6_scanout),
5161 .dout(enc_data_wr_wl_c6[4:0]),
5162 .siclk(siclk),
5163 .soclk(soclk)
5164);
5165
5166l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c7 // BS & SR 11/04/03, MB grows to 32
5167 (.din(enc_data_wr_wl_c6[4:0]), .l1clk(l1clk),
5168 .scan_in(ff_enc_data_wr_wl_c7_scanin),
5169 .scan_out(ff_enc_data_wr_wl_c7_scanout),
5170 .dout(enc_data_wr_wl_c7[4:0]),
5171 .siclk(siclk),
5172 .soclk(soclk)
5173);
5174
5175l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c8 // BS & SR 11/04/03, MB grows to 32
5176 (.din(enc_data_wr_wl_c7[4:0]), .l1clk(l1clk),
5177 .scan_in(ff_enc_data_wr_wl_c8_scanin),
5178 .scan_out(ff_enc_data_wr_wl_c8_scanout),
5179 .dout(enc_data_wr_wl_c8[4:0]),
5180 .siclk(siclk),
5181 .soclk(soclk)
5182);
5183
5184l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c9 // BS & SR 11/04/03, MB grows to 32
5185 (.din(enc_data_wr_wl_c8[4:0]), .l1clk(l1clk),
5186 .scan_in(ff_enc_data_wr_wl_c9_scanin),
5187 .scan_out(ff_enc_data_wr_wl_c9_scanout),
5188 .dout(enc_data_wr_wl_c9[4:0]),
5189 .siclk(siclk),
5190 .soclk(soclk)
5191);
5192
5193// BS & SR 11/04/03, MB grows to 32
5194
5195assign dec_low_insert_ptr[0] = ( enc_data_wr_wl_c8[1:0] == 2'd0 );
5196assign dec_low_insert_ptr[1] = ( enc_data_wr_wl_c8[1:0] == 2'd1 );
5197assign dec_low_insert_ptr[2] = ( enc_data_wr_wl_c8[1:0] == 2'd2 );
5198assign dec_low_insert_ptr[3] = ( enc_data_wr_wl_c8[1:0] == 2'd3 );
5199
5200assign dec_hi_insert_ptr[0] = ( enc_data_wr_wl_c8[4:2] == 3'd0 );
5201assign dec_hi_insert_ptr[1] = ( enc_data_wr_wl_c8[4:2] == 3'd1 );
5202assign dec_hi_insert_ptr[2] = ( enc_data_wr_wl_c8[4:2] == 3'd2 );
5203assign dec_hi_insert_ptr[3] = ( enc_data_wr_wl_c8[4:2] == 3'd3 );
5204assign dec_hi_insert_ptr[4] = ( enc_data_wr_wl_c8[4:2] == 3'd4 );
5205assign dec_hi_insert_ptr[5] = ( enc_data_wr_wl_c8[4:2] == 3'd5 );
5206assign dec_hi_insert_ptr[6] = ( enc_data_wr_wl_c8[4:2] == 3'd6 );
5207assign dec_hi_insert_ptr[7] = ( enc_data_wr_wl_c8[4:2] == 3'd7 );
5208
5209assign insert_ptr_c8[0] = ( dec_hi_insert_ptr[0] & dec_low_insert_ptr[0] ) ;
5210assign insert_ptr_c8[1] = ( dec_hi_insert_ptr[0] & dec_low_insert_ptr[1] ) ;
5211assign insert_ptr_c8[2] = ( dec_hi_insert_ptr[0] & dec_low_insert_ptr[2] ) ;
5212assign insert_ptr_c8[3] = ( dec_hi_insert_ptr[0] & dec_low_insert_ptr[3] ) ;
5213assign insert_ptr_c8[4] = ( dec_hi_insert_ptr[1] & dec_low_insert_ptr[0] ) ;
5214assign insert_ptr_c8[5] = ( dec_hi_insert_ptr[1] & dec_low_insert_ptr[1] ) ;
5215assign insert_ptr_c8[6] = ( dec_hi_insert_ptr[1] & dec_low_insert_ptr[2] ) ;
5216assign insert_ptr_c8[7] = ( dec_hi_insert_ptr[1] & dec_low_insert_ptr[3] ) ;
5217assign insert_ptr_c8[8] = ( dec_hi_insert_ptr[2] & dec_low_insert_ptr[0] ) ;
5218assign insert_ptr_c8[9] = ( dec_hi_insert_ptr[2] & dec_low_insert_ptr[1] ) ;
5219assign insert_ptr_c8[10] = ( dec_hi_insert_ptr[2] & dec_low_insert_ptr[2] ) ;
5220assign insert_ptr_c8[11] = ( dec_hi_insert_ptr[2] & dec_low_insert_ptr[3] ) ;
5221assign insert_ptr_c8[12] = ( dec_hi_insert_ptr[3] & dec_low_insert_ptr[0] ) ;
5222assign insert_ptr_c8[13] = ( dec_hi_insert_ptr[3] & dec_low_insert_ptr[1] ) ;
5223assign insert_ptr_c8[14] = ( dec_hi_insert_ptr[3] & dec_low_insert_ptr[2] ) ;
5224assign insert_ptr_c8[15] = ( dec_hi_insert_ptr[3] & dec_low_insert_ptr[3] ) ;
5225// BS & SR 11/04/03, MB grows to 32
5226assign insert_ptr_c8[16] = ( dec_hi_insert_ptr[4] & dec_low_insert_ptr[0] ) ;
5227assign insert_ptr_c8[17] = ( dec_hi_insert_ptr[4] & dec_low_insert_ptr[1] ) ;
5228assign insert_ptr_c8[18] = ( dec_hi_insert_ptr[4] & dec_low_insert_ptr[2] ) ;
5229assign insert_ptr_c8[19] = ( dec_hi_insert_ptr[4] & dec_low_insert_ptr[3] ) ;
5230assign insert_ptr_c8[20] = ( dec_hi_insert_ptr[5] & dec_low_insert_ptr[0] ) ;
5231assign insert_ptr_c8[21] = ( dec_hi_insert_ptr[5] & dec_low_insert_ptr[1] ) ;
5232assign insert_ptr_c8[22] = ( dec_hi_insert_ptr[5] & dec_low_insert_ptr[2] ) ;
5233assign insert_ptr_c8[23] = ( dec_hi_insert_ptr[5] & dec_low_insert_ptr[3] ) ;
5234assign insert_ptr_c8[24] = ( dec_hi_insert_ptr[6] & dec_low_insert_ptr[0] ) ;
5235assign insert_ptr_c8[25] = ( dec_hi_insert_ptr[6] & dec_low_insert_ptr[1] ) ;
5236assign insert_ptr_c8[26] = ( dec_hi_insert_ptr[6] & dec_low_insert_ptr[2] ) ;
5237assign insert_ptr_c8[27] = ( dec_hi_insert_ptr[6] & dec_low_insert_ptr[3] ) ;
5238assign insert_ptr_c8[28] = ( dec_hi_insert_ptr[7] & dec_low_insert_ptr[0] ) ;
5239assign insert_ptr_c8[29] = ( dec_hi_insert_ptr[7] & dec_low_insert_ptr[1] ) ;
5240assign insert_ptr_c8[30] = ( dec_hi_insert_ptr[7] & dec_low_insert_ptr[2] ) ;
5241assign insert_ptr_c8[31] = ( dec_hi_insert_ptr[7] & dec_low_insert_ptr[3] ) ;
5242
5243
5244assign mb_data_wr_wl_c8 = insert_ptr_c8 & {32{misbuf_mbdata_wr_en_c8}} ; // BS & SR 11/04/03, MB grows to 32
5245//assign misbuf_mb_data_write_wl = mb_data_wr_wl_c8 ;
5246assign misbuf_mb_data_write_wl = l2t_mb2_run_r1 ? mbtag_write_ptr[31:0] : mb_data_wr_wl_c8[31:0];
5247assign misbuf_mbentry_c8 = enc_data_wr_wl_c8 ;
5248
5249//////////////////////////////////////////////////////////////////////////////
5250// DEP bit is used by the st ack logic to send an ACK for a store issued
5251// out of the Miss Buffer.
5252//
5253// THis bit is set
5254// - if an ifetch or load not issued from the MB misses in L2. //BS and SR 11/07/03, store pipelining support
5255// we set the DEP bit in such a case, so that a future store to the same address
5256// sees that the load/ifetch's dep bit has been set and then sets its own DEP bit
5257// and goes into the Miss Buffer. This avoids early caming and early store ack in the
5258// case of store hit to outstanding load.
5259// - for a swap/cas2 not issued from the miss buffer
5260// - if any instruction other than a store instruction hits the Miss Buffer
5261// - if a store instruction hits the Miss Buffer and DEP bit for at least one entry it hits
5262// against is a 1, BS and SR 11/07/03, store pipelining support
5263// ( if DEP bits for all the entries the store hits against are 0's , then should not
5264// ( set DEP bit. BS and SR 11/07/03, store pipelining support)
5265// - an instruction from the Miss Buffer encountering a tag par err.
5266// - an instruction from the Miss Buffer with tecc=1
5267// - an instruction from the IQ encountering a tag parity error.
5268// - an instruction from core/SIU encountering a VUAD SBE // VUAD ecc change
5269//////////////////////////////////////////////////////////////////////////////
5270
5271
5272assign misbuf_dep_inst_c2 = misbuf_hit_c2 ;
5273
5274l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_dep_c3
5275 (.din(misbuf_dep_inst_c2), .l1clk(l1clk),
5276 .scan_in(ff_mbf_dep_c3_scanin),
5277 .scan_out(ff_mbf_dep_c3_scanout),
5278 .dout(misbuf_dep_inst_c3_tmp),
5279 .siclk(siclk),
5280 .soclk(soclk)
5281);
5282
5283// the following signal represents the DEP bit of an instr.
5284l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_dep_inst_c3
5285 (.din(arbdec_arbdp_inst_dep_c2), .l1clk(l1clk),
5286 .scan_in(ff_dep_inst_c3_scanin),
5287 .scan_out(ff_dep_inst_c3_scanout),
5288 .dout(dep_inst_c3),
5289 .siclk(siclk),
5290 .soclk(soclk)
5291);
5292
5293// the following signal represents the TECC bit of an instr.
5294l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_tecc_c3
5295 (.din(arb_tecc_c2), .l1clk(l1clk),
5296 .scan_in(ff_tecc_c3_scanin),
5297 .scan_out(ff_tecc_c3_scanout),
5298 .dout(tecc_c3),
5299 .siclk(siclk),
5300 .soclk(soclk)
5301);
5302
5303//BS and SR 11/07/03, store pipelining support
5304
5305assign set_dep_ldifetch_miss_c2 = ( arb_decdp_ld_inst_c2 | arb_decdp_imiss_inst_c2 | arb_decdp_cas1_inst_c2
5306 ) & tag_miss_unqual_c2;
5307
5308//BS and SR 11/07/03, store pipelining support
5309
5310l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_set_dep_c2_ldifetch_miss_c2
5311 (.din(set_dep_ldifetch_miss_c2), .l1clk(l1clk),
5312 .scan_in(ff_set_dep_c2_ldifetch_miss_c2_scanin),
5313 .scan_out(ff_set_dep_c2_ldifetch_miss_c2_scanout),
5314 .dout(set_dep_ldifetch_miss_c3),
5315 .siclk(siclk),
5316 .soclk(soclk)
5317);
5318
5319
5320assign misbuf_dep_inst_c3 = (misbuf_dep_inst_c3_tmp & ~tag_store_inst_c3 & ~arb_pf_ice_inst_c3) |
5321 //if mbf hit and not a store instruction or Prefetch ICE instruction hit set DEP
5322 ( misbuf_dep_inst_c3_tmp & tag_store_inst_c3 & mb_hit_dep_one) |
5323 // if mbf hit and a store instruction hit set DEP only if at least one
5324 // of the DEP bits of the entries the store hits against is 1;
5325 (arb_vuad_ce_err_c3 & ~inst_mb_c3) |
5326 // Set on vuad ce error for an instruction not issued from misbuf
5327 ( misbuf_dep_inst_c3_tmp & tag_store_inst_c3 & filbuf_match_c3 ) |
5328 // If an instruction hits in both filbuf and misbuf then
5329 // there is a previous store to the same address and a pending fill to
5330 // happen. In this case set the dep bit : fix for bug 84674
5331 ( dep_inst_c3 & tag_misbuf_par_err_c3 & ~tag_hit_unqual_c3 ) |
5332 // if a tagpar do not reset DEP
5333 ( dep_inst_c3 & tecc_c3 ) | // if a tag scrub, do not reset DEP
5334 ( dep_inst_c3 & arb_vuad_ce_err_c3) | // if a VUAD CE on a dependant instruction, do not reset DEP
5335 ( ~inst_mb_c3 & tag_misbuf_par_err_c3 & ~tag_hit_unqual_c3) | // if a tagpar set DEP
5336 ( ~inst_mb_c3 & (set_dep_ldifetch_miss_c3 | arb_decdp_cas2_inst_c3 | arb_decdp_swap_inst_c3)) ;
5337 // BS and SR 11/07/03, store pipelining support
5338
5339
5340//BS and SR 11/07/03, store pipelining support
5341// due to timing reason the qualifying with tag_store_inst_c3 is moved to tag_ctl
5342//assign misbuf_hit_st_dep_zero = ( misbuf_dep_inst_c3_tmp & tag_store_inst_c3 & ~mb_hit_dep_one);
5343assign misbuf_hit_st_dep_zero = ( misbuf_dep_inst_c3_tmp & ~mb_hit_dep_one);
5344 // if mbf hit and a store instruction hit and all the DEP bits of the entries
5345 // the store hits against are 0's, do not set DEP bit, but enable Caming
5346 // for store and send store ack. This would accelerate acks for the
5347 // store pipelining case
5348
5349l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_mbf_dep_c4
5350 (.din({misbuf_dep_inst_c3,arb_decdp_swap_inst_c2,arb_decdp_cas2_inst_c2}), .l1clk(l1clk),
5351 .scan_in(ff_mbf_dep_c4_scanin),
5352 .scan_out(ff_mbf_dep_c4_scanout),
5353 .dout({misbuf_dep_inst_c4,arb_decdp_swap_inst_c3,arb_decdp_cas2_inst_c3}),
5354 .siclk(siclk),
5355 .soclk(soclk)
5356);
5357
5358// BS and SR 11/07/03, store pipelining support
5359// We create 32 DEP bits to decide if subsequent stores that hit to one or more
5360// entries with DEP bit = 1, should also set their DEP bit . Loads will not look
5361// at DEP bits of entries they hit against . If a store hits against entries for
5362// which all DEP bits are 0, the store will issue the ack and cam the directory
5363// in the first phase itself , thereby accelerating the acks for the store pipelining
5364// case
5365
5366assign mb_dep_prev = ( (mb_tag_wr_wl_c3 & {32{misbuf_dep_inst_c3}}) | mb_dep ) & ~reset_valid_bit_c3 ;
5367
5368// BS & SR 11/04/03, MB grows to 32
5369l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_dep_bit // sync reset active low
5370 (.din(mb_dep_prev[31:0]), .l1clk(l1clk),
5371 .scan_in(ff_dep_bit_scanin),
5372 .scan_out(ff_dep_bit_scanout),
5373 .clr(~dbb_rst_l), .dout(mb_dep[31:0]),
5374 .siclk(siclk),
5375 .soclk(soclk)
5376);
5377
5378// BS and SR 11/07/03, store pipelining support
5379// this logic senses if one or more DEP bits for all the entries that the current
5380// instruction hits against in the Miss Buffer are 1 or not. the logic is used only
5381// by stores to not set DEP bit and send ack immeditaley in the first pass in case
5382// the result of this logic turns out to be false. If the result turns out ot be true,
5383// then the store can set its dep bit and ack and caming will happen in the second
5384// pass (after getting replayed from the Miss Buffer)
5385
5386assign mb_hit_dep_one = | (misbuf_hit_vec_c3[31:0] & mb_dep[31:0]);
5387
5388l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_dep_c5
5389 (.din(misbuf_dep_inst_c4), .l1clk(l1clk),
5390 .scan_in(ff_mbf_dep_c5_scanin),
5391 .scan_out(ff_mbf_dep_c5_scanout),
5392 .dout(misbuf_dep_inst_c5),
5393 .siclk(siclk),
5394 .soclk(soclk)
5395);
5396
5397// BS 03/11/04 extra cycle for mem access
5398
5399l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_dep_c52
5400 (.din(misbuf_dep_inst_c5), .l1clk(l1clk),
5401 .scan_in(ff_mbf_dep_c52_scanin),
5402 .scan_out(ff_mbf_dep_c52_scanout),
5403 .dout(misbuf_dep_inst_c52),
5404 .siclk(siclk),
5405 .soclk(soclk)
5406);
5407
5408
5409l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_dep_c6
5410 (.din(misbuf_dep_inst_c52), .l1clk(l1clk),
5411 .scan_in(ff_mbf_dep_c6_scanin),
5412 .scan_out(ff_mbf_dep_c6_scanout),
5413 .dout(misbuf_dep_inst_c6),
5414 .siclk(siclk),
5415 .soclk(soclk)
5416);
5417
5418l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_dep_c7
5419 (.din(misbuf_dep_inst_c6), .l1clk(l1clk),
5420 .scan_in(ff_mbf_dep_c7_scanin),
5421 .scan_out(ff_mbf_dep_c7_scanout),
5422 .dout(misbuf_dep_inst_c7),
5423 .siclk(siclk),
5424 .soclk(soclk)
5425);
5426
5427l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_dep_c8
5428 (.din(misbuf_dep_inst_c7), .l1clk(l1clk),
5429 .scan_in(ff_mbf_dep_c8_scanin),
5430 .scan_out(ff_mbf_dep_c8_scanout),
5431 .dout(misbuf_dep_c8),
5432 .siclk(siclk),
5433 .soclk(soclk)
5434);
5435
5436//////////////////////////////////////////////////////////////////////////////
5437// EVICT bit in MBdata
5438// The evict bit is set for a "true miss" with no VUAD CE, to indicate that its
5439// next pass is going to cause an EVICTION. The EVICT bit is reset
5440// when an evict instruction makes a pass down the Pipe.
5441// Tecc and VUAD CE cases are exception cases: EVICT bit is not reset for an evict
5442// instruction pass if that pass encounters a TECC error or VUAD CE.
5443//////////////////////////////////////////////////////////////////////////////
5444
5445
5446assign buffer_miss_vld_c2 = ~misbuf_tag_hit_unqual_c2_internal &
5447 ~filbuf_misbuf_match_c2 &
5448 ~wbuf_hit_unqual_c2 &
5449 ~rdmat_hit_unqual_c2 &
5450 arb_misbuf_inst_vld_c2 ;
5451assign misbuf_mark_evict_tmp_c2 =
5452 tag_miss_unqual_c2 & // 0 for an evict instruction
5453 buffer_miss_vld_c2;
5454
5455l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_mark_evict_tmp_c3
5456 (.din(misbuf_mark_evict_tmp_c2), .l1clk(l1clk),
5457 .scan_in(ff_misbuf_mark_evict_tmp_c3_scanin),
5458 .scan_out(ff_misbuf_mark_evict_tmp_c3_scanout),
5459 .dout(misbuf_mark_evict_tmp_c3),
5460 .siclk(siclk),
5461 .soclk(soclk)
5462);
5463
5464l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_vld_unqual_c3
5465 (.din(arb_evict_vld_c2), .l1clk(l1clk),
5466 .scan_in(ff_evict_vld_unqual_c3_scanin),
5467 .scan_out(ff_evict_vld_unqual_c3_scanout),
5468 .dout(evict_vld_unqual_c3),
5469 .siclk(siclk),
5470 .soclk(soclk)
5471);
5472
5473l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_decdp_wr64_inst_c3
5474 (.din(arb_decdp_wr64_inst_c2), .l1clk(l1clk),
5475 .scan_in(ff_decdp_wr64_inst_c3_scanin),
5476 .scan_out(ff_decdp_wr64_inst_c3_scanout),
5477 .dout(wr64_inst_c3),
5478 .siclk(siclk),
5479 .soclk(soclk)
5480);
5481
5482
5483l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_decdp_ld64_inst_c3
5484 (.din(arb_decdp_ld64_inst_c2), .l1clk(l1clk),
5485 .scan_in(ff_decdp_ld64_inst_c3_scanin),
5486 .scan_out(ff_decdp_ld64_inst_c3_scanout),
5487 .dout(ld64_inst_c3),
5488 .siclk(siclk),
5489 .soclk(soclk)
5490);
5491
5492l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c4
5493 (.din(ld64_inst_c3), .l1clk(l1clk),
5494 .scan_in(ff_ld64_inst_c4_scanin),
5495 .scan_out(ff_ld64_inst_c4_scanout),
5496 .dout(ld64_inst_c4),
5497 .siclk(siclk),
5498 .soclk(soclk)
5499);
5500
5501l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c5
5502 (.din(ld64_inst_c4), .l1clk(l1clk),
5503 .scan_in(ff_ld64_inst_c5_scanin),
5504 .scan_out(ff_ld64_inst_c5_scanout),
5505 .dout(ld64_inst_c5),
5506 .siclk(siclk),
5507 .soclk(soclk)
5508);
5509
5510// BS 03/11/04 extra cycle for mem access
5511
5512l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c52
5513 (.din(ld64_inst_c5), .l1clk(l1clk),
5514 .scan_in(ff_ld64_inst_c52_scanin),
5515 .scan_out(ff_ld64_inst_c52_scanout),
5516 .dout(ld64_inst_c52),
5517 .siclk(siclk),
5518 .soclk(soclk)
5519);
5520
5521
5522l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c6
5523 (.din(ld64_inst_c52), .l1clk(l1clk),
5524 .scan_in(ff_ld64_inst_c6_scanin),
5525 .scan_out(ff_ld64_inst_c6_scanout),
5526 .dout(ld64_inst_c6),
5527 .siclk(siclk),
5528 .soclk(soclk)
5529);
5530
5531l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c7
5532 (.din(ld64_inst_c6), .l1clk(l1clk),
5533 .scan_in(ff_ld64_inst_c7_scanin),
5534 .scan_out(ff_ld64_inst_c7_scanout),
5535 .dout(ld64_inst_c7),
5536 .siclk(siclk),
5537 .soclk(soclk)
5538);
5539
5540
5541assign misbuf_mark_mcu_rdy_c3 = ( misbuf_mark_evict_tmp_c3 &
5542 ~wr64_inst_c3 & // do not set EVICT for a wr64 instruction
5543 ~arb_decdp_cas2_from_mb_c3 &
5544 ~arb_vuad_ce_err_c3 & // a VUAD CE will gate setting of EVICT
5545 ~tag_misbuf_par_err_c3 // a par err will gate setting of EVICT
5546 & ~arb_pf_ice_inst_c3) ;
5547
5548l2t_misbuf_ctl_msff_ctl_macro__width_2 ff_mcu_rdy_c4
5549 (.din({misbuf_mark_mcu_rdy_c3,arb_decdp_cas2_from_mb_c2}), .l1clk(l1clk),
5550 .scan_in(ff_mcu_rdy_c4_scanin),
5551 .scan_out(ff_mcu_rdy_c4_scanout),
5552 .dout({mcu_rdy_c4,arb_decdp_cas2_from_mb_c3}),
5553 .siclk(siclk),
5554 .soclk(soclk)
5555);
5556
5557l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_rdy_c5
5558 (.din(mcu_rdy_c4), .l1clk(l1clk),
5559 .scan_in(ff_mcu_rdy_c5_scanin),
5560 .scan_out(ff_mcu_rdy_c5_scanout),
5561 .dout(mcu_rdy_c5),
5562 .siclk(siclk),
5563 .soclk(soclk)
5564);
5565
5566// BS 03/11/04 extra cycle for mem access
5567
5568l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_rdy_c52
5569 (.din(mcu_rdy_c5), .l1clk(l1clk),
5570 .scan_in(ff_mcu_rdy_c52_scanin),
5571 .scan_out(ff_mcu_rdy_c52_scanout),
5572 .dout(mcu_rdy_c52),
5573 .siclk(siclk),
5574 .soclk(soclk)
5575);
5576
5577
5578l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_rdy_c6
5579 (.din(mcu_rdy_c52), .l1clk(l1clk),
5580 .scan_in(ff_mcu_rdy_c6_scanin),
5581 .scan_out(ff_mcu_rdy_c6_scanout),
5582 .dout(mcu_rdy_c6),
5583 .siclk(siclk),
5584 .soclk(soclk)
5585);
5586
5587l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_rdy_c7
5588 (.din(mcu_rdy_c6), .l1clk(l1clk),
5589 .scan_in(ff_mcu_rdy_c7_scanin),
5590 .scan_out(ff_mcu_rdy_c7_scanout),
5591 .dout(mcu_rdy_c7),
5592 .siclk(siclk),
5593 .soclk(soclk)
5594);
5595
5596l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_rdy_c8
5597 (.din(mcu_rdy_c7), .l1clk(l1clk),
5598 .scan_in(ff_mcu_rdy_c8_scanin),
5599 .scan_out(ff_mcu_rdy_c8_scanout),
5600 .dout(mcu_rdy_c8),
5601 .siclk(siclk),
5602 .soclk(soclk)
5603);
5604
5605
5606// If an eviction packet encounters a tag parity error or VUAD CE,
5607// the EVICT bit needs to be set again so that the instruction
5608// can make an eviction pass after the tag/vuad array has been
5609// repaired.
5610//
5611// Similarly if an evict packet is issued with tecc=1
5612// the evict_ready bit needs to be set again for that packet.
5613// Both the above cases are covered in the expression for
5614// evict_par_vuad_ce_err_c3
5615
5616
5617l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_par_err_c3
5618 (.din(arb_evict_tecc_vld_c2), .l1clk(l1clk),
5619 .scan_in(ff_evict_par_err_c3_scanin),
5620 .scan_out(ff_evict_par_err_c3_scanout),
5621 .dout(evict_tecc_vld_c3),
5622 .siclk(siclk),
5623 .soclk(soclk)
5624);
5625
5626
5627assign evict_par_vuad_ce_err_c3 = (evict_vld_unqual_c3 & (arb_vuad_ce_err_c3 |
5628 tag_misbuf_par_err_c3)) | evict_tecc_vld_c3;
5629
5630l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_par_err_c4
5631 (
5632 .scan_in(ff_evict_par_err_c4_scanin),
5633 .scan_out(ff_evict_par_err_c4_scanout),
5634 .din(evict_par_vuad_ce_err_c3),
5635 .l1clk(l1clk),
5636 .dout(evict_par_err_c4),
5637 .siclk(siclk),
5638 .soclk(soclk)
5639 );
5640
5641l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_par_err_c5
5642 (.din(evict_par_err_c4), .l1clk(l1clk),
5643 .scan_in(ff_evict_par_err_c5_scanin),
5644 .scan_out(ff_evict_par_err_c5_scanout),
5645 .dout(evict_par_err_c5),
5646 .siclk(siclk),
5647 .soclk(soclk)
5648);
5649
5650// BS 03/11/04 extra cycle for mem access
5651
5652l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_par_err_c52
5653 (.din(evict_par_err_c5), .l1clk(l1clk),
5654 .scan_in(ff_evict_par_err_c52_scanin),
5655 .scan_out(ff_evict_par_err_c52_scanout),
5656 .dout(evict_par_err_c52),
5657 .siclk(siclk),
5658 .soclk(soclk)
5659);
5660
5661
5662l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_par_err_c6
5663 (.din(evict_par_err_c52), .l1clk(l1clk),
5664 .scan_in(ff_evict_par_err_c6_scanin),
5665 .scan_out(ff_evict_par_err_c6_scanout),
5666 .dout(evict_par_err_c6),
5667 .siclk(siclk),
5668 .soclk(soclk)
5669);
5670
5671l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_par_err_c7
5672 (.din(evict_par_err_c6), .l1clk(l1clk),
5673 .scan_in(ff_evict_par_err_c7_scanin),
5674 .scan_out(ff_evict_par_err_c7_scanout),
5675 .dout(evict_par_err_c7),
5676 .siclk(siclk),
5677 .soclk(soclk)
5678);
5679
5680
5681// all ld64 are no_fill instructions.
5682
5683// The following expression for the EVICT bit is used for
5684// causing an eviction pass. It is not used for making a
5685// request to DRAM. Hence, if we want to turn off the eviction
5686// pass while not turning off requests to DRAM, this is the place
5687// to do it.
5688
5689assign misbuf_evict_nopfice_c7 = ( mcu_rdy_c7
5690 & ~ld64_inst_c7 // LD 64 no fill
5691 & ~l2_bypass_mode_on_d1) // L2 off
5692 | evict_par_err_c7 ;
5693
5694assign misbuf_evict_c7 = misbuf_evict_nopfice_c7 | arb_pf_ice_inst_c7;
5695
5696l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_evict_c8
5697 (.din(misbuf_evict_c7), .l1clk(l1clk),
5698 .scan_in(ff_misbuf_evict_c8_scanin),
5699 .scan_out(ff_misbuf_evict_c8_scanout),
5700 .dout(misbuf_evict_c8),
5701 .siclk(siclk),
5702 .soclk(soclk)
5703);
5704
5705//////////////////////////////////////////////////////////////////////////////
5706// The Code in this section handles a RDMA instruction completion.
5707// i.e. if an instruction is not able to complete because of
5708// "rdma_reg_vld" being high, this logic will enable the READY
5709// condition for such an instruction that gets inserted in
5710// the Miss Buffer.
5711//
5712//
5713// Completion of a wr64 is signalled if it misses
5714// everything ( $, FB WBB and RDMAT). Remember that
5715// the tag_miss_unqual_c2 is already qualified with
5716// ~tag_rdma_reg_vld so completion is actually off
5717// when that signal is high.
5718//////////////////////////////////////////////////////////////////////////////
5719// int 5.0 changes
5720// removed the tag_misbuf_par_err_c3 for timing reasons.
5721// THe following signal will be transmitted to tagctl
5722// where it is used after qualification with *par_err_c3.
5723assign misbuf_wr64_miss_comp_c3 = misbuf_mark_evict_tmp_c3 &
5724 wr64_inst_c3 ;
5725
5726l2t_misbuf_ctl_msff_ctl_macro__width_7 ff_buffer_miss_vld_c3
5727 (.din({buffer_miss_vld_c2,buffer_miss_vld_c3,buffer_miss_vld_c4,
5728 buffer_miss_vld_c5,buffer_miss_vld_c52,buffer_miss_vld_c6,
5729 buffer_miss_vld_c7}), .l1clk(l1clk),
5730 .scan_in(ff_buffer_miss_vld_c3_scanin),
5731 .scan_out(ff_buffer_miss_vld_c3_scanout),
5732 .dout({buffer_miss_vld_c3,buffer_miss_vld_c4,buffer_miss_vld_c5,buffer_miss_vld_c52,
5733 buffer_miss_vld_c6,buffer_miss_vld_c7,buffer_miss_vld_c8}),
5734 .siclk(siclk),
5735 .soclk(soclk)
5736);
5737
5738l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_reg_vld_c3
5739 (.din(tag_misbuf_rdma_reg_vld_c2), .l1clk(l1clk),
5740 .scan_in(ff_rdma_reg_vld_c3_scanin),
5741 .scan_out(ff_rdma_reg_vld_c3_scanout),
5742 .dout(rdma_reg_vld_c3),
5743 .siclk(siclk),
5744 .soclk(soclk)
5745);
5746
5747assign wr64_miss_not_comp_c3 = buffer_miss_vld_c3 &
5748 tag_alt_tag_miss_unqual_c3 &
5749 ~tag_misbuf_par_err_c3 &
5750 ~arb_vuad_ce_err_c3 &
5751 wr64_inst_c3 &
5752 rdma_reg_vld_c3;
5753
5754assign rdma_comp_rdy_c3 = ( wr64_miss_not_comp_c3 | tag_hit_not_comp_c3 ) ;
5755
5756l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_comp_rdy_c4
5757 (.din(rdma_comp_rdy_c3), .l1clk(l1clk),
5758 .scan_in(ff_rdma_comp_rdy_c4_scanin),
5759 .scan_out(ff_rdma_comp_rdy_c4_scanout),
5760 .dout(rdma_comp_rdy_c4),
5761 .siclk(siclk),
5762 .soclk(soclk)
5763);
5764
5765l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_comp_rdy_c5
5766 (.din(rdma_comp_rdy_c4), .l1clk(l1clk),
5767 .scan_in(ff_rdma_comp_rdy_c5_scanin),
5768 .scan_out(ff_rdma_comp_rdy_c5_scanout),
5769 .dout(rdma_comp_rdy_c5),
5770 .siclk(siclk),
5771 .soclk(soclk)
5772);
5773
5774// BS 03/11/04 extra cycle for mem access
5775
5776l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_comp_rdy_c52
5777 (.din(rdma_comp_rdy_c5), .l1clk(l1clk),
5778 .scan_in(ff_rdma_comp_rdy_c52_scanin),
5779 .scan_out(ff_rdma_comp_rdy_c52_scanout),
5780 .dout(rdma_comp_rdy_c52),
5781 .siclk(siclk),
5782 .soclk(soclk)
5783);
5784
5785
5786l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_comp_rdy_c6
5787 (.din(rdma_comp_rdy_c52), .l1clk(l1clk),
5788 .scan_in(ff_rdma_comp_rdy_c6_scanin),
5789 .scan_out(ff_rdma_comp_rdy_c6_scanout),
5790 .dout(rdma_comp_rdy_c6),
5791 .siclk(siclk),
5792 .soclk(soclk)
5793);
5794
5795l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_comp_rdy_c7
5796 (.din(rdma_comp_rdy_c6), .l1clk(l1clk),
5797 .scan_in(ff_rdma_comp_rdy_c7_scanin),
5798 .scan_out(ff_rdma_comp_rdy_c7_scanout),
5799 .dout(rdma_comp_rdy_c7),
5800 .siclk(siclk),
5801 .soclk(soclk)
5802);
5803
5804l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdma_comp_rdy_c8
5805 (.din(rdma_comp_rdy_c7), .l1clk(l1clk),
5806 .scan_in(ff_rdma_comp_rdy_c8_scanin),
5807 .scan_out(ff_rdma_comp_rdy_c8_scanout),
5808 .dout(rdma_comp_rdy_c8),
5809 .siclk(siclk),
5810 .soclk(soclk)
5811);
5812
5813//////////////////////////////////////////////////////////////////////////////
5814// TECC bit in MBdata:
5815// The TECC bit is set in mbdata if a tag parity is encountered for an
5816// instruction that writes/rewrites into the miss Buffer.
5817// This bit is used to cause a scrub when the instruction is reissued.
5818//////////////////////////////////////////////////////////////////////////////
5819
5820
5821assign misbuf_tecc_c3 = tag_misbuf_par_err_c3 &
5822 ~tag_hit_unqual_c3 &
5823 buffer_miss_vld_c3; // a hit in any of the buffers
5824 // triggers an alternate ready mechanism
5825 // that might set L2 ready
5826 // Hence, tecc_ready setting needs to
5827 // be disabled in this case.
5828
5829l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_tecc_c4
5830 (.din(misbuf_tecc_c3), .l1clk(l1clk),
5831 .scan_in(ff_misbuf_tecc_c4_scanin),
5832 .scan_out(ff_misbuf_tecc_c4_scanout),
5833 .dout(misbuf_tecc_c4),
5834 .siclk(siclk),
5835 .soclk(soclk)
5836);
5837
5838l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_tecc_c5
5839 (.din(misbuf_tecc_c4), .l1clk(l1clk),
5840 .scan_in(ff_misbuf_tecc_c5_scanin),
5841 .scan_out(ff_misbuf_tecc_c5_scanout),
5842 .dout(misbuf_tecc_c5),
5843 .siclk(siclk),
5844 .soclk(soclk)
5845);
5846
5847// BS 03/11/04 extra cycle for mem access
5848
5849l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_tecc_c52
5850 (.din(misbuf_tecc_c5), .l1clk(l1clk),
5851 .scan_in(ff_misbuf_tecc_c52_scanin),
5852 .scan_out(ff_misbuf_tecc_c52_scanout),
5853 .dout(misbuf_tecc_c52),
5854 .siclk(siclk),
5855 .soclk(soclk)
5856);
5857
5858
5859l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_tecc_c6
5860 (.din(misbuf_tecc_c52), .l1clk(l1clk),
5861 .scan_in(ff_misbuf_tecc_c6_scanin),
5862 .scan_out(ff_misbuf_tecc_c6_scanout),
5863 .dout(misbuf_tecc_c6),
5864 .siclk(siclk),
5865 .soclk(soclk)
5866);
5867
5868l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_tecc_c7
5869 (.din(misbuf_tecc_c6), .l1clk(l1clk),
5870 .scan_in(ff_misbuf_tecc_c7_scanin),
5871 .scan_out(ff_misbuf_tecc_c7_scanout),
5872 .dout(misbuf_tecc_c7),
5873 .siclk(siclk),
5874 .soclk(soclk)
5875);
5876
5877l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_tecc_c8
5878 (.din(misbuf_tecc_c7), .l1clk(l1clk),
5879 .scan_in(ff_misbuf_tecc_c8_scanin),
5880 .scan_out(ff_misbuf_tecc_c8_scanout),
5881 .dout(misbuf_tecc_c8),
5882 .siclk(siclk),
5883 .soclk(soclk)
5884);
5885
5886///////////////////////////////////////////////////////
5887// VALID bit : set on insertion and reset on deletion
5888///////////////////////////////////////////////////////
5889
5890// BS & SR 11/04/03, MB grows to 32
5891l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_write_ptr_c3 // sync reset active low
5892 (.din(mb_write_ptr_c2[31:0]), .l1clk(l1clk),
5893 .scan_in(ff_mb_write_ptr_c3_scanin),
5894 .scan_out(ff_mb_write_ptr_c3_scanout),
5895 .clr(~dbb_rst_l),
5896 .dout(mb_write_ptr_c3[31:0]),
5897 .siclk(siclk),
5898 .soclk(soclk)
5899);
5900
5901assign mb_tag_wr_wl_c3 = mb_write_ptr_c3 & {32{mbf_insert_c3}} ; // BS & SR 11/04/03, MB grows to 32
5902assign mb_tag_wr_wl_c3_tmp = mb_write_ptr_c3 & {32{mbf_insert_c3_tmp}} ; // BS & SR 11/04/03, MB grows to 32
5903
5904l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_mb_entry_c3 // BS & SR 11/04/03, MB grows to 32
5905 (.din(inst_mb_entry_c2[4:0]), .l1clk(l1clk),
5906 .scan_in(ff_mb_entry_c3_scanin),
5907 .scan_out(ff_mb_entry_c3_scanout),
5908 .dout(mb_entry_c3[4:0]),
5909 .siclk(siclk),
5910 .soclk(soclk)
5911);
5912
5913l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_mb_entry_c3_1 // BS & SR 11/04/03, MB grows to 32
5914 (.din(inst_mb_entry_c2[4:0]), .l1clk(l1clk),
5915 .scan_in(ff_mb_entry_c3_1_scanin),
5916 .scan_out(ff_mb_entry_c3_1_scanout),
5917 .dout(mb_entry_c3_1[4:0]),
5918 .siclk(siclk),
5919 .soclk(soclk)
5920);
5921
5922assign dec_mb_entry_c3[0] = ( mb_entry_c3_1 == 5'd0 ) ;
5923assign dec_mb_entry_c3[1] = ( mb_entry_c3_1 == 5'd1 ) ;
5924assign dec_mb_entry_c3[2] = ( mb_entry_c3_1 == 5'd2 ) ;
5925assign dec_mb_entry_c3[3] = ( mb_entry_c3_1 == 5'd3 ) ;
5926assign dec_mb_entry_c3[4] = ( mb_entry_c3_1 == 5'd4 ) ;
5927assign dec_mb_entry_c3[5] = ( mb_entry_c3_1 == 5'd5 ) ;
5928assign dec_mb_entry_c3[6] = ( mb_entry_c3_1 == 5'd6 ) ;
5929assign dec_mb_entry_c3[7] = ( mb_entry_c3_1 == 5'd7 ) ;
5930assign dec_mb_entry_c3[8] = ( mb_entry_c3_1 == 5'd8 ) ;
5931assign dec_mb_entry_c3[9] = ( mb_entry_c3_1 == 5'd9 ) ;
5932assign dec_mb_entry_c3[10] = ( mb_entry_c3_1 == 5'd10 ) ;
5933assign dec_mb_entry_c3[11] = ( mb_entry_c3_1 == 5'd11 ) ;
5934assign dec_mb_entry_c3[12] = ( mb_entry_c3_1 == 5'd12 ) ;
5935assign dec_mb_entry_c3[13] = ( mb_entry_c3_1 == 5'd13 ) ;
5936assign dec_mb_entry_c3[14] = ( mb_entry_c3_1 == 5'd14 ) ;
5937assign dec_mb_entry_c3[15] = ( mb_entry_c3_1 == 5'd15 ) ;
5938
5939// BS & SR 11/04/03, MB grows to 32
5940assign dec_mb_entry_c3[16] = ( mb_entry_c3_1 == 5'd16) ;
5941assign dec_mb_entry_c3[17] = ( mb_entry_c3_1 == 5'd17) ;
5942assign dec_mb_entry_c3[18] = ( mb_entry_c3_1 == 5'd18) ;
5943assign dec_mb_entry_c3[19] = ( mb_entry_c3_1 == 5'd19) ;
5944assign dec_mb_entry_c3[20] = ( mb_entry_c3_1 == 5'd20) ;
5945assign dec_mb_entry_c3[21] = ( mb_entry_c3_1 == 5'd21) ;
5946assign dec_mb_entry_c3[22] = ( mb_entry_c3_1 == 5'd22) ;
5947assign dec_mb_entry_c3[23] = ( mb_entry_c3_1 == 5'd23) ;
5948assign dec_mb_entry_c3[24] = ( mb_entry_c3_1 == 5'd24) ;
5949assign dec_mb_entry_c3[25] = ( mb_entry_c3_1 == 5'd25) ;
5950assign dec_mb_entry_c3[26] = ( mb_entry_c3_1 == 5'd26) ;
5951assign dec_mb_entry_c3[27] = ( mb_entry_c3_1 == 5'd27) ;
5952assign dec_mb_entry_c3[28] = ( mb_entry_c3_1 == 5'd28) ;
5953assign dec_mb_entry_c3[29] = ( mb_entry_c3_1 == 5'd29) ;
5954assign dec_mb_entry_c3[30] = ( mb_entry_c3_1 == 5'd30) ;
5955assign dec_mb_entry_c3[31] = ( mb_entry_c3_1 == 5'd31) ;
5956
5957// Used by filbuf since this is the same as fill entry.
5958assign reset_valid_bit_c3 = ( dec_mb_entry_c3 & {32{mbf_delete_c3}} ) ; // BS & SR 11/04/03, MB grows to 32
5959assign mb_valid_prev = ( mb_tag_wr_wl_c3 | mb_valid ) & ~reset_valid_bit_c3 ;
5960
5961// BS & SR 11/04/03, MB grows to 32
5962l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_valid_bit // sync reset active low
5963 (.din(mb_valid_prev[31:0]), .l1clk(l1clk),
5964 .scan_in(ff_valid_bit_scanin),
5965 .scan_out(ff_valid_bit_scanout),
5966 .clr(~dbb_rst_l), .dout(mb_valid[31:0]),
5967 .siclk(siclk),
5968 .soclk(soclk)
5969);
5970
5971//assign mb_valid_stall_pfice_c3 = |(mb_valid[31:0]);
5972
5973
5974///////////////////////////////////////////////////////
5975// RDMA bit : set on insertion of a RDMA instruction
5976// and reset on deletion
5977// used only for purposes of picking an instruction
5978// in the Miss Buffer.
5979///////////////////////////////////////////////////////
5980
5981
5982assign mb_rdma_prev = (( mb_tag_wr_wl_c3 & {32{rdma_inst_c3}} ) |
5983 mb_rdma ) & ~reset_valid_bit_c3 ;
5984// BS & SR 11/04/03, MB grows to 32
5985l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_rdma_bit // sync reset active low
5986 (.din(mb_rdma_prev[31:0]), .l1clk(l1clk),
5987 .scan_in(ff_rdma_bit_scanin),
5988 .scan_out(ff_rdma_bit_scanout),
5989 .clr(~dbb_rst_l), .dout(mb_rdma[31:0]),
5990 .siclk(siclk),
5991 .soclk(soclk)
5992);
5993
5994
5995///////////////////////////////////////////////////////
5996// BIS bit : set on insertion of a BIS instruction
5997// and reset on deletion
5998// used to assert a dummy request to DRAM
5999///////////////////////////////////////////////////////
6000
6001assign mb_bis_prev = (( mb_tag_wr_wl_c3 & {32{arb_decdp_bis_inst_c3}} )
6002 | mb_bis ) & ~reset_valid_bit_c3 ;
6003
6004// BS & SR 11/04/03, MB grows to 32
6005l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_bis_bit // sync reset active low
6006 (.din(mb_bis_prev[31:0]), .l1clk(l1clk),
6007 .scan_in(ff_bis_bit_scanin),
6008 .scan_out(ff_bis_bit_scanout),
6009 .clr(~dbb_rst_l), .dout(mb_bis[31:0]),
6010 .siclk(siclk),
6011 .soclk(soclk)
6012);
6013
6014
6015//////////////////////////////////////////////////////////////////////////
6016// DRAM READY bit : set on insertion/reinsertion
6017// of all cases of "true miss" in C8, other than a Prefetch ICE.
6018// and reset on a PICK for mcu issue.
6019// The reason the mcu_ready bit is set in C7 is as follows:
6020//
6021// ------------------------------------------------------------------------
6022// #1 #2(C8) #3(C9) #4((c10) #5(c11)
6023// ------------------------------------------------------------------------
6024// mcu_ready mcu_pick_prev mcu_pick read req
6025// set
6026// write
6027// fbtag.
6028// other
6029// fb fields.
6030// --------------------------------------------------------------------------
6031// fbtagecc and other fields of fb come from mbdata.
6032// mbdata gets written in c9. Hence it cannot be read before
6033// c10.
6034// This required cycle #4 to correspond to c10.
6035//////////////////////////////////////////////////////////////////////////
6036
6037// BS 06/24/04 : Support for Prefetch ICE.
6038// Have to squash the DRAM read on a Prefetch ICE. Prefetch ICE should
6039// miss in L2 tags , and get inserted in the Miss Buffer , but should
6040// not assert a DRAM read request. It should cause the eviction pass
6041// to happen using the way from PA[21:18] of the instruction itself.
6042// In the eviction pass, the miss buffer entry will get deleted .
6043// However if there is a tag parity error during the Prefetch ICE
6044// first pass, the Prefetch ICE will get inserted into the miss buffer
6045// , but the DRMA ready bit will not be set as usual. The evict_rdy
6046// bit will not be set due to the tag parity error.
6047// Then a scrub will be issued from the Miss Buffer and when it finishes,
6048// it will ready the Prefetch ICE and this time it will miss cleanly, and
6049// follow normal behavior for Prefetch ICE. This has to be verified with
6050// directed diags
6051
6052// Also in case of VUAD CE have to disable the MCU request
6053// as we do not know if it is a valid hit or miss.
6054
6055l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_arb_pf_ice_inst_c8
6056 (.din(arb_pf_ice_inst_c7), .l1clk(l1clk),
6057 .scan_in(ff_arb_pf_ice_inst_c8_scanin),
6058 .scan_out(ff_arb_pf_ice_inst_c8_scanout),
6059 .dout(arb_pf_ice_inst_c8),
6060 .siclk(siclk),
6061 .soclk(soclk)
6062 );
6063
6064//
6065// In case both tag parity error and VUAD CE happen for the same
6066// instruction and it is a tag miss, the mcu ready bit will be set as it gets set on a regular tag parity error
6067// However the L2 ready bit will not be set in C9 but will be set after the scrub
6068// itself. Hence we need to gate off the setting of arb_vuad_ce_err_c3 by not of
6069// tag_misbuf_par_err_c3 so that we get the behv of L2 ready and MCU ready same
6070// as if only tag parity error occured.
6071// In case of a tag hit, have to process the instruction as if a VUAD ecc error
6072// has happened, i.e put it in the miss buffer and replay from it. The tag parity
6073// error on a tag hit means the parity bit itself is in error , the instruction
6074// normally would just finish in the pipe. So if a VUAD ecc error also happened,
6075// have to move it to miss buffer and replay from there.
6076
6077assign arb_vuad_ce_err_c3_tmp = ~(tag_misbuf_par_err_c3 & ~tag_hit_unqual_c3 ) & arb_vuad_ce_err_c3 ;
6078
6079l2t_misbuf_ctl_msff_ctl_macro__width_7 ff_arb_vuad_ce_err_slice
6080 (.din({arb_vuad_ce_err_c3_tmp,arb_vuad_ce_err_c4,arb_vuad_ce_err_c5,arb_vuad_ce_err_c52,
6081 arb_vuad_ce_err_c6,arb_vuad_ce_err_c7,misbuf_tag_hit_unqual_c2_internal}),
6082 .scan_in(ff_arb_vuad_ce_err_slice_scanin),
6083 .scan_out(ff_arb_vuad_ce_err_slice_scanout),
6084 .dout({arb_vuad_ce_err_c4,arb_vuad_ce_err_c5,arb_vuad_ce_err_c52,arb_vuad_ce_err_c6,
6085 arb_vuad_ce_err_c7,arb_vuad_ce_err_c8,misbuf_hit_unqual_c3}),
6086 .l1clk(l1clk),
6087 .siclk(siclk),
6088 .soclk(soclk)
6089 );
6090
6091assign misbuf_vuad_ce_err_c6 = arb_vuad_ce_err_c6 ; // vuad ecc change
6092
6093//// For vuad ecc ce
6094
6095assign reset_vuad_ce_replay[31:0] = ({32{~arb_vuad_ce_err_c3_tmp & mbissue_inst_vld_c3}} & dec_mb_entry_c3);
6096
6097// in case of a dependant insertion to miss buffer , do not set the ce_replay bit if there is a vuad ce
6098// this is because the replay of the dependant should only happen after its dependancy has cleared
6099// and not before that. Replaying before the dependancy has been cleared , might have the dependant
6100// hit in the tag or fill buffer and the dependant might complete before the instruction it is
6101// dependant on. Also vuad_ce_err_rdy[31:0] will not be set for a dependant insertion to miss buffer
6102// with vuad ce.
6103
6104assign tag_misbuf_ack_c3 = ( tag_misbuf_int_ack_c3 &
6105 ((~inst_mb_c3 & ~misbuf_hit_unqual_c3) |
6106 (~inst_mb_c3 &
6107 (misbuf_hit_st_dep_zero & tag_store_inst_c3 & ~filbuf_match_c3)) | dep_inst_c3 ));
6108
6109
6110assign vuad_ce_replay_in[31:0] = (({32{arb_vuad_ce_err_c3_tmp & ~mbissue_inst_vld_c3 & mbf_insert_c3 & buffer_miss_vld_c3}}
6111 & mb_write_ptr_c3 ) |
6112 ({32{arb_vuad_ce_err_c3_tmp & mbissue_inst_vld_c3 & buffer_miss_vld_c3}}
6113 & dec_mb_entry_c3) |
6114 vuad_ce_replay) &
6115 ~(reset_vuad_ce_replay);
6116
6117assign vuad_ack_pending_in[31:0] = (({32{tag_misbuf_ack_c3 & arb_vuad_ce_err_c3_tmp & ~mbissue_inst_vld_c3 & mbf_insert_c3 &
6118 buffer_miss_vld_c3}}
6119 & mb_write_ptr_c3 ) |
6120 ({32{tag_misbuf_ack_c3 & arb_vuad_ce_err_c3_tmp & mbissue_inst_vld_c3 & buffer_miss_vld_c3}}
6121 & dec_mb_entry_c3) |
6122 vuad_ack_pending) &
6123 ~(reset_vuad_ce_replay);
6124
6125
6126
6127l2t_misbuf_ctl_msff_ctl_macro__width_65 ff_vuad_ce_replay
6128 (
6129 .scan_in(ff_vuad_ce_replay_scanin),
6130 .scan_out(ff_vuad_ce_replay_scanout),
6131 .din({vuad_ce_replay_in[31:0],mbissue_inst_vld_c2,vuad_ack_pending_in[31:0]}),
6132 .l1clk(l1clk),
6133 .dout({vuad_ce_replay[31:0],mbissue_inst_vld_c3,vuad_ack_pending[31:0]}),
6134 .siclk(siclk),
6135 .soclk(soclk)
6136 );
6137
6138//assign misbuf_vuad_ce_instr_c2 = |({32{arb_misbuf_inst_vld_c2}} & vuad_ce_replay & ~mb_l2_ready);
6139assign misbuf_vuad_ce_instr_c2 = |({32{arb_misbuf_inst_vld_c2 & arbdec_arbdp_inst_mb_c2}} &
6140 dec_mb_entry_c2 & vuad_ce_replay & ~mb_l2_ready);
6141
6142assign misbuf_vuad_ce_instr_ack_c2 = |({32{arb_misbuf_inst_vld_c2 & arbdec_arbdp_inst_mb_c2}} &
6143 dec_mb_entry_c2 & vuad_ce_replay & vuad_ack_pending & ~mb_l2_ready);
6144
6145//////
6146
6147// VUAD ecc changes
6148 assign mcu_ready_set_c8 = ( insert_ptr_c8 & {32{misbuf_mbdata_wr_en_c8 & ~arb_pf_ice_inst_c8 &
6149 ~arb_vuad_ce_err_c8 & mcu_rdy_c8}} ) ; // BS & SR 11/04/03, MB grows to 32
6150
6151 assign reset_mcu_ready = ( picker_out & {32{mcu_pick}} ) ; // BS & SR 11/04/03, MB grows to 32
6152
6153 assign mb_mcu_ready_in = ( mb_mcu_ready | mcu_ready_set_c8 ) &
6154 ~( reset_mcu_ready ) ;
6155
6156l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mcu_ready_bit // sync reset active low, BS & SR 11/04/03, MB grows to 32
6157 (.din(mb_mcu_ready_in[31:0]), .l1clk(l1clk),
6158 .scan_in(ff_mcu_ready_bit_scanin),
6159 .scan_out(ff_mcu_ready_bit_scanout),
6160 .clr(~dbb_rst_l), .dout(mb_mcu_ready[31:0]),
6161 .siclk(siclk),
6162 .soclk(soclk)
6163);
6164
6165
6166
6167
6168/////////////////////////////////////////////////////////////////
6169// YOUNG bit : Denotes the Youngest MB entry for that address.
6170//
6171// Set in the C3 cycle of non-dependent insertion and reset
6172// in the C3 cycle of an instruction hitting a young miss Buffer
6173// entry.Also reset on dequeue.
6174//
6175/////////////////////////////////////////////////////////////////
6176
6177assign mb_young_prev = ( mb_tag_wr_wl_c3 | mb_young ) &
6178 ~( misbuf_hit_vec_c3 | reset_valid_bit_c3 ) ;
6179
6180l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_young_bit // sync reset active low. // BS & SR 11/04/03, MB grows to 32
6181 (.din(mb_young_prev[31:0]), .l1clk(l1clk),
6182 .scan_in(ff_young_bit_scanin),
6183 .scan_out(ff_young_bit_scanout),
6184 .clr(~dbb_rst_l), .dout(mb_young[31:0]),
6185 .siclk(siclk),
6186 .soclk(soclk)
6187);
6188
6189/////////////////////////////////////////////////////////////////
6190// NEXT LINK Field : Denotes the next(agewise) dependent's miss buffer
6191// ID.
6192//
6193// Set in the C3 cycle of dependents insertion into the Miss Buffer.
6194// However next link is set for the older entry and not for the inserting
6195// entry.
6196/////////////////////////////////////////////////////////////////
6197
6198assign next_link_wr_en_c3 = mb_young & misbuf_hit_vec_c3;
6199
6200// BS & SR 11/04/03, MB grows to 32
6201l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link0
6202 (.din(enc_tag_wr_wl_c3[4:0]),
6203 .scan_in(ff_next_link0_scanin),
6204 .scan_out(ff_next_link0_scanout),
6205 .en(next_link_wr_en_c3[0]),
6206 .l1clk(l1clk), .dout(next_link_entry0[4:0]),
6207 .siclk(siclk),
6208 .soclk(soclk)
6209
6210);
6211l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link1
6212 (.din(enc_tag_wr_wl_c3[4:0]),
6213 .scan_in(ff_next_link1_scanin),
6214 .scan_out(ff_next_link1_scanout),
6215 .en(next_link_wr_en_c3[1]),
6216 .l1clk(l1clk), .dout(next_link_entry1[4:0]),
6217 .siclk(siclk),
6218 .soclk(soclk)
6219
6220);
6221l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link2
6222 (.din(enc_tag_wr_wl_c3[4:0]),
6223 .scan_in(ff_next_link2_scanin),
6224 .scan_out(ff_next_link2_scanout),
6225 .en(next_link_wr_en_c3[2]),
6226 .l1clk(l1clk), .dout(next_link_entry2[4:0]),
6227 .siclk(siclk),
6228 .soclk(soclk)
6229
6230);
6231l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link3
6232 (.din(enc_tag_wr_wl_c3[4:0]),
6233 .scan_in(ff_next_link3_scanin),
6234 .scan_out(ff_next_link3_scanout),
6235 .en(next_link_wr_en_c3[3]),
6236 .l1clk(l1clk), .dout(next_link_entry3[4:0]),
6237 .siclk(siclk),
6238 .soclk(soclk)
6239
6240);
6241l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link4
6242 (.din(enc_tag_wr_wl_c3[4:0]),
6243 .scan_in(ff_next_link4_scanin),
6244 .scan_out(ff_next_link4_scanout),
6245 .en(next_link_wr_en_c3[4]),
6246 .l1clk(l1clk), .dout(next_link_entry4[4:0]),
6247 .siclk(siclk),
6248 .soclk(soclk)
6249
6250);
6251l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link5
6252 (.din(enc_tag_wr_wl_c3[4:0]),
6253 .scan_in(ff_next_link5_scanin),
6254 .scan_out(ff_next_link5_scanout),
6255 .en(next_link_wr_en_c3[5]),
6256 .l1clk(l1clk), .dout(next_link_entry5[4:0]),
6257 .siclk(siclk),
6258 .soclk(soclk)
6259
6260);
6261l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link6
6262 (.din(enc_tag_wr_wl_c3[4:0]),
6263 .scan_in(ff_next_link6_scanin),
6264 .scan_out(ff_next_link6_scanout),
6265 .en(next_link_wr_en_c3[6]),
6266 .l1clk(l1clk), .dout(next_link_entry6[4:0]),
6267 .siclk(siclk),
6268 .soclk(soclk)
6269
6270);
6271l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link7
6272 (.din(enc_tag_wr_wl_c3[4:0]),
6273 .scan_in(ff_next_link7_scanin),
6274 .scan_out(ff_next_link7_scanout),
6275 .en(next_link_wr_en_c3[7]),
6276 .l1clk(l1clk), .dout(next_link_entry7[4:0]),
6277 .siclk(siclk),
6278 .soclk(soclk)
6279
6280);
6281l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link8
6282 (.din(enc_tag_wr_wl_c3[4:0]),
6283 .scan_in(ff_next_link8_scanin),
6284 .scan_out(ff_next_link8_scanout),
6285 .en(next_link_wr_en_c3[8]),
6286 .l1clk(l1clk), .dout(next_link_entry8[4:0]),
6287 .siclk(siclk),
6288 .soclk(soclk)
6289
6290);
6291l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link9
6292 (.din(enc_tag_wr_wl_c3[4:0]),
6293 .scan_in(ff_next_link9_scanin),
6294 .scan_out(ff_next_link9_scanout),
6295 .en(next_link_wr_en_c3[9]),
6296 .l1clk(l1clk), .dout(next_link_entry9[4:0]),
6297 .siclk(siclk),
6298 .soclk(soclk)
6299
6300);
6301l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link10
6302 (.din(enc_tag_wr_wl_c3[4:0]),
6303 .scan_in(ff_next_link10_scanin),
6304 .scan_out(ff_next_link10_scanout),
6305 .en(next_link_wr_en_c3[10]),
6306 .l1clk(l1clk), .dout(next_link_entry10[4:0]),
6307 .siclk(siclk),
6308 .soclk(soclk)
6309
6310);
6311l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link11
6312 (.din(enc_tag_wr_wl_c3[4:0]),
6313 .scan_in(ff_next_link11_scanin),
6314 .scan_out(ff_next_link11_scanout),
6315 .en(next_link_wr_en_c3[11]),
6316 .l1clk(l1clk), .dout(next_link_entry11[4:0]),
6317 .siclk(siclk),
6318 .soclk(soclk)
6319
6320);
6321l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link12
6322 (.din(enc_tag_wr_wl_c3[4:0]),
6323 .scan_in(ff_next_link12_scanin),
6324 .scan_out(ff_next_link12_scanout),
6325 .en(next_link_wr_en_c3[12]),
6326 .l1clk(l1clk), .dout(next_link_entry12[4:0]),
6327 .siclk(siclk),
6328 .soclk(soclk)
6329
6330);
6331l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link13
6332 (.din(enc_tag_wr_wl_c3[4:0]),
6333 .scan_in(ff_next_link13_scanin),
6334 .scan_out(ff_next_link13_scanout),
6335 .en(next_link_wr_en_c3[13]),
6336 .l1clk(l1clk), .dout(next_link_entry13[4:0]),
6337 .siclk(siclk),
6338 .soclk(soclk)
6339
6340);
6341l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link14
6342 (.din(enc_tag_wr_wl_c3[4:0]),
6343 .scan_in(ff_next_link14_scanin),
6344 .scan_out(ff_next_link14_scanout),
6345 .en(next_link_wr_en_c3[14]),
6346 .l1clk(l1clk), .dout(next_link_entry14[4:0]),
6347 .siclk(siclk),
6348 .soclk(soclk)
6349
6350);
6351l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link15
6352 (.din(enc_tag_wr_wl_c3[4:0]),
6353 .scan_in(ff_next_link15_scanin),
6354 .scan_out(ff_next_link15_scanout),
6355 .en(next_link_wr_en_c3[15]),
6356 .l1clk(l1clk), .dout(next_link_entry15[4:0]),
6357 .siclk(siclk),
6358 .soclk(soclk)
6359
6360);
6361
6362// BS & SR 11/04/03, MB grows to 32
6363l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link16
6364 (
6365 .scan_in(ff_next_link16_scanin),
6366 .scan_out(ff_next_link16_scanout),
6367 .din(enc_tag_wr_wl_c3[4:0]),
6368 .en(next_link_wr_en_c3[16]),
6369 .l1clk(l1clk),
6370 .dout(next_link_entry16[4:0]),
6371 .siclk(siclk),
6372 .soclk(soclk)
6373
6374);
6375
6376l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link17
6377 (
6378 .scan_in(ff_next_link17_scanin),
6379 .scan_out(ff_next_link17_scanout),
6380 .din(enc_tag_wr_wl_c3[4:0]),
6381 .en(next_link_wr_en_c3[17]),
6382 .l1clk(l1clk),
6383 .dout(next_link_entry17[4:0]),
6384 .siclk(siclk),
6385 .soclk(soclk)
6386
6387);
6388
6389l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link18
6390 (
6391 .scan_in(ff_next_link18_scanin),
6392 .scan_out(ff_next_link18_scanout),
6393 .din(enc_tag_wr_wl_c3[4:0]),
6394 .en(next_link_wr_en_c3[18]),
6395 .l1clk(l1clk),
6396 .dout(next_link_entry18[4:0]),
6397 .siclk(siclk),
6398 .soclk(soclk)
6399
6400);
6401
6402l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link19
6403 (
6404 .scan_in(ff_next_link19_scanin),
6405 .scan_out(ff_next_link19_scanout),
6406 .din(enc_tag_wr_wl_c3[4:0]),
6407 .en(next_link_wr_en_c3[19]),
6408 .l1clk(l1clk),
6409 .dout(next_link_entry19[4:0]),
6410 .siclk(siclk),
6411 .soclk(soclk)
6412
6413);
6414
6415l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link20
6416 (
6417 .scan_in(ff_next_link20_scanin),
6418 .scan_out(ff_next_link20_scanout),
6419 .din(enc_tag_wr_wl_c3[4:0]),
6420 .en(next_link_wr_en_c3[20]),
6421 .l1clk(l1clk),
6422 .dout(next_link_entry20[4:0]),
6423 .siclk(siclk),
6424 .soclk(soclk)
6425
6426);
6427
6428l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link21
6429 (
6430 .scan_in(ff_next_link21_scanin),
6431 .scan_out(ff_next_link21_scanout),
6432 .din(enc_tag_wr_wl_c3[4:0]),
6433 .en(next_link_wr_en_c3[21]),
6434 .l1clk(l1clk),
6435 .dout(next_link_entry21[4:0]),
6436 .siclk(siclk),
6437 .soclk(soclk)
6438
6439);
6440
6441
6442l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link22
6443 (
6444 .scan_in(ff_next_link22_scanin),
6445 .scan_out(ff_next_link22_scanout),
6446 .din(enc_tag_wr_wl_c3[4:0]),
6447 .en(next_link_wr_en_c3[22]),
6448 .l1clk(l1clk),
6449 .dout(next_link_entry22[4:0]),
6450 .siclk(siclk),
6451 .soclk(soclk)
6452
6453);
6454
6455l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link23
6456 (
6457 .scan_in(ff_next_link23_scanin),
6458 .scan_out(ff_next_link23_scanout),
6459 .din(enc_tag_wr_wl_c3[4:0]),
6460 .en(next_link_wr_en_c3[23]),
6461 .l1clk(l1clk),
6462 .dout(next_link_entry23[4:0]),
6463 .siclk(siclk),
6464 .soclk(soclk)
6465
6466);
6467
6468
6469l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link24
6470 (
6471 .scan_in(ff_next_link24_scanin),
6472 .scan_out(ff_next_link24_scanout),
6473 .din(enc_tag_wr_wl_c3[4:0]),
6474 .en(next_link_wr_en_c3[24]),
6475 .l1clk(l1clk),
6476 .dout(next_link_entry24[4:0]),
6477 .siclk(siclk),
6478 .soclk(soclk)
6479
6480);
6481
6482
6483l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link25
6484 (
6485 .scan_in(ff_next_link25_scanin),
6486 .scan_out(ff_next_link25_scanout),
6487 .din(enc_tag_wr_wl_c3[4:0]),
6488 .en(next_link_wr_en_c3[25]),
6489 .l1clk(l1clk),
6490 .dout(next_link_entry25[4:0]),
6491 .siclk(siclk),
6492 .soclk(soclk)
6493
6494);
6495
6496
6497l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link26
6498 (
6499 .scan_in(ff_next_link26_scanin),
6500 .scan_out(ff_next_link26_scanout),
6501 .din(enc_tag_wr_wl_c3[4:0]),
6502 .en(next_link_wr_en_c3[26]),
6503 .l1clk(l1clk),
6504 .dout(next_link_entry26[4:0]),
6505 .siclk(siclk),
6506 .soclk(soclk)
6507
6508);
6509
6510
6511l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link27
6512 (
6513 .scan_in(ff_next_link27_scanin),
6514 .scan_out(ff_next_link27_scanout),
6515 .din(enc_tag_wr_wl_c3[4:0]),
6516 .en(next_link_wr_en_c3[27]),
6517 .l1clk(l1clk),
6518 .dout(next_link_entry27[4:0]),
6519 .siclk(siclk),
6520 .soclk(soclk)
6521
6522);
6523
6524
6525l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link28
6526 (
6527 .scan_in(ff_next_link28_scanin),
6528 .scan_out(ff_next_link28_scanout),
6529 .din(enc_tag_wr_wl_c3[4:0]),
6530 .en(next_link_wr_en_c3[28]),
6531 .l1clk(l1clk),
6532 .dout(next_link_entry28[4:0]),
6533 .siclk(siclk),
6534 .soclk(soclk)
6535
6536);
6537
6538
6539l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link29
6540 (
6541 .scan_in(ff_next_link29_scanin),
6542 .scan_out(ff_next_link29_scanout),
6543 .din(enc_tag_wr_wl_c3[4:0]),
6544 .en(next_link_wr_en_c3[29]),
6545 .l1clk(l1clk),
6546 .dout(next_link_entry29[4:0]),
6547 .siclk(siclk),
6548 .soclk(soclk)
6549
6550);
6551
6552l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link30
6553 (
6554 .scan_in(ff_next_link30_scanin),
6555 .scan_out(ff_next_link30_scanout),
6556 .din(enc_tag_wr_wl_c3[4:0]),
6557 .en(next_link_wr_en_c3[30]),
6558 .l1clk(l1clk),
6559 .dout(next_link_entry30[4:0]),
6560 .siclk(siclk),
6561 .soclk(soclk)
6562
6563);
6564
6565l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_next_link31
6566 (
6567 .scan_in(ff_next_link31_scanin),
6568 .scan_out(ff_next_link31_scanout),
6569 .din(enc_tag_wr_wl_c3[4:0]),
6570 .en(next_link_wr_en_c3[31]),
6571 .l1clk(l1clk),
6572 .dout(next_link_entry31[4:0]),
6573 .siclk(siclk),
6574 .soclk(soclk)
6575
6576);
6577
6578
6579////////////////////////////////////////////////////////////////////
6580// CTRUE bit : Denotes "final" pass for a partial store/swap/ldstub
6581// and "store" for a CAS2 instruction in the miss buffer.
6582// - This bit is set in the C8 cycle of a parital store hitting
6583// the $ for the inserting/resinserting entry in C8.
6584// If there is a UE/Notdata error, the bit will still be set
6585// but the write will be disabled in the final pass.
6586// - Also set in C8 of a CAS1 packet hitting in the cache/fb
6587// if the compare operation is true.But this bit is set
6588// for the Miss Buffer entry of the CAS2 dependent of the
6589// CAS1 packet and not for the CAS1 packet itself.
6590// If CAS1 encounters UE,CE,Notdata , this bit will not be
6591// set indicating there will still be a CAS2 pass but the
6592// write to the cache will be disabled.
6593// If CAS1 is issued from the Miss Buffer, the CTRUE bit is set for
6594// its miss buffer dependent.
6595// If CAS1 is issued from the IQ, The CTRUE bit is set for the
6596// miss buffer entry of the instruction that is following 2 cycles
6597// after.
6598////////////////////////////////////////////////////////////////////
6599
6600l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c4
6601 (.din(inst_mb_c3), .l1clk(l1clk),
6602 .scan_in(ff_inst_mb_c4_scanin),
6603 .scan_out(ff_inst_mb_c4_scanout),
6604 .dout(inst_mb_c4),
6605 .siclk(siclk),
6606 .soclk(soclk)
6607);
6608
6609l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c5
6610 (.din(inst_mb_c4), .l1clk(l1clk),
6611 .scan_in(ff_inst_mb_c5_scanin),
6612 .scan_out(ff_inst_mb_c5_scanout),
6613 .dout(tag_inst_mb_c5),
6614 .siclk(siclk),
6615 .soclk(soclk)
6616);
6617
6618// BS 03/11/04 extra cycle for mem access
6619
6620l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c52
6621 (.din(tag_inst_mb_c5), .l1clk(l1clk),
6622 .scan_in(ff_inst_mb_c52_scanin),
6623 .scan_out(ff_inst_mb_c52_scanout),
6624 .dout(tag_inst_mb_c52),
6625 .siclk(siclk),
6626 .soclk(soclk)
6627);
6628
6629
6630l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c6
6631 (.din(tag_inst_mb_c52), .l1clk(l1clk),
6632 .scan_in(ff_inst_mb_c6_scanin),
6633 .scan_out(ff_inst_mb_c6_scanout),
6634 .dout(inst_mb_c6),
6635 .siclk(siclk),
6636 .soclk(soclk)
6637);
6638
6639l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c7
6640 (.din(inst_mb_c6), .l1clk(l1clk),
6641 .scan_in(ff_inst_mb_c7_scanin),
6642 .scan_out(ff_inst_mb_c7_scanout),
6643 .dout(inst_mb_c7),
6644 .siclk(siclk),
6645 .soclk(soclk)
6646);
6647
6648l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c8
6649 (.din(inst_mb_c7), .l1clk(l1clk),
6650 .scan_in(ff_inst_mb_c8_scanin),
6651 .scan_out(ff_inst_mb_c8_scanout),
6652 .dout(inst_mb_c8),
6653 .siclk(siclk),
6654 .soclk(soclk)
6655);
6656
6657
6658l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_mb_c9
6659 (.din(inst_mb_c8), .l1clk(l1clk),
6660 .scan_in(ff_inst_mb_c9_scanin),
6661 .scan_out(ff_inst_mb_c9_scanout),
6662 .dout(inst_mb_c9),
6663 .siclk(siclk),
6664 .soclk(soclk)
6665);
6666
6667l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_enc_data_wr_wl_c7_1
6668 (.din(enc_data_wr_wl_c6[4:0]), .l1clk(l1clk),
6669 .scan_in(ff_enc_data_wr_wl_c7_1_scanin),
6670 .scan_out(ff_enc_data_wr_wl_c7_1_scanout),
6671 .dout(enc_data_wr_wl_c7_1[4:0]),
6672 .siclk(siclk),
6673 .soclk(soclk)
6674);
6675
6676l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 mux_ctrue_entry
6677 (.dout(misbuf_ctrue_rdy_entry[4:0]),
6678 .din0(enc_data_wr_wl_c9[4:0]),// cas1 from mb contains cas2(dep) id
6679 .din1(enc_data_wr_wl_c7_1[4:0]), // cas1 from IQ. contains cas2 id
6680 .sel0(inst_mb_c9),
6681 .sel1(~inst_mb_c9));
6682
6683// In case of cas instruction encountering an vuad error
6684// do not set the ctrue bit in the same pass as the cas will
6685// be replayed
6686
6687assign set_arb_misbuf_cas1_hit_c8 = arb_misbuf_cas1_hit_c8 & ~arb_vuad_ce_err_c8;
6688
6689l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_cas1_hit_c9
6690 (.din(set_arb_misbuf_cas1_hit_c8), .l1clk(l1clk),
6691 .scan_in(ff_cas1_hit_c9_scanin),
6692 .scan_out(ff_cas1_hit_c9_scanout),
6693 .dout(cas1_hit_c9),
6694 .siclk(siclk),
6695 .soclk(soclk)
6696);
6697
6698
6699 assign cas_rdy_set_c9[0] = ( misbuf_ctrue_rdy_entry == 5'd0 ) & cas1_hit_c9;
6700 assign cas_rdy_set_c9[1] = ( misbuf_ctrue_rdy_entry == 5'd1 ) & cas1_hit_c9;
6701 assign cas_rdy_set_c9[2] = ( misbuf_ctrue_rdy_entry == 5'd2 ) & cas1_hit_c9;
6702 assign cas_rdy_set_c9[3] = ( misbuf_ctrue_rdy_entry == 5'd3 ) & cas1_hit_c9;
6703 assign cas_rdy_set_c9[4] = ( misbuf_ctrue_rdy_entry == 5'd4 ) & cas1_hit_c9;
6704 assign cas_rdy_set_c9[5] = ( misbuf_ctrue_rdy_entry == 5'd5 ) & cas1_hit_c9;
6705 assign cas_rdy_set_c9[6] = ( misbuf_ctrue_rdy_entry == 5'd6 ) & cas1_hit_c9;
6706 assign cas_rdy_set_c9[7] = ( misbuf_ctrue_rdy_entry == 5'd7 ) & cas1_hit_c9;
6707 assign cas_rdy_set_c9[8] = ( misbuf_ctrue_rdy_entry == 5'd8 ) & cas1_hit_c9;
6708 assign cas_rdy_set_c9[9] = ( misbuf_ctrue_rdy_entry == 5'd9 ) & cas1_hit_c9;
6709 assign cas_rdy_set_c9[10] = ( misbuf_ctrue_rdy_entry == 5'd10 ) & cas1_hit_c9;
6710 assign cas_rdy_set_c9[11] = ( misbuf_ctrue_rdy_entry == 5'd11 ) & cas1_hit_c9;
6711 assign cas_rdy_set_c9[12] = ( misbuf_ctrue_rdy_entry == 5'd12 ) & cas1_hit_c9;
6712 assign cas_rdy_set_c9[13] = ( misbuf_ctrue_rdy_entry == 5'd13 ) & cas1_hit_c9;
6713 assign cas_rdy_set_c9[14] = ( misbuf_ctrue_rdy_entry == 5'd14 ) & cas1_hit_c9;
6714 assign cas_rdy_set_c9[15] = ( misbuf_ctrue_rdy_entry == 5'd15 ) & cas1_hit_c9;
6715// BS & SR 11/04/03, MB grows to 32
6716 assign cas_rdy_set_c9[16] = ( misbuf_ctrue_rdy_entry == 5'd16 ) & cas1_hit_c9;
6717 assign cas_rdy_set_c9[17] = ( misbuf_ctrue_rdy_entry == 5'd17 ) & cas1_hit_c9;
6718 assign cas_rdy_set_c9[18] = ( misbuf_ctrue_rdy_entry == 5'd18 ) & cas1_hit_c9;
6719 assign cas_rdy_set_c9[19] = ( misbuf_ctrue_rdy_entry == 5'd19 ) & cas1_hit_c9;
6720 assign cas_rdy_set_c9[20] = ( misbuf_ctrue_rdy_entry == 5'd20 ) & cas1_hit_c9;
6721 assign cas_rdy_set_c9[21] = ( misbuf_ctrue_rdy_entry == 5'd21 ) & cas1_hit_c9;
6722 assign cas_rdy_set_c9[22] = ( misbuf_ctrue_rdy_entry == 5'd22 ) & cas1_hit_c9;
6723 assign cas_rdy_set_c9[23] = ( misbuf_ctrue_rdy_entry == 5'd23 ) & cas1_hit_c9;
6724 assign cas_rdy_set_c9[24] = ( misbuf_ctrue_rdy_entry == 5'd24 ) & cas1_hit_c9;
6725 assign cas_rdy_set_c9[25] = ( misbuf_ctrue_rdy_entry == 5'd25 ) & cas1_hit_c9;
6726 assign cas_rdy_set_c9[26] = ( misbuf_ctrue_rdy_entry == 5'd26 ) & cas1_hit_c9;
6727 assign cas_rdy_set_c9[27] = ( misbuf_ctrue_rdy_entry == 5'd27 ) & cas1_hit_c9;
6728 assign cas_rdy_set_c9[28] = ( misbuf_ctrue_rdy_entry == 5'd28 ) & cas1_hit_c9;
6729 assign cas_rdy_set_c9[29] = ( misbuf_ctrue_rdy_entry == 5'd29 ) & cas1_hit_c9;
6730 assign cas_rdy_set_c9[30] = ( misbuf_ctrue_rdy_entry == 5'd30 ) & cas1_hit_c9;
6731 assign cas_rdy_set_c9[31] = ( misbuf_ctrue_rdy_entry == 5'd31 ) & cas1_hit_c9;
6732
6733
6734l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_uncorr_err_c9
6735 (.din(deccck_uncorr_err_c8), .l1clk(l1clk),
6736 .scan_in(ff_uncorr_err_c9_scanin),
6737 .scan_out(ff_uncorr_err_c9_scanout),
6738 .dout(uncorr_err_c9),
6739 .siclk(siclk),
6740 .soclk(soclk)
6741);
6742
6743// BS 06/13/04 added Notdata logic
6744l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_notdata_err_c9
6745 (.din(deccck_notdata_err_c8), .l1clk(l1clk),
6746 .scan_in(ff_notdata_err_c9_scanin),
6747 .scan_out(ff_notdata_err_c9_scanout),
6748 .dout(notdata_err_c9),
6749 .siclk(siclk),
6750 .soclk(soclk)
6751);
6752
6753
6754l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_corr_err_c9
6755 // (.din(deccck_corr_err_c8), .l1clk(l1clk),
6756 (.din(misbuf_corr_err_c8), .l1clk(l1clk),
6757 .scan_in(ff_corr_err_c9_scanin),
6758 .scan_out(ff_corr_err_c9_scanout),
6759 .dout(corr_err_c9),
6760 .siclk(siclk),
6761 .soclk(soclk)
6762);
6763
6764l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_inst_bufidhi_c9
6765 (.din(arbdec_arbdp_inst_bufidhi_c8), .l1clk(l1clk),
6766 .scan_in(ff_inst_bufidhi_c9_scanin),
6767 .scan_out(ff_inst_bufidhi_c9_scanout),
6768 .dout(arbdec_arbdp_inst_bufidhi_c9),
6769 .siclk(siclk),
6770 .soclk(soclk)
6771);
6772
6773assign cas_ctrue_set_preerror_c9 = cas_rdy_set_c9; // BS 04/0/4/05 : fix for bug 90935
6774 // in case of cas1 always use the cas_rdy bits to set
6775 // mb_corr_err or mb_uncorr_err irrespective of the
6776 // ctrue bit. This is because even if the ctrue bit is 0 (miscompare)
6777 // or ctrue is not set because of error, we want to report
6778 // the error in cas ack pass.
6779
6780
6781
6782assign cas_ctrue_set_c9 = cas_rdy_set_c9 & // BS & SR 11/04/03, MB grows to 32
6783 ({32{arbdec_arbdp_inst_bufidhi_c9}} | // if bit 116 of PCX packet (bufidhi bit) = 1'b1, force the
6784 // compare to be true and during CAS2 phase have to write
6785 // Notdata into L2, BS 06/13/04. Notdata gets written by
6786 // inverting the ecc bits of the CAS2 store data in c1 phase
6787 // of the CAS2 pass . Ecc bits of both 4 byte chunks get
6788 // flipped irrespective of whether it is a low cas, high cas
6789 // or whole cas.
6790 {32{arb_misbuf_ctrue_c9 & // compare is true
6791 ~notdata_err_c9 & ~uncorr_err_c9}}) ; // no UE or Notdata in the read.
6792
6793assign pst_ctrue_set_c8 = insert_ptr_c8 & {32{arb_pst_ctrue_en_c8}} ; // BS & SR 11/04/03, MB grows to 32
6794
6795assign mb_ctrue_prev = ( (pst_ctrue_set_c8 & ~{32{misbuf_vuad_ce_err_c8}}) | // pst ctrue set if no vuad error
6796 cas_ctrue_set_c9 | // cas2 ctrue.
6797 mb_ctrue ) &
6798 ~reset_valid_bit_c3 ;
6799
6800l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_ctrue_bit // sync reset active low // BS & SR 11/04/03, MB grows to 32
6801 (.din(mb_ctrue_prev[31:0]), .l1clk(l1clk),
6802 .scan_in(ff_ctrue_bit_scanin),
6803 .scan_out(ff_ctrue_bit_scanout),
6804 .clr(~dbb_rst_l), .dout(mb_ctrue[31:0]),
6805 .siclk(siclk),
6806 .soclk(soclk)
6807);
6808
6809
6810//////////////////////////////////////////////////////////////////////////////
6811// Miss Buffer ID to the Fill Buffer: The ID( mbf entry #) of a miss buffer
6812// instruction is written into the Fill Buffer in the following cases
6813// 1) INstruction from the miss buffer is deleted due to a Fill Buffer hit
6814// and hence the dependent instruction's ID is written into the FIll Buffer.
6815// 2) Instruction from the IQ hits the Fill Buffer ( and is a non-dependent
6816// instruction ) so its ID is written into the Fill Buffer.
6817// 3) ID of a "true miss" when it requests to DRAM and enqueues in the FB
6818// Here is the Pipeline for case 1 and case 2.
6819//
6820// case 1: The next link mux has to be mbist_done in C3 to
6821// handle the case where a dependent was just issued
6822// from the IQ one cycle before the Miss Buffer
6823// instruction that will complete.
6824//---------------------------------------------
6825// C3 C4 C5
6826//---------------------------------------------
6827// mbf fbf
6828// delete write
6829// nextlink mux
6830//
6831// nextlink vld
6832// logic
6833//------------------------------------
6834//
6835//
6836// case 2
6837//------------------------------------
6838// C4 C5
6839//------------------------------------
6840// mbf insert fbf write
6841//
6842// enc tag wr ptr
6843//----------------------------------------------------------------------------
6844//////////////////////////////////////////////////////////////////////////////
6845
6846// case 2 related control output
6847
6848assign mbf_insert_mbid_c3 = enc_tag_wr_wl_c3 ;
6849
6850l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_mbf_insert_mbid_c4 // BS & SR 11/04/03, MB grows to 32
6851 (.din(mbf_insert_mbid_c3[4:0]), .l1clk(l1clk),
6852 .scan_in(ff_mbf_insert_mbid_c4_scanin),
6853 .scan_out(ff_mbf_insert_mbid_c4_scanout),
6854 .dout(misbuf_mbf_insert_mbid_c4[4:0]),
6855 .siclk(siclk),
6856 .soclk(soclk)
6857);
6858
6859l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_insert_c4
6860 (.din(mbf_insert_c3), .l1clk(l1clk),
6861 .scan_in(ff_mbf_insert_c4_scanin),
6862 .scan_out(ff_mbf_insert_c4_scanout),
6863 .dout(misbuf_mbf_insert_c4),
6864 .siclk(siclk),
6865 .soclk(soclk)
6866);
6867
6868l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_hit_c3
6869 (.din(misbuf_hit_c2), .l1clk(l1clk),
6870 .scan_in(ff_misbuf_hit_c3_scanin),
6871 .scan_out(ff_misbuf_hit_c3_scanout),
6872 .dout(misbuf_hit_c3),
6873 .siclk(siclk),
6874 .soclk(soclk)
6875);
6876
6877//--\/--- ADDED TO FIX bug#4619 -----\/-----------
6878l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_arb_hit_c3 // int 5.0 changes
6879 (.din(misbuf_hit_c2), .l1clk(l1clk),
6880 .scan_in(ff_misbuf_arb_hit_c3_scanin),
6881 .scan_out(ff_misbuf_arb_hit_c3_scanout),
6882 .dout(misbuf_arb_hit_c3),
6883 .siclk(siclk),
6884 .soclk(soclk)
6885);
6886//--\/--- ADDED TO FIX bug#4619 -----\/-----------
6887
6888
6889l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_hit_c4
6890(.din({misbuf_hit_c3}), .l1clk(l1clk),
6891.scan_in(ff_misbuf_hit_c4_scanin),
6892.scan_out(ff_misbuf_hit_c4_scanout),
6893.dout({misbuf_hit_c4}),
6894 .siclk(siclk),
6895 .soclk(soclk)
6896);
6897
6898
6899// Case 1 related.
6900
6901assign misbuf_next_vld_c3 = ( |( dec_mb_entry_c3 & ~mb_young)) &
6902 inst_mb_c3 &
6903 mb_inst_vld_c3_1 ;
6904
6905l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_filbuf_next_vld_c4
6906 (.din(misbuf_next_vld_c3), .l1clk(l1clk),
6907 .scan_in(ff_misbuf_filbuf_next_vld_c4_scanin),
6908 .scan_out(ff_misbuf_filbuf_next_vld_c4_scanout),
6909 .dout(misbuf_filbuf_next_vld_c4),
6910 .siclk(siclk),
6911 .soclk(soclk)
6912);
6913
6914l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mbf_delete_c4
6915 (.din(mbf_delete_c3), .l1clk(l1clk),
6916 .scan_in(ff_mbf_delete_c4_scanin),
6917 .scan_out(ff_mbf_delete_c4_scanout),
6918 .dout(misbuf_mbf_delete_c4),
6919 .siclk(siclk),
6920 .soclk(soclk)
6921);
6922
6923assign sel_0to3 = |( dec_mb_entry_c3[3:0] );
6924assign sel_4to7 = |( dec_mb_entry_c3[7:4] );
6925assign sel_8to11 = |( dec_mb_entry_c3[11:8] );
6926assign sel_12to15 = |( dec_mb_entry_c3[15:12] );
6927// BS & SR 11/04/03, MB grows to 32
6928assign sel_19to16 = |( dec_mb_entry_c3[19:16] );
6929assign sel_23to20 = |( dec_mb_entry_c3[23:20] );
6930assign sel_27to24 = |( dec_mb_entry_c3[27:24] );
6931assign sel_31to28 = |( dec_mb_entry_c3[31:28] );
6932
6933assign sel_default_0123 = ~sel_0to3 | dec_mb_entry_c3[3] ;
6934assign sel_default_4567 = ~sel_4to7 | dec_mb_entry_c3[7] ;
6935assign sel_default_89ab = ~sel_8to11 | dec_mb_entry_c3[11] ;
6936assign sel_default_cdef = ~sel_12to15 | dec_mb_entry_c3[15] ;
6937// BS & SR 11/04/03, MB grows to 32
6938assign sel_default_a_0123 = ~sel_19to16 | dec_mb_entry_c3[19] ;
6939assign sel_default_a_4567 = ~sel_23to20 | dec_mb_entry_c3[23] ;
6940assign sel_default_a_89ab = ~sel_27to24 | dec_mb_entry_c3[27] ;
6941assign sel_default_a_cdef = ~sel_31to28 | dec_mb_entry_c3[31] ;
6942
6943assign sel_default_0to15 = (sel_0to3 | sel_4to7 | sel_8to11 | sel_12to15);
6944assign sel_default_16to31 = ~sel_default_0to15;
6945
6946l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_0123
6947 ( .dout(nextlink_id0123[4:0]),
6948 .din0(next_link_entry0[4:0]), .din1(next_link_entry1[4:0]),
6949 .din2(next_link_entry2[4:0]), .din3(next_link_entry3[4:0]),
6950 .sel0(dec_mb_entry_c3[0]), .sel1(dec_mb_entry_c3[1]),
6951 .sel2(dec_mb_entry_c3[2]), .sel3(sel_default_0123));
6952
6953l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_4567
6954 ( .dout(nextlink_id4567[4:0]),
6955 .din0(next_link_entry4[4:0]), .din1(next_link_entry5[4:0]),
6956 .din2(next_link_entry6[4:0]), .din3(next_link_entry7[4:0]),
6957 .sel0(dec_mb_entry_c3[4]), .sel1(dec_mb_entry_c3[5]),
6958 .sel2(dec_mb_entry_c3[6]), .sel3(sel_default_4567));
6959
6960l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_89ab
6961 ( .dout(nextlink_id89ab[4:0]),
6962 .din0(next_link_entry8[4:0]), .din1(next_link_entry9[4:0]),
6963 .din2(next_link_entry10[4:0]), .din3(next_link_entry11[4:0]),
6964 .sel0(dec_mb_entry_c3[8]), .sel1(dec_mb_entry_c3[9]),
6965 .sel2(dec_mb_entry_c3[10]), .sel3(sel_default_89ab));
6966
6967l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_cdef
6968 (.dout(nextlink_idcdef[4:0]),
6969 .din0(next_link_entry12[4:0]), .din1(next_link_entry13[4:0]),
6970 .din2(next_link_entry14[4:0]), .din3(next_link_entry15[4:0]),
6971 .sel0(dec_mb_entry_c3[12]), .sel1(dec_mb_entry_c3[13]),
6972 .sel2(dec_mb_entry_c3[14]), .sel3(sel_default_cdef));
6973
6974// BS & SR 11/04/03, MB grows to 32
6975
6976l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_a0123
6977 (
6978 .dout(nextlink_ida0123[4:0]),
6979 .din0(next_link_entry16[4:0]),
6980 .din1(next_link_entry17[4:0]),
6981 .din2(next_link_entry18[4:0]),
6982 .din3(next_link_entry19[4:0]),
6983 .sel0(dec_mb_entry_c3[16]),
6984 .sel1(dec_mb_entry_c3[17]),
6985 .sel2(dec_mb_entry_c3[18]),
6986 .sel3(sel_default_a_0123)
6987 );
6988
6989l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_a4567
6990 (
6991 .dout(nextlink_ida4567[4:0]),
6992 .din0(next_link_entry20[4:0]),
6993 .din1(next_link_entry21[4:0]),
6994 .din2(next_link_entry22[4:0]),
6995 .din3(next_link_entry23[4:0]),
6996 .sel0(dec_mb_entry_c3[20]),
6997 .sel1(dec_mb_entry_c3[21]),
6998 .sel2(dec_mb_entry_c3[22]),
6999 .sel3(sel_default_a_4567)
7000 );
7001
7002l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_a89ab
7003 (
7004 .dout(nextlink_ida89ab[4:0]),
7005 .din0(next_link_entry24[4:0]),
7006 .din1(next_link_entry25[4:0]),
7007 .din2(next_link_entry26[4:0]),
7008 .din3(next_link_entry27[4:0]),
7009 .sel0(dec_mb_entry_c3[24]),
7010 .sel1(dec_mb_entry_c3[25]),
7011 .sel2(dec_mb_entry_c3[26]),
7012 .sel3(sel_default_a_89ab)
7013 );
7014l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_nextlink_acdef
7015 (
7016 .dout(nextlink_idacdef[4:0]),
7017 .din0(next_link_entry28[4:0]),
7018 .din1(next_link_entry29[4:0]),
7019 .din2(next_link_entry30[4:0]),
7020 .din3(next_link_entry31[4:0]),
7021 .sel0(dec_mb_entry_c3[28]),
7022 .sel1(dec_mb_entry_c3[29]),
7023 .sel2(dec_mb_entry_c3[30]),
7024 .sel3(sel_default_a_cdef)
7025 );
7026
7027l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_next_link_c3_a
7028 (.dout(misbuf_next_link_a_c3[4:0]),
7029 .din0(nextlink_id0123[4:0]), .din1(nextlink_id4567[4:0]),
7030 .din2(nextlink_id89ab[4:0]), .din3(nextlink_idcdef[4:0]),
7031 .sel0(sel_0to3),
7032 .sel1(sel_4to7),
7033 .sel2(sel_8to11),
7034 .sel3(sel_12to15));
7035
7036l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_next_link_c3_b
7037 (.dout(misbuf_next_link_b_c3[4:0]),
7038 .din0(nextlink_ida0123[4:0]), .din1(nextlink_ida4567[4:0]),
7039 .din2(nextlink_ida89ab[4:0]), .din3(nextlink_idacdef[4:0]),
7040 .sel0(sel_19to16),
7041 .sel1(sel_23to20),
7042 .sel2(sel_27to24),
7043 .sel3(sel_31to28));
7044
7045l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 mux_next_link_c3
7046 (.dout(misbuf_next_link_c3[4:0]),
7047 .din0(misbuf_next_link_a_c3[4:0]),
7048 .din1(misbuf_next_link_b_c3[4:0]),
7049 .sel0(sel_default_0to15),
7050 .sel1(sel_default_16to31)
7051 );
7052
7053
7054l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_misbuf_filbuf_next_link_c4 // BS & SR 11/04/03, MB grows to 32
7055 (.din(misbuf_next_link_c3[4:0]), .l1clk(l1clk),
7056 .scan_in(ff_misbuf_filbuf_next_link_c4_scanin),
7057 .scan_out(ff_misbuf_filbuf_next_link_c4_scanout),
7058 .dout(misbuf_filbuf_next_link_c4[4:0]),
7059 .siclk(siclk),
7060 .soclk(soclk)
7061);
7062
7063
7064
7065//////////////////////////////////////////////////////////////////////////////
7066// MB_DATA_VLD in misbuf: A zero in this bit for a valid instruction is
7067// used to indicate that the instruction is inflight
7068// and even if READY=1 , it cannot be picked for issue.
7069//////////////////////////////////////////////////////////////////////////////
7070
7071assign mb_data_vld_in = (( insert_ptr_c8 & {32{misbuf_mbdata_wr_en_c8}} ) | // BS & SR 11/04/03, MB grows to 32
7072 mb_data_vld ) &
7073 ~( picker_out_d1 & {32{l2_pick_d1}} ) ; // reset on pick
7074
7075
7076
7077l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_data_vld // sync reset active low , BS & SR 11/04/03, MB grows to 32
7078 (.din(mb_data_vld_in[31:0]), .l1clk(l1clk),
7079 .scan_in(ff_mb_data_vld_scanin),
7080 .scan_out(ff_mb_data_vld_scanout),
7081 .clr(~dbb_rst_l), .dout(mb_data_vld[31:0]),
7082 .siclk(siclk),
7083 .soclk(soclk)
7084);
7085
7086
7087//////////////////////////////////////////////////////////////////////////////
7088// EVICT READY bit in Mbctl: THis is a duplicate of the evict bit
7089// written into mbdata. USed for
7090// * Picking instructions for their eviction pass.
7091// * Potentially disable the pick of evict ready entries
7092// when the WBB is full thereby removing the WBB full condition
7093// from the arbiter.
7094// Notice that tecc pick has a higher priority than an evict pick.
7095// A mb_tecc_ready pick was originally designed not to reset the evict_ready
7096// bit. However, if evict_ready & tecc_ready, we can reset both the ready bits
7097// because, the tecc&evict instruction will cause a scrub and also cause evict_ready
7098// to be set again.
7099//////////////////////////////////////////////////////////////////////////////
7100// for a pf ice in first pass do not set this evict ready till the
7101// requests pending in mb is processed.
7102
7103
7104assign misbuf_evict_qual_c7 = misbuf_evict_nopfice_c7;
7105
7106l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_gate_evict_set_staging
7107 (
7108 .scan_in(ff_gate_evict_set_staging_scanin),
7109 .scan_out(ff_gate_evict_set_staging_scanout),
7110 .din(misbuf_evict_qual_c7),
7111 .l1clk(l1clk),
7112 .dout(misbuf_evict_c8_pfice_qual),
7113 .siclk(siclk),
7114 .soclk(soclk)
7115 );
7116
7117
7118assign mb_evict_ready_in = (( insert_ptr_c8 & {32{misbuf_evict_c8_pfice_qual}}) |
7119 pfice_inst_rdy | mb_evict_ready ) &
7120 ~( picker_out_d1 & {32{l2_pick_d1}} ) ; // BS & SR 11/04/03, MB grows to 32
7121 // reset on pick
7122
7123l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_evict_ready // sync reset active low , BS & SR 11/04/03, MB grows to 32
7124 (.din(mb_evict_ready_in[31:0]), .l1clk(l1clk),
7125 .scan_in(ff_mb_evict_ready_scanin),
7126 .scan_out(ff_mb_evict_ready_scanout),
7127 .clr(~dbb_rst_l), .dout(mb_evict_ready[31:0]),
7128 .siclk(siclk),
7129 .soclk(soclk)
7130);
7131
7132//////////////////////////////////////////////////////////////////////////////
7133// TECC READY bit in Mbctl: THis is a duplicate of the tecc bit
7134// written into mbdata. USed for
7135// * Picking instructions for their tecc pass.
7136// Tecc pick has a higher priority than an evict pick.
7137// Notice that all TECCs do not cause the setting of a TECC bit in the $.
7138// If an instruction gets bypassed data from the Fill Buffer, the tecc is
7139// a don't care. ALso, a parity error will not be signalled if a hit
7140// is encountered inspite of a parity error in another way
7141//////////////////////////////////////////////////////////////////////////////
7142
7143assign mb_tecc_ready_in = (( insert_ptr_c8 & {32{misbuf_tecc_c8
7144 & misbuf_mbdata_wr_en_c8 }}) |
7145 mb_tecc_ready ) & // BS & SR 11/04/03, MB grows to 32
7146 ~( picker_out_d1 & {32{l2_pick_d1}} ) ; // reset on pick
7147
7148l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_tecc_ready // sync reset active low
7149 (.din(mb_tecc_ready_in[31:0]), .l1clk(l1clk),
7150 .scan_in(ff_mb_tecc_ready_scanin),
7151 .scan_out(ff_mb_tecc_ready_scanout),
7152 .clr(~dbb_rst_l), .dout(mb_tecc_ready[31:0]),
7153 .siclk(siclk),
7154 .soclk(soclk)
7155);
7156
7157//////////////////////////////////////////////////////////////////////////////
7158// L2_READY in misbuf: This bit is set for any instruction in the mBF that is
7159// ready for issue/reissue down the L2 pipeline. the READY bit for an
7160// entry is reset when that entry is "l2 picked". The following
7161// components go into the L2_READY set condition.
7162// * Misses Readied on mcu data arrival by the FIll Buffer.
7163// * Stores/ Miss Buffer dependents readied on a Fill by the
7164// Fill Buffer ( Readied in the C4 cycle of a FILL ).
7165// * Miss Buffer dependents readied when the older instruction
7166// dequeues from the Miss Buffer. ( in the C4 stage of the older inst.)
7167// * WBB dependents readied when the Write back is acked by DRAM/BTU
7168// * Ready a CSR instruction when the FIll Buffer is empty and the mIss Buffer
7169// has only one entry available.
7170// * Ready a Partial store for its 2nd pass if the 1st pass is able to
7171// set the CTRUE bit.
7172// * Ready a CAS2 packet if the CAS1 packet hits the $ or FB after the
7173// first packet has reached C8.
7174// * Ready a STQ2 packet if the STQ1 packet hits the $ or FB after the
7175// first packet has reached C4
7176// * Ready a tecc instruction in C8
7177//////////////////////////////////////////////////////////////////////////////
7178
7179//////
7180// Misses Readied on mcu data arrival by the FIll Buffer
7181//--------------------------------------
7182// R1 R2
7183//------------------------------------
7184// rd_data_vld_d1 ready
7185// dep
7186// mux out
7187// ID of true miss
7188// mbf inst. in
7189// filbuf.
7190//////
7191
7192
7193l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_ready_miss_r2
7194 (.din(filbuf_fbf_ready_miss_r1), .l1clk(l1clk),
7195 .scan_in(ff_ready_miss_r2_scanin),
7196 .scan_out(ff_ready_miss_r2_scanout),
7197 .dout(ready_miss_r2),
7198 .siclk(siclk),
7199 .soclk(soclk)
7200);
7201
7202l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_fbf_enc_ld_mbid_r1 // BS & SR 11/04/03, MB grows to 32
7203 (.din(filbuf_fbf_enc_ld_mbid_r1[4:0]), .l1clk(l1clk),
7204 .scan_in(ff_fbf_enc_ld_mbid_r1_scanin),
7205 .scan_out(ff_fbf_enc_ld_mbid_r1_scanout),
7206 .dout(ld_mbid_r2[4:0]),
7207 .siclk(siclk),
7208 .soclk(soclk)
7209);
7210
7211assign mb_miss_rdy_r2[0] = ( ld_mbid_r2 == 5'd0) & ready_miss_r2 ;
7212assign mb_miss_rdy_r2[1] = ( ld_mbid_r2 == 5'd1) & ready_miss_r2 ;
7213assign mb_miss_rdy_r2[2] = ( ld_mbid_r2 == 5'd2) & ready_miss_r2 ;
7214assign mb_miss_rdy_r2[3] = ( ld_mbid_r2 == 5'd3) & ready_miss_r2 ;
7215assign mb_miss_rdy_r2[4] = ( ld_mbid_r2 == 5'd4) & ready_miss_r2 ;
7216assign mb_miss_rdy_r2[5] = ( ld_mbid_r2 == 5'd5) & ready_miss_r2 ;
7217assign mb_miss_rdy_r2[6] = ( ld_mbid_r2 == 5'd6) & ready_miss_r2 ;
7218assign mb_miss_rdy_r2[7] = ( ld_mbid_r2 == 5'd7) & ready_miss_r2 ;
7219assign mb_miss_rdy_r2[8] = ( ld_mbid_r2 == 5'd8) & ready_miss_r2 ;
7220assign mb_miss_rdy_r2[9] = ( ld_mbid_r2 == 5'd9) & ready_miss_r2 ;
7221assign mb_miss_rdy_r2[10] = ( ld_mbid_r2 == 5'd10) & ready_miss_r2 ;
7222assign mb_miss_rdy_r2[11] = ( ld_mbid_r2 == 5'd11) & ready_miss_r2 ;
7223assign mb_miss_rdy_r2[12] = ( ld_mbid_r2 == 5'd12) & ready_miss_r2 ;
7224assign mb_miss_rdy_r2[13] = ( ld_mbid_r2 == 5'd13) & ready_miss_r2 ;
7225assign mb_miss_rdy_r2[14] = ( ld_mbid_r2 == 5'd14) & ready_miss_r2 ;
7226assign mb_miss_rdy_r2[15] = ( ld_mbid_r2 == 5'd15) & ready_miss_r2 ;
7227// BS & SR 11/04/03, MB grows to 32
7228assign mb_miss_rdy_r2[16] = ( ld_mbid_r2 == 5'd16) & ready_miss_r2 ;
7229assign mb_miss_rdy_r2[17] = ( ld_mbid_r2 == 5'd17) & ready_miss_r2 ;
7230assign mb_miss_rdy_r2[18] = ( ld_mbid_r2 == 5'd18) & ready_miss_r2 ;
7231assign mb_miss_rdy_r2[19] = ( ld_mbid_r2 == 5'd19) & ready_miss_r2 ;
7232assign mb_miss_rdy_r2[20] = ( ld_mbid_r2 == 5'd20) & ready_miss_r2 ;
7233assign mb_miss_rdy_r2[21] = ( ld_mbid_r2 == 5'd21) & ready_miss_r2 ;
7234assign mb_miss_rdy_r2[22] = ( ld_mbid_r2 == 5'd22) & ready_miss_r2 ;
7235assign mb_miss_rdy_r2[23] = ( ld_mbid_r2 == 5'd23) & ready_miss_r2 ;
7236assign mb_miss_rdy_r2[24] = ( ld_mbid_r2 == 5'd24) & ready_miss_r2 ;
7237assign mb_miss_rdy_r2[25] = ( ld_mbid_r2 == 5'd25) & ready_miss_r2 ;
7238assign mb_miss_rdy_r2[26] = ( ld_mbid_r2 == 5'd26) & ready_miss_r2 ;
7239assign mb_miss_rdy_r2[27] = ( ld_mbid_r2 == 5'd27) & ready_miss_r2 ;
7240assign mb_miss_rdy_r2[28] = ( ld_mbid_r2 == 5'd28) & ready_miss_r2 ;
7241assign mb_miss_rdy_r2[29] = ( ld_mbid_r2 == 5'd29) & ready_miss_r2 ;
7242assign mb_miss_rdy_r2[30] = ( ld_mbid_r2 == 5'd30) & ready_miss_r2 ;
7243assign mb_miss_rdy_r2[31] = ( ld_mbid_r2 == 5'd31) & ready_miss_r2 ;
7244
7245
7246
7247//////
7248// Stores/ Miss Buffer dependents in FB
7249// readied in the C5 cycle of a Fill
7250//--------------------------------------
7251// C4 C5
7252//------------------------------------
7253// fill_complete_c4 ready
7254// dep
7255// mux out
7256// ID of dependent
7257// mbf inst. in
7258// filbuf.
7259//////
7260
7261
7262l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbf_st_or_dep_rdy_c5
7263 (.din(filbuf_fbf_st_or_dep_rdy_c4), .l1clk(l1clk),
7264 .scan_in(ff_fbf_st_or_dep_rdy_c5_scanin),
7265 .scan_out(ff_fbf_st_or_dep_rdy_c5_scanout),
7266 .dout(st_or_dep_rdy_c5),
7267 .siclk(siclk),
7268 .soclk(soclk)
7269);
7270
7271l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_fbf_enc_dep_mbid_c5 // BS & SR 11/04/03, MB grows to 32
7272 (.din(filbuf_fbf_enc_dep_mbid_c4[4:0]), .l1clk(l1clk),
7273 .scan_in(ff_fbf_enc_dep_mbid_c5_scanin),
7274 .scan_out(ff_fbf_enc_dep_mbid_c5_scanout),
7275 .dout(dep_mbid_c5[4:0]),
7276 .siclk(siclk),
7277 .soclk(soclk)
7278);
7279
7280
7281
7282assign fb_dep_rdy_c5[0] = ( dep_mbid_c5 == 5'd0) & st_or_dep_rdy_c5 ;
7283assign fb_dep_rdy_c5[1] = ( dep_mbid_c5 == 5'd1) & st_or_dep_rdy_c5 ;
7284assign fb_dep_rdy_c5[2] = ( dep_mbid_c5 == 5'd2) & st_or_dep_rdy_c5 ;
7285assign fb_dep_rdy_c5[3] = ( dep_mbid_c5 == 5'd3) & st_or_dep_rdy_c5 ;
7286assign fb_dep_rdy_c5[4] = ( dep_mbid_c5 == 5'd4) & st_or_dep_rdy_c5 ;
7287assign fb_dep_rdy_c5[5] = ( dep_mbid_c5 == 5'd5) & st_or_dep_rdy_c5 ;
7288assign fb_dep_rdy_c5[6] = ( dep_mbid_c5 == 5'd6) & st_or_dep_rdy_c5 ;
7289assign fb_dep_rdy_c5[7] = ( dep_mbid_c5 == 5'd7) & st_or_dep_rdy_c5 ;
7290assign fb_dep_rdy_c5[8] = ( dep_mbid_c5 == 5'd8) & st_or_dep_rdy_c5 ;
7291assign fb_dep_rdy_c5[9] = ( dep_mbid_c5 == 5'd9) & st_or_dep_rdy_c5 ;
7292assign fb_dep_rdy_c5[10] = ( dep_mbid_c5 == 5'd10) & st_or_dep_rdy_c5 ;
7293assign fb_dep_rdy_c5[11] = ( dep_mbid_c5 == 5'd11) & st_or_dep_rdy_c5 ;
7294assign fb_dep_rdy_c5[12] = ( dep_mbid_c5 == 5'd12) & st_or_dep_rdy_c5 ;
7295assign fb_dep_rdy_c5[13] = ( dep_mbid_c5 == 5'd13) & st_or_dep_rdy_c5 ;
7296assign fb_dep_rdy_c5[14] = ( dep_mbid_c5 == 5'd14) & st_or_dep_rdy_c5 ;
7297assign fb_dep_rdy_c5[15] = ( dep_mbid_c5 == 5'd15) & st_or_dep_rdy_c5 ;
7298// BS & SR 11/04/03, MB grows to 32
7299assign fb_dep_rdy_c5[16] = ( dep_mbid_c5 == 5'd16) & st_or_dep_rdy_c5 ;
7300assign fb_dep_rdy_c5[17] = ( dep_mbid_c5 == 5'd17) & st_or_dep_rdy_c5 ;
7301assign fb_dep_rdy_c5[18] = ( dep_mbid_c5 == 5'd18) & st_or_dep_rdy_c5 ;
7302assign fb_dep_rdy_c5[19] = ( dep_mbid_c5 == 5'd19) & st_or_dep_rdy_c5 ;
7303assign fb_dep_rdy_c5[20] = ( dep_mbid_c5 == 5'd20) & st_or_dep_rdy_c5 ;
7304assign fb_dep_rdy_c5[21] = ( dep_mbid_c5 == 5'd21) & st_or_dep_rdy_c5 ;
7305assign fb_dep_rdy_c5[22] = ( dep_mbid_c5 == 5'd22) & st_or_dep_rdy_c5 ;
7306assign fb_dep_rdy_c5[23] = ( dep_mbid_c5 == 5'd23) & st_or_dep_rdy_c5 ;
7307assign fb_dep_rdy_c5[24] = ( dep_mbid_c5 == 5'd24) & st_or_dep_rdy_c5 ;
7308assign fb_dep_rdy_c5[25] = ( dep_mbid_c5 == 5'd25) & st_or_dep_rdy_c5 ;
7309assign fb_dep_rdy_c5[26] = ( dep_mbid_c5 == 5'd26) & st_or_dep_rdy_c5 ;
7310assign fb_dep_rdy_c5[27] = ( dep_mbid_c5 == 5'd27) & st_or_dep_rdy_c5 ;
7311assign fb_dep_rdy_c5[28] = ( dep_mbid_c5 == 5'd28) & st_or_dep_rdy_c5 ;
7312assign fb_dep_rdy_c5[29] = ( dep_mbid_c5 == 5'd29) & st_or_dep_rdy_c5 ;
7313assign fb_dep_rdy_c5[30] = ( dep_mbid_c5 == 5'd30) & st_or_dep_rdy_c5 ;
7314assign fb_dep_rdy_c5[31] = ( dep_mbid_c5 == 5'd31) & st_or_dep_rdy_c5 ;
7315
7316
7317
7318//////
7319// Miss Buffer dependents READY:
7320//--------------------------------------
7321// C3 C4
7322//------------------------------------
7323// mbf_delete_c3 ready
7324// dep
7325// mux out
7326// ID of dependent
7327// mbf inst. in
7328// misbuf.
7329//
7330// find out
7331// if next_link
7332// is vld.
7333//------------------------------------
7334// We do not ready a miss buffer dependent immediately
7335// after the older instruction dequeues from the Miss buffer.
7336// There are cases where the dependent may have to wait in the miss buffer
7337// for other events to occur. For example, a load that hits the fill Buffer
7338// will not ready the Miss Buffer dependent.
7339//
7340// dep rdy conditions:
7341// - older instruction hits the $ ( non cas1).
7342// - older instruction is a wr64 and completes.
7343// - older instruction is a ld64 and hits the FB.
7344// -older instruction hits FB in $ off mode.
7345//
7346//////
7347
7348
7349l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_decdp_cas1_inst_c2
7350 (.din(arb_decdp_cas1_inst_c2), .l1clk(l1clk),
7351 .scan_in(ff_decdp_cas1_inst_c2_scanin),
7352 .scan_out(ff_decdp_cas1_inst_c2_scanout),
7353 .dout(cas1_inst_c3),
7354 .siclk(siclk),
7355 .soclk(soclk)
7356);
7357
7358l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_l2_bypass_mode_on_d1
7359 (.din(csr_l2_bypass_mode_on), .l1clk(l1clk),
7360 .scan_in(ff_l2_bypass_mode_on_d1_scanin),
7361 .scan_out(ff_l2_bypass_mode_on_d1_scanout),
7362 .dout(l2_bypass_mode_on_d1),
7363 .siclk(siclk),
7364 .soclk(soclk)
7365);
7366
7367
7368l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_match_c3
7369 (.din(filbuf_misbuf_match_c2), .l1clk(l1clk),
7370 .scan_in(ff_filbuf_match_c3_scanin),
7371 .scan_out(ff_filbuf_match_c3_scanout),
7372 .dout(filbuf_match_c3_unqual),
7373 .siclk(siclk),
7374 .soclk(soclk)
7375);
7376
7377assign filbuf_match_c3 = filbuf_match_c3_unqual & mb_inst_vld_c3 ;
7378
7379l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_stinst_match_c3
7380 (.din(filbuf_misbuf_stinst_match_c2), .l1clk(l1clk),
7381 .scan_in(ff_filbuf_stinst_match_c3_scanin),
7382 .scan_out(ff_filbuf_stinst_match_c3_scanout),
7383 .dout(filbuf_stinst_match_c3),
7384 .siclk(siclk),
7385 .soclk(soclk)
7386);
7387// int 5.0 changes
7388//-----\/ FIX for bug #4619 --\/-----
7389// inval instructions will ready their dependents
7390// when they are deleted from the miss buffer
7391//-----\/ FIX for bug #4619 --\/-----
7392l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_inval_inst_c3
7393 (.din(arb_misbuf_inval_inst_c2), .l1clk(l1clk),
7394 .scan_in(ff_misbuf_inval_inst_c3_scanin),
7395 .scan_out(ff_misbuf_inval_inst_c3_scanout),
7396 .dout(misbuf_inval_inst_c3),
7397 .siclk(siclk),
7398 .soclk(soclk)
7399);
7400
7401
7402
7403assign mb_dep_rdy_en_c3 = misbuf_next_vld_c3 & mbf_delete_c3 & (
7404 (tag_hit_c3 & ~cas1_inst_c3 & ~vuad_err_true_c3) | // fix for bug 116974
7405 // If instruction from MB sees a vuad error
7406 // but still completes e.g a load bypass from
7407 // Fill Buffer, it should not ready the dependant
7408 // in the miss buffer as the hit can be a false hit
7409 // due to vuad error. The fill should happen and only
7410 // then the dependant should be readied.
7411 ( misbuf_inval_inst_c3) | // int 5.0 changes FIX for bug #4619
7412 ( misbuf_wr64_miss_comp_c3 & ~tag_misbuf_par_err_c3 & ~arb_vuad_ce_err_c3) | // int 5.0 changes
7413 (filbuf_match_c3 & ~cas1_inst_c3 &
7414 (ld64_inst_c3 | // fb match for ld64
7415 (l2_bypass_mode_on_d1 &
7416 ~filbuf_stinst_match_c3
7417 )) // no fill or $ OFF
7418 ) );
7419
7420l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mb_dep_rdy_en_c4
7421 (.din(mb_dep_rdy_en_c3), .l1clk(l1clk),
7422 .scan_in(ff_mb_dep_rdy_en_c4_scanin),
7423 .scan_out(ff_mb_dep_rdy_en_c4_scanout),
7424 .dout(mb_dep_rdy_en_c4),
7425 .siclk(siclk),
7426 .soclk(soclk)
7427);
7428
7429assign mb_dep_rdy_c4[0] = ( misbuf_filbuf_next_link_c4 == 5'd0) & mb_dep_rdy_en_c4 ;
7430assign mb_dep_rdy_c4[1] = ( misbuf_filbuf_next_link_c4 == 5'd1) & mb_dep_rdy_en_c4 ;
7431assign mb_dep_rdy_c4[2] = ( misbuf_filbuf_next_link_c4 == 5'd2) & mb_dep_rdy_en_c4 ;
7432assign mb_dep_rdy_c4[3] = ( misbuf_filbuf_next_link_c4 == 5'd3) & mb_dep_rdy_en_c4 ;
7433assign mb_dep_rdy_c4[4] = ( misbuf_filbuf_next_link_c4 == 5'd4) & mb_dep_rdy_en_c4 ;
7434assign mb_dep_rdy_c4[5] = ( misbuf_filbuf_next_link_c4 == 5'd5) & mb_dep_rdy_en_c4 ;
7435assign mb_dep_rdy_c4[6] = ( misbuf_filbuf_next_link_c4 == 5'd6) & mb_dep_rdy_en_c4 ;
7436assign mb_dep_rdy_c4[7] = ( misbuf_filbuf_next_link_c4 == 5'd7) & mb_dep_rdy_en_c4 ;
7437assign mb_dep_rdy_c4[8] = ( misbuf_filbuf_next_link_c4 == 5'd8) & mb_dep_rdy_en_c4 ;
7438assign mb_dep_rdy_c4[9] = ( misbuf_filbuf_next_link_c4 == 5'd9) & mb_dep_rdy_en_c4 ;
7439assign mb_dep_rdy_c4[10] = ( misbuf_filbuf_next_link_c4 == 5'd10) & mb_dep_rdy_en_c4 ;
7440assign mb_dep_rdy_c4[11] = ( misbuf_filbuf_next_link_c4 == 5'd11) & mb_dep_rdy_en_c4 ;
7441assign mb_dep_rdy_c4[12] = ( misbuf_filbuf_next_link_c4 == 5'd12) & mb_dep_rdy_en_c4 ;
7442assign mb_dep_rdy_c4[13] = ( misbuf_filbuf_next_link_c4 == 5'd13) & mb_dep_rdy_en_c4 ;
7443assign mb_dep_rdy_c4[14] = ( misbuf_filbuf_next_link_c4 == 5'd14) & mb_dep_rdy_en_c4 ;
7444assign mb_dep_rdy_c4[15] = ( misbuf_filbuf_next_link_c4 == 5'd15) & mb_dep_rdy_en_c4 ;
7445// BS & SR 11/04/03, MB grows to 32
7446assign mb_dep_rdy_c4[16] = ( misbuf_filbuf_next_link_c4 == 5'd16) & mb_dep_rdy_en_c4 ;
7447assign mb_dep_rdy_c4[17] = ( misbuf_filbuf_next_link_c4 == 5'd17) & mb_dep_rdy_en_c4 ;
7448assign mb_dep_rdy_c4[18] = ( misbuf_filbuf_next_link_c4 == 5'd18) & mb_dep_rdy_en_c4 ;
7449assign mb_dep_rdy_c4[19] = ( misbuf_filbuf_next_link_c4 == 5'd19) & mb_dep_rdy_en_c4 ;
7450assign mb_dep_rdy_c4[20] = ( misbuf_filbuf_next_link_c4 == 5'd20) & mb_dep_rdy_en_c4 ;
7451assign mb_dep_rdy_c4[21] = ( misbuf_filbuf_next_link_c4 == 5'd21) & mb_dep_rdy_en_c4 ;
7452assign mb_dep_rdy_c4[22] = ( misbuf_filbuf_next_link_c4 == 5'd22) & mb_dep_rdy_en_c4 ;
7453assign mb_dep_rdy_c4[23] = ( misbuf_filbuf_next_link_c4 == 5'd23) & mb_dep_rdy_en_c4 ;
7454assign mb_dep_rdy_c4[24] = ( misbuf_filbuf_next_link_c4 == 5'd24) & mb_dep_rdy_en_c4 ;
7455assign mb_dep_rdy_c4[25] = ( misbuf_filbuf_next_link_c4 == 5'd25) & mb_dep_rdy_en_c4 ;
7456assign mb_dep_rdy_c4[26] = ( misbuf_filbuf_next_link_c4 == 5'd26) & mb_dep_rdy_en_c4 ;
7457assign mb_dep_rdy_c4[27] = ( misbuf_filbuf_next_link_c4 == 5'd27) & mb_dep_rdy_en_c4 ;
7458assign mb_dep_rdy_c4[28] = ( misbuf_filbuf_next_link_c4 == 5'd28) & mb_dep_rdy_en_c4 ;
7459assign mb_dep_rdy_c4[29] = ( misbuf_filbuf_next_link_c4 == 5'd29) & mb_dep_rdy_en_c4 ;
7460assign mb_dep_rdy_c4[30] = ( misbuf_filbuf_next_link_c4 == 5'd30) & mb_dep_rdy_en_c4 ;
7461assign mb_dep_rdy_c4[31] = ( misbuf_filbuf_next_link_c4 == 5'd31) & mb_dep_rdy_en_c4 ;
7462
7463
7464///////////
7465// Ready from Wbctl for WBB hits sitting in the Miss Buffer.
7466//--------------------------------------
7467// 1 2
7468//------------------------------------
7469// wbb eviction ready
7470// complete
7471// dep
7472// mux out
7473// ID of dependent
7474///////////
7475
7476
7477l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_wbb_dep_rdy_en_d1
7478 (.din(wbuf_misbuf_dep_rdy_en), .l1clk(l1clk),
7479 .scan_in(ff_wbb_dep_rdy_en_d1_scanin),
7480 .scan_out(ff_wbb_dep_rdy_en_d1_scanout),
7481 .dout(wbb_dep_rdy_en_d1),
7482 .siclk(siclk),
7483 .soclk(soclk)
7484);
7485
7486l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_dep_mbid_d1 // BS & SR 11/04/03, MB grows to 32
7487 (.din(wbuf_misbuf_dep_mbid[4:0]), .l1clk(l1clk),
7488 .scan_in(ff_dep_mbid_d1_scanin),
7489 .scan_out(ff_dep_mbid_d1_scanout),
7490 .dout(wbb_dep_mbid_d1[4:0]),
7491 .siclk(siclk),
7492 .soclk(soclk)
7493);
7494
7495
7496assign wbb_dep_rdy_d1[0] = ( wbb_dep_mbid_d1 == 5'd0) & wbb_dep_rdy_en_d1 ;
7497assign wbb_dep_rdy_d1[1] = ( wbb_dep_mbid_d1 == 5'd1) & wbb_dep_rdy_en_d1 ;
7498assign wbb_dep_rdy_d1[2] = ( wbb_dep_mbid_d1 == 5'd2) & wbb_dep_rdy_en_d1 ;
7499assign wbb_dep_rdy_d1[3] = ( wbb_dep_mbid_d1 == 5'd3) & wbb_dep_rdy_en_d1 ;
7500assign wbb_dep_rdy_d1[4] = ( wbb_dep_mbid_d1 == 5'd4) & wbb_dep_rdy_en_d1 ;
7501assign wbb_dep_rdy_d1[5] = ( wbb_dep_mbid_d1 == 5'd5) & wbb_dep_rdy_en_d1 ;
7502assign wbb_dep_rdy_d1[6] = ( wbb_dep_mbid_d1 == 5'd6) & wbb_dep_rdy_en_d1 ;
7503assign wbb_dep_rdy_d1[7] = ( wbb_dep_mbid_d1 == 5'd7) & wbb_dep_rdy_en_d1 ;
7504assign wbb_dep_rdy_d1[8] = ( wbb_dep_mbid_d1 == 5'd8) & wbb_dep_rdy_en_d1 ;
7505assign wbb_dep_rdy_d1[9] = ( wbb_dep_mbid_d1 == 5'd9) & wbb_dep_rdy_en_d1 ;
7506assign wbb_dep_rdy_d1[10] = ( wbb_dep_mbid_d1 == 5'd10) & wbb_dep_rdy_en_d1 ;
7507assign wbb_dep_rdy_d1[11] = ( wbb_dep_mbid_d1 == 5'd11) & wbb_dep_rdy_en_d1 ;
7508assign wbb_dep_rdy_d1[12] = ( wbb_dep_mbid_d1 == 5'd12) & wbb_dep_rdy_en_d1 ;
7509assign wbb_dep_rdy_d1[13] = ( wbb_dep_mbid_d1 == 5'd13) & wbb_dep_rdy_en_d1 ;
7510assign wbb_dep_rdy_d1[14] = ( wbb_dep_mbid_d1 == 5'd14) & wbb_dep_rdy_en_d1 ;
7511assign wbb_dep_rdy_d1[15] = ( wbb_dep_mbid_d1 == 5'd15) & wbb_dep_rdy_en_d1 ;
7512// BS & SR 11/04/03, MB grows to 32
7513assign wbb_dep_rdy_d1[16] = ( wbb_dep_mbid_d1 == 5'd16) & wbb_dep_rdy_en_d1 ;
7514assign wbb_dep_rdy_d1[17] = ( wbb_dep_mbid_d1 == 5'd17) & wbb_dep_rdy_en_d1 ;
7515assign wbb_dep_rdy_d1[18] = ( wbb_dep_mbid_d1 == 5'd18) & wbb_dep_rdy_en_d1 ;
7516assign wbb_dep_rdy_d1[19] = ( wbb_dep_mbid_d1 == 5'd19) & wbb_dep_rdy_en_d1 ;
7517assign wbb_dep_rdy_d1[20] = ( wbb_dep_mbid_d1 == 5'd20) & wbb_dep_rdy_en_d1 ;
7518assign wbb_dep_rdy_d1[21] = ( wbb_dep_mbid_d1 == 5'd21) & wbb_dep_rdy_en_d1 ;
7519assign wbb_dep_rdy_d1[22] = ( wbb_dep_mbid_d1 == 5'd22) & wbb_dep_rdy_en_d1 ;
7520assign wbb_dep_rdy_d1[23] = ( wbb_dep_mbid_d1 == 5'd23) & wbb_dep_rdy_en_d1 ;
7521assign wbb_dep_rdy_d1[24] = ( wbb_dep_mbid_d1 == 5'd24) & wbb_dep_rdy_en_d1 ;
7522assign wbb_dep_rdy_d1[25] = ( wbb_dep_mbid_d1 == 5'd25) & wbb_dep_rdy_en_d1 ;
7523assign wbb_dep_rdy_d1[26] = ( wbb_dep_mbid_d1 == 5'd26) & wbb_dep_rdy_en_d1 ;
7524assign wbb_dep_rdy_d1[27] = ( wbb_dep_mbid_d1 == 5'd27) & wbb_dep_rdy_en_d1 ;
7525assign wbb_dep_rdy_d1[28] = ( wbb_dep_mbid_d1 == 5'd28) & wbb_dep_rdy_en_d1 ;
7526assign wbb_dep_rdy_d1[29] = ( wbb_dep_mbid_d1 == 5'd29) & wbb_dep_rdy_en_d1 ;
7527assign wbb_dep_rdy_d1[30] = ( wbb_dep_mbid_d1 == 5'd30) & wbb_dep_rdy_en_d1 ;
7528assign wbb_dep_rdy_d1[31] = ( wbb_dep_mbid_d1 == 5'd31) & wbb_dep_rdy_en_d1 ;
7529
7530
7531
7532
7533///////////
7534// Ready from rdmat for rdmat hits sitting in the Miss Buffer.
7535//--------------------------------------
7536// 1 2
7537//------------------------------------
7538// rdmat eviction ready
7539// complete
7540// dep
7541// mux out
7542// ID of dependent
7543///////////
7544
7545
7546
7547l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_rdmatb_dep_rdy_en_d1
7548 (.din(rdmat_misbuf_dep_rdy_en), .l1clk(l1clk),
7549 .scan_in(ff_rdmatb_dep_rdy_en_d1_scanin),
7550 .scan_out(ff_rdmatb_dep_rdy_en_d1_scanout),
7551 .dout(rdmat_dep_rdy_en_d1),
7552 .siclk(siclk),
7553 .soclk(soclk)
7554);
7555
7556l2t_misbuf_ctl_msff_ctl_macro__width_5 ff_dep_rdmat_mbid_d1 // BS & SR 11/04/03, MB grows to 32
7557 (.din(rdmat_misbuf_dep_mbid[4:0]), .l1clk(l1clk),
7558 .scan_in(ff_dep_rdmat_mbid_d1_scanin),
7559 .scan_out(ff_dep_rdmat_mbid_d1_scanout),
7560 .dout(rdmat_dep_mbid_d1[4:0]),
7561 .siclk(siclk),
7562 .soclk(soclk)
7563);
7564
7565
7566assign rdmat_dep_rdy_d1[0] = ( rdmat_dep_mbid_d1 == 5'd0) & rdmat_dep_rdy_en_d1 ;
7567assign rdmat_dep_rdy_d1[1] = ( rdmat_dep_mbid_d1 == 5'd1) & rdmat_dep_rdy_en_d1 ;
7568assign rdmat_dep_rdy_d1[2] = ( rdmat_dep_mbid_d1 == 5'd2) & rdmat_dep_rdy_en_d1 ;
7569assign rdmat_dep_rdy_d1[3] = ( rdmat_dep_mbid_d1 == 5'd3) & rdmat_dep_rdy_en_d1 ;
7570assign rdmat_dep_rdy_d1[4] = ( rdmat_dep_mbid_d1 == 5'd4) & rdmat_dep_rdy_en_d1 ;
7571assign rdmat_dep_rdy_d1[5] = ( rdmat_dep_mbid_d1 == 5'd5) & rdmat_dep_rdy_en_d1 ;
7572assign rdmat_dep_rdy_d1[6] = ( rdmat_dep_mbid_d1 == 5'd6) & rdmat_dep_rdy_en_d1 ;
7573assign rdmat_dep_rdy_d1[7] = ( rdmat_dep_mbid_d1 == 5'd7) & rdmat_dep_rdy_en_d1 ;
7574assign rdmat_dep_rdy_d1[8] = ( rdmat_dep_mbid_d1 == 5'd8) & rdmat_dep_rdy_en_d1 ;
7575assign rdmat_dep_rdy_d1[9] = ( rdmat_dep_mbid_d1 == 5'd9) & rdmat_dep_rdy_en_d1 ;
7576assign rdmat_dep_rdy_d1[10] = ( rdmat_dep_mbid_d1 == 5'd10) & rdmat_dep_rdy_en_d1 ;
7577assign rdmat_dep_rdy_d1[11] = ( rdmat_dep_mbid_d1 == 5'd11) & rdmat_dep_rdy_en_d1 ;
7578assign rdmat_dep_rdy_d1[12] = ( rdmat_dep_mbid_d1 == 5'd12) & rdmat_dep_rdy_en_d1 ;
7579assign rdmat_dep_rdy_d1[13] = ( rdmat_dep_mbid_d1 == 5'd13) & rdmat_dep_rdy_en_d1 ;
7580assign rdmat_dep_rdy_d1[14] = ( rdmat_dep_mbid_d1 == 5'd14) & rdmat_dep_rdy_en_d1 ;
7581assign rdmat_dep_rdy_d1[15] = ( rdmat_dep_mbid_d1 == 5'd15) & rdmat_dep_rdy_en_d1 ;
7582// BS & SR 11/04/03, MB grows to 32
7583assign rdmat_dep_rdy_d1[16] = ( rdmat_dep_mbid_d1 == 5'd16) & rdmat_dep_rdy_en_d1 ;
7584assign rdmat_dep_rdy_d1[17] = ( rdmat_dep_mbid_d1 == 5'd17) & rdmat_dep_rdy_en_d1 ;
7585assign rdmat_dep_rdy_d1[18] = ( rdmat_dep_mbid_d1 == 5'd18) & rdmat_dep_rdy_en_d1 ;
7586assign rdmat_dep_rdy_d1[19] = ( rdmat_dep_mbid_d1 == 5'd19) & rdmat_dep_rdy_en_d1 ;
7587assign rdmat_dep_rdy_d1[20] = ( rdmat_dep_mbid_d1 == 5'd20) & rdmat_dep_rdy_en_d1 ;
7588assign rdmat_dep_rdy_d1[21] = ( rdmat_dep_mbid_d1 == 5'd21) & rdmat_dep_rdy_en_d1 ;
7589assign rdmat_dep_rdy_d1[22] = ( rdmat_dep_mbid_d1 == 5'd22) & rdmat_dep_rdy_en_d1 ;
7590assign rdmat_dep_rdy_d1[23] = ( rdmat_dep_mbid_d1 == 5'd23) & rdmat_dep_rdy_en_d1 ;
7591assign rdmat_dep_rdy_d1[24] = ( rdmat_dep_mbid_d1 == 5'd24) & rdmat_dep_rdy_en_d1 ;
7592assign rdmat_dep_rdy_d1[25] = ( rdmat_dep_mbid_d1 == 5'd25) & rdmat_dep_rdy_en_d1 ;
7593assign rdmat_dep_rdy_d1[26] = ( rdmat_dep_mbid_d1 == 5'd26) & rdmat_dep_rdy_en_d1 ;
7594assign rdmat_dep_rdy_d1[27] = ( rdmat_dep_mbid_d1 == 5'd27) & rdmat_dep_rdy_en_d1 ;
7595assign rdmat_dep_rdy_d1[28] = ( rdmat_dep_mbid_d1 == 5'd28) & rdmat_dep_rdy_en_d1 ;
7596assign rdmat_dep_rdy_d1[29] = ( rdmat_dep_mbid_d1 == 5'd29) & rdmat_dep_rdy_en_d1 ;
7597assign rdmat_dep_rdy_d1[30] = ( rdmat_dep_mbid_d1 == 5'd30) & rdmat_dep_rdy_en_d1 ;
7598assign rdmat_dep_rdy_d1[31] = ( rdmat_dep_mbid_d1 == 5'd31) & rdmat_dep_rdy_en_d1 ;
7599
7600///////////
7601// C8 ready.
7602// * Ready for CAS2 ( readies dependent entry in C9)
7603// * PST 2nd pass ( Readies same instruction in mb)
7604// * tag parity detected ( Readies same instruction in mb)
7605// * A TECC instruction ( Readies same instruction in mb)
7606///////////
7607
7608
7609assign cas2_or_pst_rdy_c8 = ( mb_data_wr_wl_c8 & // insert or reinsert pointer.
7610 {32{arb_pst_ctrue_en_c8 | // pst ctrue enable c8 // BS & SR 11/04/03, MB grows to 32
7611 arb_arbdp_tecc_inst_mb_c8 |// tecc instruction
7612 rdma_comp_rdy_c8}} ) | // rdma reg incomplete instruction
7613 cas_rdy_set_c9 ; // CAS rdy set c9( does not imply ctrue=1)
7614
7615
7616///////////////////////////////
7617// CSR store ready:
7618// A CSR store is inserted in the Miss Buffer
7619// like any miss. The MBID of a CSR store is saved
7620// since there can only be one CSR store pending
7621// in the L2$. Once the cache is disabled all snoops
7622// will receive a miss response from the L2.
7623//
7624// Pipeline for writing mbid and mbid vld for
7625// a CSR write.
7626//-------------------------------------------
7627// C3 C4
7628//-------------------------------------------
7629// mbidvld=1
7630// mbid = valid
7631//
7632// if mb_count=1
7633// & fb_count=0
7634// set RDY.
7635///////////////////////////////
7636
7637
7638assign set_mbid_vld_prev= arb_csr_st_c2 & // CSR store
7639 misbuf_mbtag_wr_en_c2 ;
7640
7641
7642l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_set_mbid_vld
7643 (.din(set_mbid_vld_prev), .l1clk(l1clk),
7644 .scan_in(ff_set_mbid_vld_scanin),
7645 .scan_out(ff_set_mbid_vld_scanout),
7646 .dout(set_mbid_vld),
7647 .siclk(siclk),
7648 .soclk(soclk)
7649);
7650
7651assign reset_mbid_vld = ( mb_count_c4==6'd1) // only entry is csr write, BS & SR 11/04/03, MB grows to 32
7652 & filbuf_fb_count_eq_0 ; // fill buffer empty.
7653
7654
7655assign mbid_vld_in = (( mbid_vld & ~reset_mbid_vld ) | set_mbid_vld ) ;
7656
7657l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_mbid_vld // sync reset active low
7658 (.din(mbid_vld_in), .l1clk(l1clk), .clr(~dbb_rst_l),
7659 .scan_in(ff_mbid_vld_scanin),
7660 .scan_out(ff_mbid_vld_scanout),
7661 .dout(mbid_vld),
7662 .siclk(siclk),
7663 .soclk(soclk)
7664);
7665
7666assign rdy_csr_inst_en = mbid_vld & reset_mbid_vld ;
7667
7668
7669l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_mbid // BS & SR 11/04/03, MB grows to 32
7670 (.din(enc_tag_wr_wl_c3[4:0]), .l1clk(l1clk),
7671 .scan_in(ff_mbid_scanin),
7672 .scan_out(ff_mbid_scanout),
7673 .en(set_mbid_vld),
7674 .dout(csr_mbid[4:0]),
7675 .siclk(siclk),
7676 .soclk(soclk)
7677);
7678
7679
7680
7681assign csr_inst_rdy[0] = ( csr_mbid == 5'd0) & rdy_csr_inst_en ;
7682assign csr_inst_rdy[1] = ( csr_mbid == 5'd1) & rdy_csr_inst_en ;
7683assign csr_inst_rdy[2] = ( csr_mbid == 5'd2) & rdy_csr_inst_en ;
7684assign csr_inst_rdy[3] = ( csr_mbid == 5'd3) & rdy_csr_inst_en ;
7685assign csr_inst_rdy[4] = ( csr_mbid == 5'd4) & rdy_csr_inst_en ;
7686assign csr_inst_rdy[5] = ( csr_mbid == 5'd5) & rdy_csr_inst_en ;
7687assign csr_inst_rdy[6] = ( csr_mbid == 5'd6) & rdy_csr_inst_en ;
7688assign csr_inst_rdy[7] = ( csr_mbid == 5'd7) & rdy_csr_inst_en ;
7689assign csr_inst_rdy[8] = ( csr_mbid == 5'd8) & rdy_csr_inst_en ;
7690assign csr_inst_rdy[9] = ( csr_mbid == 5'd9) & rdy_csr_inst_en ;
7691assign csr_inst_rdy[10] = ( csr_mbid == 5'd10) & rdy_csr_inst_en ;
7692assign csr_inst_rdy[11] = ( csr_mbid == 5'd11) & rdy_csr_inst_en ;
7693assign csr_inst_rdy[12] = ( csr_mbid == 5'd12) & rdy_csr_inst_en ;
7694assign csr_inst_rdy[13] = ( csr_mbid == 5'd13) & rdy_csr_inst_en ;
7695assign csr_inst_rdy[14] = ( csr_mbid == 5'd14) & rdy_csr_inst_en ;
7696assign csr_inst_rdy[15] = ( csr_mbid == 5'd15) & rdy_csr_inst_en ;
7697// BS & SR 11/04/03, MB grows to 32
7698assign csr_inst_rdy[16] = ( csr_mbid == 5'd16) & rdy_csr_inst_en ;
7699assign csr_inst_rdy[17] = ( csr_mbid == 5'd17) & rdy_csr_inst_en ;
7700assign csr_inst_rdy[18] = ( csr_mbid == 5'd18) & rdy_csr_inst_en ;
7701assign csr_inst_rdy[19] = ( csr_mbid == 5'd19) & rdy_csr_inst_en ;
7702assign csr_inst_rdy[20] = ( csr_mbid == 5'd20) & rdy_csr_inst_en ;
7703assign csr_inst_rdy[21] = ( csr_mbid == 5'd21) & rdy_csr_inst_en ;
7704assign csr_inst_rdy[22] = ( csr_mbid == 5'd22) & rdy_csr_inst_en ;
7705assign csr_inst_rdy[23] = ( csr_mbid == 5'd23) & rdy_csr_inst_en ;
7706assign csr_inst_rdy[24] = ( csr_mbid == 5'd24) & rdy_csr_inst_en ;
7707assign csr_inst_rdy[25] = ( csr_mbid == 5'd25) & rdy_csr_inst_en ;
7708assign csr_inst_rdy[26] = ( csr_mbid == 5'd26) & rdy_csr_inst_en ;
7709assign csr_inst_rdy[27] = ( csr_mbid == 5'd27) & rdy_csr_inst_en ;
7710assign csr_inst_rdy[28] = ( csr_mbid == 5'd28) & rdy_csr_inst_en ;
7711assign csr_inst_rdy[29] = ( csr_mbid == 5'd29) & rdy_csr_inst_en ;
7712assign csr_inst_rdy[30] = ( csr_mbid == 5'd30) & rdy_csr_inst_en ;
7713assign csr_inst_rdy[31] = ( csr_mbid == 5'd31) & rdy_csr_inst_en ;
7714
7715
7716assign set_mbid_vld_pfice_prev = arb_pf_ice_inst_c2 & misbuf_mbtag_wr_en_c2;
7717
7718l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_set_mbid_vld_pfice_prev
7719 (.din(set_mbid_vld_pfice_prev), .l1clk(l1clk),
7720 .scan_in(ff_set_mbid_vld_pfice_prev_scanin),
7721 .scan_out(ff_set_mbid_vld_pfice_prev_scanout),
7722 .dout(set_mbid_vld_pfice),
7723 .siclk(siclk),
7724 .soclk(soclk)
7725);
7726
7727assign ready_pf_ice_instr = ( mb_count_c4==6'd1) // only entry is csr write, BS & SR 11/04/03, MB grows to 32
7728 & filbuf_fb_count_eq_0 ; // fill buffer empty.
7729
7730assign pf_ice_mbid_vld_in = ((pf_ice_mbid_vld & ~ready_pf_ice_instr ) | set_mbid_vld_pfice) ;
7731
7732l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_pfice_mbid_vld // sync reset active low
7733 (.din(pf_ice_mbid_vld_in), .l1clk(l1clk), .clr(~dbb_rst_l),
7734 .scan_in(ff_pfice_mbid_vld_scanin),
7735 .scan_out(ff_pfice_mbid_vld_scanout),
7736 .dout(pf_ice_mbid_vld),
7737 .siclk(siclk),
7738 .soclk(soclk)
7739);
7740
7741assign pf_ice_rdy_inst_en = pf_ice_mbid_vld & ready_pf_ice_instr ;
7742
7743
7744l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 ff_pfice_mbid // BS & SR 11/04/03, MB grows to 32
7745 (.din(enc_tag_wr_wl_c3[4:0]), .l1clk(l1clk),
7746 .scan_in(ff_pfice_mbid_scanin),
7747 .scan_out(ff_pfice_mbid_scanout),
7748 .en(set_mbid_vld_pfice),
7749 .dout(pf_ice_csr_mbid[4:0]),
7750 .siclk(siclk),
7751 .soclk(soclk)
7752);
7753
7754// pf ice inst ready
7755assign pfice_inst_rdy[0] = ( pf_ice_csr_mbid == 5'd0) & pf_ice_rdy_inst_en ;
7756assign pfice_inst_rdy[1] = ( pf_ice_csr_mbid == 5'd1) & pf_ice_rdy_inst_en ;
7757assign pfice_inst_rdy[2] = ( pf_ice_csr_mbid == 5'd2) & pf_ice_rdy_inst_en ;
7758assign pfice_inst_rdy[3] = ( pf_ice_csr_mbid == 5'd3) & pf_ice_rdy_inst_en ;
7759assign pfice_inst_rdy[4] = ( pf_ice_csr_mbid == 5'd4) & pf_ice_rdy_inst_en ;
7760assign pfice_inst_rdy[5] = ( pf_ice_csr_mbid == 5'd5) & pf_ice_rdy_inst_en ;
7761assign pfice_inst_rdy[6] = ( pf_ice_csr_mbid == 5'd6) & pf_ice_rdy_inst_en ;
7762assign pfice_inst_rdy[7] = ( pf_ice_csr_mbid == 5'd7) & pf_ice_rdy_inst_en ;
7763assign pfice_inst_rdy[8] = ( pf_ice_csr_mbid == 5'd8) & pf_ice_rdy_inst_en ;
7764assign pfice_inst_rdy[9] = ( pf_ice_csr_mbid == 5'd9) & pf_ice_rdy_inst_en ;
7765assign pfice_inst_rdy[10] = ( pf_ice_csr_mbid == 5'd10) & pf_ice_rdy_inst_en ;
7766assign pfice_inst_rdy[11] = ( pf_ice_csr_mbid == 5'd11) & pf_ice_rdy_inst_en ;
7767assign pfice_inst_rdy[12] = ( pf_ice_csr_mbid == 5'd12) & pf_ice_rdy_inst_en ;
7768assign pfice_inst_rdy[13] = ( pf_ice_csr_mbid == 5'd13) & pf_ice_rdy_inst_en ;
7769assign pfice_inst_rdy[14] = ( pf_ice_csr_mbid == 5'd14) & pf_ice_rdy_inst_en ;
7770assign pfice_inst_rdy[15] = ( pf_ice_csr_mbid == 5'd15) & pf_ice_rdy_inst_en ;
7771assign pfice_inst_rdy[16] = ( pf_ice_csr_mbid == 5'd16) & pf_ice_rdy_inst_en ;
7772assign pfice_inst_rdy[17] = ( pf_ice_csr_mbid == 5'd17) & pf_ice_rdy_inst_en ;
7773assign pfice_inst_rdy[18] = ( pf_ice_csr_mbid == 5'd18) & pf_ice_rdy_inst_en ;
7774assign pfice_inst_rdy[19] = ( pf_ice_csr_mbid == 5'd19) & pf_ice_rdy_inst_en ;
7775assign pfice_inst_rdy[20] = ( pf_ice_csr_mbid == 5'd20) & pf_ice_rdy_inst_en ;
7776assign pfice_inst_rdy[21] = ( pf_ice_csr_mbid == 5'd21) & pf_ice_rdy_inst_en ;
7777assign pfice_inst_rdy[22] = ( pf_ice_csr_mbid == 5'd22) & pf_ice_rdy_inst_en ;
7778assign pfice_inst_rdy[23] = ( pf_ice_csr_mbid == 5'd23) & pf_ice_rdy_inst_en ;
7779assign pfice_inst_rdy[24] = ( pf_ice_csr_mbid == 5'd24) & pf_ice_rdy_inst_en ;
7780assign pfice_inst_rdy[25] = ( pf_ice_csr_mbid == 5'd25) & pf_ice_rdy_inst_en ;
7781assign pfice_inst_rdy[26] = ( pf_ice_csr_mbid == 5'd26) & pf_ice_rdy_inst_en ;
7782assign pfice_inst_rdy[27] = ( pf_ice_csr_mbid == 5'd27) & pf_ice_rdy_inst_en ;
7783assign pfice_inst_rdy[28] = ( pf_ice_csr_mbid == 5'd28) & pf_ice_rdy_inst_en ;
7784assign pfice_inst_rdy[29] = ( pf_ice_csr_mbid == 5'd29) & pf_ice_rdy_inst_en ;
7785assign pfice_inst_rdy[30] = ( pf_ice_csr_mbid == 5'd30) & pf_ice_rdy_inst_en ;
7786assign pfice_inst_rdy[31] = ( pf_ice_csr_mbid == 5'd31) & pf_ice_rdy_inst_en ;
7787
7788
7789// VUAD CE ready logic
7790
7791
7792l2t_misbuf_ctl_msff_ctl_macro__width_30 ff_vuad_ce_err_ready // VUAD ecc changes
7793 (
7794 .scan_in(ff_vuad_ce_err_ready_scanin),
7795 .scan_out(ff_vuad_ce_err_ready_scanout),
7796 .din({enc_tag_wr_wl_c3[4:0],enc_tag_wr_wl_c4[4:0],enc_tag_wr_wl_c5[4:0],enc_tag_wr_wl_c52[4:0],
7797 enc_tag_wr_wl_c6[4:0],enc_tag_wr_wl_c7[4:0]}),
7798 .dout({enc_tag_wr_wl_c4[4:0],enc_tag_wr_wl_c5[4:0],enc_tag_wr_wl_c52[4:0],
7799 enc_tag_wr_wl_c6[4:0],enc_tag_wr_wl_c7[4:0],enc_tag_wr_wl_c8[4:0]}),
7800 .l1clk(l1clk),
7801 .siclk(siclk),
7802 .soclk(soclk)
7803 );
7804
7805
7806assign nonmisbuf_inst_c8 = ~misbuf_inst_c8 & arb_vuad_ce_err_c8 & buffer_miss_vld_c8;// in case of hit in any buffer,
7807 // do not set vuad_ce_err_rdy bit
7808
7809assign misbuf_inst_with_vuaderr_c8 = misbuf_inst_c8 & arb_vuad_ce_err_c8 & ~misbuf_evict_c8 & buffer_miss_vld_c8;
7810
7811assign vuad_ce_err_rdy[0 ] = ((enc_tag_wr_wl_c8 == 5'd0) & nonmisbuf_inst_c8) |
7812 (( enc_data_wr_wl_c8==5'd0 ) & misbuf_inst_with_vuaderr_c8 );
7813assign vuad_ce_err_rdy[1 ] = ((enc_tag_wr_wl_c8 == 5'd1) & nonmisbuf_inst_c8) |
7814 (( enc_data_wr_wl_c8==5'd1 ) & misbuf_inst_with_vuaderr_c8 );
7815assign vuad_ce_err_rdy[2 ] = ((enc_tag_wr_wl_c8 == 5'd2) & nonmisbuf_inst_c8) |
7816 (( enc_data_wr_wl_c8==5'd2 ) & misbuf_inst_with_vuaderr_c8 );
7817assign vuad_ce_err_rdy[3 ] = ((enc_tag_wr_wl_c8 == 5'd3) & nonmisbuf_inst_c8) |
7818 (( enc_data_wr_wl_c8==5'd3 ) & misbuf_inst_with_vuaderr_c8 );
7819assign vuad_ce_err_rdy[4 ] = ((enc_tag_wr_wl_c8 == 5'd4) & nonmisbuf_inst_c8) |
7820 (( enc_data_wr_wl_c8==5'd4 ) & misbuf_inst_with_vuaderr_c8 );
7821assign vuad_ce_err_rdy[5 ] = ((enc_tag_wr_wl_c8 == 5'd5) & nonmisbuf_inst_c8) |
7822 (( enc_data_wr_wl_c8==5'd5 ) & misbuf_inst_with_vuaderr_c8 );
7823assign vuad_ce_err_rdy[6 ] = ((enc_tag_wr_wl_c8 == 5'd6) & nonmisbuf_inst_c8) |
7824 (( enc_data_wr_wl_c8==5'd6 ) & misbuf_inst_with_vuaderr_c8 );
7825assign vuad_ce_err_rdy[7 ] = ((enc_tag_wr_wl_c8 == 5'd7) & nonmisbuf_inst_c8) |
7826 (( enc_data_wr_wl_c8==5'd7 ) & misbuf_inst_with_vuaderr_c8 );
7827assign vuad_ce_err_rdy[8 ] = ((enc_tag_wr_wl_c8 == 5'd8) & nonmisbuf_inst_c8) |
7828 (( enc_data_wr_wl_c8==5'd8 ) & misbuf_inst_with_vuaderr_c8 );
7829assign vuad_ce_err_rdy[9 ] = ((enc_tag_wr_wl_c8 == 5'd9) & nonmisbuf_inst_c8) |
7830 (( enc_data_wr_wl_c8==5'd9 ) & misbuf_inst_with_vuaderr_c8 );
7831assign vuad_ce_err_rdy[10] = ((enc_tag_wr_wl_c8 == 5'd10) & nonmisbuf_inst_c8) |
7832 (( enc_data_wr_wl_c8==5'd10 ) & misbuf_inst_with_vuaderr_c8 );
7833assign vuad_ce_err_rdy[11] = ((enc_tag_wr_wl_c8 == 5'd11) & nonmisbuf_inst_c8) |
7834 (( enc_data_wr_wl_c8==5'd11 ) & misbuf_inst_with_vuaderr_c8 );
7835assign vuad_ce_err_rdy[12] = ((enc_tag_wr_wl_c8 == 5'd12) & nonmisbuf_inst_c8) |
7836 (( enc_data_wr_wl_c8==5'd12 ) & misbuf_inst_with_vuaderr_c8 );
7837assign vuad_ce_err_rdy[13] = ((enc_tag_wr_wl_c8 == 5'd13) & nonmisbuf_inst_c8) |
7838 (( enc_data_wr_wl_c8==5'd13 ) & misbuf_inst_with_vuaderr_c8 );
7839assign vuad_ce_err_rdy[14] = ((enc_tag_wr_wl_c8 == 5'd14) & nonmisbuf_inst_c8) |
7840 (( enc_data_wr_wl_c8==5'd14 ) & misbuf_inst_with_vuaderr_c8 );
7841assign vuad_ce_err_rdy[15] = ((enc_tag_wr_wl_c8 == 5'd15) & nonmisbuf_inst_c8) |
7842 (( enc_data_wr_wl_c8==5'd15 ) & misbuf_inst_with_vuaderr_c8 );
7843assign vuad_ce_err_rdy[16] = ((enc_tag_wr_wl_c8 == 5'd16) & nonmisbuf_inst_c8) |
7844 (( enc_data_wr_wl_c8 == 5'd16) & misbuf_inst_with_vuaderr_c8 );
7845assign vuad_ce_err_rdy[17] = ((enc_tag_wr_wl_c8 == 5'd17) & nonmisbuf_inst_c8) |
7846 (( enc_data_wr_wl_c8 == 5'd17) & misbuf_inst_with_vuaderr_c8 );
7847assign vuad_ce_err_rdy[18] = ((enc_tag_wr_wl_c8 == 5'd18) & nonmisbuf_inst_c8) |
7848 (( enc_data_wr_wl_c8 == 5'd18) & misbuf_inst_with_vuaderr_c8 );
7849assign vuad_ce_err_rdy[19] = ((enc_tag_wr_wl_c8 == 5'd19) & nonmisbuf_inst_c8) |
7850 (( enc_data_wr_wl_c8 == 5'd19) & misbuf_inst_with_vuaderr_c8 );
7851assign vuad_ce_err_rdy[20] = ((enc_tag_wr_wl_c8 == 5'd20) & nonmisbuf_inst_c8) |
7852 (( enc_data_wr_wl_c8 == 5'd20) & misbuf_inst_with_vuaderr_c8 );
7853assign vuad_ce_err_rdy[21] = ((enc_tag_wr_wl_c8 == 5'd21) & nonmisbuf_inst_c8) |
7854 (( enc_data_wr_wl_c8 == 5'd21) & misbuf_inst_with_vuaderr_c8 );
7855assign vuad_ce_err_rdy[22] = ((enc_tag_wr_wl_c8 == 5'd22) & nonmisbuf_inst_c8) |
7856 (( enc_data_wr_wl_c8 == 5'd22) & misbuf_inst_with_vuaderr_c8 );
7857assign vuad_ce_err_rdy[23] = ((enc_tag_wr_wl_c8 == 5'd23) & nonmisbuf_inst_c8) |
7858 (( enc_data_wr_wl_c8 == 5'd23) & misbuf_inst_with_vuaderr_c8 );
7859assign vuad_ce_err_rdy[24] = ((enc_tag_wr_wl_c8 == 5'd24) & nonmisbuf_inst_c8) |
7860 (( enc_data_wr_wl_c8 == 5'd24) & misbuf_inst_with_vuaderr_c8 );
7861assign vuad_ce_err_rdy[25] = ((enc_tag_wr_wl_c8 == 5'd25) & nonmisbuf_inst_c8) |
7862 (( enc_data_wr_wl_c8 == 5'd25) & misbuf_inst_with_vuaderr_c8 );
7863assign vuad_ce_err_rdy[26] = ((enc_tag_wr_wl_c8 == 5'd26) & nonmisbuf_inst_c8) |
7864 (( enc_data_wr_wl_c8 == 5'd26) & misbuf_inst_with_vuaderr_c8 );
7865assign vuad_ce_err_rdy[27] = ((enc_tag_wr_wl_c8 == 5'd27) & nonmisbuf_inst_c8) |
7866 (( enc_data_wr_wl_c8 == 5'd27) & misbuf_inst_with_vuaderr_c8 );
7867assign vuad_ce_err_rdy[28] = ((enc_tag_wr_wl_c8 == 5'd28) & nonmisbuf_inst_c8) |
7868 (( enc_data_wr_wl_c8 == 5'd28) & misbuf_inst_with_vuaderr_c8 );
7869assign vuad_ce_err_rdy[29] = ((enc_tag_wr_wl_c8 == 5'd29) & nonmisbuf_inst_c8) |
7870 (( enc_data_wr_wl_c8 == 5'd29) & misbuf_inst_with_vuaderr_c8 );
7871assign vuad_ce_err_rdy[30] = ((enc_tag_wr_wl_c8 == 5'd30) & nonmisbuf_inst_c8) |
7872 (( enc_data_wr_wl_c8 == 5'd30) & misbuf_inst_with_vuaderr_c8 );
7873assign vuad_ce_err_rdy[31] = ((enc_tag_wr_wl_c8 == 5'd31) & nonmisbuf_inst_c8) |
7874 (( enc_data_wr_wl_c8 == 5'd31) & misbuf_inst_with_vuaderr_c8 );
7875
7876assign clr_mb_l2_rdy_pfice = ({32{(mbissue_inst_vld_c3 & arb_pf_ice_inst_c3 & ~evict_tecc_vld_c3 &
7877 ~arb_vuad_ce_err_c3 & ~tag_misbuf_par_err_c3)}}) & dec_mb_entry_c3;
7878
7879assign mb_l2_ready_in = (
7880 mb_miss_rdy_r2 | // miss readied by fill data
7881 fb_dep_rdy_c5 | // miss/dep readied by fill op
7882 mb_dep_rdy_c4 | // mbf dep ready
7883 wbb_dep_rdy_d1 | // wbb dependent ready
7884 rdmat_dep_rdy_d1 | // rdma dep ready
7885 cas2_or_pst_rdy_c8 | // ctrue instr
7886 csr_inst_rdy | // csr stores.
7887 vuad_ce_err_rdy | // VUAD ce error ready in c9
7888 mb_l2_ready ) &
7889 ~( (picker_out_d1 &
7890 ~mb_evict_ready & // if evict ready is set, that is
7891 // the that will be reset before l2_ready.
7892 ~mb_tecc_ready & // if tecc ready is set, that will be
7893 // the first to get reset.
7894 {32{l2_pick_d1}}) // reset on pick , BS & SR 11/04/03, MB grows to 32
7895 | clr_mb_l2_rdy_pfice // clear l2_ready when pfice makes its last pass
7896 ) ;
7897
7898l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_l2_ready // sync reset active low, BS & SR 11/04/03, MB grows to 32
7899 (.din(mb_l2_ready_in[31:0]), .l1clk(l1clk),
7900 .scan_in(ff_mb_l2_ready_scanin),
7901 .scan_out(ff_mb_l2_ready_scanout),
7902 .clr(~dbb_rst_l), .dout(mb_l2_ready[31:0]),
7903 .siclk(siclk),
7904 .soclk(soclk)
7905 );
7906
7907
7908/////////////////////////////////////////////////////////////////////////////////
7909// Interface with the L2 Arbiter:
7910// An instruction is picked for L2 issue if the the MB tag and
7911// data are not in use for a DRAM issue.
7912//
7913// THe Miss buffer can issue instructions to the L2 pipeline
7914// at the rate of 1 every 3 cycles. Here is the pipeline for
7915// miss buffer issue. The following pipeline assumes that
7916// the instruction picked by the Miss Buffer for issue is
7917// immediately picked for issue by the arbiter.
7918//
7919//--------------------------------------------------------------------------
7920// inst A PICK READ (PX1) ISSUE(PX2)
7921//--------------------------------------------------------------------------
7922// -pick if
7923// ~l2_wait
7924// or mbsel_c1 -read mbtag
7925// -read mbdata
7926// -set l2_wait -enable px2 rd flop
7927// if l2_pick_d1 - hold mbtag
7928// and mbdata if
7929// l2_wait
7930//--------------------------------------------------------------------------
7931//
7932// l2_pick is similar to mcu pick. It is used to turn off
7933// L2_READY, EVICT_READY and DATA_VLD bits in misbuf.
7934//
7935// picker_out_qual is used to qualify a pick.
7936// If this signal is low, it implies that either
7937// an l2 pick is pending issue or
7938// a mcu_pick is pending acknowledgement
7939// or there is no "READY" instruction for mcu or l2 issue.
7940//
7941/////////////////////////////////////////////////////////////////////////////////
7942
7943
7944assign l2_pick = |( l2_pick_vec ) & picker_out_qual & ~mcu_pick_2 &
7945 ~mb_rewrite_en_c8 ;
7946
7947l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_l2_pick_d1
7948 (.din(l2_pick), .l1clk(l1clk),
7949 .scan_in(ff_l2_pick_d1_scanin),
7950 .scan_out(ff_l2_pick_d1_scanout),
7951 .dout(l2_pick_d1),
7952 .siclk(siclk),
7953 .soclk(soclk)
7954);
7955
7956
7957assign l2_wait_set = l2_pick & ( ~l2_wait | arb_misbuf_mbsel_c1) ;
7958assign l2_wait_reset = arb_misbuf_mbsel_c1 ;
7959
7960// In the following case, set takes preference over the reset
7961// condition.
7962assign l2_wait_in = ( l2_wait & ~l2_wait_reset) |
7963 l2_wait_set ;
7964
7965l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_l2_wait // sync reset active low
7966 (.din(l2_wait_in), .l1clk(l1clk), .clr(~dbb_rst_l),
7967 .scan_in(ff_l2_wait_scanin),
7968 .scan_out(ff_l2_wait_scanout),
7969 .dout(l2_wait),
7970 .siclk(siclk),
7971 .soclk(soclk)
7972);
7973
7974
7975assign picker_out_qual = ~l2_wait | // l2 pick active
7976 arb_misbuf_mbsel_c1 | // l2 pick selected
7977 mcu_pick_2 ; // mcu pick
7978
7979
7980assign misbuf_buf_rd_en = l2t_mb2_run_r1 ? (l2t_mb2_mbtag_rd_en_r2 | l2t_mb2_mbdata_rd_en_r2)
7981 : (l2_pick | mcu_pick_2);
7982
7983// Signals for enabling rd data flops for the Miss Buffer.
7984assign misbuf_arb_l2rd_en = l2t_mb2_run_r1 ? 1'b1 : l2_pick_d1;
7985
7986assign misbuf_arb_vld_px1 = l2_wait ;
7987
7988////////////////////////////
7989// CTRUE bit to L2.
7990// THis is the only bit going to
7991// the arbiter as part of the instr.
7992// from misbuf.
7993////////////////////////////
7994
7995
7996assign l2_pick_read_ctrue = |( picker_out_d1 & mb_ctrue ) ;
7997
7998l2t_misbuf_ctl_msff_ctl_macro__en_1__width_1 ff_read_reg_ctrue_in
7999 (.din(l2_pick_read_ctrue),
8000 .scan_in(ff_read_reg_ctrue_in_scanin),
8001 .scan_out(ff_read_reg_ctrue_in_scanout),
8002 .en(l2_pick_d1), .l1clk(l1clk),
8003 .dout(misbuf_arbdp_ctrue_px2),
8004 .siclk(siclk),
8005 .soclk(soclk)
8006);
8007
8008
8009
8010//////////////////////////////////////////////////////////////////
8011// Interface with DRAM:
8012// An entry with mcu_ready is picked to issue a request to
8013// DRAM. If it is determined in cycle X that there is atleast one
8014// mcu_ready entry in the MBF, then the pick in cycle X+1 is
8015// reserved for issue to DRAM. Unless the following conditions are
8016// true:
8017// * Fill Buffer has no entry available.
8018// * Prev request is pending to DRAM
8019//
8020// Pipeline for RD requests to DRAM:
8021//-----------------------------------------------------------------
8022// #1 #2 #3 #4
8023//-----------------------------------------------------------------
8024// mcu_pick_prev pick mbtag rd 2-1 addr mux
8025// rd_req xmit
8026// rd_addr xmit
8027//
8028// write TAG,WR/RD,
8029// mbf entry,
8030// into FB
8031//
8032//-----------------------------------------------------------------
8033// In the best case, cycle #1 can coincide with C4 of a miss inst.
8034//
8035// The Dram ready bit is set in C8. Hence it can only be consumed
8036// in C9. mcu_pick_prev is set in C8 based on the mcu set
8037// condition. This condition was added on 2/3/2003
8038//////////////////////////////////////////////////////////////////
8039
8040l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_l2t_rd_ack_d1
8041 (.din(mcu_l2t_rd_ack), .l1clk(l1clk),
8042 .scan_in(ff_mcu_l2t_rd_ack_d1_scanin),
8043 .scan_out(ff_mcu_l2t_rd_ack_d1_scanout),
8044 .dout(mcu_l2t_rd_ack_d1),
8045 .siclk(siclk),
8046 .soclk(soclk)
8047);
8048
8049// VUAD ecc changes
8050assign mcu_pick_prev = ~mcu_pick & // back to back picks not allowed.
8051 ~mb_rewrite_en_c7 & // read and write in same cyc not allowed.
8052 ( mcu_l2t_rd_ack_d1 | // ack from Dram
8053 ~mcu_ack_pend_state ) & // request pending in mcu
8054 filbuf_misbuf_entry_avail & // fill buffer has entries
8055 ( |( mb_mcu_ready) |
8056 ( misbuf_mbdata_wr_en_c8 & ~(arb_pf_ice_inst_c8 | arb_vuad_ce_err_c8)
8057 & mcu_rdy_c8 ) ); // atleast one ready entry
8058
8059l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_filbuf_mcu_pick
8060 (.din(mcu_pick_prev), .l1clk(l1clk),
8061 .scan_in(ff_misbuf_filbuf_mcu_pick_scanin),
8062 .scan_out(ff_misbuf_filbuf_mcu_pick_scanout),
8063 .dout(misbuf_filbuf_mcu_pick),
8064 .siclk(siclk),
8065 .soclk(soclk)
8066);
8067
8068l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_pick
8069 (.din(mcu_pick_prev), .l1clk(l1clk),
8070 .scan_in(ff_mcu_pick_scanin),
8071 .scan_out(ff_mcu_pick_scanout),
8072 .dout(mcu_pick),
8073 .siclk(siclk),
8074 .soclk(soclk)
8075);
8076
8077l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_pick_2
8078 (.din(mcu_pick_prev), .l1clk(l1clk),
8079 .scan_in(ff_mcu_pick_2_scanin),
8080 .scan_out(ff_mcu_pick_2_scanout),
8081 .dout(mcu_pick_2),
8082 .siclk(siclk),
8083 .soclk(soclk)
8084);
8085
8086
8087
8088l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_pick_d1
8089 (.din(mcu_pick), .l1clk(l1clk),
8090 .scan_in(ff_mcu_pick_d1_scanin),
8091 .scan_out(ff_mcu_pick_d1_scanout),
8092 .dout(mcu_pick_d1),
8093 .siclk(siclk),
8094 .soclk(soclk)
8095);
8096
8097l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_pick_d2
8098 (.din(mcu_pick_d1), .l1clk(l1clk),
8099 .scan_in(ff_mcu_pick_d2_scanin),
8100 .scan_out(ff_mcu_pick_d2_scanout),
8101 .dout(mcu_pick_d2),
8102 .siclk(siclk),
8103 .soclk(soclk)
8104);
8105
8106assign misbuf_arb_mcurd_en = mcu_pick_d1;
8107
8108assign l2t_mcu_rd_req = mcu_pick_d2 ;
8109
8110
8111assign dummy_req_d1 = |( mb_bis & picker_out_d1 ) & mcu_pick_d1 ;
8112
8113l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_dummy_req_d2
8114 (.din(dummy_req_d1), .l1clk(l1clk),
8115 .scan_in(ff_dummy_req_d2_scanin),
8116 .scan_out(ff_dummy_req_d2_scanout),
8117 .dout(dummy_req_d2),
8118 .siclk(siclk),
8119 .soclk(soclk)
8120);
8121
8122assign l2t_mcu_rd_dummy_req = dummy_req_d2 ;
8123
8124
8125
8126assign mcu_ack_pending_in = ( mcu_ack_pend_state |
8127 mcu_pick ) &
8128 ~mcu_l2t_rd_ack_d1 ;
8129
8130l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_mcu_ack_pend_state // sync reset active low
8131 (.din(mcu_ack_pending_in), .l1clk(l1clk),
8132 .scan_in(ff_mcu_ack_pend_state_scanin),
8133 .scan_out(ff_mcu_ack_pend_state_scanout),
8134 .clr(~dbb_rst_l),
8135 .dout(mcu_ack_pend_state),
8136 .siclk(siclk),
8137 .soclk(soclk)
8138);
8139
8140
8141////////////////////////////////////////////////////////////////////
8142// Miss Buffer to Fill Buffer Miss Interface.
8143//
8144// The fields required for processing a miss in the Fill Buffer are
8145// written in two stages:
8146// 1) When it is picked for mcu issue i.e. during fill buffer insertion
8147// 2) When an eviction is performed.
8148//
8149// THe following Bits are used for saving the fields required
8150// by the Fill Buffer for miss processing that may not be available
8151// at the time of fill Buffer insertion.
8152//
8153// WAY, FBID, WAY_VLD and FBID_VLD
8154//
8155// Fill Buffer id valid is asserted in the d2 cycle of a mcu_pick
8156// IN the same cycle FBID is written in misbuf.
8157//
8158// WAY and way_vld are asserted in the C4 cycle of an eviction
8159// operation.
8160//
8161// Prioritized(FBID_VLD and WAY_VLD) is used to mux out the
8162// WAY and FBID fields from the selected miss buffer entry.
8163// Also, this one hot vector is used for resetting FBID_VLD & WAY_VLD.
8164////////////////////////////////////////////////////////////////////
8165
8166//////////////
8167// WAY FIELD: This Field needs to be maintained in misbuf
8168// WAY is stored into the WAY FIELD when an eviction
8169// operation completes and gets a way allocated for
8170// a Miss in the Miss Buffer.
8171// Needs to be used in conjunction with EVICT_DONE
8172// which is synonymous with "way valid"
8173//
8174// Written in the C4 cycle of an eviction operation.
8175/////////////
8176
8177assign evict_vld_c3 = evict_vld_unqual_c3 & ~arb_pf_ice_inst_c3 &
8178 ~tag_misbuf_par_err_c3 & ~arb_vuad_ce_err_c3; // in case of vuad ce, also disable
8179 // setting of mb_way_vld[31:0] on an
8180 // eviction as the eviction will be
8181 // replayed
8182
8183l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_evict_vld_c4
8184 (.din(evict_vld_c3), .l1clk(l1clk),
8185 .scan_in(ff_evict_vld_c4_scanin),
8186 .scan_out(ff_evict_vld_c4_scanout),
8187 .dout(evict_vld_c4),
8188 .siclk(siclk),
8189 .soclk(soclk)
8190);
8191
8192assign dec_wr_wl_c4[0] = ( enc_data_wr_wl_c4==5'd0 ) & evict_vld_c4 ;
8193assign dec_wr_wl_c4[1] = ( enc_data_wr_wl_c4==5'd1 ) & evict_vld_c4 ;
8194assign dec_wr_wl_c4[2] = ( enc_data_wr_wl_c4==5'd2 ) & evict_vld_c4 ;
8195assign dec_wr_wl_c4[3] = ( enc_data_wr_wl_c4==5'd3 ) & evict_vld_c4 ;
8196assign dec_wr_wl_c4[4] = ( enc_data_wr_wl_c4==5'd4 ) & evict_vld_c4 ;
8197assign dec_wr_wl_c4[5] = ( enc_data_wr_wl_c4==5'd5 ) & evict_vld_c4 ;
8198assign dec_wr_wl_c4[6] = ( enc_data_wr_wl_c4==5'd6 ) & evict_vld_c4 ;
8199assign dec_wr_wl_c4[7] = ( enc_data_wr_wl_c4==5'd7 ) & evict_vld_c4 ;
8200assign dec_wr_wl_c4[8] = ( enc_data_wr_wl_c4==5'd8 ) & evict_vld_c4 ;
8201assign dec_wr_wl_c4[9] = ( enc_data_wr_wl_c4==5'd9 ) & evict_vld_c4 ;
8202assign dec_wr_wl_c4[10] = ( enc_data_wr_wl_c4==5'd10 ) & evict_vld_c4 ;
8203assign dec_wr_wl_c4[11] = ( enc_data_wr_wl_c4==5'd11 ) & evict_vld_c4 ;
8204assign dec_wr_wl_c4[12] = ( enc_data_wr_wl_c4==5'd12 ) & evict_vld_c4 ;
8205assign dec_wr_wl_c4[13] = ( enc_data_wr_wl_c4==5'd13 ) & evict_vld_c4 ;
8206assign dec_wr_wl_c4[14] = ( enc_data_wr_wl_c4==5'd14 ) & evict_vld_c4 ;
8207assign dec_wr_wl_c4[15] = ( enc_data_wr_wl_c4==5'd15 ) & evict_vld_c4 ;
8208assign dec_wr_wl_c4[16] = ( enc_data_wr_wl_c4 == 5'd16) & evict_vld_c4 ;
8209assign dec_wr_wl_c4[17] = ( enc_data_wr_wl_c4 == 5'd17) & evict_vld_c4 ;
8210assign dec_wr_wl_c4[18] = ( enc_data_wr_wl_c4 == 5'd18) & evict_vld_c4 ;
8211assign dec_wr_wl_c4[19] = ( enc_data_wr_wl_c4 == 5'd19) & evict_vld_c4 ;
8212assign dec_wr_wl_c4[20] = ( enc_data_wr_wl_c4 == 5'd20) & evict_vld_c4 ;
8213assign dec_wr_wl_c4[21] = ( enc_data_wr_wl_c4 == 5'd21) & evict_vld_c4 ;
8214assign dec_wr_wl_c4[22] = ( enc_data_wr_wl_c4 == 5'd22) & evict_vld_c4 ;
8215assign dec_wr_wl_c4[23] = ( enc_data_wr_wl_c4 == 5'd23) & evict_vld_c4 ;
8216assign dec_wr_wl_c4[24] = ( enc_data_wr_wl_c4 == 5'd24) & evict_vld_c4 ;
8217assign dec_wr_wl_c4[25] = ( enc_data_wr_wl_c4 == 5'd25) & evict_vld_c4 ;
8218assign dec_wr_wl_c4[26] = ( enc_data_wr_wl_c4 == 5'd26) & evict_vld_c4 ;
8219assign dec_wr_wl_c4[27] = ( enc_data_wr_wl_c4 == 5'd27) & evict_vld_c4 ;
8220assign dec_wr_wl_c4[28] = ( enc_data_wr_wl_c4 == 5'd28) & evict_vld_c4 ;
8221assign dec_wr_wl_c4[29] = ( enc_data_wr_wl_c4 == 5'd29) & evict_vld_c4 ;
8222assign dec_wr_wl_c4[30] = ( enc_data_wr_wl_c4 == 5'd30) & evict_vld_c4 ;
8223assign dec_wr_wl_c4[31] = ( enc_data_wr_wl_c4 == 5'd31) & evict_vld_c4 ;
8224
8225
8226
8227l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way0
8228 (.din(tag_lru_way_c4[3:0]),
8229
8230 .scan_in(ff_way0_scanin),
8231 .scan_out(ff_way0_scanout),
8232 .en(dec_wr_wl_c4[0]), .l1clk(l1clk), .dout(way0[3:0]),
8233 .siclk(siclk),
8234 .soclk(soclk));
8235l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way1
8236 (.din(tag_lru_way_c4[3:0]),
8237
8238 .scan_in(ff_way1_scanin),
8239 .scan_out(ff_way1_scanout),
8240 .en(dec_wr_wl_c4[1]), .l1clk(l1clk), .dout(way1[3:0]),
8241 .siclk(siclk),
8242 .soclk(soclk));
8243l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way2
8244 (.din(tag_lru_way_c4[3:0]),
8245
8246 .scan_in(ff_way2_scanin),
8247 .scan_out(ff_way2_scanout),
8248 .en(dec_wr_wl_c4[2]), .l1clk(l1clk), .dout(way2[3:0]),
8249 .siclk(siclk),
8250 .soclk(soclk));
8251l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way3
8252 (.din(tag_lru_way_c4[3:0]),
8253
8254 .scan_in(ff_way3_scanin),
8255 .scan_out(ff_way3_scanout),
8256 .en(dec_wr_wl_c4[3]), .l1clk(l1clk), .dout(way3[3:0]),
8257 .siclk(siclk),
8258 .soclk(soclk));
8259l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way4
8260 (.din(tag_lru_way_c4[3:0]),
8261
8262 .scan_in(ff_way4_scanin),
8263 .scan_out(ff_way4_scanout),
8264 .en(dec_wr_wl_c4[4]), .l1clk(l1clk), .dout(way4[3:0]),
8265 .siclk(siclk),
8266 .soclk(soclk));
8267l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way5
8268 (.din(tag_lru_way_c4[3:0]),
8269
8270 .scan_in(ff_way5_scanin),
8271 .scan_out(ff_way5_scanout),
8272 .en(dec_wr_wl_c4[5]), .l1clk(l1clk), .dout(way5[3:0]),
8273 .siclk(siclk),
8274 .soclk(soclk));
8275l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way6
8276 (.din(tag_lru_way_c4[3:0]),
8277
8278 .scan_in(ff_way6_scanin),
8279 .scan_out(ff_way6_scanout),
8280 .en(dec_wr_wl_c4[6]), .l1clk(l1clk), .dout(way6[3:0]),
8281 .siclk(siclk),
8282 .soclk(soclk));
8283l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way7
8284 (.din(tag_lru_way_c4[3:0]),
8285
8286 .scan_in(ff_way7_scanin),
8287 .scan_out(ff_way7_scanout),
8288 .en(dec_wr_wl_c4[7]), .l1clk(l1clk), .dout(way7[3:0]),
8289 .siclk(siclk),
8290 .soclk(soclk));
8291l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way8
8292 (.din(tag_lru_way_c4[3:0]),
8293
8294 .scan_in(ff_way8_scanin),
8295 .scan_out(ff_way8_scanout),
8296 .en(dec_wr_wl_c4[8]), .l1clk(l1clk), .dout(way8[3:0]),
8297 .siclk(siclk),
8298 .soclk(soclk));
8299l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way9
8300 (.din(tag_lru_way_c4[3:0]),
8301
8302 .scan_in(ff_way9_scanin),
8303 .scan_out(ff_way9_scanout),
8304 .en(dec_wr_wl_c4[9]), .l1clk(l1clk), .dout(way9[3:0]),
8305 .siclk(siclk),
8306 .soclk(soclk));
8307l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way10
8308 (.din(tag_lru_way_c4[3:0]),
8309
8310 .scan_in(ff_way10_scanin),
8311 .scan_out(ff_way10_scanout),
8312 .en(dec_wr_wl_c4[10]), .l1clk(l1clk), .dout(way10[3:0]),
8313 .siclk(siclk),
8314 .soclk(soclk));
8315l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way11
8316 (.din(tag_lru_way_c4[3:0]),
8317
8318 .scan_in(ff_way11_scanin),
8319 .scan_out(ff_way11_scanout),
8320 .en(dec_wr_wl_c4[11]), .l1clk(l1clk), .dout(way11[3:0]),
8321 .siclk(siclk),
8322 .soclk(soclk));
8323l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way12
8324 (.din(tag_lru_way_c4[3:0]),
8325
8326 .scan_in(ff_way12_scanin),
8327 .scan_out(ff_way12_scanout),
8328 .en(dec_wr_wl_c4[12]), .l1clk(l1clk), .dout(way12[3:0]),
8329 .siclk(siclk),
8330 .soclk(soclk));
8331l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way13
8332 (.din(tag_lru_way_c4[3:0]),
8333
8334 .scan_in(ff_way13_scanin),
8335 .scan_out(ff_way13_scanout),
8336 .en(dec_wr_wl_c4[13]), .l1clk(l1clk), .dout(way13[3:0]),
8337 .siclk(siclk),
8338 .soclk(soclk));
8339l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way14
8340 (.din(tag_lru_way_c4[3:0]),
8341
8342 .scan_in(ff_way14_scanin),
8343 .scan_out(ff_way14_scanout),
8344 .en(dec_wr_wl_c4[14]), .l1clk(l1clk), .dout(way14[3:0]),
8345 .siclk(siclk),
8346 .soclk(soclk));
8347l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way15
8348 (.din(tag_lru_way_c4[3:0]),
8349
8350 .scan_in(ff_way15_scanin),
8351 .scan_out(ff_way15_scanout),
8352 .en(dec_wr_wl_c4[15]), .l1clk(l1clk), .dout(way15[3:0]),
8353 .siclk(siclk),
8354 .soclk(soclk));
8355
8356// // BS & SR 11/04/03, MB grows to 32
8357l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way16
8358 (
8359 .scan_in(ff_way16_scanin),
8360 .scan_out(ff_way16_scanout),
8361 .din(tag_lru_way_c4[3:0]),
8362 .en(dec_wr_wl_c4[16]),
8363 .l1clk(l1clk),
8364 .dout(way16[3:0]),
8365 .siclk(siclk),
8366 .soclk(soclk)
8367
8368);
8369
8370l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way17
8371 (
8372 .scan_in(ff_way17_scanin),
8373 .scan_out(ff_way17_scanout),
8374 .din(tag_lru_way_c4[3:0]),
8375 .en(dec_wr_wl_c4[17]),
8376 .l1clk(l1clk),
8377 .dout(way17[3:0]),
8378 .siclk(siclk),
8379 .soclk(soclk)
8380
8381);
8382
8383l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way18
8384 (
8385 .scan_in(ff_way18_scanin),
8386 .scan_out(ff_way18_scanout),
8387 .din(tag_lru_way_c4[3:0]),
8388 .en(dec_wr_wl_c4[18]),
8389 .l1clk(l1clk),
8390 .dout(way18[3:0]),
8391 .siclk(siclk),
8392 .soclk(soclk)
8393
8394);
8395
8396l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way19
8397 (
8398 .scan_in(ff_way19_scanin),
8399 .scan_out(ff_way19_scanout),
8400 .din(tag_lru_way_c4[3:0]),
8401 .en(dec_wr_wl_c4[19]),
8402 .l1clk(l1clk),
8403 .dout(way19[3:0]),
8404 .siclk(siclk),
8405 .soclk(soclk)
8406
8407);
8408
8409l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way20
8410 (
8411 .scan_in(ff_way20_scanin),
8412 .scan_out(ff_way20_scanout),
8413 .din(tag_lru_way_c4[3:0]),
8414 .en(dec_wr_wl_c4[20]),
8415 .l1clk(l1clk),
8416 .dout(way20[3:0]),
8417 .siclk(siclk),
8418 .soclk(soclk)
8419
8420);
8421
8422l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way21
8423 (
8424 .scan_in(ff_way21_scanin),
8425 .scan_out(ff_way21_scanout),
8426 .din(tag_lru_way_c4[3:0]),
8427 .en(dec_wr_wl_c4[21]),
8428 .l1clk(l1clk),
8429 .dout(way21[3:0]),
8430 .siclk(siclk),
8431 .soclk(soclk)
8432
8433);
8434
8435l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way22
8436 (
8437 .scan_in(ff_way22_scanin),
8438 .scan_out(ff_way22_scanout),
8439 .din(tag_lru_way_c4[3:0]),
8440 .en(dec_wr_wl_c4[22]),
8441 .l1clk(l1clk),
8442 .dout(way22[3:0]),
8443 .siclk(siclk),
8444 .soclk(soclk)
8445
8446);
8447
8448l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way23
8449 (
8450 .scan_in(ff_way23_scanin),
8451 .scan_out(ff_way23_scanout),
8452 .din(tag_lru_way_c4[3:0]),
8453 .en(dec_wr_wl_c4[23]),
8454 .l1clk(l1clk),
8455 .dout(way23[3:0]),
8456 .siclk(siclk),
8457 .soclk(soclk)
8458
8459);
8460
8461l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way24
8462 (
8463 .scan_in(ff_way24_scanin),
8464 .scan_out(ff_way24_scanout),
8465 .din(tag_lru_way_c4[3:0]),
8466 .en(dec_wr_wl_c4[24]),
8467 .l1clk(l1clk),
8468 .dout(way24[3:0]),
8469 .siclk(siclk),
8470 .soclk(soclk)
8471
8472);
8473
8474l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way25
8475 (
8476 .scan_in(ff_way25_scanin),
8477 .scan_out(ff_way25_scanout),
8478 .din(tag_lru_way_c4[3:0]),
8479 .en(dec_wr_wl_c4[25]),
8480 .l1clk(l1clk),
8481 .dout(way25[3:0]),
8482 .siclk(siclk),
8483 .soclk(soclk)
8484
8485);
8486
8487l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way26
8488 (
8489 .scan_in(ff_way26_scanin),
8490 .scan_out(ff_way26_scanout),
8491 .din(tag_lru_way_c4[3:0]),
8492 .en(dec_wr_wl_c4[26]),
8493 .l1clk(l1clk),
8494 .dout(way26[3:0]),
8495 .siclk(siclk),
8496 .soclk(soclk)
8497
8498);
8499
8500l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way27
8501 (
8502 .scan_in(ff_way27_scanin),
8503 .scan_out(ff_way27_scanout),
8504 .din(tag_lru_way_c4[3:0]),
8505 .en(dec_wr_wl_c4[27]),
8506 .l1clk(l1clk),
8507 .dout(way27[3:0]),
8508 .siclk(siclk),
8509 .soclk(soclk)
8510
8511);
8512
8513l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way28
8514 (
8515 .scan_in(ff_way28_scanin),
8516 .scan_out(ff_way28_scanout),
8517 .din(tag_lru_way_c4[3:0]),
8518 .en(dec_wr_wl_c4[28]),
8519 .l1clk(l1clk),
8520 .dout(way28[3:0]),
8521 .siclk(siclk),
8522 .soclk(soclk)
8523
8524);
8525
8526l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way29
8527 (
8528 .scan_in(ff_way29_scanin),
8529 .scan_out(ff_way29_scanout),
8530 .din(tag_lru_way_c4[3:0]),
8531 .en(dec_wr_wl_c4[29]),
8532 .l1clk(l1clk),
8533 .dout(way29[3:0]),
8534 .siclk(siclk),
8535 .soclk(soclk)
8536
8537);
8538
8539l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way30
8540 (
8541 .scan_in(ff_way30_scanin),
8542 .scan_out(ff_way30_scanout),
8543 .din(tag_lru_way_c4[3:0]),
8544 .en(dec_wr_wl_c4[30]),
8545 .l1clk(l1clk),
8546 .dout(way30[3:0]),
8547 .siclk(siclk),
8548 .soclk(soclk)
8549
8550);
8551
8552l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way31
8553 (
8554 .scan_in(ff_way31_scanin),
8555 .scan_out(ff_way31_scanout),
8556 .din(tag_lru_way_c4[3:0]),
8557 .en(dec_wr_wl_c4[31]),
8558 .l1clk(l1clk),
8559 .dout(way31[3:0]),
8560 .siclk(siclk),
8561 .soclk(soclk)
8562
8563);
8564
8565////////////
8566// WAY_VLD bit
8567// set when an eviction is mbist_done in the C4 cycle
8568// of an eviction packet and reset when the evicted way
8569// is written into the Fill Buffer.
8570//
8571// For pf ice instruction, the mb_way_vld should be cleared
8572// in the eviction pass
8573////////////
8574l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_arb_pf_ice_inst_c4
8575 (
8576 .scan_in(ff_arb_pf_ice_inst_c4_scanin),
8577 .scan_out(ff_arb_pf_ice_inst_c4_scanout),
8578 .dout (arb_pf_ice_inst_c3),
8579 .din (arb_pf_ice_inst_c2),
8580 .l1clk (l1clk),
8581 .siclk(siclk),
8582 .soclk(soclk)
8583 );
8584
8585assign mb_way_vld_in = ( mb_way_vld | dec_wr_wl_c4 ) &
8586 ~(mb_way_fb_vld_reset);
8587
8588l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_way_vld // sync reset active low
8589 (.din(mb_way_vld_in[31:0]), .l1clk(l1clk), // BS & SR 11/04/03, MB grows to 32
8590 .scan_in(ff_mb_way_vld_scanin),
8591 .scan_out(ff_mb_way_vld_scanout),
8592 .clr(~dbb_rst_l), .dout(mb_way_vld[31:0]),
8593 .siclk(siclk),
8594 .soclk(soclk)
8595);
8596
8597//////////////
8598// FBID FIELD:
8599// FBID is tracked in the Miss Buffer
8600// to perform the write of Miss fields in FB
8601// asynchronous with the mcu pick.
8602//
8603// For a No Fill entry, fbid vld is not set
8604// This is because way_vld will not be set for
8605// this instruction as it never makes an eviction
8606// pass.
8607//////////////
8608
8609
8610
8611assign dec_mcu_pick_d2 = picker_out_d2 & {32{mcu_pick_d2 & ~filbuf_misbuf_nofill_d2}} ; // BS & SR 11/04/03, MB grows to 32
8612
8613l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid0
8614 (.din(filbuf_misbuf_fbid_d2[2:0]),
8615
8616 .scan_in(ff_fbid0_scanin),
8617 .scan_out(ff_fbid0_scanout),
8618 .en(dec_mcu_pick_d2[0]), .l1clk(l1clk), .dout(fbid0[2:0]),
8619 .siclk(siclk),
8620 .soclk(soclk));
8621l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid1
8622 (.din(filbuf_misbuf_fbid_d2[2:0]),
8623
8624 .scan_in(ff_fbid1_scanin),
8625 .scan_out(ff_fbid1_scanout),
8626 .en(dec_mcu_pick_d2[1]), .l1clk(l1clk), .dout(fbid1[2:0]),
8627 .siclk(siclk),
8628 .soclk(soclk));
8629l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid2
8630 (.din(filbuf_misbuf_fbid_d2[2:0]),
8631
8632 .scan_in(ff_fbid2_scanin),
8633 .scan_out(ff_fbid2_scanout),
8634 .en(dec_mcu_pick_d2[2]), .l1clk(l1clk), .dout(fbid2[2:0]),
8635 .siclk(siclk),
8636 .soclk(soclk));
8637l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid3
8638 (.din(filbuf_misbuf_fbid_d2[2:0]),
8639
8640 .scan_in(ff_fbid3_scanin),
8641 .scan_out(ff_fbid3_scanout),
8642 .en(dec_mcu_pick_d2[3]), .l1clk(l1clk), .dout(fbid3[2:0]),
8643 .siclk(siclk),
8644 .soclk(soclk));
8645l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid4
8646 (.din(filbuf_misbuf_fbid_d2[2:0]),
8647
8648 .scan_in(ff_fbid4_scanin),
8649 .scan_out(ff_fbid4_scanout),
8650 .en(dec_mcu_pick_d2[4]), .l1clk(l1clk), .dout(fbid4[2:0]),
8651 .siclk(siclk),
8652 .soclk(soclk));
8653l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid5
8654 (.din(filbuf_misbuf_fbid_d2[2:0]),
8655
8656 .scan_in(ff_fbid5_scanin),
8657 .scan_out(ff_fbid5_scanout),
8658 .en(dec_mcu_pick_d2[5]), .l1clk(l1clk), .dout(fbid5[2:0]),
8659 .siclk(siclk),
8660 .soclk(soclk));
8661l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid6
8662 (.din(filbuf_misbuf_fbid_d2[2:0]),
8663
8664 .scan_in(ff_fbid6_scanin),
8665 .scan_out(ff_fbid6_scanout),
8666 .en(dec_mcu_pick_d2[6]), .l1clk(l1clk), .dout(fbid6[2:0]),
8667 .siclk(siclk),
8668 .soclk(soclk));
8669l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid7
8670 (.din(filbuf_misbuf_fbid_d2[2:0]),
8671
8672 .scan_in(ff_fbid7_scanin),
8673 .scan_out(ff_fbid7_scanout),
8674 .en(dec_mcu_pick_d2[7]), .l1clk(l1clk), .dout(fbid7[2:0]),
8675 .siclk(siclk),
8676 .soclk(soclk));
8677l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid8
8678 (.din(filbuf_misbuf_fbid_d2[2:0]),
8679
8680 .scan_in(ff_fbid8_scanin),
8681 .scan_out(ff_fbid8_scanout),
8682 .en(dec_mcu_pick_d2[8]), .l1clk(l1clk), .dout(fbid8[2:0]),
8683 .siclk(siclk),
8684 .soclk(soclk));
8685l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid9
8686 (.din(filbuf_misbuf_fbid_d2[2:0]),
8687
8688 .scan_in(ff_fbid9_scanin),
8689 .scan_out(ff_fbid9_scanout),
8690 .en(dec_mcu_pick_d2[9]), .l1clk(l1clk), .dout(fbid9[2:0]),
8691 .siclk(siclk),
8692 .soclk(soclk));
8693l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid10
8694 (.din(filbuf_misbuf_fbid_d2[2:0]),
8695
8696 .scan_in(ff_fbid10_scanin),
8697 .scan_out(ff_fbid10_scanout),
8698 .en(dec_mcu_pick_d2[10]), .l1clk(l1clk), .dout(fbid10[2:0]),
8699 .siclk(siclk),
8700 .soclk(soclk));
8701l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid11
8702 (.din(filbuf_misbuf_fbid_d2[2:0]),
8703
8704 .scan_in(ff_fbid11_scanin),
8705 .scan_out(ff_fbid11_scanout),
8706 .en(dec_mcu_pick_d2[11]), .l1clk(l1clk), .dout(fbid11[2:0]),
8707 .siclk(siclk),
8708 .soclk(soclk));
8709l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid12
8710 (.din(filbuf_misbuf_fbid_d2[2:0]),
8711
8712 .scan_in(ff_fbid12_scanin),
8713 .scan_out(ff_fbid12_scanout),
8714 .en(dec_mcu_pick_d2[12]), .l1clk(l1clk), .dout(fbid12[2:0]),
8715 .siclk(siclk),
8716 .soclk(soclk));
8717l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid13
8718 (.din(filbuf_misbuf_fbid_d2[2:0]),
8719
8720 .scan_in(ff_fbid13_scanin),
8721 .scan_out(ff_fbid13_scanout),
8722 .en(dec_mcu_pick_d2[13]), .l1clk(l1clk), .dout(fbid13[2:0]),
8723 .siclk(siclk),
8724 .soclk(soclk));
8725l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid14
8726 (.din(filbuf_misbuf_fbid_d2[2:0]),
8727
8728 .scan_in(ff_fbid14_scanin),
8729 .scan_out(ff_fbid14_scanout),
8730 .en(dec_mcu_pick_d2[14]), .l1clk(l1clk), .dout(fbid14[2:0]),
8731 .siclk(siclk),
8732 .soclk(soclk));
8733l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid15
8734 (.din(filbuf_misbuf_fbid_d2[2:0]),
8735
8736 .scan_in(ff_fbid15_scanin),
8737 .scan_out(ff_fbid15_scanout),
8738 .en(dec_mcu_pick_d2[15]), .l1clk(l1clk), .dout(fbid15[2:0]),
8739 .siclk(siclk),
8740 .soclk(soclk));
8741// BS & SR 11/04/03, MB grows to 32
8742l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid16
8743 (
8744 .scan_in(ff_fbid16_scanin),
8745 .scan_out(ff_fbid16_scanout),
8746 .din(filbuf_misbuf_fbid_d2[2:0]),
8747 .en(dec_mcu_pick_d2[16]),
8748 .l1clk(l1clk),
8749 .dout(fbid16[2:0]),
8750 .siclk(siclk),
8751 .soclk(soclk)
8752
8753);
8754
8755l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid17
8756 (
8757 .scan_in(ff_fbid17_scanin),
8758 .scan_out(ff_fbid17_scanout),
8759 .din(filbuf_misbuf_fbid_d2[2:0]),
8760 .en(dec_mcu_pick_d2[17]),
8761 .l1clk(l1clk),
8762 .dout(fbid17[2:0]),
8763 .siclk(siclk),
8764 .soclk(soclk)
8765
8766);
8767
8768l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid18
8769 (
8770 .scan_in(ff_fbid18_scanin),
8771 .scan_out(ff_fbid18_scanout),
8772 .din(filbuf_misbuf_fbid_d2[2:0]),
8773 .en(dec_mcu_pick_d2[18]),
8774 .l1clk(l1clk),
8775 .dout(fbid18[2:0]),
8776 .siclk(siclk),
8777 .soclk(soclk)
8778
8779);
8780
8781l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid19
8782 (
8783 .scan_in(ff_fbid19_scanin),
8784 .scan_out(ff_fbid19_scanout),
8785 .din(filbuf_misbuf_fbid_d2[2:0]),
8786 .en(dec_mcu_pick_d2[19]),
8787 .l1clk(l1clk),
8788 .dout(fbid19[2:0]),
8789 .siclk(siclk),
8790 .soclk(soclk)
8791
8792);
8793
8794l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid20
8795 (
8796 .scan_in(ff_fbid20_scanin),
8797 .scan_out(ff_fbid20_scanout),
8798 .din(filbuf_misbuf_fbid_d2[2:0]),
8799 .en(dec_mcu_pick_d2[20]),
8800 .l1clk(l1clk),
8801 .dout(fbid20[2:0]),
8802 .siclk(siclk),
8803 .soclk(soclk)
8804
8805);
8806
8807l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid21
8808 (
8809 .scan_in(ff_fbid21_scanin),
8810 .scan_out(ff_fbid21_scanout),
8811 .din(filbuf_misbuf_fbid_d2[2:0]),
8812 .en(dec_mcu_pick_d2[21]),
8813 .l1clk(l1clk),
8814 .dout(fbid21[2:0]),
8815 .siclk(siclk),
8816 .soclk(soclk)
8817
8818);
8819
8820l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid22
8821 (
8822 .scan_in(ff_fbid22_scanin),
8823 .scan_out(ff_fbid22_scanout),
8824 .din(filbuf_misbuf_fbid_d2[2:0]),
8825 .en(dec_mcu_pick_d2[22]),
8826 .l1clk(l1clk),
8827 .dout(fbid22[2:0]),
8828 .siclk(siclk),
8829 .soclk(soclk)
8830
8831);
8832
8833l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid23
8834 (
8835 .scan_in(ff_fbid23_scanin),
8836 .scan_out(ff_fbid23_scanout),
8837 .din(filbuf_misbuf_fbid_d2[2:0]),
8838 .en(dec_mcu_pick_d2[23]),
8839 .l1clk(l1clk),
8840 .dout(fbid23[2:0]),
8841 .siclk(siclk),
8842 .soclk(soclk)
8843
8844);
8845
8846l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid24
8847 (
8848 .scan_in(ff_fbid24_scanin),
8849 .scan_out(ff_fbid24_scanout),
8850 .din(filbuf_misbuf_fbid_d2[2:0]),
8851 .en(dec_mcu_pick_d2[24]),
8852 .l1clk(l1clk),
8853 .dout(fbid24[2:0]),
8854 .siclk(siclk),
8855 .soclk(soclk)
8856
8857);
8858
8859l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid25
8860 (
8861 .scan_in(ff_fbid25_scanin),
8862 .scan_out(ff_fbid25_scanout),
8863 .din(filbuf_misbuf_fbid_d2[2:0]),
8864 .en(dec_mcu_pick_d2[25]),
8865 .l1clk(l1clk),
8866 .dout(fbid25[2:0]),
8867 .siclk(siclk),
8868 .soclk(soclk)
8869
8870);
8871
8872l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid26
8873 (
8874 .scan_in(ff_fbid26_scanin),
8875 .scan_out(ff_fbid26_scanout),
8876 .din(filbuf_misbuf_fbid_d2[2:0]),
8877 .en(dec_mcu_pick_d2[26]),
8878 .l1clk(l1clk),
8879 .dout(fbid26[2:0]),
8880 .siclk(siclk),
8881 .soclk(soclk)
8882
8883);
8884
8885l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid27
8886 (
8887 .scan_in(ff_fbid27_scanin),
8888 .scan_out(ff_fbid27_scanout),
8889 .din(filbuf_misbuf_fbid_d2[2:0]),
8890 .en(dec_mcu_pick_d2[27]),
8891 .l1clk(l1clk),
8892 .dout(fbid27[2:0]),
8893 .siclk(siclk),
8894 .soclk(soclk)
8895
8896);
8897
8898l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid28
8899 (
8900 .scan_in(ff_fbid28_scanin),
8901 .scan_out(ff_fbid28_scanout),
8902 .din(filbuf_misbuf_fbid_d2[2:0]),
8903 .en(dec_mcu_pick_d2[28]),
8904 .l1clk(l1clk),
8905 .dout(fbid28[2:0]),
8906 .siclk(siclk),
8907 .soclk(soclk)
8908
8909);
8910
8911l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid29
8912 (
8913 .scan_in(ff_fbid29_scanin),
8914 .scan_out(ff_fbid29_scanout),
8915 .din(filbuf_misbuf_fbid_d2[2:0]),
8916 .en(dec_mcu_pick_d2[29]),
8917 .l1clk(l1clk),
8918 .dout(fbid29[2:0]),
8919 .siclk(siclk),
8920 .soclk(soclk)
8921
8922);
8923
8924l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid30
8925 (
8926 .scan_in(ff_fbid30_scanin),
8927 .scan_out(ff_fbid30_scanout),
8928 .din(filbuf_misbuf_fbid_d2[2:0]),
8929 .en(dec_mcu_pick_d2[30]),
8930 .l1clk(l1clk),
8931 .dout(fbid30[2:0]),
8932 .siclk(siclk),
8933 .soclk(soclk)
8934
8935);
8936
8937l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 ff_fbid31
8938 (
8939 .scan_in(ff_fbid31_scanin),
8940 .scan_out(ff_fbid31_scanout),
8941 .din(filbuf_misbuf_fbid_d2[2:0]),
8942 .en(dec_mcu_pick_d2[31]),
8943 .l1clk(l1clk),
8944 .dout(fbid31[2:0]),
8945 .siclk(siclk),
8946 .soclk(soclk)
8947
8948);
8949
8950
8951
8952////////////
8953// FBID_VLD
8954// set when mcu _pick_d2 is asserted.
8955// to indicate that the entry in the Miss Buffer
8956// has been picked for requesting to mcu
8957////////////
8958
8959// bug #2196.
8960// a ld64 miss or any operation in
8961// Off mode, will cause fbid_vld to be set
8962// but the "mb_way_fb_vld_reset" reset condition
8963// will never happen. This causes the bit to have
8964// stale state. Resetting now with fbid vld.
8965assign mb_fbid_vld_in = ( mb_fbid_vld | dec_mcu_pick_d2 ) &
8966 ~(mb_way_fb_vld_reset |
8967 reset_valid_bit_c3) ;
8968
8969l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_fbid_vld // sync reset active low , BS & SR 11/04/03, MB grows to 32
8970 (.din(mb_fbid_vld_in[31:0]), .l1clk(l1clk),
8971 .scan_in(ff_mb_fbid_vld_scanin),
8972 .scan_out(ff_mb_fbid_vld_scanout),
8973 .clr(~dbb_rst_l), .dout(mb_fbid_vld[31:0]),
8974 .siclk(siclk),
8975 .soclk(soclk)
8976);
8977
8978////////////
8979// Muxing out way and fbid for
8980// writing into FBctl
8981////////////
8982
8983
8984assign way_fbid_vld = ( mb_fbid_vld & mb_way_vld) ;
8985
8986assign way_fbid_rd_vld_prev = |(way_fbid_vld) ;
8987
8988l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_filbuf_way_fbid_vld
8989 (.din(way_fbid_rd_vld_prev), .l1clk(l1clk),
8990 .scan_in(ff_misbuf_filbuf_way_fbid_vld_scanin),
8991 .scan_out(ff_misbuf_filbuf_way_fbid_vld_scanout),
8992 .dout(misbuf_filbuf_way_fbid_vld),
8993 .siclk(siclk),
8994 .soclk(soclk)
8995);
8996
8997
8998// Needs to be coded differently for timing.
8999
9000assign mb_way_fb_vld_tmp[0] = way_fbid_vld[0] ;
9001assign mb_way_fb_vld_tmp[1] = way_fbid_vld[1] & ~(way_fbid_vld[0]);
9002assign mb_way_fb_vld_tmp[2] = way_fbid_vld[2] & ~(|(way_fbid_vld[1:0])) ;
9003assign mb_way_fb_vld_tmp[3] = way_fbid_vld[3] & ~(|(way_fbid_vld[2:0])) ;
9004assign fbsel_def_0123 = ~(|way_fbid_vld[2:0]);
9005
9006assign mb_way_fb_vld_tmp[4] = way_fbid_vld[4] ;
9007assign mb_way_fb_vld_tmp[5] = way_fbid_vld[5] & ~(way_fbid_vld[4]);
9008assign mb_way_fb_vld_tmp[6] = way_fbid_vld[6] & ~(|(way_fbid_vld[5:4])) ;
9009assign mb_way_fb_vld_tmp[7] = way_fbid_vld[7] & ~(|(way_fbid_vld[6:4])) ;
9010assign fbsel_def_4567 = ~(|way_fbid_vld[6:4]);
9011
9012assign mb_way_fb_vld_tmp[8] = way_fbid_vld[8] ;
9013assign mb_way_fb_vld_tmp[9] = way_fbid_vld[9] & ~(way_fbid_vld[8]);
9014assign mb_way_fb_vld_tmp[10] = way_fbid_vld[10] & ~(|(way_fbid_vld[9:8])) ;
9015assign mb_way_fb_vld_tmp[11] = way_fbid_vld[11] & ~(|(way_fbid_vld[10:8])) ;
9016assign fbsel_def_89ab = ~(|way_fbid_vld[10:8]);
9017
9018assign mb_way_fb_vld_tmp[12] = way_fbid_vld[12] ;
9019assign mb_way_fb_vld_tmp[13] = way_fbid_vld[13] & ~(way_fbid_vld[12]);
9020assign mb_way_fb_vld_tmp[14] = way_fbid_vld[14] & ~(|(way_fbid_vld[13:12])) ;
9021assign mb_way_fb_vld_tmp[15] = way_fbid_vld[15] & ~(|(way_fbid_vld[14:12])) ;
9022assign fbsel_def_cdef = ~(|way_fbid_vld[14:12]);
9023
9024// BS & SR 11/04/03, MB grows to 32
9025assign mb_way_fb_vld_tmp[16] = way_fbid_vld[16] ;
9026assign mb_way_fb_vld_tmp[17] = way_fbid_vld[17] & ~(way_fbid_vld[16]);
9027assign mb_way_fb_vld_tmp[18] = way_fbid_vld[18] & ~(|(way_fbid_vld[17:16])) ;
9028assign mb_way_fb_vld_tmp[19] = way_fbid_vld[19] & ~(|(way_fbid_vld[18:16])) ;
9029assign fbsel_def_a_0123 = ~(|way_fbid_vld[18:16]);
9030
9031assign mb_way_fb_vld_tmp[20] = way_fbid_vld[20] ;
9032assign mb_way_fb_vld_tmp[21] = way_fbid_vld[21] & ~(way_fbid_vld[20]);
9033assign mb_way_fb_vld_tmp[22] = way_fbid_vld[22] & ~(|(way_fbid_vld[21:20])) ;
9034assign mb_way_fb_vld_tmp[23] = way_fbid_vld[23] & ~(|(way_fbid_vld[22:20])) ;
9035assign fbsel_def_a_4567 = ~(|way_fbid_vld[22:20]);
9036
9037assign mb_way_fb_vld_tmp[24] = way_fbid_vld[24] ;
9038assign mb_way_fb_vld_tmp[25] = way_fbid_vld[25] & ~(way_fbid_vld[24]);
9039assign mb_way_fb_vld_tmp[26] = way_fbid_vld[26] & ~(|(way_fbid_vld[25:24])) ;
9040assign mb_way_fb_vld_tmp[27] = way_fbid_vld[27] & ~(|(way_fbid_vld[26:24])) ;
9041assign fbsel_def_a_89ab = ~(|way_fbid_vld[26:24]);
9042
9043assign mb_way_fb_vld_tmp[28] = way_fbid_vld[28] ;
9044assign mb_way_fb_vld_tmp[29] = way_fbid_vld[29] & ~(way_fbid_vld[28]);
9045assign mb_way_fb_vld_tmp[30] = way_fbid_vld[30] & ~(|(way_fbid_vld[29:28])) ;
9046assign mb_way_fb_vld_tmp[31] = way_fbid_vld[31] & ~(|(way_fbid_vld[30:28])) ;
9047assign fbsel_def_a_cdef = ~(|way_fbid_vld[30:28]);
9048
9049assign mb_way_fb_vld_tmp_0to3 = |( way_fbid_vld[3:0]) ;
9050assign mb_way_fb_vld_tmp_4to7 = |( way_fbid_vld[7:4]) ;
9051assign mb_way_fb_vld_tmp_8to11 = |( way_fbid_vld[11:8]) ;
9052assign mb_way_fb_vld_tmp_12to15 = |( way_fbid_vld[15:12]) ;
9053assign mb_way_fb_vld_tmp_16to19 = |( way_fbid_vld[19:16]) ;
9054assign mb_way_fb_vld_tmp_20to23 = |( way_fbid_vld[23:20]) ;
9055assign mb_way_fb_vld_tmp_24to27 = |( way_fbid_vld[27:24]) ;
9056//assign mb_way_fb_vld_tmp_28to31 = |( way_fbid_vld[31:28]) ;
9057
9058
9059// signal to reset way vld and fbid vld.
9060assign mb_way_fb_vld_reset[3:0] = mb_way_fb_vld_tmp[3:0] ;
9061assign mb_way_fb_vld_reset[7:4] = mb_way_fb_vld_tmp[7:4] &
9062 ~{4{mb_way_fb_vld_tmp_0to3}} ;
9063assign mb_way_fb_vld_reset[11:8] = mb_way_fb_vld_tmp[11:8] &
9064 ~{4{mb_way_fb_vld_tmp_0to3}} &
9065 ~{4{mb_way_fb_vld_tmp_4to7}};
9066assign mb_way_fb_vld_reset[15:12] = mb_way_fb_vld_tmp[15:12] &
9067 ~{4{mb_way_fb_vld_tmp_0to3}}
9068 & ~{4{mb_way_fb_vld_tmp_4to7}} &
9069 ~{4{mb_way_fb_vld_tmp_8to11}} ;
9070
9071// BS & SR 11/04/03, MB grows to 32
9072assign mb_way_fb_vld_reset[19:16] = mb_way_fb_vld_tmp[19:16] &
9073 ~{4{mb_way_fb_vld_tmp_0to3}} &
9074 ~{4{mb_way_fb_vld_tmp_4to7}} &
9075 ~{4{mb_way_fb_vld_tmp_8to11}} &
9076 ~{4{mb_way_fb_vld_tmp_12to15}} ;
9077
9078assign mb_way_fb_vld_reset[23:20] = mb_way_fb_vld_tmp[23:20] &
9079 ~{4{mb_way_fb_vld_tmp_0to3}} &
9080 ~{4{mb_way_fb_vld_tmp_4to7}} &
9081 ~{4{mb_way_fb_vld_tmp_8to11}} &
9082 ~{4{mb_way_fb_vld_tmp_12to15}} &
9083 ~{4{mb_way_fb_vld_tmp_16to19}};
9084
9085assign mb_way_fb_vld_reset[27:24] = mb_way_fb_vld_tmp[27:24] &
9086 ~{4{mb_way_fb_vld_tmp_0to3}} &
9087 ~{4{mb_way_fb_vld_tmp_4to7}} &
9088 ~{4{mb_way_fb_vld_tmp_8to11}} &
9089 ~{4{mb_way_fb_vld_tmp_12to15}} &
9090 ~{4{mb_way_fb_vld_tmp_16to19}} &
9091 ~{4{mb_way_fb_vld_tmp_20to23}};
9092
9093assign mb_way_fb_vld_reset[31:28] = mb_way_fb_vld_tmp[31:28] &
9094 ~{4{mb_way_fb_vld_tmp_0to3}} &
9095 ~{4{mb_way_fb_vld_tmp_4to7}} &
9096 ~{4{mb_way_fb_vld_tmp_8to11}} &
9097 ~{4{mb_way_fb_vld_tmp_12to15}} &
9098 ~{4{mb_way_fb_vld_tmp_16to19}} &
9099 ~{4{mb_way_fb_vld_tmp_20to23}} &
9100 ~{4{mb_way_fb_vld_tmp_24to27}};
9101
9102assign fbsel_0to3 = mb_way_fb_vld_tmp_0to3 ;
9103assign fbsel_4to7 = mb_way_fb_vld_tmp_4to7 & ~mb_way_fb_vld_tmp_0to3;
9104assign fbsel_8to11 = mb_way_fb_vld_tmp_8to11 & ~mb_way_fb_vld_tmp_0to3 &
9105 ~mb_way_fb_vld_tmp_4to7 ;
9106
9107
9108// BS & SR 11/04/03, MB grows to 32
9109
9110assign fbsel_15to12 = mb_way_fb_vld_tmp_12to15 &
9111 ~mb_way_fb_vld_tmp_8to11 &
9112 ~mb_way_fb_vld_tmp_0to3 &
9113 ~mb_way_fb_vld_tmp_4to7 ;
9114assign fbsel_19to16 = mb_way_fb_vld_tmp_16to19 &
9115 ~mb_way_fb_vld_tmp_12to15 &
9116 ~mb_way_fb_vld_tmp_8to11 &
9117 ~mb_way_fb_vld_tmp_0to3 &
9118 ~mb_way_fb_vld_tmp_4to7 ;
9119assign fbsel_23to20 = mb_way_fb_vld_tmp_20to23 &
9120 ~mb_way_fb_vld_tmp_16to19 &
9121 ~mb_way_fb_vld_tmp_12to15 &
9122 ~mb_way_fb_vld_tmp_8to11 &
9123 ~mb_way_fb_vld_tmp_0to3 &
9124 ~mb_way_fb_vld_tmp_4to7 ;
9125assign fbsel_27to24 = mb_way_fb_vld_tmp_24to27 &
9126 ~mb_way_fb_vld_tmp_20to23 &
9127 ~mb_way_fb_vld_tmp_16to19 &
9128 ~mb_way_fb_vld_tmp_12to15 &
9129 ~mb_way_fb_vld_tmp_8to11 &
9130 ~mb_way_fb_vld_tmp_0to3 &
9131 ~mb_way_fb_vld_tmp_4to7 ;
9132//assign fbsel_31to28 = mb_way_fb_vld_tmp_28to31 &
9133// ~mb_way_fb_vld_tmp_24to27 &
9134// ~mb_way_fb_vld_tmp_20to23 &
9135// ~mb_way_fb_vld_tmp_16to19 &
9136// ~mb_way_fb_vld_tmp_12to15 &
9137// ~mb_way_fb_vld_tmp_8to11 &
9138// ~mb_way_fb_vld_tmp_0to3 &
9139// ~mb_way_fb_vld_tmp_4to7 ;
9140
9141//assign fbsel_def_vld = ~( fbsel_0to3 | fbsel_4to7 | fbsel_8to11 | fbsel_15to12 | fbsel_19to16 |
9142// fbsel_27to24 ) ;
9143
9144assign fbsel_def_vld = ~( fbsel_0to3 | fbsel_4to7 | fbsel_8to11 | fbsel_15to12 | fbsel_19to16 |
9145 // fbsel_27to24 ) ; fix for bug 85990
9146 fbsel_23to20 | fbsel_27to24 ) ;
9147
9148
9149l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_0to3_d1
9150 (.din(fbsel_0to3), .l1clk(l1clk),
9151 .scan_in(ff_fbsel_0to3_d1_scanin),
9152 .scan_out(ff_fbsel_0to3_d1_scanout),
9153 .dout(fbsel_0to3_d1),
9154 .siclk(siclk),
9155 .soclk(soclk)
9156);
9157
9158l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_4to7_d1
9159 (.din(fbsel_4to7), .l1clk(l1clk),
9160 .scan_in(ff_fbsel_4to7_d1_scanin),
9161 .scan_out(ff_fbsel_4to7_d1_scanout),
9162 .dout(fbsel_4to7_d1),
9163 .siclk(siclk),
9164 .soclk(soclk)
9165);
9166
9167l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_8tob_d1
9168 (.din(fbsel_8to11), .l1clk(l1clk),
9169 .scan_in(ff_fbsel_8tob_d1_scanin),
9170 .scan_out(ff_fbsel_8tob_d1_scanout),
9171 .dout(fbsel_8to11_d1),
9172 .siclk(siclk),
9173 .soclk(soclk)
9174);
9175
9176
9177// BS & SR 11/04/03, MB grows to 32
9178l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_15to12_d1
9179 (.din(fbsel_15to12), .l1clk(l1clk),
9180 .scan_in(ff_fbsel_15to12_d1_scanin),
9181 .scan_out(ff_fbsel_15to12_d1_scanout),
9182 .dout(fbsel_15to12_d1),
9183 .siclk(siclk),
9184 .soclk(soclk)
9185);
9186
9187l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_a_0to3_d1
9188 (.din(fbsel_19to16), .l1clk(l1clk),
9189 .scan_in(ff_fbsel_a_0to3_d1_scanin),
9190 .scan_out(ff_fbsel_a_0to3_d1_scanout),
9191 .dout(fbsel_19to16_d1),
9192 .siclk(siclk),
9193 .soclk(soclk)
9194);
9195
9196l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_a_4to7_d1
9197 (.din(fbsel_23to20), .l1clk(l1clk),
9198 .scan_in(ff_fbsel_a_4to7_d1_scanin),
9199 .scan_out(ff_fbsel_a_4to7_d1_scanout),
9200 .dout(fbsel_23to20_d1),
9201 .siclk(siclk),
9202 .soclk(soclk)
9203);
9204
9205l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_a_8tob_d1
9206 (.din(fbsel_27to24), .l1clk(l1clk),
9207 .scan_in(ff_fbsel_a_8tob_d1_scanin),
9208 .scan_out(ff_fbsel_a_8tob_d1_scanout),
9209 .dout(fbsel_27to24_d1),
9210 .siclk(siclk),
9211 .soclk(soclk)
9212);
9213
9214l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_fbsel_def_vld_d1
9215 (.din(fbsel_def_vld), .l1clk(l1clk),
9216 .scan_in(ff_fbsel_def_vld_d1_scanin),
9217 .scan_out(ff_fbsel_def_vld_d1_scanout),
9218 .dout(fbsel_def_vld_d1),
9219 .siclk(siclk),
9220 .soclk(soclk)
9221);
9222
9223
9224assign sel_mux0 = fbsel_0to3_d1 ;
9225assign sel_mux1 = fbsel_4to7_d1 ;
9226assign sel_mux2 = fbsel_8to11_d1;
9227// BS & SR 11/04/03, MB grows to 32
9228assign sel_mux3 = fbsel_15to12_d1 ;
9229assign sel_mux4 = fbsel_19to16_d1 ;
9230assign sel_mux5 = fbsel_23to20_d1 ;
9231assign sel_mux6 = fbsel_27to24_d1 ;
9232assign sel_mux7 = fbsel_def_vld_d1 ;
9233
9234
9235assign sel_mux0123 = sel_mux0 | sel_mux1 | sel_mux2 | sel_mux3;
9236assign sel_mux4567 = ~sel_mux0123;
9237
9238////////////////////////////////////
9239// 1st level of muxing out the way for Fb write.
9240////////////////////////////////////
9241l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_0123
9242 (.dout(way0123[3:0]),
9243 .din0(way0[3:0]), .din1(way1[3:0]),
9244 .din2(way2[3:0]), .din3(way3[3:0]),
9245 .sel0(mb_way_fb_vld_tmp[0]), .sel1(mb_way_fb_vld_tmp[1]),
9246 .sel2(mb_way_fb_vld_tmp[2]), .sel3(fbsel_def_0123));
9247
9248l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_4567
9249 (.dout(way4567[3:0]),
9250 .din0(way4[3:0]), .din1(way5[3:0]),
9251 .din2(way6[3:0]), .din3(way7[3:0]),
9252 .sel0(mb_way_fb_vld_tmp[4]), .sel1(mb_way_fb_vld_tmp[5]),
9253 .sel2(mb_way_fb_vld_tmp[6]), .sel3(fbsel_def_4567));
9254
9255l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_89ab
9256 (.dout(way89ab[3:0]),
9257 .din0(way8[3:0]), .din1(way9[3:0]),
9258 .din2(way10[3:0]), .din3(way11[3:0]),
9259 .sel0(mb_way_fb_vld_tmp[8]), .sel1(mb_way_fb_vld_tmp[9]),
9260 .sel2(mb_way_fb_vld_tmp[10]), .sel3(fbsel_def_89ab));
9261
9262l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_cdef
9263 (.dout(waycdef[3:0]),
9264 .din0(way12[3:0]), .din1(way13[3:0]),
9265 .din2(way14[3:0]), .din3(way15[3:0]),
9266 .sel0(mb_way_fb_vld_tmp[12]), .sel1(mb_way_fb_vld_tmp[13]),
9267 .sel2(mb_way_fb_vld_tmp[14]), .sel3(fbsel_def_cdef));
9268
9269// BS & SR 11/04/03, MB grows to 32
9270
9271l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_a0123
9272 (.dout(waya0123[3:0]),
9273 .din0(way16[3:0]), .din1(way17[3:0]),
9274 .din2(way18[3:0]), .din3(way19[3:0]),
9275 .sel0(mb_way_fb_vld_tmp[16]), .sel1(mb_way_fb_vld_tmp[17]),
9276 .sel2(mb_way_fb_vld_tmp[18]), .sel3(fbsel_def_a_0123));
9277
9278l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_a4567
9279 (.dout(waya4567[3:0]),
9280 .din0(way20[3:0]), .din1(way21[3:0]),
9281 .din2(way22[3:0]), .din3(way23[3:0]),
9282 .sel0(mb_way_fb_vld_tmp[20]), .sel1(mb_way_fb_vld_tmp[21]),
9283 .sel2(mb_way_fb_vld_tmp[22]), .sel3(fbsel_def_a_4567));
9284
9285l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_a89ab
9286 (.dout(waya89ab[3:0]),
9287 .din0(way24[3:0]), .din1(way25[3:0]),
9288 .din2(way26[3:0]), .din3(way27[3:0]),
9289 .sel0(mb_way_fb_vld_tmp[24]), .sel1(mb_way_fb_vld_tmp[25]),
9290 .sel2(mb_way_fb_vld_tmp[26]), .sel3(fbsel_def_a_89ab));
9291
9292l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_acdef
9293 (.dout(wayacdef[3:0]),
9294 .din0(way28[3:0]), .din1(way29[3:0]),
9295 .din2(way30[3:0]), .din3(way31[3:0]),
9296 .sel0(mb_way_fb_vld_tmp[28]), .sel1(mb_way_fb_vld_tmp[29]),
9297 .sel2(mb_way_fb_vld_tmp[30]), .sel3(fbsel_def_a_cdef));
9298
9299
9300
9301
9302l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_0123
9303 (.din(way0123[3:0]), .l1clk(l1clk),
9304 .scan_in(ff_misbuf_filbuf_way_0123_scanin),
9305 .scan_out(ff_misbuf_filbuf_way_0123_scanout),
9306 .dout(way0123_d1[3:0]),
9307 .siclk(siclk),
9308 .soclk(soclk)
9309);
9310
9311l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_4567
9312 (.din(way4567[3:0]), .l1clk(l1clk),
9313 .scan_in(ff_misbuf_filbuf_way_4567_scanin),
9314 .scan_out(ff_misbuf_filbuf_way_4567_scanout),
9315 .dout(way4567_d1[3:0]),
9316 .siclk(siclk),
9317 .soclk(soclk)
9318);
9319
9320l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_89ab
9321 (.din(way89ab[3:0]), .l1clk(l1clk),
9322 .scan_in(ff_misbuf_filbuf_way_89ab_scanin),
9323 .scan_out(ff_misbuf_filbuf_way_89ab_scanout),
9324 .dout(way89ab_d1[3:0]),
9325 .siclk(siclk),
9326 .soclk(soclk)
9327);
9328
9329l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_cdef
9330 (.din(waycdef[3:0]), .l1clk(l1clk),
9331 .scan_in(ff_misbuf_filbuf_way_cdef_scanin),
9332 .scan_out(ff_misbuf_filbuf_way_cdef_scanout),
9333 .dout(waycdef_d1[3:0]),
9334 .siclk(siclk),
9335 .soclk(soclk)
9336);
9337
9338// BS & SR 11/04/03, MB grows to 32
9339
9340l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_a0123
9341 (.din(waya0123[3:0]), .l1clk(l1clk),
9342 .scan_in(ff_misbuf_filbuf_way_a0123_scanin),
9343 .scan_out(ff_misbuf_filbuf_way_a0123_scanout),
9344 .dout(waya0123_d1[3:0]),
9345 .siclk(siclk),
9346 .soclk(soclk)
9347);
9348
9349l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_a4567
9350 (.din(waya4567[3:0]), .l1clk(l1clk),
9351 .scan_in(ff_misbuf_filbuf_way_a4567_scanin),
9352 .scan_out(ff_misbuf_filbuf_way_a4567_scanout),
9353 .dout(waya4567_d1[3:0]),
9354 .siclk(siclk),
9355 .soclk(soclk)
9356);
9357
9358l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_a89ab
9359 (.din(waya89ab[3:0]), .l1clk(l1clk),
9360 .scan_in(ff_misbuf_filbuf_way_a89ab_scanin),
9361 .scan_out(ff_misbuf_filbuf_way_a89ab_scanout),
9362 .dout(waya89ab_d1[3:0]),
9363 .siclk(siclk),
9364 .soclk(soclk)
9365);
9366
9367l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_acdef
9368 (.din(wayacdef[3:0]), .l1clk(l1clk),
9369 .scan_in(ff_misbuf_filbuf_way_acdef_scanin),
9370 .scan_out(ff_misbuf_filbuf_way_acdef_scanout),
9371 .dout(wayacdef_d1[3:0]),
9372 .siclk(siclk),
9373 .soclk(soclk)
9374);
9375
9376
9377////////////////////////////////////
9378// 2nd level of muxing out the way for Fb write.
9379////////////////////////////////////
9380
9381l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_prev_a
9382 (.dout(misbuf_filbuf_a_way[3:0]),
9383 .din0(way0123_d1[3:0]), .din1(way4567_d1[3:0]),
9384 .din2(way89ab_d1[3:0]), .din3(waycdef_d1[3:0]),
9385 .sel0(sel_mux0), .sel1(sel_mux1),
9386 .sel2(sel_mux2), .sel3(sel_mux3));
9387
9388// BS & SR 11/04/03, MB grows to 32
9389
9390l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_way_prev_b
9391 (.dout(misbuf_filbuf_b_way[3:0]),
9392 .din0(waya0123_d1[3:0]), .din1(waya4567_d1[3:0]),
9393 .din2(waya89ab_d1[3:0]), .din3(wayacdef_d1[3:0]),
9394 .sel0(sel_mux4), .sel1(sel_mux5),
9395 .sel2(sel_mux6), .sel3(sel_mux7));
9396
9397l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_way_prev
9398 (.dout(misbuf_filbuf_way[3:0]),
9399 .din0(misbuf_filbuf_a_way[3:0]), .din1(misbuf_filbuf_b_way[3:0]),
9400 .sel0(sel_mux0123), .sel1(sel_mux4567));
9401
9402////////////////////////////////////////////////////
9403// 1'st level of muxing out the fbid for Fb write.
9404//////////////////////////////////////////////////
9405
9406l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_0123
9407 (.dout(fbid0123[2:0]),
9408 .din0(fbid0[2:0]), .din1(fbid1[2:0]),
9409 .din2(fbid2[2:0]), .din3(fbid3[2:0]),
9410 .sel0(mb_way_fb_vld_tmp[0]), .sel1(mb_way_fb_vld_tmp[1]),
9411 .sel2(mb_way_fb_vld_tmp[2]), .sel3(fbsel_def_0123));
9412
9413l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_4567
9414 (.dout(fbid4567[2:0]),
9415 .din0(fbid4[2:0]), .din1(fbid5[2:0]),
9416 .din2(fbid6[2:0]), .din3(fbid7[2:0]),
9417 .sel0(mb_way_fb_vld_tmp[4]), .sel1(mb_way_fb_vld_tmp[5]),
9418 .sel2(mb_way_fb_vld_tmp[6]), .sel3(fbsel_def_4567));
9419
9420l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_89ab
9421 (.dout(fbid89ab[2:0]),
9422 .din0(fbid8[2:0]), .din1(fbid9[2:0]),
9423 .din2(fbid10[2:0]), .din3(fbid11[2:0]),
9424 .sel0(mb_way_fb_vld_tmp[8]), .sel1(mb_way_fb_vld_tmp[9]),
9425 .sel2(mb_way_fb_vld_tmp[10]), .sel3(fbsel_def_89ab));
9426
9427l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_cdef
9428 (.dout(fbidcdef[2:0]),
9429 .din0(fbid12[2:0]), .din1(fbid13[2:0]),
9430 .din2(fbid14[2:0]), .din3(fbid15[2:0]),
9431 .sel0(mb_way_fb_vld_tmp[12]), .sel1(mb_way_fb_vld_tmp[13]),
9432 .sel2(mb_way_fb_vld_tmp[14]), .sel3(fbsel_def_cdef));
9433
9434// BS & SR 11/04/03, MB grows to 32
9435
9436l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_a0123
9437 (.dout(fbida0123[2:0]),
9438 .din0(fbid16[2:0]), .din1(fbid17[2:0]),
9439 .din2(fbid18[2:0]), .din3(fbid19[2:0]),
9440 .sel0(mb_way_fb_vld_tmp[16]), .sel1(mb_way_fb_vld_tmp[17]),
9441 .sel2(mb_way_fb_vld_tmp[18]), .sel3(fbsel_def_a_0123));
9442
9443l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_a4567
9444 (.dout(fbida4567[2:0]),
9445 .din0(fbid20[2:0]), .din1(fbid21[2:0]),
9446 .din2(fbid22[2:0]), .din3(fbid23[2:0]),
9447 .sel0(mb_way_fb_vld_tmp[20]), .sel1(mb_way_fb_vld_tmp[21]),
9448 .sel2(mb_way_fb_vld_tmp[22]), .sel3(fbsel_def_a_4567));
9449
9450l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_a89ab
9451 (.dout(fbida89ab[2:0]),
9452 .din0(fbid24[2:0]), .din1(fbid25[2:0]),
9453 .din2(fbid26[2:0]), .din3(fbid27[2:0]),
9454 .sel0(mb_way_fb_vld_tmp[24]), .sel1(mb_way_fb_vld_tmp[25]),
9455 .sel2(mb_way_fb_vld_tmp[26]), .sel3(fbsel_def_a_89ab));
9456
9457l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_acdef
9458 (.dout(fbidacdef[2:0]),
9459 .din0(fbid28[2:0]), .din1(fbid29[2:0]),
9460 .din2(fbid30[2:0]), .din3(fbid31[2:0]),
9461 .sel0(mb_way_fb_vld_tmp[28]), .sel1(mb_way_fb_vld_tmp[29]),
9462 .sel2(mb_way_fb_vld_tmp[30]), .sel3(fbsel_def_a_cdef));
9463
9464
9465
9466l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_0123
9467 (.din(fbid0123[2:0]), .l1clk(l1clk),
9468 .scan_in(ff_misbuf_filbuf_fbid_0123_scanin),
9469 .scan_out(ff_misbuf_filbuf_fbid_0123_scanout),
9470 .dout(fbid0123_d1[2:0]),
9471 .siclk(siclk),
9472 .soclk(soclk)
9473);
9474
9475l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_4567
9476 (.din(fbid4567[2:0]), .l1clk(l1clk),
9477 .scan_in(ff_misbuf_filbuf_fbid_4567_scanin),
9478 .scan_out(ff_misbuf_filbuf_fbid_4567_scanout),
9479 .dout(fbid4567_d1[2:0]),
9480 .siclk(siclk),
9481 .soclk(soclk)
9482);
9483
9484l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_89ab
9485 (.din(fbid89ab[2:0]), .l1clk(l1clk),
9486 .scan_in(ff_misbuf_filbuf_fbid_89ab_scanin),
9487 .scan_out(ff_misbuf_filbuf_fbid_89ab_scanout),
9488 .dout(fbid89ab_d1[2:0]),
9489 .siclk(siclk),
9490 .soclk(soclk)
9491);
9492
9493l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_cdef
9494 (.din(fbidcdef[2:0]), .l1clk(l1clk),
9495 .scan_in(ff_misbuf_filbuf_fbid_cdef_scanin),
9496 .scan_out(ff_misbuf_filbuf_fbid_cdef_scanout),
9497 .dout(fbidcdef_d1[2:0]),
9498 .siclk(siclk),
9499 .soclk(soclk)
9500);
9501
9502// BS & SR 11/04/03, MB grows to 32
9503
9504l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_a0123
9505 (.din(fbida0123[2:0]), .l1clk(l1clk),
9506 .scan_in(ff_misbuf_filbuf_fbid_a0123_scanin),
9507 .scan_out(ff_misbuf_filbuf_fbid_a0123_scanout),
9508 .dout(fbida0123_d1[2:0]),
9509 .siclk(siclk),
9510 .soclk(soclk)
9511);
9512
9513l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_a4567
9514 (.din(fbida4567[2:0]), .l1clk(l1clk),
9515 .scan_in(ff_misbuf_filbuf_fbid_a4567_scanin),
9516 .scan_out(ff_misbuf_filbuf_fbid_a4567_scanout),
9517 .dout(fbida4567_d1[2:0]),
9518 .siclk(siclk),
9519 .soclk(soclk)
9520);
9521
9522l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_a89ab
9523 (.din(fbida89ab[2:0]), .l1clk(l1clk),
9524 .scan_in(ff_misbuf_filbuf_fbid_a89ab_scanin),
9525 .scan_out(ff_misbuf_filbuf_fbid_a89ab_scanout),
9526 .dout(fbida89ab_d1[2:0]),
9527 .siclk(siclk),
9528 .soclk(soclk)
9529);
9530
9531l2t_misbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_acdef
9532 (.din(fbidacdef[2:0]), .l1clk(l1clk),
9533 .scan_in(ff_misbuf_filbuf_fbid_acdef_scanin),
9534 .scan_out(ff_misbuf_filbuf_fbid_acdef_scanout),
9535 .dout(fbidacdef_d1[2:0]),
9536 .siclk(siclk),
9537 .soclk(soclk)
9538);
9539
9540
9541//////////////////////////////////////////////////
9542// 2nd level of muxing out the fbid for Fb write.
9543///////////////////////////////////////////////////
9544
9545l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_a
9546 (.dout(misbuf_filbuf_fbid_a[2:0]),
9547 .din0(fbid0123_d1[2:0]), .din1(fbid4567_d1[2:0]),
9548 .din2(fbid89ab_d1[2:0]), .din3(fbidcdef_d1[2:0]),
9549 .sel0(sel_mux0), .sel1(sel_mux1),
9550 .sel2(sel_mux2), .sel3(sel_mux3));
9551
9552l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 mux_fbid_b
9553 (.dout(misbuf_filbuf_fbid_b[2:0]),
9554 .din0(fbida0123_d1[2:0]), .din1(fbida4567_d1[2:0]),
9555 .din2(fbida89ab_d1[2:0]), .din3(fbidacdef_d1[2:0]),
9556 .sel0(sel_mux4), .sel1(sel_mux5),
9557 .sel2(sel_mux6), .sel3(sel_mux7));
9558
9559l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_3 mux_fbid
9560 (.dout(misbuf_filbuf_fbid[2:0]),
9561 .din0(misbuf_filbuf_fbid_a[2:0]), .din1(misbuf_filbuf_fbid_b[2:0]),
9562 .sel0(sel_mux0123), .sel1(sel_mux4567));
9563
9564
9565
9566/////////////////////////////////////////////////////////////
9567// ERROR LOGIC:
9568// CERR and UERR bits are set for ce,ue and notdata errors for instructions that
9569// make two passes even when they hit the L2. This includes
9570// psts, cas, swap/ldstub instrctions.
9571//
9572// CERR: For PSTs, Ldstubs, SWAPs and CAs instructions,
9573// the l2 data or Fb corr or Notdata err signal is recorded in mb_corr_err
9574// so as to signal a disrupting trap to the sparc and thread
9575// that the instr. is performed by. For both non-atomic and atomic
9576// store, this ERR is actually signalled with a store.
9577//
9578// UNCORR: This bit has a dual purpose. The one mentioned above
9579// and also it is used to gate off the store part of the atomic
9580// or a partial store. A notdata error will also set this bit for
9581// any psts/cas/swap/ldstub.
9582/////////////////////////////////////////////////////////////
9583
9584
9585// A CAS sets its ctrue bit only in C9.
9586// The following logic uses either the C8 errors or the C9 errors
9587// for setting the misbuf_err bits based on whether the "ctrue setting"
9588// instruction is a regular PST or a CAS instruction.
9589// we need to gate off the notdata error reporting for off mode
9590
9591// in case of vuad ce error, do not set mb_corr,mb_uncorr,mb_nderr[31:0] bits
9592// for a partial store . Partial store will get replayed and then will set
9593// ctrue and error bits.
9594
9595assign partial_st_wr8_inst_c2 = arb_decdp_wr8_inst_c2 & arb_decdp_pst_inst_c2;
9596
9597l2t_misbuf_ctl_msff_ctl_macro__width_11 ff_wr8_piped
9598 (
9599 .scan_in(ff_wr8_piped_scanin),
9600 .scan_out(ff_wr8_piped_scanout),
9601 .din ({partial_st_wr8_inst_c2,partial_st_wr8_inst_c3,partial_st_wr8_inst_c4,partial_st_wr8_inst_c5,
9602 partial_st_wr8_inst_c52,partial_st_wr8_inst_c6,partial_st_wr8_inst_c7,
9603 filbuf_misbuf_ue_offmode_c7,filbuf_misbuf_ue_offmode_c8,
9604 filbuf_misbuf_ce_offmode_c7,filbuf_misbuf_ce_offmode_c8}),
9605 .dout ({partial_st_wr8_inst_c3,partial_st_wr8_inst_c4,partial_st_wr8_inst_c5,
9606 partial_st_wr8_inst_c52,partial_st_wr8_inst_c6,partial_st_wr8_inst_c7,partial_st_wr8_inst_c8,
9607 filbuf_misbuf_ue_offmode_c8,filbuf_misbuf_ue_offmode_c9,
9608 filbuf_misbuf_ce_offmode_c8,filbuf_misbuf_ce_offmode_c9}),
9609 .l1clk (l1clk),
9610 .siclk(siclk),
9611 .soclk(soclk)
9612 );
9613
9614assign misbuf_corr_err_c8 = deccck_spcd_corr_err_c8 | deccck_spcfb_corr_err_c8 ;
9615
9616assign mb_corr_err_in = ((pst_ctrue_set_c8 & {32{(misbuf_corr_err_c8 & ~misbuf_vuad_ce_err_c8) |
9617 filbuf_misbuf_ce_offmode_c8}}) | // PST/SWAP/LDSTUB CE
9618 (cas_ctrue_set_preerror_c9 & {32{corr_err_c9
9619 | filbuf_misbuf_ce_offmode_c9}}) | // CAS1 CE
9620 mb_corr_err ) & ~reset_valid_bit_c3 ;
9621
9622
9623l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_corr_err // sync reset active low, BS & SR 11/04/03, MB grows to 32
9624 (
9625 .scan_in(ff_mb_corr_err_scanin),
9626 .scan_out(ff_mb_corr_err_scanout),
9627 .din(mb_corr_err_in[31:0]),
9628 .l1clk(l1clk),
9629 .dout(mb_corr_err[31:0]),
9630 .clr(~dbb_rst_l),
9631 .siclk(siclk),
9632 .soclk(soclk)
9633 );
9634
9635
9636// BS 06/13/04 : in case of Notdata error on read pass for partial stores and swap/ldstubs,
9637// have to squash the store in the second pass. Setting mb_uncorr_err is required.
9638//
9639//assign mb_uncorr_err_in = ( ( pst_ctrue_set_c8 & {32{(deccck_uncorr_err_c8 | deccck_notdata_err_c8)}}) |
9640// // PST/SWAP/LDSTUB UE or Notdata errors
9641// ( cas_ctrue_set_preerror_c9 & {32{(uncorr_err_c9 | notdata_err_c9)}})
9642// // CAS1 UE or Notdata error
9643// | mb_uncorr_err )
9644// & ~reset_valid_bit_c3 ; // BS & SR 11/04/03, MB grows to 32
9645//
9646
9647assign mb_uncorr_err_in = ((pst_ctrue_set_c8 & {32{((deccck_uncorr_err_c8 & ~misbuf_vuad_ce_err_c8 &
9648 ~deccck_notdata_err_c8)
9649 | filbuf_misbuf_ue_offmode_c8)
9650 }}) | // PST/SWAP/LDSTUB UE
9651 // if UE and Notdata detected in same line
9652 // only Notdata needs to be reported, in which case
9653 // should not set mb_uncorr_err
9654 // fix for bug 101500
9655 ( cas_ctrue_set_preerror_c9 & {32{(uncorr_err_c9 | filbuf_misbuf_ue_offmode_c9)}}) // CAS1 UE
9656 | mb_uncorr_err ) & ~reset_valid_bit_c3 ;
9657
9658
9659l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_uncorr_err // sync reset active low // BS & SR 11/04/03, MB grows to 32
9660 (.din(mb_uncorr_err_in[31:0]), .l1clk(l1clk),
9661 .scan_in(ff_mb_uncorr_err_scanin),
9662 .scan_out(ff_mb_uncorr_err_scanout),
9663 .dout(mb_uncorr_err[31:0]),
9664 .clr(~dbb_rst_l),
9665 .siclk(siclk),
9666 .soclk(soclk)
9667 );
9668
9669// DO NOT USE csr_l2_bypass_mode_on unreg verion..
9670
9671assign mb_nderr_in[31:0] = ((pst_ctrue_set_c8 &
9672 {32{(deccck_notdata_err_c8 & ~misbuf_vuad_ce_err_c8 & ~partial_st_wr8_inst_c8 & ~l2_bypass_mode_on_d1)}}) |
9673 (cas_ctrue_set_preerror_c9 & {32{(notdata_err_c9)}}) | // CAS1 Notdata error
9674 mb_nderr) & ~reset_valid_bit_c3 ;
9675
9676
9677l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 ff_mb_nderr_in // sync reset active low // BS & SR 11/04/03, MB grows to 32
9678 (.din(mb_nderr_in[31:0]), .l1clk(l1clk),
9679 .scan_in(ff_mb_nderr_in_scanin),
9680 .scan_out(ff_mb_nderr_in_scanout),
9681 .dout(mb_nderr[31:0]),
9682 .clr(~dbb_rst_l),
9683 .siclk(siclk),
9684 .soclk(soclk)
9685 );
9686
9687
9688
9689
9690//////////////////////////////////////////////////////////
9691// ERR bit to l2t_tag to gate off writes to the
9692// data array.
9693//////////////////////////////////////////////////////////
9694
9695assign mb_entry_dec_c1[0] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd0 ) ;
9696assign mb_entry_dec_c1[1] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd1 ) ;
9697assign mb_entry_dec_c1[2] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd2 ) ;
9698assign mb_entry_dec_c1[3] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd3 ) ;
9699assign mb_entry_dec_c1[4] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd4 ) ;
9700assign mb_entry_dec_c1[5] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd5 ) ;
9701assign mb_entry_dec_c1[6] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd6 ) ;
9702assign mb_entry_dec_c1[7] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd7 ) ;
9703assign mb_entry_dec_c1[8] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd8 ) ;
9704assign mb_entry_dec_c1[9] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd9 ) ;
9705assign mb_entry_dec_c1[10] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd10 ) ;
9706assign mb_entry_dec_c1[11] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd11 ) ;
9707assign mb_entry_dec_c1[12] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd12 ) ;
9708assign mb_entry_dec_c1[13] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd13 ) ;
9709assign mb_entry_dec_c1[14] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd14 ) ;
9710assign mb_entry_dec_c1[15] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd15 ) ;
9711// BS & SR 11/04/03, MB grows to 32
9712assign mb_entry_dec_c1[16] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd16 ) ;
9713assign mb_entry_dec_c1[17] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd17 ) ;
9714assign mb_entry_dec_c1[18] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd18 ) ;
9715assign mb_entry_dec_c1[19] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd19 ) ;
9716assign mb_entry_dec_c1[20] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd20 ) ;
9717assign mb_entry_dec_c1[21] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd21 ) ;
9718assign mb_entry_dec_c1[22] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd22 ) ;
9719assign mb_entry_dec_c1[23] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd23 ) ;
9720assign mb_entry_dec_c1[24] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd24 ) ;
9721assign mb_entry_dec_c1[25] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd25 ) ;
9722assign mb_entry_dec_c1[26] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd26) ;
9723assign mb_entry_dec_c1[27] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd27) ;
9724assign mb_entry_dec_c1[28] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd28) ;
9725assign mb_entry_dec_c1[29] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd29) ;
9726assign mb_entry_dec_c1[30] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd30) ;
9727assign mb_entry_dec_c1[31] = ( arbdec_arbdp_inst_mb_entry_c1 == 5'd31) ;
9728
9729
9730
9731
9732
9733
9734assign misbuf_corr_err_c1 = |( mb_entry_dec_c1 & mb_corr_err ) ;
9735
9736assign misbuf_uncorr_err_c1 = |( mb_entry_dec_c1 & mb_uncorr_err ) ;
9737
9738assign misbuf_notdata_err_c1 = |( mb_entry_dec_c1 & mb_nderr );
9739
9740
9741
9742l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_corr_err_c2
9743 (.din(misbuf_corr_err_c1), .l1clk(l1clk),
9744 .scan_in(ff_misbuf_corr_err_c2_scanin),
9745 .scan_out(ff_misbuf_corr_err_c2_scanout),
9746 .dout(misbuf_corr_err_unqual_c2),
9747 .siclk(siclk),
9748 .soclk(soclk)
9749
9750);
9751
9752l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_uncorr_err_c2
9753 (.din(misbuf_uncorr_err_c1), .l1clk(l1clk),
9754 .scan_in(ff_misbuf_uncorr_err_c2_scanin),
9755 .scan_out(ff_misbuf_uncorr_err_c2_scanout),
9756 .dout(misbuf_uncorr_err_unqual_c2),
9757 .siclk(siclk),
9758 .soclk(soclk)
9759
9760);
9761
9762l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_nderr_unqual_c2
9763 (
9764 .scan_in(ff_misbuf_nderr_unqual_c2_scanin),
9765 .scan_out(ff_misbuf_nderr_unqual_c2_scanout),
9766 .din(misbuf_notdata_err_c1),
9767 .l1clk(l1clk),
9768 .dout(misbuf_nderr_unqual_c2),
9769 .siclk(siclk),
9770 .soclk(soclk)
9771 );
9772
9773
9774//assign misbuf_corr_err_c2 = arbdec_arbdp_inst_mb_c2 & misbuf_corr_err_unqual_c2 ;
9775//assign misbuf_uncorr_err_c2 = arbdec_arbdp_inst_mb_c2 & misbuf_uncorr_err_unqual_c2 ;
9776// arbdec_arbdp_inst_mb_c2 qualification may not be required since
9777// these expressions are qualified with pst_with_ctrue_c?
9778// which implies that an instruction is from the Miss Buffer.
9779
9780// need to qualify with arb_misbuf_inst_vld_c2
9781
9782//assign misbuf_corr_err_c2 = misbuf_corr_err_unqual_c2 & arb_misbuf_inst_vld_c2 & ~arb_misbuf_inval_inst_c2;
9783//assign misbuf_uncorr_err_c2 = misbuf_uncorr_err_unqual_c2 & arb_misbuf_inst_vld_c2 & ~arb_misbuf_inval_inst_c2;
9784//assign misbuf_notdata_err_c2 = misbuf_nderr_unqual_c2 & arb_misbuf_inst_vld_c2 & ~arb_misbuf_inval_inst_c2;
9785
9786assign misbuf_corr_err_c2 = misbuf_corr_err_unqual_c2 & arb_misbuf_inst_vld_c2 &
9787 ~arb_misbuf_inval_inst_c2 & arbdec_arbdp_inst_mb_c2;
9788assign misbuf_uncorr_err_c2 = misbuf_uncorr_err_unqual_c2 & arb_misbuf_inst_vld_c2 &
9789 ~arb_misbuf_inval_inst_c2 & arbdec_arbdp_inst_mb_c2;
9790assign misbuf_notdata_err_c2 = misbuf_nderr_unqual_c2 & arb_misbuf_inst_vld_c2 &
9791 ~arb_misbuf_inval_inst_c2 & arbdec_arbdp_inst_mb_c2;
9792
9793
9794
9795
9796
9797
9798////////////////////////////////////////////////////////////////////////
9799// MBF PICKER: THe picker in the MBF is shared between L2 and DRAM
9800// request picks. The DRAM request pick has preference over
9801// the L2 request.
9802//
9803// l2 pick: mb_l2_ready is pre-conditioned to account for rdma reads.
9804// An rdma read will be picked only if the rdma register in
9805// tag is invalid. Since the PICK is performed in PX0, the
9806// rdma register valid signal from tag is a PX0_p signal that
9807// is used after flopping one cycle.
9808//
9809// For more details, read the description of the rdma register
9810// in tag.
9811//
9812////////////////////////////////////////////////////////////////////////
9813
9814
9815
9816assign mb_l2_ready_qual_in = mb_l2_ready_in &
9817 ~({32{tag_rdma_vld_px0_p}} & mb_rdma ) ; // BS & SR 11/04/03, MB grows to 32
9818
9819
9820l2t_misbuf_ctl_msff_ctl_macro__width_32 ff_mb_l2_ready_qual // BS & SR 11/04/03, MB grows to 32
9821 (.din(mb_l2_ready_qual_in[31:0]), .l1clk(l1clk),
9822 .scan_in(ff_mb_l2_ready_qual_scanin),
9823 .scan_out(ff_mb_l2_ready_qual_scanout),
9824 .dout(mb_l2_ready_qual[31:0]),
9825 .siclk(siclk),
9826 .soclk(soclk)
9827);
9828
9829
9830l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_pick_1
9831 (.din(mcu_pick_prev), .l1clk(l1clk),
9832 .scan_in(ff_mcu_pick_1_scanin),
9833 .scan_out(ff_mcu_pick_1_scanout),
9834 .dout(mcu_pick_1),
9835 .siclk(siclk),
9836 .soclk(soclk)
9837);
9838
9839l2t_misbuf_ctl_msff_ctl_macro__width_1 ff_mcu_pick_2_l
9840 (.din(~mcu_pick_prev), .l1clk(l1clk),
9841 .scan_in(ff_mcu_pick_2_l_scanin),
9842 .scan_out(ff_mcu_pick_2_l_scanout),
9843 .dout(mcu_pick_2_l),
9844 .siclk(siclk),
9845 .soclk(soclk)
9846);
9847
9848
9849assign mcu_pick_vec = mb_mcu_ready ;
9850
9851assign l2_pick_vec = (( mb_l2_ready_qual | mb_evict_ready | mb_tecc_ready)
9852 & mb_data_vld) ;
9853
9854l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_32 mux_mb_read_pick_vec // BS & SR 11/04/03, MB grows to 32
9855 ( .dout ( mb_read_pick_vec[31:0]),
9856 .din0(mcu_pick_vec[31:0]),
9857 .din1(l2_pick_vec[31:0]),
9858 .sel0(mcu_pick_1),
9859 .sel1(mcu_pick_2_l));
9860
9861
9862
9863
9864/////////////////
9865// PICKER
9866/////////////////
9867assign pick_quad0_in = mb_read_pick_vec[3:0] ;
9868assign pick_quad1_in = mb_read_pick_vec[7:4] ;
9869assign pick_quad2_in = mb_read_pick_vec[11:8] ;
9870assign pick_quad3_in = mb_read_pick_vec[15:12] ;
9871
9872// BS & SR 11/04/03, MB grows to 32
9873assign pick_quad4_in = mb_read_pick_vec[19:16] ;
9874assign pick_quad5_in = mb_read_pick_vec[23:20] ;
9875assign pick_quad6_in = mb_read_pick_vec[27:24] ;
9876assign pick_quad7_in = mb_read_pick_vec[31:28] ;
9877
9878assign pick_quad_in[0] = |( pick_quad0_in ) ;
9879assign pick_quad_in[1] = |( pick_quad1_in ) ;
9880assign pick_quad_in[2] = |( pick_quad2_in ) ;
9881assign pick_quad_in[3] = |( pick_quad3_in ) ;
9882
9883// BS & SR 11/04/03, MB grows to 32
9884assign pick_quad_in[4] = |( pick_quad4_in ) ;
9885assign pick_quad_in[5] = |( pick_quad5_in ) ;
9886assign pick_quad_in[6] = |( pick_quad6_in ) ;
9887assign pick_quad_in[7] = |( pick_quad7_in ) ;
9888
9889// CHECK THIS
9890
9891assign init_pick_state = ~dbb_rst_l | ~dbginit_l;
9892assign sel_mcu_lshift = mcu_pick_d1 & ~init_pick_state ;
9893assign sel_mcu_same = ~mcu_pick_d1 & ~init_pick_state ;
9894
9895assign mcu_pick_state_lshift = { mcu_pick_state[6:0], mcu_pick_state[7] } ; // BS & SR 11/04/03, MB grows to 32
9896
9897l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_8 mux_mcu_st // BS & SR 11/04/03, MB grows to 32
9898 (.dout(mcu_pick_state_prev[7:0]),
9899 .din0(8'b1),
9900 .din1(mcu_pick_state_lshift[7:0]),
9901 .din2(mcu_pick_state[7:0]),
9902 .sel0(init_pick_state),
9903 .sel1(sel_mcu_lshift),
9904 .sel2(sel_mcu_same)) ;
9905
9906l2t_misbuf_ctl_msff_ctl_macro__width_8 ff_mcu_state // BS & SR 11/04/03, MB grows to 32
9907 (.din(mcu_pick_state_prev[7:0]), .l1clk(l1clk),
9908 .scan_in(ff_mcu_state_scanin),
9909 .scan_out(ff_mcu_state_scanout),
9910 .dout(mcu_pick_state[7:0]),
9911 .siclk(siclk),
9912 .soclk(soclk)
9913);
9914
9915
9916// DRAM STATE quad0
9917assign sel_mcu_lshift_quad0 = mcu_pick_d1 & (|(picker_out_d1[3:0])) & ~init_pick_state ;
9918assign sel_mcu_same_quad0 = ~( mcu_pick_d1 & (|(picker_out_d1[3:0])) ) & ~init_pick_state ;
9919assign mcu_pick_state_lshift_quad0 = { mcu_pick_state_quad0[2:0], mcu_pick_state_quad0[3] } ;
9920
9921l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad0
9922 (.dout(mcu_pick_state_prev_quad0[3:0]),
9923 .din0(4'b1),
9924 .din1(mcu_pick_state_lshift_quad0[3:0]),
9925 .din2(mcu_pick_state_quad0[3:0]),
9926 .sel0(init_pick_state),
9927 .sel1(sel_mcu_lshift_quad0),
9928 .sel2(sel_mcu_same_quad0)) ;
9929
9930
9931l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad0
9932 (.din(mcu_pick_state_prev_quad0[3:0]), .l1clk(l1clk),
9933 .scan_in(ff_mcu_state_quad0_scanin),
9934 .scan_out(ff_mcu_state_quad0_scanout),
9935 .dout(mcu_pick_state_quad0[3:0]),
9936 .siclk(siclk),
9937 .soclk(soclk)
9938);
9939
9940
9941// DRAM STATE quad1
9942
9943
9944
9945assign sel_mcu_lshift_quad1 = mcu_pick_d1 & (|(picker_out_d1[7:4])) & ~init_pick_state ;
9946assign sel_mcu_same_quad1 = ~( mcu_pick_d1 & (|(picker_out_d1[7:4])) ) & ~init_pick_state ;
9947assign mcu_pick_state_lshift_quad1 = { mcu_pick_state_quad1[2:0], mcu_pick_state_quad1[3] } ;
9948
9949l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad1
9950 (.dout(mcu_pick_state_prev_quad1[3:0]),
9951 .din0(4'b1),
9952 .din1(mcu_pick_state_lshift_quad1[3:0]),
9953 .din2(mcu_pick_state_quad1[3:0]),
9954 .sel0(init_pick_state),
9955 .sel1(sel_mcu_lshift_quad1),
9956 .sel2(sel_mcu_same_quad1)) ;
9957
9958
9959l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad1
9960 (.din(mcu_pick_state_prev_quad1[3:0]), .l1clk(l1clk),
9961 .scan_in(ff_mcu_state_quad1_scanin),
9962 .scan_out(ff_mcu_state_quad1_scanout),
9963 .dout(mcu_pick_state_quad1[3:0]),
9964 .siclk(siclk),
9965 .soclk(soclk)
9966);
9967
9968
9969// DRAM STATE quad2
9970assign sel_mcu_lshift_quad2 = mcu_pick_d1 & (|(picker_out_d1[11:8]))
9971 & ~init_pick_state ;
9972assign sel_mcu_same_quad2 = ~( mcu_pick_d1 & (|(picker_out_d1[11:8])) )
9973 & ~init_pick_state ;
9974assign mcu_pick_state_lshift_quad2 = { mcu_pick_state_quad2[2:0],
9975 mcu_pick_state_quad2[3] } ;
9976
9977l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad2
9978 (.dout(mcu_pick_state_prev_quad2[3:0]),
9979 .din0(4'b1),
9980 .din1(mcu_pick_state_lshift_quad2[3:0]),
9981 .din2(mcu_pick_state_quad2[3:0]),
9982 .sel0(init_pick_state),
9983 .sel1(sel_mcu_lshift_quad2),
9984 .sel2(sel_mcu_same_quad2)) ;
9985
9986
9987l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad2
9988 (.din(mcu_pick_state_prev_quad2[3:0]), .l1clk(l1clk),
9989 .scan_in(ff_mcu_state_quad2_scanin),
9990 .scan_out(ff_mcu_state_quad2_scanout),
9991 .dout(mcu_pick_state_quad2[3:0]),
9992 .siclk(siclk),
9993 .soclk(soclk)
9994);
9995
9996// DRAM STATE quad3
9997assign sel_mcu_lshift_quad3 = mcu_pick_d1 & (|(picker_out_d1[15:12]))
9998 & ~init_pick_state ;
9999assign sel_mcu_same_quad3 = ~( mcu_pick_d1 & (|(picker_out_d1[15:12])) )
10000 & ~init_pick_state ;
10001assign mcu_pick_state_lshift_quad3 = { mcu_pick_state_quad3[2:0],
10002 mcu_pick_state_quad3[3] } ;
10003
10004l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad3
10005 (.dout(mcu_pick_state_prev_quad3[3:0]),
10006 .din0(4'b1),
10007 .din1(mcu_pick_state_lshift_quad3[3:0]),
10008 .din2(mcu_pick_state_quad3[3:0]),
10009 .sel0(init_pick_state),
10010 .sel1(sel_mcu_lshift_quad3),
10011 .sel2(sel_mcu_same_quad3)) ;
10012
10013l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad3
10014 (.din(mcu_pick_state_prev_quad3[3:0]), .l1clk(l1clk),
10015 .scan_in(ff_mcu_state_quad3_scanin),
10016 .scan_out(ff_mcu_state_quad3_scanout),
10017 .dout(mcu_pick_state_quad3[3:0]),
10018 .siclk(siclk),
10019 .soclk(soclk)
10020);
10021
10022
10023
10024// BS & SR 11/04/03, MB grows to 32
10025
10026// DRAM STATE quad4
10027assign sel_mcu_lshift_quad4 = mcu_pick_d1 & (|(picker_out_d1[19:16])) & ~init_pick_state ;
10028assign sel_mcu_same_quad4 = ~( mcu_pick_d1 & (|(picker_out_d1[19:16])) ) & ~init_pick_state ;
10029assign mcu_pick_state_lshift_quad4 = { mcu_pick_state_quad4[2:0], mcu_pick_state_quad4[3] } ;
10030
10031l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad4
10032 (
10033 .dout(mcu_pick_state_prev_quad4[3:0]),
10034 .din0(4'b1),
10035 .din1(mcu_pick_state_lshift_quad4[3:0]),
10036 .din2(mcu_pick_state_quad4[3:0]),
10037 .sel0(init_pick_state),
10038 .sel1(sel_mcu_lshift_quad4),
10039 .sel2(sel_mcu_same_quad4)) ;
10040
10041l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad4
10042 (
10043 .scan_in(ff_mcu_state_quad4_scanin),
10044 .scan_out(ff_mcu_state_quad4_scanout),
10045 .din(mcu_pick_state_prev_quad4[3:0]), .l1clk(l1clk),
10046 .dout(mcu_pick_state_quad4[3:0]),
10047 .siclk(siclk),
10048 .soclk(soclk)
10049);
10050
10051// DRAM STATE quad5
10052assign sel_mcu_lshift_quad5 = mcu_pick_d1 & (|(picker_out_d1[23:20])) & ~init_pick_state ;
10053assign sel_mcu_same_quad5 = ~( mcu_pick_d1 & (|(picker_out_d1[23:20])) ) & ~init_pick_state ;
10054assign mcu_pick_state_lshift_quad5 = { mcu_pick_state_quad5[2:0], mcu_pick_state_quad5[3] } ;
10055
10056l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad5
10057 (
10058 .dout(mcu_pick_state_prev_quad5[3:0]),
10059 .din0(4'b1),
10060 .din1(mcu_pick_state_lshift_quad5[3:0]),
10061 .din2(mcu_pick_state_quad5[3:0]),
10062 .sel0(init_pick_state),
10063 .sel1(sel_mcu_lshift_quad5),
10064 .sel2(sel_mcu_same_quad5)) ;
10065
10066l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad5
10067 (
10068 .scan_in(ff_mcu_state_quad5_scanin),
10069 .scan_out(ff_mcu_state_quad5_scanout),
10070 .din(mcu_pick_state_prev_quad5[3:0]), .l1clk(l1clk),
10071 .dout(mcu_pick_state_quad5[3:0]),
10072 .siclk(siclk),
10073 .soclk(soclk)
10074);
10075
10076// DRAM STATE quad6
10077assign sel_mcu_lshift_quad6 = mcu_pick_d1 & (|(picker_out_d1[27:24])) & ~init_pick_state ;
10078assign sel_mcu_same_quad6 = ~( mcu_pick_d1 & (|(picker_out_d1[27:24])) ) & ~init_pick_state ;
10079assign mcu_pick_state_lshift_quad6 = { mcu_pick_state_quad6[2:0], mcu_pick_state_quad6[3] } ;
10080
10081l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad6
10082 (
10083 .dout(mcu_pick_state_prev_quad6[3:0]),
10084 .din0(4'b1),
10085 .din1(mcu_pick_state_lshift_quad6[3:0]),
10086 .din2(mcu_pick_state_quad6[3:0]),
10087 .sel0(init_pick_state),
10088 .sel1(sel_mcu_lshift_quad6),
10089 .sel2(sel_mcu_same_quad6)) ;
10090
10091l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad6
10092 (
10093 .scan_in(ff_mcu_state_quad6_scanin),
10094 .scan_out(ff_mcu_state_quad6_scanout),
10095 .din(mcu_pick_state_prev_quad6[3:0]), .l1clk(l1clk),
10096 .dout(mcu_pick_state_quad6[3:0]),
10097 .siclk(siclk),
10098 .soclk(soclk)
10099);
10100
10101
10102// DRAM STATE quad7
10103assign sel_mcu_lshift_quad7 = mcu_pick_d1 & (|(picker_out_d1[31:28])) & ~init_pick_state ;
10104assign sel_mcu_same_quad7 = ~( mcu_pick_d1 & (|(picker_out_d1[31:28])) ) & ~init_pick_state ;
10105assign mcu_pick_state_lshift_quad7 = { mcu_pick_state_quad7[2:0], mcu_pick_state_quad7[3] } ;
10106
10107l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_mcu_st_quad7
10108 (
10109 .dout(mcu_pick_state_prev_quad7[3:0]),
10110 .din0(4'b1),
10111 .din1(mcu_pick_state_lshift_quad7[3:0]),
10112 .din2(mcu_pick_state_quad7[3:0]),
10113 .sel0(init_pick_state),
10114 .sel1(sel_mcu_lshift_quad7),
10115 .sel2(sel_mcu_same_quad7)) ;
10116
10117l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_mcu_state_quad7
10118 (
10119 .scan_in(ff_mcu_state_quad7_scanin),
10120 .scan_out(ff_mcu_state_quad7_scanout),
10121 .din(mcu_pick_state_prev_quad7[3:0]), .l1clk(l1clk),
10122 .dout(mcu_pick_state_quad7[3:0]),
10123 .siclk(siclk),
10124 .soclk(soclk)
10125);
10126
10127//////////
10128// L2 STATE
10129assign sel_l2_lshift = l2_pick_d1 & ~init_pick_state ;
10130assign sel_l2_same = ~l2_pick_d1 & ~init_pick_state ;
10131assign l2_pick_state_lshift = { l2_pick_state[6:0], l2_pick_state[7] } ;
10132
10133l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_8 mux_l2_st
10134 (.dout(l2_pick_state_prev[7:0]),
10135 .din0(8'b1),
10136 .din1(l2_pick_state_lshift[7:0]),
10137 .din2(l2_pick_state[7:0]),
10138 .sel0(init_pick_state),
10139 .sel1(sel_l2_lshift),
10140 .sel2(sel_l2_same)) ;
10141
10142
10143l2t_misbuf_ctl_msff_ctl_macro__width_8 ff_l2_state
10144 (.din(l2_pick_state_prev[7:0]), .l1clk(l1clk),
10145 .scan_in(ff_l2_state_scanin),
10146 .scan_out(ff_l2_state_scanout),
10147 .dout(l2_pick_state[7:0]),
10148 .siclk(siclk),
10149 .soclk(soclk)
10150);
10151
10152
10153
10154// L2 state quad0
10155
10156
10157assign sel_l2_lshift_quad0 = ( l2_pick_d1 & (|(picker_out_d1[3:0]))) &
10158 ~init_pick_state ;
10159assign sel_l2_same_quad0 = ~( l2_pick_d1 & (|(picker_out_d1[3:0])) )
10160 & ~init_pick_state ;
10161assign l2_pick_state_lshift_quad0 = { l2_pick_state_quad0[2:0], l2_pick_state_quad0[3] } ;
10162
10163l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad0
10164 (.dout(l2_pick_state_prev_quad0[3:0]),
10165 .din0(4'b1),
10166 .din1(l2_pick_state_lshift_quad0[3:0]),
10167 .din2(l2_pick_state_quad0[3:0]),
10168 .sel0(init_pick_state),
10169 .sel1(sel_l2_lshift_quad0),
10170 .sel2(sel_l2_same_quad0)) ;
10171
10172
10173l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad0
10174 (.din(l2_pick_state_prev_quad0[3:0]), .l1clk(l1clk),
10175 .scan_in(ff_l2_state_quad0_scanin),
10176 .scan_out(ff_l2_state_quad0_scanout),
10177 .dout(l2_pick_state_quad0[3:0]),
10178 .siclk(siclk),
10179 .soclk(soclk)
10180);
10181
10182// L2 state quad1
10183
10184assign sel_l2_lshift_quad1 = ( l2_pick_d1 & (|(picker_out_d1[7:4])) )
10185 & ~init_pick_state ;
10186assign sel_l2_same_quad1 = ~( l2_pick_d1 & (|(picker_out_d1[7:4])) )
10187 & ~init_pick_state ;
10188assign l2_pick_state_lshift_quad1 = { l2_pick_state_quad1[2:0],
10189 l2_pick_state_quad1[3] } ;
10190
10191l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad1
10192 (.dout(l2_pick_state_prev_quad1[3:0]),
10193 .din0(4'b1),
10194 .din1(l2_pick_state_lshift_quad1[3:0]),
10195 .din2(l2_pick_state_quad1[3:0]),
10196 .sel0(init_pick_state),
10197 .sel1(sel_l2_lshift_quad1),
10198 .sel2(sel_l2_same_quad1)) ;
10199
10200
10201l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad1
10202 (.din(l2_pick_state_prev_quad1[3:0]), .l1clk(l1clk),
10203 .scan_in(ff_l2_state_quad1_scanin),
10204 .scan_out(ff_l2_state_quad1_scanout),
10205 .dout(l2_pick_state_quad1[3:0]),
10206 .siclk(siclk),
10207 .soclk(soclk)
10208);
10209
10210// L2 state quad2
10211
10212
10213assign sel_l2_lshift_quad2 = ( l2_pick_d1 & (|(picker_out_d1[11:8])) )
10214 & ~init_pick_state ;
10215assign sel_l2_same_quad2 = ~( l2_pick_d1 & (|(picker_out_d1[11:8])) )
10216 & ~init_pick_state ;
10217assign l2_pick_state_lshift_quad2 = { l2_pick_state_quad2[2:0],
10218 l2_pick_state_quad2[3] } ;
10219
10220l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad2
10221 (.dout(l2_pick_state_prev_quad2[3:0]),
10222 .din0(4'b1),
10223 .din1(l2_pick_state_lshift_quad2[3:0]),
10224 .din2(l2_pick_state_quad2[3:0]),
10225 .sel0(init_pick_state),
10226 .sel1(sel_l2_lshift_quad2),
10227 .sel2(sel_l2_same_quad2)) ;
10228
10229
10230l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad2
10231 (.din(l2_pick_state_prev_quad2[3:0]), .l1clk(l1clk),
10232 .scan_in(ff_l2_state_quad2_scanin),
10233 .scan_out(ff_l2_state_quad2_scanout),
10234 .dout(l2_pick_state_quad2[3:0]),
10235 .siclk(siclk),
10236 .soclk(soclk)
10237);
10238
10239
10240// L2 state quad3
10241
10242
10243assign sel_l2_lshift_quad3 = ( l2_pick_d1 & (|(picker_out_d1[15:12])) ) & ~init_pick_state ;
10244assign sel_l2_same_quad3 = ~( l2_pick_d1 & (|(picker_out_d1[15:12])) ) & ~init_pick_state ;
10245assign l2_pick_state_lshift_quad3 = { l2_pick_state_quad3[2:0], l2_pick_state_quad3[3] } ;
10246
10247l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad3
10248 (.dout(l2_pick_state_prev_quad3[3:0]),
10249 .din0(4'b1),
10250 .din1(l2_pick_state_lshift_quad3[3:0]),
10251 .din2(l2_pick_state_quad3[3:0]),
10252 .sel0(init_pick_state),
10253 .sel1(sel_l2_lshift_quad3),
10254 .sel2(sel_l2_same_quad3)) ;
10255
10256
10257l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad3
10258 (.din(l2_pick_state_prev_quad3[3:0]), .l1clk(l1clk),
10259 .scan_in(ff_l2_state_quad3_scanin),
10260 .scan_out(ff_l2_state_quad3_scanout),
10261 .dout(l2_pick_state_quad3[3:0]),
10262 .siclk(siclk),
10263 .soclk(soclk)
10264);
10265
10266
10267// BS & SR 11/04/03, MB grows to 32
10268// L2 STATE quad4
10269assign sel_l2_lshift_quad4 = l2_pick_d1 & (|(picker_out_d1[19:16])) & ~init_pick_state ;
10270assign sel_l2_same_quad4 = ~( l2_pick_d1 & (|(picker_out_d1[19:16])) ) & ~init_pick_state ;
10271assign l2_pick_state_lshift_quad4 = { l2_pick_state_quad4[2:0], l2_pick_state_quad4[3] } ;
10272
10273l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad4
10274 (
10275 .dout(l2_pick_state_prev_quad4[3:0]),
10276 .din0(4'b1),
10277 .din1(l2_pick_state_lshift_quad4[3:0]),
10278 .din2(l2_pick_state_quad4[3:0]),
10279 .sel0(init_pick_state),
10280 .sel1(sel_l2_lshift_quad4),
10281 .sel2(sel_l2_same_quad4)) ;
10282
10283l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad4
10284 (
10285 .scan_in(ff_l2_state_quad4_scanin),
10286 .scan_out(ff_l2_state_quad4_scanout),
10287 .din(l2_pick_state_prev_quad4[3:0]), .l1clk(l1clk),
10288 .dout(l2_pick_state_quad4[3:0]),
10289 .siclk(siclk),
10290 .soclk(soclk)
10291);
10292
10293// L2 STATE quad5
10294assign sel_l2_lshift_quad5 = l2_pick_d1 & (|(picker_out_d1[23:20])) & ~init_pick_state ;
10295assign sel_l2_same_quad5 = ~( l2_pick_d1 & (|(picker_out_d1[23:20])) ) & ~init_pick_state ;
10296assign l2_pick_state_lshift_quad5 = { l2_pick_state_quad5[2:0], l2_pick_state_quad5[3] } ;
10297
10298l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad5
10299 (
10300 .dout(l2_pick_state_prev_quad5[3:0]),
10301 .din0(4'b1),
10302 .din1(l2_pick_state_lshift_quad5[3:0]),
10303 .din2(l2_pick_state_quad5[3:0]),
10304 .sel0(init_pick_state),
10305 .sel1(sel_l2_lshift_quad5),
10306 .sel2(sel_l2_same_quad5)) ;
10307
10308l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad5
10309 (
10310 .scan_in(ff_l2_state_quad5_scanin),
10311 .scan_out(ff_l2_state_quad5_scanout),
10312 .din(l2_pick_state_prev_quad5[3:0]), .l1clk(l1clk),
10313 .dout(l2_pick_state_quad5[3:0]),
10314 .siclk(siclk),
10315 .soclk(soclk)
10316);
10317
10318
10319// L2 STATE quad6
10320assign sel_l2_lshift_quad6 = l2_pick_d1 & (|(picker_out_d1[27:24])) & ~init_pick_state ;
10321assign sel_l2_same_quad6 = ~( l2_pick_d1 & (|(picker_out_d1[27:24])) ) & ~init_pick_state ;
10322assign l2_pick_state_lshift_quad6 = { l2_pick_state_quad6[2:0], l2_pick_state_quad6[3] } ;
10323
10324l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad6
10325 (
10326 .dout(l2_pick_state_prev_quad6[3:0]),
10327 .din0(4'b1),
10328 .din1(l2_pick_state_lshift_quad6[3:0]),
10329 .din2(l2_pick_state_quad6[3:0]),
10330 .sel0(init_pick_state),
10331 .sel1(sel_l2_lshift_quad6),
10332 .sel2(sel_l2_same_quad6)) ;
10333
10334l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad6
10335 (
10336 .scan_in(ff_l2_state_quad6_scanin),
10337 .scan_out(ff_l2_state_quad6_scanout),
10338 .din(l2_pick_state_prev_quad6[3:0]), .l1clk(l1clk),
10339 .dout(l2_pick_state_quad6[3:0]),
10340 .siclk(siclk),
10341 .soclk(soclk)
10342);
10343
10344
10345// L2 STATE quad7
10346assign sel_l2_lshift_quad7 = l2_pick_d1 & (|(picker_out_d1[31:28])) & ~init_pick_state ;
10347assign sel_l2_same_quad7 = ~( l2_pick_d1 & (|(picker_out_d1[31:28])) ) & ~init_pick_state ;
10348assign l2_pick_state_lshift_quad7 = { l2_pick_state_quad7[2:0], l2_pick_state_quad7[3] } ;
10349
10350l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_st_quad7
10351 (
10352 .dout(l2_pick_state_prev_quad7[3:0]),
10353 .din0(4'b1),
10354 .din1(l2_pick_state_lshift_quad7[3:0]),
10355 .din2(l2_pick_state_quad7[3:0]),
10356 .sel0(init_pick_state),
10357 .sel1(sel_l2_lshift_quad7),
10358 .sel2(sel_l2_same_quad7)) ;
10359
10360l2t_misbuf_ctl_msff_ctl_macro__width_4 ff_l2_state_quad7
10361 (
10362 .scan_in(ff_l2_state_quad7_scanin),
10363 .scan_out(ff_l2_state_quad7_scanout),
10364 .din(l2_pick_state_prev_quad7[3:0]), .l1clk(l1clk),
10365 .dout(l2_pick_state_quad7[3:0]),
10366 .siclk(siclk),
10367 .soclk(soclk)
10368);
10369
10370
10371
10372
10373
10374
10375// mux for picking the anchor of the RPE.
10376// real mcu pick
10377
10378
10379l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_pick_state
10380 ( .dout ( pick_state[7:0]),
10381 .din0(l2_pick_state[7:0]),
10382 .din1(mcu_pick_state[7:0]),
10383 .sel0(~mcu_pick),
10384 .sel1(mcu_pick));
10385
10386l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad0
10387 ( .dout(pick_state_quad0[3:0]),
10388 .din0(l2_pick_state_quad0[3:0]),
10389 .din1(mcu_pick_state_quad0[3:0]),
10390 .sel0(~mcu_pick),
10391 .sel1(mcu_pick));
10392
10393l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad1
10394 ( .dout (pick_state_quad1[3:0]),
10395 .din0(l2_pick_state_quad1[3:0]),
10396 .din1(mcu_pick_state_quad1[3:0]),
10397 .sel0(~mcu_pick),
10398 .sel1(mcu_pick));
10399
10400l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad2
10401 ( .dout (pick_state_quad2[3:0]),
10402 .din0(l2_pick_state_quad2[3:0]),
10403 .din1(mcu_pick_state_quad2[3:0]),
10404 .sel0(~mcu_pick),
10405 .sel1(mcu_pick));
10406
10407l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad3
10408 ( .dout (pick_state_quad3[3:0]),
10409 .din0(l2_pick_state_quad3[3:0]),
10410 .din1(mcu_pick_state_quad3[3:0]),
10411 .sel0(~mcu_pick),
10412 .sel1(mcu_pick));
10413
10414// BS & SR 11/04/03, MB grows to 32
10415l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad4
10416 ( .dout (pick_state_quad4[3:0]),
10417 .din0(l2_pick_state_quad4[3:0]),
10418 .din1(mcu_pick_state_quad4[3:0]),
10419 .sel0(~mcu_pick),
10420 .sel1(mcu_pick));
10421
10422l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad5
10423 ( .dout (pick_state_quad5[3:0]),
10424 .din0(l2_pick_state_quad5[3:0]),
10425 .din1(mcu_pick_state_quad5[3:0]),
10426 .sel0(~mcu_pick),
10427 .sel1(mcu_pick));
10428
10429l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad6
10430 ( .dout (pick_state_quad6[3:0]),
10431 .din0(l2_pick_state_quad6[3:0]),
10432 .din1(mcu_pick_state_quad6[3:0]),
10433 .sel0(~mcu_pick),
10434 .sel1(mcu_pick));
10435
10436l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_pick_state_quad7
10437 ( .dout (pick_state_quad7[3:0]),
10438 .din0(l2_pick_state_quad7[3:0]),
10439 .din1(mcu_pick_state_quad7[3:0]),
10440 .sel0(~mcu_pick),
10441 .sel1(mcu_pick));
10442
10443
10444
10445
10446
10447assign pick_s0 = pick_state[0] ;
10448assign pick_s1 = pick_state[1] ;
10449assign pick_s2 = pick_state[2] ;
10450assign pick_s3 = pick_state[3] ;
10451// BS & SR 11/04/03, MB grows to 32
10452assign pick_s4 = pick_state[4] ;
10453assign pick_s5 = pick_state[5] ;
10454assign pick_s6 = pick_state[6] ;
10455assign pick_s7 = pick_state[7] ;
10456
10457
10458assign pick_s0_quad0 = pick_state_quad0[0];
10459assign pick_s1_quad0 = pick_state_quad0[1];
10460assign pick_s2_quad0 = pick_state_quad0[2];
10461assign pick_s3_quad0 = pick_state_quad0[3];
10462
10463assign pick_s0_quad1 = pick_state_quad1[0];
10464assign pick_s1_quad1 = pick_state_quad1[1];
10465assign pick_s2_quad1 = pick_state_quad1[2];
10466assign pick_s3_quad1 = pick_state_quad1[3];
10467
10468assign pick_s0_quad2 = pick_state_quad2[0];
10469assign pick_s1_quad2 = pick_state_quad2[1];
10470assign pick_s2_quad2 = pick_state_quad2[2];
10471assign pick_s3_quad2 = pick_state_quad2[3];
10472
10473assign pick_s0_quad3 = pick_state_quad3[0];
10474assign pick_s1_quad3 = pick_state_quad3[1];
10475assign pick_s2_quad3 = pick_state_quad3[2];
10476assign pick_s3_quad3 = pick_state_quad3[3];
10477
10478// BS & SR 11/04/03, MB grows to 32
10479assign pick_s0_quad4 = pick_state_quad4[0];
10480assign pick_s1_quad4 = pick_state_quad4[1];
10481assign pick_s2_quad4 = pick_state_quad4[2];
10482assign pick_s3_quad4 = pick_state_quad4[3];
10483
10484assign pick_s0_quad5 = pick_state_quad5[0];
10485assign pick_s1_quad5 = pick_state_quad5[1];
10486assign pick_s2_quad5 = pick_state_quad5[2];
10487assign pick_s3_quad5 = pick_state_quad5[3];
10488
10489assign pick_s0_quad6 = pick_state_quad6[0];
10490assign pick_s1_quad6 = pick_state_quad6[1];
10491assign pick_s2_quad6 = pick_state_quad6[2];
10492assign pick_s3_quad6 = pick_state_quad6[3];
10493
10494assign pick_s0_quad7 = pick_state_quad7[0];
10495assign pick_s1_quad7 = pick_state_quad7[1];
10496assign pick_s2_quad7 = pick_state_quad7[2];
10497assign pick_s3_quad7 = pick_state_quad7[3];
10498
10499
10500
10501
10502
10503// QUAD0 bits.
10504assign pick_quad0_sel[0] = pick_quad0_in[0] &
10505 ( pick_s0_quad0 |
10506 ( pick_s1_quad0 & ~( pick_quad0_in[1] | pick_quad0_in[2] | pick_quad0_in[3] )) |
10507 ( pick_s2_quad0 & ~(pick_quad0_in[2] | pick_quad0_in[3] )) |
10508 ( pick_s3_quad0 & ~(pick_quad0_in[3] ) ) ) ;
10509
10510
10511assign pick_quad0_sel[1] = pick_quad0_in[1] & ( pick_s1_quad0 |
10512 ( pick_s2_quad0 & ~( pick_quad0_in[2] |
10513 pick_quad0_in[3] | pick_quad0_in[0] ) ) |
10514 ( pick_s3_quad0 & ~(pick_quad0_in[3] | pick_quad0_in[0] )) |
10515 ( pick_s0_quad0 & ~(pick_quad0_in[0] ) ) ) ;
10516
10517
10518assign pick_quad0_sel[2] = pick_quad0_in[2] & ( pick_s2_quad0 |
10519 ( pick_s3_quad0 & ~( pick_quad0_in[3] |
10520 pick_quad0_in[0] | pick_quad0_in[1] ) ) |
10521 ( pick_s0_quad0 & ~(pick_quad0_in[0] | pick_quad0_in[1] )) |
10522 ( pick_s1_quad0 & ~(pick_quad0_in[1] ) ) ) ;
10523
10524assign pick_quad0_sel[3] = pick_quad0_in[3] & ( pick_s3_quad0 |
10525 ( pick_s0_quad0 & ~( pick_quad0_in[0] |
10526 pick_quad0_in[1] | pick_quad0_in[2] ) ) |
10527 ( pick_s1_quad0 & ~(pick_quad0_in[1] | pick_quad0_in[2] )) |
10528 ( pick_s2_quad0 & ~(pick_quad0_in[2] ) ) ) ;
10529
10530
10531// QUAD1 bits.
10532assign pick_quad1_sel[0] = pick_quad1_in[0] & ( pick_s0_quad1 |
10533 ( pick_s1_quad1 & ~( pick_quad1_in[1] |
10534 pick_quad1_in[2] | pick_quad1_in[3] ) ) |
10535 ( pick_s2_quad1 & ~(pick_quad1_in[2] | pick_quad1_in[3] )) |
10536 ( pick_s3_quad1 & ~(pick_quad1_in[3] ) ) ) ;
10537
10538
10539assign pick_quad1_sel[1] = pick_quad1_in[1] & ( pick_s1_quad1 |
10540 ( pick_s2_quad1 & ~( pick_quad1_in[2] |
10541 pick_quad1_in[3] | pick_quad1_in[0] ) ) |
10542 ( pick_s3_quad1 & ~(pick_quad1_in[3] | pick_quad1_in[0] )) |
10543 ( pick_s0_quad1 & ~(pick_quad1_in[0] ) ) ) ;
10544
10545
10546assign pick_quad1_sel[2] = pick_quad1_in[2] & ( pick_s2_quad1 |
10547 ( pick_s3_quad1 & ~( pick_quad1_in[3] |
10548 pick_quad1_in[0] | pick_quad1_in[1] ) ) |
10549 ( pick_s0_quad1 & ~(pick_quad1_in[0] | pick_quad1_in[1] )) |
10550 ( pick_s1_quad1 & ~(pick_quad1_in[1] ) ) ) ;
10551
10552assign pick_quad1_sel[3] = pick_quad1_in[3] & ( pick_s3_quad1 |
10553 ( pick_s0_quad1 & ~( pick_quad1_in[0] |
10554 pick_quad1_in[1] | pick_quad1_in[2] ) ) |
10555 ( pick_s1_quad1 & ~(pick_quad1_in[1] | pick_quad1_in[2] )) |
10556 ( pick_s2_quad1 & ~(pick_quad1_in[2] ) ) ) ;
10557
10558// QUAD2 bits.
10559assign pick_quad2_sel[0] = pick_quad2_in[0] & ( pick_s0_quad2 |
10560 ( pick_s1_quad2 & ~( pick_quad2_in[1] |
10561 pick_quad2_in[2] | pick_quad2_in[3] ) ) |
10562 ( pick_s2_quad2 & ~(pick_quad2_in[2] | pick_quad2_in[3] )) |
10563 ( pick_s3_quad2 & ~(pick_quad2_in[3] ) ) ) ;
10564
10565
10566assign pick_quad2_sel[1] = pick_quad2_in[1] & ( pick_s1_quad2 |
10567 ( pick_s2_quad2 & ~( pick_quad2_in[2] |
10568 pick_quad2_in[3] | pick_quad2_in[0] ) ) |
10569 ( pick_s3_quad2 & ~(pick_quad2_in[3] | pick_quad2_in[0] )) |
10570 ( pick_s0_quad2 & ~(pick_quad2_in[0] ) ) ) ;
10571
10572
10573assign pick_quad2_sel[2] = pick_quad2_in[2] & ( pick_s2_quad2 |
10574 ( pick_s3_quad2 & ~( pick_quad2_in[3] |
10575 pick_quad2_in[0] | pick_quad2_in[1] ) ) |
10576 ( pick_s0_quad2 & ~(pick_quad2_in[0] | pick_quad2_in[1] )) |
10577 ( pick_s1_quad2 & ~(pick_quad2_in[1] ) ) ) ;
10578
10579assign pick_quad2_sel[3] = pick_quad2_in[3] & ( pick_s3_quad2 |
10580 ( pick_s0_quad2 & ~( pick_quad2_in[0] |
10581 pick_quad2_in[1] | pick_quad2_in[2] ) ) |
10582 ( pick_s1_quad2 & ~(pick_quad2_in[1] | pick_quad2_in[2] )) |
10583 ( pick_s2_quad2 & ~(pick_quad2_in[2] ) ) ) ;
10584
10585
10586// QUAD3 bits.
10587assign pick_quad3_sel[0] = pick_quad3_in[0] &
10588 ( pick_s0_quad3 |
10589 ( pick_s1_quad3 & ~( pick_quad3_in[1] | pick_quad3_in[2] | pick_quad3_in[3] ) ) |
10590 ( pick_s2_quad3 & ~(pick_quad3_in[2] | pick_quad3_in[3] )) |
10591 ( pick_s3_quad3 & ~(pick_quad3_in[3] ) ) ) ;
10592
10593
10594assign pick_quad3_sel[1] = pick_quad3_in[1] &
10595 ( pick_s1_quad3 |
10596 ( pick_s2_quad3 & ~( pick_quad3_in[2] | pick_quad3_in[3] | pick_quad3_in[0] ) ) |
10597 ( pick_s3_quad3 & ~(pick_quad3_in[3] | pick_quad3_in[0] )) |
10598 ( pick_s0_quad3 & ~(pick_quad3_in[0] ) ) ) ;
10599
10600
10601assign pick_quad3_sel[2] = pick_quad3_in[2] &
10602 ( pick_s2_quad3 |
10603 ( pick_s3_quad3 & ~( pick_quad3_in[3] | pick_quad3_in[0] | pick_quad3_in[1] ) ) |
10604 ( pick_s0_quad3 & ~(pick_quad3_in[0] | pick_quad3_in[1] )) |
10605 ( pick_s1_quad3 & ~(pick_quad3_in[1] ) ) ) ;
10606
10607assign pick_quad3_sel[3] = pick_quad3_in[3] &
10608 ( pick_s3_quad3 |
10609 ( pick_s0_quad3 & ~( pick_quad3_in[0] | pick_quad3_in[1] | pick_quad3_in[2] ) ) |
10610 ( pick_s1_quad3 & ~(pick_quad3_in[1] | pick_quad3_in[2] )) |
10611 ( pick_s2_quad3 & ~(pick_quad3_in[2] ) ) ) ;
10612
10613// BS & SR 11/04/03, MB grows to 32
10614
10615// QUAD4 bits.
10616assign pick_quad4_sel[0] = pick_quad4_in[0] &
10617 ( pick_s0_quad4 |
10618 ( pick_s1_quad4 & ~( pick_quad4_in[1] | pick_quad4_in[2] | pick_quad4_in[3] ) ) |
10619 ( pick_s2_quad4 & ~(pick_quad4_in[2] | pick_quad4_in[3] )) |
10620 ( pick_s3_quad4 & ~(pick_quad4_in[3] ) ) ) ;
10621
10622
10623assign pick_quad4_sel[1] = pick_quad4_in[1] &
10624 ( pick_s1_quad4 |
10625 ( pick_s2_quad4 & ~( pick_quad4_in[2] | pick_quad4_in[3] | pick_quad4_in[0] ) ) |
10626 ( pick_s3_quad4 & ~(pick_quad4_in[3] | pick_quad4_in[0] )) |
10627 ( pick_s0_quad4 & ~(pick_quad4_in[0] ) ) ) ;
10628
10629
10630assign pick_quad4_sel[2] = pick_quad4_in[2] &
10631 ( pick_s2_quad4 |
10632 ( pick_s3_quad4 & ~( pick_quad4_in[3] | pick_quad4_in[0] | pick_quad4_in[1] ) ) |
10633 ( pick_s0_quad4 & ~(pick_quad4_in[0] | pick_quad4_in[1] )) |
10634 ( pick_s1_quad4 & ~(pick_quad4_in[1] ) ) ) ;
10635
10636assign pick_quad4_sel[3] = pick_quad4_in[3] &
10637 ( pick_s3_quad4 |
10638 ( pick_s0_quad4 & ~( pick_quad4_in[0] | pick_quad4_in[1] | pick_quad4_in[2] ) ) |
10639 ( pick_s1_quad4 & ~(pick_quad4_in[1] | pick_quad4_in[2] )) |
10640 ( pick_s2_quad4 & ~(pick_quad4_in[2] ) ) ) ;
10641
10642
10643// QUAD5 bits.
10644assign pick_quad5_sel[0] = pick_quad5_in[0] &
10645 ( pick_s0_quad5 |
10646 ( pick_s1_quad5 & ~( pick_quad5_in[1] | pick_quad5_in[2] | pick_quad5_in[3] ) ) |
10647 ( pick_s2_quad5 & ~(pick_quad5_in[2] | pick_quad5_in[3] )) |
10648 ( pick_s3_quad5 & ~(pick_quad5_in[3] ) ) ) ;
10649
10650
10651assign pick_quad5_sel[1] = pick_quad5_in[1] &
10652 ( pick_s1_quad5 |
10653 ( pick_s2_quad5 & ~( pick_quad5_in[2] | pick_quad5_in[3] | pick_quad5_in[0] ) ) |
10654 ( pick_s3_quad5 & ~(pick_quad5_in[3] | pick_quad5_in[0] )) |
10655 ( pick_s0_quad5 & ~(pick_quad5_in[0] ) ) ) ;
10656
10657
10658assign pick_quad5_sel[2] = pick_quad5_in[2] &
10659 ( pick_s2_quad5 |
10660 ( pick_s3_quad5 & ~( pick_quad5_in[3] | pick_quad5_in[0] | pick_quad5_in[1] ) ) |
10661 ( pick_s0_quad5 & ~(pick_quad5_in[0] | pick_quad5_in[1] )) |
10662 ( pick_s1_quad5 & ~(pick_quad5_in[1] ) ) ) ;
10663
10664assign pick_quad5_sel[3] = pick_quad5_in[3] &
10665 ( pick_s3_quad5 |
10666 ( pick_s0_quad5 & ~( pick_quad5_in[0] | pick_quad5_in[1] | pick_quad5_in[2] ) ) |
10667 ( pick_s1_quad5 & ~(pick_quad5_in[1] | pick_quad5_in[2] )) |
10668 ( pick_s2_quad5 & ~(pick_quad5_in[2] ) ) ) ;
10669
10670
10671// QUAD6 bits.
10672assign pick_quad6_sel[0] = pick_quad6_in[0] &
10673 ( pick_s0_quad6 |
10674 ( pick_s1_quad6 & ~( pick_quad6_in[1] | pick_quad6_in[2] | pick_quad6_in[3] ) ) |
10675 ( pick_s2_quad6 & ~(pick_quad6_in[2] | pick_quad6_in[3] )) |
10676 ( pick_s3_quad6 & ~(pick_quad6_in[3] ) ) ) ;
10677
10678
10679assign pick_quad6_sel[1] = pick_quad6_in[1] &
10680 ( pick_s1_quad6 |
10681 ( pick_s2_quad6 & ~( pick_quad6_in[2] | pick_quad6_in[3] | pick_quad6_in[0] ) ) |
10682 ( pick_s3_quad6 & ~(pick_quad6_in[3] | pick_quad6_in[0] )) |
10683 ( pick_s0_quad6 & ~(pick_quad6_in[0] ) ) ) ;
10684
10685
10686assign pick_quad6_sel[2] = pick_quad6_in[2] &
10687 ( pick_s2_quad6 |
10688 ( pick_s3_quad6 & ~( pick_quad6_in[3] | pick_quad6_in[0] | pick_quad6_in[1] ) ) |
10689 ( pick_s0_quad6 & ~(pick_quad6_in[0] | pick_quad6_in[1] )) |
10690 ( pick_s1_quad6 & ~(pick_quad6_in[1] ) ) ) ;
10691
10692assign pick_quad6_sel[3] = pick_quad6_in[3] &
10693 ( pick_s3_quad6 |
10694 ( pick_s0_quad6 & ~( pick_quad6_in[0] | pick_quad6_in[1] | pick_quad6_in[2] ) ) |
10695 ( pick_s1_quad6 & ~(pick_quad6_in[1] | pick_quad6_in[2] )) |
10696 ( pick_s2_quad6 & ~(pick_quad6_in[2] ) ) ) ;
10697
10698
10699// QUAD7 bits.
10700assign pick_quad7_sel[0] = pick_quad7_in[0] &
10701 ( pick_s0_quad7 |
10702 ( pick_s1_quad7 & ~( pick_quad7_in[1] | pick_quad7_in[2] | pick_quad7_in[3] ) ) |
10703 ( pick_s2_quad7 & ~(pick_quad7_in[2] | pick_quad7_in[3] )) |
10704 ( pick_s3_quad7 & ~(pick_quad7_in[3] ) ) ) ;
10705
10706
10707assign pick_quad7_sel[1] = pick_quad7_in[1] &
10708 ( pick_s1_quad7 |
10709 ( pick_s2_quad7 & ~( pick_quad7_in[2] | pick_quad7_in[3] | pick_quad7_in[0] ) ) |
10710 ( pick_s3_quad7 & ~(pick_quad7_in[3] | pick_quad7_in[0] )) |
10711 ( pick_s0_quad7 & ~(pick_quad7_in[0] ) ) ) ;
10712
10713
10714assign pick_quad7_sel[2] = pick_quad7_in[2] &
10715 ( pick_s2_quad7 |
10716 ( pick_s3_quad7 & ~( pick_quad7_in[3] | pick_quad7_in[0] | pick_quad7_in[1] ) ) |
10717 ( pick_s0_quad7 & ~(pick_quad7_in[0] | pick_quad7_in[1] )) |
10718 ( pick_s1_quad7 & ~(pick_quad7_in[1] ) ) ) ;
10719
10720assign pick_quad7_sel[3] = pick_quad7_in[3] &
10721 ( pick_s3_quad7 |
10722 ( pick_s0_quad7 & ~( pick_quad7_in[0] | pick_quad7_in[1] | pick_quad7_in[2] ) ) |
10723 ( pick_s1_quad7 & ~(pick_quad7_in[1] | pick_quad7_in[2] )) |
10724 ( pick_s2_quad7 & ~(pick_quad7_in[2] ) ) ) ;
10725
10726
10727
10728// BS & SR 11/04/03, MB grows to 32
10729// OCTAL bits.
10730assign pick_oct_sel[0] = pick_quad_in[0] &
10731 ( pick_s0 |
10732 ( pick_s1 & ~( pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] |
10733 pick_quad_in[5] | pick_quad_in[6] | pick_quad_in[7])) |
10734 ( pick_s2 & ~(pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] |
10735 pick_quad_in[5] | pick_quad_in[6] | pick_quad_in[7])) |
10736 ( pick_s3 & ~(pick_quad_in[3] | pick_quad_in[4] |
10737 pick_quad_in[5] | pick_quad_in[6] | pick_quad_in[7])) |
10738 ( pick_s4 & ~(pick_quad_in[4] |
10739 pick_quad_in[5] | pick_quad_in[6] | pick_quad_in[7])) |
10740 ( pick_s5 & ~(pick_quad_in[5] | pick_quad_in[6] | pick_quad_in[7])) |
10741 ( pick_s6 & ~(pick_quad_in[6] | pick_quad_in[7])) |
10742 ( pick_s7 & ~(pick_quad_in[7]))
10743 ) ;
10744
10745
10746assign pick_oct_sel[1] = pick_quad_in[1] &
10747 ( pick_s1 |
10748 ( pick_s2 & ~( pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] |
10749 pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0])) |
10750 ( pick_s3 & ~(pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] |
10751 pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0])) |
10752 ( pick_s4 & ~(pick_quad_in[4] | pick_quad_in[5] |
10753 pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0])) |
10754 ( pick_s5 & ~(pick_quad_in[5] |
10755 pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0])) |
10756 ( pick_s6 & ~(pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0])) |
10757 ( pick_s7 & ~(pick_quad_in[7] | pick_quad_in[0])) |
10758 ( pick_s0 & ~(pick_quad_in[0]))
10759 ) ;
10760
10761
10762
10763assign pick_oct_sel[2] = pick_quad_in[2] &
10764 ( pick_s2 |
10765 ( pick_s3 & ~( pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6] |
10766 pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1])) |
10767 ( pick_s4 & ~(pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6] |
10768 pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1])) |
10769 ( pick_s5 & ~(pick_quad_in[5] | pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1])) |
10770 ( pick_s6 & ~(pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1])) |
10771 ( pick_s7 & ~(pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1])) |
10772 ( pick_s0 & ~(pick_quad_in[0] | pick_quad_in[1])) |
10773 ( pick_s1 & ~(pick_quad_in[1]))
10774 ) ;
10775
10776
10777
10778
10779assign pick_oct_sel[3] = pick_quad_in[3] &
10780 ( pick_s3 |
10781 ( pick_s4 & ~( pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6] |
10782 pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2])) |
10783 ( pick_s5 & ~(pick_quad_in[5] | pick_quad_in[6] |
10784 pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2])) |
10785 ( pick_s6 & ~(pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2])) |
10786 ( pick_s7 & ~(pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2])) |
10787 ( pick_s0 & ~(pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2])) |
10788 ( pick_s1 & ~(pick_quad_in[1] | pick_quad_in[2])) |
10789 ( pick_s2 & ~(pick_quad_in[2]))
10790 ) ;
10791
10792assign pick_oct_sel[4] = pick_quad_in[4] &
10793 ( pick_s4 |
10794 ( pick_s5 & ~( pick_quad_in[5] | pick_quad_in[6] | pick_quad_in[7] |
10795 pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3])) |
10796 ( pick_s6 & ~( pick_quad_in[6] | pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] |
10797 pick_quad_in[3])) |
10798 ( pick_s7 & ~(pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3])) |
10799 ( pick_s0 & ~(pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3])) |
10800 ( pick_s1 & ~(pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3])) |
10801 ( pick_s2 & ~(pick_quad_in[2] | pick_quad_in[3])) |
10802 ( pick_s3 & ~(pick_quad_in[3]))
10803 ) ;
10804
10805assign pick_oct_sel[5] = pick_quad_in[5] &
10806 ( pick_s5 |
10807 ( pick_s6 & ~(pick_quad_in[6] | pick_quad_in[7] |
10808 pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4])) |
10809 ( pick_s7 & ~(pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] |
10810 pick_quad_in[3] | pick_quad_in[4])) |
10811 ( pick_s0 & ~(pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4])) |
10812 ( pick_s1 & ~(pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4])) |
10813 ( pick_s2 & ~(pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4])) |
10814 ( pick_s3 & ~(pick_quad_in[3] | pick_quad_in[4])) |
10815 ( pick_s4 & ~(pick_quad_in[4]))
10816 ) ;
10817
10818
10819assign pick_oct_sel[6] = pick_quad_in[6] &
10820 ( pick_s6 |
10821 ( pick_s7 & ~(pick_quad_in[7] | pick_quad_in[0] | pick_quad_in[1] |
10822 pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] )) |
10823 ( pick_s0 & ~(pick_quad_in[0] | pick_quad_in[1] | pick_quad_in[2] |
10824 pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] )) |
10825 ( pick_s1 & ~(pick_quad_in[1] | pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5])) |
10826 ( pick_s2 & ~(pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5])) |
10827 ( pick_s3 & ~(pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5])) |
10828 ( pick_s4 & ~(pick_quad_in[4] | pick_quad_in[5])) |
10829 ( pick_s5 & ~(pick_quad_in[5]))
10830 ) ;
10831
10832
10833assign pick_oct_sel[7] = pick_quad_in[7] &
10834 ( pick_s7 |
10835 ( pick_s0 & ~(pick_quad_in[0] | pick_quad_in[1] |
10836 pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6] )) |
10837 ( pick_s1 & ~(pick_quad_in[1] | pick_quad_in[2] |
10838 pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6] )) |
10839 ( pick_s2 & ~(pick_quad_in[2] | pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6])) |
10840 ( pick_s3 & ~(pick_quad_in[3] | pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6])) |
10841 ( pick_s4 & ~(pick_quad_in[4] | pick_quad_in[5] | pick_quad_in[6])) |
10842 ( pick_s5 & ~(pick_quad_in[5] | pick_quad_in[6])) |
10843 ( pick_s6 & ~(pick_quad_in[6]))
10844 ) ;
10845
10846
10847
10848
10849
10850assign picker_out[3:0] = pick_quad0_sel & {4{pick_oct_sel[0] & picker_out_qual }} ;
10851assign picker_out[7:4] = pick_quad1_sel & {4{pick_oct_sel[1] & picker_out_qual }} ;
10852assign picker_out[11:8] = pick_quad2_sel & {4{pick_oct_sel[2] & picker_out_qual }} ;
10853assign picker_out[15:12] = pick_quad3_sel & {4{pick_oct_sel[3]& picker_out_qual }} ;
10854
10855// BS & SR 11/04/03, MB grows to 32
10856
10857assign picker_out[19:16] = pick_quad4_sel & {4{pick_oct_sel[4] & picker_out_qual }} ;
10858assign picker_out[23:20] = pick_quad5_sel & {4{pick_oct_sel[5] & picker_out_qual }} ;
10859assign picker_out[27:24] = pick_quad6_sel & {4{pick_oct_sel[6] & picker_out_qual }} ;
10860assign picker_out[31:28] = pick_quad7_sel & {4{pick_oct_sel[7] & picker_out_qual }} ;
10861
10862
10863
10864l2t_misbuf_ctl_msff_ctl_macro__width_32 ff_picker_out_d1 // BS & SR 11/04/03, MB grows to 32
10865 (.din(picker_out[31:0]), .l1clk(l1clk),
10866 .scan_in(ff_picker_out_d1_scanin),
10867 .scan_out(ff_picker_out_d1_scanout),
10868 .dout(picker_out_d1[31:0]),
10869 .siclk(siclk),
10870 .soclk(soclk)
10871);
10872
10873l2t_misbuf_ctl_msff_ctl_macro__width_32 ff_picker_out_d2 // BS & SR 11/04/03, MB grows to 32
10874 (.din(picker_out_d1[31:0]), .l1clk(l1clk),
10875 .scan_in(ff_picker_out_d2_scanin),
10876 .scan_out(ff_picker_out_d2_scanout),
10877 .dout(picker_out_d2[31:0]),
10878 .siclk(siclk),
10879 .soclk(soclk)
10880);
10881
10882// Read wordlines for the tag and data arrays.
10883// setup will depend on timing of picker_out_qual i.e. "mbsel_px"
10884
10885assign misbuf_mb_read_wl[31:0] = l2t_mb2_run_r1 ? mbtag_write_ptr[31:0] : picker_out[31:0];
10886
10887
10888// fixscan start:
10889assign reset_flop_scanin = spares_scanout ;
10890assign ff_l2t_mbist_r1_scanin = reset_flop_scanout ;
10891assign ff_loggingerr_scanin = ff_l2t_mbist_r1_scanout ;
10892assign ff_tag_hit_unqual_c3_scanin = ff_loggingerr_scanout ;
10893assign ff_mbf_insert_c3_scanin = ff_tag_hit_unqual_c3_scanout;
10894assign ff_mbf_insert_c3_1_scanin = ff_mbf_insert_c3_scanout ;
10895assign ff_inst_mb_c3_1_scanin = ff_mbf_insert_c3_1_scanout;
10896assign ff_arb_vuad_ce_err_c3_scanin = ff_inst_mb_c3_1_scanout ;
10897assign ff_mbf_delete_c3_scanin = ff_arb_vuad_ce_err_c3_scanout;
10898assign ff_mbf_delete_c3_1_scanin = ff_mbf_delete_c3_scanout ;
10899assign ff_mbctl_nondep_fbhit_c3_scanin = ff_mbf_delete_c3_1_scanout;
10900assign ff_mb_count_c4_scanin = ff_mbctl_nondep_fbhit_c3_scanout;
10901assign ff_rdma_inst_c2_scanin = ff_mb_count_c4_scanout ;
10902assign ff_rdma_inst_c3_scanin = ff_rdma_inst_c2_scanout ;
10903assign ff_mb_rdma_count_c4_scanin = ff_rdma_inst_c3_scanout ;
10904assign ff_inst_mb_entry_c2_scanin = ff_mb_rdma_count_c4_scanout;
10905assign ff_mb_mbist_cam_match_scanin = ff_inst_mb_entry_c2_scanout;
10906assign ff_l2_dir_map_on_d1_scanin = ff_mb_mbist_cam_match_scanout;
10907assign ff_tmp_cam_hit_vec_c2_scanin = ff_l2_dir_map_on_d1_scanout;
10908assign ff_tmp_idx_hit_vec_c2_scanin = ff_tmp_cam_hit_vec_c2_scanout;
10909assign ff_misbuf_c1c2_match_c1_d1_scanin = ff_tmp_idx_hit_vec_c2_scanout;
10910assign ff_misbuf_c1c2_match_c1_d1_1_scanin = ff_misbuf_c1c2_match_c1_d1_scanout;
10911assign ff_mb_hit_off_c1_d1_scanin = ff_misbuf_c1c2_match_c1_d1_1_scanout;
10912assign ff_misbuf_hit_vec_c3_scanin = ff_mb_hit_off_c1_d1_scanout;
10913assign ff_idx_c1c2comp_c1_d1_scanin = ff_misbuf_hit_vec_c3_scanout;
10914assign ff_misbuf_idx_hit_vec_c3_scanin = ff_idx_c1c2comp_c1_d1_scanout;
10915assign ff_hit_count_c4_scanin = ff_misbuf_idx_hit_vec_c3_scanout;
10916assign ff_mb_idx_count_full_c5_scanin = ff_hit_count_c4_scanout ;
10917assign ff_inst_mb_c3_scanin = ff_mb_idx_count_full_c5_scanout;
10918assign ff_inst_mb_c3_2_scanin = ff_inst_mb_c3_scanout ;
10919assign ff_mb_inst_vld_c3_scanin = ff_inst_mb_c3_2_scanout ;
10920assign ff_mb_inst_vld_c3_1_scanin = ff_mb_inst_vld_c3_scanout;
10921assign ff_mb_inst_vld_staging_scanin = ff_mb_inst_vld_c3_1_scanout;
10922assign ff_mb_inst_vld_c3_2_scanin = ff_mb_inst_vld_staging_scanout;
10923assign ff_mb_rewrite_en_c4_scanin = ff_mb_inst_vld_c3_2_scanout;
10924assign ff_mb_rewrite_en_c5_scanin = ff_mb_rewrite_en_c4_scanout;
10925assign ff_mb_rewrite_en_c52_scanin = ff_mb_rewrite_en_c5_scanout;
10926assign ff_mb_rewrite_en_c6_scanin = ff_mb_rewrite_en_c52_scanout;
10927assign ff_mb_rewrite_en_c7_scanin = ff_mb_rewrite_en_c6_scanout;
10928assign ff_mb_rewrite_en_c8_scanin = ff_mb_rewrite_en_c7_scanout;
10929assign ff_mbdata_wr_en_c4_scanin = ff_mb_rewrite_en_c8_scanout;
10930assign ff_mbdata_wr_en_c5_scanin = ff_mbdata_wr_en_c4_scanout;
10931assign ff_mbdata_wr_en_c52_scanin = ff_mbdata_wr_en_c5_scanout;
10932assign ff_mbdata_wr_en_c6_scanin = ff_mbdata_wr_en_c52_scanout;
10933assign ff_mbdata_wr_en_c7_scanin = ff_mbdata_wr_en_c6_scanout;
10934assign ff_mbdata_wr_en_c8_scanin = ff_mbdata_wr_en_c7_scanout;
10935assign ff_enc_tag_wr_wl_c3_scanin = ff_mbdata_wr_en_c8_scanout;
10936assign ff_enc_data_wr_wl_c4_scanin = ff_enc_tag_wr_wl_c3_scanout;
10937assign ff_enc_data_wr_wl_c5_scanin = ff_enc_data_wr_wl_c4_scanout;
10938assign ff_enc_data_wr_wl_c52_scanin = ff_enc_data_wr_wl_c5_scanout;
10939assign ff_enc_data_wr_wl_c6_scanin = ff_enc_data_wr_wl_c52_scanout;
10940assign ff_enc_data_wr_wl_c7_scanin = ff_enc_data_wr_wl_c6_scanout;
10941assign ff_enc_data_wr_wl_c8_scanin = ff_enc_data_wr_wl_c7_scanout;
10942assign ff_enc_data_wr_wl_c9_scanin = ff_enc_data_wr_wl_c8_scanout;
10943assign ff_mbf_dep_c3_scanin = ff_enc_data_wr_wl_c9_scanout;
10944assign ff_dep_inst_c3_scanin = ff_mbf_dep_c3_scanout ;
10945assign ff_tecc_c3_scanin = ff_dep_inst_c3_scanout ;
10946assign ff_set_dep_c2_ldifetch_miss_c2_scanin = ff_tecc_c3_scanout ;
10947assign ff_mbf_dep_c4_scanin = ff_set_dep_c2_ldifetch_miss_c2_scanout;
10948assign ff_dep_bit_scanin = ff_mbf_dep_c4_scanout ;
10949assign ff_mbf_dep_c5_scanin = ff_dep_bit_scanout ;
10950assign ff_mbf_dep_c52_scanin = ff_mbf_dep_c5_scanout ;
10951assign ff_mbf_dep_c6_scanin = ff_mbf_dep_c52_scanout ;
10952assign ff_mbf_dep_c7_scanin = ff_mbf_dep_c6_scanout ;
10953assign ff_mbf_dep_c8_scanin = ff_mbf_dep_c7_scanout ;
10954assign ff_misbuf_mark_evict_tmp_c3_scanin = ff_mbf_dep_c8_scanout ;
10955assign ff_evict_vld_unqual_c3_scanin = ff_misbuf_mark_evict_tmp_c3_scanout;
10956assign ff_decdp_wr64_inst_c3_scanin = ff_evict_vld_unqual_c3_scanout;
10957assign ff_decdp_ld64_inst_c3_scanin = ff_decdp_wr64_inst_c3_scanout;
10958assign ff_ld64_inst_c4_scanin = ff_decdp_ld64_inst_c3_scanout;
10959assign ff_ld64_inst_c5_scanin = ff_ld64_inst_c4_scanout ;
10960assign ff_ld64_inst_c52_scanin = ff_ld64_inst_c5_scanout ;
10961assign ff_ld64_inst_c6_scanin = ff_ld64_inst_c52_scanout ;
10962assign ff_ld64_inst_c7_scanin = ff_ld64_inst_c6_scanout ;
10963assign ff_mcu_rdy_c4_scanin = ff_ld64_inst_c7_scanout ;
10964assign ff_mcu_rdy_c5_scanin = ff_mcu_rdy_c4_scanout ;
10965assign ff_mcu_rdy_c52_scanin = ff_mcu_rdy_c5_scanout ;
10966assign ff_mcu_rdy_c6_scanin = ff_mcu_rdy_c52_scanout ;
10967assign ff_mcu_rdy_c7_scanin = ff_mcu_rdy_c6_scanout ;
10968assign ff_mcu_rdy_c8_scanin = ff_mcu_rdy_c7_scanout ;
10969assign ff_evict_par_err_c3_scanin = ff_mcu_rdy_c8_scanout ;
10970assign ff_evict_par_err_c4_scanin = ff_evict_par_err_c3_scanout;
10971assign ff_evict_par_err_c5_scanin = ff_evict_par_err_c4_scanout;
10972assign ff_evict_par_err_c52_scanin = ff_evict_par_err_c5_scanout;
10973assign ff_evict_par_err_c6_scanin = ff_evict_par_err_c52_scanout;
10974assign ff_evict_par_err_c7_scanin = ff_evict_par_err_c6_scanout;
10975assign ff_misbuf_evict_c8_scanin = ff_evict_par_err_c7_scanout;
10976assign ff_buffer_miss_vld_c3_scanin = ff_misbuf_evict_c8_scanout;
10977assign ff_rdma_reg_vld_c3_scanin = ff_buffer_miss_vld_c3_scanout;
10978assign ff_rdma_comp_rdy_c4_scanin = ff_rdma_reg_vld_c3_scanout;
10979assign ff_rdma_comp_rdy_c5_scanin = ff_rdma_comp_rdy_c4_scanout;
10980assign ff_rdma_comp_rdy_c52_scanin = ff_rdma_comp_rdy_c5_scanout;
10981assign ff_rdma_comp_rdy_c6_scanin = ff_rdma_comp_rdy_c52_scanout;
10982assign ff_rdma_comp_rdy_c7_scanin = ff_rdma_comp_rdy_c6_scanout;
10983assign ff_rdma_comp_rdy_c8_scanin = ff_rdma_comp_rdy_c7_scanout;
10984assign ff_misbuf_tecc_c4_scanin = ff_rdma_comp_rdy_c8_scanout;
10985assign ff_misbuf_tecc_c5_scanin = ff_misbuf_tecc_c4_scanout;
10986assign ff_misbuf_tecc_c52_scanin = ff_misbuf_tecc_c5_scanout;
10987assign ff_misbuf_tecc_c6_scanin = ff_misbuf_tecc_c52_scanout;
10988assign ff_misbuf_tecc_c7_scanin = ff_misbuf_tecc_c6_scanout;
10989assign ff_misbuf_tecc_c8_scanin = ff_misbuf_tecc_c7_scanout;
10990assign ff_mb_write_ptr_c3_scanin = ff_misbuf_tecc_c8_scanout;
10991assign ff_mb_entry_c3_scanin = ff_mb_write_ptr_c3_scanout;
10992assign ff_mb_entry_c3_1_scanin = ff_mb_entry_c3_scanout ;
10993assign ff_valid_bit_scanin = ff_mb_entry_c3_1_scanout ;
10994assign ff_rdma_bit_scanin = ff_valid_bit_scanout ;
10995assign ff_bis_bit_scanin = ff_rdma_bit_scanout ;
10996assign ff_arb_pf_ice_inst_c8_scanin = ff_bis_bit_scanout ;
10997assign ff_arb_vuad_ce_err_slice_scanin = ff_arb_pf_ice_inst_c8_scanout;
10998assign ff_vuad_ce_replay_scanin = ff_arb_vuad_ce_err_slice_scanout;
10999assign ff_mcu_ready_bit_scanin = ff_vuad_ce_replay_scanout;
11000assign ff_young_bit_scanin = ff_mcu_ready_bit_scanout ;
11001assign ff_next_link0_scanin = ff_young_bit_scanout ;
11002assign ff_next_link1_scanin = ff_next_link0_scanout ;
11003assign ff_next_link2_scanin = ff_next_link1_scanout ;
11004assign ff_next_link3_scanin = ff_next_link2_scanout ;
11005assign ff_next_link4_scanin = ff_next_link3_scanout ;
11006assign ff_next_link5_scanin = ff_next_link4_scanout ;
11007assign ff_next_link6_scanin = ff_next_link5_scanout ;
11008assign ff_next_link7_scanin = ff_next_link6_scanout ;
11009assign ff_next_link8_scanin = ff_next_link7_scanout ;
11010assign ff_next_link9_scanin = ff_next_link8_scanout ;
11011assign ff_next_link10_scanin = ff_next_link9_scanout ;
11012assign ff_next_link11_scanin = ff_next_link10_scanout ;
11013assign ff_next_link12_scanin = ff_next_link11_scanout ;
11014assign ff_next_link13_scanin = ff_next_link12_scanout ;
11015assign ff_next_link14_scanin = ff_next_link13_scanout ;
11016assign ff_next_link15_scanin = ff_next_link14_scanout ;
11017assign ff_next_link16_scanin = ff_next_link15_scanout ;
11018assign ff_next_link17_scanin = ff_next_link16_scanout ;
11019assign ff_next_link18_scanin = ff_next_link17_scanout ;
11020assign ff_next_link19_scanin = ff_next_link18_scanout ;
11021assign ff_next_link20_scanin = ff_next_link19_scanout ;
11022assign ff_next_link21_scanin = ff_next_link20_scanout ;
11023assign ff_next_link22_scanin = ff_next_link21_scanout ;
11024assign ff_next_link23_scanin = ff_next_link22_scanout ;
11025assign ff_next_link24_scanin = ff_next_link23_scanout ;
11026assign ff_next_link25_scanin = ff_next_link24_scanout ;
11027assign ff_next_link26_scanin = ff_next_link25_scanout ;
11028assign ff_next_link27_scanin = ff_next_link26_scanout ;
11029assign ff_next_link28_scanin = ff_next_link27_scanout ;
11030assign ff_next_link29_scanin = ff_next_link28_scanout ;
11031assign ff_next_link30_scanin = ff_next_link29_scanout ;
11032assign ff_next_link31_scanin = ff_next_link30_scanout ;
11033assign ff_inst_mb_c4_scanin = ff_next_link31_scanout ;
11034assign ff_inst_mb_c5_scanin = ff_inst_mb_c4_scanout ;
11035assign ff_inst_mb_c52_scanin = ff_inst_mb_c5_scanout ;
11036assign ff_inst_mb_c6_scanin = ff_inst_mb_c52_scanout ;
11037assign ff_inst_mb_c7_scanin = ff_inst_mb_c6_scanout ;
11038assign ff_inst_mb_c8_scanin = ff_inst_mb_c7_scanout ;
11039assign ff_inst_mb_c9_scanin = ff_inst_mb_c8_scanout ;
11040assign ff_enc_data_wr_wl_c7_1_scanin = ff_inst_mb_c9_scanout ;
11041assign ff_cas1_hit_c9_scanin = ff_enc_data_wr_wl_c7_1_scanout;
11042assign ff_uncorr_err_c9_scanin = ff_cas1_hit_c9_scanout ;
11043assign ff_notdata_err_c9_scanin = ff_uncorr_err_c9_scanout ;
11044assign ff_corr_err_c9_scanin = ff_notdata_err_c9_scanout;
11045assign ff_inst_bufidhi_c9_scanin = ff_corr_err_c9_scanout ;
11046assign ff_ctrue_bit_scanin = ff_inst_bufidhi_c9_scanout;
11047assign ff_mbf_insert_mbid_c4_scanin = ff_ctrue_bit_scanout ;
11048assign ff_mbf_insert_c4_scanin = ff_mbf_insert_mbid_c4_scanout;
11049assign ff_misbuf_hit_c3_scanin = ff_mbf_insert_c4_scanout ;
11050assign ff_misbuf_arb_hit_c3_scanin = ff_misbuf_hit_c3_scanout ;
11051assign ff_misbuf_hit_c4_scanin = ff_misbuf_arb_hit_c3_scanout;
11052assign ff_misbuf_filbuf_next_vld_c4_scanin = ff_misbuf_hit_c4_scanout ;
11053assign ff_mbf_delete_c4_scanin = ff_misbuf_filbuf_next_vld_c4_scanout;
11054assign ff_misbuf_filbuf_next_link_c4_scanin = ff_mbf_delete_c4_scanout ;
11055assign ff_mb_data_vld_scanin = ff_misbuf_filbuf_next_link_c4_scanout;
11056assign ff_gate_evict_set_staging_scanin = ff_mb_data_vld_scanout ;
11057assign ff_mb_evict_ready_scanin = ff_gate_evict_set_staging_scanout;
11058assign ff_mb_tecc_ready_scanin = ff_mb_evict_ready_scanout;
11059assign ff_ready_miss_r2_scanin = ff_mb_tecc_ready_scanout ;
11060assign ff_fbf_enc_ld_mbid_r1_scanin = ff_ready_miss_r2_scanout ;
11061assign ff_fbf_st_or_dep_rdy_c5_scanin = ff_fbf_enc_ld_mbid_r1_scanout;
11062assign ff_fbf_enc_dep_mbid_c5_scanin = ff_fbf_st_or_dep_rdy_c5_scanout;
11063assign ff_decdp_cas1_inst_c2_scanin = ff_fbf_enc_dep_mbid_c5_scanout;
11064assign ff_l2_bypass_mode_on_d1_scanin = ff_decdp_cas1_inst_c2_scanout;
11065assign ff_filbuf_match_c3_scanin = ff_l2_bypass_mode_on_d1_scanout;
11066assign ff_filbuf_stinst_match_c3_scanin = ff_filbuf_match_c3_scanout;
11067assign ff_misbuf_inval_inst_c3_scanin = ff_filbuf_stinst_match_c3_scanout;
11068assign ff_mb_dep_rdy_en_c4_scanin = ff_misbuf_inval_inst_c3_scanout;
11069assign ff_wbb_dep_rdy_en_d1_scanin = ff_mb_dep_rdy_en_c4_scanout;
11070assign ff_dep_mbid_d1_scanin = ff_wbb_dep_rdy_en_d1_scanout;
11071assign ff_rdmatb_dep_rdy_en_d1_scanin = ff_dep_mbid_d1_scanout ;
11072assign ff_dep_rdmat_mbid_d1_scanin = ff_rdmatb_dep_rdy_en_d1_scanout;
11073assign ff_set_mbid_vld_scanin = ff_dep_rdmat_mbid_d1_scanout;
11074assign ff_mbid_vld_scanin = ff_set_mbid_vld_scanout ;
11075assign ff_mbid_scanin = ff_mbid_vld_scanout ;
11076assign ff_set_mbid_vld_pfice_prev_scanin = ff_mbid_scanout ;
11077assign ff_pfice_mbid_vld_scanin = ff_set_mbid_vld_pfice_prev_scanout;
11078assign ff_pfice_mbid_scanin = ff_pfice_mbid_vld_scanout;
11079assign ff_vuad_ce_err_ready_scanin = ff_pfice_mbid_scanout ;
11080assign ff_mb_l2_ready_scanin = ff_vuad_ce_err_ready_scanout;
11081assign ff_l2_pick_d1_scanin = ff_mb_l2_ready_scanout ;
11082assign ff_l2_wait_scanin = ff_l2_pick_d1_scanout ;
11083assign ff_read_reg_ctrue_in_scanin = ff_l2_wait_scanout ;
11084assign ff_mcu_l2t_rd_ack_d1_scanin = ff_read_reg_ctrue_in_scanout;
11085assign ff_misbuf_filbuf_mcu_pick_scanin = ff_mcu_l2t_rd_ack_d1_scanout;
11086assign ff_mcu_pick_scanin = ff_misbuf_filbuf_mcu_pick_scanout;
11087assign ff_mcu_pick_2_scanin = ff_mcu_pick_scanout ;
11088assign ff_mcu_pick_d1_scanin = ff_mcu_pick_2_scanout ;
11089assign ff_mcu_pick_d2_scanin = ff_mcu_pick_d1_scanout ;
11090assign ff_dummy_req_d2_scanin = ff_mcu_pick_d2_scanout ;
11091assign ff_mcu_ack_pend_state_scanin = ff_dummy_req_d2_scanout ;
11092assign ff_evict_vld_c4_scanin = ff_mcu_ack_pend_state_scanout;
11093assign ff_way0_scanin = ff_evict_vld_c4_scanout ;
11094assign ff_way1_scanin = ff_way0_scanout ;
11095assign ff_way2_scanin = ff_way1_scanout ;
11096assign ff_way3_scanin = ff_way2_scanout ;
11097assign ff_way4_scanin = ff_way3_scanout ;
11098assign ff_way5_scanin = ff_way4_scanout ;
11099assign ff_way6_scanin = ff_way5_scanout ;
11100assign ff_way7_scanin = ff_way6_scanout ;
11101assign ff_way8_scanin = ff_way7_scanout ;
11102assign ff_way9_scanin = ff_way8_scanout ;
11103assign ff_way10_scanin = ff_way9_scanout ;
11104assign ff_way11_scanin = ff_way10_scanout ;
11105assign ff_way12_scanin = ff_way11_scanout ;
11106assign ff_way13_scanin = ff_way12_scanout ;
11107assign ff_way14_scanin = ff_way13_scanout ;
11108assign ff_way15_scanin = ff_way14_scanout ;
11109assign ff_way16_scanin = ff_way15_scanout ;
11110assign ff_way17_scanin = ff_way16_scanout ;
11111assign ff_way18_scanin = ff_way17_scanout ;
11112assign ff_way19_scanin = ff_way18_scanout ;
11113assign ff_way20_scanin = ff_way19_scanout ;
11114assign ff_way21_scanin = ff_way20_scanout ;
11115assign ff_way22_scanin = ff_way21_scanout ;
11116assign ff_way23_scanin = ff_way22_scanout ;
11117assign ff_way24_scanin = ff_way23_scanout ;
11118assign ff_way25_scanin = ff_way24_scanout ;
11119assign ff_way26_scanin = ff_way25_scanout ;
11120assign ff_way27_scanin = ff_way26_scanout ;
11121assign ff_way28_scanin = ff_way27_scanout ;
11122assign ff_way29_scanin = ff_way28_scanout ;
11123assign ff_way30_scanin = ff_way29_scanout ;
11124assign ff_way31_scanin = ff_way30_scanout ;
11125assign ff_arb_pf_ice_inst_c4_scanin = ff_way31_scanout ;
11126assign ff_mb_way_vld_scanin = ff_arb_pf_ice_inst_c4_scanout;
11127assign ff_fbid0_scanin = ff_mb_way_vld_scanout ;
11128assign ff_fbid1_scanin = ff_fbid0_scanout ;
11129assign ff_fbid2_scanin = ff_fbid1_scanout ;
11130assign ff_fbid3_scanin = ff_fbid2_scanout ;
11131assign ff_fbid4_scanin = ff_fbid3_scanout ;
11132assign ff_fbid5_scanin = ff_fbid4_scanout ;
11133assign ff_fbid6_scanin = ff_fbid5_scanout ;
11134assign ff_fbid7_scanin = ff_fbid6_scanout ;
11135assign ff_fbid8_scanin = ff_fbid7_scanout ;
11136assign ff_fbid9_scanin = ff_fbid8_scanout ;
11137assign ff_fbid10_scanin = ff_fbid9_scanout ;
11138assign ff_fbid11_scanin = ff_fbid10_scanout ;
11139assign ff_fbid12_scanin = ff_fbid11_scanout ;
11140assign ff_fbid13_scanin = ff_fbid12_scanout ;
11141assign ff_fbid14_scanin = ff_fbid13_scanout ;
11142assign ff_fbid15_scanin = ff_fbid14_scanout ;
11143assign ff_fbid16_scanin = ff_fbid15_scanout ;
11144assign ff_fbid17_scanin = ff_fbid16_scanout ;
11145assign ff_fbid18_scanin = ff_fbid17_scanout ;
11146assign ff_fbid19_scanin = ff_fbid18_scanout ;
11147assign ff_fbid20_scanin = ff_fbid19_scanout ;
11148assign ff_fbid21_scanin = ff_fbid20_scanout ;
11149assign ff_fbid22_scanin = ff_fbid21_scanout ;
11150assign ff_fbid23_scanin = ff_fbid22_scanout ;
11151assign ff_fbid24_scanin = ff_fbid23_scanout ;
11152assign ff_fbid25_scanin = ff_fbid24_scanout ;
11153assign ff_fbid26_scanin = ff_fbid25_scanout ;
11154assign ff_fbid27_scanin = ff_fbid26_scanout ;
11155assign ff_fbid28_scanin = ff_fbid27_scanout ;
11156assign ff_fbid29_scanin = ff_fbid28_scanout ;
11157assign ff_fbid30_scanin = ff_fbid29_scanout ;
11158assign ff_fbid31_scanin = ff_fbid30_scanout ;
11159assign ff_mb_fbid_vld_scanin = ff_fbid31_scanout ;
11160assign ff_misbuf_filbuf_way_fbid_vld_scanin = ff_mb_fbid_vld_scanout ;
11161assign ff_fbsel_0to3_d1_scanin = ff_misbuf_filbuf_way_fbid_vld_scanout;
11162assign ff_fbsel_4to7_d1_scanin = ff_fbsel_0to3_d1_scanout ;
11163assign ff_fbsel_8tob_d1_scanin = ff_fbsel_4to7_d1_scanout ;
11164assign ff_fbsel_15to12_d1_scanin = ff_fbsel_8tob_d1_scanout ;
11165assign ff_fbsel_a_0to3_d1_scanin = ff_fbsel_15to12_d1_scanout;
11166assign ff_fbsel_a_4to7_d1_scanin = ff_fbsel_a_0to3_d1_scanout;
11167assign ff_fbsel_a_8tob_d1_scanin = ff_fbsel_a_4to7_d1_scanout;
11168assign ff_fbsel_def_vld_d1_scanin = ff_fbsel_a_8tob_d1_scanout;
11169assign ff_misbuf_filbuf_way_0123_scanin = ff_fbsel_def_vld_d1_scanout;
11170assign ff_misbuf_filbuf_way_4567_scanin = ff_misbuf_filbuf_way_0123_scanout;
11171assign ff_misbuf_filbuf_way_89ab_scanin = ff_misbuf_filbuf_way_4567_scanout;
11172assign ff_misbuf_filbuf_way_cdef_scanin = ff_misbuf_filbuf_way_89ab_scanout;
11173assign ff_misbuf_filbuf_way_a0123_scanin = ff_misbuf_filbuf_way_cdef_scanout;
11174assign ff_misbuf_filbuf_way_a4567_scanin = ff_misbuf_filbuf_way_a0123_scanout;
11175assign ff_misbuf_filbuf_way_a89ab_scanin = ff_misbuf_filbuf_way_a4567_scanout;
11176assign ff_misbuf_filbuf_way_acdef_scanin = ff_misbuf_filbuf_way_a89ab_scanout;
11177assign ff_misbuf_filbuf_fbid_0123_scanin = ff_misbuf_filbuf_way_acdef_scanout;
11178assign ff_misbuf_filbuf_fbid_4567_scanin = ff_misbuf_filbuf_fbid_0123_scanout;
11179assign ff_misbuf_filbuf_fbid_89ab_scanin = ff_misbuf_filbuf_fbid_4567_scanout;
11180assign ff_misbuf_filbuf_fbid_cdef_scanin = ff_misbuf_filbuf_fbid_89ab_scanout;
11181assign ff_misbuf_filbuf_fbid_a0123_scanin = ff_misbuf_filbuf_fbid_cdef_scanout;
11182assign ff_misbuf_filbuf_fbid_a4567_scanin = ff_misbuf_filbuf_fbid_a0123_scanout;
11183assign ff_misbuf_filbuf_fbid_a89ab_scanin = ff_misbuf_filbuf_fbid_a4567_scanout;
11184assign ff_misbuf_filbuf_fbid_acdef_scanin = ff_misbuf_filbuf_fbid_a89ab_scanout;
11185assign ff_wr8_piped_scanin = ff_misbuf_filbuf_fbid_acdef_scanout;
11186assign ff_mb_corr_err_scanin = ff_wr8_piped_scanout ;
11187assign ff_mb_uncorr_err_scanin = ff_mb_corr_err_scanout ;
11188assign ff_mb_nderr_in_scanin = ff_mb_uncorr_err_scanout ;
11189assign ff_misbuf_corr_err_c2_scanin = ff_mb_nderr_in_scanout ;
11190assign ff_misbuf_uncorr_err_c2_scanin = ff_misbuf_corr_err_c2_scanout;
11191assign ff_misbuf_nderr_unqual_c2_scanin = ff_misbuf_uncorr_err_c2_scanout;
11192assign ff_mb_l2_ready_qual_scanin = ff_misbuf_nderr_unqual_c2_scanout;
11193assign ff_mcu_pick_1_scanin = ff_mb_l2_ready_qual_scanout;
11194assign ff_mcu_pick_2_l_scanin = ff_mcu_pick_1_scanout ;
11195assign ff_mcu_state_scanin = ff_mcu_pick_2_l_scanout ;
11196assign ff_mcu_state_quad0_scanin = ff_mcu_state_scanout ;
11197assign ff_mcu_state_quad1_scanin = ff_mcu_state_quad0_scanout;
11198assign ff_mcu_state_quad2_scanin = ff_mcu_state_quad1_scanout;
11199assign ff_mcu_state_quad3_scanin = ff_mcu_state_quad2_scanout;
11200assign ff_mcu_state_quad4_scanin = ff_mcu_state_quad3_scanout;
11201assign ff_mcu_state_quad5_scanin = ff_mcu_state_quad4_scanout;
11202assign ff_mcu_state_quad6_scanin = ff_mcu_state_quad5_scanout;
11203assign ff_mcu_state_quad7_scanin = ff_mcu_state_quad6_scanout;
11204assign ff_l2_state_scanin = ff_mcu_state_quad7_scanout;
11205assign ff_l2_state_quad0_scanin = ff_l2_state_scanout ;
11206assign ff_l2_state_quad1_scanin = ff_l2_state_quad0_scanout;
11207assign ff_l2_state_quad2_scanin = ff_l2_state_quad1_scanout;
11208assign ff_l2_state_quad3_scanin = ff_l2_state_quad2_scanout;
11209assign ff_l2_state_quad4_scanin = ff_l2_state_quad3_scanout;
11210assign ff_l2_state_quad5_scanin = ff_l2_state_quad4_scanout;
11211assign ff_l2_state_quad6_scanin = ff_l2_state_quad5_scanout;
11212assign ff_l2_state_quad7_scanin = ff_l2_state_quad6_scanout;
11213assign ff_picker_out_d1_scanin = ff_l2_state_quad7_scanout;
11214assign ff_picker_out_d2_scanin = ff_picker_out_d1_scanout ;
11215assign scan_out = ff_picker_out_d2_scanout ;
11216// fixscan end:
11217endmodule
11218
11219
11220
11221
11222
11223
11224
11225
11226
11227
11228
11229module adder_1b(/*AUTOARG*/
11230 // Outputs
11231 cout, sum,
11232 // Inputs
11233 oper1, oper2, cin
11234 );
11235input oper1;
11236input oper2;
11237input cin;
11238output cout;
11239output sum;
11240
11241assign sum = oper1 ^ oper2 ^ cin ;
11242assign cout = ( cin & ( oper1 | oper2 ) ) |
11243 ( oper1 & oper2 ) ;
11244endmodule
11245
11246module adder_2b(/*AUTOARG*/
11247 // Outputs
11248 sum, cout,
11249 // Inputs
11250 oper1, oper2, cin
11251 );
11252
11253input [1:0] oper1;
11254input [1:0] oper2;
11255input cin;
11256output [1:0] sum;
11257output cout;
11258
11259wire [1:0] gen, prop;
11260wire [2:0] carry ;
11261
11262assign carry[0] = cin;
11263
11264assign gen[0] = oper1[0] & oper2[0] ;
11265assign prop[0] = oper1[0] | oper2[0] ;
11266assign sum[0] = oper1[0] ^ oper2[0] ^ carry[0] ;
11267
11268
11269assign carry[1] = ( carry[0] & prop[0] ) | gen[0] ;
11270
11271assign gen[1] = oper1[1] & oper2[1] ;
11272assign prop[1] = oper1[1] | oper2[1] ;
11273assign sum[1] = oper1[1] ^ oper2[1] ^ carry[1] ;
11274
11275assign carry[2] = ( carry[0] & prop[0] & prop[1] ) |
11276 ( gen[0] & prop[1] ) |
11277 gen[1] ;
11278
11279assign cout = carry[2] ;
11280endmodule
11281
11282
11283module adder_3b(/*AUTOARG*/
11284 // Outputs
11285 sum, cout,
11286 // Inputs
11287 oper1, oper2, cin
11288 );
11289
11290input [2:0] oper1;
11291input [2:0] oper2;
11292input cin;
11293output [2:0] sum;
11294output cout;
11295
11296wire [2:0] gen, prop;
11297wire [3:0] carry ;
11298
11299assign carry[0] = cin;
11300
11301assign gen[0] = oper1[0] & oper2[0] ;
11302assign prop[0] = oper1[0] | oper2[0] ;
11303assign sum[0] = oper1[0] ^ oper2[0] ^ carry[0] ;
11304
11305
11306assign carry[1] = ( carry[0] & prop[0] ) | gen[0] ;
11307
11308assign gen[1] = oper1[1] & oper2[1] ;
11309assign prop[1] = oper1[1] | oper2[1] ;
11310assign sum[1] = oper1[1] ^ oper2[1] ^ carry[1] ;
11311
11312assign carry[2] = ( carry[0] & prop[0] & prop[1] ) |
11313 ( gen[0] & prop[1] ) | gen[1] ;
11314
11315assign gen[2] = oper1[2] & oper2[2] ;
11316assign prop[2] = oper1[2] | oper2[2] ;
11317assign sum[2] = oper1[2] ^ oper2[2] ^ carry[2] ;
11318
11319assign carry[3] = ( carry[0] & prop[0] & prop[1] & prop[2] ) |
11320 ( gen[0] & prop[1] & prop[2] ) |
11321 ( gen[1] & prop[2] ) | gen[2] ;
11322
11323
11324assign cout = carry[3];
11325endmodule
11326
11327module adder_4b(/*AUTOARG*/
11328 // Outputs
11329 sum, cout,
11330 // Inputs
11331 oper1, oper2, cin
11332 );
11333
11334input [3:0] oper1;
11335input [3:0] oper2;
11336input cin;
11337output [3:0] sum;
11338output cout;
11339
11340wire [3:0] gen, prop;
11341wire [4:0] carry ;
11342
11343assign carry[0] = cin;
11344
11345assign gen[0] = oper1[0] & oper2[0] ;
11346assign prop[0] = oper1[0] | oper2[0] ;
11347assign sum[0] = oper1[0] ^ oper2[0] ^ carry[0] ;
11348
11349
11350assign carry[1] = ( carry[0] & prop[0] ) | gen[0] ;
11351
11352assign gen[1] = oper1[1] & oper2[1] ;
11353assign prop[1] = oper1[1] | oper2[1] ;
11354assign sum[1] = oper1[1] ^ oper2[1] ^ carry[1] ;
11355
11356assign carry[2] = ( carry[0] & prop[0] & prop[1] ) |
11357 ( gen[0] & prop[1] ) | gen[1] ;
11358
11359assign gen[2] = oper1[2] & oper2[2] ;
11360assign prop[2] = oper1[2] | oper2[2] ;
11361assign sum[2] = oper1[2] ^ oper2[2] ^ carry[2] ;
11362
11363assign carry[3] = ( carry[0] & prop[0] & prop[1] & prop[2] ) |
11364 ( gen[0] & prop[1] & prop[2] ) |
11365 ( gen[1] & prop[2] ) | gen[2] ;
11366
11367assign gen[3] = oper1[3] & oper2[3] ;
11368assign prop[3] = oper1[3] | oper2[3] ;
11369assign sum[3] = oper1[3] ^ oper2[3] ^ carry[3] ;
11370
11371assign carry[4] = ( carry[0] & prop[0] & prop[1] & prop[2] & prop[3] ) |
11372 ( gen[0] & prop[1] & prop[2] & prop[3] ) |
11373 ( gen[1] & prop[2] & prop[3] ) |
11374 ( gen[2] & prop[3] ) |
11375 ( gen[3] );
11376
11377
11378
11379assign cout = carry[4];
11380endmodule
11381
11382
11383module adder_5b(/*AUTOARG*/
11384 // Outputs
11385 sum, cout,
11386 // Inputs
11387 oper1, oper2, cin
11388 );
11389
11390input [4:0] oper1;
11391input [4:0] oper2;
11392input cin;
11393output [4:0] sum;
11394output cout;
11395
11396wire [4:0] gen, prop;
11397wire [5:0] carry ;
11398
11399assign carry[0] = cin;
11400
11401assign gen[0] = oper1[0] & oper2[0] ;
11402assign prop[0] = oper1[0] | oper2[0] ;
11403assign sum[0] = oper1[0] ^ oper2[0] ^ carry[0] ;
11404
11405
11406assign carry[1] = ( carry[0] & prop[0] ) | gen[0] ;
11407
11408assign gen[1] = oper1[1] & oper2[1] ;
11409assign prop[1] = oper1[1] | oper2[1] ;
11410assign sum[1] = oper1[1] ^ oper2[1] ^ carry[1] ;
11411
11412assign carry[2] = ( carry[0] & prop[0] & prop[1] ) |
11413 ( gen[0] & prop[1] ) | gen[1] ;
11414
11415assign gen[2] = oper1[2] & oper2[2] ;
11416assign prop[2] = oper1[2] | oper2[2] ;
11417assign sum[2] = oper1[2] ^ oper2[2] ^ carry[2] ;
11418
11419assign carry[3] = ( carry[0] & prop[0] & prop[1] & prop[2] ) |
11420 ( gen[0] & prop[1] & prop[2] ) |
11421 ( gen[1] & prop[2] ) | gen[2] ;
11422
11423assign gen[3] = oper1[3] & oper2[3] ;
11424assign prop[3] = oper1[3] | oper2[3] ;
11425assign sum[3] = oper1[3] ^ oper2[3] ^ carry[3] ;
11426
11427assign carry[4] = ( carry[0] & prop[0] & prop[1] & prop[2] & prop[3] ) |
11428 ( gen[0] & prop[1] & prop[2] & prop[3] ) |
11429 ( gen[1] & prop[2] & prop[3] ) |
11430 ( gen[2] & prop[3] ) |
11431 ( gen[3] );
11432
11433assign gen[4] = oper1[4] & oper2[4];
11434assign prop[4] = oper1[4] | oper2[4];
11435assign sum[4] = oper1[4] ^ oper2[4] ^ carry[4];
11436
11437assign carry[5] = ( carry[0] & prop[0] & prop[1] & prop[2] & prop[3] & prop[4] ) |
11438 ( gen[0] & prop[1] & prop[2] & prop[3] & prop[4] ) |
11439 ( gen[1] & prop[2] & prop[3] & prop[4] ) |
11440 ( gen[2] & prop[3] & prop[4] ) |
11441 ( gen[3] & prop[4] ) |
11442 ( gen[4] );
11443
11444
11445assign cout = carry[5];
11446endmodule
11447
11448
11449
11450
11451
11452
11453
11454// any PARAMS parms go into naming of macro
11455
11456module l2t_misbuf_ctl_l1clkhdr_ctl_macro (
11457 l2clk,
11458 l1en,
11459 pce_ov,
11460 stop,
11461 se,
11462 l1clk);
11463
11464
11465 input l2clk;
11466 input l1en;
11467 input pce_ov;
11468 input stop;
11469 input se;
11470 output l1clk;
11471
11472
11473
11474
11475
11476cl_sc1_l1hdr_8x c_0 (
11477
11478
11479 .l2clk(l2clk),
11480 .pce(l1en),
11481 .l1clk(l1clk),
11482 .se(se),
11483 .pce_ov(pce_ov),
11484 .stop(stop)
11485);
11486
11487
11488
11489endmodule
11490
11491
11492
11493
11494
11495
11496
11497
11498
11499
11500
11501
11502
11503// any PARAMS parms go into naming of macro
11504
11505module l2t_misbuf_ctl_msff_ctl_macro__width_1 (
11506 din,
11507 l1clk,
11508 scan_in,
11509 siclk,
11510 soclk,
11511 dout,
11512 scan_out);
11513wire [0:0] fdin;
11514
11515 input [0:0] din;
11516 input l1clk;
11517 input scan_in;
11518
11519
11520 input siclk;
11521 input soclk;
11522
11523 output [0:0] dout;
11524 output scan_out;
11525assign fdin[0:0] = din[0:0];
11526
11527
11528
11529
11530
11531
11532dff #(1) d0_0 (
11533.l1clk(l1clk),
11534.siclk(siclk),
11535.soclk(soclk),
11536.d(fdin[0:0]),
11537.si(scan_in),
11538.so(scan_out),
11539.q(dout[0:0])
11540);
11541
11542
11543
11544
11545
11546
11547
11548
11549
11550
11551
11552
11553endmodule
11554
11555
11556
11557
11558
11559
11560
11561
11562
11563
11564
11565
11566
11567// any PARAMS parms go into naming of macro
11568
11569module l2t_misbuf_ctl_msff_ctl_macro__width_20 (
11570 din,
11571 l1clk,
11572 scan_in,
11573 siclk,
11574 soclk,
11575 dout,
11576 scan_out);
11577wire [19:0] fdin;
11578wire [18:0] so;
11579
11580 input [19:0] din;
11581 input l1clk;
11582 input scan_in;
11583
11584
11585 input siclk;
11586 input soclk;
11587
11588 output [19:0] dout;
11589 output scan_out;
11590assign fdin[19:0] = din[19:0];
11591
11592
11593
11594
11595
11596
11597dff #(20) d0_0 (
11598.l1clk(l1clk),
11599.siclk(siclk),
11600.soclk(soclk),
11601.d(fdin[19:0]),
11602.si({scan_in,so[18:0]}),
11603.so({so[18:0],scan_out}),
11604.q(dout[19:0])
11605);
11606
11607
11608
11609
11610
11611
11612
11613
11614
11615
11616
11617
11618endmodule
11619
11620
11621
11622
11623
11624
11625
11626
11627
11628
11629
11630
11631
11632// any PARAMS parms go into naming of macro
11633
11634module l2t_misbuf_ctl_msff_ctl_macro__width_7 (
11635 din,
11636 l1clk,
11637 scan_in,
11638 siclk,
11639 soclk,
11640 dout,
11641 scan_out);
11642wire [6:0] fdin;
11643wire [5:0] so;
11644
11645 input [6:0] din;
11646 input l1clk;
11647 input scan_in;
11648
11649
11650 input siclk;
11651 input soclk;
11652
11653 output [6:0] dout;
11654 output scan_out;
11655assign fdin[6:0] = din[6:0];
11656
11657
11658
11659
11660
11661
11662dff #(7) d0_0 (
11663.l1clk(l1clk),
11664.siclk(siclk),
11665.soclk(soclk),
11666.d(fdin[6:0]),
11667.si({scan_in,so[5:0]}),
11668.so({so[5:0],scan_out}),
11669.q(dout[6:0])
11670);
11671
11672
11673
11674
11675
11676
11677
11678
11679
11680
11681
11682
11683endmodule
11684
11685
11686
11687
11688
11689
11690
11691
11692
11693
11694
11695
11696
11697// any PARAMS parms go into naming of macro
11698
11699module l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_2 (
11700 din,
11701 l1clk,
11702 scan_in,
11703 siclk,
11704 soclk,
11705 dout,
11706 scan_out);
11707wire [1:0] fdin;
11708wire [0:0] so;
11709
11710 input [1:0] din;
11711 input l1clk;
11712 input scan_in;
11713
11714
11715 input siclk;
11716 input soclk;
11717
11718 output [1:0] dout;
11719 output scan_out;
11720assign fdin[1:0] = din[1:0];
11721
11722
11723
11724
11725
11726
11727dff #(2) d0_0 (
11728.l1clk(l1clk),
11729.siclk(siclk),
11730.soclk(soclk),
11731.d(fdin[1:0]),
11732.si({scan_in,so[0:0]}),
11733.so({so[0:0],scan_out}),
11734.q(dout[1:0])
11735);
11736
11737
11738
11739
11740
11741
11742
11743
11744
11745
11746
11747
11748endmodule
11749
11750
11751
11752
11753
11754
11755
11756
11757
11758// general mux macro for pass-gate and and-or muxes with/wout priority encoders
11759// also for pass-gate with decoder
11760
11761
11762
11763
11764
11765// any PARAMS parms go into naming of macro
11766
11767module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 (
11768 din0,
11769 sel0,
11770 din1,
11771 sel1,
11772 dout);
11773 input [5:0] din0;
11774 input sel0;
11775 input [5:0] din1;
11776 input sel1;
11777 output [5:0] dout;
11778
11779
11780
11781
11782
11783assign dout[5:0] = ( {6{sel0}} & din0[5:0] ) |
11784 ( {6{sel1}} & din1[5:0]);
11785
11786
11787
11788
11789
11790endmodule
11791
11792
11793
11794
11795
11796
11797// any PARAMS parms go into naming of macro
11798
11799module l2t_misbuf_ctl_msff_ctl_macro__clr_1__en_1__width_6 (
11800 din,
11801 en,
11802 clr,
11803 l1clk,
11804 scan_in,
11805 siclk,
11806 soclk,
11807 dout,
11808 scan_out);
11809wire [5:0] fdin;
11810wire [4:0] so;
11811
11812 input [5:0] din;
11813 input en;
11814 input clr;
11815 input l1clk;
11816 input scan_in;
11817
11818
11819 input siclk;
11820 input soclk;
11821
11822 output [5:0] dout;
11823 output scan_out;
11824assign fdin[5:0] = (din[5:0] & {6{en}} & ~{6{clr}}) | (dout[5:0] & ~{6{en}} & ~{6{clr}});
11825
11826
11827
11828
11829
11830
11831dff #(6) d0_0 (
11832.l1clk(l1clk),
11833.siclk(siclk),
11834.soclk(soclk),
11835.d(fdin[5:0]),
11836.si({scan_in,so[4:0]}),
11837.so({so[4:0],scan_out}),
11838.q(dout[5:0])
11839);
11840
11841
11842
11843
11844
11845
11846
11847
11848
11849
11850
11851
11852endmodule
11853
11854
11855
11856
11857
11858
11859
11860
11861
11862// general mux macro for pass-gate and and-or muxes with/wout priority encoders
11863// also for pass-gate with decoder
11864
11865
11866
11867
11868
11869// any PARAMS parms go into naming of macro
11870
11871module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 (
11872 din0,
11873 sel0,
11874 din1,
11875 sel1,
11876 dout);
11877 input [3:0] din0;
11878 input sel0;
11879 input [3:0] din1;
11880 input sel1;
11881 output [3:0] dout;
11882
11883
11884
11885
11886
11887assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
11888 ( {4{sel1}} & din1[3:0]);
11889
11890
11891
11892
11893
11894endmodule
11895
11896
11897
11898
11899
11900
11901// any PARAMS parms go into naming of macro
11902
11903module l2t_misbuf_ctl_msff_ctl_macro__clr_1__en_1__width_4 (
11904 din,
11905 en,
11906 clr,
11907 l1clk,
11908 scan_in,
11909 siclk,
11910 soclk,
11911 dout,
11912 scan_out);
11913wire [3:0] fdin;
11914wire [2:0] so;
11915
11916 input [3:0] din;
11917 input en;
11918 input clr;
11919 input l1clk;
11920 input scan_in;
11921
11922
11923 input siclk;
11924 input soclk;
11925
11926 output [3:0] dout;
11927 output scan_out;
11928assign fdin[3:0] = (din[3:0] & {4{en}} & ~{4{clr}}) | (dout[3:0] & ~{4{en}} & ~{4{clr}});
11929
11930
11931
11932
11933
11934
11935dff #(4) d0_0 (
11936.l1clk(l1clk),
11937.siclk(siclk),
11938.soclk(soclk),
11939.d(fdin[3:0]),
11940.si({scan_in,so[2:0]}),
11941.so({so[2:0],scan_out}),
11942.q(dout[3:0])
11943);
11944
11945
11946
11947
11948
11949
11950
11951
11952
11953
11954
11955
11956endmodule
11957
11958
11959
11960
11961
11962
11963
11964
11965
11966
11967
11968
11969
11970// any PARAMS parms go into naming of macro
11971
11972module l2t_misbuf_ctl_msff_ctl_macro__width_5 (
11973 din,
11974 l1clk,
11975 scan_in,
11976 siclk,
11977 soclk,
11978 dout,
11979 scan_out);
11980wire [4:0] fdin;
11981wire [3:0] so;
11982
11983 input [4:0] din;
11984 input l1clk;
11985 input scan_in;
11986
11987
11988 input siclk;
11989 input soclk;
11990
11991 output [4:0] dout;
11992 output scan_out;
11993assign fdin[4:0] = din[4:0];
11994
11995
11996
11997
11998
11999
12000dff #(5) d0_0 (
12001.l1clk(l1clk),
12002.siclk(siclk),
12003.soclk(soclk),
12004.d(fdin[4:0]),
12005.si({scan_in,so[3:0]}),
12006.so({so[3:0],scan_out}),
12007.q(dout[4:0])
12008);
12009
12010
12011
12012
12013
12014
12015
12016
12017
12018
12019
12020
12021endmodule
12022
12023
12024
12025
12026
12027
12028
12029
12030
12031
12032
12033
12034
12035// any PARAMS parms go into naming of macro
12036
12037module l2t_misbuf_ctl_msff_ctl_macro__width_33 (
12038 din,
12039 l1clk,
12040 scan_in,
12041 siclk,
12042 soclk,
12043 dout,
12044 scan_out);
12045wire [32:0] fdin;
12046wire [31:0] so;
12047
12048 input [32:0] din;
12049 input l1clk;
12050 input scan_in;
12051
12052
12053 input siclk;
12054 input soclk;
12055
12056 output [32:0] dout;
12057 output scan_out;
12058assign fdin[32:0] = din[32:0];
12059
12060
12061
12062
12063
12064
12065dff #(33) d0_0 (
12066.l1clk(l1clk),
12067.siclk(siclk),
12068.soclk(soclk),
12069.d(fdin[32:0]),
12070.si({scan_in,so[31:0]}),
12071.so({so[31:0],scan_out}),
12072.q(dout[32:0])
12073);
12074
12075
12076
12077
12078
12079
12080
12081
12082
12083
12084
12085
12086endmodule
12087
12088
12089
12090
12091
12092
12093
12094
12095
12096
12097
12098
12099
12100// any PARAMS parms go into naming of macro
12101
12102module l2t_misbuf_ctl_msff_ctl_macro__width_32 (
12103 din,
12104 l1clk,
12105 scan_in,
12106 siclk,
12107 soclk,
12108 dout,
12109 scan_out);
12110wire [31:0] fdin;
12111wire [30:0] so;
12112
12113 input [31:0] din;
12114 input l1clk;
12115 input scan_in;
12116
12117
12118 input siclk;
12119 input soclk;
12120
12121 output [31:0] dout;
12122 output scan_out;
12123assign fdin[31:0] = din[31:0];
12124
12125
12126
12127
12128
12129
12130dff #(32) d0_0 (
12131.l1clk(l1clk),
12132.siclk(siclk),
12133.soclk(soclk),
12134.d(fdin[31:0]),
12135.si({scan_in,so[30:0]}),
12136.so({so[30:0],scan_out}),
12137.q(dout[31:0])
12138);
12139
12140
12141
12142
12143
12144
12145
12146
12147
12148
12149
12150
12151endmodule
12152
12153
12154
12155
12156
12157
12158
12159
12160
12161
12162
12163
12164
12165// any PARAMS parms go into naming of macro
12166
12167module l2t_misbuf_ctl_msff_ctl_macro__dmsff_32x__width_3 (
12168 din,
12169 l1clk,
12170 scan_in,
12171 siclk,
12172 soclk,
12173 dout,
12174 scan_out);
12175wire [2:0] fdin;
12176wire [1:0] so;
12177
12178 input [2:0] din;
12179 input l1clk;
12180 input scan_in;
12181
12182
12183 input siclk;
12184 input soclk;
12185
12186 output [2:0] dout;
12187 output scan_out;
12188assign fdin[2:0] = din[2:0];
12189
12190
12191
12192
12193
12194
12195dff #(3) d0_0 (
12196.l1clk(l1clk),
12197.siclk(siclk),
12198.soclk(soclk),
12199.d(fdin[2:0]),
12200.si({scan_in,so[1:0]}),
12201.so({so[1:0],scan_out}),
12202.q(dout[2:0])
12203);
12204
12205
12206
12207
12208
12209
12210
12211
12212
12213
12214
12215
12216endmodule
12217
12218
12219
12220
12221
12222
12223
12224
12225
12226
12227
12228
12229
12230// any PARAMS parms go into naming of macro
12231
12232module l2t_misbuf_ctl_msff_ctl_macro__width_6 (
12233 din,
12234 l1clk,
12235 scan_in,
12236 siclk,
12237 soclk,
12238 dout,
12239 scan_out);
12240wire [5:0] fdin;
12241wire [4:0] so;
12242
12243 input [5:0] din;
12244 input l1clk;
12245 input scan_in;
12246
12247
12248 input siclk;
12249 input soclk;
12250
12251 output [5:0] dout;
12252 output scan_out;
12253assign fdin[5:0] = din[5:0];
12254
12255
12256
12257
12258
12259
12260dff #(6) d0_0 (
12261.l1clk(l1clk),
12262.siclk(siclk),
12263.soclk(soclk),
12264.d(fdin[5:0]),
12265.si({scan_in,so[4:0]}),
12266.so({so[4:0],scan_out}),
12267.q(dout[5:0])
12268);
12269
12270
12271
12272
12273
12274
12275
12276
12277
12278
12279
12280
12281endmodule
12282
12283
12284
12285
12286
12287
12288
12289
12290
12291
12292
12293
12294
12295// any PARAMS parms go into naming of macro
12296
12297module l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_1 (
12298 din,
12299 clr,
12300 l1clk,
12301 scan_in,
12302 siclk,
12303 soclk,
12304 dout,
12305 scan_out);
12306wire [0:0] fdin;
12307
12308 input [0:0] din;
12309 input clr;
12310 input l1clk;
12311 input scan_in;
12312
12313
12314 input siclk;
12315 input soclk;
12316
12317 output [0:0] dout;
12318 output scan_out;
12319assign fdin[0:0] = din[0:0] & ~{1{clr}};
12320
12321
12322
12323
12324
12325
12326dff #(1) d0_0 (
12327.l1clk(l1clk),
12328.siclk(siclk),
12329.soclk(soclk),
12330.d(fdin[0:0]),
12331.si(scan_in),
12332.so(scan_out),
12333.q(dout[0:0])
12334);
12335
12336
12337
12338
12339
12340
12341
12342
12343
12344
12345
12346
12347endmodule
12348
12349
12350
12351
12352
12353
12354
12355
12356
12357// general mux macro for pass-gate and and-or muxes with/wout priority encoders
12358// also for pass-gate with decoder
12359
12360
12361
12362
12363
12364// any PARAMS parms go into naming of macro
12365
12366module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_5 (
12367 din0,
12368 sel0,
12369 din1,
12370 sel1,
12371 din2,
12372 sel2,
12373 dout);
12374 input [4:0] din0;
12375 input sel0;
12376 input [4:0] din1;
12377 input sel1;
12378 input [4:0] din2;
12379 input sel2;
12380 output [4:0] dout;
12381
12382
12383
12384
12385
12386assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) |
12387 ( {5{sel1}} & din1[4:0]) |
12388 ( {5{sel2}} & din2[4:0]);
12389
12390
12391
12392
12393
12394endmodule
12395
12396
12397
12398
12399
12400
12401// any PARAMS parms go into naming of macro
12402
12403module l2t_misbuf_ctl_msff_ctl_macro__width_3 (
12404 din,
12405 l1clk,
12406 scan_in,
12407 siclk,
12408 soclk,
12409 dout,
12410 scan_out);
12411wire [2:0] fdin;
12412wire [1:0] so;
12413
12414 input [2:0] din;
12415 input l1clk;
12416 input scan_in;
12417
12418
12419 input siclk;
12420 input soclk;
12421
12422 output [2:0] dout;
12423 output scan_out;
12424assign fdin[2:0] = din[2:0];
12425
12426
12427
12428
12429
12430
12431dff #(3) d0_0 (
12432.l1clk(l1clk),
12433.siclk(siclk),
12434.soclk(soclk),
12435.d(fdin[2:0]),
12436.si({scan_in,so[1:0]}),
12437.so({so[1:0],scan_out}),
12438.q(dout[2:0])
12439);
12440
12441
12442
12443
12444
12445
12446
12447
12448
12449
12450
12451
12452endmodule
12453
12454
12455
12456
12457
12458
12459
12460
12461
12462
12463
12464
12465
12466// any PARAMS parms go into naming of macro
12467
12468module l2t_misbuf_ctl_msff_ctl_macro__clr_1__width_32 (
12469 din,
12470 clr,
12471 l1clk,
12472 scan_in,
12473 siclk,
12474 soclk,
12475 dout,
12476 scan_out);
12477wire [31:0] fdin;
12478wire [30:0] so;
12479
12480 input [31:0] din;
12481 input clr;
12482 input l1clk;
12483 input scan_in;
12484
12485
12486 input siclk;
12487 input soclk;
12488
12489 output [31:0] dout;
12490 output scan_out;
12491assign fdin[31:0] = din[31:0] & ~{32{clr}};
12492
12493
12494
12495
12496
12497
12498dff #(32) d0_0 (
12499.l1clk(l1clk),
12500.siclk(siclk),
12501.soclk(soclk),
12502.d(fdin[31:0]),
12503.si({scan_in,so[30:0]}),
12504.so({so[30:0],scan_out}),
12505.q(dout[31:0])
12506);
12507
12508
12509
12510
12511
12512
12513
12514
12515
12516
12517
12518
12519endmodule
12520
12521
12522
12523
12524
12525
12526
12527
12528
12529
12530
12531
12532
12533// any PARAMS parms go into naming of macro
12534
12535module l2t_misbuf_ctl_msff_ctl_macro__width_2 (
12536 din,
12537 l1clk,
12538 scan_in,
12539 siclk,
12540 soclk,
12541 dout,
12542 scan_out);
12543wire [1:0] fdin;
12544wire [0:0] so;
12545
12546 input [1:0] din;
12547 input l1clk;
12548 input scan_in;
12549
12550
12551 input siclk;
12552 input soclk;
12553
12554 output [1:0] dout;
12555 output scan_out;
12556assign fdin[1:0] = din[1:0];
12557
12558
12559
12560
12561
12562
12563dff #(2) d0_0 (
12564.l1clk(l1clk),
12565.siclk(siclk),
12566.soclk(soclk),
12567.d(fdin[1:0]),
12568.si({scan_in,so[0:0]}),
12569.so({so[0:0],scan_out}),
12570.q(dout[1:0])
12571);
12572
12573
12574
12575
12576
12577
12578
12579
12580
12581
12582
12583
12584endmodule
12585
12586
12587
12588
12589
12590
12591
12592
12593
12594
12595
12596
12597
12598// any PARAMS parms go into naming of macro
12599
12600module l2t_misbuf_ctl_msff_ctl_macro__width_65 (
12601 din,
12602 l1clk,
12603 scan_in,
12604 siclk,
12605 soclk,
12606 dout,
12607 scan_out);
12608wire [64:0] fdin;
12609wire [63:0] so;
12610
12611 input [64:0] din;
12612 input l1clk;
12613 input scan_in;
12614
12615
12616 input siclk;
12617 input soclk;
12618
12619 output [64:0] dout;
12620 output scan_out;
12621assign fdin[64:0] = din[64:0];
12622
12623
12624
12625
12626
12627
12628dff #(65) d0_0 (
12629.l1clk(l1clk),
12630.siclk(siclk),
12631.soclk(soclk),
12632.d(fdin[64:0]),
12633.si({scan_in,so[63:0]}),
12634.so({so[63:0],scan_out}),
12635.q(dout[64:0])
12636);
12637
12638
12639
12640
12641
12642
12643
12644
12645
12646
12647
12648
12649endmodule
12650
12651
12652
12653
12654
12655
12656
12657
12658
12659
12660
12661
12662
12663// any PARAMS parms go into naming of macro
12664
12665module l2t_misbuf_ctl_msff_ctl_macro__en_1__width_5 (
12666 din,
12667 en,
12668 l1clk,
12669 scan_in,
12670 siclk,
12671 soclk,
12672 dout,
12673 scan_out);
12674wire [4:0] fdin;
12675wire [3:0] so;
12676
12677 input [4:0] din;
12678 input en;
12679 input l1clk;
12680 input scan_in;
12681
12682
12683 input siclk;
12684 input soclk;
12685
12686 output [4:0] dout;
12687 output scan_out;
12688assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}});
12689
12690
12691
12692
12693
12694
12695dff #(5) d0_0 (
12696.l1clk(l1clk),
12697.siclk(siclk),
12698.soclk(soclk),
12699.d(fdin[4:0]),
12700.si({scan_in,so[3:0]}),
12701.so({so[3:0],scan_out}),
12702.q(dout[4:0])
12703);
12704
12705
12706
12707
12708
12709
12710
12711
12712
12713
12714
12715
12716endmodule
12717
12718
12719
12720
12721
12722
12723
12724
12725
12726// general mux macro for pass-gate and and-or muxes with/wout priority encoders
12727// also for pass-gate with decoder
12728
12729
12730
12731
12732
12733// any PARAMS parms go into naming of macro
12734
12735module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 (
12736 din0,
12737 sel0,
12738 din1,
12739 sel1,
12740 dout);
12741 input [4:0] din0;
12742 input sel0;
12743 input [4:0] din1;
12744 input sel1;
12745 output [4:0] dout;
12746
12747
12748
12749
12750
12751assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) |
12752 ( {5{sel1}} & din1[4:0]);
12753
12754
12755
12756
12757
12758endmodule
12759
12760
12761// general mux macro for pass-gate and and-or muxes with/wout priority encoders
12762// also for pass-gate with decoder
12763
12764
12765
12766
12767
12768// any PARAMS parms go into naming of macro
12769
12770module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 (
12771 din0,
12772 sel0,
12773 din1,
12774 sel1,
12775 din2,
12776 sel2,
12777 din3,
12778 sel3,
12779 dout);
12780 input [4:0] din0;
12781 input sel0;
12782 input [4:0] din1;
12783 input sel1;
12784 input [4:0] din2;
12785 input sel2;
12786 input [4:0] din3;
12787 input sel3;
12788 output [4:0] dout;
12789
12790
12791
12792
12793
12794assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) |
12795 ( {5{sel1}} & din1[4:0]) |
12796 ( {5{sel2}} & din2[4:0]) |
12797 ( {5{sel3}} & din3[4:0]);
12798
12799
12800
12801
12802
12803endmodule
12804
12805
12806
12807
12808
12809
12810// any PARAMS parms go into naming of macro
12811
12812module l2t_misbuf_ctl_msff_ctl_macro__width_30 (
12813 din,
12814 l1clk,
12815 scan_in,
12816 siclk,
12817 soclk,
12818 dout,
12819 scan_out);
12820wire [29:0] fdin;
12821wire [28:0] so;
12822
12823 input [29:0] din;
12824 input l1clk;
12825 input scan_in;
12826
12827
12828 input siclk;
12829 input soclk;
12830
12831 output [29:0] dout;
12832 output scan_out;
12833assign fdin[29:0] = din[29:0];
12834
12835
12836
12837
12838
12839
12840dff #(30) d0_0 (
12841.l1clk(l1clk),
12842.siclk(siclk),
12843.soclk(soclk),
12844.d(fdin[29:0]),
12845.si({scan_in,so[28:0]}),
12846.so({so[28:0],scan_out}),
12847.q(dout[29:0])
12848);
12849
12850
12851
12852
12853
12854
12855
12856
12857
12858
12859
12860
12861endmodule
12862
12863
12864
12865
12866
12867
12868
12869
12870
12871
12872
12873
12874
12875// any PARAMS parms go into naming of macro
12876
12877module l2t_misbuf_ctl_msff_ctl_macro__en_1__width_1 (
12878 din,
12879 en,
12880 l1clk,
12881 scan_in,
12882 siclk,
12883 soclk,
12884 dout,
12885 scan_out);
12886wire [0:0] fdin;
12887
12888 input [0:0] din;
12889 input en;
12890 input l1clk;
12891 input scan_in;
12892
12893
12894 input siclk;
12895 input soclk;
12896
12897 output [0:0] dout;
12898 output scan_out;
12899assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
12900
12901
12902
12903
12904
12905
12906dff #(1) d0_0 (
12907.l1clk(l1clk),
12908.siclk(siclk),
12909.soclk(soclk),
12910.d(fdin[0:0]),
12911.si(scan_in),
12912.so(scan_out),
12913.q(dout[0:0])
12914);
12915
12916
12917
12918
12919
12920
12921
12922
12923
12924
12925
12926
12927endmodule
12928
12929
12930
12931
12932
12933
12934
12935
12936
12937
12938
12939
12940
12941// any PARAMS parms go into naming of macro
12942
12943module l2t_misbuf_ctl_msff_ctl_macro__en_1__width_4 (
12944 din,
12945 en,
12946 l1clk,
12947 scan_in,
12948 siclk,
12949 soclk,
12950 dout,
12951 scan_out);
12952wire [3:0] fdin;
12953wire [2:0] so;
12954
12955 input [3:0] din;
12956 input en;
12957 input l1clk;
12958 input scan_in;
12959
12960
12961 input siclk;
12962 input soclk;
12963
12964 output [3:0] dout;
12965 output scan_out;
12966assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}});
12967
12968
12969
12970
12971
12972
12973dff #(4) d0_0 (
12974.l1clk(l1clk),
12975.siclk(siclk),
12976.soclk(soclk),
12977.d(fdin[3:0]),
12978.si({scan_in,so[2:0]}),
12979.so({so[2:0],scan_out}),
12980.q(dout[3:0])
12981);
12982
12983
12984
12985
12986
12987
12988
12989
12990
12991
12992
12993
12994endmodule
12995
12996
12997
12998
12999
13000
13001
13002
13003
13004
13005
13006
13007
13008// any PARAMS parms go into naming of macro
13009
13010module l2t_misbuf_ctl_msff_ctl_macro__en_1__width_3 (
13011 din,
13012 en,
13013 l1clk,
13014 scan_in,
13015 siclk,
13016 soclk,
13017 dout,
13018 scan_out);
13019wire [2:0] fdin;
13020wire [1:0] so;
13021
13022 input [2:0] din;
13023 input en;
13024 input l1clk;
13025 input scan_in;
13026
13027
13028 input siclk;
13029 input soclk;
13030
13031 output [2:0] dout;
13032 output scan_out;
13033assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}});
13034
13035
13036
13037
13038
13039
13040dff #(3) d0_0 (
13041.l1clk(l1clk),
13042.siclk(siclk),
13043.soclk(soclk),
13044.d(fdin[2:0]),
13045.si({scan_in,so[1:0]}),
13046.so({so[1:0],scan_out}),
13047.q(dout[2:0])
13048);
13049
13050
13051
13052
13053
13054
13055
13056
13057
13058
13059
13060
13061endmodule
13062
13063
13064
13065
13066
13067
13068
13069
13070
13071// general mux macro for pass-gate and and-or muxes with/wout priority encoders
13072// also for pass-gate with decoder
13073
13074
13075
13076
13077
13078// any PARAMS parms go into naming of macro
13079
13080module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 (
13081 din0,
13082 sel0,
13083 din1,
13084 sel1,
13085 din2,
13086 sel2,
13087 din3,
13088 sel3,
13089 dout);
13090 input [3:0] din0;
13091 input sel0;
13092 input [3:0] din1;
13093 input sel1;
13094 input [3:0] din2;
13095 input sel2;
13096 input [3:0] din3;
13097 input sel3;
13098 output [3:0] dout;
13099
13100
13101
13102
13103
13104assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
13105 ( {4{sel1}} & din1[3:0]) |
13106 ( {4{sel2}} & din2[3:0]) |
13107 ( {4{sel3}} & din3[3:0]);
13108
13109
13110
13111
13112
13113endmodule
13114
13115
13116
13117
13118
13119
13120// any PARAMS parms go into naming of macro
13121
13122module l2t_misbuf_ctl_msff_ctl_macro__width_4 (
13123 din,
13124 l1clk,
13125 scan_in,
13126 siclk,
13127 soclk,
13128 dout,
13129 scan_out);
13130wire [3:0] fdin;
13131wire [2:0] so;
13132
13133 input [3:0] din;
13134 input l1clk;
13135 input scan_in;
13136
13137
13138 input siclk;
13139 input soclk;
13140
13141 output [3:0] dout;
13142 output scan_out;
13143assign fdin[3:0] = din[3:0];
13144
13145
13146
13147
13148
13149
13150dff #(4) d0_0 (
13151.l1clk(l1clk),
13152.siclk(siclk),
13153.soclk(soclk),
13154.d(fdin[3:0]),
13155.si({scan_in,so[2:0]}),
13156.so({so[2:0],scan_out}),
13157.q(dout[3:0])
13158);
13159
13160
13161
13162
13163
13164
13165
13166
13167
13168
13169
13170
13171endmodule
13172
13173
13174
13175
13176
13177
13178
13179
13180
13181// general mux macro for pass-gate and and-or muxes with/wout priority encoders
13182// also for pass-gate with decoder
13183
13184
13185
13186
13187
13188// any PARAMS parms go into naming of macro
13189
13190module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_3 (
13191 din0,
13192 sel0,
13193 din1,
13194 sel1,
13195 din2,
13196 sel2,
13197 din3,
13198 sel3,
13199 dout);
13200 input [2:0] din0;
13201 input sel0;
13202 input [2:0] din1;
13203 input sel1;
13204 input [2:0] din2;
13205 input sel2;
13206 input [2:0] din3;
13207 input sel3;
13208 output [2:0] dout;
13209
13210
13211
13212
13213
13214assign dout[2:0] = ( {3{sel0}} & din0[2:0] ) |
13215 ( {3{sel1}} & din1[2:0]) |
13216 ( {3{sel2}} & din2[2:0]) |
13217 ( {3{sel3}} & din3[2:0]);
13218
13219
13220
13221
13222
13223endmodule
13224
13225
13226// general mux macro for pass-gate and and-or muxes with/wout priority encoders
13227// also for pass-gate with decoder
13228
13229
13230
13231
13232
13233// any PARAMS parms go into naming of macro
13234
13235module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_3 (
13236 din0,
13237 sel0,
13238 din1,
13239 sel1,
13240 dout);
13241 input [2:0] din0;
13242 input sel0;
13243 input [2:0] din1;
13244 input sel1;
13245 output [2:0] dout;
13246
13247
13248
13249
13250
13251assign dout[2:0] = ( {3{sel0}} & din0[2:0] ) |
13252 ( {3{sel1}} & din1[2:0]);
13253
13254
13255
13256
13257
13258endmodule
13259
13260
13261
13262
13263
13264
13265// any PARAMS parms go into naming of macro
13266
13267module l2t_misbuf_ctl_msff_ctl_macro__width_11 (
13268 din,
13269 l1clk,
13270 scan_in,
13271 siclk,
13272 soclk,
13273 dout,
13274 scan_out);
13275wire [10:0] fdin;
13276wire [9:0] so;
13277
13278 input [10:0] din;
13279 input l1clk;
13280 input scan_in;
13281
13282
13283 input siclk;
13284 input soclk;
13285
13286 output [10:0] dout;
13287 output scan_out;
13288assign fdin[10:0] = din[10:0];
13289
13290
13291
13292
13293
13294
13295dff #(11) d0_0 (
13296.l1clk(l1clk),
13297.siclk(siclk),
13298.soclk(soclk),
13299.d(fdin[10:0]),
13300.si({scan_in,so[9:0]}),
13301.so({so[9:0],scan_out}),
13302.q(dout[10:0])
13303);
13304
13305
13306
13307
13308
13309
13310
13311
13312
13313
13314
13315
13316endmodule
13317
13318
13319
13320
13321
13322
13323
13324
13325
13326// general mux macro for pass-gate and and-or muxes with/wout priority encoders
13327// also for pass-gate with decoder
13328
13329
13330
13331
13332
13333// any PARAMS parms go into naming of macro
13334
13335module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_32 (
13336 din0,
13337 sel0,
13338 din1,
13339 sel1,
13340 dout);
13341 input [31:0] din0;
13342 input sel0;
13343 input [31:0] din1;
13344 input sel1;
13345 output [31:0] dout;
13346
13347
13348
13349
13350
13351assign dout[31:0] = ( {32{sel0}} & din0[31:0] ) |
13352 ( {32{sel1}} & din1[31:0]);
13353
13354
13355
13356
13357
13358endmodule
13359
13360
13361// general mux macro for pass-gate and and-or muxes with/wout priority encoders
13362// also for pass-gate with decoder
13363
13364
13365
13366
13367
13368// any PARAMS parms go into naming of macro
13369
13370module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_8 (
13371 din0,
13372 sel0,
13373 din1,
13374 sel1,
13375 din2,
13376 sel2,
13377 dout);
13378 input [7:0] din0;
13379 input sel0;
13380 input [7:0] din1;
13381 input sel1;
13382 input [7:0] din2;
13383 input sel2;
13384 output [7:0] dout;
13385
13386
13387
13388
13389
13390assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) |
13391 ( {8{sel1}} & din1[7:0]) |
13392 ( {8{sel2}} & din2[7:0]);
13393
13394
13395
13396
13397
13398endmodule
13399
13400
13401
13402
13403
13404
13405// any PARAMS parms go into naming of macro
13406
13407module l2t_misbuf_ctl_msff_ctl_macro__width_8 (
13408 din,
13409 l1clk,
13410 scan_in,
13411 siclk,
13412 soclk,
13413 dout,
13414 scan_out);
13415wire [7:0] fdin;
13416wire [6:0] so;
13417
13418 input [7:0] din;
13419 input l1clk;
13420 input scan_in;
13421
13422
13423 input siclk;
13424 input soclk;
13425
13426 output [7:0] dout;
13427 output scan_out;
13428assign fdin[7:0] = din[7:0];
13429
13430
13431
13432
13433
13434
13435dff #(8) d0_0 (
13436.l1clk(l1clk),
13437.siclk(siclk),
13438.soclk(soclk),
13439.d(fdin[7:0]),
13440.si({scan_in,so[6:0]}),
13441.so({so[6:0],scan_out}),
13442.q(dout[7:0])
13443);
13444
13445
13446
13447
13448
13449
13450
13451
13452
13453
13454
13455
13456endmodule
13457
13458
13459
13460
13461
13462
13463
13464
13465
13466// general mux macro for pass-gate and and-or muxes with/wout priority encoders
13467// also for pass-gate with decoder
13468
13469
13470
13471
13472
13473// any PARAMS parms go into naming of macro
13474
13475module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 (
13476 din0,
13477 sel0,
13478 din1,
13479 sel1,
13480 din2,
13481 sel2,
13482 dout);
13483 input [3:0] din0;
13484 input sel0;
13485 input [3:0] din1;
13486 input sel1;
13487 input [3:0] din2;
13488 input sel2;
13489 output [3:0] dout;
13490
13491
13492
13493
13494
13495assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
13496 ( {4{sel1}} & din1[3:0]) |
13497 ( {4{sel2}} & din2[3:0]);
13498
13499
13500
13501
13502
13503endmodule
13504
13505
13506// general mux macro for pass-gate and and-or muxes with/wout priority encoders
13507// also for pass-gate with decoder
13508
13509
13510
13511
13512
13513// any PARAMS parms go into naming of macro
13514
13515module l2t_misbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 (
13516 din0,
13517 sel0,
13518 din1,
13519 sel1,
13520 dout);
13521 input [7:0] din0;
13522 input sel0;
13523 input [7:0] din1;
13524 input sel1;
13525 output [7:0] dout;
13526
13527
13528
13529
13530
13531assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) |
13532 ( {8{sel1}} & din1[7:0]);
13533
13534
13535
13536
13537
13538endmodule
13539
Full OpenSPARC design & verification tarball including full HDL.