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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_oque_dp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_oque_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016
1017
1018module l2t_oque_dp (
1019 tcu_pce_ov,
1020 tcu_aclk,
1021 tcu_bclk,
1022 tcu_scan_en,
1023 tcu_clk_stop,
1024 tcu_muxtest,
1025 tcu_dectest,
1026 rtn_err_field_c7,
1027 arbdec_arbdp_inst_l1way_c7,
1028 arbdec_arbdp_inst_tid_c7,
1029 oqu_mmu_ld_hit_c7,
1030 arbdec_arbdp_l1way_c3,
1031 arbdec_arbdp_inst_nc_c7,
1032 csr_report_ldrc,
1033 arbdec_arbdp_inst_cpuid_c7,
1034 oqu_rqtyp_rtn_c7,
1035 dirvec_dirdp_way_info_c7,
1036 oqu_strst_ack_c7,
1037 arbdat_arbdp_oque_int_ret_c7,
1038 oqu_fwd_req_ret_c7,
1039 oqu_int_ack_c7,
1040 arbadr_arbdp_oque_l1_index_c7,
1041 oqu_imiss_hit_c8,
1042 decc_ret_data_c7,
1043 dirvec_dirdp_inval_pckt_c7,
1044 st_ack_data,
1045 sel_st_ack_c7,
1046 decc_ret_diag_data_c7,
1047 tagd_diag_data_c7,
1048 vuadpm_vuad_diag_data_c7,
1049 oq_array_data_out,
1050 oqu_pf_ack_c7,
1051 oqu_rmo_st_c7,
1052 oqu_atm_inst_ack_c7,
1053 oqu_diag_acc_c8,
1054 oqu_mux1_sel_data_c7,
1055 oqu_sel_array_out_l,
1056 oqu_mux_csr_sel_c7,
1057 oqu_sel_inval_c7,
1058 oqu_out_mux1_sel_c7,
1059 oqu_out_mux2_sel_c7,
1060 arbadr_arbdp_line_addr_c7,
1061 arb_dc_inval_vld_c7,
1062 arb_ic_inval_vld_c7,
1063 csr_rd_data_c8,
1064 l2clk,
1065 scan_out,
1066 scan_in,
1067 oque_oq_array_data_in,
1068 l2t_cpx_data_ca,
1069 oque_tid_c8,
1070 mb0_l2t_mbist_write_data,
1071 mbist_oqarray_sel,
1072 oqarray_rw_fail,
1073 oqarray_rd_en);
1074wire stop;
1075wire pce_ov;
1076wire siclk;
1077wire soclk;
1078wire se;
1079wire muxtst;
1080wire test;
1081wire sel_c8_n;
1082wire err_pkt_dispatch;
1083wire csr_report_ldrc_and_errkt;
1084wire nc_bit_c7_fnl;
1085wire tid_c7_buf_b0;
1086wire [1:0] arbdec_arbdp_inst_l1way_c7_buf;
1087wire arbdec_arbdp_inst_cpuid_c7_buf_b0;
1088wire arbadr_arbdp_oque_l1_index_c7_buf_b11;
1089wire sel_inval_c8;
1090wire ff_MERGED_scanin;
1091wire ff_MERGED_scanout;
1092wire oqu_strst_ack_c7_n;
1093wire csr_or_diag_sel_c7_127to112_n;
1094wire oqu_fwd_req_ret_c7_n;
1095wire oqu_mmu_ld_hit_c7_n;
1096wire dirvec_dirdp_way_info_sel;
1097wire mux1_sel_data_0_or_mux1_sel_data_1;
1098wire mux1_sel_data_2_or_oqu_int_ack;
1099wire oqu_mux_csr_sel_c7_n;
1100wire sel_st_ack_c7_n;
1101wire int_or_diag_sel_c7_n;
1102wire oqu_mux_csr_sel_c7_n_and_int_or_diag_sel_c7_and_sel_st_ack_n;
1103wire oqu_mux_csr_sel_c7_and_int_or_diag_sel_c7_and_sel_st_ack_n;
1104wire int_or_diag_sel_and_not_sel_st_ack;
1105wire csr_or_diag_sel_c7_111to64_n;
1106wire [2:0] ret_buf_c7;
1107wire ff_decc_data_0_scanin;
1108wire ff_decc_data_0_scanout;
1109wire ff_decc_data_1_scanin;
1110wire ff_decc_data_1_scanout;
1111wire ff_decc_data_2_scanin;
1112wire ff_decc_data_2_scanout;
1113wire ff_decc_data_3_scanin;
1114wire ff_decc_data_3_scanout;
1115wire ext_inval_data_0_scanin;
1116wire ext_inval_data_0_scanout;
1117wire ext_inval_data_1_scanin;
1118wire ext_inval_data_1_scanout;
1119wire ext_inval_data_2_scanin;
1120wire ext_inval_data_2_scanout;
1121wire ext_inval_data_3_scanin;
1122wire ext_inval_data_3_scanout;
1123wire [145:0] oque_oq_array_data_in_inv;
1124wire oque_oq_array_data_in_inv_ff_scanin;
1125wire oque_oq_array_data_in_inv_ff_scanout;
1126wire sel_inval_c8_n;
1127wire ff_data_rtn_d1_1_scanin;
1128wire ff_data_rtn_d1_1_scanout;
1129wire ff_data_rtn_d1_2_scanin;
1130wire ff_data_rtn_d1_2_scanout;
1131wire ff_data_rtn_d1_3_scanin;
1132wire ff_data_rtn_d1_3_scanout;
1133wire ff_data_rtn_d1_4_scanin;
1134wire ff_data_rtn_d1_4_scanout;
1135wire [3:0] mbist_oqarray_sel_r1;
1136wire [39:0] mbist_oqarray_dout;
1137wire ff_mbist_oqarray_dout_scanin;
1138wire ff_mbist_oqarray_dout_scanout;
1139wire [39:0] for_mbist_oqarray_dout;
1140wire ff_mbist_flop_scanin;
1141wire ff_mbist_flop_scanout;
1142wire [39:0] mb0_l2t_mbist_write_data_r1;
1143wire oqarray_rw_fail_unreg;
1144wire ff_mbist_flop1_scanin;
1145wire ff_mbist_flop1_scanout;
1146wire [39:0] mb0_l2t_mbist_write_data_r2;
1147wire oqarray_fail1;
1148wire oqarray_fail2;
1149wire ff_oqarray_rd_en_scanin;
1150wire ff_oqarray_rd_en_scanout;
1151wire oqarray_rd_en_r1;
1152wire oqarray_rd_en_r2;
1153wire oqarray_rw_fail_w;
1154wire oqarray_rd_en_r2_n;
1155wire oqu_sel_array_out_l_n;
1156wire oq_array_data_out_sel;
1157wire staged_data_out_sel;
1158wire [145:0] oque_cpx_data_c8_buff;
1159wire ff_tmp_cpx_data_ca_1_scanin;
1160wire ff_tmp_cpx_data_ca_1_scanout;
1161wire ff_tmp_cpx_data_ca_2_scanin;
1162wire ff_tmp_cpx_data_ca_2_scanout;
1163wire ff_tmp_cpx_data_ca_3_scanin;
1164wire ff_tmp_cpx_data_ca_3_scanout;
1165wire ff_tmp_cpx_data_ca_4_scanin;
1166wire ff_tmp_cpx_data_ca_4_scanout;
1167wire [37:0] mux2_sel_c8_0_ff;
1168wire ff_mux2_sel_c8_0_scanin;
1169wire ff_mux2_sel_c8_0_scanout;
1170wire [37:0] mux2_sel_c8_1_ff;
1171wire ff_mux2_sel_c8_1_scanin;
1172wire ff_mux2_sel_c8_1_scanout;
1173wire [37:0] mux2_sel_c8_2_ff;
1174wire ff_mux2_sel_c8_2_scanin;
1175wire ff_mux2_sel_c8_2_scanout;
1176
1177
1178 input tcu_pce_ov;
1179 input tcu_aclk;
1180 input tcu_bclk;
1181 input tcu_scan_en;
1182 input tcu_clk_stop;
1183 input tcu_muxtest;
1184 input tcu_dectest;
1185
1186//input oqu_l2_miss_c7 ; // NEW_PIN
1187//input oqu_cerr_ack_c7; // asynchronous corr err
1188//input oqu_uerr_ack_c7; // asynchronous uncorr err
1189//input [2:0] deccck_ret_err_c7;
1190input [2:0] rtn_err_field_c7;
1191
1192input [1:0] arbdec_arbdp_inst_l1way_c7 ;
1193input [2:0] arbdec_arbdp_inst_tid_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
1194input oqu_mmu_ld_hit_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
1195input [1:0] arbdec_arbdp_l1way_c3; // BS and SR 11/12/03 N2 Xbar Packet format change
1196
1197
1198input arbdec_arbdp_inst_nc_c7;
1199input csr_report_ldrc;
1200input [2:0] arbdec_arbdp_inst_cpuid_c7 ;
1201input [3:0] oqu_rqtyp_rtn_c7;
1202input [3:0] dirvec_dirdp_way_info_c7; // BS and SR 11/18/03 Support for 8 way I$
1203input oqu_strst_ack_c7;
1204input [17:0] arbdat_arbdp_oque_int_ret_c7;
1205
1206input oqu_fwd_req_ret_c7 ;
1207
1208input oqu_int_ack_c7;
1209input [11:6] arbadr_arbdp_oque_l1_index_c7;
1210input oqu_imiss_hit_c8;
1211input [127:0] decc_ret_data_c7;
1212input [111:0] dirvec_dirdp_inval_pckt_c7;
1213input [63:0] st_ack_data;
1214input sel_st_ack_c7;
1215input [38:0] decc_ret_diag_data_c7 ;
1216input [27:0] tagd_diag_data_c7;
1217input [38:0] vuadpm_vuad_diag_data_c7;
1218input [159:0] oq_array_data_out ;
1219input oqu_pf_ack_c7; // NEW_PIN from oqu.
1220input oqu_rmo_st_c7; // NEW_PIN from oqu.
1221
1222input oqu_atm_inst_ack_c7;
1223input oqu_diag_acc_c8;
1224
1225input [3:0] oqu_mux1_sel_data_c7; // mux sels
1226input oqu_sel_array_out_l; // Mux sel from oqu. NEW_PIN
1227input oqu_mux_csr_sel_c7;
1228input oqu_sel_inval_c7; // sel for oqarray_data_in
1229input [2:0] oqu_out_mux1_sel_c7; // sel for mux1
1230input [2:0] oqu_out_mux2_sel_c7; // sel for mux2
1231
1232
1233input [5:4] arbadr_arbdp_line_addr_c7; // from arbaddr dp
1234input arb_dc_inval_vld_c7; // from tag
1235input arb_ic_inval_vld_c7; // from tag
1236
1237input [63:0] csr_rd_data_c8;
1238
1239input l2clk;
1240
1241output scan_out;
1242input scan_in;
1243//output oqu_dispatched_err_pkt;
1244
1245output [`CPX_WIDTH-1:0] oque_oq_array_data_in ;
1246output [`CPX_WIDTH-1:0] l2t_cpx_data_ca;
1247output [5:0] oque_tid_c8 ; // BS and SR 11/12/03 N2 Xbar Packet format change
1248
1249input [7:0] mb0_l2t_mbist_write_data;
1250input [3:0] mbist_oqarray_sel;
1251output oqarray_rw_fail;
1252input oqarray_rd_en;
1253
1254assign stop = tcu_clk_stop;
1255assign pce_ov = tcu_pce_ov;
1256assign siclk = tcu_aclk;
1257assign soclk = tcu_bclk;
1258assign se = tcu_scan_en;
1259assign muxtst = tcu_muxtest;
1260assign test = tcu_dectest;
1261
1262
1263//assign scan_out = 1'b0;
1264
1265
1266
1267wire [`CPX_WIDTH-13:0] ext_inval_data_c8;
1268wire [`CPX_WIDTH-13:0] ext_ret_data_c8;
1269
1270wire [`CPX_WIDTH-1:0] staged_data_out_c9;
1271wire [`CPX_WIDTH-1:0] staged_cpx_packet_c9;
1272
1273
1274wire [2:0] inst_tid_c8; // BS and SR 11/12/03 N2 Xbar Packet format change
1275wire inst_nc_c8;
1276
1277wire [2:0] tid_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
1278wire nc_bit_c7 ;
1279
1280wire [2:0] tid_c8; // BS and SR 11/12/03 N2 Xbar Packet format change
1281wire [1:0] mmuid_c7; // BS and SR 11/12/03 N2 Xbar Packet format change
1282wire [1:0] arbdec_arbdp_l1way_c4; // BS and SR 11/12/03 N2 Xbar Packet format change
1283wire [1:0] arbdec_arbdp_l1way_c5; // BS and SR 11/12/03 N2 Xbar Packet format change
1284wire [1:0] arbdec_arbdp_l1way_c52; // BS 03/11/04 extra cycle for mem access
1285wire [1:0] arbdec_arbdp_l1way_c6; // BS and SR 11/12/03 N2 Xbar Packet format change
1286
1287
1288
1289wire [2:0] inval_buf_c7;
1290wire [2:0] inval_buf_c8;
1291
1292wire [38:0] tmp_inval_data_c7 ;
1293wire int_or_diag_sel_c7;
1294wire [127:0] ext_inval_data_c7;
1295
1296wire [2:0] mod_sz_field_st_c7 ;
1297wire [1:0] l1_way_c8;
1298wire sel_c8 ;
1299wire [2:0] inst_cpuid_c8;
1300wire [2:0] cpuid_c7;
1301wire [2:0] cpuid_c8;
1302
1303wire [5:0] inst_inval_index_c8;
1304wire [5:0] inval_index_c7;
1305wire [63:0] dir_or_csr_data;
1306
1307wire [2:0] async_error_c7;
1308
1309wire [2:0] ret_buf_c8;
1310wire [2:0] inval_way_c7;
1311wire [2:0] ret_way_c7;
1312wire [2:0] ret_way_c8;
1313wire [1:0] inst_l1way_c7;
1314wire [`CPX_WIDTH-1:0] tmp_cpx_data_ca;
1315wire [`CPX_WIDTH-1:0] tmp_cpx_data_ca_d1;
1316
1317wire [2:0] error_field_c7;
1318wire [2:0] error_field_c8;
1319wire [2:0] rtn_err_field_c8;
1320wire [`CPX_WIDTH-1:0] oque_cpx_data_c8;
1321wire [`CPX_WIDTH-1:0] oque_cpx_data_c8_muxout;
1322
1323
1324wire [3:0] hi_inval_c7 ;
1325wire [3:0] hi_inval_c8 ;
1326wire [3:0] cpx_hi_inval_c7;
1327
1328wire rmo_st_c8;
1329wire cpx_rmo_c7;
1330
1331wire csr_or_diag_sel_c7_111to64 ;
1332wire csr_or_diag_sel_c7_127to112 ;
1333wire [2:0] mux1_sel_c8 ;
1334wire [2:0] mux2_sel_c8 ;
1335
1336
1337////////////////////////////////////////////////////////////////////////////////
1338//____________________________________________________________________
1339//Pkt |bits|No |Load|I$f |I$f |Strm|Evct|Stor|Strm|Int | FP |Fwd |Err |
1340// | | | | 1 | 2 |Load| Inv|Ack |Stor| | |rep | |
1341// | | | | | | | | |Ack | | | | |
1342//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1343//Vld |144 | 1 | V | V | V | V | V | V | V | V | V | V | V |
1344//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1345//Rtn |143 | 4 |0000|0001|0001|0010|0011|0100|0110|0111|1000|1011|1100|
1346//Typ |140 | | | | | | | | | | | | |
1347//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1348//ERR |139 | 3 | V | V | V | V | X | X | X | X | X | V | V |
1349// |137 | | | | | | | | | | | | |
1350//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1351// NC |136 | 1 | V | V | V | V | V | V | V |flus| V |R/!W| X |
1352//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1353// |135 | 1 | T | T | T | T | X | T | T | X | T | X | 0 |
1354//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1355// |134 | 1 | T | T | T | T | X | T | T | X | T | X | 0 |
1356//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1357// |133 | 1 | WV | WV | WV | WV | X | X | X | X | X |tar | X |
1358//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1359// |132 | 1 | W | W | W | W | X | X | X | X | X |tar | X |
1360//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1361// |131 | 1 | W | W | W | W | X | P | X | X | X |tar | X |
1362//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1363// |130 | 1 | X | X | X | 0 | X | P | 0 | X | X | X | X |
1364//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1365// |129 | 1 |atm | X | X | 0 | X |atm | X | X | X | X | X |
1366//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1367// |128 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1368//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1369//data|127 |128| | | | |6PA,|3cpu|3cpu| | | | |
1370// |0 | | V | V | V | V |112 |6PA,|6pa,| | | + | |
1371// | | | | | | |Inv |112 |112 | V! | V* |Data|Add |
1372// | | | | | | | |Inv |Inv | | | | |
1373//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1374// | | | | | | | | | | | | | |
1375//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1376////////////////////////////////////////////////////////////////////////////////
1377
1378
1379////////////////////////////////////////////////////////////////////////////////
1380// In casse of Imiss or Diag instruction a bubble is inserted and
1381// a dummy instruction is inserted in the next cycle that looks
1382// like the current instruction. sel_c8 is used to select the
1383// bit fields for the dummy instruction, which is the delayed
1384// version of the original values.
1385
1386// assign sel_c8 = (oqu_imiss_hit_c8 | oqu_diag_acc_c8) ;
1387
1388l2t_oque_dp_or_macro__width_1 sel_c8_or_slice
1389 (
1390 .dout (sel_c8),
1391 .din0 (oqu_imiss_hit_c8),
1392 .din1 (oqu_diag_acc_c8)
1393 );
1394
1395
1396
1397////////////////////////////////////////////////////////////////////////////////
1398// TID (Thread ID), bit 136:134 of the CPX Packet
1399////////////////////////////////////////////////////////////////////////////////
1400//msff_macro ff_MERGED2 (width=12,stack=12r,dmsff=32x) // BS and SR 11/12/03 N2 Xbar Packet format change
1401// (.dout({inst_tid_c8[2:0],hi_inval_c8[3:0],rmo_st_c8,sel_inval_c8,cpuid_c8[2:0]}),
1402// .scan_in(ff_MERGED2_scanin),
1403// .scan_out(ff_MERGED2_scanout),
1404// .din({arbdec_arbdp_inst_tid_c7[2:0],hi_inval_c7[3:0],oqu_rmo_st_c7,oqu_sel_inval_c7,ext_inval_data_c7[120:118]}),
1405// .clk(l2clk),
1406// .en(1'b1),
1407//
1408// ) ;
1409
1410
1411l2t_oque_dp_inv_macro__width_1 sel_c8_inv_slice
1412 (
1413 .dout (sel_c8_n ),
1414 .din (sel_c8 )
1415 );
1416
1417
1418// bug id fix 91281
1419//assign nc_bit_c7_fnl = nc_bit_c7 | (csr_report_ldrc & (oqu_rqtyp_rtn_c7[3:0] == 4'hc));
1420
1421l2t_oque_dp_cmp_macro__width_8 cmp_rtn_type_err_ind_pkt
1422 (
1423 .dout (err_pkt_dispatch),
1424 .din0 ({4'b1,4'hc}),
1425 .din1 ({4'b1,oqu_rqtyp_rtn_c7[3:0]})
1426 );
1427l2t_oque_dp_and_macro__width_1 and_csr_report_ldrc_for_errpkt
1428 (
1429 .dout (csr_report_ldrc_and_errkt),
1430 .din0 (err_pkt_dispatch),
1431 .din1 (csr_report_ldrc)
1432 );
1433l2t_oque_dp_or_macro__width_1 or_csr_report_ldrc_for_errpkt
1434 (
1435 .dout (nc_bit_c7_fnl),
1436 .din0 (csr_report_ldrc_and_errkt),
1437 .din1 (nc_bit_c7)
1438 );
1439
1440
1441
1442l2t_oque_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_20r__width_20 mux_MERGED // BS and SR 11/12/03 N2 Xbar Packet format change
1443 (
1444 .dout({tid_c7[2:0],nc_bit_c7,inst_l1way_c7[1:0],cpuid_c7[2:0],inval_index_c7[5:0],cpx_rmo_c7,cpx_hi_inval_c7[3:0]}),
1445 .din0({arbdec_arbdp_inst_tid_c7[2:0],arbdec_arbdp_inst_nc_c7,arbdec_arbdp_inst_l1way_c7[1:0],
1446 arbdec_arbdp_inst_cpuid_c7[2:0],arbadr_arbdp_oque_l1_index_c7[11:6],oqu_rmo_st_c7,hi_inval_c7[3:0]}),
1447 .sel0(sel_c8_n),
1448 .din1({inst_tid_c8[2:0],inst_nc_c8,l1_way_c8[1:0],inst_cpuid_c8[2:0],inst_inval_index_c8[5:0],rmo_st_c8,hi_inval_c8[3:0]}),
1449 .sel1(sel_c8)
1450 ) ;
1451
1452
1453l2t_oque_dp_buff_macro__minbuff_1__stack_40r__width_5 MERGED_minbuff (
1454 .din ({tid_c7[0], arbdec_arbdp_inst_l1way_c7[1:0], arbdec_arbdp_inst_cpuid_c7[0], arbadr_arbdp_oque_l1_index_c7[11]}),
1455 .dout({tid_c7_buf_b0,arbdec_arbdp_inst_l1way_c7_buf[1:0],arbdec_arbdp_inst_cpuid_c7_buf_b0,arbadr_arbdp_oque_l1_index_c7_buf_b11}));
1456
1457
1458l2t_oque_dp_msff_macro__dmsff_32x__stack_40r__width_37 ff_MERGED // BS and SR 11/12/03 N2 Xbar Packet format change
1459 (.dout({inst_tid_c8[2:0],hi_inval_c8[3:0],rmo_st_c8,sel_inval_c8,cpuid_c8[2:0],
1460 tid_c8[2:0],l1_way_c8[1:0],inst_cpuid_c8[2:0],inst_inval_index_c8[5:0],
1461 inst_nc_c8,
1462 arbdec_arbdp_l1way_c4[1:0],
1463 arbdec_arbdp_l1way_c5[1:0],arbdec_arbdp_l1way_c52[1:0],arbdec_arbdp_l1way_c6[1:0],mmuid_c7[1:0]}),
1464 .scan_in(ff_MERGED_scanin),
1465 .scan_out(ff_MERGED_scanout),
1466 .din({arbdec_arbdp_inst_tid_c7[2:0],hi_inval_c7[3:0],oqu_rmo_st_c7, // 36:29
1467 oqu_sel_inval_c7,ext_inval_data_c7[120:118], // 28:25
1468 tid_c7[2:1],tid_c7_buf_b0,arbdec_arbdp_inst_l1way_c7_buf[1:0], // 24:20
1469 arbdec_arbdp_inst_cpuid_c7[2:1],arbdec_arbdp_inst_cpuid_c7_buf_b0, // 19:17
1470 arbadr_arbdp_oque_l1_index_c7_buf_b11,arbadr_arbdp_oque_l1_index_c7[10:6], // 16:11
1471 arbdec_arbdp_inst_nc_c7, // 10
1472 arbdec_arbdp_l1way_c3[1:0], // 09:08
1473 arbdec_arbdp_l1way_c4[1:0],arbdec_arbdp_l1way_c5[1:0],
1474 arbdec_arbdp_l1way_c52[1:0],arbdec_arbdp_l1way_c6[1:0]}),
1475 .clk(l2clk),
1476 .en(1'b1),
1477 .se(se),
1478 .siclk(siclk),
1479 .soclk(soclk),
1480 .pce_ov(pce_ov),
1481 .stop(stop)
1482
1483 ) ;
1484
1485
1486////////////////////////////////////////////////////////////////////////////////
1487// NC (Non Cachable) bit, bit 136 of the CPX Packet
1488////////////////////////////////////////////////////////////////////////////////
1489
1490////////////////////////////////////////////////////////////////////////////////
1491// RQTYP (Return request type), bit 143:140 of the CPX Packet
1492////////////////////////////////////////////////////////////////////////////////
1493
1494////////////////////////////////////////////////////////////////////////////////
1495// SIZE, bit 130:128 of the CPX Packet
1496//_____________________________________________________________________
1497//Pkt |bits|No |Load|I$f |I$f |Strm|Evct|Stor|Strm|Int | FP |Fwd |Err |
1498// | | | | 1 | 2 |Load| Inv|Ack |Stor| | |rep | |
1499// | | | | | | | | |Ack | | | | |
1500//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1501// |130 | 1 | X | X | X | 0 | X |P[0]| 0 | X | X | X | X |
1502//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1503// |129 | 1 |atm | X | X | 0 | X |atm | 0 | X | X | X | X |
1504//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1505// |128 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1506//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1507
1508////////////////////////////////////////////////////////////////////////////////
1509
1510
1511// sz_field == {P[0], atomic, 1'b0} for Store instruction
1512// == {0, 0, 0} for Streaming Store instruction // BS and SR 11/12/03 N2 Xbar Packet format change
1513// inst_l1way_c7 == P[1:0] in case of Store instruction
1514// == {0, 0} in case of Streaming Store instruction // BS and SR 11/12/03 N2 Xbar Packet format change
1515assign mod_sz_field_st_c7[2] = inst_l1way_c7[0] ;
1516assign mod_sz_field_st_c7[1] = oqu_atm_inst_ack_c7 ; // qualified.
1517assign mod_sz_field_st_c7[0] = 1'b0;
1518
1519l2t_oque_dp_inv_macro__width_1 oqu_strst_ack_c7_inv_macro
1520 (
1521 .dout (oqu_strst_ack_c7_n ),
1522 .din (oqu_strst_ack_c7 )
1523 );
1524
1525
1526l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_3r__width_3 mux_buf_c7
1527 (.dout (inval_buf_c7[2:0]),
1528 .din0 (mod_sz_field_st_c7[2:0]), .sel0 (oqu_strst_ack_c7_n),
1529 .din1 (3'b0), .sel1 (oqu_strst_ack_c7) // BS and SR 11/12/03 N2 Xbar Packet format change
1530 ) ;
1531
1532
1533// BS and SR 11/12/03 N2 Xbar Packet format change
1534// sz_field == {0, atomic, prefetch} for Load/Atomic/Prefetch data return
1535// == {0, 0, 0} for Streaming Load Data Return
1536
1537
1538
1539////////////////////////////////////////////////////////////////////////////////
1540// CPUID
1541////////////////////////////////////////////////////////////////////////////////
1542
1543
1544l2t_oque_dp_inv_macro__width_1 csr_or_diag_sel_c7_127to112_inv_slice
1545 (
1546 .dout (csr_or_diag_sel_c7_127to112_n ),
1547 .din (csr_or_diag_sel_c7_127to112 )
1548 );
1549
1550
1551l2t_oque_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14r__width_14 mux_MERGED2
1552 (
1553 .dout ({ext_inval_data_c7[125],ext_inval_data_c7[124:121],ext_inval_data_c7[120:118],ext_inval_data_c7[117:112]}),
1554 .din0 ({cpx_rmo_c7,cpx_hi_inval_c7[3:0],cpuid_c7[2:0],inval_index_c7[5:0]}),
1555 .sel0 (csr_or_diag_sel_c7_127to112_n),
1556 .din1 ({ext_inval_data_c7[61],ext_inval_data_c7[60:57],ext_inval_data_c7[56:54],ext_inval_data_c7[53:48]}),
1557 .sel1 (csr_or_diag_sel_c7_127to112)
1558 ) ;
1559
1560// assign cpuid_c8[2:0] = ext_inval_data_c8[120:118] ;
1561
1562
1563assign oque_tid_c8 = {cpuid_c8[2:0], tid_c8[2:0]} ; // BS and SR 11/12/03 N2 Xbar Packet format change
1564
1565
1566////////////////////////////////////////////////////////////////////////////////
1567// WAY-INFO
1568//_____________________________________________________________________
1569//Pkt |bits|No |Load|I$f |I$f |Strm|Evct|Stor|Strm|Int | FP |Fwd |Err |
1570// | | | | 1 | 2 |Load| Inv|Ack |Stor| | |rep | |
1571// | | | | | | | | |Ack | | | | |
1572//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1573// |133 | 1 | WV | WV | WV | WV | X | X | X | X | X |tar | X |
1574//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1575// |132 | 1 | W | W | W | W | X | X | X | X | X |tar | X |
1576//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1577// |131 | 1 | W | W | W | W | X |P[1]| X | X | X |tar | X |
1578//____|____|___|____|____|____|____|____|____|____|____|____|____|____|
1579//
1580// In case of Forward Request instruction, CPU ID field of the PCX packet will
1581// contain the Source of the Forward Request, that Surce ID will be returned as
1582// Target ID by the L2 in the Forward Reply packet. Target ID occupy same bit
1583// position in the Forward Reply packet as the Way Valid & Way bits for the
1584// Load & I$ fill packets.
1585////////////////////////////////////////////////////////////////////////////////
1586
1587
1588l2t_oque_dp_inv_macro__width_1 oqu_fwd_req_ret_c7_inv_slice
1589 (
1590 .dout (oqu_fwd_req_ret_c7_n ),
1591 .din (oqu_fwd_req_ret_c7 )
1592 );
1593
1594
1595l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_3r__width_3 mux_inval_way_c7
1596 (.dout (inval_way_c7[2:0]),
1597 .din0 ({2'b0,inst_l1way_c7[1]}), .sel0 (oqu_fwd_req_ret_c7_n),
1598 .din1 (cpuid_c7[2:0]), .sel1 (oqu_fwd_req_ret_c7)
1599 ) ;
1600
1601
1602//why ret_way_c7[2:0] != dirvec_dirdp_way_info_c7[2:0] ;
1603// BS and SR 11/12/03 N2 Xbar Packet format change
1604// assign dirvec_dirdp_way_info_sel = ~oqu_mmu_ld_hit_c7 & oqu_fwd_req_ret_c7_n;
1605
1606l2t_oque_dp_inv_macro__width_1 inv_oqu_mmu_ld_hit_c7
1607 (
1608 .dout (oqu_mmu_ld_hit_c7_n),
1609 .din (oqu_mmu_ld_hit_c7)
1610 );
1611
1612l2t_oque_dp_and_macro__width_1 and_dirvec_dirdp_way_info_sel
1613 (
1614 .dout (dirvec_dirdp_way_info_sel),
1615 .din0 (oqu_mmu_ld_hit_c7_n),
1616 .din1 (oqu_fwd_req_ret_c7_n)
1617 );
1618
1619
1620// BS 03/11/04 extra cycle for mem access
1621
1622
1623
1624l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_3__stack_3r__width_3 mux_ret_way_c7 // BS and SR 11/12/03 N2 Xbar Packet format change
1625 (.dout (ret_way_c7[2:0]),
1626 .din0 (dirvec_dirdp_way_info_c7[3:1]), .sel0 (dirvec_dirdp_way_info_sel), // BS and SR 11/18/03 Support for 8 way I$
1627 .din1 (cpuid_c7[2:0]), .sel1 (oqu_fwd_req_ret_c7),
1628 .din2 ({1'b0,mmuid_c7[1:0]}), .sel2 (oqu_mmu_ld_hit_c7) // BS and SR 11/12/03 N2 Xbar Packet format change
1629 ) ;
1630
1631
1632////////////////////////////////////////////////////////////////////////////////
1633// INVAL INDEX.
1634////////////////////////////////////////////////////////////////////////////////
1635// Index bits[11:6] for the L1$. Although for D$ bits<4,5,8,9,10> and for I$
1636// bits<5,8,9,10,11> are used as index bits in L1$, bits<11:6> are send by the
1637// L2. For D$ bit<11> will be ignored and four inval bits corresponding to
1638// bits<5:4> == 00, 01, 10 & 11 are send. For I$ two inval bits corresponding to
1639// the bit<5> == 0 & 1 are send.
1640
1641
1642
1643////////////////////////////////////////////////////////////////////////////////
1644// higher order bits or dir payload.
1645// added to support the invalidation packet.
1646////////////////////////////////////////////////////////////////////////////////
1647assign hi_inval_c7 = {arb_ic_inval_vld_c7, arb_dc_inval_vld_c7, arbadr_arbdp_line_addr_c7} ;
1648
1649
1650
1651////////////////////////////////////////////////////////////////
1652// bit # 125 of the payload of a inval* packet
1653////////////////////////////////////////////////////////////////
1654
1655
1656////////////////////////////////////////////////////////////////////////////////
1657// ERR FIELDS
1658// async errors from oqu.
1659// sync errors from decc.
1660// THe MSB of the error field is used by the Performance counter
1661// to count the number of misses for a Load/Imiss/StrmLoad instruction.
1662////////////////////////////////////////////////////////////////////////////////
1663//
1664///****************************************************************************/
1665///****************************************************************************/
1666///****************************************************************************/
1667///****************************************************************************/
1668///****************************************************************************/
1669//msff_macro ff_deccck_ret_err_c8 (width=1,stack=4r,dmsff=32x)
1670// (
1671// .scan_in(ff_deccck_ret_err_c8_scanin),
1672// .scan_out(ff_deccck_ret_err_c8_scanout),
1673// .dout(ret_err_c8_1),
1674// .clk(l2clk),
1675// .en(1'b1),
1676// .din(deccck_ret_err_c7[1])) ;
1677//
1678//assign async_error_c7 = {oqu_l2_miss_c7,
1679// oqu_uerr_ack_c7, // comes from pst/atomic stores and Dis errs from FB
1680// oqu_cerr_ack_c7} ; // comes from pst/atomic stores and Dis errs from FB
1681//
1682//
1683//assign error_field_c7[2] = (async_error_c7[2]) ;
1684//
1685//// assign error_field_c7[1] = (async_error_c7[1] | (deccck_ret_err_c8[1] & oqu_imiss_hit_c8)) ;
1686//
1687//and_macro error_field_c7_2_and_slice (width=1)
1688// (
1689// .dout (deccck_ret_err_1_and_oqu_imiss_hit_c8),
1690// .din0 (oqu_imiss_hit_c8),
1691// .din1 (ret_err_c8_1)
1692// );
1693//
1694//or_macro error_field_c7_1_or_slice (width=1)
1695// (
1696// .dout (error_field_c7[1]),
1697// .din0 (async_error_c7[1]),
1698// .din1 (deccck_ret_err_1_and_oqu_imiss_hit_c8)
1699// );
1700//
1701//assign error_field_c7[0] = (async_error_c7[0]) ;
1702//
1703//// assign rtn_err_field_c8 = error_field_c8 | deccck_ret_err_c8 ;
1704//
1705//or_macro rtn_err_field_c8_or_slice (width=3)
1706// (
1707// .dout (rtn_err_field_c7[2:0]),
1708// .din0 (error_field_c7[2:0]),
1709// .din1 (deccck_ret_err_c7[2:0])
1710// );
1711//
1712///****************************************************************************/
1713///****************************************************************************/
1714///****************************************************************************/
1715///****************************************************************************/
1716///****************************************************************************/
1717
1718
1719////////////////////////////////////////////////////////////////////////////////
1720// DATA MUXES
1721////////////////////////////////////////////////////////////////////////////////
1722
1723//assign int_or_diag_sel_c7 = (oqu_mux1_sel_data_c7[0] | oqu_mux1_sel_data_c7[1] |
1724// oqu_mux1_sel_data_c7[2] | oqu_int_ack_c7) ;
1725
1726l2t_oque_dp_or_macro__width_1 mux1_sel_data_0_or_mux1_sel_data_1_slice
1727 (
1728 .dout (mux1_sel_data_0_or_mux1_sel_data_1),
1729 .din0 (oqu_mux1_sel_data_c7[0]),
1730 .din1 (oqu_mux1_sel_data_c7[1])
1731 );
1732
1733l2t_oque_dp_or_macro__width_1 mux1_sel_data_2_or_oqu_int_ack_slice
1734 (
1735 .dout (mux1_sel_data_2_or_oqu_int_ack),
1736 .din0 (oqu_mux1_sel_data_c7[2]),
1737 .din1 (oqu_int_ack_c7)
1738 );
1739
1740l2t_oque_dp_or_macro__width_1 int_or_diag_sel_or_slice
1741 (
1742 .dout (int_or_diag_sel_c7),
1743 .din0 (mux1_sel_data_2_or_oqu_int_ack),
1744 .din1 (mux1_sel_data_0_or_mux1_sel_data_1)
1745 );
1746
1747l2t_oque_dp_mux_macro__mux_pgpe__ports_4__stack_39r__width_39 mux_tmp_inv_data_c7
1748 (
1749 .dout (tmp_inval_data_c7[38:0]),
1750 .din0 (decc_ret_diag_data_c7[38:0]),
1751 .sel0 (oqu_mux1_sel_data_c7[0]),
1752 .din1 ({11'b0, tagd_diag_data_c7[27:0]}),
1753 .sel1 (oqu_mux1_sel_data_c7[1]),
1754 .din2 (vuadpm_vuad_diag_data_c7[38:0]),
1755 .sel2 (oqu_mux1_sel_data_c7[2]),
1756 .din3 ({21'b0, arbdat_arbdp_oque_int_ret_c7[17:0]}),
1757 .muxtst(muxtst),
1758 .test(test)
1759// .sel3 (oqu_mux1_sel_data_c7[3])
1760 );
1761
1762
1763l2t_oque_dp_inv_macro__width_1 oqu_mux_csr_sel_c7_inv_macro
1764 (
1765 .dout (oqu_mux_csr_sel_c7_n ),
1766 .din (oqu_mux_csr_sel_c7 )
1767 );
1768
1769
1770//mux_macro mux_csr_sel_1 (width=32,ports=2,mux=aonpe,stack=32r,dmux=4x)
1771// (.dout (dir_or_csr_data[63:32]),
1772// .din0 (dirvec_dirdp_inval_pckt_c7[63:32]), .sel0 (oqu_mux_csr_sel_c7_n),
1773// .din1 (csr_rd_data_c8[63:32]), .sel1 (oqu_mux_csr_sel_c7)
1774// ) ;
1775//
1776//mux_macro mux_csr_sel_2 (width=32,ports=2,mux=aonpe,stack=32r,dmux=4x)
1777// (.dout (dir_or_csr_data[31:0]),
1778// .din0 (dirvec_dirdp_inval_pckt_c7[31:0]), .sel0 (oqu_mux_csr_sel_c7_n),
1779// .din1 (csr_rd_data_c8[31:0]), .sel1 (oqu_mux_csr_sel_c7)
1780// ) ;
1781//
1782l2t_oque_dp_inv_macro__dinv_16x__width_2 int_or_diag_sel_c7_inv_slice
1783 (
1784 .dout ({sel_st_ack_c7_n,int_or_diag_sel_c7_n}),
1785 .din ({sel_st_ack_c7,int_or_diag_sel_c7})
1786 );
1787
1788//mux_macro int_diag_sel63to0_1 (width=32,ports=2,mux=aonpe,stack=32r,dmux=8x)
1789// (.dout (ext_inval_data_c7[63:32]),
1790// .din0 (dir_or_csr_data[63:32]), .sel0 (int_or_diag_sel_c7_n),
1791// .din1 ({25'b0,tmp_inval_data_c7[38:32]}), .sel1 (int_or_diag_sel_c7)
1792// ) ;
1793//
1794//mux_macro int_diag_sel63to0_2 (width=32,ports=2,mux=aonpe,stack=32r,dmux=8x)
1795// (.dout (ext_inval_data_c7[31:0]),
1796// .din0 (dir_or_csr_data[31:0]), .sel0 (int_or_diag_sel_c7_n),
1797// .din1 (tmp_inval_data_c7[31:0]), .sel1 (int_or_diag_sel_c7)
1798// ) ;
1799//
1800
1801
1802l2t_oque_dp_and_macro__dinv_32x__dnand_16x__ports_3__width_2 and_csr_sel_int_or_diag_sel
1803 (
1804 .dout ({oqu_mux_csr_sel_c7_n_and_int_or_diag_sel_c7_and_sel_st_ack_n, oqu_mux_csr_sel_c7_and_int_or_diag_sel_c7_and_sel_st_ack_n}),
1805 .din0 ({oqu_mux_csr_sel_c7_n,oqu_mux_csr_sel_c7}),
1806 .din1 ({int_or_diag_sel_c7_n,int_or_diag_sel_c7_n}),
1807 .din2 ({sel_st_ack_c7_n,sel_st_ack_c7_n})
1808 );
1809
1810l2t_oque_dp_and_macro__width_1 and_int_or_diag_sel_and_not_sel_st_ack
1811 (
1812 .dout (int_or_diag_sel_and_not_sel_st_ack),
1813 .din0 (int_or_diag_sel_c7),
1814 .din1 (sel_st_ack_c7_n)
1815 );
1816
1817
1818l2t_oque_dp_mux_macro__dmux_32x__mux_pgnpe__ports_4__stack_32r__width_32 mux_csr_int_diag_sel63to0_1
1819 (
1820 .dout (ext_inval_data_c7[63:32]),
1821 .din0 (dirvec_dirdp_inval_pckt_c7[63:32]),
1822 .din1 (csr_rd_data_c8[63:32]),
1823 .din2 ({25'b0,tmp_inval_data_c7[38:32]}),
1824 .din3 (st_ack_data[63:32]),
1825 .sel0 (oqu_mux_csr_sel_c7_n_and_int_or_diag_sel_c7_and_sel_st_ack_n),
1826 .sel1 (oqu_mux_csr_sel_c7_and_int_or_diag_sel_c7_and_sel_st_ack_n),
1827 .sel2 (int_or_diag_sel_and_not_sel_st_ack),
1828 .sel3 (sel_st_ack_c7),
1829 .muxtst(muxtst)
1830 );
1831
1832
1833l2t_oque_dp_mux_macro__dmux_32x__mux_pgnpe__ports_4__stack_32r__width_32 mux_csr_int_diag_sel63to0_2
1834 (
1835 .dout (ext_inval_data_c7[31:0]),
1836 .din0 (dirvec_dirdp_inval_pckt_c7[31:0]),
1837 .din1 (csr_rd_data_c8[31:0]),
1838 .din2 (tmp_inval_data_c7[31:0]),
1839 .din3 (st_ack_data[31:0]),
1840 .sel0 (oqu_mux_csr_sel_c7_n_and_int_or_diag_sel_c7_and_sel_st_ack_n),
1841 .sel1 (oqu_mux_csr_sel_c7_and_int_or_diag_sel_c7_and_sel_st_ack_n),
1842 .sel2 (int_or_diag_sel_and_not_sel_st_ack),
1843 .sel3 (sel_st_ack_c7),
1844 .muxtst(muxtst)
1845 );
1846
1847// assign csr_or_diag_sel_c7_111to64 = ( int_or_diag_sel_c7 | oqu_mux_csr_sel_c7) ;
1848// assign csr_or_diag_sel_c7_127to112 = (~int_or_diag_sel_c7 & oqu_mux_csr_sel_c7) ;
1849
1850
1851l2t_oque_dp_and_macro__width_1 csr_or_diag_sel_c7_127to112_slice
1852 (
1853 .dout (csr_or_diag_sel_c7_127to112),
1854 .din0 (int_or_diag_sel_c7_n),
1855 .din1 (oqu_mux_csr_sel_c7)
1856 );
1857
1858l2t_oque_dp_or_macro__width_1 csr_or_diag_sel_c7_111to64_slice
1859 (
1860 .dout (csr_or_diag_sel_c7_111to64),
1861 .din0 (int_or_diag_sel_c7),
1862 .din1 (oqu_mux_csr_sel_c7)
1863 );
1864
1865l2t_oque_dp_inv_macro__width_1 csr_or_diag_sel_c7_111to64_inv_slice
1866 (
1867 .dout (csr_or_diag_sel_c7_111to64_n ),
1868 .din (csr_or_diag_sel_c7_111to64 )
1869 );
1870
1871l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_48r__width_48 int_diag_sel111to64
1872 (.dout (ext_inval_data_c7[111:64]),
1873 .din0 (dirvec_dirdp_inval_pckt_c7[111:64]), .sel0 (csr_or_diag_sel_c7_111to64_n),
1874 .din1 (ext_inval_data_c7[47:0]) // .sel1 (csr_or_diag_sel_c7_111to64)
1875 ) ;
1876
1877
1878/////////////////////////////////////////////////////////////////////////
1879// Flop ret_data //
1880/////////////////////////////////////////////////////////////////////////
1881
1882// inv_macro inv_ret_way_c7 (width=3)
1883// (
1884// .dout (ret_way_c7_inv[2:0] ),
1885// .din (ret_way_c7[2:0] )
1886// );
1887
1888assign ret_buf_c7[2:0] = {dirvec_dirdp_way_info_c7[0],oqu_atm_inst_ack_c7,oqu_pf_ack_c7} ;
1889// inv_macro inv_ret_buf_c7 (width=3)
1890// (
1891// .dout (ret_buf_c7_inv[2:0] ),
1892// .din (ret_buf_c7[2:0] )
1893// );
1894
1895l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_24 ff_decc_data_0
1896 (.dout_l(ext_ret_data_c8[133:110]),
1897 .din({ret_way_c7[2:0],ret_buf_c7[2:0],decc_ret_data_c7[127:110]}),
1898 .scan_in(ff_decc_data_0_scanin),
1899 .scan_out(ff_decc_data_0_scanout),
1900 .clk(l2clk),
1901 .en(1'b1),
1902 .se(se),
1903 .siclk(siclk),
1904 .soclk(soclk),
1905 .pce_ov(pce_ov),
1906 .stop(stop)
1907
1908 ) ;
1909
1910
1911l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 ff_decc_data_1
1912 (.dout_l(ext_ret_data_c8[109:74]),
1913 .din(decc_ret_data_c7[109:74]),
1914 .scan_in(ff_decc_data_1_scanin),
1915 .scan_out(ff_decc_data_1_scanout),
1916 .clk(l2clk),
1917 .en(1'b1),
1918 .se(se),
1919 .siclk(siclk),
1920 .soclk(soclk),
1921 .pce_ov(pce_ov),
1922 .stop(stop)
1923
1924 ) ;
1925
1926l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 ff_decc_data_2
1927 (.dout_l(ext_ret_data_c8[73:38]),
1928 .din(decc_ret_data_c7[73:38]),
1929 .scan_in(ff_decc_data_2_scanin),
1930 .scan_out(ff_decc_data_2_scanout),
1931 .clk(l2clk),
1932 .en(1'b1),
1933 .se(se),
1934 .siclk(siclk),
1935 .soclk(soclk),
1936 .pce_ov(pce_ov),
1937 .stop(stop)
1938
1939 ) ;
1940
1941l2t_oque_dp_msffi_macro__dmsffi_16x__stack_38r__width_38 ff_decc_data_3
1942 (.dout_l(ext_ret_data_c8[37:0]),
1943 .din(decc_ret_data_c7[37:0]),
1944 .scan_in(ff_decc_data_3_scanin),
1945 .scan_out(ff_decc_data_3_scanout),
1946 .clk(l2clk),
1947 .en(1'b1),
1948 .se(se),
1949 .siclk(siclk),
1950 .soclk(soclk),
1951 .pce_ov(pce_ov),
1952 .stop(stop)
1953
1954 ) ;
1955
1956/////////////////////////////////////////////////////////////////////////
1957// Flop ext_inval_data //
1958/////////////////////////////////////////////////////////////////////////
1959l2t_oque_dp_msffi_macro__dmsffi_16x__stack_34r__width_24 ext_inval_data_0 //
1960 (.dout_l(ext_inval_data_c8[133:110]),
1961 .din ({inval_way_c7[2:0],inval_buf_c7[2:0],ext_inval_data_c7[127:110]}),
1962 .scan_in(ext_inval_data_0_scanin),
1963 .scan_out(ext_inval_data_0_scanout),
1964 .clk(l2clk),
1965 .en(1'b1),
1966 .se(se),
1967 .siclk(siclk),
1968 .soclk(soclk),
1969 .pce_ov(pce_ov),
1970 .stop(stop)
1971
1972 ) ;
1973
1974l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 ext_inval_data_1 //
1975 (.dout_l(ext_inval_data_c8[109:74]),
1976 .din(ext_inval_data_c7[109:74]),
1977 .scan_in(ext_inval_data_1_scanin),
1978 .scan_out(ext_inval_data_1_scanout),
1979 .clk(l2clk),
1980 .en(1'b1),
1981 .se(se),
1982 .siclk(siclk),
1983 .soclk(soclk),
1984 .pce_ov(pce_ov),
1985 .stop(stop)
1986
1987 ) ;
1988
1989l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 ext_inval_data_2 //
1990 (.dout_l(ext_inval_data_c8[73:38]),
1991 .din(ext_inval_data_c7[73:38]),
1992 .scan_in(ext_inval_data_2_scanin),
1993 .scan_out(ext_inval_data_2_scanout),
1994 .clk(l2clk),
1995 .en(1'b1),
1996 .se(se),
1997 .siclk(siclk),
1998 .soclk(soclk),
1999 .pce_ov(pce_ov),
2000 .stop(stop)
2001
2002 ) ;
2003
2004l2t_oque_dp_msffi_macro__dmsffi_16x__stack_38r__width_38 ext_inval_data_3 //
2005 (.dout_l(ext_inval_data_c8[37:0]),
2006 .din(ext_inval_data_c7[37:0]),
2007 .scan_in(ext_inval_data_3_scanin),
2008 .scan_out(ext_inval_data_3_scanout),
2009 .clk(l2clk),
2010 .en(1'b1),
2011 .se(se),
2012 .siclk(siclk),
2013 .soclk(soclk),
2014 .pce_ov(pce_ov),
2015 .stop(stop)
2016
2017 ) ;
2018
2019/////////////////////////////////////////////////////////////////////////
2020// Flop top oque_oq_array_data
2021/////////////////////////////////////////////////////////////////////////
2022
2023l2t_oque_dp_msffi_macro__dmsffi_16x__stack_12r__width_11 oque_oq_array_data_in_inv_ff //
2024 (.dout_l(oque_oq_array_data_in_inv[144:134]),
2025 .din ({oqu_rqtyp_rtn_c7[3:0],rtn_err_field_c7[2:0],nc_bit_c7_fnl,tid_c7[2:0]}),
2026 .scan_in(oque_oq_array_data_in_inv_ff_scanin),
2027 .scan_out(oque_oq_array_data_in_inv_ff_scanout),
2028 .clk(l2clk),
2029 .en(1'b1),
2030 .se(se),
2031 .siclk(siclk),
2032 .soclk(soclk),
2033 .pce_ov(pce_ov),
2034 .stop(stop)
2035
2036 ) ;
2037
2038
2039
2040
2041// assign ext_ret_data_c8[`CPX_WYVLD:`CPX_WY_LO] = ret_way_c8 ; // 133:131
2042// assign ext_ret_data_c8[`CPX_BF_HI:`CPX_BF_LO] = ret_buf_c8 ; // 130:128
2043// assign ext_ret_data_c8[127:0] = decc_ret_data_c8 ;
2044
2045// assign ext_inval_data_c8[`CPX_WYVLD:`CPX_WY_LO] = inval_way_c8 ; // 133:131
2046// assign ext_inval_data_c8[`CPX_BF_HI:`CPX_BF_LO] = inval_buf_c8 ; // 130:128
2047
2048//assign ext_inval_data_c8[127:126] = 2'b0 ;
2049//assign ext_inval_data_c8[125] = cpx_rmo_c8 ;
2050//assign ext_inval_data_c8[124:121] = cpx_hi_inval_c8 ;
2051//assign ext_inval_data_c8[120:118] = cpuid_c8 ;
2052//assign ext_inval_data_c8[117:112] = inval_index_c8 ;
2053
2054
2055l2t_oque_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2r__width_2 int_diag_sel127to126
2056 (.dout (ext_inval_data_c7[127:126]),
2057 .din0 (2'b0), .sel0 (csr_or_diag_sel_c7_127to112_n),
2058 .din1 (ext_inval_data_c7[63:62]), .sel1 (csr_or_diag_sel_c7_127to112)
2059 ) ;
2060
2061
2062////////////////////////////////////////////////////////////////////////////////
2063// OQ ARRAY DATA IN
2064// Data needs to be flopped in OQ ARRAY
2065// Array is written in phase 2 of C6 .
2066////////////////////////////////////////////////////////////////////////////////
2067
2068
2069l2t_oque_dp_inv_macro__dinv_32x__width_1 sel_inval_c8_inv_slice
2070 (
2071 .dout (sel_inval_c8_n ),
2072 .din (sel_inval_c8 )
2073 );
2074
2075// inv_macro inv_oqu_rqtyp_rtn_c7 (width=4)
2076// (
2077// .dout (oqu_rqtyp_rtn_c7_inv[3:0] ),
2078// .din (oqu_rqtyp_rtn_c7[3:0] )
2079// );
2080
2081// inv_macro inv_tid_c7 (width=3)
2082// (
2083// .dout (tid_c7_inv[2:0] ),
2084// .din (tid_c7[2:0] )
2085// );
2086
2087// this data will be delayed by 4 gates after the negative edge
2088l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_36r__width_36 mux_oq_in_data_c8_1
2089 ( .dout (oque_oq_array_data_in_inv[`CPX_WIDTH-13:98]), // 133:0
2090 .din0 (ext_inval_data_c8[`CPX_WIDTH-13:98]), .sel0 (sel_inval_c8),
2091 .din1 (ext_ret_data_c8[`CPX_WIDTH-13:98]), .sel1 (sel_inval_c8_n)
2092 ) ;
2093
2094l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_36r__width_36 mux_oq_in_data_c8_2
2095 ( .dout (oque_oq_array_data_in_inv[97:62]), // 133:0
2096 .din0 (ext_inval_data_c8[97:62]), .sel0 (sel_inval_c8),
2097 .din1 (ext_ret_data_c8[97:62]), .sel1 (sel_inval_c8_n)
2098 ) ;
2099
2100l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_36r__width_36 mux_oq_in_data_c8_3
2101 ( .dout (oque_oq_array_data_in_inv[61:26]), // 133:0
2102 .din0 (ext_inval_data_c8[61:26]), .sel0 (sel_inval_c8),
2103 .din1 (ext_ret_data_c8[61:26]), .sel1 (sel_inval_c8_n)
2104 ) ;
2105
2106l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_26r__width_26 mux_oq_in_data_c8_4
2107 ( .dout (oque_oq_array_data_in_inv[25:0]), // 133:0
2108 .din0 (ext_inval_data_c8[25:0]), .sel0 (sel_inval_c8),
2109 .din1 (ext_ret_data_c8[25:0]), .sel1 (sel_inval_c8_n)
2110 ) ;
2111
2112//////////////////////////////////////////////////////////////////
2113// Invert back oque_oq_array_data //
2114//////////////////////////////////////////////////////////////////
2115l2t_oque_dp_inv_macro__stack_38r__width_38 inv1_oque_oq_array_data_in
2116 (
2117 .dout (oque_oq_array_data_in[37:0]),
2118 .din (oque_oq_array_data_in_inv[37:0])
2119 );
2120
2121
2122 l2t_oque_dp_inv_macro__stack_36r__width_36 inv2_oque_oq_array_data_in
2123 (
2124 .dout (oque_oq_array_data_in[73:38]),
2125 .din (oque_oq_array_data_in_inv[73:38])
2126 );
2127
2128 l2t_oque_dp_inv_macro__stack_36r__width_36 inv3_oque_oq_array_data_in
2129 (
2130 .dout (oque_oq_array_data_in[109:74]),
2131 .din (oque_oq_array_data_in_inv[109:74])
2132 );
2133
2134 l2t_oque_dp_inv_macro__stack_36r__width_35 inv4_oque_oq_array_data_in
2135 (
2136 .dout (oque_oq_array_data_in[144:110]),
2137 .din (oque_oq_array_data_in_inv[144:110])
2138 );
2139
2140
2141assign oque_oq_array_data_in[145] = 1'b1 ;
2142//////////////////////////////////////////////////////////////////
2143l2t_oque_dp_msff_macro__stack_36r__width_36 ff_data_rtn_d1_1
2144 (.dout(staged_data_out_c9[`CPX_WIDTH-1:110]),
2145 .scan_in(ff_data_rtn_d1_1_scanin),
2146 .scan_out(ff_data_rtn_d1_1_scanout),
2147 .din(oque_oq_array_data_in[`CPX_WIDTH-1:110]),
2148 .clk(l2clk),
2149 .en(1'b1),
2150 .se(se),
2151 .siclk(siclk),
2152 .soclk(soclk),
2153 .pce_ov(pce_ov),
2154 .stop(stop)
2155
2156 ) ;
2157
2158l2t_oque_dp_msff_macro__stack_36r__width_36 ff_data_rtn_d1_2
2159 (.dout(staged_data_out_c9[109:74]),
2160 .scan_in(ff_data_rtn_d1_2_scanin),
2161 .scan_out(ff_data_rtn_d1_2_scanout),
2162 .din(oque_oq_array_data_in[109:74]),
2163 .clk(l2clk),
2164 .en(1'b1),
2165 .se(se),
2166 .siclk(siclk),
2167 .soclk(soclk),
2168 .pce_ov(pce_ov),
2169 .stop(stop)
2170
2171 ) ;
2172l2t_oque_dp_msff_macro__stack_36r__width_36 ff_data_rtn_d1_3
2173 (.dout(staged_data_out_c9[73:38]),
2174 .scan_in(ff_data_rtn_d1_3_scanin),
2175 .scan_out(ff_data_rtn_d1_3_scanout),
2176 .din(oque_oq_array_data_in[73:38]),
2177 .clk(l2clk),
2178 .en(1'b1),
2179 .se(se),
2180 .siclk(siclk),
2181 .soclk(soclk),
2182 .pce_ov(pce_ov),
2183 .stop(stop)
2184
2185 ) ;
2186l2t_oque_dp_msff_macro__stack_38r__width_38 ff_data_rtn_d1_4
2187 (.dout(staged_data_out_c9[37:0]),
2188 .scan_in(ff_data_rtn_d1_4_scanin),
2189 .scan_out(ff_data_rtn_d1_4_scanout),
2190 .din(oque_oq_array_data_in[37:0]),
2191 .clk(l2clk),
2192 .en(1'b1),
2193 .se(se),
2194 .siclk(siclk),
2195 .soclk(soclk),
2196 .pce_ov(pce_ov),
2197 .stop(stop)
2198 ) ;
2199
2200
2201l2t_oque_dp_msff_macro__stack_44r__width_44 ff_mbist_oqarray_dout
2202 (.dout({mbist_oqarray_sel_r1[3:0],mbist_oqarray_dout[39:0]}),
2203 .scan_in(ff_mbist_oqarray_dout_scanin),
2204 .scan_out(ff_mbist_oqarray_dout_scanout),
2205 .din({mbist_oqarray_sel[3:0],for_mbist_oqarray_dout[39:0]}),
2206 .clk(l2clk),
2207 .en(1'b1),
2208 .se(se),
2209 .siclk(siclk),
2210 .soclk(soclk),
2211 .pce_ov(pce_ov),
2212 .stop(stop)
2213 );
2214
2215
2216l2t_oque_dp_msff_macro__stack_42r__width_41 ff_mbist_flop
2217 (
2218 .scan_in(ff_mbist_flop_scanin),
2219 .scan_out(ff_mbist_flop_scanout),
2220 .dout ({oqarray_rw_fail,mb0_l2t_mbist_write_data_r1[39:0]}),
2221 .din ({oqarray_rw_fail_unreg,{5{mb0_l2t_mbist_write_data[7:0]}}}),
2222 .clk (l2clk),
2223 .en(1'b1),
2224 .se(se),
2225 .siclk(siclk),
2226 .soclk(soclk),
2227 .pce_ov(pce_ov),
2228 .stop(stop)
2229 );
2230
2231l2t_oque_dp_msff_macro__stack_40r__width_40 ff_mbist_flop1
2232 (
2233 .scan_in(ff_mbist_flop1_scanin),
2234 .scan_out(ff_mbist_flop1_scanout),
2235 .dout (mb0_l2t_mbist_write_data_r2[39:0]),
2236 .din (mb0_l2t_mbist_write_data_r1[39:0]),
2237 .clk (l2clk),
2238 .en(1'b1),
2239 .se(se),
2240 .siclk(siclk),
2241 .soclk(soclk),
2242 .pce_ov(pce_ov),
2243 .stop(stop)
2244 );
2245
2246l2t_oque_dp_cmp_macro__dcmp_8x__width_32 mbist_first
2247 (
2248 .dout (oqarray_fail1),
2249 .din0 (mb0_l2t_mbist_write_data_r2[31:0]),
2250 .din1 (mbist_oqarray_dout[31:0])
2251 );
2252l2t_oque_dp_cmp_macro__dcmp_8x__width_8 mbist_second
2253 (
2254 .dout (oqarray_fail2),
2255 .din0 (mb0_l2t_mbist_write_data_r2[39:32]),
2256 .din1 (mbist_oqarray_dout[39:32])
2257 );
2258
2259
2260
2261l2t_oque_dp_msff_macro__stack_4r__width_2 ff_oqarray_rd_en
2262 (
2263 .scan_in(ff_oqarray_rd_en_scanin),
2264 .scan_out(ff_oqarray_rd_en_scanout),
2265 .dout({oqarray_rd_en_r1,oqarray_rd_en_r2}),
2266 .din({oqarray_rd_en,oqarray_rd_en_r1}),
2267 .clk(l2clk),
2268 .en(1'b1),
2269 .se(se),
2270 .siclk(siclk),
2271 .soclk(soclk),
2272 .pce_ov(pce_ov),
2273 .stop(stop)
2274 );
2275
2276
2277//assign oqarray_rd_en_r3_n = ~oqarray_rd_en_r3;
2278
2279l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__width_1 mux_oq_fail
2280 (
2281 .dout (oqarray_rw_fail_unreg),
2282 .din0 (oqarray_rw_fail_w),
2283 .din1 (1'b1),
2284 .sel0 (oqarray_rd_en_r2),
2285 .sel1 (oqarray_rd_en_r2_n)
2286 );
2287
2288
2289l2t_oque_dp_and_macro__width_1 and_mbist_oq_fail
2290 (
2291 .dout (oqarray_rw_fail_w),
2292 .din0 (oqarray_fail1),
2293 .din1 (oqarray_fail2)
2294 );
2295
2296
2297
2298//mux_macro mux_mbist_oqarray_dout (width=40,ports=4,mux=aonpe,stack=40r,dmux=8x)
2299// (
2300// .dout (for_mbist_oqarray_dout[39:0]),
2301// .din0 (oq_array_data_out[39:0]),
2302// .din1 (oq_array_data_out[79:40]),
2303// .din2 (oq_array_data_out[119:80]),
2304// .din3 ({14'b0,oq_array_data_out[145:120]}),
2305// .sel0 (mbist_oqarray_sel_r1[3]),
2306// .sel1 (mbist_oqarray_sel_r1[2]),
2307// .sel2 (mbist_oqarray_sel_r1[1]),
2308// .sel3 (mbist_oqarray_sel_r1[0])
2309// );
2310
2311l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_4__stack_40r__width_40 mux_mbist_oqarray_dout
2312 (
2313 .dout (for_mbist_oqarray_dout[39:0]),
2314 .din0 (oq_array_data_out[39:0]),
2315 .din1 (oq_array_data_out[79:40]),
2316 .din2 (oq_array_data_out[119:80]),
2317 .din3 (oq_array_data_out[159:120]),
2318 .sel0 (mbist_oqarray_sel_r1[3]),
2319 .sel1 (mbist_oqarray_sel_r1[2]),
2320 .sel2 (mbist_oqarray_sel_r1[1]),
2321 .sel3 (mbist_oqarray_sel_r1[0])
2322 );
2323
2324
2325
2326l2t_oque_dp_inv_macro__width_2 oqu_sel_array_out_l_inv_slice
2327 (
2328 .dout ({oqu_sel_array_out_l_n,oqarray_rd_en_r2_n}),
2329 .din ({oqu_sel_array_out_l,oqarray_rd_en_r2})
2330 );
2331
2332
2333l2t_oque_dp_and_macro__width_1 and_oq_array_data_out_sel
2334 (
2335 .dout (oq_array_data_out_sel),
2336 .din0 (oqu_sel_array_out_l_n),
2337 .din1 (oqu_out_mux1_sel_c7[1])
2338 );
2339
2340l2t_oque_dp_and_macro__width_1 and_staged_data_out_sel
2341 (
2342 .dout (staged_data_out_sel),
2343 .din0 (oqu_sel_array_out_l),
2344 .din1 (oqu_out_mux1_sel_c7[1])
2345 );
2346
2347
2348
2349
2350
2351//mux_macro mux_oqarray_dout_1 (width=36,ports=2,mux=aonpe,stack=36r,dmux=4x)
2352// ( .dout (eff_oqarray_dout[`CPX_WIDTH-1:110]), // effective array data after data
2353// // forwarding
2354// .din0 (oq_array_data_out[`CPX_WIDTH-1:110]), .sel0 (oqu_sel_array_out_l_n),
2355// .din1 (staged_data_out_c9[`CPX_WIDTH-1:110]), .sel1 (oqu_sel_array_out_l)
2356// ) ;
2357//
2358//mux_macro mux_oqarray_dout_2 (width=36,ports=2,mux=aonpe,stack=36r,dmux=4x)
2359// ( .dout (eff_oqarray_dout[109:74]), // effective array data after data
2360// // forwarding
2361// .din0 (oq_array_data_out[109:74]), .sel0 (oqu_sel_array_out_l_n),
2362// .din1 (staged_data_out_c9[109:74]), .sel1 (oqu_sel_array_out_l)
2363// ) ;
2364//
2365//mux_macro mux_oqarray_dout_3 (width=36,ports=2,mux=aonpe,stack=36r,dmux=4x)
2366// ( .dout (eff_oqarray_dout[73:38]), // effective array data after data
2367// // forwarding
2368// .din0 (oq_array_data_out[73:38]), .sel0 (oqu_sel_array_out_l_n),
2369// .din1 (staged_data_out_c9[73:38]), .sel1 (oqu_sel_array_out_l)
2370// ) ;
2371//
2372//mux_macro mux_oqarray_dout_4 (width=38,ports=2,mux=aonpe,stack=38r,dmux=4x)
2373// ( .dout (eff_oqarray_dout[37:0]), // effective array data after data
2374// // forwarding
2375// .din0 (oq_array_data_out[37:0]), .sel0 (oqu_sel_array_out_l_n),
2376// .din1 (staged_data_out_c9[37:0]), .sel1 (oqu_sel_array_out_l)
2377// ) ;
2378
2379
2380l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_36r__width_36 ff_tmp_cpx_data_ca1
2381 (.dout (tmp_cpx_data_ca[`CPX_WIDTH-1:110]),
2382 .din0 (oque_oq_array_data_in[`CPX_WIDTH-1:110]), .sel0 (oqu_out_mux1_sel_c7[2]), // def sel
2383 .din1 (oq_array_data_out[`CPX_WIDTH-1:110]), .sel1 (oq_array_data_out_sel), // oq data
2384 .din2 (staged_data_out_c9[`CPX_WIDTH-1:110]), .sel2 (staged_data_out_sel), // staged_data_out
2385 .din3 (oque_cpx_data_c8_buff[`CPX_WIDTH-1:110]),
2386 .muxtst(muxtst),
2387 .test(test) //.sel3 (oqu_out_mux1_sel_c7[0]) // staged packet sel
2388 ) ;
2389
2390l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_36r__width_36 ff_tmp_cpx_data_ca2
2391 (.dout (tmp_cpx_data_ca[109:74]),
2392 .din0 (oque_oq_array_data_in[109:74]), .sel0 (oqu_out_mux1_sel_c7[2]), // def sel
2393 .din1 (oq_array_data_out[109:74]), .sel1 (oq_array_data_out_sel), // oq data
2394 .din2 (staged_data_out_c9[109:74]), .sel2 (staged_data_out_sel), // staged_data_out
2395 .din3 (oque_cpx_data_c8_buff[109:74]),
2396 .muxtst(muxtst),
2397 .test(test) // .sel3 (oqu_out_mux1_sel_c7[0]) // staged packet sel
2398 ) ;
2399
2400l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_36r__width_36 ff_tmp_cpx_data_ca3
2401 (.dout (tmp_cpx_data_ca[73:38]),
2402 .din0 (oque_oq_array_data_in[73:38]), .sel0 (oqu_out_mux1_sel_c7[2]), // def sel
2403 .din1 (oq_array_data_out[73:38]), .sel1 (oq_array_data_out_sel), // oq data
2404 .din2 (staged_data_out_c9[73:38]), .sel2 (staged_data_out_sel), // staged_data_out
2405 .din3 (oque_cpx_data_c8_buff[73:38]),
2406 .muxtst(muxtst),
2407 .test(test) // .sel3 (oqu_out_mux1_sel_c7[0]) // staged packet sel
2408 ) ;
2409
2410l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_38r__width_38 ff_tmp_cpx_data_ca4
2411 (.dout (tmp_cpx_data_ca[37:0]),
2412 .din0 (oque_oq_array_data_in[37:0]), .sel0 (oqu_out_mux1_sel_c7[2]), // def sel //
2413 .din1 (oq_array_data_out[37:0]), .sel1 (oq_array_data_out_sel), // oq data
2414 .din2 (staged_data_out_c9[37:0]), .sel2 (staged_data_out_sel), // staged_data_out
2415 .din3 (oque_cpx_data_c8_buff[37:0]),
2416 .muxtst(muxtst),
2417 .test(test) // .sel3 (oqu_out_mux1_sel_c7[0]) // staged packet sel
2418 ) ;
2419
2420
2421
2422/////////////////////////////////////////////////////////////////
2423// Flop ff_tmp_cpx_data_ca
2424/////////////////////////////////////////////////////////////////
2425l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 ff_tmp_cpx_data_ca_1
2426 (.dout_l(tmp_cpx_data_ca_d1[`CPX_WIDTH-1:110]),
2427 .din(tmp_cpx_data_ca[`CPX_WIDTH-1:110]),
2428 .scan_in(ff_tmp_cpx_data_ca_1_scanin),
2429 .scan_out(ff_tmp_cpx_data_ca_1_scanout),
2430 .clk(l2clk),
2431 .en(1'b1),
2432 .se(se),
2433 .siclk(siclk),
2434 .soclk(soclk),
2435 .pce_ov(pce_ov),
2436 .stop(stop)
2437
2438 ) ;
2439
2440l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 ff_tmp_cpx_data_ca_2
2441 (.dout_l(tmp_cpx_data_ca_d1[109:74]),
2442 .din(tmp_cpx_data_ca[109:74]),
2443 .scan_in(ff_tmp_cpx_data_ca_2_scanin),
2444 .scan_out(ff_tmp_cpx_data_ca_2_scanout),
2445 .clk(l2clk),
2446 .en(1'b1),
2447 .se(se),
2448 .siclk(siclk),
2449 .soclk(soclk),
2450 .pce_ov(pce_ov),
2451 .stop(stop)
2452
2453 ) ;
2454l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 ff_tmp_cpx_data_ca_3
2455 (.dout_l(tmp_cpx_data_ca_d1[73:38]),
2456 .din(tmp_cpx_data_ca[73:38]),
2457 .scan_in(ff_tmp_cpx_data_ca_3_scanin),
2458 .scan_out(ff_tmp_cpx_data_ca_3_scanout),
2459 .clk(l2clk),
2460 .en(1'b1),
2461 .se(se),
2462 .siclk(siclk),
2463 .soclk(soclk),
2464 .pce_ov(pce_ov),
2465 .stop(stop)
2466
2467 ) ;
2468l2t_oque_dp_msffi_macro__dmsffi_16x__stack_38r__width_38 ff_tmp_cpx_data_ca_4
2469 (.dout_l(tmp_cpx_data_ca_d1[37:0]),
2470 .din(tmp_cpx_data_ca[37:0]),
2471 .scan_in(ff_tmp_cpx_data_ca_4_scanin),
2472 .scan_out(ff_tmp_cpx_data_ca_4_scanout),
2473 .clk(l2clk),
2474 .en(1'b1),
2475 .se(se),
2476 .siclk(siclk),
2477 .soclk(soclk),
2478 .pce_ov(pce_ov),
2479 .stop(stop)
2480 ) ;
2481
2482
2483
2484/////////////////////////////////////////////////////////
2485// flopping selects.
2486/////////////////////////////////////////////////////////
2487
2488l2t_oque_dp_msff_macro__dmsff_32x__stack_38r__width_38 ff_mux2_sel_c8_0 //
2489 (.dout(mux2_sel_c8_0_ff[37:0]),
2490 .scan_in(ff_mux2_sel_c8_0_scanin),
2491 .scan_out(ff_mux2_sel_c8_0_scanout),
2492 .din({38{oqu_out_mux2_sel_c7[0]}}),
2493 .clk(l2clk),
2494 .en(1'b1),
2495 .se(se),
2496 .siclk(siclk),
2497 .soclk(soclk),
2498 .pce_ov(pce_ov),
2499 .stop(stop)
2500 ) ;
2501
2502l2t_oque_dp_msff_macro__dmsff_32x__stack_38r__width_38 ff_mux2_sel_c8_1 //
2503 (.dout(mux2_sel_c8_1_ff[37:0]),
2504 .scan_in(ff_mux2_sel_c8_1_scanin),
2505 .scan_out(ff_mux2_sel_c8_1_scanout),
2506 .din({38{oqu_out_mux2_sel_c7[1]}}),
2507 .clk(l2clk),
2508 .en(1'b1),
2509 .se(se),
2510 .siclk(siclk),
2511 .soclk(soclk),
2512 .pce_ov(pce_ov),
2513 .stop(stop)
2514 ) ;
2515
2516l2t_oque_dp_msff_macro__dmsff_32x__stack_38r__width_38 ff_mux2_sel_c8_2 //
2517 (.dout(mux2_sel_c8_2_ff[37:0]),
2518 .scan_in(ff_mux2_sel_c8_2_scanin),
2519 .scan_out(ff_mux2_sel_c8_2_scanout),
2520 .din({38{oqu_out_mux2_sel_c7[2]}}),
2521 .clk(l2clk),
2522 .en(1'b1),
2523 .se(se),
2524 .siclk(siclk),
2525 .soclk(soclk),
2526 .pce_ov(pce_ov),
2527 .stop(stop)
2528 ) ;
2529
2530
2531// -----------------------------------------------------------------------------------
2532
2533// assign mux2_sel_c8[0] = out_mux2_sel_c8[0] ;
2534// assign mux2_sel_c8[1] = out_mux2_sel_c8[1] ;
2535// assign mux2_sel_c8[2] = out_mux2_sel_c8[2] ;
2536
2537// -----------------------------------------------------------------------------------
2538//-------------------------------------------------------------------------------------
2539///////////////////////////////////////////////////////////////////////////////////////////////
2540// First Row of muxes.
2541///////////////////////////////////////////////////////////////////////////////////////////////
2542
2543//--- 113:110 -------//
2544cl_dp1_aomux3_8x ff_cpx_data_ca_1_110
2545 (.out (oque_cpx_data_c8_muxout[110]),
2546 .in0 (tmp_cpx_data_ca_d1[110]),
2547 .sel0 (mux2_sel_c8_0_ff[0]), // Old data sel
2548 .in1 (ext_inval_data_c8[110]),
2549 .sel1 (mux2_sel_c8_1_ff[0]), // Inval
2550 .in2 (ext_ret_data_c8[110]),
2551 .sel2 (mux2_sel_c8_2_ff[0]) // Def Sel
2552 ) ;
2553
2554cl_dp1_aomux3_8x ff_cpx_data_ca_1_111
2555 (.out (oque_cpx_data_c8_muxout[111]),
2556 .in0 (tmp_cpx_data_ca_d1[111]),
2557 .sel0 (mux2_sel_c8_0_ff[1]), // Old data sel
2558 .in1 (ext_inval_data_c8[111]),
2559 .sel1 (mux2_sel_c8_1_ff[1]), // Inval
2560 .in2 (ext_ret_data_c8[111]),
2561 .sel2 (mux2_sel_c8_2_ff[1]) // Def Sel
2562 ) ;
2563
2564cl_dp1_aomux3_8x ff_cpx_data_ca_1_112
2565 (.out (oque_cpx_data_c8_muxout[112]),
2566 .in0 (tmp_cpx_data_ca_d1[112]),
2567 .sel0 (mux2_sel_c8_0_ff[2]), // Old data sel
2568 .in1 (ext_inval_data_c8[112]),
2569 .sel1 (mux2_sel_c8_1_ff[2]), // Inval
2570 .in2 (ext_ret_data_c8[112]),
2571 .sel2 (mux2_sel_c8_2_ff[2]) // Def Sel
2572 ) ;
2573
2574cl_dp1_aomux3_8x ff_cpx_data_ca_1_113
2575 (.out (oque_cpx_data_c8_muxout[113]),
2576 .in0 (tmp_cpx_data_ca_d1[113]),
2577 .sel0 (mux2_sel_c8_0_ff[3]), // Old data sel
2578 .in1 (ext_inval_data_c8[113]),
2579 .sel1 (mux2_sel_c8_1_ff[3]), // Inval
2580 .in2 (ext_ret_data_c8[113]),
2581 .sel2 (mux2_sel_c8_2_ff[3]) // Def Sel
2582 ) ;
2583//--- 117:114 -------//
2584cl_dp1_aomux3_8x ff_cpx_data_ca_1_114
2585 (.out (oque_cpx_data_c8_muxout[114]),
2586 .in0 (tmp_cpx_data_ca_d1[114]),
2587 .sel0 (mux2_sel_c8_0_ff[4]), // Old data sel
2588 .in1 (ext_inval_data_c8[114]),
2589 .sel1 (mux2_sel_c8_1_ff[4]), // Inval
2590 .in2 (ext_ret_data_c8[114]),
2591 .sel2 (mux2_sel_c8_2_ff[4]) // Def Sel
2592 ) ;
2593
2594cl_dp1_aomux3_8x ff_cpx_data_ca_1_115
2595 (.out (oque_cpx_data_c8_muxout[115]),
2596 .in0 (tmp_cpx_data_ca_d1[115]),
2597 .sel0 (mux2_sel_c8_0_ff[5]), // Old data sel
2598 .in1 (ext_inval_data_c8[115]),
2599 .sel1 (mux2_sel_c8_1_ff[5]), // Inval
2600 .in2 (ext_ret_data_c8[115]),
2601 .sel2 (mux2_sel_c8_2_ff[5]) // Def Sel
2602 ) ;
2603
2604cl_dp1_aomux3_8x ff_cpx_data_ca_1_116
2605 (.out (oque_cpx_data_c8_muxout[116]),
2606 .in0 (tmp_cpx_data_ca_d1[116]),
2607 .sel0 (mux2_sel_c8_0_ff[6]), // Old data sel
2608 .in1 (ext_inval_data_c8[116]),
2609 .sel1 (mux2_sel_c8_1_ff[6]), // Inval
2610 .in2 (ext_ret_data_c8[116]),
2611 .sel2 (mux2_sel_c8_2_ff[6]) // Def Sel
2612 ) ;
2613
2614cl_dp1_aomux3_8x ff_cpx_data_ca_1_117
2615 (.out (oque_cpx_data_c8_muxout[117]),
2616 .in0 (tmp_cpx_data_ca_d1[117]),
2617 .sel0 (mux2_sel_c8_0_ff[7]), // Old data sel
2618 .in1 (ext_inval_data_c8[117]),
2619 .sel1 (mux2_sel_c8_1_ff[7]), // Inval
2620 .in2 (ext_ret_data_c8[117]),
2621 .sel2 (mux2_sel_c8_2_ff[7]) // Def Sel
2622 ) ;
2623
2624//--- 121:118 -------//
2625cl_dp1_aomux3_8x ff_cpx_data_ca_1_118
2626 (.out (oque_cpx_data_c8_muxout[118]),
2627 .in0 (tmp_cpx_data_ca_d1[118]),
2628 .sel0 (mux2_sel_c8_0_ff[8]), // Old data sel
2629 .in1 (ext_inval_data_c8[118]),
2630 .sel1 (mux2_sel_c8_1_ff[8]), // Inval
2631 .in2 (ext_ret_data_c8[118]),
2632 .sel2 (mux2_sel_c8_2_ff[8]) // Def Sel
2633 ) ;
2634
2635cl_dp1_aomux3_8x ff_cpx_data_ca_1_119
2636 (.out (oque_cpx_data_c8_muxout[119]),
2637 .in0 (tmp_cpx_data_ca_d1[119]),
2638 .sel0 (mux2_sel_c8_0_ff[9]), // Old data sel
2639 .in1 (ext_inval_data_c8[119]),
2640 .sel1 (mux2_sel_c8_1_ff[9]), // Inval
2641 .in2 (ext_ret_data_c8[119]),
2642 .sel2 (mux2_sel_c8_2_ff[9]) // Def Sel
2643 ) ;
2644
2645cl_dp1_aomux3_8x ff_cpx_data_ca_1_120
2646 (.out (oque_cpx_data_c8_muxout[120]),
2647 .in0 (tmp_cpx_data_ca_d1[120]),
2648 .sel0 (mux2_sel_c8_0_ff[10]), // Old data sel
2649 .in1 (ext_inval_data_c8[120]),
2650 .sel1 (mux2_sel_c8_1_ff[10]), // Inval
2651 .in2 (ext_ret_data_c8[120]),
2652 .sel2 (mux2_sel_c8_2_ff[10]) // Def Sel
2653 ) ;
2654
2655cl_dp1_aomux3_8x ff_cpx_data_ca_1_121
2656 (.out (oque_cpx_data_c8_muxout[121]),
2657 .in0 (tmp_cpx_data_ca_d1[121]),
2658 .sel0 (mux2_sel_c8_0_ff[11]), // Old data sel
2659 .in1 (ext_inval_data_c8[121]),
2660 .sel1 (mux2_sel_c8_1_ff[11]), // Inval
2661 .in2 (ext_ret_data_c8[121]),
2662 .sel2 (mux2_sel_c8_2_ff[11]) // Def Sel
2663 ) ;
2664
2665//--- 125:122 -------//
2666cl_dp1_aomux3_8x ff_cpx_data_ca_1_122
2667 (.out (oque_cpx_data_c8_muxout[122]),
2668 .in0 (tmp_cpx_data_ca_d1[122]),
2669 .sel0 (mux2_sel_c8_0_ff[12]), // Old data sel
2670 .in1 (ext_inval_data_c8[122]),
2671 .sel1 (mux2_sel_c8_1_ff[12]), // Inval
2672 .in2 (ext_ret_data_c8[122]),
2673 .sel2 (mux2_sel_c8_2_ff[12]) // Def Sel
2674 ) ;
2675
2676cl_dp1_aomux3_8x ff_cpx_data_ca_1_123
2677 (.out (oque_cpx_data_c8_muxout[123]),
2678 .in0 (tmp_cpx_data_ca_d1[123]),
2679 .sel0 (mux2_sel_c8_0_ff[13]), // Old data sel
2680 .in1 (ext_inval_data_c8[123]),
2681 .sel1 (mux2_sel_c8_1_ff[13]), // Inval
2682 .in2 (ext_ret_data_c8[123]),
2683 .sel2 (mux2_sel_c8_2_ff[13]) // Def Sel
2684 ) ;
2685
2686cl_dp1_aomux3_8x ff_cpx_data_ca_1_124
2687 (.out (oque_cpx_data_c8_muxout[124]),
2688 .in0 (tmp_cpx_data_ca_d1[124]),
2689 .sel0 (mux2_sel_c8_0_ff[14]), // Old data sel
2690 .in1 (ext_inval_data_c8[124]),
2691 .sel1 (mux2_sel_c8_1_ff[14]), // Inval
2692 .in2 (ext_ret_data_c8[124]),
2693 .sel2 (mux2_sel_c8_2_ff[14]) // Def Sel
2694 ) ;
2695
2696cl_dp1_aomux3_8x ff_cpx_data_ca_1_125
2697 (.out (oque_cpx_data_c8_muxout[125]),
2698 .in0 (tmp_cpx_data_ca_d1[125]),
2699 .sel0 (mux2_sel_c8_0_ff[15]), // Old data sel
2700 .in1 (ext_inval_data_c8[125]),
2701 .sel1 (mux2_sel_c8_1_ff[15]), // Inval
2702 .in2 (ext_ret_data_c8[125]),
2703 .sel2 (mux2_sel_c8_2_ff[15]) // Def Sel
2704 ) ;
2705
2706//--- 129:126 -------//
2707cl_dp1_aomux3_8x ff_cpx_data_ca_1_126
2708 (.out (oque_cpx_data_c8_muxout[126]),
2709 .in0 (tmp_cpx_data_ca_d1[126]),
2710 .sel0 (mux2_sel_c8_0_ff[16]), // Old data sel
2711 .in1 (ext_inval_data_c8[126]),
2712 .sel1 (mux2_sel_c8_1_ff[16]), // Inval
2713 .in2 (ext_ret_data_c8[126]),
2714 .sel2 (mux2_sel_c8_2_ff[16]) // Def Sel
2715 ) ;
2716
2717cl_dp1_aomux3_8x ff_cpx_data_ca_1_127
2718 (.out (oque_cpx_data_c8_muxout[127]),
2719 .in0 (tmp_cpx_data_ca_d1[127]),
2720 .sel0 (mux2_sel_c8_0_ff[17]), // Old data sel
2721 .in1 (ext_inval_data_c8[127]),
2722 .sel1 (mux2_sel_c8_1_ff[17]), // Inval
2723 .in2 (ext_ret_data_c8[127]),
2724 .sel2 (mux2_sel_c8_2_ff[17]) // Def Sel
2725 ) ;
2726
2727cl_dp1_aomux3_8x ff_cpx_data_ca_1_128
2728 (.out (oque_cpx_data_c8_muxout[128]),
2729 .in0 (tmp_cpx_data_ca_d1[128]),
2730 .sel0 (mux2_sel_c8_0_ff[18]), // Old data sel
2731 .in1 (ext_inval_data_c8[128]),
2732 .sel1 (mux2_sel_c8_1_ff[18]), // Inval
2733 .in2 (ext_ret_data_c8[128]),
2734 .sel2 (mux2_sel_c8_2_ff[18]) // Def Sel
2735 ) ;
2736
2737cl_dp1_aomux3_8x ff_cpx_data_ca_1_129
2738 (.out (oque_cpx_data_c8_muxout[129]),
2739 .in0 (tmp_cpx_data_ca_d1[129]),
2740 .sel0 (mux2_sel_c8_0_ff[19]), // Old data sel
2741 .in1 (ext_inval_data_c8[129]),
2742 .sel1 (mux2_sel_c8_1_ff[19]), // Inval
2743 .in2 (ext_ret_data_c8[129]),
2744 .sel2 (mux2_sel_c8_2_ff[19]) // Def Sel
2745 ) ;
2746
2747//--- 133:130 -------//
2748cl_dp1_aomux3_8x ff_cpx_data_ca_1_130
2749 (.out (oque_cpx_data_c8_muxout[130]),
2750 .in0 (tmp_cpx_data_ca_d1[130]),
2751 .sel0 (mux2_sel_c8_0_ff[20]), // Old data sel
2752 .in1 (ext_inval_data_c8[130]),
2753 .sel1 (mux2_sel_c8_1_ff[20]), // Inval
2754 .in2 (ext_ret_data_c8[130]),
2755 .sel2 (mux2_sel_c8_2_ff[20]) // Def Sel
2756 ) ;
2757
2758cl_dp1_aomux3_8x ff_cpx_data_ca_1_131
2759 (.out (oque_cpx_data_c8_muxout[131]),
2760 .in0 (tmp_cpx_data_ca_d1[131]),
2761 .sel0 (mux2_sel_c8_0_ff[21]), // Old data sel
2762 .in1 (ext_inval_data_c8[131]),
2763 .sel1 (mux2_sel_c8_1_ff[21]), // Inval
2764 .in2 (ext_ret_data_c8[131]),
2765 .sel2 (mux2_sel_c8_2_ff[21]) // Def Sel
2766 ) ;
2767
2768cl_dp1_aomux3_8x ff_cpx_data_ca_1_132
2769 (.out (oque_cpx_data_c8_muxout[132]),
2770 .in0 (tmp_cpx_data_ca_d1[132]),
2771 .sel0 (mux2_sel_c8_0_ff[22]), // Old data sel
2772 .in1 (ext_inval_data_c8[132]),
2773 .sel1 (mux2_sel_c8_1_ff[22]), // Inval
2774 .in2 (ext_ret_data_c8[132]),
2775 .sel2 (mux2_sel_c8_2_ff[22]) // Def Sel
2776 ) ;
2777
2778cl_dp1_aomux3_8x ff_cpx_data_ca_1_133
2779 (.out (oque_cpx_data_c8_muxout[133]),
2780 .in0 (tmp_cpx_data_ca_d1[133]),
2781 .sel0 (mux2_sel_c8_0_ff[23]), // Old data sel
2782 .in1 (ext_inval_data_c8[133]),
2783 .sel1 (mux2_sel_c8_1_ff[23]), // Inval
2784 .in2 (ext_ret_data_c8[133]),
2785 .sel2 (mux2_sel_c8_2_ff[23]) // Def Sel
2786 ) ;
2787
2788//--- 137:134 -------//
2789cl_dp1_aomux3_8x ff_cpx_data_ca_1_134
2790 (.out (oque_cpx_data_c8_muxout[134]),
2791 .in0 (tmp_cpx_data_ca_d1[134]),
2792 .sel0 (mux2_sel_c8_0_ff[24]), // Old data sel
2793 .in1 (oque_oq_array_data_in_inv[134]),
2794 .sel1 (mux2_sel_c8_1_ff[24]), // Inval
2795 .in2 (oque_oq_array_data_in_inv[134]),
2796 .sel2 (mux2_sel_c8_2_ff[24]) // Def Sel
2797 ) ;
2798
2799cl_dp1_aomux3_8x ff_cpx_data_ca_1_135
2800 (.out (oque_cpx_data_c8_muxout[135]),
2801 .in0 (tmp_cpx_data_ca_d1[135]),
2802 .sel0 (mux2_sel_c8_0_ff[25]), // Old data sel
2803 .in1 (oque_oq_array_data_in_inv[135]),
2804 .sel1 (mux2_sel_c8_1_ff[25]), // Inval
2805 .in2 (oque_oq_array_data_in_inv[135]),
2806 .sel2 (mux2_sel_c8_2_ff[25]) // Def Sel
2807 ) ;
2808
2809cl_dp1_aomux3_8x ff_cpx_data_ca_1_136
2810 (.out (oque_cpx_data_c8_muxout[136]),
2811 .in0 (tmp_cpx_data_ca_d1[136]),
2812 .sel0 (mux2_sel_c8_0_ff[26]), // Old data sel
2813 .in1 (oque_oq_array_data_in_inv[136]),
2814 .sel1 (mux2_sel_c8_1_ff[26]), // Inval
2815 .in2 (oque_oq_array_data_in_inv[136]),
2816 .sel2 (mux2_sel_c8_2_ff[26]) // Def Sel
2817 ) ;
2818
2819cl_dp1_aomux3_8x ff_cpx_data_ca_1_137
2820 (.out (oque_cpx_data_c8_muxout[137]),
2821 .in0 (tmp_cpx_data_ca_d1[137]),
2822 .sel0 (mux2_sel_c8_0_ff[27]), // Old data sel
2823 .in1 (oque_oq_array_data_in_inv[137]),
2824 .sel1 (mux2_sel_c8_1_ff[27]), // Inval
2825 .in2 (oque_oq_array_data_in_inv[137]),
2826 .sel2 (mux2_sel_c8_2_ff[27]) // Def Sel
2827 ) ;
2828
2829//--- 141:138 -------//
2830cl_dp1_aomux3_8x ff_cpx_data_ca_1_138
2831 (.out (oque_cpx_data_c8_muxout[138]),
2832 .in0 (tmp_cpx_data_ca_d1[138]),
2833 .sel0 (mux2_sel_c8_0_ff[28]), // Old data sel
2834 .in1 (oque_oq_array_data_in_inv[138]),
2835 .sel1 (mux2_sel_c8_1_ff[28]), // Inval
2836 .in2 (oque_oq_array_data_in_inv[138]),
2837 .sel2 (mux2_sel_c8_2_ff[28]) // Def Sel
2838 ) ;
2839
2840cl_dp1_aomux3_8x ff_cpx_data_ca_1_139
2841 (.out (oque_cpx_data_c8_muxout[139]),
2842 .in0 (tmp_cpx_data_ca_d1[139]),
2843 .sel0 (mux2_sel_c8_0_ff[29]), // Old data sel
2844 .in1 (oque_oq_array_data_in_inv[139]),
2845 .sel1 (mux2_sel_c8_1_ff[29]), // Inval
2846 .in2 (oque_oq_array_data_in_inv[139]),
2847 .sel2 (mux2_sel_c8_2_ff[29]) // Def Sel
2848 ) ;
2849
2850cl_dp1_aomux3_8x ff_cpx_data_ca_1_140
2851 (.out (oque_cpx_data_c8_muxout[140]),
2852 .in0 (tmp_cpx_data_ca_d1[140]),
2853 .sel0 (mux2_sel_c8_0_ff[30]), // Old data sel
2854 .in1 (oque_oq_array_data_in_inv[140]),
2855 .sel1 (mux2_sel_c8_1_ff[30]), // Inval
2856 .in2 (oque_oq_array_data_in_inv[140]),
2857 .sel2 (mux2_sel_c8_2_ff[30]) // Def Sel
2858 ) ;
2859
2860cl_dp1_aomux3_8x ff_cpx_data_ca_1_141
2861 (.out (oque_cpx_data_c8_muxout[141]),
2862 .in0 (tmp_cpx_data_ca_d1[141]),
2863 .sel0 (mux2_sel_c8_0_ff[31]), // Old data sel
2864 .in1 (oque_oq_array_data_in_inv[141]),
2865 .sel1 (mux2_sel_c8_1_ff[31]), // Inval
2866 .in2 (oque_oq_array_data_in_inv[141]),
2867 .sel2 (mux2_sel_c8_2_ff[31]) // Def Sel
2868 ) ;
2869
2870//--- 145:142 -------//
2871cl_dp1_aomux3_8x ff_cpx_data_ca_1_142
2872 (.out (oque_cpx_data_c8_muxout[142]),
2873 .in0 (tmp_cpx_data_ca_d1[142]),
2874 .sel0 (mux2_sel_c8_0_ff[32]), // Old data sel
2875 .in1 (oque_oq_array_data_in_inv[142]),
2876 .sel1 (mux2_sel_c8_1_ff[32]), // Inval
2877 .in2 (oque_oq_array_data_in_inv[142]),
2878 .sel2 (mux2_sel_c8_2_ff[32]) // Def Sel
2879 ) ;
2880
2881cl_dp1_aomux3_8x ff_cpx_data_ca_1_143
2882 (.out (oque_cpx_data_c8_muxout[143]),
2883 .in0 (tmp_cpx_data_ca_d1[143]),
2884 .sel0 (mux2_sel_c8_0_ff[33]), // Old data sel
2885 .in1 (oque_oq_array_data_in_inv[143]),
2886 .sel1 (mux2_sel_c8_1_ff[33]), // Inval
2887 .in2 (oque_oq_array_data_in_inv[143]),
2888 .sel2 (mux2_sel_c8_2_ff[33]) // Def Sel
2889 ) ;
2890
2891cl_dp1_aomux3_8x ff_cpx_data_ca_1_144
2892 (.out (oque_cpx_data_c8_muxout[144]),
2893 .in0 (tmp_cpx_data_ca_d1[144]),
2894 .sel0 (mux2_sel_c8_0_ff[34]), // Old data sel
2895 .in1 (oque_oq_array_data_in_inv[144]),
2896 .sel1 (mux2_sel_c8_1_ff[34]), // Inval
2897 .in2 (oque_oq_array_data_in_inv[144]),
2898 .sel2 (mux2_sel_c8_2_ff[34]) // Def Sel
2899 ) ;
2900
2901cl_dp1_aomux3_8x ff_cpx_data_ca_1_145
2902 (.out (oque_cpx_data_c8_muxout[145]),
2903 .in0 (tmp_cpx_data_ca_d1[145]),
2904 .sel0 (mux2_sel_c8_0_ff[35]), // Old data sel
2905 .in1 (oque_oq_array_data_in_inv[145]),
2906 .sel1 (mux2_sel_c8_1_ff[35]), // Inval
2907 .in2 (oque_oq_array_data_in_inv[145]),
2908 .sel2 (mux2_sel_c8_2_ff[35]) // Def Sel
2909 ) ;
2910
2911assign oque_oq_array_data_in_inv[145] = 1'b0 ;
2912///////////////////////////////////////////////////////////////////////////////////////////////
2913// Second Row of muxes.
2914///////////////////////////////////////////////////////////////////////////////////////////////
2915
2916//--- 77:74 -------//
2917cl_dp1_aomux3_8x ff_cpx_data_ca_1_74
2918 (.out (oque_cpx_data_c8_muxout[74]),
2919 .in0 (tmp_cpx_data_ca_d1[74]),
2920 .sel0 (mux2_sel_c8_0_ff[0]), // Old data sel
2921 .in1 (ext_inval_data_c8[74]),
2922 .sel1 (mux2_sel_c8_1_ff[0]), // Inval
2923 .in2 (ext_ret_data_c8[74]),
2924 .sel2 (mux2_sel_c8_2_ff[0]) // Def Sel
2925 ) ;
2926
2927cl_dp1_aomux3_8x ff_cpx_data_ca_1_75
2928 (.out (oque_cpx_data_c8_muxout[75]),
2929 .in0 (tmp_cpx_data_ca_d1[75]),
2930 .sel0 (mux2_sel_c8_0_ff[1]), // Old data sel
2931 .in1 (ext_inval_data_c8[75]),
2932 .sel1 (mux2_sel_c8_1_ff[1]), // Inval
2933 .in2 (ext_ret_data_c8[75]),
2934 .sel2 (mux2_sel_c8_2_ff[1]) // Def Sel
2935 ) ;
2936
2937cl_dp1_aomux3_8x ff_cpx_data_ca_1_76
2938 (.out (oque_cpx_data_c8_muxout[76]),
2939 .in0 (tmp_cpx_data_ca_d1[76]),
2940 .sel0 (mux2_sel_c8_0_ff[2]), // Old data sel
2941 .in1 (ext_inval_data_c8[76]),
2942 .sel1 (mux2_sel_c8_1_ff[2]), // Inval
2943 .in2 (ext_ret_data_c8[76]),
2944 .sel2 (mux2_sel_c8_2_ff[2]) // Def Sel
2945 ) ;
2946
2947cl_dp1_aomux3_8x ff_cpx_data_ca_1_77
2948 (.out (oque_cpx_data_c8_muxout[77]),
2949 .in0 (tmp_cpx_data_ca_d1[77]),
2950 .sel0 (mux2_sel_c8_0_ff[3]), // Old data sel
2951 .in1 (ext_inval_data_c8[77]),
2952 .sel1 (mux2_sel_c8_1_ff[3]), // Inval
2953 .in2 (ext_ret_data_c8[77]),
2954 .sel2 (mux2_sel_c8_2_ff[3]) // Def Sel
2955 ) ;
2956//--- 81:78 -------//
2957cl_dp1_aomux3_8x ff_cpx_data_ca_1_78
2958 (.out (oque_cpx_data_c8_muxout[78]),
2959 .in0 (tmp_cpx_data_ca_d1[78]),
2960 .sel0 (mux2_sel_c8_0_ff[4]), // Old data sel
2961 .in1 (ext_inval_data_c8[78]),
2962 .sel1 (mux2_sel_c8_1_ff[4]), // Inval
2963 .in2 (ext_ret_data_c8[78]),
2964 .sel2 (mux2_sel_c8_2_ff[4]) // Def Sel
2965 ) ;
2966
2967cl_dp1_aomux3_8x ff_cpx_data_ca_1_79
2968 (.out (oque_cpx_data_c8_muxout[79]),
2969 .in0 (tmp_cpx_data_ca_d1[79]),
2970 .sel0 (mux2_sel_c8_0_ff[5]), // Old data sel
2971 .in1 (ext_inval_data_c8[79]),
2972 .sel1 (mux2_sel_c8_1_ff[5]), // Inval
2973 .in2 (ext_ret_data_c8[79]),
2974 .sel2 (mux2_sel_c8_2_ff[5]) // Def Sel
2975 ) ;
2976
2977cl_dp1_aomux3_8x ff_cpx_data_ca_1_80
2978 (.out (oque_cpx_data_c8_muxout[80]),
2979 .in0 (tmp_cpx_data_ca_d1[80]),
2980 .sel0 (mux2_sel_c8_0_ff[6]), // Old data sel
2981 .in1 (ext_inval_data_c8[80]),
2982 .sel1 (mux2_sel_c8_1_ff[6]), // Inval
2983 .in2 (ext_ret_data_c8[80]),
2984 .sel2 (mux2_sel_c8_2_ff[6]) // Def Sel
2985 ) ;
2986
2987cl_dp1_aomux3_8x ff_cpx_data_ca_1_81
2988 (.out (oque_cpx_data_c8_muxout[81]),
2989 .in0 (tmp_cpx_data_ca_d1[81]),
2990 .sel0 (mux2_sel_c8_0_ff[7]), // Old data sel
2991 .in1 (ext_inval_data_c8[81]),
2992 .sel1 (mux2_sel_c8_1_ff[7]), // Inval
2993 .in2 (ext_ret_data_c8[81]),
2994 .sel2 (mux2_sel_c8_2_ff[7]) // Def Sel
2995 ) ;
2996
2997//--- 85:82 -------//
2998cl_dp1_aomux3_8x ff_cpx_data_ca_1_82
2999 (.out (oque_cpx_data_c8_muxout[82]),
3000 .in0 (tmp_cpx_data_ca_d1[82]),
3001 .sel0 (mux2_sel_c8_0_ff[8]), // Old data sel
3002 .in1 (ext_inval_data_c8[82]),
3003 .sel1 (mux2_sel_c8_1_ff[8]), // Inval
3004 .in2 (ext_ret_data_c8[82]),
3005 .sel2 (mux2_sel_c8_2_ff[8]) // Def Sel
3006 ) ;
3007
3008cl_dp1_aomux3_8x ff_cpx_data_ca_1_83
3009 (.out (oque_cpx_data_c8_muxout[83]),
3010 .in0 (tmp_cpx_data_ca_d1[83]),
3011 .sel0 (mux2_sel_c8_0_ff[9]), // Old data sel
3012 .in1 (ext_inval_data_c8[83]),
3013 .sel1 (mux2_sel_c8_1_ff[9]), // Inval
3014 .in2 (ext_ret_data_c8[83]),
3015 .sel2 (mux2_sel_c8_2_ff[9]) // Def Sel
3016 ) ;
3017
3018cl_dp1_aomux3_8x ff_cpx_data_ca_1_84
3019 (.out (oque_cpx_data_c8_muxout[84]),
3020 .in0 (tmp_cpx_data_ca_d1[84]),
3021 .sel0 (mux2_sel_c8_0_ff[10]), // Old data sel
3022 .in1 (ext_inval_data_c8[84]),
3023 .sel1 (mux2_sel_c8_1_ff[10]), // Inval
3024 .in2 (ext_ret_data_c8[84]),
3025 .sel2 (mux2_sel_c8_2_ff[10]) // Def Sel
3026 ) ;
3027
3028cl_dp1_aomux3_8x ff_cpx_data_ca_1_85
3029 (.out (oque_cpx_data_c8_muxout[85]),
3030 .in0 (tmp_cpx_data_ca_d1[85]),
3031 .sel0 (mux2_sel_c8_0_ff[11]), // Old data sel
3032 .in1 (ext_inval_data_c8[85]),
3033 .sel1 (mux2_sel_c8_1_ff[11]), // Inval
3034 .in2 (ext_ret_data_c8[85]),
3035 .sel2 (mux2_sel_c8_2_ff[11]) // Def Sel
3036 ) ;
3037
3038//--- 89:86 -------//
3039cl_dp1_aomux3_8x ff_cpx_data_ca_1_86
3040 (.out (oque_cpx_data_c8_muxout[86]),
3041 .in0 (tmp_cpx_data_ca_d1[86]),
3042 .sel0 (mux2_sel_c8_0_ff[12]), // Old data sel
3043 .in1 (ext_inval_data_c8[86]),
3044 .sel1 (mux2_sel_c8_1_ff[12]), // Inval
3045 .in2 (ext_ret_data_c8[86]),
3046 .sel2 (mux2_sel_c8_2_ff[12]) // Def Sel
3047 ) ;
3048
3049cl_dp1_aomux3_8x ff_cpx_data_ca_1_87
3050 (.out (oque_cpx_data_c8_muxout[87]),
3051 .in0 (tmp_cpx_data_ca_d1[87]),
3052 .sel0 (mux2_sel_c8_0_ff[13]), // Old data sel
3053 .in1 (ext_inval_data_c8[87]),
3054 .sel1 (mux2_sel_c8_1_ff[13]), // Inval
3055 .in2 (ext_ret_data_c8[87]),
3056 .sel2 (mux2_sel_c8_2_ff[13]) // Def Sel
3057 ) ;
3058
3059cl_dp1_aomux3_8x ff_cpx_data_ca_1_88
3060 (.out (oque_cpx_data_c8_muxout[88]),
3061 .in0 (tmp_cpx_data_ca_d1[88]),
3062 .sel0 (mux2_sel_c8_0_ff[14]), // Old data sel
3063 .in1 (ext_inval_data_c8[88]),
3064 .sel1 (mux2_sel_c8_1_ff[14]), // Inval
3065 .in2 (ext_ret_data_c8[88]),
3066 .sel2 (mux2_sel_c8_2_ff[14]) // Def Sel
3067 ) ;
3068
3069cl_dp1_aomux3_8x ff_cpx_data_ca_1_89
3070 (.out (oque_cpx_data_c8_muxout[89]),
3071 .in0 (tmp_cpx_data_ca_d1[89]),
3072 .sel0 (mux2_sel_c8_0_ff[15]), // Old data sel
3073 .in1 (ext_inval_data_c8[89]),
3074 .sel1 (mux2_sel_c8_1_ff[15]), // Inval
3075 .in2 (ext_ret_data_c8[89]),
3076 .sel2 (mux2_sel_c8_2_ff[15]) // Def Sel
3077 ) ;
3078
3079//--- 93:90 -------//
3080cl_dp1_aomux3_8x ff_cpx_data_ca_1_90
3081 (.out (oque_cpx_data_c8_muxout[90]),
3082 .in0 (tmp_cpx_data_ca_d1[90]),
3083 .sel0 (mux2_sel_c8_0_ff[16]), // Old data sel
3084 .in1 (ext_inval_data_c8[90]),
3085 .sel1 (mux2_sel_c8_1_ff[16]), // Inval
3086 .in2 (ext_ret_data_c8[90]),
3087 .sel2 (mux2_sel_c8_2_ff[16]) // Def Sel
3088 ) ;
3089
3090cl_dp1_aomux3_8x ff_cpx_data_ca_1_91
3091 (.out (oque_cpx_data_c8_muxout[91]),
3092 .in0 (tmp_cpx_data_ca_d1[91]),
3093 .sel0 (mux2_sel_c8_0_ff[17]), // Old data sel
3094 .in1 (ext_inval_data_c8[91]),
3095 .sel1 (mux2_sel_c8_1_ff[17]), // Inval
3096 .in2 (ext_ret_data_c8[91]),
3097 .sel2 (mux2_sel_c8_2_ff[17]) // Def Sel
3098 ) ;
3099
3100cl_dp1_aomux3_8x ff_cpx_data_ca_1_92
3101 (.out (oque_cpx_data_c8_muxout[92]),
3102 .in0 (tmp_cpx_data_ca_d1[92]),
3103 .sel0 (mux2_sel_c8_0_ff[18]), // Old data sel
3104 .in1 (ext_inval_data_c8[92]),
3105 .sel1 (mux2_sel_c8_1_ff[18]), // Inval
3106 .in2 (ext_ret_data_c8[92]),
3107 .sel2 (mux2_sel_c8_2_ff[18]) // Def Sel
3108 ) ;
3109
3110cl_dp1_aomux3_8x ff_cpx_data_ca_1_93
3111 (.out (oque_cpx_data_c8_muxout[93]),
3112 .in0 (tmp_cpx_data_ca_d1[93]),
3113 .sel0 (mux2_sel_c8_0_ff[19]), // Old data sel
3114 .in1 (ext_inval_data_c8[93]),
3115 .sel1 (mux2_sel_c8_1_ff[19]), // Inval
3116 .in2 (ext_ret_data_c8[93]),
3117 .sel2 (mux2_sel_c8_2_ff[19]) // Def Sel
3118 ) ;
3119
3120//--- 97:94 -------//
3121cl_dp1_aomux3_8x ff_cpx_data_ca_1_94
3122 (.out (oque_cpx_data_c8_muxout[94]),
3123 .in0 (tmp_cpx_data_ca_d1[94]),
3124 .sel0 (mux2_sel_c8_0_ff[20]), // Old data sel
3125 .in1 (ext_inval_data_c8[94]),
3126 .sel1 (mux2_sel_c8_1_ff[20]), // Inval
3127 .in2 (ext_ret_data_c8[94]),
3128 .sel2 (mux2_sel_c8_2_ff[20]) // Def Sel
3129 ) ;
3130
3131cl_dp1_aomux3_8x ff_cpx_data_ca_1_95
3132 (.out (oque_cpx_data_c8_muxout[95]),
3133 .in0 (tmp_cpx_data_ca_d1[95]),
3134 .sel0 (mux2_sel_c8_0_ff[21]), // Old data sel
3135 .in1 (ext_inval_data_c8[95]),
3136 .sel1 (mux2_sel_c8_1_ff[21]), // Inval
3137 .in2 (ext_ret_data_c8[95]),
3138 .sel2 (mux2_sel_c8_2_ff[21]) // Def Sel
3139 ) ;
3140
3141cl_dp1_aomux3_8x ff_cpx_data_ca_1_96
3142 (.out (oque_cpx_data_c8_muxout[96]),
3143 .in0 (tmp_cpx_data_ca_d1[96]),
3144 .sel0 (mux2_sel_c8_0_ff[22]), // Old data sel
3145 .in1 (ext_inval_data_c8[96]),
3146 .sel1 (mux2_sel_c8_1_ff[22]), // Inval
3147 .in2 (ext_ret_data_c8[96]),
3148 .sel2 (mux2_sel_c8_2_ff[22]) // Def Sel
3149 ) ;
3150
3151cl_dp1_aomux3_8x ff_cpx_data_ca_1_97
3152 (.out (oque_cpx_data_c8_muxout[97]),
3153 .in0 (tmp_cpx_data_ca_d1[97]),
3154 .sel0 (mux2_sel_c8_0_ff[23]), // Old data sel
3155 .in1 (ext_inval_data_c8[97]),
3156 .sel1 (mux2_sel_c8_1_ff[23]), // Inval
3157 .in2 (ext_ret_data_c8[97]),
3158 .sel2 (mux2_sel_c8_2_ff[23]) // Def Sel
3159 ) ;
3160
3161//--- 101:98 -------//
3162cl_dp1_aomux3_8x ff_cpx_data_ca_1_98
3163 (.out (oque_cpx_data_c8_muxout[98]),
3164 .in0 (tmp_cpx_data_ca_d1[98]),
3165 .sel0 (mux2_sel_c8_0_ff[24]), // Old data sel
3166 .in1 (ext_inval_data_c8[98]),
3167 .sel1 (mux2_sel_c8_1_ff[24]), // Inval
3168 .in2 (ext_ret_data_c8[98]),
3169 .sel2 (mux2_sel_c8_2_ff[24]) // Def Sel
3170 ) ;
3171
3172cl_dp1_aomux3_8x ff_cpx_data_ca_1_99
3173 (.out (oque_cpx_data_c8_muxout[99]),
3174 .in0 (tmp_cpx_data_ca_d1[99]),
3175 .sel0 (mux2_sel_c8_0_ff[25]), // Old data sel
3176 .in1 (ext_inval_data_c8[99]),
3177 .sel1 (mux2_sel_c8_1_ff[25]), // Inval
3178 .in2 (ext_ret_data_c8[99]),
3179 .sel2 (mux2_sel_c8_2_ff[25]) // Def Sel
3180 ) ;
3181
3182cl_dp1_aomux3_8x ff_cpx_data_ca_1_100
3183 (.out (oque_cpx_data_c8_muxout[100]),
3184 .in0 (tmp_cpx_data_ca_d1[100]),
3185 .sel0 (mux2_sel_c8_0_ff[26]), // Old data sel
3186 .in1 (ext_inval_data_c8[100]),
3187 .sel1 (mux2_sel_c8_1_ff[26]), // Inval
3188 .in2 (ext_ret_data_c8[100]),
3189 .sel2 (mux2_sel_c8_2_ff[26]) // Def Sel
3190 ) ;
3191
3192cl_dp1_aomux3_8x ff_cpx_data_ca_1_101
3193 (.out (oque_cpx_data_c8_muxout[101]),
3194 .in0 (tmp_cpx_data_ca_d1[101]),
3195 .sel0 (mux2_sel_c8_0_ff[27]), // Old data sel
3196 .in1 (ext_inval_data_c8[101]),
3197 .sel1 (mux2_sel_c8_1_ff[27]), // Inval
3198 .in2 (ext_ret_data_c8[101]),
3199 .sel2 (mux2_sel_c8_2_ff[27]) // Def Sel
3200 ) ;
3201
3202//--- 105:102 -------//
3203cl_dp1_aomux3_8x ff_cpx_data_ca_1_102
3204 (.out (oque_cpx_data_c8_muxout[102]),
3205 .in0 (tmp_cpx_data_ca_d1[102]),
3206 .sel0 (mux2_sel_c8_0_ff[28]), // Old data sel
3207 .in1 (ext_inval_data_c8[102]),
3208 .sel1 (mux2_sel_c8_1_ff[28]), // Inval
3209 .in2 (ext_ret_data_c8[102]),
3210 .sel2 (mux2_sel_c8_2_ff[28]) // Def Sel
3211 ) ;
3212
3213cl_dp1_aomux3_8x ff_cpx_data_ca_1_103
3214 (.out (oque_cpx_data_c8_muxout[103]),
3215 .in0 (tmp_cpx_data_ca_d1[103]),
3216 .sel0 (mux2_sel_c8_0_ff[29]), // Old data sel
3217 .in1 (ext_inval_data_c8[103]),
3218 .sel1 (mux2_sel_c8_1_ff[29]), // Inval
3219 .in2 (ext_ret_data_c8[103]),
3220 .sel2 (mux2_sel_c8_2_ff[29]) // Def Sel
3221 ) ;
3222
3223cl_dp1_aomux3_8x ff_cpx_data_ca_1_104
3224 (.out (oque_cpx_data_c8_muxout[104]),
3225 .in0 (tmp_cpx_data_ca_d1[104]),
3226 .sel0 (mux2_sel_c8_0_ff[30]), // Old data sel
3227 .in1 (ext_inval_data_c8[104]),
3228 .sel1 (mux2_sel_c8_1_ff[30]), // Inval
3229 .in2 (ext_ret_data_c8[104]),
3230 .sel2 (mux2_sel_c8_2_ff[30]) // Def Sel
3231 ) ;
3232
3233cl_dp1_aomux3_8x ff_cpx_data_ca_1_105
3234 (.out (oque_cpx_data_c8_muxout[105]),
3235 .in0 (tmp_cpx_data_ca_d1[105]),
3236 .sel0 (mux2_sel_c8_0_ff[31]), // Old data sel
3237 .in1 (ext_inval_data_c8[105]),
3238 .sel1 (mux2_sel_c8_1_ff[31]), // Inval
3239 .in2 (ext_ret_data_c8[105]),
3240 .sel2 (mux2_sel_c8_2_ff[31]) // Def Sel
3241 ) ;
3242
3243//--- 109:106 -------//
3244cl_dp1_aomux3_8x ff_cpx_data_ca_1_106
3245 (.out (oque_cpx_data_c8_muxout[106]),
3246 .in0 (tmp_cpx_data_ca_d1[106]),
3247 .sel0 (mux2_sel_c8_0_ff[32]), // Old data sel
3248 .in1 (ext_inval_data_c8[106]),
3249 .sel1 (mux2_sel_c8_1_ff[32]), // Inval
3250 .in2 (ext_ret_data_c8[106]),
3251 .sel2 (mux2_sel_c8_2_ff[32]) // Def Sel
3252 ) ;
3253
3254cl_dp1_aomux3_8x ff_cpx_data_ca_1_107
3255 (.out (oque_cpx_data_c8_muxout[107]),
3256 .in0 (tmp_cpx_data_ca_d1[107]),
3257 .sel0 (mux2_sel_c8_0_ff[33]), // Old data sel
3258 .in1 (ext_inval_data_c8[107]),
3259 .sel1 (mux2_sel_c8_1_ff[33]), // Inval
3260 .in2 (ext_ret_data_c8[107]),
3261 .sel2 (mux2_sel_c8_2_ff[33]) // Def Sel
3262 ) ;
3263
3264cl_dp1_aomux3_8x ff_cpx_data_ca_1_108
3265 (.out (oque_cpx_data_c8_muxout[108]),
3266 .in0 (tmp_cpx_data_ca_d1[108]),
3267 .sel0 (mux2_sel_c8_0_ff[34]), // Old data sel
3268 .in1 (ext_inval_data_c8[108]),
3269 .sel1 (mux2_sel_c8_1_ff[34]), // Inval
3270 .in2 (ext_ret_data_c8[108]),
3271 .sel2 (mux2_sel_c8_2_ff[34]) // Def Sel
3272 ) ;
3273
3274cl_dp1_aomux3_8x ff_cpx_data_ca_1_109
3275 (.out (oque_cpx_data_c8_muxout[109]),
3276 .in0 (tmp_cpx_data_ca_d1[109]),
3277 .sel0 (mux2_sel_c8_0_ff[35]), // Old data sel
3278 .in1 (ext_inval_data_c8[109]),
3279 .sel1 (mux2_sel_c8_1_ff[35]), // Inval
3280 .in2 (ext_ret_data_c8[109]),
3281 .sel2 (mux2_sel_c8_2_ff[35]) // Def Sel
3282 ) ;
3283
3284///////////////////////////////////////////////////////////////////////////////////////////////
3285///////////////////////////////////////////////////////////////////////////////////////////////
3286// Third Row of muxes.
3287///////////////////////////////////////////////////////////////////////////////////////////////
3288
3289//--- 41:38 -------//
3290cl_dp1_aomux3_8x ff_cpx_data_ca_1_38
3291 (.out (oque_cpx_data_c8_muxout[38]),
3292 .in0 (tmp_cpx_data_ca_d1[38]),
3293 .sel0 (mux2_sel_c8_0_ff[0]), // Old data sel
3294 .in1 (ext_inval_data_c8[38]),
3295 .sel1 (mux2_sel_c8_1_ff[0]), // Inval
3296 .in2 (ext_ret_data_c8[38]),
3297 .sel2 (mux2_sel_c8_2_ff[0]) // Def Sel
3298 ) ;
3299
3300cl_dp1_aomux3_8x ff_cpx_data_ca_1_39
3301 (.out (oque_cpx_data_c8_muxout[39]),
3302 .in0 (tmp_cpx_data_ca_d1[39]),
3303 .sel0 (mux2_sel_c8_0_ff[1]), // Old data sel
3304 .in1 (ext_inval_data_c8[39]),
3305 .sel1 (mux2_sel_c8_1_ff[1]), // Inval
3306 .in2 (ext_ret_data_c8[39]),
3307 .sel2 (mux2_sel_c8_2_ff[1]) // Def Sel
3308 ) ;
3309
3310cl_dp1_aomux3_8x ff_cpx_data_ca_1_40
3311 (.out (oque_cpx_data_c8_muxout[40]),
3312 .in0 (tmp_cpx_data_ca_d1[40]),
3313 .sel0 (mux2_sel_c8_0_ff[2]), // Old data sel
3314 .in1 (ext_inval_data_c8[40]),
3315 .sel1 (mux2_sel_c8_1_ff[2]), // Inval
3316 .in2 (ext_ret_data_c8[40]),
3317 .sel2 (mux2_sel_c8_2_ff[2]) // Def Sel
3318 ) ;
3319
3320cl_dp1_aomux3_8x ff_cpx_data_ca_1_41
3321 (.out (oque_cpx_data_c8_muxout[41]),
3322 .in0 (tmp_cpx_data_ca_d1[41]),
3323 .sel0 (mux2_sel_c8_0_ff[3]), // Old data sel
3324 .in1 (ext_inval_data_c8[41]),
3325 .sel1 (mux2_sel_c8_1_ff[3]), // Inval
3326 .in2 (ext_ret_data_c8[41]),
3327 .sel2 (mux2_sel_c8_2_ff[3]) // Def Sel
3328 ) ;
3329//--- 45:42 -------//
3330cl_dp1_aomux3_8x ff_cpx_data_ca_1_42
3331 (.out (oque_cpx_data_c8_muxout[42]),
3332 .in0 (tmp_cpx_data_ca_d1[42]),
3333 .sel0 (mux2_sel_c8_0_ff[4]), // Old data sel
3334 .in1 (ext_inval_data_c8[42]),
3335 .sel1 (mux2_sel_c8_1_ff[4]), // Inval
3336 .in2 (ext_ret_data_c8[42]),
3337 .sel2 (mux2_sel_c8_2_ff[4]) // Def Sel
3338 ) ;
3339
3340cl_dp1_aomux3_8x ff_cpx_data_ca_1_43
3341 (.out (oque_cpx_data_c8_muxout[43]),
3342 .in0 (tmp_cpx_data_ca_d1[43]),
3343 .sel0 (mux2_sel_c8_0_ff[5]), // Old data sel
3344 .in1 (ext_inval_data_c8[43]),
3345 .sel1 (mux2_sel_c8_1_ff[5]), // Inval
3346 .in2 (ext_ret_data_c8[43]),
3347 .sel2 (mux2_sel_c8_2_ff[5]) // Def Sel
3348 ) ;
3349
3350cl_dp1_aomux3_8x ff_cpx_data_ca_1_44
3351 (.out (oque_cpx_data_c8_muxout[44]),
3352 .in0 (tmp_cpx_data_ca_d1[44]),
3353 .sel0 (mux2_sel_c8_0_ff[6]), // Old data sel
3354 .in1 (ext_inval_data_c8[44]),
3355 .sel1 (mux2_sel_c8_1_ff[6]), // Inval
3356 .in2 (ext_ret_data_c8[44]),
3357 .sel2 (mux2_sel_c8_2_ff[6]) // Def Sel
3358 ) ;
3359
3360cl_dp1_aomux3_8x ff_cpx_data_ca_1_45
3361 (.out (oque_cpx_data_c8_muxout[45]),
3362 .in0 (tmp_cpx_data_ca_d1[45]),
3363 .sel0 (mux2_sel_c8_0_ff[7]), // Old data sel
3364 .in1 (ext_inval_data_c8[45]),
3365 .sel1 (mux2_sel_c8_1_ff[7]), // Inval
3366 .in2 (ext_ret_data_c8[45]),
3367 .sel2 (mux2_sel_c8_2_ff[7]) // Def Sel
3368 ) ;
3369
3370//--- 49:46 -------//
3371cl_dp1_aomux3_8x ff_cpx_data_ca_1_46
3372 (.out (oque_cpx_data_c8_muxout[46]),
3373 .in0 (tmp_cpx_data_ca_d1[46]),
3374 .sel0 (mux2_sel_c8_0_ff[8]), // Old data sel
3375 .in1 (ext_inval_data_c8[46]),
3376 .sel1 (mux2_sel_c8_1_ff[8]), // Inval
3377 .in2 (ext_ret_data_c8[46]),
3378 .sel2 (mux2_sel_c8_2_ff[8]) // Def Sel
3379 ) ;
3380
3381cl_dp1_aomux3_8x ff_cpx_data_ca_1_47
3382 (.out (oque_cpx_data_c8_muxout[47]),
3383 .in0 (tmp_cpx_data_ca_d1[47]),
3384 .sel0 (mux2_sel_c8_0_ff[9]), // Old data sel
3385 .in1 (ext_inval_data_c8[47]),
3386 .sel1 (mux2_sel_c8_1_ff[9]), // Inval
3387 .in2 (ext_ret_data_c8[47]),
3388 .sel2 (mux2_sel_c8_2_ff[9]) // Def Sel
3389 ) ;
3390
3391cl_dp1_aomux3_8x ff_cpx_data_ca_1_48
3392 (.out (oque_cpx_data_c8_muxout[48]),
3393 .in0 (tmp_cpx_data_ca_d1[48]),
3394 .sel0 (mux2_sel_c8_0_ff[10]), // Old data sel
3395 .in1 (ext_inval_data_c8[48]),
3396 .sel1 (mux2_sel_c8_1_ff[10]), // Inval
3397 .in2 (ext_ret_data_c8[48]),
3398 .sel2 (mux2_sel_c8_2_ff[10]) // Def Sel
3399 ) ;
3400
3401cl_dp1_aomux3_8x ff_cpx_data_ca_1_49
3402 (.out (oque_cpx_data_c8_muxout[49]),
3403 .in0 (tmp_cpx_data_ca_d1[49]),
3404 .sel0 (mux2_sel_c8_0_ff[11]), // Old data sel
3405 .in1 (ext_inval_data_c8[49]),
3406 .sel1 (mux2_sel_c8_1_ff[11]), // Inval
3407 .in2 (ext_ret_data_c8[49]),
3408 .sel2 (mux2_sel_c8_2_ff[11]) // Def Sel
3409 ) ;
3410
3411//--- 53:50 -------//
3412cl_dp1_aomux3_8x ff_cpx_data_ca_1_50
3413 (.out (oque_cpx_data_c8_muxout[50]),
3414 .in0 (tmp_cpx_data_ca_d1[50]),
3415 .sel0 (mux2_sel_c8_0_ff[12]), // Old data sel
3416 .in1 (ext_inval_data_c8[50]),
3417 .sel1 (mux2_sel_c8_1_ff[12]), // Inval
3418 .in2 (ext_ret_data_c8[50]),
3419 .sel2 (mux2_sel_c8_2_ff[12]) // Def Sel
3420 ) ;
3421
3422cl_dp1_aomux3_8x ff_cpx_data_ca_1_51
3423 (.out (oque_cpx_data_c8_muxout[51]),
3424 .in0 (tmp_cpx_data_ca_d1[51]),
3425 .sel0 (mux2_sel_c8_0_ff[13]), // Old data sel
3426 .in1 (ext_inval_data_c8[51]),
3427 .sel1 (mux2_sel_c8_1_ff[13]), // Inval
3428 .in2 (ext_ret_data_c8[51]),
3429 .sel2 (mux2_sel_c8_2_ff[13]) // Def Sel
3430 ) ;
3431
3432cl_dp1_aomux3_8x ff_cpx_data_ca_1_52
3433 (.out (oque_cpx_data_c8_muxout[52]),
3434 .in0 (tmp_cpx_data_ca_d1[52]),
3435 .sel0 (mux2_sel_c8_0_ff[14]), // Old data sel
3436 .in1 (ext_inval_data_c8[52]),
3437 .sel1 (mux2_sel_c8_1_ff[14]), // Inval
3438 .in2 (ext_ret_data_c8[52]),
3439 .sel2 (mux2_sel_c8_2_ff[14]) // Def Sel
3440 ) ;
3441
3442cl_dp1_aomux3_8x ff_cpx_data_ca_1_53
3443 (.out (oque_cpx_data_c8_muxout[53]),
3444 .in0 (tmp_cpx_data_ca_d1[53]),
3445 .sel0 (mux2_sel_c8_0_ff[15]), // Old data sel
3446 .in1 (ext_inval_data_c8[53]),
3447 .sel1 (mux2_sel_c8_1_ff[15]), // Inval
3448 .in2 (ext_ret_data_c8[53]),
3449 .sel2 (mux2_sel_c8_2_ff[15]) // Def Sel
3450 ) ;
3451
3452//--- 57:54 -------//
3453cl_dp1_aomux3_8x ff_cpx_data_ca_1_54
3454 (.out (oque_cpx_data_c8_muxout[54]),
3455 .in0 (tmp_cpx_data_ca_d1[54]),
3456 .sel0 (mux2_sel_c8_0_ff[16]), // Old data sel
3457 .in1 (ext_inval_data_c8[54]),
3458 .sel1 (mux2_sel_c8_1_ff[16]), // Inval
3459 .in2 (ext_ret_data_c8[54]),
3460 .sel2 (mux2_sel_c8_2_ff[16]) // Def Sel
3461 ) ;
3462
3463cl_dp1_aomux3_8x ff_cpx_data_ca_1_55
3464 (.out (oque_cpx_data_c8_muxout[55]),
3465 .in0 (tmp_cpx_data_ca_d1[55]),
3466 .sel0 (mux2_sel_c8_0_ff[17]), // Old data sel
3467 .in1 (ext_inval_data_c8[55]),
3468 .sel1 (mux2_sel_c8_1_ff[17]), // Inval
3469 .in2 (ext_ret_data_c8[55]),
3470 .sel2 (mux2_sel_c8_2_ff[17]) // Def Sel
3471 ) ;
3472
3473cl_dp1_aomux3_8x ff_cpx_data_ca_1_56
3474 (.out (oque_cpx_data_c8_muxout[56]),
3475 .in0 (tmp_cpx_data_ca_d1[56]),
3476 .sel0 (mux2_sel_c8_0_ff[18]), // Old data sel
3477 .in1 (ext_inval_data_c8[56]),
3478 .sel1 (mux2_sel_c8_1_ff[18]), // Inval
3479 .in2 (ext_ret_data_c8[56]),
3480 .sel2 (mux2_sel_c8_2_ff[18]) // Def Sel
3481 ) ;
3482
3483cl_dp1_aomux3_8x ff_cpx_data_ca_1_57
3484 (.out (oque_cpx_data_c8_muxout[57]),
3485 .in0 (tmp_cpx_data_ca_d1[57]),
3486 .sel0 (mux2_sel_c8_0_ff[19]), // Old data sel
3487 .in1 (ext_inval_data_c8[57]),
3488 .sel1 (mux2_sel_c8_1_ff[19]), // Inval
3489 .in2 (ext_ret_data_c8[57]),
3490 .sel2 (mux2_sel_c8_2_ff[19]) // Def Sel
3491 ) ;
3492
3493//--- 61:58 -------//
3494cl_dp1_aomux3_8x ff_cpx_data_ca_1_58
3495 (.out (oque_cpx_data_c8_muxout[58]),
3496 .in0 (tmp_cpx_data_ca_d1[58]),
3497 .sel0 (mux2_sel_c8_0_ff[20]), // Old data sel
3498 .in1 (ext_inval_data_c8[58]),
3499 .sel1 (mux2_sel_c8_1_ff[20]), // Inval
3500 .in2 (ext_ret_data_c8[58]),
3501 .sel2 (mux2_sel_c8_2_ff[20]) // Def Sel
3502 ) ;
3503
3504cl_dp1_aomux3_8x ff_cpx_data_ca_1_59
3505 (.out (oque_cpx_data_c8_muxout[59]),
3506 .in0 (tmp_cpx_data_ca_d1[59]),
3507 .sel0 (mux2_sel_c8_0_ff[21]), // Old data sel
3508 .in1 (ext_inval_data_c8[59]),
3509 .sel1 (mux2_sel_c8_1_ff[21]), // Inval
3510 .in2 (ext_ret_data_c8[59]),
3511 .sel2 (mux2_sel_c8_2_ff[21]) // Def Sel
3512 ) ;
3513
3514cl_dp1_aomux3_8x ff_cpx_data_ca_1_60
3515 (.out (oque_cpx_data_c8_muxout[60]),
3516 .in0 (tmp_cpx_data_ca_d1[60]),
3517 .sel0 (mux2_sel_c8_0_ff[22]), // Old data sel
3518 .in1 (ext_inval_data_c8[60]),
3519 .sel1 (mux2_sel_c8_1_ff[22]), // Inval
3520 .in2 (ext_ret_data_c8[60]),
3521 .sel2 (mux2_sel_c8_2_ff[22]) // Def Sel
3522 ) ;
3523
3524cl_dp1_aomux3_8x ff_cpx_data_ca_1_61
3525 (.out (oque_cpx_data_c8_muxout[61]),
3526 .in0 (tmp_cpx_data_ca_d1[61]),
3527 .sel0 (mux2_sel_c8_0_ff[23]), // Old data sel
3528 .in1 (ext_inval_data_c8[61]),
3529 .sel1 (mux2_sel_c8_1_ff[23]), // Inval
3530 .in2 (ext_ret_data_c8[61]),
3531 .sel2 (mux2_sel_c8_2_ff[23]) // Def Sel
3532 ) ;
3533
3534//--- 65:62 -------//
3535cl_dp1_aomux3_8x ff_cpx_data_ca_1_62
3536 (.out (oque_cpx_data_c8_muxout[62]),
3537 .in0 (tmp_cpx_data_ca_d1[62]),
3538 .sel0 (mux2_sel_c8_0_ff[24]), // Old data sel
3539 .in1 (ext_inval_data_c8[62]),
3540 .sel1 (mux2_sel_c8_1_ff[24]), // Inval
3541 .in2 (ext_ret_data_c8[62]),
3542 .sel2 (mux2_sel_c8_2_ff[24]) // Def Sel
3543 ) ;
3544
3545cl_dp1_aomux3_8x ff_cpx_data_ca_1_63
3546 (.out (oque_cpx_data_c8_muxout[63]),
3547 .in0 (tmp_cpx_data_ca_d1[63]),
3548 .sel0 (mux2_sel_c8_0_ff[25]), // Old data sel
3549 .in1 (ext_inval_data_c8[63]),
3550 .sel1 (mux2_sel_c8_1_ff[25]), // Inval
3551 .in2 (ext_ret_data_c8[63]),
3552 .sel2 (mux2_sel_c8_2_ff[25]) // Def Sel
3553 ) ;
3554
3555cl_dp1_aomux3_8x ff_cpx_data_ca_1_64
3556 (.out (oque_cpx_data_c8_muxout[64]),
3557 .in0 (tmp_cpx_data_ca_d1[64]),
3558 .sel0 (mux2_sel_c8_0_ff[26]), // Old data sel
3559 .in1 (ext_inval_data_c8[64]),
3560 .sel1 (mux2_sel_c8_1_ff[26]), // Inval
3561 .in2 (ext_ret_data_c8[64]),
3562 .sel2 (mux2_sel_c8_2_ff[26]) // Def Sel
3563 ) ;
3564
3565cl_dp1_aomux3_8x ff_cpx_data_ca_1_65
3566 (.out (oque_cpx_data_c8_muxout[65]),
3567 .in0 (tmp_cpx_data_ca_d1[65]),
3568 .sel0 (mux2_sel_c8_0_ff[27]), // Old data sel
3569 .in1 (ext_inval_data_c8[65]),
3570 .sel1 (mux2_sel_c8_1_ff[27]), // Inval
3571 .in2 (ext_ret_data_c8[65]),
3572 .sel2 (mux2_sel_c8_2_ff[27]) // Def Sel
3573 ) ;
3574
3575//--- 69:66 -------//
3576cl_dp1_aomux3_8x ff_cpx_data_ca_1_66
3577 (.out (oque_cpx_data_c8_muxout[66]),
3578 .in0 (tmp_cpx_data_ca_d1[66]),
3579 .sel0 (mux2_sel_c8_0_ff[28]), // Old data sel
3580 .in1 (ext_inval_data_c8[66]),
3581 .sel1 (mux2_sel_c8_1_ff[28]), // Inval
3582 .in2 (ext_ret_data_c8[66]),
3583 .sel2 (mux2_sel_c8_2_ff[28]) // Def Sel
3584 ) ;
3585
3586cl_dp1_aomux3_8x ff_cpx_data_ca_1_67
3587 (.out (oque_cpx_data_c8_muxout[67]),
3588 .in0 (tmp_cpx_data_ca_d1[67]),
3589 .sel0 (mux2_sel_c8_0_ff[29]), // Old data sel
3590 .in1 (ext_inval_data_c8[67]),
3591 .sel1 (mux2_sel_c8_1_ff[29]), // Inval
3592 .in2 (ext_ret_data_c8[67]),
3593 .sel2 (mux2_sel_c8_2_ff[29]) // Def Sel
3594 ) ;
3595
3596cl_dp1_aomux3_8x ff_cpx_data_ca_1_68
3597 (.out (oque_cpx_data_c8_muxout[68]),
3598 .in0 (tmp_cpx_data_ca_d1[68]),
3599 .sel0 (mux2_sel_c8_0_ff[30]), // Old data sel
3600 .in1 (ext_inval_data_c8[68]),
3601 .sel1 (mux2_sel_c8_1_ff[30]), // Inval
3602 .in2 (ext_ret_data_c8[68]),
3603 .sel2 (mux2_sel_c8_2_ff[30]) // Def Sel
3604 ) ;
3605
3606cl_dp1_aomux3_8x ff_cpx_data_ca_1_69
3607 (.out (oque_cpx_data_c8_muxout[69]),
3608 .in0 (tmp_cpx_data_ca_d1[69]),
3609 .sel0 (mux2_sel_c8_0_ff[31]), // Old data sel
3610 .in1 (ext_inval_data_c8[69]),
3611 .sel1 (mux2_sel_c8_1_ff[31]), // Inval
3612 .in2 (ext_ret_data_c8[69]),
3613 .sel2 (mux2_sel_c8_2_ff[31]) // Def Sel
3614 ) ;
3615
3616//--- 73:70 -------//
3617cl_dp1_aomux3_8x ff_cpx_data_ca_1_70
3618 (.out (oque_cpx_data_c8_muxout[70]),
3619 .in0 (tmp_cpx_data_ca_d1[70]),
3620 .sel0 (mux2_sel_c8_0_ff[32]), // Old data sel
3621 .in1 (ext_inval_data_c8[70]),
3622 .sel1 (mux2_sel_c8_1_ff[32]), // Inval
3623 .in2 (ext_ret_data_c8[70]),
3624 .sel2 (mux2_sel_c8_2_ff[32]) // Def Sel
3625 ) ;
3626
3627cl_dp1_aomux3_8x ff_cpx_data_ca_1_71
3628 (.out (oque_cpx_data_c8_muxout[71]),
3629 .in0 (tmp_cpx_data_ca_d1[71]),
3630 .sel0 (mux2_sel_c8_0_ff[33]), // Old data sel
3631 .in1 (ext_inval_data_c8[71]),
3632 .sel1 (mux2_sel_c8_1_ff[33]), // Inval
3633 .in2 (ext_ret_data_c8[71]),
3634 .sel2 (mux2_sel_c8_2_ff[33]) // Def Sel
3635 ) ;
3636
3637cl_dp1_aomux3_8x ff_cpx_data_ca_1_72
3638 (.out (oque_cpx_data_c8_muxout[72]),
3639 .in0 (tmp_cpx_data_ca_d1[72]),
3640 .sel0 (mux2_sel_c8_0_ff[34]), // Old data sel
3641 .in1 (ext_inval_data_c8[72]),
3642 .sel1 (mux2_sel_c8_1_ff[34]), // Inval
3643 .in2 (ext_ret_data_c8[72]),
3644 .sel2 (mux2_sel_c8_2_ff[34]) // Def Sel
3645 ) ;
3646
3647cl_dp1_aomux3_8x ff_cpx_data_ca_1_73
3648 (.out (oque_cpx_data_c8_muxout[73]),
3649 .in0 (tmp_cpx_data_ca_d1[73]),
3650 .sel0 (mux2_sel_c8_0_ff[35]), // Old data sel
3651 .in1 (ext_inval_data_c8[73]),
3652 .sel1 (mux2_sel_c8_1_ff[35]), // Inval
3653 .in2 (ext_ret_data_c8[73]),
3654 .sel2 (mux2_sel_c8_2_ff[35]) // Def Sel
3655 ) ;
3656
3657///////////////////////////////////////////////////////////////////////////////////////////////
3658///////////////////////////////////////////////////////////////////////////////////////////////
3659// Fourth Row of muxes.
3660///////////////////////////////////////////////////////////////////////////////////////////////
3661
3662//--- 3:0 -------//
3663cl_dp1_aomux3_8x ff_cpx_data_ca_1_0
3664 (.out (oque_cpx_data_c8_muxout[0]),
3665 .in0 (tmp_cpx_data_ca_d1[0]),
3666 .sel0 (mux2_sel_c8_0_ff[0]), // Old data sel
3667 .in1 (ext_inval_data_c8[0]),
3668 .sel1 (mux2_sel_c8_1_ff[0]), // Inval
3669 .in2 (ext_ret_data_c8[0]),
3670 .sel2 (mux2_sel_c8_2_ff[0]) // Def Sel
3671 ) ;
3672
3673cl_dp1_aomux3_8x ff_cpx_data_ca_1_1
3674 (.out (oque_cpx_data_c8_muxout[1]),
3675 .in0 (tmp_cpx_data_ca_d1[1]),
3676 .sel0 (mux2_sel_c8_0_ff[1]), // Old data sel
3677 .in1 (ext_inval_data_c8[1]),
3678 .sel1 (mux2_sel_c8_1_ff[1]), // Inval
3679 .in2 (ext_ret_data_c8[1]),
3680 .sel2 (mux2_sel_c8_2_ff[1]) // Def Sel
3681 ) ;
3682
3683cl_dp1_aomux3_8x ff_cpx_data_ca_1_2
3684 (.out (oque_cpx_data_c8_muxout[2]),
3685 .in0 (tmp_cpx_data_ca_d1[2]),
3686 .sel0 (mux2_sel_c8_0_ff[2]), // Old data sel
3687 .in1 (ext_inval_data_c8[2]),
3688 .sel1 (mux2_sel_c8_1_ff[2]), // Inval
3689 .in2 (ext_ret_data_c8[2]),
3690 .sel2 (mux2_sel_c8_2_ff[2]) // Def Sel
3691 ) ;
3692
3693cl_dp1_aomux3_8x ff_cpx_data_ca_1_3
3694 (.out (oque_cpx_data_c8_muxout[3]),
3695 .in0 (tmp_cpx_data_ca_d1[3]),
3696 .sel0 (mux2_sel_c8_0_ff[3]), // Old data sel
3697 .in1 (ext_inval_data_c8[3]),
3698 .sel1 (mux2_sel_c8_1_ff[3]), // Inval
3699 .in2 (ext_ret_data_c8[3]),
3700 .sel2 (mux2_sel_c8_2_ff[3]) // Def Sel
3701 ) ;
3702//--- 7:4 -------//
3703cl_dp1_aomux3_8x ff_cpx_data_ca_1_4
3704 (.out (oque_cpx_data_c8_muxout[4]),
3705 .in0 (tmp_cpx_data_ca_d1[4]),
3706 .sel0 (mux2_sel_c8_0_ff[4]), // Old data sel
3707 .in1 (ext_inval_data_c8[4]),
3708 .sel1 (mux2_sel_c8_1_ff[4]), // Inval
3709 .in2 (ext_ret_data_c8[4]),
3710 .sel2 (mux2_sel_c8_2_ff[4]) // Def Sel
3711 ) ;
3712
3713cl_dp1_aomux3_8x ff_cpx_data_ca_1_5
3714 (.out (oque_cpx_data_c8_muxout[5]),
3715 .in0 (tmp_cpx_data_ca_d1[5]),
3716 .sel0 (mux2_sel_c8_0_ff[5]), // Old data sel
3717 .in1 (ext_inval_data_c8[5]),
3718 .sel1 (mux2_sel_c8_1_ff[5]), // Inval
3719 .in2 (ext_ret_data_c8[5]),
3720 .sel2 (mux2_sel_c8_2_ff[5]) // Def Sel
3721 ) ;
3722
3723cl_dp1_aomux3_8x ff_cpx_data_ca_1_6
3724 (.out (oque_cpx_data_c8_muxout[6]),
3725 .in0 (tmp_cpx_data_ca_d1[6]),
3726 .sel0 (mux2_sel_c8_0_ff[6]), // Old data sel
3727 .in1 (ext_inval_data_c8[6]),
3728 .sel1 (mux2_sel_c8_1_ff[6]), // Inval
3729 .in2 (ext_ret_data_c8[6]),
3730 .sel2 (mux2_sel_c8_2_ff[6]) // Def Sel
3731 ) ;
3732
3733cl_dp1_aomux3_8x ff_cpx_data_ca_1_7
3734 (.out (oque_cpx_data_c8_muxout[7]),
3735 .in0 (tmp_cpx_data_ca_d1[7]),
3736 .sel0 (mux2_sel_c8_0_ff[7]), // Old data sel
3737 .in1 (ext_inval_data_c8[7]),
3738 .sel1 (mux2_sel_c8_1_ff[7]), // Inval
3739 .in2 (ext_ret_data_c8[7]),
3740 .sel2 (mux2_sel_c8_2_ff[7]) // Def Sel
3741 ) ;
3742
3743//--- 11:8 -------//
3744cl_dp1_aomux3_8x ff_cpx_data_ca_1_8
3745 (.out (oque_cpx_data_c8_muxout[8]),
3746 .in0 (tmp_cpx_data_ca_d1[8]),
3747 .sel0 (mux2_sel_c8_0_ff[8]), // Old data sel
3748 .in1 (ext_inval_data_c8[8]),
3749 .sel1 (mux2_sel_c8_1_ff[8]), // Inval
3750 .in2 (ext_ret_data_c8[8]),
3751 .sel2 (mux2_sel_c8_2_ff[8]) // Def Sel
3752 ) ;
3753
3754cl_dp1_aomux3_8x ff_cpx_data_ca_1_9
3755 (.out (oque_cpx_data_c8_muxout[9]),
3756 .in0 (tmp_cpx_data_ca_d1[9]),
3757 .sel0 (mux2_sel_c8_0_ff[9]), // Old data sel
3758 .in1 (ext_inval_data_c8[9]),
3759 .sel1 (mux2_sel_c8_1_ff[9]), // Inval
3760 .in2 (ext_ret_data_c8[9]),
3761 .sel2 (mux2_sel_c8_2_ff[9]) // Def Sel
3762 ) ;
3763
3764cl_dp1_aomux3_8x ff_cpx_data_ca_1_10
3765 (.out (oque_cpx_data_c8_muxout[10]),
3766 .in0 (tmp_cpx_data_ca_d1[10]),
3767 .sel0 (mux2_sel_c8_0_ff[10]), // Old data sel
3768 .in1 (ext_inval_data_c8[10]),
3769 .sel1 (mux2_sel_c8_1_ff[10]), // Inval
3770 .in2 (ext_ret_data_c8[10]),
3771 .sel2 (mux2_sel_c8_2_ff[10]) // Def Sel
3772 ) ;
3773
3774cl_dp1_aomux3_8x ff_cpx_data_ca_1_11
3775 (.out (oque_cpx_data_c8_muxout[11]),
3776 .in0 (tmp_cpx_data_ca_d1[11]),
3777 .sel0 (mux2_sel_c8_0_ff[11]), // Old data sel
3778 .in1 (ext_inval_data_c8[11]),
3779 .sel1 (mux2_sel_c8_1_ff[11]), // Inval
3780 .in2 (ext_ret_data_c8[11]),
3781 .sel2 (mux2_sel_c8_2_ff[11]) // Def Sel
3782 ) ;
3783
3784//--- 15:12 -------//
3785cl_dp1_aomux3_8x ff_cpx_data_ca_1_12
3786 (.out (oque_cpx_data_c8_muxout[12]),
3787 .in0 (tmp_cpx_data_ca_d1[12]),
3788 .sel0 (mux2_sel_c8_0_ff[12]), // Old data sel
3789 .in1 (ext_inval_data_c8[12]),
3790 .sel1 (mux2_sel_c8_1_ff[12]), // Inval
3791 .in2 (ext_ret_data_c8[12]),
3792 .sel2 (mux2_sel_c8_2_ff[12]) // Def Sel
3793 ) ;
3794
3795cl_dp1_aomux3_8x ff_cpx_data_ca_1_13
3796 (.out (oque_cpx_data_c8_muxout[13]),
3797 .in0 (tmp_cpx_data_ca_d1[13]),
3798 .sel0 (mux2_sel_c8_0_ff[13]), // Old data sel
3799 .in1 (ext_inval_data_c8[13]),
3800 .sel1 (mux2_sel_c8_1_ff[13]), // Inval
3801 .in2 (ext_ret_data_c8[13]),
3802 .sel2 (mux2_sel_c8_2_ff[13]) // Def Sel
3803 ) ;
3804
3805cl_dp1_aomux3_8x ff_cpx_data_ca_1_14
3806 (.out (oque_cpx_data_c8_muxout[14]),
3807 .in0 (tmp_cpx_data_ca_d1[14]),
3808 .sel0 (mux2_sel_c8_0_ff[14]), // Old data sel
3809 .in1 (ext_inval_data_c8[14]),
3810 .sel1 (mux2_sel_c8_1_ff[14]), // Inval
3811 .in2 (ext_ret_data_c8[14]),
3812 .sel2 (mux2_sel_c8_2_ff[14]) // Def Sel
3813 ) ;
3814
3815cl_dp1_aomux3_8x ff_cpx_data_ca_1_15
3816 (.out (oque_cpx_data_c8_muxout[15]),
3817 .in0 (tmp_cpx_data_ca_d1[15]),
3818 .sel0 (mux2_sel_c8_0_ff[15]), // Old data sel
3819 .in1 (ext_inval_data_c8[15]),
3820 .sel1 (mux2_sel_c8_1_ff[15]), // Inval
3821 .in2 (ext_ret_data_c8[15]),
3822 .sel2 (mux2_sel_c8_2_ff[15]) // Def Sel
3823 ) ;
3824
3825//--- 19:16 -------//
3826cl_dp1_aomux3_8x ff_cpx_data_ca_1_16
3827 (.out (oque_cpx_data_c8_muxout[16]),
3828 .in0 (tmp_cpx_data_ca_d1[16]),
3829 .sel0 (mux2_sel_c8_0_ff[16]), // Old data sel
3830 .in1 (ext_inval_data_c8[16]),
3831 .sel1 (mux2_sel_c8_1_ff[16]), // Inval
3832 .in2 (ext_ret_data_c8[16]),
3833 .sel2 (mux2_sel_c8_2_ff[16]) // Def Sel
3834 ) ;
3835
3836cl_dp1_aomux3_8x ff_cpx_data_ca_1_17
3837 (.out (oque_cpx_data_c8_muxout[17]),
3838 .in0 (tmp_cpx_data_ca_d1[17]),
3839 .sel0 (mux2_sel_c8_0_ff[17]), // Old data sel
3840 .in1 (ext_inval_data_c8[17]),
3841 .sel1 (mux2_sel_c8_1_ff[17]), // Inval
3842 .in2 (ext_ret_data_c8[17]),
3843 .sel2 (mux2_sel_c8_2_ff[17]) // Def Sel
3844 ) ;
3845
3846cl_dp1_aomux3_8x ff_cpx_data_ca_1_18
3847 (.out (oque_cpx_data_c8_muxout[18]),
3848 .in0 (tmp_cpx_data_ca_d1[18]),
3849 .sel0 (mux2_sel_c8_0_ff[18]), // Old data sel
3850 .in1 (ext_inval_data_c8[18]),
3851 .sel1 (mux2_sel_c8_1_ff[18]), // Inval
3852 .in2 (ext_ret_data_c8[18]),
3853 .sel2 (mux2_sel_c8_2_ff[18]) // Def Sel
3854 ) ;
3855
3856cl_dp1_aomux3_8x ff_cpx_data_ca_1_19
3857 (.out (oque_cpx_data_c8_muxout[19]),
3858 .in0 (tmp_cpx_data_ca_d1[19]),
3859 .sel0 (mux2_sel_c8_0_ff[19]), // Old data sel
3860 .in1 (ext_inval_data_c8[19]),
3861 .sel1 (mux2_sel_c8_1_ff[19]), // Inval
3862 .in2 (ext_ret_data_c8[19]),
3863 .sel2 (mux2_sel_c8_2_ff[19]) // Def Sel
3864 ) ;
3865
3866//--- 23:20 -------//
3867cl_dp1_aomux3_8x ff_cpx_data_ca_1_20
3868 (.out (oque_cpx_data_c8_muxout[20]),
3869 .in0 (tmp_cpx_data_ca_d1[20]),
3870 .sel0 (mux2_sel_c8_0_ff[20]), // Old data sel
3871 .in1 (ext_inval_data_c8[20]),
3872 .sel1 (mux2_sel_c8_1_ff[20]), // Inval
3873 .in2 (ext_ret_data_c8[20]),
3874 .sel2 (mux2_sel_c8_2_ff[20]) // Def Sel
3875 ) ;
3876
3877cl_dp1_aomux3_8x ff_cpx_data_ca_1_21
3878 (.out (oque_cpx_data_c8_muxout[21]),
3879 .in0 (tmp_cpx_data_ca_d1[21]),
3880 .sel0 (mux2_sel_c8_0_ff[21]), // Old data sel
3881 .in1 (ext_inval_data_c8[21]),
3882 .sel1 (mux2_sel_c8_1_ff[21]), // Inval
3883 .in2 (ext_ret_data_c8[21]),
3884 .sel2 (mux2_sel_c8_2_ff[21]) // Def Sel
3885 ) ;
3886
3887cl_dp1_aomux3_8x ff_cpx_data_ca_1_22
3888 (.out (oque_cpx_data_c8_muxout[22]),
3889 .in0 (tmp_cpx_data_ca_d1[22]),
3890 .sel0 (mux2_sel_c8_0_ff[22]), // Old data sel
3891 .in1 (ext_inval_data_c8[22]),
3892 .sel1 (mux2_sel_c8_1_ff[22]), // Inval
3893 .in2 (ext_ret_data_c8[22]),
3894 .sel2 (mux2_sel_c8_2_ff[22]) // Def Sel
3895 ) ;
3896
3897cl_dp1_aomux3_8x ff_cpx_data_ca_1_23
3898 (.out (oque_cpx_data_c8_muxout[23]),
3899 .in0 (tmp_cpx_data_ca_d1[23]),
3900 .sel0 (mux2_sel_c8_0_ff[23]), // Old data sel
3901 .in1 (ext_inval_data_c8[23]),
3902 .sel1 (mux2_sel_c8_1_ff[23]), // Inval
3903 .in2 (ext_ret_data_c8[23]),
3904 .sel2 (mux2_sel_c8_2_ff[23]) // Def Sel
3905 ) ;
3906
3907//--- 27:24 -------//
3908cl_dp1_aomux3_8x ff_cpx_data_ca_1_24
3909 (.out (oque_cpx_data_c8_muxout[24]),
3910 .in0 (tmp_cpx_data_ca_d1[24]),
3911 .sel0 (mux2_sel_c8_0_ff[24]), // Old data sel
3912 .in1 (ext_inval_data_c8[24]),
3913 .sel1 (mux2_sel_c8_1_ff[24]), // Inval
3914 .in2 (ext_ret_data_c8[24]),
3915 .sel2 (mux2_sel_c8_2_ff[24]) // Def Sel
3916 ) ;
3917
3918cl_dp1_aomux3_8x ff_cpx_data_ca_1_25
3919 (.out (oque_cpx_data_c8_muxout[25]),
3920 .in0 (tmp_cpx_data_ca_d1[25]),
3921 .sel0 (mux2_sel_c8_0_ff[25]), // Old data sel
3922 .in1 (ext_inval_data_c8[25]),
3923 .sel1 (mux2_sel_c8_1_ff[25]), // Inval
3924 .in2 (ext_ret_data_c8[25]),
3925 .sel2 (mux2_sel_c8_2_ff[25]) // Def Sel
3926 ) ;
3927
3928cl_dp1_aomux3_8x ff_cpx_data_ca_1_26
3929 (.out (oque_cpx_data_c8_muxout[26]),
3930 .in0 (tmp_cpx_data_ca_d1[26]),
3931 .sel0 (mux2_sel_c8_0_ff[26]), // Old data sel
3932 .in1 (ext_inval_data_c8[26]),
3933 .sel1 (mux2_sel_c8_1_ff[26]), // Inval
3934 .in2 (ext_ret_data_c8[26]),
3935 .sel2 (mux2_sel_c8_2_ff[26]) // Def Sel
3936 ) ;
3937
3938cl_dp1_aomux3_8x ff_cpx_data_ca_1_27
3939 (.out (oque_cpx_data_c8_muxout[27]),
3940 .in0 (tmp_cpx_data_ca_d1[27]),
3941 .sel0 (mux2_sel_c8_0_ff[27]), // Old data sel
3942 .in1 (ext_inval_data_c8[27]),
3943 .sel1 (mux2_sel_c8_1_ff[27]), // Inval
3944 .in2 (ext_ret_data_c8[27]),
3945 .sel2 (mux2_sel_c8_2_ff[27]) // Def Sel
3946 ) ;
3947
3948//--- 31:28 -------//
3949cl_dp1_aomux3_8x ff_cpx_data_ca_1_28
3950 (.out (oque_cpx_data_c8_muxout[28]),
3951 .in0 (tmp_cpx_data_ca_d1[28]),
3952 .sel0 (mux2_sel_c8_0_ff[28]), // Old data sel
3953 .in1 (ext_inval_data_c8[28]),
3954 .sel1 (mux2_sel_c8_1_ff[28]), // Inval
3955 .in2 (ext_ret_data_c8[28]),
3956 .sel2 (mux2_sel_c8_2_ff[28]) // Def Sel
3957 ) ;
3958
3959cl_dp1_aomux3_8x ff_cpx_data_ca_1_29
3960 (.out (oque_cpx_data_c8_muxout[29]),
3961 .in0 (tmp_cpx_data_ca_d1[29]),
3962 .sel0 (mux2_sel_c8_0_ff[29]), // Old data sel
3963 .in1 (ext_inval_data_c8[29]),
3964 .sel1 (mux2_sel_c8_1_ff[29]), // Inval
3965 .in2 (ext_ret_data_c8[29]),
3966 .sel2 (mux2_sel_c8_2_ff[29]) // Def Sel
3967 ) ;
3968
3969cl_dp1_aomux3_8x ff_cpx_data_ca_1_30
3970 (.out (oque_cpx_data_c8_muxout[30]),
3971 .in0 (tmp_cpx_data_ca_d1[30]),
3972 .sel0 (mux2_sel_c8_0_ff[30]), // Old data sel
3973 .in1 (ext_inval_data_c8[30]),
3974 .sel1 (mux2_sel_c8_1_ff[30]), // Inval
3975 .in2 (ext_ret_data_c8[30]),
3976 .sel2 (mux2_sel_c8_2_ff[30]) // Def Sel
3977 ) ;
3978
3979cl_dp1_aomux3_8x ff_cpx_data_ca_1_31
3980 (.out (oque_cpx_data_c8_muxout[31]),
3981 .in0 (tmp_cpx_data_ca_d1[31]),
3982 .sel0 (mux2_sel_c8_0_ff[31]), // Old data sel
3983 .in1 (ext_inval_data_c8[31]),
3984 .sel1 (mux2_sel_c8_1_ff[31]), // Inval
3985 .in2 (ext_ret_data_c8[31]),
3986 .sel2 (mux2_sel_c8_2_ff[31]) // Def Sel
3987 ) ;
3988
3989//--- 35:32 -------//
3990cl_dp1_aomux3_8x ff_cpx_data_ca_1_32
3991 (.out (oque_cpx_data_c8_muxout[32]),
3992 .in0 (tmp_cpx_data_ca_d1[32]),
3993 .sel0 (mux2_sel_c8_0_ff[32]), // Old data sel
3994 .in1 (ext_inval_data_c8[32]),
3995 .sel1 (mux2_sel_c8_1_ff[32]), // Inval
3996 .in2 (ext_ret_data_c8[32]),
3997 .sel2 (mux2_sel_c8_2_ff[32]) // Def Sel
3998 ) ;
3999
4000cl_dp1_aomux3_8x ff_cpx_data_ca_1_33
4001 (.out (oque_cpx_data_c8_muxout[33]),
4002 .in0 (tmp_cpx_data_ca_d1[33]),
4003 .sel0 (mux2_sel_c8_0_ff[33]), // Old data sel
4004 .in1 (ext_inval_data_c8[33]),
4005 .sel1 (mux2_sel_c8_1_ff[33]), // Inval
4006 .in2 (ext_ret_data_c8[33]),
4007 .sel2 (mux2_sel_c8_2_ff[33]) // Def Sel
4008 ) ;
4009
4010cl_dp1_aomux3_8x ff_cpx_data_ca_1_34
4011 (.out (oque_cpx_data_c8_muxout[34]),
4012 .in0 (tmp_cpx_data_ca_d1[34]),
4013 .sel0 (mux2_sel_c8_0_ff[34]), // Old data sel
4014 .in1 (ext_inval_data_c8[34]),
4015 .sel1 (mux2_sel_c8_1_ff[34]), // Inval
4016 .in2 (ext_ret_data_c8[34]),
4017 .sel2 (mux2_sel_c8_2_ff[34]) // Def Sel
4018 ) ;
4019
4020cl_dp1_aomux3_8x ff_cpx_data_ca_1_35
4021 (.out (oque_cpx_data_c8_muxout[35]),
4022 .in0 (tmp_cpx_data_ca_d1[35]),
4023 .sel0 (mux2_sel_c8_0_ff[35]), // Old data sel
4024 .in1 (ext_inval_data_c8[35]),
4025 .sel1 (mux2_sel_c8_1_ff[35]), // Inval
4026 .in2 (ext_ret_data_c8[35]),
4027 .sel2 (mux2_sel_c8_2_ff[35]) // Def Sel
4028 ) ;
4029
4030cl_dp1_aomux3_8x ff_cpx_data_ca_1_36
4031 (.out (oque_cpx_data_c8_muxout[36]),
4032 .in0 (tmp_cpx_data_ca_d1[36]),
4033 .sel0 (mux2_sel_c8_0_ff[36]), // Old data sel
4034 .in1 (ext_inval_data_c8[36]),
4035 .sel1 (mux2_sel_c8_1_ff[36]), // Inval
4036 .in2 (ext_ret_data_c8[36]),
4037 .sel2 (mux2_sel_c8_2_ff[36]) // Def Sel
4038 ) ;
4039
4040cl_dp1_aomux3_8x ff_cpx_data_ca_1_37
4041 (.out (oque_cpx_data_c8_muxout[37]),
4042 .in0 (tmp_cpx_data_ca_d1[37]),
4043 .sel0 (mux2_sel_c8_0_ff[37]), // Old data sel
4044 .in1 (ext_inval_data_c8[37]),
4045 .sel1 (mux2_sel_c8_1_ff[37]), // Inval
4046 .in2 (ext_ret_data_c8[37]),
4047 .sel2 (mux2_sel_c8_2_ff[37]) // Def Sel
4048 ) ;
4049
4050///////////////////////////////////////////////////////////////////////////////////////////////
4051//----------------------------------------------------------------------------------------
4052
4053l2t_oque_dp_buff_macro__dbuff_16x__stack_38r__width_38 buff1_oque_cpx_data_c8
4054 (
4055 .dout (oque_cpx_data_c8_buff[37:0]),
4056 .din (oque_cpx_data_c8[37:0])
4057 );
4058
4059
4060 l2t_oque_dp_buff_macro__dbuff_16x__stack_36r__width_36 buff2_oque_cpx_data_c8
4061 (
4062 .dout (oque_cpx_data_c8_buff[73:38]),
4063 .din (oque_cpx_data_c8[73:38])
4064 );
4065
4066 l2t_oque_dp_buff_macro__dbuff_16x__stack_36r__width_36 buff3_oque_cpx_data_c8
4067 (
4068 .dout (oque_cpx_data_c8_buff[109:74]),
4069 .din (oque_cpx_data_c8[109:74])
4070 );
4071
4072 l2t_oque_dp_buff_macro__dbuff_16x__stack_36r__width_36 buff4_oque_cpx_data_c8
4073 (
4074 .dout (oque_cpx_data_c8_buff[145:110]),
4075 .din (oque_cpx_data_c8[145:110])
4076 );
4077
4078//-----------------------------------------------------------------------------
4079//-----------------------------------------------------------------------------
4080
4081
4082l2t_oque_dp_inv_macro__dinv_48x__stack_38r__width_38 inv1_oque_cpx_data_c8
4083 (
4084 .dout (oque_cpx_data_c8[37:0]),
4085 .din (oque_cpx_data_c8_muxout[37:0])
4086 );
4087
4088
4089 l2t_oque_dp_inv_macro__dinv_48x__stack_36r__width_36 inv2_oque_cpx_data_c8
4090 (
4091 .dout (oque_cpx_data_c8[73:38]),
4092 .din (oque_cpx_data_c8_muxout[73:38])
4093 );
4094
4095 l2t_oque_dp_inv_macro__dinv_48x__stack_36r__width_36 inv3_oque_cpx_data_c8
4096 (
4097 .dout (oque_cpx_data_c8[109:74]),
4098 .din (oque_cpx_data_c8_muxout[109:74])
4099 );
4100
4101 l2t_oque_dp_inv_macro__dinv_48x__stack_36r__width_36 inv4_oque_cpx_data_c8
4102 (
4103 .dout (oque_cpx_data_c8[145:110]),
4104 .din (oque_cpx_data_c8_muxout[145:110])
4105 );
4106
4107// oque_cpx_data_c8
4108
4109// /
4110// /mux_macro ff_cpx_data_ca_1 (width=36,ports=3,mux=pgnpe,dmux=32x,stack=36r)
4111// / (.dout (oque_cpx_data_c8_muxout[146-1:110]),
4112// / .din0 (tmp_cpx_data_ca_d1[146-1:110]),
4113// /// .din0 (tmp_cpx_data_ca[146-1:110]),
4114// / .sel0 (mux2_sel_c8[0]), // Old data sel
4115// / .din1 ({oque_oq_array_data_in[145:134], ext_inval_data_c8[146-13:110]}),
4116// / .sel1 (mux2_sel_c8[1]), // Inval
4117// / .din2 ({oque_oq_array_data_in[145:134], ext_ret_data_c8[146-13:110]}),
4118// / .sel2 (mux2_sel_c8[2]) // Def Sel
4119// / ) ;
4120// /
4121// /mux_macro ff_cpx_data_ca_2 (width=36,ports=3,mux=pgnpe,dmux=32x,stack=36r)
4122// / (.dout (oque_cpx_data_c8_muxout[109:74]),
4123// /// .din0 (tmp_cpx_data_ca[109:74]),
4124// / .din0 (tmp_cpx_data_ca_d1[109:74]),
4125// / .sel0 (mux2_sel_c8[0]), // Old data sel
4126// / .din1 (ext_inval_data_c8[109:74]),
4127// / .sel1 (mux2_sel_c8[1]), // Inval
4128// / .din2 (ext_ret_data_c8[109:74]),
4129// / .sel2 (mux2_sel_c8[2]) // Def Sel
4130// / ) ;
4131// /
4132// /mux_macro ff_cpx_data_ca_3 (width=36,ports=3,mux=pgnpe,dmux=32x,stack=36r)
4133// / (.dout (oque_cpx_data_c8_muxout[73:38]),
4134// /// .din0 (tmp_cpx_data_ca[73:38]),
4135// / .din0 (tmp_cpx_data_ca_d1[73:38]),
4136// / .sel0 (mux2_sel_c8[0]), // Old data sel
4137// / .din1 (ext_inval_data_c8[73:38]),
4138// / .sel1 (mux2_sel_c8[1]), // Inval
4139// / .din2 (ext_ret_data_c8[73:38]),
4140// / .sel2 (mux2_sel_c8[2]) // Def Sel
4141// / ) ;
4142// /
4143// /mux_macro ff_cpx_data_ca_4 (width=38,ports=3,mux=pgnpe,dmux=32x,stack=38r)
4144// / (.dout (oque_cpx_data_c8_muxout[37:0]),
4145// /// .din0 (tmp_cpx_data_ca[37:0]),
4146// / .din0 (tmp_cpx_data_ca_d1[37:0]),
4147// / .sel0 (mux2_sel_c8[0]), // Old data sel
4148// / .din1 (ext_inval_data_c8[37:0]),
4149// / .sel1 (mux2_sel_c8[1]), // Inval
4150// / .din2 (ext_ret_data_c8[37:0]),
4151// / .sel2 (mux2_sel_c8[2]) // Def Sel
4152// / ) ;
4153// /
4154//
4155// assign l2t_cpx_data_ca = oque_cpx_data_c8_muxout ;
4156
4157assign l2t_cpx_data_ca = oque_cpx_data_c8 ;
4158
4159
4160//
4161//assign oqu_dispatched_err_pkt = (l2t_cpx_data_ca[145:141] == 5'b11100);
4162//
4163//
4164//cmp_macro cmp_oqu_dispatched_err_pkt (width=8,dcmp=8x)
4165// (
4166// .dout (oqu_dispatched_err_pkt),
4167// .din0 ({3'b0,oque_cpx_data_c8_buff[145:141]}),
4168// .din1 (8'b00011100)
4169// );
4170//
4171
4172
4173// fixscan start:
4174assign ff_MERGED_scanin = scan_in ;
4175assign ff_decc_data_0_scanin = ff_MERGED_scanout ;
4176assign ff_decc_data_1_scanin = ff_decc_data_0_scanout ;
4177assign ff_decc_data_2_scanin = ff_decc_data_1_scanout ;
4178assign ff_decc_data_3_scanin = ff_decc_data_2_scanout ;
4179assign ext_inval_data_0_scanin = ff_decc_data_3_scanout ;
4180assign ext_inval_data_1_scanin = ext_inval_data_0_scanout ;
4181assign ext_inval_data_2_scanin = ext_inval_data_1_scanout ;
4182assign ext_inval_data_3_scanin = ext_inval_data_2_scanout ;
4183assign oque_oq_array_data_in_inv_ff_scanin = ext_inval_data_3_scanout ;
4184assign ff_data_rtn_d1_1_scanin = oque_oq_array_data_in_inv_ff_scanout;
4185assign ff_data_rtn_d1_2_scanin = ff_data_rtn_d1_1_scanout ;
4186assign ff_data_rtn_d1_3_scanin = ff_data_rtn_d1_2_scanout ;
4187assign ff_data_rtn_d1_4_scanin = ff_data_rtn_d1_3_scanout ;
4188assign ff_mbist_oqarray_dout_scanin = ff_data_rtn_d1_4_scanout ;
4189assign ff_mbist_flop_scanin = ff_mbist_oqarray_dout_scanout;
4190assign ff_mbist_flop1_scanin = ff_mbist_flop_scanout ;
4191assign ff_oqarray_rd_en_scanin = ff_mbist_flop1_scanout ;
4192assign ff_tmp_cpx_data_ca_1_scanin = ff_oqarray_rd_en_scanout ;
4193assign ff_tmp_cpx_data_ca_2_scanin = ff_tmp_cpx_data_ca_1_scanout;
4194assign ff_tmp_cpx_data_ca_3_scanin = ff_tmp_cpx_data_ca_2_scanout;
4195assign ff_tmp_cpx_data_ca_4_scanin = ff_tmp_cpx_data_ca_3_scanout;
4196assign ff_mux2_sel_c8_0_scanin = ff_tmp_cpx_data_ca_4_scanout;
4197assign ff_mux2_sel_c8_1_scanin = ff_mux2_sel_c8_0_scanout ;
4198assign ff_mux2_sel_c8_2_scanin = ff_mux2_sel_c8_1_scanout ;
4199assign scan_out = ff_mux2_sel_c8_2_scanout ;
4200// fixscan end:
4201endmodule
4202
4203
4204
4205//
4206// or macro for ports = 2,3
4207//
4208//
4209
4210
4211
4212
4213
4214module l2t_oque_dp_or_macro__width_1 (
4215 din0,
4216 din1,
4217 dout);
4218 input [0:0] din0;
4219 input [0:0] din1;
4220 output [0:0] dout;
4221
4222
4223
4224
4225
4226
4227or2 #(1) d0_0 (
4228.in0(din0[0:0]),
4229.in1(din1[0:0]),
4230.out(dout[0:0])
4231);
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241endmodule
4242
4243
4244
4245
4246
4247//
4248// invert macro
4249//
4250//
4251
4252
4253
4254
4255
4256module l2t_oque_dp_inv_macro__width_1 (
4257 din,
4258 dout);
4259 input [0:0] din;
4260 output [0:0] dout;
4261
4262
4263
4264
4265
4266
4267inv #(1) d0_0 (
4268.in(din[0:0]),
4269.out(dout[0:0])
4270);
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280endmodule
4281
4282
4283
4284
4285
4286//
4287// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
4288//
4289//
4290
4291
4292
4293
4294
4295module l2t_oque_dp_cmp_macro__width_8 (
4296 din0,
4297 din1,
4298 dout);
4299 input [7:0] din0;
4300 input [7:0] din1;
4301 output dout;
4302
4303
4304
4305
4306
4307
4308cmp #(8) m0_0 (
4309.in0(din0[7:0]),
4310.in1(din1[7:0]),
4311.out(dout)
4312);
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323endmodule
4324
4325
4326
4327
4328
4329//
4330// and macro for ports = 2,3,4
4331//
4332//
4333
4334
4335
4336
4337
4338module l2t_oque_dp_and_macro__width_1 (
4339 din0,
4340 din1,
4341 dout);
4342 input [0:0] din0;
4343 input [0:0] din1;
4344 output [0:0] dout;
4345
4346
4347
4348
4349
4350
4351and2 #(1) d0_0 (
4352.in0(din0[0:0]),
4353.in1(din1[0:0]),
4354.out(dout[0:0])
4355);
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365endmodule
4366
4367
4368
4369
4370
4371// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4372// also for pass-gate with decoder
4373
4374
4375
4376
4377
4378// any PARAMS parms go into naming of macro
4379
4380module l2t_oque_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_20r__width_20 (
4381 din0,
4382 sel0,
4383 din1,
4384 sel1,
4385 dout);
4386wire buffout0;
4387wire buffout1;
4388
4389 input [19:0] din0;
4390 input sel0;
4391 input [19:0] din1;
4392 input sel1;
4393 output [19:0] dout;
4394
4395
4396
4397
4398
4399cl_dp1_muxbuff2_8x c0_0 (
4400 .in0(sel0),
4401 .in1(sel1),
4402 .out0(buffout0),
4403 .out1(buffout1)
4404);
4405mux2s #(20) d0_0 (
4406 .sel0(buffout0),
4407 .sel1(buffout1),
4408 .in0(din0[19:0]),
4409 .in1(din1[19:0]),
4410.dout(dout[19:0])
4411);
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425endmodule
4426
4427
4428//
4429// buff macro
4430//
4431//
4432
4433
4434
4435
4436
4437module l2t_oque_dp_buff_macro__minbuff_1__stack_40r__width_5 (
4438 din,
4439 dout);
4440 input [4:0] din;
4441 output [4:0] dout;
4442
4443
4444
4445
4446
4447
4448buff #(5) d0_0 (
4449.in(din[4:0]),
4450.out(dout[4:0])
4451);
4452
4453
4454
4455
4456
4457
4458
4459
4460endmodule
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470// any PARAMS parms go into naming of macro
4471
4472module l2t_oque_dp_msff_macro__dmsff_32x__stack_40r__width_37 (
4473 din,
4474 clk,
4475 en,
4476 se,
4477 scan_in,
4478 siclk,
4479 soclk,
4480 pce_ov,
4481 stop,
4482 dout,
4483 scan_out);
4484wire l1clk;
4485wire siclk_out;
4486wire soclk_out;
4487wire [35:0] so;
4488
4489 input [36:0] din;
4490
4491
4492 input clk;
4493 input en;
4494 input se;
4495 input scan_in;
4496 input siclk;
4497 input soclk;
4498 input pce_ov;
4499 input stop;
4500
4501
4502
4503 output [36:0] dout;
4504
4505
4506 output scan_out;
4507
4508
4509
4510
4511cl_dp1_l1hdr_8x c0_0 (
4512.l2clk(clk),
4513.pce(en),
4514.aclk(siclk),
4515.bclk(soclk),
4516.l1clk(l1clk),
4517 .se(se),
4518 .pce_ov(pce_ov),
4519 .stop(stop),
4520 .siclk_out(siclk_out),
4521 .soclk_out(soclk_out)
4522);
4523dff #(37) d0_0 (
4524.l1clk(l1clk),
4525.siclk(siclk_out),
4526.soclk(soclk_out),
4527.d(din[36:0]),
4528.si({scan_in,so[35:0]}),
4529.so({so[35:0],scan_out}),
4530.q(dout[36:0])
4531);
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552endmodule
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4563// also for pass-gate with decoder
4564
4565
4566
4567
4568
4569// any PARAMS parms go into naming of macro
4570
4571module l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_3r__width_3 (
4572 din0,
4573 sel0,
4574 din1,
4575 sel1,
4576 dout);
4577wire buffout0;
4578wire buffout1;
4579
4580 input [2:0] din0;
4581 input sel0;
4582 input [2:0] din1;
4583 input sel1;
4584 output [2:0] dout;
4585
4586
4587
4588
4589
4590cl_dp1_muxbuff2_8x c0_0 (
4591 .in0(sel0),
4592 .in1(sel1),
4593 .out0(buffout0),
4594 .out1(buffout1)
4595);
4596mux2s #(3) d0_0 (
4597 .sel0(buffout0),
4598 .sel1(buffout1),
4599 .in0(din0[2:0]),
4600 .in1(din1[2:0]),
4601.dout(dout[2:0])
4602);
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616endmodule
4617
4618
4619// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4620// also for pass-gate with decoder
4621
4622
4623
4624
4625
4626// any PARAMS parms go into naming of macro
4627
4628module l2t_oque_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14r__width_14 (
4629 din0,
4630 sel0,
4631 din1,
4632 sel1,
4633 dout);
4634wire buffout0;
4635wire buffout1;
4636
4637 input [13:0] din0;
4638 input sel0;
4639 input [13:0] din1;
4640 input sel1;
4641 output [13:0] dout;
4642
4643
4644
4645
4646
4647cl_dp1_muxbuff2_8x c0_0 (
4648 .in0(sel0),
4649 .in1(sel1),
4650 .out0(buffout0),
4651 .out1(buffout1)
4652);
4653mux2s #(14) d0_0 (
4654 .sel0(buffout0),
4655 .sel1(buffout1),
4656 .in0(din0[13:0]),
4657 .in1(din1[13:0]),
4658.dout(dout[13:0])
4659);
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673endmodule
4674
4675
4676// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4677// also for pass-gate with decoder
4678
4679
4680
4681
4682
4683// any PARAMS parms go into naming of macro
4684
4685module l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_3__stack_3r__width_3 (
4686 din0,
4687 sel0,
4688 din1,
4689 sel1,
4690 din2,
4691 sel2,
4692 dout);
4693wire buffout0;
4694wire buffout1;
4695wire buffout2;
4696
4697 input [2:0] din0;
4698 input sel0;
4699 input [2:0] din1;
4700 input sel1;
4701 input [2:0] din2;
4702 input sel2;
4703 output [2:0] dout;
4704
4705
4706
4707
4708
4709cl_dp1_muxbuff3_8x c0_0 (
4710 .in0(sel0),
4711 .in1(sel1),
4712 .in2(sel2),
4713 .out0(buffout0),
4714 .out1(buffout1),
4715 .out2(buffout2)
4716);
4717mux3s #(3) d0_0 (
4718 .sel0(buffout0),
4719 .sel1(buffout1),
4720 .sel2(buffout2),
4721 .in0(din0[2:0]),
4722 .in1(din1[2:0]),
4723 .in2(din2[2:0]),
4724.dout(dout[2:0])
4725);
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739endmodule
4740
4741
4742// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4743// also for pass-gate with decoder
4744
4745
4746
4747
4748
4749// any PARAMS parms go into naming of macro
4750
4751module l2t_oque_dp_mux_macro__mux_pgpe__ports_4__stack_39r__width_39 (
4752 din0,
4753 din1,
4754 din2,
4755 din3,
4756 sel0,
4757 sel1,
4758 sel2,
4759 muxtst,
4760 test,
4761 dout);
4762wire psel0;
4763wire psel1;
4764wire psel2;
4765wire psel3;
4766
4767 input [38:0] din0;
4768 input [38:0] din1;
4769 input [38:0] din2;
4770 input [38:0] din3;
4771 input sel0;
4772 input sel1;
4773 input sel2;
4774 input muxtst;
4775 input test;
4776 output [38:0] dout;
4777
4778
4779
4780
4781
4782cl_dp1_penc4_8x c0_0 (
4783 .sel0(sel0),
4784 .sel1(sel1),
4785 .sel2(sel2),
4786 .psel0(psel0),
4787 .psel1(psel1),
4788 .psel2(psel2),
4789 .psel3(psel3),
4790 .test(test)
4791);
4792
4793mux4 #(39) d0_0 (
4794 .sel0(psel0),
4795 .sel1(psel1),
4796 .sel2(psel2),
4797 .sel3(psel3),
4798 .in0(din0[38:0]),
4799 .in1(din1[38:0]),
4800 .in2(din2[38:0]),
4801 .in3(din3[38:0]),
4802.dout(dout[38:0]),
4803 .muxtst(muxtst)
4804);
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818endmodule
4819
4820
4821//
4822// invert macro
4823//
4824//
4825
4826
4827
4828
4829
4830module l2t_oque_dp_inv_macro__dinv_16x__width_2 (
4831 din,
4832 dout);
4833 input [1:0] din;
4834 output [1:0] dout;
4835
4836
4837
4838
4839
4840
4841inv #(2) d0_0 (
4842.in(din[1:0]),
4843.out(dout[1:0])
4844);
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854endmodule
4855
4856
4857
4858
4859
4860//
4861// and macro for ports = 2,3,4
4862//
4863//
4864
4865
4866
4867
4868
4869module l2t_oque_dp_and_macro__dinv_32x__dnand_16x__ports_3__width_2 (
4870 din0,
4871 din1,
4872 din2,
4873 dout);
4874 input [1:0] din0;
4875 input [1:0] din1;
4876 input [1:0] din2;
4877 output [1:0] dout;
4878
4879
4880
4881
4882
4883
4884and3 #(2) d0_0 (
4885.in0(din0[1:0]),
4886.in1(din1[1:0]),
4887.in2(din2[1:0]),
4888.out(dout[1:0])
4889);
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899endmodule
4900
4901
4902
4903
4904
4905// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4906// also for pass-gate with decoder
4907
4908
4909
4910
4911
4912// any PARAMS parms go into naming of macro
4913
4914module l2t_oque_dp_mux_macro__dmux_32x__mux_pgnpe__ports_4__stack_32r__width_32 (
4915 din0,
4916 sel0,
4917 din1,
4918 sel1,
4919 din2,
4920 sel2,
4921 din3,
4922 sel3,
4923 muxtst,
4924 dout);
4925wire buffout0;
4926wire buffout1;
4927wire buffout2;
4928wire buffout3;
4929
4930 input [31:0] din0;
4931 input sel0;
4932 input [31:0] din1;
4933 input sel1;
4934 input [31:0] din2;
4935 input sel2;
4936 input [31:0] din3;
4937 input sel3;
4938 input muxtst;
4939 output [31:0] dout;
4940
4941
4942
4943
4944
4945cl_dp1_muxbuff4_8x c0_0 (
4946 .in0(sel0),
4947 .in1(sel1),
4948 .in2(sel2),
4949 .in3(sel3),
4950 .out0(buffout0),
4951 .out1(buffout1),
4952 .out2(buffout2),
4953 .out3(buffout3)
4954);
4955mux4 #(32) d0_0 (
4956 .sel0(buffout0),
4957 .sel1(buffout1),
4958 .sel2(buffout2),
4959 .sel3(buffout3),
4960 .in0(din0[31:0]),
4961 .in1(din1[31:0]),
4962 .in2(din2[31:0]),
4963 .in3(din3[31:0]),
4964.dout(dout[31:0]),
4965 .muxtst(muxtst)
4966);
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980endmodule
4981
4982
4983// general mux macro for pass-gate and and-or muxes with/wout priority encoders
4984// also for pass-gate with decoder
4985
4986
4987
4988
4989
4990// any PARAMS parms go into naming of macro
4991
4992module l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_48r__width_48 (
4993 din0,
4994 din1,
4995 sel0,
4996 dout);
4997wire psel0_unused;
4998wire psel1;
4999
5000 input [47:0] din0;
5001 input [47:0] din1;
5002 input sel0;
5003 output [47:0] dout;
5004
5005
5006
5007
5008
5009cl_dp1_penc2_8x c0_0 (
5010 .sel0(sel0),
5011 .psel0(psel0_unused),
5012 .psel1(psel1)
5013);
5014
5015mux2e #(48) d0_0 (
5016 .sel(psel1),
5017 .in0(din0[47:0]),
5018 .in1(din1[47:0]),
5019.dout(dout[47:0])
5020);
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034endmodule
5035
5036
5037
5038
5039
5040
5041// any PARAMS parms go into naming of macro
5042
5043module l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_24 (
5044 din,
5045 clk,
5046 en,
5047 se,
5048 scan_in,
5049 siclk,
5050 soclk,
5051 pce_ov,
5052 stop,
5053 dout_l,
5054 scan_out);
5055wire l1clk;
5056wire siclk_out;
5057wire soclk_out;
5058wire [22:0] so;
5059
5060 input [23:0] din;
5061
5062
5063 input clk;
5064 input en;
5065 input se;
5066 input scan_in;
5067 input siclk;
5068 input soclk;
5069 input pce_ov;
5070 input stop;
5071
5072
5073
5074 output [23:0] dout_l;
5075
5076
5077 output scan_out;
5078
5079
5080
5081
5082cl_dp1_l1hdr_8x c0_0 (
5083.l2clk(clk),
5084.pce(en),
5085.aclk(siclk),
5086.bclk(soclk),
5087.l1clk(l1clk),
5088 .se(se),
5089 .pce_ov(pce_ov),
5090 .stop(stop),
5091 .siclk_out(siclk_out),
5092 .soclk_out(soclk_out)
5093);
5094msffi_dp #(24) d0_0 (
5095.l1clk(l1clk),
5096.siclk(siclk_out),
5097.soclk(soclk_out),
5098.d(din[23:0]),
5099.si({scan_in,so[22:0]}),
5100.so({so[22:0],scan_out}),
5101.q_l(dout_l[23:0])
5102);
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122endmodule
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136// any PARAMS parms go into naming of macro
5137
5138module l2t_oque_dp_msffi_macro__dmsffi_16x__stack_36r__width_36 (
5139 din,
5140 clk,
5141 en,
5142 se,
5143 scan_in,
5144 siclk,
5145 soclk,
5146 pce_ov,
5147 stop,
5148 dout_l,
5149 scan_out);
5150wire l1clk;
5151wire siclk_out;
5152wire soclk_out;
5153wire [34:0] so;
5154
5155 input [35:0] din;
5156
5157
5158 input clk;
5159 input en;
5160 input se;
5161 input scan_in;
5162 input siclk;
5163 input soclk;
5164 input pce_ov;
5165 input stop;
5166
5167
5168
5169 output [35:0] dout_l;
5170
5171
5172 output scan_out;
5173
5174
5175
5176
5177cl_dp1_l1hdr_8x c0_0 (
5178.l2clk(clk),
5179.pce(en),
5180.aclk(siclk),
5181.bclk(soclk),
5182.l1clk(l1clk),
5183 .se(se),
5184 .pce_ov(pce_ov),
5185 .stop(stop),
5186 .siclk_out(siclk_out),
5187 .soclk_out(soclk_out)
5188);
5189msffi_dp #(36) d0_0 (
5190.l1clk(l1clk),
5191.siclk(siclk_out),
5192.soclk(soclk_out),
5193.d(din[35:0]),
5194.si({scan_in,so[34:0]}),
5195.so({so[34:0],scan_out}),
5196.q_l(dout_l[35:0])
5197);
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217endmodule
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231// any PARAMS parms go into naming of macro
5232
5233module l2t_oque_dp_msffi_macro__dmsffi_16x__stack_38r__width_38 (
5234 din,
5235 clk,
5236 en,
5237 se,
5238 scan_in,
5239 siclk,
5240 soclk,
5241 pce_ov,
5242 stop,
5243 dout_l,
5244 scan_out);
5245wire l1clk;
5246wire siclk_out;
5247wire soclk_out;
5248wire [36:0] so;
5249
5250 input [37:0] din;
5251
5252
5253 input clk;
5254 input en;
5255 input se;
5256 input scan_in;
5257 input siclk;
5258 input soclk;
5259 input pce_ov;
5260 input stop;
5261
5262
5263
5264 output [37:0] dout_l;
5265
5266
5267 output scan_out;
5268
5269
5270
5271
5272cl_dp1_l1hdr_8x c0_0 (
5273.l2clk(clk),
5274.pce(en),
5275.aclk(siclk),
5276.bclk(soclk),
5277.l1clk(l1clk),
5278 .se(se),
5279 .pce_ov(pce_ov),
5280 .stop(stop),
5281 .siclk_out(siclk_out),
5282 .soclk_out(soclk_out)
5283);
5284msffi_dp #(38) d0_0 (
5285.l1clk(l1clk),
5286.siclk(siclk_out),
5287.soclk(soclk_out),
5288.d(din[37:0]),
5289.si({scan_in,so[36:0]}),
5290.so({so[36:0],scan_out}),
5291.q_l(dout_l[37:0])
5292);
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312endmodule
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326// any PARAMS parms go into naming of macro
5327
5328module l2t_oque_dp_msffi_macro__dmsffi_16x__stack_34r__width_24 (
5329 din,
5330 clk,
5331 en,
5332 se,
5333 scan_in,
5334 siclk,
5335 soclk,
5336 pce_ov,
5337 stop,
5338 dout_l,
5339 scan_out);
5340wire l1clk;
5341wire siclk_out;
5342wire soclk_out;
5343wire [22:0] so;
5344
5345 input [23:0] din;
5346
5347
5348 input clk;
5349 input en;
5350 input se;
5351 input scan_in;
5352 input siclk;
5353 input soclk;
5354 input pce_ov;
5355 input stop;
5356
5357
5358
5359 output [23:0] dout_l;
5360
5361
5362 output scan_out;
5363
5364
5365
5366
5367cl_dp1_l1hdr_8x c0_0 (
5368.l2clk(clk),
5369.pce(en),
5370.aclk(siclk),
5371.bclk(soclk),
5372.l1clk(l1clk),
5373 .se(se),
5374 .pce_ov(pce_ov),
5375 .stop(stop),
5376 .siclk_out(siclk_out),
5377 .soclk_out(soclk_out)
5378);
5379msffi_dp #(24) d0_0 (
5380.l1clk(l1clk),
5381.siclk(siclk_out),
5382.soclk(soclk_out),
5383.d(din[23:0]),
5384.si({scan_in,so[22:0]}),
5385.so({so[22:0],scan_out}),
5386.q_l(dout_l[23:0])
5387);
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407endmodule
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421// any PARAMS parms go into naming of macro
5422
5423module l2t_oque_dp_msffi_macro__dmsffi_16x__stack_12r__width_11 (
5424 din,
5425 clk,
5426 en,
5427 se,
5428 scan_in,
5429 siclk,
5430 soclk,
5431 pce_ov,
5432 stop,
5433 dout_l,
5434 scan_out);
5435wire l1clk;
5436wire siclk_out;
5437wire soclk_out;
5438wire [9:0] so;
5439
5440 input [10:0] din;
5441
5442
5443 input clk;
5444 input en;
5445 input se;
5446 input scan_in;
5447 input siclk;
5448 input soclk;
5449 input pce_ov;
5450 input stop;
5451
5452
5453
5454 output [10:0] dout_l;
5455
5456
5457 output scan_out;
5458
5459
5460
5461
5462cl_dp1_l1hdr_8x c0_0 (
5463.l2clk(clk),
5464.pce(en),
5465.aclk(siclk),
5466.bclk(soclk),
5467.l1clk(l1clk),
5468 .se(se),
5469 .pce_ov(pce_ov),
5470 .stop(stop),
5471 .siclk_out(siclk_out),
5472 .soclk_out(soclk_out)
5473);
5474msffi_dp #(11) d0_0 (
5475.l1clk(l1clk),
5476.siclk(siclk_out),
5477.soclk(soclk_out),
5478.d(din[10:0]),
5479.si({scan_in,so[9:0]}),
5480.so({so[9:0],scan_out}),
5481.q_l(dout_l[10:0])
5482);
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502endmodule
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5513// also for pass-gate with decoder
5514
5515
5516
5517
5518
5519// any PARAMS parms go into naming of macro
5520
5521module l2t_oque_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2r__width_2 (
5522 din0,
5523 sel0,
5524 din1,
5525 sel1,
5526 dout);
5527wire buffout0;
5528wire buffout1;
5529
5530 input [1:0] din0;
5531 input sel0;
5532 input [1:0] din1;
5533 input sel1;
5534 output [1:0] dout;
5535
5536
5537
5538
5539
5540cl_dp1_muxbuff2_8x c0_0 (
5541 .in0(sel0),
5542 .in1(sel1),
5543 .out0(buffout0),
5544 .out1(buffout1)
5545);
5546mux2s #(2) d0_0 (
5547 .sel0(buffout0),
5548 .sel1(buffout1),
5549 .in0(din0[1:0]),
5550 .in1(din1[1:0]),
5551.dout(dout[1:0])
5552);
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566endmodule
5567
5568
5569//
5570// invert macro
5571//
5572//
5573
5574
5575
5576
5577
5578module l2t_oque_dp_inv_macro__dinv_32x__width_1 (
5579 din,
5580 dout);
5581 input [0:0] din;
5582 output [0:0] dout;
5583
5584
5585
5586
5587
5588
5589inv #(1) d0_0 (
5590.in(din[0:0]),
5591.out(dout[0:0])
5592);
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602endmodule
5603
5604
5605
5606
5607
5608// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5609// also for pass-gate with decoder
5610
5611
5612
5613
5614
5615// any PARAMS parms go into naming of macro
5616
5617module l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_36r__width_36 (
5618 din0,
5619 sel0,
5620 din1,
5621 sel1,
5622 dout);
5623wire buffout0;
5624wire buffout1;
5625
5626 input [35:0] din0;
5627 input sel0;
5628 input [35:0] din1;
5629 input sel1;
5630 output [35:0] dout;
5631
5632
5633
5634
5635
5636cl_dp1_muxbuff2_8x c0_0 (
5637 .in0(sel0),
5638 .in1(sel1),
5639 .out0(buffout0),
5640 .out1(buffout1)
5641);
5642mux2s #(36) d0_0 (
5643 .sel0(buffout0),
5644 .sel1(buffout1),
5645 .in0(din0[35:0]),
5646 .in1(din1[35:0]),
5647.dout(dout[35:0])
5648);
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662endmodule
5663
5664
5665// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5666// also for pass-gate with decoder
5667
5668
5669
5670
5671
5672// any PARAMS parms go into naming of macro
5673
5674module l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__stack_26r__width_26 (
5675 din0,
5676 sel0,
5677 din1,
5678 sel1,
5679 dout);
5680wire buffout0;
5681wire buffout1;
5682
5683 input [25:0] din0;
5684 input sel0;
5685 input [25:0] din1;
5686 input sel1;
5687 output [25:0] dout;
5688
5689
5690
5691
5692
5693cl_dp1_muxbuff2_8x c0_0 (
5694 .in0(sel0),
5695 .in1(sel1),
5696 .out0(buffout0),
5697 .out1(buffout1)
5698);
5699mux2s #(26) d0_0 (
5700 .sel0(buffout0),
5701 .sel1(buffout1),
5702 .in0(din0[25:0]),
5703 .in1(din1[25:0]),
5704.dout(dout[25:0])
5705);
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719endmodule
5720
5721
5722//
5723// invert macro
5724//
5725//
5726
5727
5728
5729
5730
5731module l2t_oque_dp_inv_macro__stack_38r__width_38 (
5732 din,
5733 dout);
5734 input [37:0] din;
5735 output [37:0] dout;
5736
5737
5738
5739
5740
5741
5742inv #(38) d0_0 (
5743.in(din[37:0]),
5744.out(dout[37:0])
5745);
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755endmodule
5756
5757
5758
5759
5760
5761//
5762// invert macro
5763//
5764//
5765
5766
5767
5768
5769
5770module l2t_oque_dp_inv_macro__stack_36r__width_36 (
5771 din,
5772 dout);
5773 input [35:0] din;
5774 output [35:0] dout;
5775
5776
5777
5778
5779
5780
5781inv #(36) d0_0 (
5782.in(din[35:0]),
5783.out(dout[35:0])
5784);
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794endmodule
5795
5796
5797
5798
5799
5800//
5801// invert macro
5802//
5803//
5804
5805
5806
5807
5808
5809module l2t_oque_dp_inv_macro__stack_36r__width_35 (
5810 din,
5811 dout);
5812 input [34:0] din;
5813 output [34:0] dout;
5814
5815
5816
5817
5818
5819
5820inv #(35) d0_0 (
5821.in(din[34:0]),
5822.out(dout[34:0])
5823);
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833endmodule
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843// any PARAMS parms go into naming of macro
5844
5845module l2t_oque_dp_msff_macro__stack_36r__width_36 (
5846 din,
5847 clk,
5848 en,
5849 se,
5850 scan_in,
5851 siclk,
5852 soclk,
5853 pce_ov,
5854 stop,
5855 dout,
5856 scan_out);
5857wire l1clk;
5858wire siclk_out;
5859wire soclk_out;
5860wire [34:0] so;
5861
5862 input [35:0] din;
5863
5864
5865 input clk;
5866 input en;
5867 input se;
5868 input scan_in;
5869 input siclk;
5870 input soclk;
5871 input pce_ov;
5872 input stop;
5873
5874
5875
5876 output [35:0] dout;
5877
5878
5879 output scan_out;
5880
5881
5882
5883
5884cl_dp1_l1hdr_8x c0_0 (
5885.l2clk(clk),
5886.pce(en),
5887.aclk(siclk),
5888.bclk(soclk),
5889.l1clk(l1clk),
5890 .se(se),
5891 .pce_ov(pce_ov),
5892 .stop(stop),
5893 .siclk_out(siclk_out),
5894 .soclk_out(soclk_out)
5895);
5896dff #(36) d0_0 (
5897.l1clk(l1clk),
5898.siclk(siclk_out),
5899.soclk(soclk_out),
5900.d(din[35:0]),
5901.si({scan_in,so[34:0]}),
5902.so({so[34:0],scan_out}),
5903.q(dout[35:0])
5904);
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925endmodule
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939// any PARAMS parms go into naming of macro
5940
5941module l2t_oque_dp_msff_macro__stack_38r__width_38 (
5942 din,
5943 clk,
5944 en,
5945 se,
5946 scan_in,
5947 siclk,
5948 soclk,
5949 pce_ov,
5950 stop,
5951 dout,
5952 scan_out);
5953wire l1clk;
5954wire siclk_out;
5955wire soclk_out;
5956wire [36:0] so;
5957
5958 input [37:0] din;
5959
5960
5961 input clk;
5962 input en;
5963 input se;
5964 input scan_in;
5965 input siclk;
5966 input soclk;
5967 input pce_ov;
5968 input stop;
5969
5970
5971
5972 output [37:0] dout;
5973
5974
5975 output scan_out;
5976
5977
5978
5979
5980cl_dp1_l1hdr_8x c0_0 (
5981.l2clk(clk),
5982.pce(en),
5983.aclk(siclk),
5984.bclk(soclk),
5985.l1clk(l1clk),
5986 .se(se),
5987 .pce_ov(pce_ov),
5988 .stop(stop),
5989 .siclk_out(siclk_out),
5990 .soclk_out(soclk_out)
5991);
5992dff #(38) d0_0 (
5993.l1clk(l1clk),
5994.siclk(siclk_out),
5995.soclk(soclk_out),
5996.d(din[37:0]),
5997.si({scan_in,so[36:0]}),
5998.so({so[36:0],scan_out}),
5999.q(dout[37:0])
6000);
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021endmodule
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035// any PARAMS parms go into naming of macro
6036
6037module l2t_oque_dp_msff_macro__stack_44r__width_44 (
6038 din,
6039 clk,
6040 en,
6041 se,
6042 scan_in,
6043 siclk,
6044 soclk,
6045 pce_ov,
6046 stop,
6047 dout,
6048 scan_out);
6049wire l1clk;
6050wire siclk_out;
6051wire soclk_out;
6052wire [42:0] so;
6053
6054 input [43:0] din;
6055
6056
6057 input clk;
6058 input en;
6059 input se;
6060 input scan_in;
6061 input siclk;
6062 input soclk;
6063 input pce_ov;
6064 input stop;
6065
6066
6067
6068 output [43:0] dout;
6069
6070
6071 output scan_out;
6072
6073
6074
6075
6076cl_dp1_l1hdr_8x c0_0 (
6077.l2clk(clk),
6078.pce(en),
6079.aclk(siclk),
6080.bclk(soclk),
6081.l1clk(l1clk),
6082 .se(se),
6083 .pce_ov(pce_ov),
6084 .stop(stop),
6085 .siclk_out(siclk_out),
6086 .soclk_out(soclk_out)
6087);
6088dff #(44) d0_0 (
6089.l1clk(l1clk),
6090.siclk(siclk_out),
6091.soclk(soclk_out),
6092.d(din[43:0]),
6093.si({scan_in,so[42:0]}),
6094.so({so[42:0],scan_out}),
6095.q(dout[43:0])
6096);
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117endmodule
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131// any PARAMS parms go into naming of macro
6132
6133module l2t_oque_dp_msff_macro__stack_42r__width_41 (
6134 din,
6135 clk,
6136 en,
6137 se,
6138 scan_in,
6139 siclk,
6140 soclk,
6141 pce_ov,
6142 stop,
6143 dout,
6144 scan_out);
6145wire l1clk;
6146wire siclk_out;
6147wire soclk_out;
6148wire [39:0] so;
6149
6150 input [40:0] din;
6151
6152
6153 input clk;
6154 input en;
6155 input se;
6156 input scan_in;
6157 input siclk;
6158 input soclk;
6159 input pce_ov;
6160 input stop;
6161
6162
6163
6164 output [40:0] dout;
6165
6166
6167 output scan_out;
6168
6169
6170
6171
6172cl_dp1_l1hdr_8x c0_0 (
6173.l2clk(clk),
6174.pce(en),
6175.aclk(siclk),
6176.bclk(soclk),
6177.l1clk(l1clk),
6178 .se(se),
6179 .pce_ov(pce_ov),
6180 .stop(stop),
6181 .siclk_out(siclk_out),
6182 .soclk_out(soclk_out)
6183);
6184dff #(41) d0_0 (
6185.l1clk(l1clk),
6186.siclk(siclk_out),
6187.soclk(soclk_out),
6188.d(din[40:0]),
6189.si({scan_in,so[39:0]}),
6190.so({so[39:0],scan_out}),
6191.q(dout[40:0])
6192);
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213endmodule
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227// any PARAMS parms go into naming of macro
6228
6229module l2t_oque_dp_msff_macro__stack_40r__width_40 (
6230 din,
6231 clk,
6232 en,
6233 se,
6234 scan_in,
6235 siclk,
6236 soclk,
6237 pce_ov,
6238 stop,
6239 dout,
6240 scan_out);
6241wire l1clk;
6242wire siclk_out;
6243wire soclk_out;
6244wire [38:0] so;
6245
6246 input [39:0] din;
6247
6248
6249 input clk;
6250 input en;
6251 input se;
6252 input scan_in;
6253 input siclk;
6254 input soclk;
6255 input pce_ov;
6256 input stop;
6257
6258
6259
6260 output [39:0] dout;
6261
6262
6263 output scan_out;
6264
6265
6266
6267
6268cl_dp1_l1hdr_8x c0_0 (
6269.l2clk(clk),
6270.pce(en),
6271.aclk(siclk),
6272.bclk(soclk),
6273.l1clk(l1clk),
6274 .se(se),
6275 .pce_ov(pce_ov),
6276 .stop(stop),
6277 .siclk_out(siclk_out),
6278 .soclk_out(soclk_out)
6279);
6280dff #(40) d0_0 (
6281.l1clk(l1clk),
6282.siclk(siclk_out),
6283.soclk(soclk_out),
6284.d(din[39:0]),
6285.si({scan_in,so[38:0]}),
6286.so({so[38:0],scan_out}),
6287.q(dout[39:0])
6288);
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309endmodule
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319//
6320// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
6321//
6322//
6323
6324
6325
6326
6327
6328module l2t_oque_dp_cmp_macro__dcmp_8x__width_32 (
6329 din0,
6330 din1,
6331 dout);
6332 input [31:0] din0;
6333 input [31:0] din1;
6334 output dout;
6335
6336
6337
6338
6339
6340
6341cmp #(32) m0_0 (
6342.in0(din0[31:0]),
6343.in1(din1[31:0]),
6344.out(dout)
6345);
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356endmodule
6357
6358
6359
6360
6361
6362//
6363// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
6364//
6365//
6366
6367
6368
6369
6370
6371module l2t_oque_dp_cmp_macro__dcmp_8x__width_8 (
6372 din0,
6373 din1,
6374 dout);
6375 input [7:0] din0;
6376 input [7:0] din1;
6377 output dout;
6378
6379
6380
6381
6382
6383
6384cmp #(8) m0_0 (
6385.in0(din0[7:0]),
6386.in1(din1[7:0]),
6387.out(dout)
6388);
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399endmodule
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409// any PARAMS parms go into naming of macro
6410
6411module l2t_oque_dp_msff_macro__stack_4r__width_2 (
6412 din,
6413 clk,
6414 en,
6415 se,
6416 scan_in,
6417 siclk,
6418 soclk,
6419 pce_ov,
6420 stop,
6421 dout,
6422 scan_out);
6423wire l1clk;
6424wire siclk_out;
6425wire soclk_out;
6426wire [0:0] so;
6427
6428 input [1:0] din;
6429
6430
6431 input clk;
6432 input en;
6433 input se;
6434 input scan_in;
6435 input siclk;
6436 input soclk;
6437 input pce_ov;
6438 input stop;
6439
6440
6441
6442 output [1:0] dout;
6443
6444
6445 output scan_out;
6446
6447
6448
6449
6450cl_dp1_l1hdr_8x c0_0 (
6451.l2clk(clk),
6452.pce(en),
6453.aclk(siclk),
6454.bclk(soclk),
6455.l1clk(l1clk),
6456 .se(se),
6457 .pce_ov(pce_ov),
6458 .stop(stop),
6459 .siclk_out(siclk_out),
6460 .soclk_out(soclk_out)
6461);
6462dff #(2) d0_0 (
6463.l1clk(l1clk),
6464.siclk(siclk_out),
6465.soclk(soclk_out),
6466.d(din[1:0]),
6467.si({scan_in,so[0:0]}),
6468.so({so[0:0],scan_out}),
6469.q(dout[1:0])
6470);
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491endmodule
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6502// also for pass-gate with decoder
6503
6504
6505
6506
6507
6508// any PARAMS parms go into naming of macro
6509
6510module l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_2__width_1 (
6511 din0,
6512 sel0,
6513 din1,
6514 sel1,
6515 dout);
6516wire buffout0;
6517wire buffout1;
6518
6519 input [0:0] din0;
6520 input sel0;
6521 input [0:0] din1;
6522 input sel1;
6523 output [0:0] dout;
6524
6525
6526
6527
6528
6529cl_dp1_muxbuff2_8x c0_0 (
6530 .in0(sel0),
6531 .in1(sel1),
6532 .out0(buffout0),
6533 .out1(buffout1)
6534);
6535mux2s #(1) d0_0 (
6536 .sel0(buffout0),
6537 .sel1(buffout1),
6538 .in0(din0[0:0]),
6539 .in1(din1[0:0]),
6540.dout(dout[0:0])
6541);
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555endmodule
6556
6557
6558// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6559// also for pass-gate with decoder
6560
6561
6562
6563
6564
6565// any PARAMS parms go into naming of macro
6566
6567module l2t_oque_dp_mux_macro__dmux_4x__mux_aonpe__ports_4__stack_40r__width_40 (
6568 din0,
6569 sel0,
6570 din1,
6571 sel1,
6572 din2,
6573 sel2,
6574 din3,
6575 sel3,
6576 dout);
6577wire buffout0;
6578wire buffout1;
6579wire buffout2;
6580wire buffout3;
6581
6582 input [39:0] din0;
6583 input sel0;
6584 input [39:0] din1;
6585 input sel1;
6586 input [39:0] din2;
6587 input sel2;
6588 input [39:0] din3;
6589 input sel3;
6590 output [39:0] dout;
6591
6592
6593
6594
6595
6596cl_dp1_muxbuff4_8x c0_0 (
6597 .in0(sel0),
6598 .in1(sel1),
6599 .in2(sel2),
6600 .in3(sel3),
6601 .out0(buffout0),
6602 .out1(buffout1),
6603 .out2(buffout2),
6604 .out3(buffout3)
6605);
6606mux4s #(40) d0_0 (
6607 .sel0(buffout0),
6608 .sel1(buffout1),
6609 .sel2(buffout2),
6610 .sel3(buffout3),
6611 .in0(din0[39:0]),
6612 .in1(din1[39:0]),
6613 .in2(din2[39:0]),
6614 .in3(din3[39:0]),
6615.dout(dout[39:0])
6616);
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630endmodule
6631
6632
6633//
6634// invert macro
6635//
6636//
6637
6638
6639
6640
6641
6642module l2t_oque_dp_inv_macro__width_2 (
6643 din,
6644 dout);
6645 input [1:0] din;
6646 output [1:0] dout;
6647
6648
6649
6650
6651
6652
6653inv #(2) d0_0 (
6654.in(din[1:0]),
6655.out(dout[1:0])
6656);
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666endmodule
6667
6668
6669
6670
6671
6672// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6673// also for pass-gate with decoder
6674
6675
6676
6677
6678
6679// any PARAMS parms go into naming of macro
6680
6681module l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_36r__width_36 (
6682 din0,
6683 din1,
6684 din2,
6685 din3,
6686 sel0,
6687 sel1,
6688 sel2,
6689 muxtst,
6690 test,
6691 dout);
6692wire psel0;
6693wire psel1;
6694wire psel2;
6695wire psel3;
6696
6697 input [35:0] din0;
6698 input [35:0] din1;
6699 input [35:0] din2;
6700 input [35:0] din3;
6701 input sel0;
6702 input sel1;
6703 input sel2;
6704 input muxtst;
6705 input test;
6706 output [35:0] dout;
6707
6708
6709
6710
6711
6712cl_dp1_penc4_8x c0_0 (
6713 .sel0(sel0),
6714 .sel1(sel1),
6715 .sel2(sel2),
6716 .psel0(psel0),
6717 .psel1(psel1),
6718 .psel2(psel2),
6719 .psel3(psel3),
6720 .test(test)
6721);
6722
6723mux4 #(36) d0_0 (
6724 .sel0(psel0),
6725 .sel1(psel1),
6726 .sel2(psel2),
6727 .sel3(psel3),
6728 .in0(din0[35:0]),
6729 .in1(din1[35:0]),
6730 .in2(din2[35:0]),
6731 .in3(din3[35:0]),
6732.dout(dout[35:0]),
6733 .muxtst(muxtst)
6734);
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748endmodule
6749
6750
6751// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6752// also for pass-gate with decoder
6753
6754
6755
6756
6757
6758// any PARAMS parms go into naming of macro
6759
6760module l2t_oque_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_38r__width_38 (
6761 din0,
6762 din1,
6763 din2,
6764 din3,
6765 sel0,
6766 sel1,
6767 sel2,
6768 muxtst,
6769 test,
6770 dout);
6771wire psel0;
6772wire psel1;
6773wire psel2;
6774wire psel3;
6775
6776 input [37:0] din0;
6777 input [37:0] din1;
6778 input [37:0] din2;
6779 input [37:0] din3;
6780 input sel0;
6781 input sel1;
6782 input sel2;
6783 input muxtst;
6784 input test;
6785 output [37:0] dout;
6786
6787
6788
6789
6790
6791cl_dp1_penc4_8x c0_0 (
6792 .sel0(sel0),
6793 .sel1(sel1),
6794 .sel2(sel2),
6795 .psel0(psel0),
6796 .psel1(psel1),
6797 .psel2(psel2),
6798 .psel3(psel3),
6799 .test(test)
6800);
6801
6802mux4 #(38) d0_0 (
6803 .sel0(psel0),
6804 .sel1(psel1),
6805 .sel2(psel2),
6806 .sel3(psel3),
6807 .in0(din0[37:0]),
6808 .in1(din1[37:0]),
6809 .in2(din2[37:0]),
6810 .in3(din3[37:0]),
6811.dout(dout[37:0]),
6812 .muxtst(muxtst)
6813);
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827endmodule
6828
6829
6830
6831
6832
6833
6834// any PARAMS parms go into naming of macro
6835
6836module l2t_oque_dp_msff_macro__dmsff_32x__stack_38r__width_38 (
6837 din,
6838 clk,
6839 en,
6840 se,
6841 scan_in,
6842 siclk,
6843 soclk,
6844 pce_ov,
6845 stop,
6846 dout,
6847 scan_out);
6848wire l1clk;
6849wire siclk_out;
6850wire soclk_out;
6851wire [36:0] so;
6852
6853 input [37:0] din;
6854
6855
6856 input clk;
6857 input en;
6858 input se;
6859 input scan_in;
6860 input siclk;
6861 input soclk;
6862 input pce_ov;
6863 input stop;
6864
6865
6866
6867 output [37:0] dout;
6868
6869
6870 output scan_out;
6871
6872
6873
6874
6875cl_dp1_l1hdr_8x c0_0 (
6876.l2clk(clk),
6877.pce(en),
6878.aclk(siclk),
6879.bclk(soclk),
6880.l1clk(l1clk),
6881 .se(se),
6882 .pce_ov(pce_ov),
6883 .stop(stop),
6884 .siclk_out(siclk_out),
6885 .soclk_out(soclk_out)
6886);
6887dff #(38) d0_0 (
6888.l1clk(l1clk),
6889.siclk(siclk_out),
6890.soclk(soclk_out),
6891.d(din[37:0]),
6892.si({scan_in,so[36:0]}),
6893.so({so[36:0],scan_out}),
6894.q(dout[37:0])
6895);
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916endmodule
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926//
6927// buff macro
6928//
6929//
6930
6931
6932
6933
6934
6935module l2t_oque_dp_buff_macro__dbuff_16x__stack_38r__width_38 (
6936 din,
6937 dout);
6938 input [37:0] din;
6939 output [37:0] dout;
6940
6941
6942
6943
6944
6945
6946buff #(38) d0_0 (
6947.in(din[37:0]),
6948.out(dout[37:0])
6949);
6950
6951
6952
6953
6954
6955
6956
6957
6958endmodule
6959
6960
6961
6962
6963
6964//
6965// buff macro
6966//
6967//
6968
6969
6970
6971
6972
6973module l2t_oque_dp_buff_macro__dbuff_16x__stack_36r__width_36 (
6974 din,
6975 dout);
6976 input [35:0] din;
6977 output [35:0] dout;
6978
6979
6980
6981
6982
6983
6984buff #(36) d0_0 (
6985.in(din[35:0]),
6986.out(dout[35:0])
6987);
6988
6989
6990
6991
6992
6993
6994
6995
6996endmodule
6997
6998
6999
7000
7001
7002//
7003// invert macro
7004//
7005//
7006
7007
7008
7009
7010
7011module l2t_oque_dp_inv_macro__dinv_48x__stack_38r__width_38 (
7012 din,
7013 dout);
7014 input [37:0] din;
7015 output [37:0] dout;
7016
7017
7018
7019
7020
7021
7022inv #(38) d0_0 (
7023.in(din[37:0]),
7024.out(dout[37:0])
7025);
7026
7027
7028
7029
7030
7031
7032
7033
7034
7035endmodule
7036
7037
7038
7039
7040
7041//
7042// invert macro
7043//
7044//
7045
7046
7047
7048
7049
7050module l2t_oque_dp_inv_macro__dinv_48x__stack_36r__width_36 (
7051 din,
7052 dout);
7053 input [35:0] din;
7054 output [35:0] dout;
7055
7056
7057
7058
7059
7060
7061inv #(36) d0_0 (
7062.in(din[35:0]),
7063.out(dout[35:0])
7064);
7065
7066
7067
7068
7069
7070
7071
7072
7073
7074endmodule
7075
7076
7077
7078
Full OpenSPARC design & verification tarball including full HDL.