Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_rdmarpt_dp.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_rdmarpt_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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34// ========== Copyright Header End ============================================
35module l2t_rdmarpt_dp (
36 l2t_l2b_fbrd_en_c3,
37 l2t_l2b_fbrd_wl_c3,
38 l2t_l2b_fbwr_wl_r2,
39 filbuf_fbd_rd_en_c2,
40 filbuf_fbd_rd_entry_c2,
41 filbuf_fbd_wr_entry_r1,
42 l2clk,
43 tcu_pce_ov,
44 tcu_aclk,
45 tcu_bclk,
46 tcu_scan_en,
47 tcu_clk_stop,
48 scan_in,
49 scan_out);
50wire pce_ov;
51wire siclk;
52wire soclk;
53wire stop;
54wire se;
55
56
57output l2t_l2b_fbrd_en_c3;
58output [2:0] l2t_l2b_fbrd_wl_c3;
59output [2:0] l2t_l2b_fbwr_wl_r2;
60
61input filbuf_fbd_rd_en_c2;
62input [2:0] filbuf_fbd_rd_entry_c2;
63input [2:0] filbuf_fbd_wr_entry_r1;
64input l2clk;
65
66input tcu_pce_ov;
67input tcu_aclk;
68input tcu_bclk;
69input tcu_scan_en;
70input tcu_clk_stop;
71input scan_in;
72output scan_out;
73
74assign pce_ov = tcu_pce_ov;
75assign siclk = tcu_aclk;
76assign soclk = tcu_bclk;
77assign stop = tcu_clk_stop;
78assign se = tcu_scan_en;
79
80
81l2t_msff_macro__dmsff_32x__stack_8r__width_7 ff_rdma_rptr_flops
82 (
83 .din ({filbuf_fbd_rd_en_c2,filbuf_fbd_rd_entry_c2[2:0],filbuf_fbd_wr_entry_r1[2:0]}),
84 .dout ({l2t_l2b_fbrd_en_c3,l2t_l2b_fbrd_wl_c3[2:0],l2t_l2b_fbwr_wl_r2[2:0]}),
85 .clk (l2clk),
86 .en (1'b1),
87 .scan_in(scan_in),
88 .scan_out(scan_out),
89 .se(se),
90 .siclk(siclk),
91 .soclk(soclk),
92 .pce_ov(pce_ov),
93 .stop(stop)
94 );
95
96
97
98
99endmodule
100
101
102
103
104// any PARAMS parms go into naming of macro
105
106module l2t_msff_macro__dmsff_32x__stack_8r__width_7 (
107 din,
108 clk,
109 en,
110 se,
111 scan_in,
112 siclk,
113 soclk,
114 pce_ov,
115 stop,
116 dout,
117 scan_out);
118wire l1clk;
119wire siclk_out;
120wire soclk_out;
121wire [5:0] so;
122
123 input [6:0] din;
124
125
126 input clk;
127 input en;
128 input se;
129 input scan_in;
130 input siclk;
131 input soclk;
132 input pce_ov;
133 input stop;
134
135
136
137 output [6:0] dout;
138
139
140 output scan_out;
141
142
143
144
145cl_dp1_l1hdr_8x c0_0 (
146.l2clk(clk),
147.pce(en),
148.aclk(siclk),
149.bclk(soclk),
150.l1clk(l1clk),
151 .se(se),
152 .pce_ov(pce_ov),
153 .stop(stop),
154 .siclk_out(siclk_out),
155 .soclk_out(soclk_out)
156);
157dff #(7) d0_0 (
158.l1clk(l1clk),
159.siclk(siclk_out),
160.soclk(soclk_out),
161.d(din[6:0]),
162.si({scan_in,so[5:0]}),
163.so({so[5:0],scan_out}),
164.q(dout[6:0])
165);
166
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185
186endmodule
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