[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_shdwscn_dp.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: l2t_shdwscn_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`define	IQ_SIZE	8
`define	OQ_SIZE	12
`define	TAG_WIDTH	28
`define	TAG_WIDTH_LESS1	27
`define	TAG_WIDTHr	28r
`define	TAG_WIDTHc	28c
`define	TAG_WIDTH6	22
`define	TAG_WIDTH6r	22r
`define	TAG_WIDTH6c	22c


`define	MBD_WIDTH	106    // BS and SR 11/12/03 N2 Xbar Packet format change

// BS and SR 11/12/03 N2 Xbar Packet format change

`define	MBD_ECC_HI	105
`define	MBD_ECC_HI_PLUS1	106
`define	MBD_ECC_HI_PLUS5	110
`define	MBD_ECC_LO	100
`define	MBD_EVICT	99 
`define	MBD_DEP		98
`define	MBD_TECC	97
`define	MBD_ENTRY_HI	96
`define	MBD_ENTRY_LO	93

`define	MBD_POISON	92   
`define	MBD_RDMA_HI	91
`define	MBD_RDMA_LO	90
`define	MBD_RQ_HI	89
`define	MBD_RQ_LO	85
`define	MBD_NC		84
`define	MBD_RSVD	83
`define	MBD_CP_HI	82
`define	MBD_CP_LO	80
`define	MBD_TH_HI	79
`define	MBD_TH_LO	77
`define	MBD_BF_HI	76
`define	MBD_BF_LO	74
`define	MBD_WY_HI	73
`define	MBD_WY_LO	72
`define	MBD_SZ_HI	71
`define	MBD_SZ_LO	64
`define	MBD_DATA_HI	63
`define	MBD_DATA_LO	0

// BS and SR 11/12/03 N2 Xbar Packet format change
`define	L2_FBF		40
`define	L2_MBF		39
`define	L2_SNP		38
`define	L2_CTRUE	37
`define	L2_EVICT  	36
`define	L2_DEP		35
`define	L2_TECC		34
`define	L2_ENTRY_HI	33
`define	L2_ENTRY_LO	29

`define	L2_POISON	28
`define	L2_RDMA_HI	27
`define	L2_RDMA_LO	26
// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
`define	L2_RQTYP_HI	25
`define	L2_RQTYP_LO	21
`define	L2_NC		20
`define	L2_RSVD		19
`define	L2_CPUID_HI	18
`define	L2_CPUID_LO	16
`define	L2_TID_HI	15	
`define	L2_TID_LO	13	
`define	L2_BUFID_HI     12	
`define	L2_BUFID_LO	10	
`define	L2_L1WY_HI	9
`define	L2_L1WY_LO	8
`define	L2_SZ_HI	7
`define	L2_SZ_LO	0


`define	ERR_MEU		63
`define	ERR_MEC		62
`define	ERR_RW		61
`define	ERR_ASYNC	60
`define	ERR_TID_HI	59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
`define	ERR_TID_LO	54
`define	ERR_LDAC	53
`define	ERR_LDAU	52
`define	ERR_LDWC	51
`define	ERR_LDWU	50
`define	ERR_LDRC	49
`define	ERR_LDRU	48
`define	ERR_LDSC	47
`define	ERR_LDSU	46
`define	ERR_LTC		45
`define	ERR_LRU		44
`define	ERR_LVU		43
`define	ERR_DAC		42
`define	ERR_DAU		41
`define	ERR_DRC		40
`define	ERR_DRU		39
`define	ERR_DSC		38
`define	ERR_DSU		37
`define	ERR_VEC		36
`define	ERR_VEU		35
`define ERR_LVC         34
`define	ERR_SYN_HI	31
`define	ERR_SYN_LO	0


`define ERR_MEND	51
`define ERR_NDRW	50
`define ERR_NDSP	49
`define ERR_NDDM	48
`define ERR_NDVCID_HI   45
`define ERR_NDVCID_LO   40
`define ERR_NDADR_HI    39
`define ERR_NDADR_LO    4


//  Phase 2 : SIU Inteface and format change

`define	JBI_HDR_SZ	26 // BS and SR 11/12/03 N2 Xbar Packet format change
`define	JBI_HDR_SZ_LESS1	25 // BS and SR 11/12/03 N2 Xbar Packet format change
`define	JBI_HDR_SZ4     23	
`define	JBI_HDR_SZc	27c
`define	JBI_HDR_SZ4c    23c	

`define	JBI_ADDR_LO	0	
`define	JBI_ADDR_HI	7	
`define	JBI_SZ_LO	8	
`define	JBI_SZ_HI	15	
// `define	JBI_RSVD	16	NOt used
`define	JBI_CTAG_LO	16	
`define	JBI_CTAG_HI	23	
`define	JBI_RQ_RD	24	
`define	JBI_RQ_WR8	25	
`define	JBI_RQ_WR64	26	
`define JBI_OPES_LO	27	// 0 = 30, P=29, E=28, S=27
`define JBI_OPES_HI	30
`define	JBI_RQ_POISON	31	
`define	JBI_ENTRY_LO	32
`define	JBI_ENTRY_HI	33

//  Phase 2 : SIU Inteface and format change
// BS and SR 11/12/03 N2 Xbar Packet format change :
`define	JBINST_SZ_LO	0	
`define	JBINST_SZ_HI	7	
// `define	JBINST_RSVD	8 NOT used	
`define	JBINST_CTAG_LO	8	
`define	JBINST_CTAG_HI	15	
`define	JBINST_RQ_RD	16	
`define	JBINST_RQ_WR8	17	
`define	JBINST_RQ_WR64	18	
`define JBINST_OPES_LO  19	// 0 = 22, P=21, E=20, S=19
`define JBINST_OPES_HI  22
`define	JBINST_ENTRY_LO	23
`define	JBINST_ENTRY_HI	24
`define	JBINST_POISON   25


`define	ST_REQ_ST	1
`define	LD_REQ_ST	2
`define	IDLE	0


module l2t_shdwscn_dp (
  l2clk, 
  rd_errstate_reg, 
  rd_notdata_reg, 
  csr_l2_erraddr_reg, 
  tcu_l2t_shscan_scan_in, 
  tcu_l2t_shscan_aclk, 
  tcu_l2t_shscan_bclk, 
  tcu_l2t_shscan_scan_en, 
  tcu_l2t_shscan_pce_ov, 
  tcu_l2t_shscan_clk_stop_d2, 
  l2t_tcu_shscan_scan_out);
wire pce_ov;
wire siclk;
wire soclk;
wire se;
wire stop;
wire [141:0] shadow_scan_flopin;
wire ff_rd_errstate_reg_00_scanin;
wire ff_rd_errstate_reg_00_scanout;
wire [63:0] shdw_rd_errstate_reg_unused;
wire ff_rd_errstate_reg_01_scanin;
wire ff_rd_errstate_reg_01_scanout;
wire ff_rd_errstate_reg_10_scanin;
wire ff_rd_errstate_reg_10_scanout;
wire ff_rd_errstate_reg_11_scanin;
wire ff_rd_errstate_reg_11_scanout;
wire ff_rd_notdata_reg_00_scanin;
wire ff_rd_notdata_reg_00_scanout;
wire [63:0] shdw_rd_notdata_reg_unused;
wire ff_rd_notdata_reg_01_scanin;
wire ff_rd_notdata_reg_01_scanout;
wire ff_rd_notdata_reg_10_scanin;
wire ff_rd_notdata_reg_10_scanout;
wire ff_rd_notdata_reg_11_scanin;
wire ff_rd_notdata_reg_11_scanout;
wire ff_csr_l2_erraddr_reg_00_scanin;
wire ff_csr_l2_erraddr_reg_00_scanout;
wire [45:32] shdw_csr_l2_erraddr_reg_unused;


input		l2clk;

input	[63:0]	rd_errstate_reg;
input 	[`ERR_MEND:`ERR_NDADR_LO]	rd_notdata_reg;
input	[39:4]	csr_l2_erraddr_reg;

// shadow scan ports
input           tcu_l2t_shscan_scan_in;
input           tcu_l2t_shscan_aclk;
input           tcu_l2t_shscan_bclk;    
input           tcu_l2t_shscan_scan_en; 
input           tcu_l2t_shscan_pce_ov;
input           tcu_l2t_shscan_clk_stop_d2; 
output          l2t_tcu_shscan_scan_out;


assign pce_ov 	= tcu_l2t_shscan_pce_ov;
assign siclk 	= tcu_l2t_shscan_aclk;
assign soclk 	= tcu_l2t_shscan_bclk;
assign se 	= tcu_l2t_shscan_scan_en;
assign stop 	= tcu_l2t_shscan_clk_stop_d2;

assign shadow_scan_flopin[141:84] = {rd_errstate_reg[63:34],rd_errstate_reg[27:0]};
assign shadow_scan_flopin[83:36]  =  rd_notdata_reg[`ERR_MEND:`ERR_NDADR_LO];
assign shadow_scan_flopin[35:0]   =  csr_l2_erraddr_reg[39:4];


l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_00 
        (
        .scan_in(ff_rd_errstate_reg_00_scanin),
        .scan_out(ff_rd_errstate_reg_00_scanout),
        .dout           (shdw_rd_errstate_reg_unused[47:32]),
	.en		(1'b1),
        .clk          	(l2clk),
        .din            (shadow_scan_flopin[15:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );

l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_01 
        (
        .scan_in(ff_rd_errstate_reg_01_scanin),
        .scan_out(ff_rd_errstate_reg_01_scanout),
        .dout           (shdw_rd_errstate_reg_unused[63:48]),
        .en             (1'b1),
        .clk            (l2clk),
        .din            (shadow_scan_flopin[31:16]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );


l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_10 
        (
        .scan_in(ff_rd_errstate_reg_10_scanin),
        .scan_out(ff_rd_errstate_reg_10_scanout),
        .dout           (shdw_rd_errstate_reg_unused[15:0]),
        .en             (1'b1),
        .clk            (l2clk),
        .din            (shadow_scan_flopin[47:32]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );

l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_11 
        (
        .scan_in(ff_rd_errstate_reg_11_scanin),
        .scan_out(ff_rd_errstate_reg_11_scanout),
        .dout           (shdw_rd_errstate_reg_unused[31:16]),
        .en             (1'b1),
        .clk            (l2clk),
        .din            (shadow_scan_flopin[63:48]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );

l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_00 
        (
        .scan_in(ff_rd_notdata_reg_00_scanin),
        .scan_out(ff_rd_notdata_reg_00_scanout),
        .dout           (shdw_rd_notdata_reg_unused[47:32]),
        .clk          	(l2clk),
	.en		(1'b1),
        .din            (shadow_scan_flopin[79:64]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );

l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_01 
        (
        .scan_in(ff_rd_notdata_reg_01_scanin),
        .scan_out(ff_rd_notdata_reg_01_scanout),
        .dout           (shdw_rd_notdata_reg_unused[63:48]),
        .clk            (l2clk),
        .en             (1'b1),
        .din            (shadow_scan_flopin[95:80]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );


l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_10 
        (
        .scan_in(ff_rd_notdata_reg_10_scanin),
        .scan_out(ff_rd_notdata_reg_10_scanout),
        .dout           (shdw_rd_notdata_reg_unused[15:0]),
        .clk            (l2clk),
        .en             (1'b1),
        .din            (shadow_scan_flopin[111:96]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );

l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_11 
        (
        .scan_in(ff_rd_notdata_reg_11_scanin),
        .scan_out(ff_rd_notdata_reg_11_scanout),
        .dout           (shdw_rd_notdata_reg_unused[31:16]),
        .clk            (l2clk),
        .en             (1'b1),
        .din            (shadow_scan_flopin[127:112]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );

l2t_shdwscn_dp_msff_macro__stack_16r__width_14 ff_csr_l2_erraddr_reg_00 
        (
        .scan_in(ff_csr_l2_erraddr_reg_00_scanin),
        .scan_out(ff_csr_l2_erraddr_reg_00_scanout),
        .dout           (shdw_csr_l2_erraddr_reg_unused[45:32]),
        .clk          	(l2clk),
	.en		(1'b1),
        .din            (shadow_scan_flopin[141:128]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );


// fixscan start:
assign ff_rd_errstate_reg_00_scanin = tcu_l2t_shscan_scan_in   ;
assign ff_rd_errstate_reg_01_scanin = ff_rd_errstate_reg_00_scanout;
assign ff_rd_errstate_reg_10_scanin = ff_rd_errstate_reg_01_scanout;
assign ff_rd_errstate_reg_11_scanin = ff_rd_errstate_reg_10_scanout;
assign ff_rd_notdata_reg_00_scanin = ff_rd_errstate_reg_11_scanout;
assign ff_rd_notdata_reg_01_scanin = ff_rd_notdata_reg_00_scanout;
assign ff_rd_notdata_reg_10_scanin = ff_rd_notdata_reg_01_scanout;
assign ff_rd_notdata_reg_11_scanin = ff_rd_notdata_reg_10_scanout;
assign ff_csr_l2_erraddr_reg_00_scanin = ff_rd_notdata_reg_11_scanout;
assign l2t_tcu_shscan_scan_out     = ff_csr_l2_erraddr_reg_00_scanout;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module l2t_shdwscn_dp_msff_macro__stack_16r__width_16 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [14:0] so;

  input [15:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [15:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module l2t_shdwscn_dp_msff_macro__stack_16r__width_14 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [12:0] so;

  input [13:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [13:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: l2t_shdwscn_dp.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	`define IQ_SIZE 8
	36	`define OQ_SIZE 12
	37	`define TAG_WIDTH 28
	38	`define TAG_WIDTH_LESS1 27
	39	`define TAG_WIDTHr 28r
	40	`define TAG_WIDTHc 28c
	41	`define TAG_WIDTH6 22
	42	`define TAG_WIDTH6r 22r
	43	`define TAG_WIDTH6c 22c
	44
	45
	46	`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
	47
	48	// BS and SR 11/12/03 N2 Xbar Packet format change
	49
	50	`define MBD_ECC_HI 105
	51	`define MBD_ECC_HI_PLUS1 106
	52	`define MBD_ECC_HI_PLUS5 110
	53	`define MBD_ECC_LO 100
	54	`define MBD_EVICT 99
	55	`define MBD_DEP 98
	56	`define MBD_TECC 97
	57	`define MBD_ENTRY_HI 96
	58	`define MBD_ENTRY_LO 93
	59
	60	`define MBD_POISON 92
	61	`define MBD_RDMA_HI 91
	62	`define MBD_RDMA_LO 90
	63	`define MBD_RQ_HI 89
	64	`define MBD_RQ_LO 85
65	`define MBD_NC 84
66	`define MBD_RSVD 83
67	`define MBD_CP_HI 82
68	`define MBD_CP_LO 80
69	`define MBD_TH_HI 79
70	`define MBD_TH_LO 77
71	`define MBD_BF_HI 76
72	`define MBD_BF_LO 74
73	`define MBD_WY_HI 73
74	`define MBD_WY_LO 72
75	`define MBD_SZ_HI 71
76	`define MBD_SZ_LO 64
77	`define MBD_DATA_HI 63
78	`define MBD_DATA_LO 0
79
80	// BS and SR 11/12/03 N2 Xbar Packet format change
81	`define L2_FBF 40
82	`define L2_MBF 39
83	`define L2_SNP 38
84	`define L2_CTRUE 37
85	`define L2_EVICT 36
86	`define L2_DEP 35
87	`define L2_TECC 34
88	`define L2_ENTRY_HI 33
89	`define L2_ENTRY_LO 29
90
91	`define L2_POISON 28
92	`define L2_RDMA_HI 27
93	`define L2_RDMA_LO 26
94	// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
95	`define L2_RQTYP_HI 25
96	`define L2_RQTYP_LO 21
97	`define L2_NC 20
98	`define L2_RSVD 19
99	`define L2_CPUID_HI 18
100	`define L2_CPUID_LO 16
101	`define L2_TID_HI 15
102	`define L2_TID_LO 13
103	`define L2_BUFID_HI 12
104	`define L2_BUFID_LO 10
105	`define L2_L1WY_HI 9
106	`define L2_L1WY_LO 8
107	`define L2_SZ_HI 7
108	`define L2_SZ_LO 0
109
110
111	`define ERR_MEU 63
112	`define ERR_MEC 62
113	`define ERR_RW 61
114	`define ERR_ASYNC 60
115	`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
116	`define ERR_TID_LO 54
117	`define ERR_LDAC 53
118	`define ERR_LDAU 52
119	`define ERR_LDWC 51
120	`define ERR_LDWU 50
121	`define ERR_LDRC 49
122	`define ERR_LDRU 48
123	`define ERR_LDSC 47
124	`define ERR_LDSU 46
125	`define ERR_LTC 45
126	`define ERR_LRU 44
127	`define ERR_LVU 43
128	`define ERR_DAC 42
129	`define ERR_DAU 41
130	`define ERR_DRC 40
131	`define ERR_DRU 39
132	`define ERR_DSC 38
133	`define ERR_DSU 37
134	`define ERR_VEC 36
135	`define ERR_VEU 35
136	`define ERR_LVC 34
137	`define ERR_SYN_HI 31
138	`define ERR_SYN_LO 0
139
140
141
142	`define ERR_MEND 51
143	`define ERR_NDRW 50
144	`define ERR_NDSP 49
145	`define ERR_NDDM 48
146	`define ERR_NDVCID_HI 45
147	`define ERR_NDVCID_LO 40
148	`define ERR_NDADR_HI 39
149	`define ERR_NDADR_LO 4
150
151
152	// Phase 2 : SIU Inteface and format change
153
154	`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
155	`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
156	`define JBI_HDR_SZ4 23
157	`define JBI_HDR_SZc 27c
158	`define JBI_HDR_SZ4c 23c
159
160	`define JBI_ADDR_LO 0
161	`define JBI_ADDR_HI 7
162	`define JBI_SZ_LO 8
163	`define JBI_SZ_HI 15
164	// `define JBI_RSVD 16 NOt used
165	`define JBI_CTAG_LO 16
166	`define JBI_CTAG_HI 23
167	`define JBI_RQ_RD 24
168	`define JBI_RQ_WR8 25
169	`define JBI_RQ_WR64 26
170	`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
171	`define JBI_OPES_HI 30
172	`define JBI_RQ_POISON 31
173	`define JBI_ENTRY_LO 32
174	`define JBI_ENTRY_HI 33
175
176	// Phase 2 : SIU Inteface and format change
177	// BS and SR 11/12/03 N2 Xbar Packet format change :
178	`define JBINST_SZ_LO 0
179	`define JBINST_SZ_HI 7
180	// `define JBINST_RSVD 8 NOT used
181	`define JBINST_CTAG_LO 8
182	`define JBINST_CTAG_HI 15
183	`define JBINST_RQ_RD 16
184	`define JBINST_RQ_WR8 17
185	`define JBINST_RQ_WR64 18
186	`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
187	`define JBINST_OPES_HI 22
188	`define JBINST_ENTRY_LO 23
189	`define JBINST_ENTRY_HI 24
190	`define JBINST_POISON 25
191
192
193	`define ST_REQ_ST 1
194	`define LD_REQ_ST 2
195	`define IDLE 0
196
197
198
199	module l2t_shdwscn_dp (
200	l2clk,
201	rd_errstate_reg,
202	rd_notdata_reg,
203	csr_l2_erraddr_reg,
204	tcu_l2t_shscan_scan_in,
205	tcu_l2t_shscan_aclk,
206	tcu_l2t_shscan_bclk,
207	tcu_l2t_shscan_scan_en,
208	tcu_l2t_shscan_pce_ov,
209	tcu_l2t_shscan_clk_stop_d2,
210	l2t_tcu_shscan_scan_out);
211	wire pce_ov;
212	wire siclk;
213	wire soclk;
214	wire se;
215	wire stop;
216	wire [141:0] shadow_scan_flopin;
217	wire ff_rd_errstate_reg_00_scanin;
218	wire ff_rd_errstate_reg_00_scanout;
219	wire [63:0] shdw_rd_errstate_reg_unused;
220	wire ff_rd_errstate_reg_01_scanin;
221	wire ff_rd_errstate_reg_01_scanout;
222	wire ff_rd_errstate_reg_10_scanin;
223	wire ff_rd_errstate_reg_10_scanout;
224	wire ff_rd_errstate_reg_11_scanin;
225	wire ff_rd_errstate_reg_11_scanout;
226	wire ff_rd_notdata_reg_00_scanin;
227	wire ff_rd_notdata_reg_00_scanout;
228	wire [63:0] shdw_rd_notdata_reg_unused;
229	wire ff_rd_notdata_reg_01_scanin;
230	wire ff_rd_notdata_reg_01_scanout;
231	wire ff_rd_notdata_reg_10_scanin;
232	wire ff_rd_notdata_reg_10_scanout;
233	wire ff_rd_notdata_reg_11_scanin;
234	wire ff_rd_notdata_reg_11_scanout;
235	wire ff_csr_l2_erraddr_reg_00_scanin;
236	wire ff_csr_l2_erraddr_reg_00_scanout;
237	wire [45:32] shdw_csr_l2_erraddr_reg_unused;
238
239
240
241	input l2clk;
242
243	input [63:0] rd_errstate_reg;
244	input [`ERR_MEND:`ERR_NDADR_LO] rd_notdata_reg;
245	input [39:4] csr_l2_erraddr_reg;
246
247	// shadow scan ports
248	input tcu_l2t_shscan_scan_in;
249	input tcu_l2t_shscan_aclk;
250	input tcu_l2t_shscan_bclk;
251	input tcu_l2t_shscan_scan_en;
252	input tcu_l2t_shscan_pce_ov;
253	input tcu_l2t_shscan_clk_stop_d2;
254	output l2t_tcu_shscan_scan_out;
255
256
257	assign pce_ov = tcu_l2t_shscan_pce_ov;
258	assign siclk = tcu_l2t_shscan_aclk;
259	assign soclk = tcu_l2t_shscan_bclk;
260	assign se = tcu_l2t_shscan_scan_en;
261	assign stop = tcu_l2t_shscan_clk_stop_d2;
262
263	assign shadow_scan_flopin[141:84] = {rd_errstate_reg[63:34],rd_errstate_reg[27:0]};
264	assign shadow_scan_flopin[83:36] = rd_notdata_reg[`ERR_MEND:`ERR_NDADR_LO];
265	assign shadow_scan_flopin[35:0] = csr_l2_erraddr_reg[39:4];
266
267
268	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_00
269	(
270	.scan_in(ff_rd_errstate_reg_00_scanin),
271	.scan_out(ff_rd_errstate_reg_00_scanout),
272	.dout (shdw_rd_errstate_reg_unused[47:32]),
273	.en (1'b1),
274	.clk (l2clk),
275	.din (shadow_scan_flopin[15:0]),
276	.se(se),
277	.siclk(siclk),
278	.soclk(soclk),
279	.pce_ov(pce_ov),
280	.stop(stop)
281	);
282
283	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_01
284	(
285	.scan_in(ff_rd_errstate_reg_01_scanin),
286	.scan_out(ff_rd_errstate_reg_01_scanout),
287	.dout (shdw_rd_errstate_reg_unused[63:48]),
288	.en (1'b1),
289	.clk (l2clk),
290	.din (shadow_scan_flopin[31:16]),
291	.se(se),
292	.siclk(siclk),
293	.soclk(soclk),
294	.pce_ov(pce_ov),
295	.stop(stop)
296	);
297
298
299
300	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_10
301	(
302	.scan_in(ff_rd_errstate_reg_10_scanin),
303	.scan_out(ff_rd_errstate_reg_10_scanout),
304	.dout (shdw_rd_errstate_reg_unused[15:0]),
305	.en (1'b1),
306	.clk (l2clk),
307	.din (shadow_scan_flopin[47:32]),
308	.se(se),
309	.siclk(siclk),
310	.soclk(soclk),
311	.pce_ov(pce_ov),
312	.stop(stop)
313	);
314
315	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_errstate_reg_11
316	(
317	.scan_in(ff_rd_errstate_reg_11_scanin),
318	.scan_out(ff_rd_errstate_reg_11_scanout),
319	.dout (shdw_rd_errstate_reg_unused[31:16]),
320	.en (1'b1),
321	.clk (l2clk),
322	.din (shadow_scan_flopin[63:48]),
323	.se(se),
324	.siclk(siclk),
325	.soclk(soclk),
326	.pce_ov(pce_ov),
327	.stop(stop)
328	);
329
330	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_00
331	(
332	.scan_in(ff_rd_notdata_reg_00_scanin),
333	.scan_out(ff_rd_notdata_reg_00_scanout),
334	.dout (shdw_rd_notdata_reg_unused[47:32]),
335	.clk (l2clk),
336	.en (1'b1),
337	.din (shadow_scan_flopin[79:64]),
338	.se(se),
339	.siclk(siclk),
340	.soclk(soclk),
341	.pce_ov(pce_ov),
342	.stop(stop)
343	);
344
345	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_01
346	(
347	.scan_in(ff_rd_notdata_reg_01_scanin),
348	.scan_out(ff_rd_notdata_reg_01_scanout),
349	.dout (shdw_rd_notdata_reg_unused[63:48]),
350	.clk (l2clk),
351	.en (1'b1),
352	.din (shadow_scan_flopin[95:80]),
353	.se(se),
354	.siclk(siclk),
355	.soclk(soclk),
356	.pce_ov(pce_ov),
357	.stop(stop)
358	);
359
360
361	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_10
362	(
363	.scan_in(ff_rd_notdata_reg_10_scanin),
364	.scan_out(ff_rd_notdata_reg_10_scanout),
365	.dout (shdw_rd_notdata_reg_unused[15:0]),
366	.clk (l2clk),
367	.en (1'b1),
368	.din (shadow_scan_flopin[111:96]),
369	.se(se),
370	.siclk(siclk),
371	.soclk(soclk),
372	.pce_ov(pce_ov),
373	.stop(stop)
374	);
375
376	l2t_shdwscn_dp_msff_macro__stack_16r__width_16 ff_rd_notdata_reg_11
377	(
378	.scan_in(ff_rd_notdata_reg_11_scanin),
379	.scan_out(ff_rd_notdata_reg_11_scanout),
380	.dout (shdw_rd_notdata_reg_unused[31:16]),
381	.clk (l2clk),
382	.en (1'b1),
383	.din (shadow_scan_flopin[127:112]),
384	.se(se),
385	.siclk(siclk),
386	.soclk(soclk),
387	.pce_ov(pce_ov),
388	.stop(stop)
389	);
390
391	l2t_shdwscn_dp_msff_macro__stack_16r__width_14 ff_csr_l2_erraddr_reg_00
392	(
393	.scan_in(ff_csr_l2_erraddr_reg_00_scanin),
394	.scan_out(ff_csr_l2_erraddr_reg_00_scanout),
395	.dout (shdw_csr_l2_erraddr_reg_unused[45:32]),
396	.clk (l2clk),
397	.en (1'b1),
398	.din (shadow_scan_flopin[141:128]),
399	.se(se),
400	.siclk(siclk),
401	.soclk(soclk),
402	.pce_ov(pce_ov),
403	.stop(stop)
404	);
405
406
407	// fixscan start:
408	assign ff_rd_errstate_reg_00_scanin = tcu_l2t_shscan_scan_in ;
409	assign ff_rd_errstate_reg_01_scanin = ff_rd_errstate_reg_00_scanout;
410	assign ff_rd_errstate_reg_10_scanin = ff_rd_errstate_reg_01_scanout;
411	assign ff_rd_errstate_reg_11_scanin = ff_rd_errstate_reg_10_scanout;
412	assign ff_rd_notdata_reg_00_scanin = ff_rd_errstate_reg_11_scanout;
413	assign ff_rd_notdata_reg_01_scanin = ff_rd_notdata_reg_00_scanout;
414	assign ff_rd_notdata_reg_10_scanin = ff_rd_notdata_reg_01_scanout;
415	assign ff_rd_notdata_reg_11_scanin = ff_rd_notdata_reg_10_scanout;
416	assign ff_csr_l2_erraddr_reg_00_scanin = ff_rd_notdata_reg_11_scanout;
417	assign l2t_tcu_shscan_scan_out = ff_csr_l2_erraddr_reg_00_scanout;
418	// fixscan end:
419	endmodule
420
421
422
423
424
425
426	// any PARAMS parms go into naming of macro
427
428	module l2t_shdwscn_dp_msff_macro__stack_16r__width_16 (
429	din,
430	clk,
431	en,
432	se,
433	scan_in,
434	siclk,
435	soclk,
436	pce_ov,
437	stop,
438	dout,
439	scan_out);
440	wire l1clk;
441	wire siclk_out;
442	wire soclk_out;
443	wire [14:0] so;
444
445	input [15:0] din;
446
447
448	input clk;
449	input en;
450	input se;
451	input scan_in;
452	input siclk;
453	input soclk;
454	input pce_ov;
455	input stop;
456
457
458
459	output [15:0] dout;
460
461
462	output scan_out;
463
464
465
466
467	cl_dp1_l1hdr_8x c0_0 (
468	.l2clk(clk),
469	.pce(en),
470	.aclk(siclk),
471	.bclk(soclk),
472	.l1clk(l1clk),
473	.se(se),
474	.pce_ov(pce_ov),
475	.stop(stop),
476	.siclk_out(siclk_out),
477	.soclk_out(soclk_out)
478	);
479	dff #(16) d0_0 (
480	.l1clk(l1clk),
481	.siclk(siclk_out),
482	.soclk(soclk_out),
483	.d(din[15:0]),
484	.si({scan_in,so[14:0]}),
485	.so({so[14:0],scan_out}),
486	.q(dout[15:0])
487	);
488
489
490
491
492
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494
495
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498
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505
506
507
508	endmodule
509
510
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519
520
521
522	// any PARAMS parms go into naming of macro
523
524	module l2t_shdwscn_dp_msff_macro__stack_16r__width_14 (
525	din,
526	clk,
527	en,
528	se,
529	scan_in,
530	siclk,
531	soclk,
532	pce_ov,
533	stop,
534	dout,
535	scan_out);
536	wire l1clk;
537	wire siclk_out;
538	wire soclk_out;
539	wire [12:0] so;
540
541	input [13:0] din;
542
543
544	input clk;
545	input en;
546	input se;
547	input scan_in;
548	input siclk;
549	input soclk;
550	input pce_ov;
551	input stop;
552
553
554
555	output [13:0] dout;
556
557
558	output scan_out;
559
560
561
562
563	cl_dp1_l1hdr_8x c0_0 (
564	.l2clk(clk),
565	.pce(en),
566	.aclk(siclk),
567	.bclk(soclk),
568	.l1clk(l1clk),
569	.se(se),
570	.pce_ov(pce_ov),
571	.stop(stop),
572	.siclk_out(siclk_out),
573	.soclk_out(soclk_out)
574	);
575	dff #(14) d0_0 (
576	.l1clk(l1clk),
577	.siclk(siclk_out),
578	.soclk(soclk_out),
579	.d(din[13:0]),
580	.si({scan_in,so[12:0]}),
581	.so({so[12:0],scan_out}),
582	.q(dout[13:0])
583	);
584
585
586
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602
603
604	endmodule
605
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612