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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_tag_ctl.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_tag_ctl.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852
853`define IQ_SIZE 8
854`define OQ_SIZE 12
855`define TAG_WIDTH 28
856`define TAG_WIDTH_LESS1 27
857`define TAG_WIDTHr 28r
858`define TAG_WIDTHc 28c
859`define TAG_WIDTH6 22
860`define TAG_WIDTH6r 22r
861`define TAG_WIDTH6c 22c
862
863
864`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
865
866// BS and SR 11/12/03 N2 Xbar Packet format change
867
868`define MBD_ECC_HI 105
869`define MBD_ECC_HI_PLUS1 106
870`define MBD_ECC_HI_PLUS5 110
871`define MBD_ECC_LO 100
872`define MBD_EVICT 99
873`define MBD_DEP 98
874`define MBD_TECC 97
875`define MBD_ENTRY_HI 96
876`define MBD_ENTRY_LO 93
877
878`define MBD_POISON 92
879`define MBD_RDMA_HI 91
880`define MBD_RDMA_LO 90
881`define MBD_RQ_HI 89
882`define MBD_RQ_LO 85
883`define MBD_NC 84
884`define MBD_RSVD 83
885`define MBD_CP_HI 82
886`define MBD_CP_LO 80
887`define MBD_TH_HI 79
888`define MBD_TH_LO 77
889`define MBD_BF_HI 76
890`define MBD_BF_LO 74
891`define MBD_WY_HI 73
892`define MBD_WY_LO 72
893`define MBD_SZ_HI 71
894`define MBD_SZ_LO 64
895`define MBD_DATA_HI 63
896`define MBD_DATA_LO 0
897
898// BS and SR 11/12/03 N2 Xbar Packet format change
899`define L2_FBF 40
900`define L2_MBF 39
901`define L2_SNP 38
902`define L2_CTRUE 37
903`define L2_EVICT 36
904`define L2_DEP 35
905`define L2_TECC 34
906`define L2_ENTRY_HI 33
907`define L2_ENTRY_LO 29
908
909`define L2_POISON 28
910`define L2_RDMA_HI 27
911`define L2_RDMA_LO 26
912// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
913`define L2_RQTYP_HI 25
914`define L2_RQTYP_LO 21
915`define L2_NC 20
916`define L2_RSVD 19
917`define L2_CPUID_HI 18
918`define L2_CPUID_LO 16
919`define L2_TID_HI 15
920`define L2_TID_LO 13
921`define L2_BUFID_HI 12
922`define L2_BUFID_LO 10
923`define L2_L1WY_HI 9
924`define L2_L1WY_LO 8
925`define L2_SZ_HI 7
926`define L2_SZ_LO 0
927
928
929`define ERR_MEU 63
930`define ERR_MEC 62
931`define ERR_RW 61
932`define ERR_ASYNC 60
933`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
934`define ERR_TID_LO 54
935`define ERR_LDAC 53
936`define ERR_LDAU 52
937`define ERR_LDWC 51
938`define ERR_LDWU 50
939`define ERR_LDRC 49
940`define ERR_LDRU 48
941`define ERR_LDSC 47
942`define ERR_LDSU 46
943`define ERR_LTC 45
944`define ERR_LRU 44
945`define ERR_LVU 43
946`define ERR_DAC 42
947`define ERR_DAU 41
948`define ERR_DRC 40
949`define ERR_DRU 39
950`define ERR_DSC 38
951`define ERR_DSU 37
952`define ERR_VEC 36
953`define ERR_VEU 35
954`define ERR_LVC 34
955`define ERR_SYN_HI 31
956`define ERR_SYN_LO 0
957
958
959
960`define ERR_MEND 51
961`define ERR_NDRW 50
962`define ERR_NDSP 49
963`define ERR_NDDM 48
964`define ERR_NDVCID_HI 45
965`define ERR_NDVCID_LO 40
966`define ERR_NDADR_HI 39
967`define ERR_NDADR_LO 4
968
969
970// Phase 2 : SIU Inteface and format change
971
972`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
974`define JBI_HDR_SZ4 23
975`define JBI_HDR_SZc 27c
976`define JBI_HDR_SZ4c 23c
977
978`define JBI_ADDR_LO 0
979`define JBI_ADDR_HI 7
980`define JBI_SZ_LO 8
981`define JBI_SZ_HI 15
982// `define JBI_RSVD 16 NOt used
983`define JBI_CTAG_LO 16
984`define JBI_CTAG_HI 23
985`define JBI_RQ_RD 24
986`define JBI_RQ_WR8 25
987`define JBI_RQ_WR64 26
988`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
989`define JBI_OPES_HI 30
990`define JBI_RQ_POISON 31
991`define JBI_ENTRY_LO 32
992`define JBI_ENTRY_HI 33
993
994// Phase 2 : SIU Inteface and format change
995// BS and SR 11/12/03 N2 Xbar Packet format change :
996`define JBINST_SZ_LO 0
997`define JBINST_SZ_HI 7
998// `define JBINST_RSVD 8 NOT used
999`define JBINST_CTAG_LO 8
1000`define JBINST_CTAG_HI 15
1001`define JBINST_RQ_RD 16
1002`define JBINST_RQ_WR8 17
1003`define JBINST_RQ_WR64 18
1004`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1005`define JBINST_OPES_HI 22
1006`define JBINST_ENTRY_LO 23
1007`define JBINST_ENTRY_HI 24
1008`define JBINST_POISON 25
1009
1010
1011`define ST_REQ_ST 1
1012`define LD_REQ_ST 2
1013`define IDLE 0
1014
1015
1016
1017
1018module l2t_tag_ctl (
1019 tcu_pce_ov,
1020 tcu_aclk,
1021 tcu_bclk,
1022 tcu_scan_en,
1023 tag_dir_l2way_sel_c4,
1024 tag_hit_way_vld_c3,
1025 tag_st_to_data_array_c3,
1026 tag_hit_l2orfb_c3,
1027 sel_diag_store_data_c7,
1028 tag_data_array_wr_active_c1,
1029 tag_miss_unqual_c2,
1030 tag_hit_unqual_c2,
1031 tag_hit_unqual_c3,
1032 tag_hit_c3,
1033 tag_lru_way_c4,
1034 misbuf_uncorr_err_c1,
1035 misbuf_notdata_err_c1,
1036 tag_rdma_vld_px0_p,
1037 tag_hit_not_comp_c3,
1038 tag_alt_tag_miss_unqual_c3,
1039 tag_misbuf_rdma_reg_vld_c2,
1040 tag_misbuf_int_ack_c3,
1041 l2t_l2b_fbwr_wen_r2,
1042 l2t_l2b_fbd_stdatasel_c3,
1043 tagctl_l2drpt_mux4_way_sel_c1,
1044 dec_col_offset_prev_c1,
1045 tag_l2d_rd_wr_c2,
1046 tag_l2d_word_en_c2,
1047 decdp_cas2_from_mb_ctrue_c1,
1048 tag_deccck_addr3_c7,
1049 tag_decc_tag_acc_en_px2,
1050 tag_data_ecc_active_c3,
1051 tag_deccck_data_sel_c8,
1052 tag_scrub_rd_vld_c7,
1053 tag_spc_rd_vld_c6,
1054 tag_bsc_rd_vld_c7,
1055 tag_scrub_addr_way,
1056 tag_imiss_hit_c5,
1057 tag_ld_hit_c5,
1058 tag_strst_ack_c5,
1059 tag_st_ack_c5,
1060 tag_inval_req_c5,
1061 tag_st_req_c5,
1062 tag_nonmem_comp_c6,
1063 tag_uerr_ack_c5,
1064 tag_cerr_ack_c5,
1065 tag_int_ack_c5,
1066 tag_fwd_req_ret_c5,
1067 tag_sel_rdma_inval_vec_c5,
1068 tag_rdma_wr_comp_c4,
1069 tag_rmo_st_ack_c5,
1070 tag_inst_mb_c5,
1071 tag_hit_c5,
1072 tag_store_inst_c5,
1073 tag_fwd_req_ld_c6,
1074 tag_rdma_gate_off_c2,
1075 tag_rd64_complete_c11,
1076 tag_uerr_ack_tmp_c4,
1077 tag_cerr_ack_tmp_c4,
1078 tag_spc_rd_cond_c3,
1079 arb_vuad_ce_err_c3,
1080 tag_rdma_vld_px1,
1081 tag_rdma_ev_en_c4,
1082 tag_inc_rdma_cnt_c4,
1083 tag_set_rdma_reg_vld_c4,
1084 tag_siu_req_en_c52,
1085 tag_store_inst_c3,
1086 scan_out,
1087 misbuf_hit_st_dep_zero,
1088 tag_way_sel_c2,
1089 vlddir_vuad_valid_c2,
1090 tagdp_lru_way_sel_c3,
1091 misbuf_vuad_ce_instr_ack_c2,
1092 tagdp_tag_par_err_c3,
1093 bist_data_enc_way_sel_c1,
1094 bist_data_enable_c1,
1095 bist_data_wr_enable_c1,
1096 bist_data_waddr_c1,
1097 mbist_run,
1098 arbadr_arbdp_addr5to4_c1,
1099 arbadr_arbdp_addr3to2_c1,
1100 arbadr_arbaddr_addr22_c2,
1101 arbadr_arbdp_diag_wr_way_c2,
1102 arbdec_arbdp_inst_way_c3,
1103 arb_decdp_tag_wr_c1,
1104 arb_decdp_cas2_from_mb_c2,
1105 arb_decdp_strst_inst_c2,
1106 arb_arbdp_dword_st_c1,
1107 arb_decdp_rmo_st_c3,
1108 arbdec_arbdp_rdma_inst_c1,
1109 arb_decdp_ld64_inst_c1,
1110 arb_decdp_wr64_inst_c2,
1111 arb_decdp_wr8_inst_c2,
1112 arb_tag_pst_with_ctrue_c1,
1113 csr_l2_bypass_mode_on,
1114 arb_bist_or_diag_acc_c1,
1115 arb_fill_vld_c2,
1116 arb_imiss_vld_c2,
1117 arb_evict_vld_c2,
1118 arb_tag_inst_vld_c2,
1119 arb_waysel_gate_c2,
1120 arb_data_diag_st_c2,
1121 arb_csr_wr_en_c3,
1122 arb_csr_rd_en_c3,
1123 arb_diag_complete_c3,
1124 deccck_scrd_uncorr_err_c8,
1125 misbuf_tag_hit_unqual_c2,
1126 misbuf_uncorr_err_c2,
1127 misbuf_corr_err_c2,
1128 misbuf_notdata_err_c2,
1129 misbuf_wr64_miss_comp_c3,
1130 misbuf_arb_hit_c3,
1131 filbuf_match_c3,
1132 arb_decdp_swap_inst_c2,
1133 arb_arbdp_tag_pst_no_ctrue_c2,
1134 arb_decdp_cas1_inst_c2,
1135 arb_decdp_ld_inst_c2,
1136 arbdec_arbdp_inst_mb_c2,
1137 arbdec_arbdp_inst_dep_c2,
1138 arb_decdp_st_inst_c2,
1139 arb_decdp_st_with_ctrue_c2,
1140 arb_decdp_inst_int_c2,
1141 arb_decdp_fwd_req_c2,
1142 arb_inst_diag_c1,
1143 arb_inval_inst_c2,
1144 arb_waysel_inst_vld_c2,
1145 arb_inst_vld_c2_prev,
1146 arb_upper_four_byte_access_c1,
1147 arb_lower_four_byte_access_c1,
1148 arb_rdwr_inst_vld_c2,
1149 arb_wr8_inst_no_ctrue_c1,
1150 filbuf_tag_hit_c2,
1151 filbuf_tag_hit_frm_mb_c2,
1152 filbuf_tag_evict_way_c3,
1153 filbuf_mcu_l2t_chunk_id_r1,
1154 filbuf_mcu_l2t_data_vld_r1,
1155 filbuf_dis_cerr_c3,
1156 filbuf_dis_uerr_c3,
1157 filbuf_dis_nderr_c3,
1158 oqu_st_complete_c7,
1159 arbdec_arbdp_tecc_c1,
1160 wmr_l,
1161 l2clk,
1162 scan_in,
1163 csr_error_nceen,
1164 csr_error_ceen,
1165 tagdp_misbuf_par_err_c3,
1166 tag_misbuf_par_err_c3,
1167 mbist_arb_l2d_en);
1168wire pce_ov;
1169wire stop;
1170wire siclk;
1171wire soclk;
1172wire se;
1173wire l1clk;
1174wire spares_scanin;
1175wire spares_scanout;
1176wire reset_flop_scanin;
1177wire reset_flop_scanout;
1178wire ff_mbist_run_scanin;
1179wire ff_mbist_run_scanout;
1180wire mbist_run_r1_n;
1181wire ff_mbist_arb_l2d_en_d1_scanin;
1182wire ff_mbist_arb_l2d_en_d1_scanout;
1183wire mbist_arb_l2d_en_d1;
1184wire csr_l2_bypass_mode_on_qual;
1185wire ff_l2_bypass_mode_on_scanin;
1186wire ff_l2_bypass_mode_on_scanout;
1187wire l2_bypass_mode_on_d1;
1188wire arb_fill_vld_c2_in;
1189wire ff_fill_vld_c3_scanin;
1190wire ff_fill_vld_c3_scanout;
1191wire arb_decdp_ld64_inst_c1_qual;
1192wire ff_ld64_inst_c2_scanin;
1193wire ff_ld64_inst_c2_scanout;
1194wire ff_temp_way_sel_c2_scanin;
1195wire ff_temp_way_sel_c2_scanout;
1196wire arb_evict_vld_c2_qual;
1197wire ff_evict_unqual_vld_c3_scanin;
1198wire ff_evict_unqual_vld_c3_scanout;
1199wire ff_wr8_no_ctrue_c2_scanin;
1200wire ff_wr8_no_ctrue_c2_scanout;
1201wire wr8_inst_no_ctrue_c2_cloned;
1202wire tag_rdma_gate_off_c2_internal;
1203wire rdma_reg_vld_cloned;
1204wire rdma_inst_c2_cloned;
1205wire ff_tag_hit_way_vld_c3_scanin;
1206wire ff_tag_hit_way_vld_c3_scanout;
1207wire [15:0] tag_l2d_way_sel_c2;
1208wire ff_tag_l2d_way_sel_c3_scanin;
1209wire ff_tag_l2d_way_sel_c3_scanout;
1210wire ff_way_sel_unqual_c3_scanin;
1211wire ff_way_sel_unqual_c3_scanout;
1212wire misbuf_hit_st_dep_zero_qual;
1213wire filbuf_tag_hit_c3_tmp;
1214wire filbuf_tag_hit_c3;
1215wire imiss_vld_c4;
1216wire ff_filbuf_tag_evict_way_c4_scanin;
1217wire ff_filbuf_tag_evict_way_c4_scanout;
1218wire ff_filbuf_tag_hit_c3_scanin;
1219wire ff_filbuf_tag_hit_c3_scanout;
1220wire evict_sel_c3;
1221wire hit_sel_c3;
1222wire [3:0] tag_dir_l2way_sel_c3;
1223wire ff_tag_dir_l2way_sel_c4_scanin;
1224wire ff_tag_dir_l2way_sel_c4_scanout;
1225wire ff_alt_tag_miss_unqual_c3_scanin;
1226wire ff_alt_tag_miss_unqual_c3_scanout;
1227wire ff_tag_hit_c3_scanin;
1228wire ff_tag_hit_c3_scanout;
1229wire ff_tag_hit_l2orfb_c3_scanin;
1230wire ff_tag_hit_l2orfb_c3_scanout;
1231wire ff_tag_hit_not_comp_c3_scanin;
1232wire ff_tag_hit_not_comp_c3_scanout;
1233wire ff_encoded_lru_c4_scanin;
1234wire ff_encoded_lru_c4_scanout;
1235wire ff_addr5to4_c2_scanin;
1236wire ff_addr5to4_c2_scanout;
1237wire ff_dec_col_offset_prev_c2_scanin;
1238wire ff_dec_col_offset_prev_c2_scanout;
1239wire col_offset_sel_c1;
1240wire ff_col_offset_sel_c2_scanin;
1241wire ff_col_offset_sel_c2_scanout;
1242wire col_offset_sel_c2_fnl;
1243wire col_offset_sel_c2_fnl_n;
1244wire [3:0] tag_l2d_col_offset_c2;
1245wire ff_imiss_tag_hit_c4_scanin;
1246wire ff_imiss_tag_hit_c4_scanout;
1247wire ff_rdma_inst_c2_scanin;
1248wire ff_rdma_inst_c2_scanout;
1249wire ff_rdma_inst_c3_scanin;
1250wire ff_rdma_inst_c3_scanout;
1251wire ff_st_to_data_array_c3_scanin;
1252wire ff_st_to_data_array_c3_scanout;
1253wire ff_tag_spc_rd_vld_c4_scanin;
1254wire ff_tag_spc_rd_vld_c4_scanout;
1255wire ff_tag_spc_rd_vld_c5_scanin;
1256wire ff_tag_spc_rd_vld_c5_scanout;
1257wire ff_tag_spc_rd_vld_c52_scanin;
1258wire ff_tag_spc_rd_vld_c52_scanout;
1259wire ff_tag_spc_rd_vld_c6_scanin;
1260wire ff_tag_spc_rd_vld_c6_scanout;
1261wire ff_tag_spc_rd_vld_c7_scanin;
1262wire ff_tag_spc_rd_vld_c7_scanout;
1263wire tag_spc_rd_vld_c7;
1264wire ff_tag_bsc_rd_vld_c4_scanin;
1265wire ff_tag_bsc_rd_vld_c4_scanout;
1266wire ff_tag_bsc_rd_vld_c5_scanin;
1267wire ff_tag_bsc_rd_vld_c5_scanout;
1268wire ff_tag_bsc_rd_vld_c52_scanin;
1269wire ff_tag_bsc_rd_vld_c52_scanout;
1270wire ff_tag_bsc_rd_vld_c6_scanin;
1271wire ff_tag_bsc_rd_vld_c6_scanout;
1272wire ff_tag_bsc_rd_vld_c7_scanin;
1273wire ff_tag_bsc_rd_vld_c7_scanout;
1274wire ff_prev_rd_wr_c2_scanin;
1275wire ff_prev_rd_wr_c2_scanout;
1276wire ff_pst_with_ctrue_c2_scanin;
1277wire ff_pst_with_ctrue_c2_scanout;
1278wire misbuffer_errors_c1;
1279wire other_term_c2_prev;
1280wire ff_mb_errs_c2_scanin;
1281wire ff_mb_errs_c2_scanout;
1282wire other_term_c2;
1283wire arb_inst_diag_c2;
1284wire ff_prev_rd_wr_c2_1_scanin;
1285wire ff_prev_rd_wr_c2_1_scanout;
1286wire ff_tag_st_to_data_array_c3_scanin;
1287wire ff_tag_st_to_data_array_c3_scanout;
1288wire ff_prev_wen_c1_scanin;
1289wire ff_prev_wen_c1_scanout;
1290wire ff_sel_prev_wen_c2_scanin;
1291wire ff_sel_prev_wen_c2_scanout;
1292wire [15:0] word_en_c1;
1293wire ff_dec_word_addr_c2_scanin;
1294wire ff_dec_word_addr_c2_scanout;
1295wire [15:0] tag_l2d_word_en_c1;
1296wire ff_dec_word_enable_c2_scanin;
1297wire ff_dec_word_enable_c2_scanout;
1298wire ff_tecc_c2_scanin;
1299wire ff_tecc_c2_scanout;
1300wire ff_scrub_fsm_cnt_scanin;
1301wire ff_scrub_fsm_cnt_scanout;
1302wire ff_scrub_addr_cnt_scanin;
1303wire ff_scrub_addr_cnt_scanout;
1304wire ff_decc_tag_acc_en_px2_scanin;
1305wire ff_decc_tag_acc_en_px2_scanout;
1306wire ff_scrub_way_vld_c3_scanin;
1307wire ff_scrub_way_vld_c3_scanout;
1308wire ff_scrub_way_vld_c4_scanin;
1309wire ff_scrub_way_vld_c4_scanout;
1310wire ff_scrub_way_vld_c5_scanin;
1311wire ff_scrub_way_vld_c5_scanout;
1312wire ff_scrub_way_vld_c52_scanin;
1313wire ff_scrub_way_vld_c52_scanout;
1314wire ff_scrub_way_vld_c6_scanin;
1315wire ff_scrub_way_vld_c6_scanout;
1316wire ff_scrub_way_vld_c7_scanin;
1317wire ff_scrub_way_vld_c7_scanout;
1318wire ff_scrub_rd_vld_c8_scanin;
1319wire ff_scrub_rd_vld_c8_scanout;
1320wire ff_scrub_wr_disable_c9_scanin;
1321wire ff_scrub_wr_disable_c9_scanout;
1322wire ff_l2b_fbwr_wen_r2_scanin;
1323wire ff_l2b_fbwr_wen_r2_scanout;
1324wire ff_tag_l2b_fbd_stdatasel_c3_scanin;
1325wire ff_tag_l2b_fbd_stdatasel_c3_scanout;
1326wire ff_imiss_vld_c3_scanin;
1327wire ff_imiss_vld_c3_scanout;
1328wire ff_imiss_hit_c4_scanin;
1329wire ff_imiss_hit_c4_scanout;
1330wire ff_imiss_hit_c5_scanin;
1331wire ff_imiss_hit_c5_scanout;
1332wire ff_swap_inst_c3_scanin;
1333wire ff_swap_inst_c3_scanout;
1334wire ff_pst_no_ctrue_c3_scanin;
1335wire ff_pst_no_ctrue_c3_scanout;
1336wire ff_cas1_inst_c3_scanin;
1337wire ff_cas1_inst_c3_scanout;
1338wire ff_ld_inst_c3_scanin;
1339wire ff_ld_inst_c3_scanout;
1340wire ff_ld_hit_c4_scanin;
1341wire ff_ld_hit_c4_scanout;
1342wire ff_ld_hit_c5_scanin;
1343wire ff_ld_hit_c5_scanout;
1344wire ff_inst_vld_c3_scanin;
1345wire ff_inst_vld_c3_scanout;
1346wire ff_inst_diag_c3_scanin;
1347wire ff_inst_diag_c3_scanout;
1348wire ff_inst_mb_c3_scanin;
1349wire ff_inst_mb_c3_scanout;
1350wire ff_inst_mb_c4_scanin;
1351wire ff_inst_mb_c4_scanout;
1352wire ff_inst_mb_c5_scanin;
1353wire ff_inst_mb_c5_scanout;
1354wire ff_misbuf_hit_unqual_c3_scanin;
1355wire ff_misbuf_hit_unqual_c3_scanout;
1356wire ff_inst_dep_c3_scanin;
1357wire ff_inst_dep_c3_scanout;
1358wire ff_store_inst_c3_scanin;
1359wire ff_store_inst_c3_scanout;
1360wire ff_store_inst_c4_scanin;
1361wire ff_store_inst_c4_scanout;
1362wire ff_store_inst_c5_scanin;
1363wire ff_store_inst_c5_scanout;
1364wire ff_cas2_from_mb_c3_scanin;
1365wire ff_cas2_from_mb_c3_scanout;
1366wire ff_pst_with_ctrue_c3_scanin;
1367wire ff_pst_with_ctrue_c3_scanout;
1368wire ff_inval_inst_c3_scanin;
1369wire ff_inval_inst_c3_scanout;
1370wire ff_strstore_c3_scanin;
1371wire ff_strstore_c3_scanout;
1372wire ff_diag_rd_en_c3_scanin;
1373wire ff_diag_rd_en_c3_scanout;
1374wire csr_rd_en_c4;
1375wire ff_diag_wr_en_c3_scanin;
1376wire ff_diag_wr_en_c3_scanout;
1377wire ff_diag_complete_c4_scanin;
1378wire ff_diag_complete_c4_scanout;
1379wire ff_tecc_c3_scanin;
1380wire ff_tecc_c3_scanout;
1381wire ff_tag_hit_unqual_c3_scanin;
1382wire ff_tag_hit_unqual_c3_scanout;
1383wire tag_misbuf_ack_c3;
1384wire vuad_ce_instr_ack_c3;
1385wire inval_req_c3;
1386wire st_inval_ack_c3;
1387wire ff_st_ack_c4_scanin;
1388wire ff_st_ack_c4_scanout;
1389wire ff_st_ack_c5_scanin;
1390wire ff_st_ack_c5_scanout;
1391wire ff_inval_req_c4_scanin;
1392wire ff_inval_req_c4_scanout;
1393wire inval_req_c4;
1394wire ff_inval_ack_c5_scanin;
1395wire ff_inval_ack_c5_scanout;
1396wire inval_req_c5;
1397wire ff_tag_hit_c4_scanin;
1398wire ff_tag_hit_c4_scanout;
1399wire ff_tag_hit_c5_scanin;
1400wire ff_tag_hit_c5_scanout;
1401wire ff_st_req_c4_scanin;
1402wire ff_st_req_c4_scanout;
1403wire ff_st_req_c5_scanin;
1404wire ff_st_req_c5_scanout;
1405wire sel_diag_store_data_c4;
1406wire ff_sel_diag_store_data_c5_scanin;
1407wire ff_sel_diag_store_data_c5_scanout;
1408wire ff_sel_diag_store_data_c52_scanin;
1409wire ff_sel_diag_store_data_c52_scanout;
1410wire ff_sel_diag_store_data_c6_scanin;
1411wire ff_sel_diag_store_data_c6_scanout;
1412wire ff_sel_diag_store_data_c7_scanin;
1413wire ff_sel_diag_store_data_c7_scanout;
1414wire ff_strst_ack_c4_scanin;
1415wire ff_strst_ack_c4_scanout;
1416wire ff_strst_ack_c5_scanin;
1417wire ff_strst_ack_c5_scanout;
1418wire ff_rmo_st_ack_c4_scanin;
1419wire ff_rmo_st_ack_c4_scanout;
1420wire ff_rmo_st_ack_c5_scanin;
1421wire ff_rmo_st_ack_c5_scanout;
1422wire ff_nonmem_comp_c5_scanin;
1423wire ff_nonmem_comp_c5_scanout;
1424wire ff_nonmem_comp_c52_scanin;
1425wire ff_nonmem_comp_c52_scanout;
1426wire ff_nonmem_comp_c6_scanin;
1427wire ff_nonmem_comp_c6_scanout;
1428wire ff_st_with_ctrue_c3_scanin;
1429wire ff_st_with_ctrue_c3_scanout;
1430wire ff_misbuf_uerr_c3_scanin;
1431wire ff_misbuf_uerr_c3_scanout;
1432wire misbuf_nderr_c3;
1433wire ff_misbuf_cerr_c3_scanin;
1434wire ff_misbuf_cerr_c3_scanout;
1435wire ff_uerr_ack_tmp_c4_scanin;
1436wire ff_uerr_ack_tmp_c4_scanout;
1437wire misbuf_nderr_c4;
1438wire ff_uerr_ack_c4_scanin;
1439wire ff_uerr_ack_c4_scanout;
1440wire ff_uerr_ack_c5_scanin;
1441wire ff_uerr_ack_c5_scanout;
1442wire misbuf_nderr_c5;
1443wire ff_error_ceen_d1_scanin;
1444wire ff_error_ceen_d1_scanout;
1445wire ff_error_nceen_d1_scanin;
1446wire ff_error_nceen_d1_scanout;
1447wire [1:0] filbuf_dis_nderr_c5;
1448wire ff_cerr_ack_tmp_c4_scanin;
1449wire ff_cerr_ack_tmp_c4_scanout;
1450wire ff_cerr_ack_c4_scanin;
1451wire ff_cerr_ack_c4_scanout;
1452wire ff_cerr_ack_c5_scanin;
1453wire ff_cerr_ack_c5_scanout;
1454wire ff_dis_nderr_c5_scanin;
1455wire ff_dis_nderr_c5_scanout;
1456wire [1:0] filbuf_dis_nderr_c4;
1457wire ff_inst_int_c3_scanin;
1458wire ff_inst_int_c3_scanout;
1459wire ff_int_ack_c4_scanin;
1460wire ff_int_ack_c4_scanout;
1461wire ff_int_ack_c5_scanin;
1462wire ff_int_ack_c5_scanout;
1463wire ff_fwd_req_c3_scanin;
1464wire ff_fwd_req_c3_scanout;
1465wire ff_fwd_req_vld_diag_c4_scanin;
1466wire ff_fwd_req_vld_diag_c4_scanout;
1467wire ff_fwd_req_ret_c4_scanin;
1468wire ff_fwd_req_ret_c4_scanout;
1469wire ff_fwd_req_ret_c5_scanin;
1470wire ff_fwd_req_ret_c5_scanout;
1471wire ff_fwd_req_ld_c4_scanin;
1472wire ff_fwd_req_ld_c4_scanout;
1473wire ff_fwd_req_ld_c5_scanin;
1474wire ff_fwd_req_ld_c5_scanout;
1475wire ff_fwd_req_ld_c52_scanin;
1476wire ff_fwd_req_ld_c52_scanout;
1477wire ff_fwd_req_ld_c6_scanin;
1478wire ff_fwd_req_ld_c6_scanout;
1479wire ff_ld64_inst_c3_scanin;
1480wire ff_ld64_inst_c3_scanout;
1481wire ff_wr64_inst_c3_scanin;
1482wire ff_wr64_inst_c3_scanout;
1483wire ff_wr8_inst_c3_scanin;
1484wire ff_wr8_inst_c3_scanout;
1485wire ff_sel_rdma_inval_vec_c4_scanin;
1486wire ff_sel_rdma_inval_vec_c4_scanout;
1487wire ff_sel_rdma_inval_vec_c5_scanin;
1488wire ff_sel_rdma_inval_vec_c5_scanout;
1489wire ff_tag_rdma_ev_en_c3_scanin;
1490wire ff_tag_rdma_ev_en_c3_scanout;
1491wire ff_rdma_reg_vld_scanin;
1492wire ff_rdma_reg_vld_scanout;
1493wire ff_tag_rdma_wr_comp_c4_scanin;
1494wire ff_tag_rdma_wr_comp_c4_scanout;
1495wire ff_misbuf_rdma_reg_vld_c2_scanin;
1496wire ff_misbuf_rdma_reg_vld_c2_scanout;
1497wire ff_rdma_vld_px0_p_scanin;
1498wire ff_rdma_vld_px0_p_scanout;
1499wire ff_rdma_vld_px1_scanin;
1500wire ff_rdma_vld_px1_scanout;
1501wire ff_set_rdma_reg_vld_c4_scanin;
1502wire ff_set_rdma_reg_vld_c4_scanout;
1503wire ff_tag_siu_req_state_0_scanin;
1504wire ff_tag_siu_req_state_0_scanout;
1505wire ff_tag_siu_req_state_scanin;
1506wire ff_tag_siu_req_state_scanout;
1507wire ff_inc_rdma_cnt_c4_scanin;
1508wire ff_inc_rdma_cnt_c4_scanout;
1509wire ff_rdmard_cnt_scanin;
1510wire ff_rdmard_cnt_scanout;
1511wire ff_rd64_complete_c4_scanin;
1512wire ff_rd64_complete_c4_scanout;
1513wire ff_rd64_complete_c5_scanin;
1514wire ff_rd64_complete_c5_scanout;
1515wire ff_rd64_complete_c52_scanin;
1516wire ff_rd64_complete_c52_scanout;
1517wire ff_rd64_complete_c6_scanin;
1518wire ff_rd64_complete_c6_scanout;
1519wire ff_rd64_complete_c7_scanin;
1520wire ff_rd64_complete_c7_scanout;
1521wire ff_rd64_complete_c8_scanin;
1522wire ff_rd64_complete_c8_scanout;
1523wire ff_rd64_complete_c9_scanin;
1524wire ff_rd64_complete_c9_scanout;
1525wire ff_rd64_complete_c10_scanin;
1526wire ff_rd64_complete_c10_scanout;
1527wire ff_rd64_complete_c11_scanin;
1528wire ff_rd64_complete_c11_scanout;
1529
1530
1531 input tcu_pce_ov;
1532 input tcu_aclk;
1533 input tcu_bclk;
1534 input tcu_scan_en;
1535
1536output [3:0] tag_dir_l2way_sel_c4; // BS and SR 11/18/03 REverse Direcrtory change
1537//output [3:0] tag_dir_l2way_sel_c3; // BS and SR 11/18/03 REverse Direcrtory change
1538output [15:0] tag_hit_way_vld_c3; // to vuad dp qualified with misbuf already
1539output tag_st_to_data_array_c3; // to vuad dp for dirty bit setting.
1540output tag_hit_l2orfb_c3;
1541
1542// to arbdat
1543output sel_diag_store_data_c7; // BS and SR 12/22/03, store ack generation for diagnostic store
1544output tag_data_array_wr_active_c1; // scrub write in C1
1545
1546
1547// to misbuf
1548output tag_miss_unqual_c2; // used for miss Buffer insertion.
1549output tag_hit_unqual_c2; // used for miss buffer deletion.
1550output tag_hit_unqual_c3; // to arb for cam en logic
1551output tag_hit_c3; // used in misbuf to ready dependents.
1552output [3:0] tag_lru_way_c4 ; // to misbuf for registering the lru way.
1553
1554// timing optimization
1555input misbuf_uncorr_err_c1;
1556input misbuf_notdata_err_c1;
1557//input arb_misbuf_inst_vld_c2;
1558//input arb_misbuf_inval_inst_c2;
1559//input decdp_ic_dc_inval_inst_c1;
1560
1561output tag_rdma_vld_px0_p; // to the miss buffer picker.
1562output tag_hit_not_comp_c3;
1563output tag_alt_tag_miss_unqual_c3;
1564output tag_misbuf_rdma_reg_vld_c2 ; // POST 3.0 pin TOP
1565output tag_misbuf_int_ack_c3;
1566
1567// to l2b fbdata
1568output [15:0] l2t_l2b_fbwr_wen_r2;
1569//output tag_l2b_fbd_stdatasel_c3;
1570output l2t_l2b_fbd_stdatasel_c3;
1571
1572output [15:0] tagctl_l2drpt_mux4_way_sel_c1;
1573// to l2d
1574//output [15:0] tag_l2d_way_sel_c2;
1575//output [3:0] tag_l2d_col_offset_c2;
1576output [3:0] dec_col_offset_prev_c1;
1577output tag_l2d_rd_wr_c2;
1578output [15:0] tag_l2d_word_en_c2;
1579
1580
1581
1582
1583
1584// flopped for timing reasons
1585input decdp_cas2_from_mb_ctrue_c1;
1586
1587output tag_deccck_addr3_c7; // decc for 64b mux sel
1588output tag_decc_tag_acc_en_px2; // arb for tag/vuad acc en generation
1589output tag_data_ecc_active_c3 ; // arb for arb mux sel generation
1590output tag_deccck_data_sel_c8; // used by arbdata to sel scrub data over store data.
1591output tag_scrub_rd_vld_c7 ; // to decc.
1592//output tag_spc_rd_vld_c7; // to decc indicating that a spc read is ON
1593output tag_spc_rd_vld_c6; // to decc for timing will be flopped in decc
1594
1595output tag_bsc_rd_vld_c7; // NEW_PIN to deccck
1596output [3:0] tag_scrub_addr_way; // goes to csr
1597
1598// to oqu
1599output tag_imiss_hit_c5; // meant for generating req_vec and type.
1600output tag_ld_hit_c5; // meant for generating req_vec
1601output tag_strst_ack_c5; // meant for generating req_vec
1602output tag_st_ack_c5; // meant for generating req_vec
1603output tag_inval_req_c5; // meant for generating req_vec, BS and SR 11/12/03 N2 Xbar Packet format change
1604output tag_st_req_c5; // meant for generating rqtyp
1605output tag_nonmem_comp_c6; // csr or diagnotic instructions complete.
1606output tag_uerr_ack_c5;
1607output tag_cerr_ack_c5;
1608output tag_int_ack_c5;
1609output tag_fwd_req_ret_c5; // to oqu
1610//output tag_fwd_req_in_c5; // to oqu.
1611output tag_sel_rdma_inval_vec_c5; // to oqu.
1612output tag_rdma_wr_comp_c4; // to oqu for rdma state m/c
1613output tag_rmo_st_ack_c5; // NEW_PIN to l2t_oqu_ctl.sv
1614output tag_inst_mb_c5; // NEW_PIN to l2t_oqu_ctl.sv
1615output tag_hit_c5; // NEW_PIN to l2t_oqu_ctl.sv
1616
1617// to oq_dctl
1618output tag_store_inst_c5; // to oq_dctl.
1619output tag_fwd_req_ld_c6;
1620
1621// to filbuf
1622output tag_rdma_gate_off_c2; // to filbuf for gating off fb hit.
1623output tag_rd64_complete_c11; // NEW_PIN
1624output tag_uerr_ack_tmp_c4; // POST_2.0 pins
1625output tag_cerr_ack_tmp_c4;
1626output tag_spc_rd_cond_c3 ; // POST 3.2
1627
1628// to arb
1629input arb_vuad_ce_err_c3; // VUAD ecc change
1630output tag_rdma_vld_px1; // to the arbiter.
1631
1632// rdmat.
1633output tag_rdma_ev_en_c4;
1634
1635// to l2b_rep
1636output tag_inc_rdma_cnt_c4; // NEW_PIN
1637output tag_set_rdma_reg_vld_c4 ; // NEW_PIN
1638output tag_siu_req_en_c52; // NEW_PIN
1639
1640// to misbuf
1641
1642output tag_store_inst_c3; //BS and SR 11/07/03, store pipelining support
1643
1644
1645output scan_out;
1646input misbuf_hit_st_dep_zero; // BS and SR 11/07/03, store pipelining support
1647input [15:0] tag_way_sel_c2; // from the tag
1648
1649input [15:0] vlddir_vuad_valid_c2; // from vuad dp
1650input [15:0] tagdp_lru_way_sel_c3; // from vuad dp
1651
1652input misbuf_vuad_ce_instr_ack_c2;
1653input tagdp_tag_par_err_c3 ; // from tagd.
1654
1655input [3:0] bist_data_enc_way_sel_c1;
1656input bist_data_enable_c1;
1657input bist_data_wr_enable_c1;
1658input [3:0] bist_data_waddr_c1;
1659input mbist_run;
1660
1661// from arbaddr
1662input [1:0] arbadr_arbdp_addr5to4_c1; // from arbaddr
1663input [1:0] arbadr_arbdp_addr3to2_c1; // from arbaddr
1664
1665input arbadr_arbaddr_addr22_c2; // diagnostic word address. from arbaddr.
1666input [3:0] arbadr_arbdp_diag_wr_way_c2; // from arbaddr. addr<21..18>
1667
1668// from arbdec
1669input [3:0] arbdec_arbdp_inst_way_c3; // from arbdec
1670input arb_decdp_tag_wr_c1; // indicates a write into the L2$ data array.
1671 // from arbdec
1672//input arb_decdp_cas2_from_mb_ctrue_c2; // indicates that cas2 will write into the L2.
1673 // from arbdec.
1674input arb_decdp_cas2_from_mb_c2;
1675input arb_decdp_strst_inst_c2;
1676input arb_arbdp_dword_st_c1 ; // indicates a 64b write to the data array
1677input arb_decdp_rmo_st_c3; // NEW_PIN from arbdec.
1678
1679// rdma related decoded inputs from arbdec.
1680input arbdec_arbdp_rdma_inst_c1; // POST 3.0 pin replaces arbdec_arbdp_rdma_inst_c2
1681input arb_decdp_ld64_inst_c1; // indicates a 64B read from the data array from BSC/JBI
1682input arb_decdp_wr64_inst_c2;
1683input arb_decdp_wr8_inst_c2;
1684
1685input arb_tag_pst_with_ctrue_c1 ;
1686
1687input csr_l2_bypass_mode_on;
1688
1689input arb_bist_or_diag_acc_c1;
1690input arb_fill_vld_c2;
1691input arb_imiss_vld_c2;
1692input arb_evict_vld_c2;
1693input arb_tag_inst_vld_c2;
1694input arb_waysel_gate_c2;
1695input arb_data_diag_st_c2; // diagnostic store to data array from arb.
1696input arb_csr_wr_en_c3 ; // csr write from miss Buffer,
1697input arb_csr_rd_en_c3 ; // csr read
1698input arb_diag_complete_c3; // vuad, tag, data access
1699
1700input deccck_scrd_uncorr_err_c8;
1701
1702// from misbuf.
1703input misbuf_tag_hit_unqual_c2; // misbuf hit not qualled with instr vld.
1704input misbuf_uncorr_err_c2; // mbf uncorr err means no store.
1705input misbuf_corr_err_c2;
1706input misbuf_notdata_err_c2;
1707input misbuf_wr64_miss_comp_c3 ; // indicates wr64 completion
1708input misbuf_arb_hit_c3; // BS and SR 1/31/04
1709//input misbuf_gate_off_par_err_c3 ; // from misbuf POST_3.4
1710input filbuf_match_c3;
1711
1712
1713
1714// arbdec
1715input arb_decdp_swap_inst_c2;
1716input arb_arbdp_tag_pst_no_ctrue_c2; // Pin on TOP
1717input arb_decdp_cas1_inst_c2;
1718input arb_decdp_ld_inst_c2;
1719input arbdec_arbdp_inst_mb_c2; // from arbdec
1720input arbdec_arbdp_inst_dep_c2; // from arbdec
1721input arb_decdp_st_inst_c2; // from arbdec.
1722input arb_decdp_st_with_ctrue_c2;
1723input arb_decdp_inst_int_c2;
1724input arb_decdp_fwd_req_c2; // from arbdec
1725
1726// arb.
1727//input arb_inst_diag_c2; // from arb.
1728input arb_inst_diag_c1; // from arb.
1729input arb_inval_inst_c2;
1730input arb_waysel_inst_vld_c2; // POST_2.0
1731//input arb_coloff_inst_vld_c2; // POST_2.0
1732input arb_inst_vld_c2_prev;
1733input arb_upper_four_byte_access_c1;// BS 05/04/04 : taking out upper_four_byte_access info to word_en_c2[15:0] gen logic in tag_ctl
1734input arb_lower_four_byte_access_c1; // BS 05/04/04 : taking out lower_four_byte_access info to word_en_c2[15:0] gen logic in tag_ctl
1735input arb_rdwr_inst_vld_c2; // POST_2.0
1736// input arb_wen_inst_vld_c2; // POST_2.0 int 5.0 changes
1737input arb_wr8_inst_no_ctrue_c1; // POST_3.4
1738
1739
1740// from filbuf
1741input filbuf_tag_hit_c2; // filbuf hit.
1742input filbuf_tag_hit_frm_mb_c2; // filbuf hit for an instruction issued from Miss Buffer
1743input [3:0] filbuf_tag_evict_way_c3; // BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Miss
1744input [1:0] filbuf_mcu_l2t_chunk_id_r1; // chunk id for fbdata wr
1745input filbuf_mcu_l2t_data_vld_r1;
1746input filbuf_dis_cerr_c3;
1747input filbuf_dis_uerr_c3;
1748input [1:0] filbuf_dis_nderr_c3;
1749
1750input oqu_st_complete_c7; // from oqu.
1751
1752input arbdec_arbdp_tecc_c1; // from arbdec. Simply the tecc bit of an instruction.
1753input wmr_l;
1754input l2clk;
1755input scan_in;
1756input csr_error_nceen;
1757input csr_error_ceen; // POST_3.2
1758
1759input tagdp_misbuf_par_err_c3;
1760output tag_misbuf_par_err_c3;
1761input mbist_arb_l2d_en;
1762
1763wire dirty_bit_set_c2;
1764wire misbuf_vuad_ce_instr_ack_c3;
1765wire [3:0] filbuf_tag_evict_way_c3_tmp;
1766wire [3:0] filbuf_tag_evict_way_c4;
1767wire [3:0] filbuf_tag_evict_way_c4_in;
1768wire sel_diag_store_data_c5; // BS and SR 12/22/03, store ack generation for diagnostic store
1769wire sel_diag_store_data_c52; // BS 03/11/04 extra cycle for mem access
1770wire sel_diag_store_data_c6; // BS and SR 12/22/03, store ack generation for diagnostic store
1771wire sel_diag_store_data_c7; // BS and SR 12/22/03, store ack generation for diagnostic store
1772
1773//wire [15:0] tag_l2d_way_sel_mod_c2; // BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
1774wire [3:0] tagdp_lru_way_sel_enc_c3; // BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
1775wire [3:0] tag_dir_l2way_sel_taghit_c3; // BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Miss
1776wire [15:0] tag_l2d_way_sel_c3; // BS and SR 11/18/03 REverse Direcrtory change
1777wire tag_store_inst_c3; //BS and SR 11/07/03, store pipelining support
1778wire [2:0] tag_siu_req_state_in, tag_siu_req_state;
1779
1780wire [3:0] mux1_way_sel_c1, mux2_way_sel_c1, mux3_way_sel_c1;
1781wire data_array_acc_active_c1, qual_way_sel_c1;
1782wire [15:0] dec_way_sel_c1;
1783
1784wire evict_unqual_vld_c3;
1785wire [15:0] mux4_way_sel_c1, hit_way_vld_c2, temp_way_sel_c2;
1786
1787wire [3:0] encoded_lru_way_c3;
1788wire tag_hit_c2;
1789
1790wire [1:0] mux1_col_offset_c1, mux2_col_offset_c1, mux3_col_offset_c1;
1791wire [3:0] dec_col_offset_prev_c1, col_offset_dec_prev_c2;
1792wire [3:0] dec_col_offset_c2;
1793// wire data_hold_c2; // int 5.0 changes
1794//wire tag_wr_c2;
1795wire prev_rd_wr_c1, prev_rd_wr_c2;
1796
1797wire [15:0] bist_word_en_c1;
1798wire [15:0] dec_word_addr_c2;
1799wire [15:0] word_en_c2 ;
1800wire [15:0] diag_word_en_c2 ;
1801wire [15:0] mux1_wen_c1 ;
1802wire [15:0] data_ecc_wen_c1 ;
1803wire [15:0] mux2_wen_c1;
1804wire [15:0] tmp_word_en_c2 ;
1805wire [15:0] prev_wen_c1, prev_wen_c2 ;
1806
1807
1808wire arb_tecc_c2;
1809
1810wire scrub_fsm_reset, scrub_fsm_en ;
1811wire [3:0] scrub_fsm_cnt, scrub_fsm_cnt_plus1 ;
1812wire scrub_addr_reset, scrub_addr_en ;
1813wire [6:0] scrub_addr_cnt_plus1, scrub_addr_cnt ;
1814wire [15:0] dec_scrub_addr_way;
1815wire scrub_way_vld_c2,scrub_way_vld_c3;
1816wire scrub_way_vld_c4,scrub_way_vld_c5, scrub_way_vld_c52; // BS 03/11/04 extra cycle for mem access
1817wire scrub_way_vld_c6,scrub_way_vld_c7;
1818wire qual_col_offset_c1;
1819wire data_array_wr_active_c1 ;
1820wire scrub_rd_vld_c8, scrub_wr_disable_c8 ;
1821wire scrub_wr_disable_c9;
1822wire imiss_tag_hit_c3, imiss_tag_hit_c4 ;
1823wire tag_spc_rd_vld_c3;
1824wire tag_spc_rd_vld_c4, tag_spc_rd_vld_c5, tag_spc_rd_vld_c52; // BS 03/11/04 extra cycle for mem access
1825wire tag_spc_rd_vld_c6;
1826
1827wire tag_hit_l2orfb_c2;
1828wire waysel_match_c2;
1829
1830wire [15:0] mcu_fbd_wen_r1 ;
1831wire [15:0] l2t_l2b_fbwr_wen_r1;
1832wire imiss_vld_c3;
1833wire imiss_hit_c3, arb_imiss_hit_c4, imiss_hit_c5 ;
1834wire swap_inst_c3, pst_no_ctrue_c3, cas1_inst_c3, ld_inst_c3 ;
1835wire ld_hit_c3, ld_hit_c4, ld_hit_c5;
1836
1837
1838wire inst_vld_c3, inst_diag_c3, inst_mb_c3;
1839wire misbuf_hit_unqual_c3;
1840wire inst_dep_c3 ;
1841wire pst_with_ctrue_c3, inval_inst_c3;
1842wire ack_c3, st_ack_c3, strst_ack_c3, cas2_from_mb_c3;
1843
1844wire csr_wr_en_c4, strstore_inst_c3 ;
1845wire diag_complete_c4;
1846
1847wire st_ack_c4, st_ack_c5;
1848wire strst_ack_c4, strst_ack_c5;
1849wire st_req_c3, st_req_c4, st_req_c5 ;
1850wire nonmem_comp_c4, nonmem_comp_c5, nonmem_comp_c52, nonmem_comp_c6; // BS 03/11/04 extra cycle for mem access
1851
1852
1853wire st_with_ctrue_c3, misbuf_uerr_c3, misbuf_cerr_c3 ;
1854wire uerr_ack_c3, uerr_ack_c4, uerr_ack_c5 ;
1855wire cerr_ack_c3, cerr_ack_c4, cerr_ack_c5 ;
1856
1857wire inst_int_c3, int_ack_c3;
1858wire int_ack_c4, int_ack_c5;
1859
1860wire fwd_req_c3, fwd_req_vld_diag_c3, fwd_req_vld_diagn_c3;
1861wire fwd_req_vld_diag_c4;
1862wire fwd_req_ret_c3, fwd_req_ret_c4, fwd_req_ret_c5 ;
1863
1864wire store_inst_c3, store_inst_c4, store_inst_c5;
1865wire fwd_req_ld_c3, fwd_req_ld_c4, fwd_req_ld_c5, fwd_req_ld_c52, fwd_req_ld_c6 ; // BS 03/11/04 extra cycle for mem access
1866wire mcu_l2t_data_vld_r2;
1867
1868wire sel_store_wen;
1869
1870wire fill_vld_c3;
1871
1872wire tag_rdmard_vld_c2, sel_c3_hit_way ;
1873
1874wire ld64_inst_c3, wr64_inst_c3, wr8_inst_c3;
1875wire set_rdma_reg_vld_c3, reset_rdma_reg_vld;
1876wire rd64_complete_c3;
1877wire wr64_hit_complete_c3, wr8_complete_c3;
1878wire rdma_reg_vld_in, rdma_reg_vld;
1879
1880wire [3:0] rdma_cnt_plus1, rdma_cnt;
1881wire rdma_cnt_reset, inc_rdma_cnt_c3;
1882wire set_rdma_reg_vld_c4;
1883wire idle_state_in_l,idle_state_l;
1884wire inc_rdma_cnt_c4;
1885
1886wire reset_rdma_vld_px0_p_in;
1887wire rdma_vld_px0_p_in;
1888wire rdma_vld_px0_p;
1889wire reset_rdma_vld_px1_in ;
1890wire rdma_vld_px1_in, rdma_vld_px1;
1891wire tag_rdma_ev_en_c3;
1892
1893
1894wire tag_fb_hit_c2;
1895wire [15:0] fbd_word_en_c2;
1896wire alt_tag_hit_unqual_c2;
1897wire tag_hit_not_comp_c2;
1898wire alt_tag_miss_unqual_c2;
1899
1900
1901wire sel_rdma_inval_vec_c3, sel_rdma_inval_vec_c4 ;
1902wire tag_rdma_wr_comp_c3;
1903 wire [15:0] dec_word_addr_c1;
1904 wire [1:0] addr5to4_c2;
1905//wire fwd_req_in_c3, fwd_req_in_c4, fwd_req_in_c5 ;
1906wire rmo_st_ack_c3, rmo_st_ack_c4, rmo_st_ack_c5 ;
1907wire inst_mb_c4, inst_mb_c5 ;
1908
1909wire tag_hit_c4;
1910wire st_to_data_array_c3;
1911wire rdma_inst_c3;
1912wire tag_bsc_rd_vld_c3, tag_bsc_rd_vld_c4;
1913wire tag_bsc_rd_vld_c5, tag_bsc_rd_vld_c52, tag_bsc_rd_vld_c6; // BS 03/11/04 extra cycle for mem access
1914
1915
1916wire rd64_complete_c4, rd64_complete_c5, rd64_complete_c52, rd64_complete_c6; // BS 03/11/04 extra cycle for mem access
1917wire rd64_complete_c7, rd64_complete_c8, rd64_complete_c9;
1918wire rd64_complete_c10, rd64_complete_c11 ;
1919
1920wire [3:0] dec_lo_way_sel_c1;
1921wire [3:0] dec_hi_way_sel_c1;
1922wire [3:0] dec_lo_scb_way;
1923wire [3:0] dec_hi_scb_way ;
1924
1925wire dbb_rst_l;
1926wire uerr_ack_tmp_c3,cerr_ack_tmp_c3;
1927wire vld_mbf_miss_c2;
1928wire st_to_data_array_c2;
1929wire [15:0] way_sel_unqual_c2_n;
1930wire [15:0] way_sel_unqual_c2_mod_n; // BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
1931wire [15:0] way_sel_unqual_c2; // BS 03/03/04, fix for Bug 79529
1932wire [15:0] way_sel_unqual_c3; // BS 03/03/04, fix for Bug 79529
1933wire vld_mbf_miss_c2_n;
1934wire prev_rd_wr_c2_1;
1935wire [15:0] tag_hit_way_vld_c2;
1936
1937wire rdma_inst_c2;
1938wire tecc_c3;
1939 wire sel_prev_wen_c1, sel_prev_wen_c2;
1940wire error_ceen_d1, error_nceen_d1;
1941wire pst_with_ctrue_c2;
1942wire ld64_inst_c2;
1943wire wr8_inst_no_ctrue_c2;
1944//wire bist_data_enable_c2;
1945wire col_offset_sel_c2;
1946wire decc_tag_acc_en_px1; // int 5.0 change
1947
1948///////////////////////////////////////////////////////////////////
1949 // Reset flop
1950 ///////////////////////////////////////////////////////////////////
1951
1952//////////////////////////////////////////////////
1953// L1 clk header
1954//////////////////////////////////////////////////
1955assign pce_ov = tcu_pce_ov;
1956assign stop = 1'b0;
1957assign siclk = tcu_aclk;
1958assign soclk = tcu_bclk;
1959assign se = tcu_scan_en;
1960
1961l2t_tag_ctl_l1clkhdr_ctl_macro clkgen (
1962 .l2clk(l2clk),
1963 .l1en(1'b1 ),
1964 .l1clk(l1clk),
1965 .pce_ov(pce_ov),
1966 .stop(stop),
1967 .se(se));
1968
1969//////////////////////////////////////////////////
1970
1971//////////////////////////////////////////
1972// Spare gate insertion
1973//////////////////////////////////////////
1974l2t_tag_ctl_spare_ctl_macro__num_4 spares (
1975 .scan_in(spares_scanin),
1976 .scan_out(spares_scanout),
1977 .l1clk (l1clk),
1978 .siclk(siclk),
1979 .soclk(soclk)
1980);
1981//////////////////////////////////////////
1982
1983
1984
1985l2t_tag_ctl_msff_ctl_macro__width_1 reset_flop
1986 (.dout(dbb_rst_l),
1987 .scan_in(reset_flop_scanin),
1988 .scan_out(reset_flop_scanout),
1989 .l1clk(l1clk),
1990 .din(wmr_l),
1991 .siclk(siclk),
1992 .soclk(soclk)
1993
1994);
1995
1996l2t_tag_ctl_msffi_ctl_macro__width_1 ff_mbist_run
1997 (
1998 .scan_in(ff_mbist_run_scanin),
1999 .scan_out(ff_mbist_run_scanout),
2000 .q_l(mbist_run_r1_n),
2001 .l1clk(l1clk),
2002 .din(mbist_run),
2003 .siclk(siclk),
2004 .soclk(soclk)
2005 );
2006
2007l2t_tag_ctl_msff_ctl_macro__width_1 ff_mbist_arb_l2d_en_d1
2008 (
2009 .scan_in(ff_mbist_arb_l2d_en_d1_scanin),
2010 .scan_out(ff_mbist_arb_l2d_en_d1_scanout),
2011 .din(mbist_arb_l2d_en),
2012 .l1clk(l1clk),
2013 .dout(mbist_arb_l2d_en_d1),
2014 .siclk(siclk),
2015 .soclk(soclk)
2016 );
2017
2018
2019assign csr_l2_bypass_mode_on_qual = mbist_run_r1_n ? csr_l2_bypass_mode_on : 1'b0;
2020
2021l2t_tag_ctl_msff_ctl_macro__width_1 ff_l2_bypass_mode_on
2022 (.din(csr_l2_bypass_mode_on_qual), .l1clk(l1clk),
2023 .scan_in(ff_l2_bypass_mode_on_scanin),
2024 .scan_out(ff_l2_bypass_mode_on_scanout),
2025 .dout(l2_bypass_mode_on_d1),
2026 .siclk(siclk),
2027 .soclk(soclk)
2028);
2029
2030
2031assign arb_fill_vld_c2_in = mbist_run_r1_n ? arb_fill_vld_c2 : 1'b0;
2032
2033l2t_tag_ctl_msff_ctl_macro__width_1 ff_fill_vld_c3
2034 (.din(arb_fill_vld_c2_in), .l1clk(l1clk),
2035 .scan_in(ff_fill_vld_c3_scanin),
2036 .scan_out(ff_fill_vld_c3_scanout),
2037 .dout(fill_vld_c3),
2038 .siclk(siclk),
2039 .soclk(soclk)
2040);
2041
2042////////////////////////////////////////////////////////////////////////////////////
2043// Way Select Logic.
2044// The way chosen for data access is from the following components
2045// * bist way
2046// * diagnostic data access way
2047// * scrub way
2048// * fill way
2049// * hit way C3 ( imiss or an rdma rd i.e.ld64)
2050// * hit way
2051// * lru way for an eviction
2052////////////////////////////////////////////////////////////////////////////////////
2053
2054
2055l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_mux1_way_sel_c1
2056 (.dout (mux1_way_sel_c1[3:0]), // bist or diagnostic way.
2057 .din0(bist_data_enc_way_sel_c1[3:0]), // bist data
2058 .din1(arbadr_arbdp_diag_wr_way_c2[3:0]), // diagnostic
2059 .sel0(bist_data_enable_c1),
2060 .sel1(~bist_data_enable_c1));
2061
2062l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_mux2_way_sel_c1
2063 (.dout (mux2_way_sel_c1[3:0]), // bist/diagnostic or scrub way.
2064 .din0(mux1_way_sel_c1[3:0]), // bist data
2065 .din1(tag_scrub_addr_way[3:0]), // scrub
2066 .sel0(~data_array_acc_active_c1), // no scrub access
2067 .sel1(data_array_acc_active_c1)); // scrub access
2068
2069l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_mux3_way_sel_c1
2070 (.dout (mux3_way_sel_c1[3:0]), // bist/diagnostic/scrub or fill way.
2071 .din0(mux2_way_sel_c1[3:0]), // bist data
2072 .din1(arbdec_arbdp_inst_way_c3[3:0]), // fill way
2073 .sel0(~fill_vld_c3), // fill vld in C2.
2074 .sel1(fill_vld_c3));
2075
2076assign tag_misbuf_par_err_c3 = tagdp_misbuf_par_err_c3 ;
2077
2078assign qual_way_sel_c1 = ( arb_bist_or_diag_acc_c1 | // L2 cache can be OFF.
2079 ( fill_vld_c3 & ~l2_bypass_mode_on_d1 ) | // l2 cache is ON
2080 data_array_acc_active_c1 ) ; // scrub state machine is accessing
2081 // the data $.
2082
2083
2084assign dec_lo_way_sel_c1[0] = ( mux3_way_sel_c1[1:0]==2'd0 )
2085 & qual_way_sel_c1 ;
2086assign dec_lo_way_sel_c1[1] = ( mux3_way_sel_c1[1:0]==2'd1 )
2087 & qual_way_sel_c1 ;
2088assign dec_lo_way_sel_c1[2] = ( mux3_way_sel_c1[1:0]==2'd2 )
2089 & qual_way_sel_c1 ;
2090assign dec_lo_way_sel_c1[3] = ( mux3_way_sel_c1[1:0]==2'd3 )
2091 & qual_way_sel_c1 ;
2092
2093
2094assign dec_hi_way_sel_c1[0] = ( mux3_way_sel_c1[3:2]==2'd0 ) ;
2095
2096assign dec_hi_way_sel_c1[1] = ( mux3_way_sel_c1[3:2]==2'd1 ) ;
2097
2098assign dec_hi_way_sel_c1[2] = ( mux3_way_sel_c1[3:2]==2'd2 ) ;
2099
2100assign dec_hi_way_sel_c1[3] = ( mux3_way_sel_c1[3:2]==2'd3 ) ;
2101
2102
2103
2104assign dec_way_sel_c1[0] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[0] ; // 0000
2105assign dec_way_sel_c1[1] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[1] ; // 0001
2106assign dec_way_sel_c1[2] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[2] ; // 0010
2107assign dec_way_sel_c1[3] = dec_hi_way_sel_c1[0] & dec_lo_way_sel_c1[3] ; // 0011
2108assign dec_way_sel_c1[4] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[0] ; // 0100
2109assign dec_way_sel_c1[5] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[1] ; // 0101
2110assign dec_way_sel_c1[6] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[2] ; // 0110
2111assign dec_way_sel_c1[7] = dec_hi_way_sel_c1[1] & dec_lo_way_sel_c1[3] ; // 0111
2112assign dec_way_sel_c1[8] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[0] ; // 1000
2113assign dec_way_sel_c1[9] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[1] ; // 1001
2114assign dec_way_sel_c1[10] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[2] ; // 1010
2115assign dec_way_sel_c1[11] = dec_hi_way_sel_c1[2] & dec_lo_way_sel_c1[3] ; // 1011
2116assign dec_way_sel_c1[12] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[0] ; // 1100
2117assign dec_way_sel_c1[13] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[1] ; // 1101
2118assign dec_way_sel_c1[14] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[2] ; // 1110
2119assign dec_way_sel_c1[15] = dec_hi_way_sel_c1[3] & dec_lo_way_sel_c1[3] ; // 1111
2120
2121
2122assign arb_decdp_ld64_inst_c1_qual = mbist_run_r1_n ? arb_decdp_ld64_inst_c1 : 1'b0;
2123
2124
2125l2t_tag_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c2
2126 (.din(arb_decdp_ld64_inst_c1_qual), .l1clk(l1clk),
2127 .scan_in(ff_ld64_inst_c2_scanin),
2128 .scan_out(ff_ld64_inst_c2_scanout),
2129 .dout(ld64_inst_c2),
2130 .siclk(siclk),
2131 .soclk(soclk)
2132);
2133
2134
2135assign tag_rdmard_vld_c2 = mbist_run_r1_n ? (ld64_inst_c2 & arb_tag_inst_vld_c2) : 1'b0;
2136
2137assign sel_c3_hit_way = ( arb_imiss_vld_c2
2138 | tag_rdmard_vld_c2 ) &
2139 ~misbuf_tag_hit_unqual_c2 &
2140 ~l2_bypass_mode_on_d1; // int 5.0 changes
2141
2142assign tagctl_l2drpt_mux4_way_sel_c1[15:0] = mux4_way_sel_c1[15:0];
2143
2144// Use a mux flop to reduce setup.
2145l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_mu4_way_sel_c1
2146 (.dout (mux4_way_sel_c1[15:0]), // bist/diag/fill/scrub OR imiss
2147 .din0(dec_way_sel_c1[15:0]), // bist/diag/fill/scrub way decoded
2148 .din1(hit_way_vld_c2[15:0]), // hit way C2
2149 .sel0(~sel_c3_hit_way),
2150 .sel1(sel_c3_hit_way));// imiss or rdma rd vld in C2.
2151
2152l2t_tag_ctl_msff_ctl_macro__width_16 ff_temp_way_sel_c2
2153 (.din(mux4_way_sel_c1[15:0]), .l1clk(l1clk),
2154 .scan_in(ff_temp_way_sel_c2_scanin),
2155 .scan_out(ff_temp_way_sel_c2_scanout),
2156 .dout(temp_way_sel_c2[15:0]),
2157 .siclk(siclk),
2158 .soclk(soclk)
2159);
2160
2161
2162/////////////////////////////////////////////////////////////////
2163// An unqualled version of evict is used to
2164// send the way selects to the data array
2165// If a tag parity error is detected while performing
2166// an eviction pass, the data array is read but, eviction
2167// is not performed during this pass.
2168/////////////////////////////////////////////////////////////////
2169
2170assign arb_evict_vld_c2_qual = mbist_run_r1_n ? arb_evict_vld_c2 : 1'b0;
2171
2172l2t_tag_ctl_msff_ctl_macro__width_1 ff_evict_unqual_vld_c3
2173 (.din(arb_evict_vld_c2_qual), .l1clk(l1clk),
2174 .scan_in(ff_evict_unqual_vld_c3_scanin),
2175 .scan_out(ff_evict_unqual_vld_c3_scanout),
2176 .dout(evict_unqual_vld_c3),
2177 .siclk(siclk),
2178 .soclk(soclk)
2179);
2180
2181/////////////////////////////////////////////////////////////////
2182// An RDMA instruction that is not a PST will not access the
2183// $ or the FB if the rdma reg vld is asserted.
2184/////////////////////////////////////////////////////////////////
2185l2t_tag_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_wr8_no_ctrue_c2
2186 (.din({2{arb_wr8_inst_no_ctrue_c1}}), .l1clk(l1clk),
2187 .scan_in(ff_wr8_no_ctrue_c2_scanin),
2188 .scan_out(ff_wr8_no_ctrue_c2_scanout),
2189 .dout({wr8_inst_no_ctrue_c2_cloned,wr8_inst_no_ctrue_c2}),
2190 .siclk(siclk),
2191 .soclk(soclk)
2192);
2193
2194// isolated the load
2195assign tag_rdma_gate_off_c2_internal = ( rdma_reg_vld & ~wr8_inst_no_ctrue_c2 & rdma_inst_c2 );
2196assign tag_rdma_gate_off_c2 = ( rdma_reg_vld_cloned & ~wr8_inst_no_ctrue_c2_cloned & rdma_inst_c2_cloned );
2197
2198
2199/////////////////////////////////////////////////////////////////
2200// The following signal is sent to vuad dp.
2201// On a miss Buffer hit, the way selects are turned off to prevent
2202// any dirty bit update in the vuad array
2203// critical signals - arb_tag_inst_vld_c2, arb_waysel_gate_c2
2204// arb_arbdp_tag_pst_no_ctrue_c2, rdma_inst_c2
2205// Use higher metal layer for all these signals.
2206/////////////////////////////////////////////////////////////////
2207
2208
2209assign hit_way_vld_c2 = tag_way_sel_c2 & vlddir_vuad_valid_c2 &
2210 {16{arb_waysel_inst_vld_c2 &
2211 ~tag_rdma_gate_off_c2_internal &
2212 arb_waysel_gate_c2 }} ;
2213
2214
2215assign vld_mbf_miss_c2 = ~misbuf_tag_hit_unqual_c2 & arb_waysel_inst_vld_c2;
2216
2217assign tag_hit_way_vld_c2 = hit_way_vld_c2 &
2218 {16{vld_mbf_miss_c2}};
2219
2220l2t_tag_ctl_msff_ctl_macro__width_16 ff_tag_hit_way_vld_c3
2221 (.din(tag_hit_way_vld_c2[15:0]), .l1clk(l1clk),
2222 .scan_in(ff_tag_hit_way_vld_c3_scanin),
2223 .scan_out(ff_tag_hit_way_vld_c3_scanout),
2224 .dout(tag_hit_way_vld_c3[15:0]),
2225 .siclk(siclk),
2226 .soclk(soclk)
2227);
2228
2229//
2230//assign way_sel_unqual_c2_n = mbist_run_r1_n ? (~(temp_way_sel_c2 |
2231// // way for a bist/diag/fill/scrub OR imiss 2nd packet.
2232// ( hit_way_vld_c2 & {16{~l2_bypass_mode_on_d1 & ~ld64_inst_c2 }} )|
2233// // C2 instruction hit way
2234// (tagdp_lru_way_sel_c3 & {16{evict_unqual_vld_c3 &
2235// ~tagdp_tag_par_err_c3 }}))) : ~temp_way_sel_c2 ;
2236
2237
2238assign way_sel_unqual_c2_n = (~(temp_way_sel_c2 |
2239 // way for a bist/diag/fill/scrub OR imiss 2nd packet.
2240 ( hit_way_vld_c2 & {16{~l2_bypass_mode_on_d1 & ~ld64_inst_c2 }} )|
2241 // C2 instruction hit way
2242 (tagdp_lru_way_sel_c3 & {16{evict_unqual_vld_c3 &
2243 ~tagdp_tag_par_err_c3 }})));
2244
2245
2246
2247
2248
2249
2250
2251assign vld_mbf_miss_c2_n = (misbuf_tag_hit_unqual_c2 & arb_waysel_inst_vld_c2) ;
2252
2253assign tag_l2d_way_sel_c2 = ~(way_sel_unqual_c2_n | {16{vld_mbf_miss_c2_n}}) ;
2254 // C2 way select is turned off if the instruction in C2 is a
2255 // mbf hit.
2256//
2257//// BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
2258//assign way_sel_unqual_c2_mod_n = ~(temp_way_sel_c2 |
2259// // way for a bist/diag/fill/scrub OR imiss 2nd packet.
2260// ( hit_way_vld_c2 & {16{~l2_bypass_mode_on_d1 & ~ld64_inst_c2 }} ));
2261//// BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
2262////assign tag_l2d_way_sel_mod_c2 = ~(way_sel_unqual_c2_mod_n | {16{vld_mbf_miss_c2_n}}) ;
2263
2264
2265// BS abd SR 11/18/03 REverse Direcrtory change
2266// L2 way number is being taken to the Directory to be stored along with
2267// Index of hit
2268
2269l2t_tag_ctl_msff_ctl_macro__width_16 ff_tag_l2d_way_sel_c3
2270 (.din(tag_l2d_way_sel_c2[15:0]), .l1clk(l1clk),
2271 .scan_in(ff_tag_l2d_way_sel_c3_scanin),
2272 .scan_out(ff_tag_l2d_way_sel_c3_scanout),
2273 .dout(tag_l2d_way_sel_c3[15:0]),
2274 .siclk(siclk),
2275 .soclk(soclk)
2276);
2277
2278assign way_sel_unqual_c2 = ~(way_sel_unqual_c2_n); // BS 03/03/04, fix for Bug 79529
2279
2280l2t_tag_ctl_msff_ctl_macro__width_16 ff_way_sel_unqual_c3 // BS 03/03/04, fix for Bug 79529
2281 (.din(way_sel_unqual_c2[15:0]), .l1clk(l1clk),
2282 .scan_in(ff_way_sel_unqual_c3_scanin),
2283 .scan_out(ff_way_sel_unqual_c3_scanout),
2284 .dout(way_sel_unqual_c3[15:0]),
2285 .siclk(siclk),
2286 .soclk(soclk)
2287);
2288// BS 03/03/04, fix for Bug 79529 :
2289// in case MB hit in C2 for a store , we may still need to cam the DIr in c5 if the
2290// misbuf_hit_st_dep_zero is true in c3. hence cannot lose way_sel_unqual_c2_n, have to
2291// preserve it in c3 and use this way_sel to cam dir in C5.
2292
2293// timing fix in misbuf
2294assign misbuf_hit_st_dep_zero_qual = misbuf_hit_st_dep_zero & (store_inst_c3 | strstore_inst_c3) ;
2295
2296assign tag_dir_l2way_sel_taghit_c3[0] = misbuf_hit_st_dep_zero_qual ?
2297 (|({way_sel_unqual_c3[1],
2298 way_sel_unqual_c3[3],
2299 way_sel_unqual_c3[5],
2300 way_sel_unqual_c3[7],
2301 way_sel_unqual_c3[9],
2302 way_sel_unqual_c3[11],
2303 way_sel_unqual_c3[13],
2304 way_sel_unqual_c3[15]})) :
2305 (|({tag_l2d_way_sel_c3[1],
2306 tag_l2d_way_sel_c3[3],
2307 tag_l2d_way_sel_c3[5],
2308 tag_l2d_way_sel_c3[7],
2309 tag_l2d_way_sel_c3[9],
2310 tag_l2d_way_sel_c3[11],
2311 tag_l2d_way_sel_c3[13],
2312 tag_l2d_way_sel_c3[15]}));
2313
2314assign tag_dir_l2way_sel_taghit_c3[1] = misbuf_hit_st_dep_zero_qual ?
2315 (|({way_sel_unqual_c3[2],
2316 way_sel_unqual_c3[3],
2317 way_sel_unqual_c3[6],
2318 way_sel_unqual_c3[7],
2319 way_sel_unqual_c3[10],
2320 way_sel_unqual_c3[11],
2321 way_sel_unqual_c3[14],
2322 way_sel_unqual_c3[15]})) :
2323 (|({tag_l2d_way_sel_c3[2],
2324 tag_l2d_way_sel_c3[3],
2325 tag_l2d_way_sel_c3[6],
2326 tag_l2d_way_sel_c3[7],
2327 tag_l2d_way_sel_c3[10],
2328 tag_l2d_way_sel_c3[11],
2329 tag_l2d_way_sel_c3[14],
2330 tag_l2d_way_sel_c3[15]}));
2331
2332assign tag_dir_l2way_sel_taghit_c3[2] = misbuf_hit_st_dep_zero_qual ?
2333 (|({way_sel_unqual_c3[4],
2334 way_sel_unqual_c3[5],
2335 way_sel_unqual_c3[6],
2336 way_sel_unqual_c3[7],
2337 way_sel_unqual_c3[12],
2338 way_sel_unqual_c3[13],
2339 way_sel_unqual_c3[14],
2340 way_sel_unqual_c3[15]})) :
2341 (|({tag_l2d_way_sel_c3[4],
2342 tag_l2d_way_sel_c3[5],
2343 tag_l2d_way_sel_c3[6],
2344 tag_l2d_way_sel_c3[7],
2345 tag_l2d_way_sel_c3[12],
2346 tag_l2d_way_sel_c3[13],
2347 tag_l2d_way_sel_c3[14],
2348 tag_l2d_way_sel_c3[15]}));
2349
2350
2351assign tag_dir_l2way_sel_taghit_c3[3] = misbuf_hit_st_dep_zero_qual ?
2352 (|({way_sel_unqual_c3[8],
2353 way_sel_unqual_c3[9],
2354 way_sel_unqual_c3[10],
2355 way_sel_unqual_c3[11],
2356 way_sel_unqual_c3[12],
2357 way_sel_unqual_c3[13],
2358 way_sel_unqual_c3[14],
2359 way_sel_unqual_c3[15]})) :
2360 (|({tag_l2d_way_sel_c3[8],
2361 tag_l2d_way_sel_c3[9],
2362 tag_l2d_way_sel_c3[10],
2363 tag_l2d_way_sel_c3[11],
2364 tag_l2d_way_sel_c3[12],
2365 tag_l2d_way_sel_c3[13],
2366 tag_l2d_way_sel_c3[14],
2367 tag_l2d_way_sel_c3[15]}));
2368// BS 04/14/04 :
2369// In case of Imiss , since the imiss will cam d$ DIR over 2 back to back cycles, we need to preserve
2370// filbuf_tag_evict_way_c3 for 2 cycles and need to hold filbuf_tag_hit_c3 high over 2 back to back cycles
2371// this is done by oring filbuf_tag_hit_c2 with imiss_vld_c3&filbuf_tag_hit_c3 to create filbuf_tag_hit_c3
2372// and by using imiss_vld_c3 to register filbuf_tag_evict_way_c3 into filbuf_tag_evict_way_c4
2373
2374assign filbuf_tag_hit_c3_tmp = filbuf_tag_hit_c2 | (imiss_vld_c3 & filbuf_tag_hit_c3);
2375assign filbuf_tag_evict_way_c4_in = ({imiss_vld_c3,imiss_vld_c3,imiss_vld_c3,imiss_vld_c3} &
2376 filbuf_tag_evict_way_c3[3:0]);
2377assign filbuf_tag_evict_way_c3_tmp = imiss_vld_c4 ? filbuf_tag_evict_way_c4[3:0] : filbuf_tag_evict_way_c3[3:0];
2378
2379l2t_tag_ctl_msff_ctl_macro__width_5 ff_filbuf_tag_evict_way_c4
2380 (.din({filbuf_tag_evict_way_c4_in[3:0],imiss_vld_c3}), .l1clk(l1clk),
2381 .scan_in(ff_filbuf_tag_evict_way_c4_scanin),
2382 .scan_out(ff_filbuf_tag_evict_way_c4_scanout),
2383 .dout({filbuf_tag_evict_way_c4[3:0],imiss_vld_c4}),
2384 .siclk(siclk),
2385 .soclk(soclk)
2386);
2387
2388l2t_tag_ctl_msff_ctl_macro__width_1 ff_filbuf_tag_hit_c3 // BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Miss
2389 (.din(filbuf_tag_hit_c3_tmp), .l1clk(l1clk),
2390 .scan_in(ff_filbuf_tag_hit_c3_scanin),
2391 .scan_out(ff_filbuf_tag_hit_c3_scanout),
2392 .dout(filbuf_tag_hit_c3),
2393 .siclk(siclk),
2394 .soclk(soclk)
2395);
2396
2397
2398
2399// BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
2400assign evict_sel_c3 = (evict_unqual_vld_c3 & ~tagdp_tag_par_err_c3 & ~arb_vuad_ce_err_c3);
2401assign hit_sel_c3 = ~(evict_sel_c3 | filbuf_tag_hit_c3);
2402assign tagdp_lru_way_sel_enc_c3[0] = |({tagdp_lru_way_sel_c3[1],
2403 tagdp_lru_way_sel_c3[3],
2404 tagdp_lru_way_sel_c3[5],
2405 tagdp_lru_way_sel_c3[7],
2406 tagdp_lru_way_sel_c3[9],
2407 tagdp_lru_way_sel_c3[11],
2408 tagdp_lru_way_sel_c3[13],
2409 tagdp_lru_way_sel_c3[15]});
2410
2411assign tagdp_lru_way_sel_enc_c3[1] = |({tagdp_lru_way_sel_c3[2],
2412 tagdp_lru_way_sel_c3[3],
2413 tagdp_lru_way_sel_c3[6],
2414 tagdp_lru_way_sel_c3[7],
2415 tagdp_lru_way_sel_c3[10],
2416 tagdp_lru_way_sel_c3[11],
2417 tagdp_lru_way_sel_c3[14],
2418 tagdp_lru_way_sel_c3[15]});
2419
2420assign tagdp_lru_way_sel_enc_c3[2] = |({tagdp_lru_way_sel_c3[4],
2421 tagdp_lru_way_sel_c3[5],
2422 tagdp_lru_way_sel_c3[6],
2423 tagdp_lru_way_sel_c3[7],
2424 tagdp_lru_way_sel_c3[12],
2425 tagdp_lru_way_sel_c3[13],
2426 tagdp_lru_way_sel_c3[14],
2427 tagdp_lru_way_sel_c3[15]});
2428
2429assign tagdp_lru_way_sel_enc_c3[3] = |({tagdp_lru_way_sel_c3[8],
2430 tagdp_lru_way_sel_c3[9],
2431 tagdp_lru_way_sel_c3[10],
2432 tagdp_lru_way_sel_c3[11],
2433 tagdp_lru_way_sel_c3[12],
2434 tagdp_lru_way_sel_c3[13],
2435 tagdp_lru_way_sel_c3[14],
2436 tagdp_lru_way_sel_c3[15]});
2437// BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
2438
2439l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_tag_dir_l2way_sel_c3
2440 // BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Miss
2441 (.dout (tag_dir_l2way_sel_c3[3:0]),
2442 .din0(filbuf_tag_evict_way_c3_tmp[3:0]), // LRU way from Filbuf on a load/iftech miss
2443 .din1(tagdp_lru_way_sel_enc_c3[3:0]), // Evict way for an eviction
2444 // BS and SR 12/22/03 , brought out evict way separately to mux for DIr L2 way
2445 .din2(tag_dir_l2way_sel_taghit_c3[3:0]), // Tag hit way from Tag array on a Load hit
2446 .sel0(filbuf_tag_hit_c3),
2447 .sel1(evict_sel_c3),
2448 .sel2(hit_sel_c3));
2449
2450
2451l2t_tag_ctl_msff_ctl_macro__width_4 ff_tag_dir_l2way_sel_c4 // BS and SR 11/18/03 Reverse Directory change
2452 (.din(tag_dir_l2way_sel_c3[3:0]), .l1clk(l1clk),
2453 .scan_in(ff_tag_dir_l2way_sel_c4_scanin),
2454 .scan_out(ff_tag_dir_l2way_sel_c4_scanout),
2455 .dout(tag_dir_l2way_sel_c4[3:0]),
2456 .siclk(siclk),
2457 .soclk(soclk)
2458);
2459
2460
2461
2462
2463
2464
2465
2466//////////////////////////////////////////////////////////////////////
2467// MISS condition for miss buffer insertion.
2468// tag miss is high if all the following conditions are true.
2469// - no tag match
2470// - NOT an interrupt or invalidate instruction.
2471// - NOT a diagnostic instruction
2472// - NOT a tecc instruction
2473// - NOT a cas2 from the xbar.
2474//
2475// The tag_miss_unqual_c2 is also qualified with the
2476// tag_rdma_reg_vld_c2 for a arb_decdp_wr64_inst_c2 so that
2477// we do not "complete" a wr64 miss when it actually encounters
2478// rdma_reg_vld = 1
2479//
2480// The tag_miss_unqual_c2 is only gated off by a wr64 rdma instruction
2481// and not by ld64 or wr8 because in those cases tag_miss_unqual_c2 is
2482// not used as a completion condition but to make a request to
2483// DRAM
2484//////////////////////////////////////////////////////////////////////
2485
2486assign waysel_match_c2 = |( tag_way_sel_c2 & vlddir_vuad_valid_c2 ) ;
2487
2488assign tag_miss_unqual_c2 = (~waysel_match_c2 | l2_bypass_mode_on_d1) & // no way sel match
2489 ~( rdma_reg_vld & arb_decdp_wr64_inst_c2 ) // not a wr64 with rdma_reg_vld
2490 & arb_waysel_gate_c2 ; // int 5.0 changes
2491
2492
2493//////////////////////////////////////////////////////////////////////
2494// A version of tag_miss* that is not gated off by
2495// the tag_rdma_reg_vld_c2 signal. This is used
2496// to indicate "what could have been" if the rdma_reg_vld
2497// was 0.
2498//////////////////////////////////////////////////////////////////////
2499
2500
2501assign alt_tag_miss_unqual_c2 = (~waysel_match_c2 |
2502 l2_bypass_mode_on_d1) // no way sel match
2503 & arb_waysel_gate_c2;
2504
2505l2t_tag_ctl_msff_ctl_macro__width_1 ff_alt_tag_miss_unqual_c3
2506 (.din(alt_tag_miss_unqual_c2), .l1clk(l1clk),
2507 .scan_in(ff_alt_tag_miss_unqual_c3_scanin),
2508 .scan_out(ff_alt_tag_miss_unqual_c3_scanout),
2509 .dout(tag_alt_tag_miss_unqual_c3),
2510 .siclk(siclk),
2511 .soclk(soclk)
2512);
2513
2514/////////////////////////////////////////////////////////////////////
2515// HIT logic
2516// hit way vld is qualified with ~l2_bypass_mode_on_d1
2517// for generating the hit signal.
2518// tag_hit_unqual_c2 is used to delete an instruction from the mbf.
2519//
2520//////////////////////////////////////////////////////////////////////
2521
2522assign tag_hit_unqual_c2 = waysel_match_c2 & arb_waysel_gate_c2 &
2523 ~tag_rdma_gate_off_c2_internal &
2524 ~l2_bypass_mode_on_d1;
2525
2526assign tag_hit_c2 = tag_hit_unqual_c2 & vld_mbf_miss_c2 ;
2527
2528
2529l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_hit_c3
2530 (.din(tag_hit_c2), .l1clk(l1clk),
2531 .scan_in(ff_tag_hit_c3_scanin),
2532 .scan_out(ff_tag_hit_c3_scanout),
2533 .dout(tag_hit_c3),
2534 .siclk(siclk),
2535 .soclk(soclk)
2536);
2537
2538// same as the expression for filbuf_hit_c2 in filbuf.
2539
2540assign tag_fb_hit_c2 = filbuf_tag_hit_frm_mb_c2 & ~tag_rdma_gate_off_c2_internal;
2541
2542assign tag_hit_l2orfb_c2 = ( tag_hit_c2 | tag_fb_hit_c2 ) ;
2543
2544
2545
2546l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_hit_l2orfb_c3
2547 (.din(tag_hit_l2orfb_c2), .l1clk(l1clk),
2548 .scan_in(ff_tag_hit_l2orfb_c3_scanin),
2549 .scan_out(ff_tag_hit_l2orfb_c3_scanout),
2550 .dout(tag_hit_l2orfb_c3),
2551 .siclk(siclk),
2552 .soclk(soclk)
2553);
2554
2555
2556
2557///////////////////////////////////////
2558// If an rdma instruction hitting the
2559// $ is not able to complete because
2560// of tag_rdma_gate_off_c2_internal being ON
2561// that instruction will be inserted in
2562// the Miss Buffer and readied in C7.
2563//
2564// - The insertion condition is taken
2565// care off by looking at rdma_reg_vld & rdma_inst
2566///////////////////////////////////////
2567
2568
2569assign alt_tag_hit_unqual_c2 = waysel_match_c2 & arb_waysel_gate_c2 &
2570 ~l2_bypass_mode_on_d1;
2571
2572assign tag_hit_not_comp_c2 = (( alt_tag_hit_unqual_c2 &
2573 vld_mbf_miss_c2 ) |
2574 filbuf_tag_hit_frm_mb_c2) &
2575 tag_rdma_gate_off_c2_internal ;
2576
2577l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_hit_not_comp_c3
2578 (.din(tag_hit_not_comp_c2), .l1clk(l1clk),
2579 .scan_in(ff_tag_hit_not_comp_c3_scanin),
2580 .scan_out(ff_tag_hit_not_comp_c3_scanout),
2581 .dout(tag_hit_not_comp_c3),
2582 .siclk(siclk),
2583 .soclk(soclk)
2584);
2585
2586
2587
2588
2589///////////////////////////////////////
2590// ** eviction way recorded in the
2591// Miss Buffer and used for a Fill.
2592////////////////////////////////////////
2593
2594assign encoded_lru_way_c3[0] = ( tagdp_lru_way_sel_c3[1] | tagdp_lru_way_sel_c3[3] | tagdp_lru_way_sel_c3[5] |
2595 tagdp_lru_way_sel_c3[7] | tagdp_lru_way_sel_c3[9] | tagdp_lru_way_sel_c3[11] |
2596 tagdp_lru_way_sel_c3[13] | tagdp_lru_way_sel_c3[15] ) ;
2597
2598assign encoded_lru_way_c3[1] = ( tagdp_lru_way_sel_c3[2] | tagdp_lru_way_sel_c3[3] | tagdp_lru_way_sel_c3[6] |
2599 tagdp_lru_way_sel_c3[7] | tagdp_lru_way_sel_c3[10] | tagdp_lru_way_sel_c3[11] |
2600 tagdp_lru_way_sel_c3[14] | tagdp_lru_way_sel_c3[15] );
2601
2602assign encoded_lru_way_c3[2] = ( tagdp_lru_way_sel_c3[4] | tagdp_lru_way_sel_c3[5] | tagdp_lru_way_sel_c3[6] |
2603 tagdp_lru_way_sel_c3[7] | tagdp_lru_way_sel_c3[12] | tagdp_lru_way_sel_c3[13] |
2604 tagdp_lru_way_sel_c3[14] | tagdp_lru_way_sel_c3[15]) ;
2605
2606assign encoded_lru_way_c3[3] = ( tagdp_lru_way_sel_c3[8] | tagdp_lru_way_sel_c3[9] | tagdp_lru_way_sel_c3[10] |
2607 tagdp_lru_way_sel_c3[11] | tagdp_lru_way_sel_c3[12] | tagdp_lru_way_sel_c3[13] |
2608 tagdp_lru_way_sel_c3[14] | tagdp_lru_way_sel_c3[15] ) ;
2609
2610l2t_tag_ctl_msff_ctl_macro__width_4 ff_encoded_lru_c4
2611 (.din(encoded_lru_way_c3[3:0]), .l1clk(l1clk),
2612 .scan_in(ff_encoded_lru_c4_scanin),
2613 .scan_out(ff_encoded_lru_c4_scanout),
2614 .dout(tag_lru_way_c4[3:0]),
2615 .siclk(siclk),
2616 .soclk(soclk)
2617);
2618
2619
2620//////////////////////////////////////////////////////////////////////
2621// COL OFFSET LOGIC
2622// col offset(16B bank accessed ) is dependent on the instruction in the pipe as shown
2623// * bist col offset in C1
2624// * diagnostic data access in C2
2625// * deccck scrub access.
2626// * col offset of an imiss 2nd packet
2627// * fill
2628// * evict
2629// * col offset of the valid instruction in C2.
2630//////////////////////////////////////////////////////////////////////
2631
2632l2t_tag_ctl_msff_ctl_macro__width_2 ff_addr5to4_c2
2633 (.din(arbadr_arbdp_addr5to4_c1[1:0]), .l1clk(l1clk),
2634 .scan_in(ff_addr5to4_c2_scanin),
2635 .scan_out(ff_addr5to4_c2_scanout),
2636 .dout(addr5to4_c2[1:0]),
2637 .siclk(siclk),
2638 .soclk(soclk)
2639);
2640
2641l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_mux1_col_c1
2642 (.dout (mux1_col_offset_c1[1:0]), // bist or diagnostic col.
2643 .din0(bist_data_waddr_c1[3:2]), // bist data
2644 .din1(addr5to4_c2[1:0]), // diagnostic 16B address.
2645 .sel0(bist_data_enable_c1),
2646 .sel1(~bist_data_enable_c1));
2647
2648l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_mux2_col_c1
2649 (.dout (mux2_col_offset_c1[1:0]), // bist/diagnostic or scrub col.
2650 .din0(mux1_col_offset_c1[1:0]), // bist or diag col
2651 .din1(scrub_addr_cnt[2:1]), // scrub
2652 .sel0(~data_array_acc_active_c1), // no scrub access
2653 .sel1(data_array_acc_active_c1));
2654
2655
2656l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_mux3_col_c1
2657 (.dout (mux3_col_offset_c1[1:0]), // bist/diag/scrub or imiss 2nd pckt col.
2658 .din0(mux2_col_offset_c1[1:0]), // bist/diag/scrub
2659 .din1({addr5to4_c2[1],1'b1}), // imiss 2nd packt
2660 .sel0(~arb_imiss_vld_c2), // default
2661 .sel1(arb_imiss_vld_c2)); // imiss 2nd packet active.
2662
2663
2664assign qual_col_offset_c1 = ( arb_imiss_vld_c2 |
2665 arb_bist_or_diag_acc_c1 |
2666 data_array_acc_active_c1 ) ;
2667
2668assign dec_col_offset_prev_c1[0] = ((( mux3_col_offset_c1[1:0] == 2'b00 ) & qual_col_offset_c1 ) |
2669 fill_vld_c3 | tag_rdmard_vld_c2 | arb_evict_vld_c2);
2670
2671assign dec_col_offset_prev_c1[1] = ( ( mux3_col_offset_c1[1:0] == 2'b01 ) & qual_col_offset_c1 ) |
2672 fill_vld_c3 |
2673 tag_rdmard_vld_c2 |
2674 arb_evict_vld_c2 ;
2675assign dec_col_offset_prev_c1[2] = ( ( mux3_col_offset_c1[1:0] == 2'b10 ) & qual_col_offset_c1 ) |
2676 fill_vld_c3 |
2677 tag_rdmard_vld_c2 |
2678 arb_evict_vld_c2 ;
2679assign dec_col_offset_prev_c1[3] = ( ( mux3_col_offset_c1[1:0] == 2'b11 ) & qual_col_offset_c1 ) |
2680 fill_vld_c3 |
2681 tag_rdmard_vld_c2 |
2682 arb_evict_vld_c2 ;
2683
2684assign dec_col_offset_c2[0] = ( addr5to4_c2[1:0] == 2'd0 );
2685assign dec_col_offset_c2[1] = ( addr5to4_c2[1:0] == 2'd1 );
2686assign dec_col_offset_c2[2] = ( addr5to4_c2[1:0] == 2'd2 );
2687assign dec_col_offset_c2[3] = ( addr5to4_c2[1:0] == 2'd3 );
2688
2689l2t_tag_ctl_msff_ctl_macro__width_4 ff_dec_col_offset_prev_c2
2690 (.din(dec_col_offset_prev_c1[3:0]), .l1clk(l1clk),
2691 .scan_in(ff_dec_col_offset_prev_c2_scanin),
2692 .scan_out(ff_dec_col_offset_prev_c2_scanout),
2693 .dout(col_offset_dec_prev_c2[3:0]),
2694 .siclk(siclk),
2695 .soclk(soclk)
2696);
2697
2698//msff_ctl_macro ff_bist_data_enable_c2 (width=1)
2699// (.din(bist_data_enable_c1), .l1clk(l1clk),
2700// .scan_in(ff_bist_data_enable_c2_scanin),
2701// .scan_out(ff_bist_data_enable_c2_scanout),
2702// .dout(bist_data_enable_c2),
2703//);
2704////
2705//msff_ctl_macro ff_arb_inst_vld_c2 (width=1)
2706// (.din(arb_inst_vld_c2_prev), .l1clk(l1clk),
2707// .scan_in(ff_arb_inst_vld_c2_scanin),
2708// .scan_out(ff_arb_inst_vld_c2_scanout),
2709// .dout(arb_inst_vld_c2),
2710//);
2711//
2712//
2713
2714
2715//assign col_offset_sel_c2 = arb_coloff_inst_vld_c2 & ~bist_data_enable_c2 ;
2716
2717assign col_offset_sel_c1 = arb_inst_vld_c2_prev & ~bist_data_enable_c1;
2718//assign col_offset_sel_c1_n = ~col_offset_sel_c1;
2719
2720
2721l2t_tag_ctl_msff_ctl_macro__width_1 ff_col_offset_sel_c2
2722 (.din(col_offset_sel_c1), .l1clk(l1clk),
2723 .scan_in(ff_col_offset_sel_c2_scanin),
2724 .scan_out(ff_col_offset_sel_c2_scanout),
2725 .dout(col_offset_sel_c2),
2726 .siclk(siclk),
2727 .soclk(soclk)
2728);
2729
2730// Big Endian to Little Endian conversion
2731// required to match data array implementation.
2732//
2733//mux_ctl_macro mux_mux4_col_c2 (width=4,ports=2,mux=aonpe)
2734// (.dout ({tag_l2d_col_offset_c2[0],
2735// tag_l2d_col_offset_c2[1],
2736// tag_l2d_col_offset_c2[2],
2737// tag_l2d_col_offset_c2[3]}),
2738// .din0(col_offset_dec_prev_c2[3:0]), // prev instruc col offset
2739// .din1(dec_col_offset_c2[3:0]), // current instruction col offset
2740// .sel0(~col_offset_sel_c2), // sel prev instruc.
2741// .sel1(col_offset_sel_c2)); // sel current instruction
2742// arb_data_diag_st_c2
2743
2744//need to drive the col offset in the desired cycle since
2745// data array then locks the col offset.
2746
2747//assign col_offset_sel_c2_fnl = col_offset_sel_c2 & ~(arb_data_diag_st_c2 | arb_evict_vld_c2 );
2748//assign col_offset_sel_c2_fnl = col_offset_sel_c2 & ~(arb_data_diag_st_c2 | arb_fill_vld_c2);
2749
2750
2751assign col_offset_sel_c2_fnl = col_offset_sel_c2 ;
2752
2753assign col_offset_sel_c2_fnl_n = ~col_offset_sel_c2_fnl;
2754
2755
2756l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_mux4_col_c2
2757 (.dout ({tag_l2d_col_offset_c2[0],
2758 tag_l2d_col_offset_c2[1],
2759 tag_l2d_col_offset_c2[2],
2760 tag_l2d_col_offset_c2[3]}),
2761 .din0(col_offset_dec_prev_c2[3:0]), // prev instruc col offset
2762 .din1(dec_col_offset_c2[3:0]), // current instruction col offset
2763 .sel0(col_offset_sel_c2_fnl_n), // sel prev instruc.
2764 .sel1(col_offset_sel_c2_fnl)); // sel current instruction
2765
2766
2767
2768//////////////////////////////////////////
2769// hold the prev value if col_offset is non-one hot.
2770// This logic is not necessary since l2d uses a default int 5.0 changes
2771//////////////////////////////////////////
2772//
2773//mux_ctl_macro mux_tmp_col_c2 (width=4,ports=2,mux=aonpe)
2774// (.dout (tmp_col_offset_c2[3:0]), // col offset
2775// .din0(col_offset_dec_prev_c2[3:0]), // prev instruc col offset
2776// .din1(dec_col_offset_c2[3:0]), // current instruction col offset
2777// .sel0(~arb_wen_inst_vld_c2), // sel prev instruc.
2778// .sel1(arb_wen_inst_vld_c2)); // sel current instruction
2779//
2780//assign data_hold_c2 = (&(tmp_col_offset_c2)) |
2781// ~(|(tmp_col_offset_c2)) ;
2782//
2783//msff_ctl_macro ff_hold_c3_l (width=1)
2784// (.din(data_hold_c2), .l1clk(l1clk),
2785// .dout(tag_l2d_hold_c3),
2786// .scan_in(),
2787// .scan_out()
2788//);
2789//
2790//
2791//
2792//
2793///////////////////////////////////////////////////////////////////
2794// tag_spc_rd_vld_c7 is asserted to indicate to decc that
2795// a sparc read is active and that any error that is detected in the
2796// data needs to be reported as an L2 read error.
2797///////////////////////////////////////////////////////////////////
2798
2799assign imiss_tag_hit_c3 = imiss_vld_c3 & tag_hit_c3 ;
2800
2801l2t_tag_ctl_msff_ctl_macro__width_1 ff_imiss_tag_hit_c4
2802 (.din(imiss_tag_hit_c3), .l1clk(l1clk),
2803 .scan_in(ff_imiss_tag_hit_c4_scanin),
2804 .scan_out(ff_imiss_tag_hit_c4_scanout),
2805 .dout(imiss_tag_hit_c4),
2806 .siclk(siclk),
2807 .soclk(soclk)
2808);
2809
2810l2t_tag_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_rdma_inst_c2
2811 (.din({2{arbdec_arbdp_rdma_inst_c1}}), .l1clk(l1clk),
2812 .scan_in(ff_rdma_inst_c2_scanin),
2813 .scan_out(ff_rdma_inst_c2_scanout),
2814 .dout({rdma_inst_c2_cloned,rdma_inst_c2}),
2815 .siclk(siclk),
2816 .soclk(soclk)
2817);
2818
2819l2t_tag_ctl_msff_ctl_macro__width_1 ff_rdma_inst_c3
2820 (.din(rdma_inst_c2), .l1clk(l1clk),
2821 .scan_in(ff_rdma_inst_c3_scanin),
2822 .scan_out(ff_rdma_inst_c3_scanout),
2823 .dout(rdma_inst_c3),
2824 .siclk(siclk),
2825 .soclk(soclk)
2826);
2827
2828 ///////////////////////
2829 // ECO fix for bug#5085.
2830 // the signal ff_tagctl_st_to_data_array_c3
2831 // is used only in vuaddp_ctl to set the
2832 // dirty bit in the VUAD. A partial store
2833 // that encounters an uncorrectable error during
2834 // its read, should set the dirty bit in the VUAD
2835 // eventhough the write is disabled.
2836 ///////////////////////
2837
2838 assign dirty_bit_set_c2 = st_to_data_array_c2 | pst_with_ctrue_c2 ;
2839
2840
2841l2t_tag_ctl_msff_ctl_macro__width_1 ff_st_to_data_array_c3
2842 (.din(dirty_bit_set_c2),
2843 .scan_in(ff_st_to_data_array_c3_scanin),
2844 .scan_out(ff_st_to_data_array_c3_scanout),
2845 .l1clk(l1clk), .dout(st_to_data_array_c3),
2846 .siclk(siclk),
2847 .soclk(soclk)
2848);
2849
2850// sparc rd vld is asserted for assertion of sparc errors detected in
2851// the decc datapath.
2852// A rd is valid if
2853// * C3 tag hit and rd is high for a non-rdma, non-pst with ctrue, non cas2 from mb
2854// instruction
2855// * C4 tag hit for an imiss instruction.
2856//
2857// A pst with ctrue ( or a cas2 from mb ) instruction will cause a rd to the $
2858// only if the earlier
2859// read detected an error. Hence, there is no need to detect another error on
2860// its second pass.
2861
2862// tag_spc_rd_cond_c3 is used by filbuf to assert
2863// errors in OFF mode when a PST, SWAP or CAS2 hits
2864// the fill buffer and detects an ERROR.
2865// Read bug#3116.
2866
2867assign tag_spc_rd_cond_c3 = ~pst_with_ctrue_c3 &
2868 ~cas2_from_mb_c3 &
2869 ~st_to_data_array_c3 &
2870 ~rdma_inst_c3 ;
2871
2872
2873assign tag_spc_rd_vld_c3 =
2874 ( tag_hit_c3 & // hitting the $
2875 tag_spc_rd_cond_c3) | imiss_tag_hit_c4 ;
2876
2877l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_spc_rd_vld_c4
2878 (.din(tag_spc_rd_vld_c3), .l1clk(l1clk),
2879 .scan_in(ff_tag_spc_rd_vld_c4_scanin),
2880 .scan_out(ff_tag_spc_rd_vld_c4_scanout),
2881 .dout(tag_spc_rd_vld_c4),
2882 .siclk(siclk),
2883 .soclk(soclk)
2884);
2885l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_spc_rd_vld_c5
2886 (.din(tag_spc_rd_vld_c4), .l1clk(l1clk),
2887 .scan_in(ff_tag_spc_rd_vld_c5_scanin),
2888 .scan_out(ff_tag_spc_rd_vld_c5_scanout),
2889 .dout(tag_spc_rd_vld_c5),
2890 .siclk(siclk),
2891 .soclk(soclk)
2892);
2893// BS 03/11/04 extra cycle for mem access
2894l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_spc_rd_vld_c52
2895 (.din(tag_spc_rd_vld_c5), .l1clk(l1clk),
2896 .scan_in(ff_tag_spc_rd_vld_c52_scanin),
2897 .scan_out(ff_tag_spc_rd_vld_c52_scanout),
2898 .dout(tag_spc_rd_vld_c52),
2899 .siclk(siclk),
2900 .soclk(soclk)
2901);
2902
2903l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_spc_rd_vld_c6
2904 (.din(tag_spc_rd_vld_c52), .l1clk(l1clk),
2905 .scan_in(ff_tag_spc_rd_vld_c6_scanin),
2906 .scan_out(ff_tag_spc_rd_vld_c6_scanout),
2907 .dout(tag_spc_rd_vld_c6),
2908 .siclk(siclk),
2909 .soclk(soclk)
2910);
2911l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_spc_rd_vld_c7
2912 (.din(tag_spc_rd_vld_c6), .l1clk(l1clk),
2913 .scan_in(ff_tag_spc_rd_vld_c7_scanin),
2914 .scan_out(ff_tag_spc_rd_vld_c7_scanout),
2915 .dout(tag_spc_rd_vld_c7),
2916 .siclk(siclk),
2917 .soclk(soclk)
2918);
2919
2920
2921///////////////////////////////////////////////////////////////////
2922// tag_bsc_rd_vld_c7 is asserted to indicate to decc that
2923// a bsc(wr8) read is active and that any error that is detected in the
2924// data needs to be reported as an L2 read error.
2925///////////////////////////////////////////////////////////////////
2926
2927// A Wr8 with ctrue instruction will cause a rd to the $
2928// only if the earlier
2929// read detected an error. Hence, there is no need to detect another error on
2930// its second pass.
2931
2932assign tag_bsc_rd_vld_c3 = ( tag_hit_c3 & // hitting the $
2933 ~st_to_data_array_c3 &
2934 ~pst_with_ctrue_c3 &
2935 wr8_inst_c3 ) ;
2936
2937
2938l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_bsc_rd_vld_c4
2939 (.din(tag_bsc_rd_vld_c3), .l1clk(l1clk),
2940 .scan_in(ff_tag_bsc_rd_vld_c4_scanin),
2941 .scan_out(ff_tag_bsc_rd_vld_c4_scanout),
2942 .dout(tag_bsc_rd_vld_c4),
2943 .siclk(siclk),
2944 .soclk(soclk)
2945);
2946l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_bsc_rd_vld_c5
2947 (.din(tag_bsc_rd_vld_c4), .l1clk(l1clk),
2948 .scan_in(ff_tag_bsc_rd_vld_c5_scanin),
2949 .scan_out(ff_tag_bsc_rd_vld_c5_scanout),
2950 .dout(tag_bsc_rd_vld_c5),
2951 .siclk(siclk),
2952 .soclk(soclk)
2953);
2954// BS 03/11/04 extra cycle for mem access
2955l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_bsc_rd_vld_c52
2956 (.din(tag_bsc_rd_vld_c5), .l1clk(l1clk),
2957 .scan_in(ff_tag_bsc_rd_vld_c52_scanin),
2958 .scan_out(ff_tag_bsc_rd_vld_c52_scanout),
2959 .dout(tag_bsc_rd_vld_c52),
2960 .siclk(siclk),
2961 .soclk(soclk)
2962);
2963
2964l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_bsc_rd_vld_c6
2965 (.din(tag_bsc_rd_vld_c52), .l1clk(l1clk),
2966 .scan_in(ff_tag_bsc_rd_vld_c6_scanin),
2967 .scan_out(ff_tag_bsc_rd_vld_c6_scanout),
2968 .dout(tag_bsc_rd_vld_c6),
2969 .siclk(siclk),
2970 .soclk(soclk)
2971);
2972l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_bsc_rd_vld_c7
2973 (.din(tag_bsc_rd_vld_c6), .l1clk(l1clk),
2974 .scan_in(ff_tag_bsc_rd_vld_c7_scanin),
2975 .scan_out(ff_tag_bsc_rd_vld_c7_scanout),
2976 .dout(tag_bsc_rd_vld_c7),
2977 .siclk(siclk),
2978 .soclk(soclk)
2979);
2980
2981
2982
2983
2984
2985//////////////////////////////////////////
2986// Read Write logic.
2987// Write is set for the following instr.
2988// * Fill,
2989// * diagnostic store.
2990// * data scrub write
2991// * bist write.
2992// * normal write in C2.
2993//////////////////////////////////////////
2994//msff_ctl_macro ff_decdp_tag_wr_c2 (width=1)
2995// (.din(arb_decdp_tag_wr_c1), .l1clk(l1clk),
2996// .scan_in(ff_decdp_tag_wr_c2_scanin),
2997// .scan_out(ff_decdp_tag_wr_c2_scanout),
2998// .dout(tag_wr_c2),
2999//);
3000
3001assign prev_rd_wr_c1 = mbist_run_r1_n ? (fill_vld_c3 | // fill instruction vld
3002 arb_data_diag_st_c2 | // diagnostic store
3003 ( data_array_wr_active_c1 & ~scrub_wr_disable_c9 )) : // scrub write operation
3004 bist_data_wr_enable_c1 ; // bist wr.
3005
3006//
3007//msff_ctl_macro ff_decdp_cas2_from_mb_ctrue_c2 (width=1)
3008// (.din(decdp_cas2_from_mb_ctrue_c1), .l1clk(l1clk),
3009// .scan_in(ff_decdp_cas2_from_mb_ctrue_c2_scanin),
3010// .scan_out(ff_decdp_cas2_from_mb_ctrue_c2_scanout),
3011// .dout(arb_decdp_cas2_from_mb_ctrue_c2),
3012//);
3013//
3014//
3015l2t_tag_ctl_msff_ctl_macro__width_1 ff_prev_rd_wr_c2
3016 (.din(prev_rd_wr_c1), .l1clk(l1clk),
3017 .scan_in(ff_prev_rd_wr_c2_scanin),
3018 .scan_out(ff_prev_rd_wr_c2_scanout),
3019 .dout(prev_rd_wr_c2),
3020 .siclk(siclk),
3021 .soclk(soclk)
3022);
3023
3024l2t_tag_ctl_msff_ctl_macro__width_1 ff_pst_with_ctrue_c2
3025 (.din(arb_tag_pst_with_ctrue_c1), .l1clk(l1clk),
3026 .scan_in(ff_pst_with_ctrue_c2_scanin),
3027 .scan_out(ff_pst_with_ctrue_c2_scanout),
3028 .dout(pst_with_ctrue_c2),
3029 .siclk(siclk),
3030 .soclk(soclk)
3031);
3032
3033// (i)in case of uncorr/notdata err on the data read for a cas1, ctrue bit gets turned off in l2t_misbuf_ctl.sv
3034// this turns off pst_with_ctrue_c2 as arb_tag_pst_with_ctrue_c1 depends on
3035// arbdec_arbdp_inst_ctrue_c1 ( which will be forced to 0). The write is disabled through all terms in the
3036// equation. Note that a corr error on a cas1 will not turn off the Ctrue bit.
3037// (ii)in case of uncorr/notdata err on a swap, the write is disabled by misbuf_uncorr_err_c2. The write is not disabled on corr
3038// error for a swap.
3039// (iii) in case of uncorr/notdata error on a regular store, the write is disabled. The write is not disabled on corr
3040// error for a regular store.
3041
3042
3043assign misbuffer_errors_c1 = (misbuf_uncorr_err_c1 | misbuf_notdata_err_c1);
3044
3045
3046
3047assign other_term_c2_prev = mbist_run_r1_n ? (( arb_decdp_tag_wr_c1 | // non diagnostic, non partial st.
3048 decdp_cas2_from_mb_ctrue_c1 | // cas2 pass
3049 ( arb_tag_pst_with_ctrue_c1 & ~misbuffer_errors_c1 )) & ~arb_inst_diag_c1) : 1'b0;
3050
3051//assign mb_error_c1 = misbuffer_errors_c1 & ~decdp_ic_dc_inval_inst_c1;
3052
3053
3054l2t_tag_ctl_msff_ctl_macro__width_2 ff_mb_errs_c2
3055 (.din({other_term_c2_prev,arb_inst_diag_c1}), .l1clk(l1clk),
3056 .scan_in(ff_mb_errs_c2_scanin),
3057 .scan_out(ff_mb_errs_c2_scanout),
3058 .dout({other_term_c2,arb_inst_diag_c2}),
3059 .siclk(siclk),
3060 .soclk(soclk)
3061);
3062//assign tag_l2d_rd_wr_c2 = ~prev_rd_wr_c2 &
3063// ~(
3064// (
3065// ( tag_wr_c2 ) | // non diagnostic, non partial st.
3066// ( arb_decdp_cas2_from_mb_ctrue_c2 ) | // cas2 pass
3067// ( pst_with_ctrue_c2 & ~misbuffer_errors_c2_fnl )) & // swap/ldstub update pass, store 2nd pass
3068// arb_rdwr_inst_vld_c2 & // instruction vld in C2
3069// ~arb_inst_diag_c2 ) ;
3070//
3071
3072assign tag_l2d_rd_wr_c2 = ~prev_rd_wr_c2 &
3073~( other_term_c2 & arb_rdwr_inst_vld_c2); // & ~arb_inst_diag_c2);
3074
3075
3076
3077
3078
3079
3080
3081//////////////////////////////////////////
3082// tag_st_to_data_array_c2 logic
3083// indicates that a C2 instruction is
3084// going to write into the L2 data array.
3085//////////////////////////////////////////
3086
3087
3088l2t_tag_ctl_msff_ctl_macro__width_1 ff_prev_rd_wr_c2_1
3089 (.din(prev_rd_wr_c1), .l1clk(l1clk),
3090 .scan_in(ff_prev_rd_wr_c2_1_scanin),
3091 .scan_out(ff_prev_rd_wr_c2_1_scanout),
3092 .dout(prev_rd_wr_c2_1),
3093 .siclk(siclk),
3094 .soclk(soclk)
3095);
3096
3097assign st_to_data_array_c2 = ~tag_l2d_rd_wr_c2 & ~prev_rd_wr_c2_1 ;
3098
3099l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_st_to_data_array_c3
3100 (.din(st_to_data_array_c2), .l1clk(l1clk),
3101 .scan_in(ff_tag_st_to_data_array_c3_scanin),
3102 .scan_out(ff_tag_st_to_data_array_c3_scanout),
3103 .dout(tag_st_to_data_array_c3),
3104 .siclk(siclk),
3105 .soclk(soclk)
3106);
3107
3108
3109//////////////////////////////////////////
3110// WORD ENABLE logic.
3111//////////////////////////////////////////
3112
3113
3114 assign bist_word_en_c1[0] = ( bist_data_waddr_c1 == 4'd0 ) ;
3115 assign bist_word_en_c1[1] = ( bist_data_waddr_c1 == 4'd1 ) ;
3116 assign bist_word_en_c1[2] = ( bist_data_waddr_c1 == 4'd2 ) ;
3117 assign bist_word_en_c1[3] = ( bist_data_waddr_c1 == 4'd3 ) ;
3118 assign bist_word_en_c1[4] = ( bist_data_waddr_c1 == 4'd4 ) ;
3119 assign bist_word_en_c1[5] = ( bist_data_waddr_c1 == 4'd5 ) ;
3120 assign bist_word_en_c1[6] = ( bist_data_waddr_c1 == 4'd6 ) ;
3121 assign bist_word_en_c1[7] = ( bist_data_waddr_c1 == 4'd7 ) ;
3122 assign bist_word_en_c1[8] = ( bist_data_waddr_c1 == 4'd8 ) ;
3123 assign bist_word_en_c1[9] = ( bist_data_waddr_c1 == 4'd9 ) ;
3124 assign bist_word_en_c1[10] = ( bist_data_waddr_c1 == 4'd10 ) ;
3125 assign bist_word_en_c1[11] = ( bist_data_waddr_c1 == 4'd11 ) ;
3126 assign bist_word_en_c1[12] = ( bist_data_waddr_c1 == 4'd12 ) ;
3127 assign bist_word_en_c1[13] = ( bist_data_waddr_c1 == 4'd13 ) ;
3128 assign bist_word_en_c1[14] = ( bist_data_waddr_c1 == 4'd14 ) ;
3129 assign bist_word_en_c1[15] = ( bist_data_waddr_c1 == 4'd15 ) ;
3130
3131 assign diag_word_en_c2[0] = word_en_c2[0] & ~arbadr_arbaddr_addr22_c2 ;
3132 assign diag_word_en_c2[1] = word_en_c2[1] & arbadr_arbaddr_addr22_c2 ;
3133 assign diag_word_en_c2[2] = word_en_c2[2] & ~arbadr_arbaddr_addr22_c2 ;
3134 assign diag_word_en_c2[3] = word_en_c2[3] & arbadr_arbaddr_addr22_c2 ;
3135 assign diag_word_en_c2[4] = word_en_c2[4] & ~arbadr_arbaddr_addr22_c2 ;
3136 assign diag_word_en_c2[5] = word_en_c2[5] & arbadr_arbaddr_addr22_c2 ;
3137 assign diag_word_en_c2[6] = word_en_c2[6] & ~arbadr_arbaddr_addr22_c2 ;
3138 assign diag_word_en_c2[7] = word_en_c2[7] & arbadr_arbaddr_addr22_c2 ;
3139 assign diag_word_en_c2[8] = word_en_c2[8] & ~arbadr_arbaddr_addr22_c2 ;
3140 assign diag_word_en_c2[9] = word_en_c2[9] & arbadr_arbaddr_addr22_c2 ;
3141 assign diag_word_en_c2[10] = word_en_c2[10] & ~arbadr_arbaddr_addr22_c2 ;
3142 assign diag_word_en_c2[11] = word_en_c2[11] & arbadr_arbaddr_addr22_c2 ;
3143 assign diag_word_en_c2[12] = word_en_c2[12] & ~arbadr_arbaddr_addr22_c2 ;
3144 assign diag_word_en_c2[13] = word_en_c2[13] & arbadr_arbaddr_addr22_c2 ;
3145 assign diag_word_en_c2[14] = word_en_c2[14] & ~arbadr_arbaddr_addr22_c2 ;
3146 assign diag_word_en_c2[15] = word_en_c2[15] & arbadr_arbaddr_addr22_c2 ;
3147
3148l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_mux1_wen_c1
3149 (.dout (mux1_wen_c1[15:0]), // bist or diagnostic wen.
3150 .din0(bist_word_en_c1[15:0]), // bist wen
3151 .din1(diag_word_en_c2[15:0]), // diagnostic word enable.
3152 .sel0(bist_data_enable_c1),
3153 .sel1(~bist_data_enable_c1));
3154
3155 assign data_ecc_wen_c1[0] = ( scrub_addr_cnt[2:0] == 3'd0 ) ;
3156 assign data_ecc_wen_c1[1] = ( scrub_addr_cnt[2:0] == 3'd0 ) ;
3157 assign data_ecc_wen_c1[2] = ( scrub_addr_cnt[2:0] == 3'd1 ) ;
3158 assign data_ecc_wen_c1[3] = ( scrub_addr_cnt[2:0] == 3'd1 ) ;
3159 assign data_ecc_wen_c1[4] = ( scrub_addr_cnt[2:0] == 3'd2 ) ;
3160 assign data_ecc_wen_c1[5] = ( scrub_addr_cnt[2:0] == 3'd2 ) ;
3161 assign data_ecc_wen_c1[6] = ( scrub_addr_cnt[2:0] == 3'd3 ) ;
3162 assign data_ecc_wen_c1[7] = ( scrub_addr_cnt[2:0] == 3'd3 ) ;
3163 assign data_ecc_wen_c1[8] = ( scrub_addr_cnt[2:0] == 3'd4 ) ;
3164 assign data_ecc_wen_c1[9] = ( scrub_addr_cnt[2:0] == 3'd4 ) ;
3165 assign data_ecc_wen_c1[10] = ( scrub_addr_cnt[2:0] == 3'd5 ) ;
3166 assign data_ecc_wen_c1[11] = ( scrub_addr_cnt[2:0] == 3'd5 ) ;
3167 assign data_ecc_wen_c1[12] = ( scrub_addr_cnt[2:0] == 3'd6 ) ;
3168 assign data_ecc_wen_c1[13] = ( scrub_addr_cnt[2:0] == 3'd6 ) ;
3169 assign data_ecc_wen_c1[14] = ( scrub_addr_cnt[2:0] == 3'd7 ) ;
3170 assign data_ecc_wen_c1[15] = ( scrub_addr_cnt[2:0] == 3'd7 ) ;
3171
3172l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_mux2_wen_c1
3173 (.dout (mux2_wen_c1[15:0]), // bist/diagnostic or scrub wen.
3174 .din0(mux1_wen_c1[15:0]), // bist or diag wen
3175 .din1(data_ecc_wen_c1[15:0]), // scrub
3176 .sel0(arb_bist_or_diag_acc_c1), // bist or diagnostic access.
3177 .sel1(~arb_bist_or_diag_acc_c1));
3178
3179 assign prev_wen_c1 = ( mux2_wen_c1 | {16{fill_vld_c3}}) ;
3180
3181l2t_tag_ctl_msff_ctl_macro__width_16 ff_prev_wen_c1
3182 (.din(prev_wen_c1[15:0]), .l1clk(l1clk),
3183 .scan_in(ff_prev_wen_c1_scanin),
3184 .scan_out(ff_prev_wen_c1_scanout),
3185 .dout(prev_wen_c2[15:0]),
3186 .siclk(siclk),
3187 .soclk(soclk)
3188);
3189
3190
3191 // The delayed word en is picked in the following cases
3192 // bist_data_enable_c1
3193 // diagnostic access c1
3194 // data_array_wr_active_c1
3195 // fill in C3
3196
3197 assign sel_prev_wen_c1 = ( arb_bist_or_diag_acc_c1 | data_array_wr_active_c1 |
3198 fill_vld_c3 ) ;
3199
3200l2t_tag_ctl_msff_ctl_macro__width_1 ff_sel_prev_wen_c2
3201 (.din(sel_prev_wen_c1), .l1clk(l1clk),
3202 .scan_in(ff_sel_prev_wen_c2_scanin),
3203 .scan_out(ff_sel_prev_wen_c2_scanout),
3204 .dout(sel_prev_wen_c2),
3205 .siclk(siclk),
3206 .soclk(soclk)
3207);
3208
3209 // Critical in the generation of wenables.
3210
3211// BS 05/04/04 : taking out upper_four_byte_access and lower_four_byte_access info to word_en_c2[15:0] gen logic in tag_ctl
3212// BE's would be used to control word_en_c2 instead of address bit [2].
3213
3214 assign dec_word_addr_c1[0] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b0001);
3215 assign dec_word_addr_c1[1] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b0001);
3216 assign dec_word_addr_c1[2] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b0011);
3217 assign dec_word_addr_c1[3] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b0011);
3218 assign dec_word_addr_c1[4] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b0101);
3219 assign dec_word_addr_c1[5] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b0101);
3220 assign dec_word_addr_c1[6] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b0111);
3221 assign dec_word_addr_c1[7] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b0111);
3222 assign dec_word_addr_c1[8] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b1001);
3223 assign dec_word_addr_c1[9] = ( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b1001);
3224 assign dec_word_addr_c1[10] =( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b1011);
3225 assign dec_word_addr_c1[11] =( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b1011);
3226 assign dec_word_addr_c1[12] =( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b1101);
3227 assign dec_word_addr_c1[13] =( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b1101);
3228 assign dec_word_addr_c1[14] =( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_lower_four_byte_access_c1} == 4'b1111);
3229 assign dec_word_addr_c1[15] =( {arbadr_arbdp_addr5to4_c1,arbadr_arbdp_addr3to2_c1[1],arb_upper_four_byte_access_c1} == 4'b1111);
3230
3231l2t_tag_ctl_msff_ctl_macro__width_16 ff_dec_word_addr_c2
3232 (.din(word_en_c1[15:0]), .l1clk(l1clk),
3233 .scan_in(ff_dec_word_addr_c2_scanin),
3234 .scan_out(ff_dec_word_addr_c2_scanout),
3235 .dout(word_en_c2[15:0]),
3236 .siclk(siclk),
3237 .soclk(soclk)
3238);
3239
3240 assign word_en_c1[0] = (dec_word_addr_c1[0]) | ( dec_word_addr_c1[1] & arb_arbdp_dword_st_c1 ) ;
3241 assign word_en_c1[1] = (dec_word_addr_c1[1]) | ( dec_word_addr_c1[0] & arb_arbdp_dword_st_c1 ) ;
3242 assign word_en_c1[2] = (dec_word_addr_c1[2]) | ( dec_word_addr_c1[3] & arb_arbdp_dword_st_c1 ) ;
3243 assign word_en_c1[3] = (dec_word_addr_c1[3]) | ( dec_word_addr_c1[2] & arb_arbdp_dword_st_c1 ) ;
3244 assign word_en_c1[4] = (dec_word_addr_c1[4]) | ( dec_word_addr_c1[5] & arb_arbdp_dword_st_c1 ) ;
3245 assign word_en_c1[5] = (dec_word_addr_c1[5]) | ( dec_word_addr_c1[4] & arb_arbdp_dword_st_c1 ) ;
3246 assign word_en_c1[6] = (dec_word_addr_c1[6]) | ( dec_word_addr_c1[7] & arb_arbdp_dword_st_c1 ) ;
3247 assign word_en_c1[7] = (dec_word_addr_c1[7]) | ( dec_word_addr_c1[6] & arb_arbdp_dword_st_c1 ) ;
3248 assign word_en_c1[8] = (dec_word_addr_c1[8]) | ( dec_word_addr_c1[9] & arb_arbdp_dword_st_c1 ) ;
3249 assign word_en_c1[9] = (dec_word_addr_c1[9]) | ( dec_word_addr_c1[8] & arb_arbdp_dword_st_c1 ) ;
3250 assign word_en_c1[10] = (dec_word_addr_c1[10]) | ( dec_word_addr_c1[11] & arb_arbdp_dword_st_c1 ) ;
3251 assign word_en_c1[11] = (dec_word_addr_c1[11]) | ( dec_word_addr_c1[10] & arb_arbdp_dword_st_c1 ) ;
3252 assign word_en_c1[12] = (dec_word_addr_c1[12]) | ( dec_word_addr_c1[13] & arb_arbdp_dword_st_c1 ) ;
3253 assign word_en_c1[13] = (dec_word_addr_c1[13]) | ( dec_word_addr_c1[12] & arb_arbdp_dword_st_c1 ) ;
3254 assign word_en_c1[14] = (dec_word_addr_c1[14]) | ( dec_word_addr_c1[15] & arb_arbdp_dword_st_c1 ) ;
3255 assign word_en_c1[15] = (dec_word_addr_c1[15]) | ( dec_word_addr_c1[14] & arb_arbdp_dword_st_c1 ) ;
3256
3257
3258l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_word_en_c1
3259 (
3260 .dout ({tag_l2d_word_en_c1[0],
3261 tag_l2d_word_en_c1[1],
3262 tag_l2d_word_en_c1[2],
3263 tag_l2d_word_en_c1[3],
3264 tag_l2d_word_en_c1[4],
3265 tag_l2d_word_en_c1[5],
3266 tag_l2d_word_en_c1[6],
3267 tag_l2d_word_en_c1[7],
3268 tag_l2d_word_en_c1[8],
3269 tag_l2d_word_en_c1[9],
3270 tag_l2d_word_en_c1[10],
3271 tag_l2d_word_en_c1[11],
3272 tag_l2d_word_en_c1[12],
3273 tag_l2d_word_en_c1[13],
3274 tag_l2d_word_en_c1[14],
3275 tag_l2d_word_en_c1[15]}),
3276 .din0 (word_en_c1[15:0]),
3277 .din1 (prev_wen_c1[15:0]),
3278 .sel0 (~sel_prev_wen_c1),
3279 .sel1 (sel_prev_wen_c1)
3280 );
3281
3282// flop tag_l2d_word_en_c1
3283l2t_tag_ctl_msff_ctl_macro__dmsff_32x__width_16 ff_dec_word_enable_c2
3284 (
3285 .scan_in(ff_dec_word_enable_c2_scanin),
3286 .scan_out(ff_dec_word_enable_c2_scanout),
3287 .din(tag_l2d_word_en_c1[15:0]),
3288 .l1clk(l1clk),
3289 .dout(tag_l2d_word_en_c2[15:0]),
3290 .siclk(siclk),
3291 .soclk(soclk)
3292 );
3293
3294
3295
3296// word en mux
3297//mux_ctl_macro mux_word_en_c2 (width=16,ports=2,mux=aonpe)
3298// ( .dout ( {tag_l2d_word_en_c2[0],
3299// tag_l2d_word_en_c2[1],
3300// tag_l2d_word_en_c2[2],
3301// tag_l2d_word_en_c2[3],
3302// tag_l2d_word_en_c2[4],
3303// tag_l2d_word_en_c2[5],
3304// tag_l2d_word_en_c2[6],
3305// tag_l2d_word_en_c2[7],
3306// tag_l2d_word_en_c2[8],
3307// tag_l2d_word_en_c2[9],
3308// tag_l2d_word_en_c2[10],
3309// tag_l2d_word_en_c2[11],
3310// tag_l2d_word_en_c2[12],
3311// tag_l2d_word_en_c2[13],
3312// tag_l2d_word_en_c2[14],
3313// tag_l2d_word_en_c2[15]}),
3314// .din0(word_en_c2[15:0]),
3315// .din1(prev_wen_c2[15:0]),
3316// .sel0(~sel_prev_wen_c2),
3317// .sel1(sel_prev_wen_c2));
3318
3319
3320
3321
3322
3323l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_tmp_word_en_c2
3324 ( .dout ( tmp_word_en_c2[15:0]),
3325 .din0(word_en_c2[15:0]),
3326 .din1(prev_wen_c2[15:0]),
3327 .sel0(~sel_prev_wen_c2),
3328 .sel1(sel_prev_wen_c2));
3329
3330
3331
3332
3333
3334////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3335// Scrub Pipeline.
3336// CSR bit[7] is used to determine if scrub mode is ON.
3337// If so { CSR[19:8], 7FFFF } is the scrub frequency.
3338//
3339// A Scrub is initiated by a FIll Operation after a scrub period defined above
3340// expires. Here's the pipeline.
3341// BUG: There is a problem with starting the scrub pipeline when the
3342//
3343// C3
3344//-----------------------------
3345// fill
3346// op with
3347// tecc=1
3348//
3349// start
3350// scrub fsm
3351// cnt=0 cnt=1
3352//
3353//
3354// SCRUB ADDR COUNTER [6:3] = WAY<3:0> ( when way reaches 15, reset the addr counter )
3355// SCRUB ADDR COUNTER [2:0] = 64b address.
3356// BS 07/14/05 : changed Scrub pipeline to take into account C52 stage
3357//------------------------------------------------------------------------------------------------------------------------
3358// cnt= 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3359//-------------------------------------------------------------------------------------------------------------------------
3360// pseudo
3361// stage PX2 C1 C2 C3 C4 C5 C52 C6 C7 C8(px2) C1 c2 C3 C4 C5
3362//-------------------------------------------------------------------------------------------------------------------------
3363// setup tagrd rdout xmit rd1 rd2 rd3 xmit ecc mux mux xmit wr1 wr2
3364// tagrd valid scrub to corr out with
3365// with scrub bit way l2t 64b c1 inst
3366// idx to data
3367// gen l2d
3368// way, perform cnt=0
3369// rd stecc
3370// from & gen
3371// l2d waysel
3372// l2d_wr
3373// & col_off
3374// vbit
3375// & way v1 v2 v3 v4 v5 v6 v7 v8
3376//
3377// scrub c3 c4 c5 c52 c6 c7
3378// way vld
3379//
3380// scrub wr c8 c9
3381// disable
3382//-------------------------------------------------------------------------------------------------------------------------
3383// cnt=1 2
3384//-------------------------------------------------------------------------------------------------------------------------
3385////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3386l2t_tag_ctl_msff_ctl_macro__width_1 ff_tecc_c2
3387 (.din(arbdec_arbdp_tecc_c1), .l1clk(l1clk),
3388 .scan_in(ff_tecc_c2_scanin),
3389 .scan_out(ff_tecc_c2_scanout),
3390 .dout(arb_tecc_c2),
3391 .siclk(siclk),
3392 .soclk(soclk)
3393);
3394
3395
3396assign scrub_fsm_reset = ~dbb_rst_l | ( scrub_fsm_cnt[3:0] == 4'b1101) ; // reset cnt on 13 instead of 12 , as we have C52
3397 // BS : 07/14/05
3398
3399
3400assign scrub_fsm_en = ( (|( scrub_fsm_cnt )) |
3401 (|(scrub_addr_cnt)) |
3402 ( fill_vld_c3 & tecc_c3 ) // trigger for data scb.
3403 ) ;
3404
3405assign scrub_fsm_cnt_plus1 = scrub_fsm_cnt + 4'b1 ;
3406
3407l2t_tag_ctl_msff_ctl_macro__clr_1__en_1__width_4 ff_scrub_fsm_cnt // sync reset active high
3408 (.din(scrub_fsm_cnt_plus1[3:0]),
3409 .scan_in(ff_scrub_fsm_cnt_scanin),
3410 .scan_out(ff_scrub_fsm_cnt_scanout),
3411 .en(scrub_fsm_en), .l1clk(l1clk), .clr(scrub_fsm_reset),
3412 .dout(scrub_fsm_cnt[3:0]),
3413 .siclk(siclk),
3414 .soclk(soclk)
3415);
3416
3417
3418assign scrub_addr_reset = ~dbb_rst_l | //~dbginit_l |
3419// (( scrub_addr_cnt[6:0] == 7'b1011_111 ) &
3420 (( scrub_addr_cnt[6:0] == 7'b1111_111 ) &
3421 ( scrub_fsm_cnt[3:0] == 4'b1101)) ; // After scrubbing the
3422 // last DWORD of way 15. reset
3423 // addr_cnt
3424 // BS : 07/14/05
3425
3426assign scrub_addr_en = ( scrub_fsm_cnt[3:0] == 4'b1101) & ~scrub_addr_reset ; // BS : 07/14/05
3427
3428assign scrub_addr_cnt_plus1 = scrub_addr_cnt + 7'b1 ;
3429
3430l2t_tag_ctl_msff_ctl_macro__clr_1__en_1__width_7 ff_scrub_addr_cnt // sync reset active high
3431 (.din(scrub_addr_cnt_plus1[6:0]),
3432 .scan_in(ff_scrub_addr_cnt_scanin),
3433 .scan_out(ff_scrub_addr_cnt_scanout),
3434 .en(scrub_addr_en), .l1clk(l1clk), .clr(scrub_addr_reset),
3435 .dout(scrub_addr_cnt[6:0]),
3436 .siclk(siclk),
3437 .soclk(soclk)
3438);
3439
3440
3441////////////////////////////////////////////////////////////
3442// The following signal, tag_decc_tag_acc_en_px2 is used
3443// to indicate to arb that a tag access needs to be performed
3444// in the next cycle.
3445////////////////////////////////////////////////////////////
3446
3447// int 5.0 changes
3448// ------------\/ Added the following logic for timing \/-----------
3449
3450assign decc_tag_acc_en_px1 = ( scrub_fsm_cnt[3:0] == 4'b0001 ) &
3451 scrub_fsm_en ;
3452
3453l2t_tag_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_decc_tag_acc_en_px2 // sync reset active high
3454 (.din(decc_tag_acc_en_px1),
3455 .scan_in(ff_decc_tag_acc_en_px2_scanin),
3456 .scan_out(ff_decc_tag_acc_en_px2_scanout),
3457 .en(scrub_fsm_en), .l1clk(l1clk), .clr(scrub_fsm_reset),
3458 .dout(tag_decc_tag_acc_en_px2),
3459 .siclk(siclk),
3460 .soclk(soclk)
3461);
3462
3463//dffre #(1) ff_decc_tag_acc_en_px2 (.din(decc_tag_acc_en_px1),
3464// .en(scrub_fsm_en), .clk(l1clk), .rst(scrub_fsm_reset),
3465// .q(decc_tag_acc_en_px2), .se(se), .si(), .so());
3466//
3467// ------------\/ Added the above logic for timing \/-----------
3468// assign tag_decc_tag_acc_en_px2 = ( scrub_fsm_cnt[3:0] == 4'b0010 ); // int 5.0 changes
3469
3470////////////////////////////////////////////////////////////
3471// The following signal tag_data_ecc_active_c3 is used by arbaddr to select
3472// the deccck idx for tag access
3473////////////////////////////////////////////////////////////
3474
3475assign tag_data_ecc_active_c3 = scrub_fsm_en ;
3476
3477
3478////////////////////////////////////////////////////////////
3479// The waysels, coloffset word_en, set etc are chosen for
3480// a scrub instruction in C1.
3481// Hence, data_array-acc_active_c1 should be set when
3482// the fsm_counter = 3or 12
3483////////////////////////////////////////////////////////////
3484
3485assign data_array_wr_active_c1 = ( scrub_fsm_cnt[3:0] == 4'b1100 ) ; // wr
3486 // BS : 07/14/05
3487assign tag_data_array_wr_active_c1 = data_array_wr_active_c1;
3488
3489assign data_array_acc_active_c1 = mbist_run_r1_n ? (( scrub_fsm_cnt[3:0] == 4'b0011 ) | // rd
3490 data_array_wr_active_c1) : ~mbist_arb_l2d_en_d1;
3491
3492
3493////////////////////////////////////////////////////////////
3494// refer to scrub pipeline
3495// The following signal tag_deccck_data_sel_c8 is used to
3496// select between store data and deccck scrub data.
3497/////////////////////////////////////////////////////////////
3498
3499assign tag_deccck_data_sel_c8 = (scrub_fsm_cnt[3:0] == 4'b1011); // BS : 07/14/05
3500
3501////////////////////////////////////////////////////////////
3502// refer to scrub pipeline
3503// The following signal tag_deccck_addr3_c7 is used to
3504// mux out the DWORD that is being scrubbed.
3505/////////////////////////////////////////////////////////////
3506
3507assign tag_deccck_addr3_c7 = scrub_addr_cnt[0] ;
3508
3509assign tag_scrub_addr_way = scrub_addr_cnt[6:3] ;
3510
3511
3512assign dec_lo_scb_way[0] = ( tag_scrub_addr_way[1:0]==2'd0 );
3513assign dec_lo_scb_way[1] = ( tag_scrub_addr_way[1:0]==2'd1 );
3514assign dec_lo_scb_way[2] = ( tag_scrub_addr_way[1:0]==2'd2 );
3515assign dec_lo_scb_way[3] = ( tag_scrub_addr_way[1:0]==2'd3 );
3516
3517
3518assign dec_hi_scb_way[0] = ( tag_scrub_addr_way[3:2]==2'd0 ) ;
3519assign dec_hi_scb_way[1] = ( tag_scrub_addr_way[3:2]==2'd1 ) ;
3520assign dec_hi_scb_way[2] = ( tag_scrub_addr_way[3:2]==2'd2 ) ;
3521assign dec_hi_scb_way[3] = ( tag_scrub_addr_way[3:2]==2'd3 ) ;
3522
3523 assign dec_scrub_addr_way[0] = dec_hi_scb_way[0] & dec_lo_scb_way[0] ; // 0000
3524 assign dec_scrub_addr_way[1] = dec_hi_scb_way[0] & dec_lo_scb_way[1] ; // 0001
3525 assign dec_scrub_addr_way[2] = dec_hi_scb_way[0] & dec_lo_scb_way[2] ; // 0010
3526 assign dec_scrub_addr_way[3] = dec_hi_scb_way[0] & dec_lo_scb_way[3] ; // 0011
3527 assign dec_scrub_addr_way[4] = dec_hi_scb_way[1] & dec_lo_scb_way[0] ; // 0100
3528 assign dec_scrub_addr_way[5] = dec_hi_scb_way[1] & dec_lo_scb_way[1] ; // 0101
3529 assign dec_scrub_addr_way[6] = dec_hi_scb_way[1] & dec_lo_scb_way[2] ; // 0110
3530 assign dec_scrub_addr_way[7] = dec_hi_scb_way[1] & dec_lo_scb_way[3] ; // 0111
3531 assign dec_scrub_addr_way[8] = dec_hi_scb_way[2] & dec_lo_scb_way[0] ; // 1000
3532 assign dec_scrub_addr_way[9] = dec_hi_scb_way[2] & dec_lo_scb_way[1] ; // 1001
3533 assign dec_scrub_addr_way[10] = dec_hi_scb_way[2] & dec_lo_scb_way[2] ; // 1010
3534 assign dec_scrub_addr_way[11] = dec_hi_scb_way[2] & dec_lo_scb_way[3] ; // 1011
3535 assign dec_scrub_addr_way[12] = dec_hi_scb_way[3] & dec_lo_scb_way[0] ; // 1100
3536 assign dec_scrub_addr_way[13] = dec_hi_scb_way[3] & dec_lo_scb_way[1] ; // 1101
3537 assign dec_scrub_addr_way[14] = dec_hi_scb_way[3] & dec_lo_scb_way[2] ; // 1110
3538 assign dec_scrub_addr_way[15] = dec_hi_scb_way[3] & dec_lo_scb_way[3] ; // 1111
3539
3540
3541assign scrub_way_vld_c2 = |( dec_scrub_addr_way & vlddir_vuad_valid_c2 ) ;
3542
3543l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_way_vld_c3
3544 (.din(scrub_way_vld_c2), .l1clk(l1clk),
3545 .scan_in(ff_scrub_way_vld_c3_scanin),
3546 .scan_out(ff_scrub_way_vld_c3_scanout),
3547 .dout(scrub_way_vld_c3),
3548 .siclk(siclk),
3549 .soclk(soclk)
3550);
3551l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_way_vld_c4
3552 (.din(scrub_way_vld_c3), .l1clk(l1clk),
3553 .scan_in(ff_scrub_way_vld_c4_scanin),
3554 .scan_out(ff_scrub_way_vld_c4_scanout),
3555 .dout(scrub_way_vld_c4),
3556 .siclk(siclk),
3557 .soclk(soclk)
3558);
3559l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_way_vld_c5
3560 (.din(scrub_way_vld_c4), .l1clk(l1clk),
3561 .scan_in(ff_scrub_way_vld_c5_scanin),
3562 .scan_out(ff_scrub_way_vld_c5_scanout),
3563 .dout(scrub_way_vld_c5),
3564 .siclk(siclk),
3565 .soclk(soclk)
3566);
3567// BS 03/11/04 extra cycle for mem access
3568l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_way_vld_c52
3569 (.din(scrub_way_vld_c5), .l1clk(l1clk),
3570 .scan_in(ff_scrub_way_vld_c52_scanin),
3571 .scan_out(ff_scrub_way_vld_c52_scanout),
3572 .dout(scrub_way_vld_c52),
3573 .siclk(siclk),
3574 .soclk(soclk)
3575);
3576l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_way_vld_c6
3577 (.din(scrub_way_vld_c52), .l1clk(l1clk),
3578 .scan_in(ff_scrub_way_vld_c6_scanin),
3579 .scan_out(ff_scrub_way_vld_c6_scanout),
3580 .dout(scrub_way_vld_c6),
3581 .siclk(siclk),
3582 .soclk(soclk)
3583);
3584l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_way_vld_c7
3585 (.din(scrub_way_vld_c6), .l1clk(l1clk),
3586 .scan_in(ff_scrub_way_vld_c7_scanin),
3587 .scan_out(ff_scrub_way_vld_c7_scanout),
3588 .dout(scrub_way_vld_c7),
3589 .siclk(siclk),
3590 .soclk(soclk)
3591);
3592
3593////////////////////////////////////////////////////////////
3594// tag_scrub_rd_vld_c7 indicates to decc that
3595// any error information on data read from the data array
3596// should be reported only if this signal is high
3597////////////////////////////////////////////////////////////
3598
3599// Bug id : 88450
3600// assign tag_scrub_rd_vld_c7 = ( scrub_fsm_cnt[3:0] == 4'b1001 ) & scrub_way_vld_c7 ;
3601assign tag_scrub_rd_vld_c7 = ( scrub_fsm_cnt[3:0] == 4'b1010 ) & scrub_way_vld_c7 ;
3602
3603////////////////////////////////////////////////////////////
3604// scrub write is disabled
3605// if the valid bit of the line being scrubbed is 0,
3606// OR if the read part of the scrub detected a dbit err.
3607// The write operation of a line scrub happens 9 cycles after
3608// the read. The valid bit and error information need to be
3609// staged until the pseudo C1 stage of the WRite operation.
3610////////////////////////////////////////////////////////////
3611l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_rd_vld_c8
3612 (.din(tag_scrub_rd_vld_c7), .l1clk(l1clk),
3613 .scan_in(ff_scrub_rd_vld_c8_scanin),
3614 .scan_out(ff_scrub_rd_vld_c8_scanout),
3615 .dout(scrub_rd_vld_c8),
3616 .siclk(siclk),
3617 .soclk(soclk)
3618);
3619
3620assign scrub_wr_disable_c8 = ~scrub_rd_vld_c8 | deccck_scrd_uncorr_err_c8 ;
3621
3622l2t_tag_ctl_msff_ctl_macro__width_1 ff_scrub_wr_disable_c9
3623 (.din(scrub_wr_disable_c8), .l1clk(l1clk),
3624 .scan_in(ff_scrub_wr_disable_c9_scanin),
3625 .scan_out(ff_scrub_wr_disable_c9_scanout),
3626 .dout(scrub_wr_disable_c9),
3627 .siclk(siclk),
3628 .soclk(soclk)
3629);
3630
3631
3632
3633//////////////////////////////////////////////////////////////////////
3634// Fb data interface.
3635// All fbdata signals are generated in filbuf and flopped here
3636// before transmitting to l2b. THe excetion is wen
3637//////////////////////////////////////////////////////////////////////
3638
3639
3640
3641
3642assign mcu_fbd_wen_r1[0]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd0 ) &
3643 filbuf_mcu_l2t_data_vld_r1;
3644assign mcu_fbd_wen_r1[1]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd0 ) &
3645 filbuf_mcu_l2t_data_vld_r1;
3646assign mcu_fbd_wen_r1[2]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd0 ) &
3647 filbuf_mcu_l2t_data_vld_r1;
3648assign mcu_fbd_wen_r1[3]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd0 ) &
3649 filbuf_mcu_l2t_data_vld_r1;
3650assign mcu_fbd_wen_r1[4]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd1 ) &
3651 filbuf_mcu_l2t_data_vld_r1;
3652assign mcu_fbd_wen_r1[5]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd1 ) &
3653 filbuf_mcu_l2t_data_vld_r1;
3654assign mcu_fbd_wen_r1[6]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd1 ) &
3655 filbuf_mcu_l2t_data_vld_r1;
3656assign mcu_fbd_wen_r1[7]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd1 ) &
3657 filbuf_mcu_l2t_data_vld_r1;
3658assign mcu_fbd_wen_r1[8]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd2 ) &
3659 filbuf_mcu_l2t_data_vld_r1;
3660assign mcu_fbd_wen_r1[9]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd2 ) &
3661 filbuf_mcu_l2t_data_vld_r1;
3662assign mcu_fbd_wen_r1[10]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd2 ) &
3663 filbuf_mcu_l2t_data_vld_r1;
3664assign mcu_fbd_wen_r1[11]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd2 ) &
3665 filbuf_mcu_l2t_data_vld_r1;
3666assign mcu_fbd_wen_r1[12]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd3 ) &
3667 filbuf_mcu_l2t_data_vld_r1;
3668assign mcu_fbd_wen_r1[13]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd3 ) &
3669 filbuf_mcu_l2t_data_vld_r1;
3670assign mcu_fbd_wen_r1[14]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd3 ) &
3671 filbuf_mcu_l2t_data_vld_r1;
3672assign mcu_fbd_wen_r1[15]= ( filbuf_mcu_l2t_chunk_id_r1[1:0] == 2'd3 ) &
3673 filbuf_mcu_l2t_data_vld_r1;
3674
3675//
3676// In off mode, the following instructions are allowed to write to the
3677// FB
3678// - non partial stores/streaming stores or wr8s.
3679// All other instructions are forbidden from writing into the fbf.
3680//
3681
3682assign sel_store_wen = ~filbuf_mcu_l2t_data_vld_r1 &
3683 st_to_data_array_c2
3684 & l2_bypass_mode_on_d1 ;
3685
3686assign fbd_word_en_c2 = tmp_word_en_c2 & {16{tag_fb_hit_c2}} ;
3687
3688l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_fb_word_en_c2
3689 ( .dout ( l2t_l2b_fbwr_wen_r1[15:0]),
3690 .din0(mcu_fbd_wen_r1[15:0]), // mcu data wen logic above
3691 .din1(fbd_word_en_c2[15:0]), // from cache wen logic only asserted when
3692 // Fb hit is high.
3693 .sel0(~sel_store_wen), // mcu data transfer active
3694 .sel1(sel_store_wen));
3695
3696l2t_tag_ctl_msff_ctl_macro__width_16 ff_l2b_fbwr_wen_r2
3697 (.din(l2t_l2b_fbwr_wen_r1[15:0]),
3698 .scan_in(ff_l2b_fbwr_wen_r2_scanin),
3699 .scan_out(ff_l2b_fbwr_wen_r2_scanout),
3700 .l1clk(l1clk),
3701 .dout(l2t_l2b_fbwr_wen_r2[15:0]),
3702 .siclk(siclk),
3703 .soclk(soclk)
3704);
3705
3706
3707/////////////////////////////////////////////////
3708// In L2 off mode, the following signal is
3709// used to select store data over data from DRAM
3710/////////////////////////////////////////////////
3711//
3712//msff_ctl_macro ff_data_vld_r3 (width=1)
3713// (.din(filbuf_mcu_l2t_data_vld_r1), .l1clk(l1clk),
3714// .scan_in(ff_data_vld_r3_scanin),
3715// .scan_out(ff_data_vld_r3_scanout),
3716// .dout(mcu_l2t_data_vld_r2),
3717//);
3718//
3719//assign tag_l2b_fbd_stdatasel_c3 = ~mcu_l2t_data_vld_r2 ;
3720
3721l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_l2b_fbd_stdatasel_c3
3722 (.din(~filbuf_mcu_l2t_data_vld_r1), .l1clk(l1clk),
3723 .scan_in(ff_tag_l2b_fbd_stdatasel_c3_scanin),
3724 .scan_out(ff_tag_l2b_fbd_stdatasel_c3_scanout),
3725 .dout(l2t_l2b_fbd_stdatasel_c3),
3726 .siclk(siclk),
3727 .soclk(soclk)
3728);
3729
3730
3731
3732//////////////////////////////////////////////////////////////////////////
3733// Signals going to oqu.
3734// Imiss return is sent for an imiss hit.
3735//
3736//
3737//////////////////////////////////////////////////////////////////////////
3738
3739
3740l2t_tag_ctl_msff_ctl_macro__width_1 ff_imiss_vld_c3
3741 (.din(arb_imiss_vld_c2), .l1clk(l1clk),
3742 .scan_in(ff_imiss_vld_c3_scanin),
3743 .scan_out(ff_imiss_vld_c3_scanout),
3744 .dout(imiss_vld_c3),
3745 .siclk(siclk),
3746 .soclk(soclk)
3747);
3748
3749assign imiss_hit_c3 = imiss_vld_c3 & tag_hit_l2orfb_c3 ;
3750
3751l2t_tag_ctl_msff_ctl_macro__width_1 ff_imiss_hit_c4
3752 (.din(imiss_hit_c3), .l1clk(l1clk),
3753 .scan_in(ff_imiss_hit_c4_scanin),
3754 .scan_out(ff_imiss_hit_c4_scanout),
3755 .dout(arb_imiss_hit_c4),
3756 .siclk(siclk),
3757 .soclk(soclk)
3758);
3759
3760l2t_tag_ctl_msff_ctl_macro__width_1 ff_imiss_hit_c5
3761 (.din(arb_imiss_hit_c4), .l1clk(l1clk),
3762 .scan_in(ff_imiss_hit_c5_scanin),
3763 .scan_out(ff_imiss_hit_c5_scanout),
3764 .dout(imiss_hit_c5),
3765 .siclk(siclk),
3766 .soclk(soclk)
3767);
3768
3769assign tag_imiss_hit_c5 = imiss_hit_c5 ;
3770/////////////////////////
3771// Ld return packet is sent for the following cases:
3772// - ld hit,
3773// - swap hit first pass.
3774// - cas1 hit
3775/////////////////////////
3776
3777l2t_tag_ctl_msff_ctl_macro__width_1 ff_swap_inst_c3
3778 (.din(arb_decdp_swap_inst_c2), .l1clk(l1clk),
3779 .scan_in(ff_swap_inst_c3_scanin),
3780 .scan_out(ff_swap_inst_c3_scanout),
3781 .dout(swap_inst_c3),
3782 .siclk(siclk),
3783 .soclk(soclk)
3784);
3785
3786l2t_tag_ctl_msff_ctl_macro__width_1 ff_pst_no_ctrue_c3
3787 (.din(arb_arbdp_tag_pst_no_ctrue_c2), .l1clk(l1clk),
3788 .scan_in(ff_pst_no_ctrue_c3_scanin),
3789 .scan_out(ff_pst_no_ctrue_c3_scanout),
3790 .dout(pst_no_ctrue_c3),
3791 .siclk(siclk),
3792 .soclk(soclk)
3793);
3794
3795l2t_tag_ctl_msff_ctl_macro__width_1 ff_cas1_inst_c3
3796 (.din(arb_decdp_cas1_inst_c2), .l1clk(l1clk),
3797 .scan_in(ff_cas1_inst_c3_scanin),
3798 .scan_out(ff_cas1_inst_c3_scanout),
3799 .dout(cas1_inst_c3),
3800 .siclk(siclk),
3801 .soclk(soclk)
3802);
3803
3804l2t_tag_ctl_msff_ctl_macro__width_1 ff_ld_inst_c3
3805 (.din(arb_decdp_ld_inst_c2), .l1clk(l1clk),
3806 .scan_in(ff_ld_inst_c3_scanin),
3807 .scan_out(ff_ld_inst_c3_scanout),
3808 .dout(ld_inst_c3),
3809 .siclk(siclk),
3810 .soclk(soclk)
3811);
3812
3813
3814assign ld_hit_c3 = ( ( swap_inst_c3 & pst_no_ctrue_c3 ) |
3815 cas1_inst_c3 |
3816 ld_inst_c3 ) & tag_hit_l2orfb_c3;
3817
3818
3819l2t_tag_ctl_msff_ctl_macro__width_1 ff_ld_hit_c4
3820 (.din(ld_hit_c3), .l1clk(l1clk),
3821 .scan_in(ff_ld_hit_c4_scanin),
3822 .scan_out(ff_ld_hit_c4_scanout),
3823 .dout(ld_hit_c4),
3824 .siclk(siclk),
3825 .soclk(soclk)
3826);
3827
3828l2t_tag_ctl_msff_ctl_macro__width_1 ff_ld_hit_c5
3829 (.din(ld_hit_c4), .l1clk(l1clk),
3830 .scan_in(ff_ld_hit_c5_scanin),
3831 .scan_out(ff_ld_hit_c5_scanout),
3832 .dout(ld_hit_c5),
3833 .siclk(siclk),
3834 .soclk(soclk)
3835);
3836
3837
3838assign tag_ld_hit_c5 = ld_hit_c5 ;
3839
3840/////////////////////////
3841// St ack is sent for the following cases:
3842// - cas2 from mb hitting the $.
3843// - swap 2nd pass hitting the $
3844// - non-dep store.
3845// - inval instruction
3846// - diagnostic write delayed st ack.
3847// -csr write from miss buffer delayed st ack
3848/////////////////////////
3849
3850l2t_tag_ctl_msff_ctl_macro__width_1 ff_inst_vld_c3
3851 (.din(arb_tag_inst_vld_c2), .l1clk(l1clk),
3852 .scan_in(ff_inst_vld_c3_scanin),
3853 .scan_out(ff_inst_vld_c3_scanout),
3854 .dout(inst_vld_c3),
3855 .siclk(siclk),
3856 .soclk(soclk)
3857);
3858
3859l2t_tag_ctl_msff_ctl_macro__width_1 ff_inst_diag_c3
3860 (.din(arb_inst_diag_c2), .l1clk(l1clk),
3861 .scan_in(ff_inst_diag_c3_scanin),
3862 .scan_out(ff_inst_diag_c3_scanout),
3863 .dout(inst_diag_c3),
3864 .siclk(siclk),
3865 .soclk(soclk)
3866);
3867
3868l2t_tag_ctl_msff_ctl_macro__width_1 ff_inst_mb_c3
3869 (.din(arbdec_arbdp_inst_mb_c2), .l1clk(l1clk),
3870 .scan_in(ff_inst_mb_c3_scanin),
3871 .scan_out(ff_inst_mb_c3_scanout),
3872 .dout(inst_mb_c3),
3873 .siclk(siclk),
3874 .soclk(soclk)
3875);
3876
3877l2t_tag_ctl_msff_ctl_macro__width_1 ff_inst_mb_c4
3878 (.din(inst_mb_c3), .l1clk(l1clk),
3879 .scan_in(ff_inst_mb_c4_scanin),
3880 .scan_out(ff_inst_mb_c4_scanout),
3881 .dout(inst_mb_c4),
3882 .siclk(siclk),
3883 .soclk(soclk)
3884);
3885
3886l2t_tag_ctl_msff_ctl_macro__width_1 ff_inst_mb_c5
3887 (.din(inst_mb_c4), .l1clk(l1clk),
3888 .scan_in(ff_inst_mb_c5_scanin),
3889 .scan_out(ff_inst_mb_c5_scanout),
3890 .dout(inst_mb_c5),
3891 .siclk(siclk),
3892 .soclk(soclk)
3893);
3894
3895
3896assign tag_inst_mb_c5 = inst_mb_c5 ;
3897
3898
3899l2t_tag_ctl_msff_ctl_macro__width_1 ff_misbuf_hit_unqual_c3
3900 (.din(misbuf_tag_hit_unqual_c2), .l1clk(l1clk),
3901 .scan_in(ff_misbuf_hit_unqual_c3_scanin),
3902 .scan_out(ff_misbuf_hit_unqual_c3_scanout),
3903 .dout(misbuf_hit_unqual_c3),
3904 .siclk(siclk),
3905 .soclk(soclk)
3906);
3907
3908l2t_tag_ctl_msff_ctl_macro__width_1 ff_inst_dep_c3
3909 (.din(arbdec_arbdp_inst_dep_c2), .l1clk(l1clk),
3910 .scan_in(ff_inst_dep_c3_scanin),
3911 .scan_out(ff_inst_dep_c3_scanout),
3912 .dout(inst_dep_c3),
3913 .siclk(siclk),
3914 .soclk(soclk)
3915);
3916
3917l2t_tag_ctl_msff_ctl_macro__width_1 ff_store_inst_c3
3918 (.din(arb_decdp_st_inst_c2), .l1clk(l1clk),
3919 .scan_in(ff_store_inst_c3_scanin),
3920 .scan_out(ff_store_inst_c3_scanout),
3921 .dout(store_inst_c3),
3922 .siclk(siclk),
3923 .soclk(soclk)
3924);
3925
3926assign tag_store_inst_c3 = (store_inst_c3 | strstore_inst_c3) ; //BS and SR 11/07/03, store pipelining support
3927
3928l2t_tag_ctl_msff_ctl_macro__width_1 ff_store_inst_c4
3929 (.din(store_inst_c3), .l1clk(l1clk),
3930 .scan_in(ff_store_inst_c4_scanin),
3931 .scan_out(ff_store_inst_c4_scanout),
3932 .dout(store_inst_c4),
3933 .siclk(siclk),
3934 .soclk(soclk)
3935);
3936
3937l2t_tag_ctl_msff_ctl_macro__width_1 ff_store_inst_c5
3938 (.din(store_inst_c4), .l1clk(l1clk),
3939 .scan_in(ff_store_inst_c5_scanin),
3940 .scan_out(ff_store_inst_c5_scanout),
3941 .dout(store_inst_c5),
3942 .siclk(siclk),
3943 .soclk(soclk)
3944);
3945
3946
3947assign tag_store_inst_c5 = store_inst_c5 ; // to oq_dctl.
3948
3949l2t_tag_ctl_msff_ctl_macro__width_1 ff_cas2_from_mb_c3
3950 (.din(arb_decdp_cas2_from_mb_c2), .l1clk(l1clk),
3951 .scan_in(ff_cas2_from_mb_c3_scanin),
3952 .scan_out(ff_cas2_from_mb_c3_scanout),
3953 .dout(cas2_from_mb_c3),
3954 .siclk(siclk),
3955 .soclk(soclk)
3956);
3957
3958l2t_tag_ctl_msff_ctl_macro__width_1 ff_pst_with_ctrue_c3
3959 (.din(pst_with_ctrue_c2), .l1clk(l1clk),
3960 .scan_in(ff_pst_with_ctrue_c3_scanin),
3961 .scan_out(ff_pst_with_ctrue_c3_scanout),
3962 .dout(pst_with_ctrue_c3),
3963 .siclk(siclk),
3964 .soclk(soclk)
3965);
3966
3967l2t_tag_ctl_msff_ctl_macro__width_1 ff_inval_inst_c3
3968 (.din(arb_inval_inst_c2), .l1clk(l1clk),
3969 .scan_in(ff_inval_inst_c3_scanin),
3970 .scan_out(ff_inval_inst_c3_scanout),
3971 .dout(inval_inst_c3),
3972 .siclk(siclk),
3973 .soclk(soclk)
3974);
3975
3976l2t_tag_ctl_msff_ctl_macro__width_1 ff_strstore_c3
3977 (.din (arb_decdp_strst_inst_c2),.l1clk(l1clk),
3978 .scan_in(ff_strstore_c3_scanin),
3979 .scan_out(ff_strstore_c3_scanout),
3980 .dout(strstore_inst_c3),
3981 .siclk(siclk),
3982 .soclk(soclk)
3983);
3984
3985
3986l2t_tag_ctl_msff_ctl_macro__width_1 ff_diag_rd_en_c3
3987 (.din(arb_csr_rd_en_c3), .l1clk(l1clk),
3988 .scan_in(ff_diag_rd_en_c3_scanin),
3989 .scan_out(ff_diag_rd_en_c3_scanout),
3990 .dout(csr_rd_en_c4),
3991 .siclk(siclk),
3992 .soclk(soclk)
3993);
3994
3995l2t_tag_ctl_msff_ctl_macro__width_1 ff_diag_wr_en_c3
3996 (.din(arb_csr_wr_en_c3), .l1clk(l1clk),
3997 .scan_in(ff_diag_wr_en_c3_scanin),
3998 .scan_out(ff_diag_wr_en_c3_scanout),
3999 .dout(csr_wr_en_c4),
4000 .siclk(siclk),
4001 .soclk(soclk)
4002);
4003
4004l2t_tag_ctl_msff_ctl_macro__width_1 ff_diag_complete_c4
4005 (.din(arb_diag_complete_c3), .l1clk(l1clk),
4006 .scan_in(ff_diag_complete_c4_scanin),
4007 .scan_out(ff_diag_complete_c4_scanout),
4008 .dout(diag_complete_c4),
4009 .siclk(siclk),
4010 .soclk(soclk)
4011);
4012
4013l2t_tag_ctl_msff_ctl_macro__width_1 ff_tecc_c3
4014 (.din(arb_tecc_c2), .l1clk(l1clk),
4015 .scan_in(ff_tecc_c3_scanin),
4016 .scan_out(ff_tecc_c3_scanout),
4017 .dout(tecc_c3),
4018 .siclk(siclk),
4019 .soclk(soclk)
4020);
4021
4022// A STore instruction will send an ack if it is
4023// - not issued from the MB and hits the $ and not the miss buffer
4024// - not issued from the mb and misses the $ AND does not encounter
4025// a parity error AND misses the miss buffer.
4026// BS and SR 11/07/03, store pipelining support
4027// - not issued from the MB and misses in the $ , but hits in the Miss Buffer
4028// with all entries having DEP = 0
4029// - not issued from the MB and hits the $ and Miss Buffer with all entries having DEP = 0
4030// BS and SR 11/07/03, store pipelining support
4031// - issued from the MB with DEP=1 and hits the $
4032// - issued from the MB with DEP=1 nd misses the $ AND does not encounter
4033// a parity error.
4034// - not a tag scrub instruction.
4035
4036l2t_tag_ctl_msff_ctl_macro__width_2 ff_tag_hit_unqual_c3
4037 (.din({tag_hit_unqual_c2,misbuf_vuad_ce_instr_ack_c2}), .l1clk(l1clk),
4038 .scan_in(ff_tag_hit_unqual_c3_scanin),
4039 .scan_out(ff_tag_hit_unqual_c3_scanout),
4040 .dout({tag_hit_unqual_c3,misbuf_vuad_ce_instr_ack_c3}),
4041 .siclk(siclk),
4042 .soclk(soclk)
4043);
4044
4045//assign ack_c3 = inst_vld_c3 &
4046// ~tecc_c3 &
4047// ~inst_diag_c3 &
4048// ( ( tag_hit_l2orfb_c3 | ~(tagdp_tag_par_err_c3 & ~tag_hit_unqual_c3) ) &
4049// (( ~inst_mb_c3 & ~misbuf_hit_unqual_c3) | (~inst_mb_c3 & ~tag_hit_unqual_c3 & misbuf_hit_st_dep_zero_qual) |
4050//// BS and SR 11/07/03, store pipelining support
4051//// - not issued from the MB and misses in the $ , but hits in the Miss Buffer
4052//// with DEP bits for all entries it hits aginst being zeroes, fix for bug 81235
4053// inst_dep_c3 )
4054// ) ;
4055//
4056// //( ( ~inst_mb_c3 & ~misbuf_hit_unqual_c3 ) |
4057// //(( misbuf_gate_off_par_err_c3 | // gate off par err for hits
4058// //~tagdp_tag_par_err_c3 )
4059// //& inst_dep_c3 )
4060// //);
4061
4062
4063
4064assign tag_misbuf_ack_c3 = (inst_vld_c3 & ~tecc_c3 & ~inst_diag_c3 &
4065(( tag_hit_l2orfb_c3 | ~(tagdp_tag_par_err_c3 & ~tag_hit_unqual_c3) ) &
4066(( ~inst_mb_c3 & ~misbuf_hit_unqual_c3) |
4067(~inst_mb_c3 &
4068(misbuf_hit_st_dep_zero_qual & ~filbuf_match_c3)) | inst_dep_c3 )));
4069
4070assign ack_c3 = tag_misbuf_ack_c3 & ~arb_vuad_ce_err_c3 ;
4071
4072assign vuad_ce_instr_ack_c3 = misbuf_vuad_ce_instr_ack_c3 & ~arb_vuad_ce_err_c3 & ~evict_unqual_vld_c3
4073 & ~(tagdp_tag_par_err_c3 & ~tag_hit_unqual_c3);
4074
4075assign tag_misbuf_int_ack_c3 = (inst_vld_c3 & ~tecc_c3 & ~inst_diag_c3 &
4076 (( tag_hit_l2orfb_c3 | ~(tagdp_tag_par_err_c3 & ~tag_hit_unqual_c3) )
4077 ));
4078
4079
4080///////////////////////
4081// The following signal is used in oqu to
4082// pick between the dir req vec and dec req vec.
4083///////////////////////
4084// int 4.0 changes
4085//-----\/ FIX for bug#4619 ------ \/
4086// added a ~misbuf_hit_unqual_c3 qualification to
4087// a inval instruction.
4088//-----\/ FIX for bug#4619 ------ \/
4089
4090assign st_ack_c3 = ( store_inst_c3 & (ack_c3 | vuad_ce_instr_ack_c3) ) | // plain store ack
4091 ( ( cas2_from_mb_c3 | // cas2 hit
4092 ( pst_with_ctrue_c3 & swap_inst_c3 ) ) // swap pass2 hit
4093 & tag_hit_l2orfb_c3 ) |
4094 ( inval_inst_c3 & inst_vld_c3 & ~misbuf_hit_unqual_c3 ); // invalidate instr int 5.0 changes
4095
4096// BS and SR 11/12/03 N2 Xbar Packet format change :
4097
4098assign inval_req_c3 = ( inval_inst_c3 & inst_vld_c3 & ~misbuf_arb_hit_c3) ; // invalidate instr
4099// send the inval ack only if it does not hit against anything in the miss buffer.
4100// if it does hit in MB, put the INV instruction into the Miss Buffer and later
4101// issue when the instruction it hit agianst is out of the MB.
4102
4103assign st_inval_ack_c3 = st_ack_c3 | inval_req_c3;
4104
4105l2t_tag_ctl_msff_ctl_macro__width_1 ff_st_ack_c4
4106 (.din(st_inval_ack_c3), .l1clk(l1clk),
4107 .scan_in(ff_st_ack_c4_scanin),
4108 .scan_out(ff_st_ack_c4_scanout),
4109 .dout(st_ack_c4),
4110 .siclk(siclk),
4111 .soclk(soclk)
4112);
4113
4114l2t_tag_ctl_msff_ctl_macro__width_1 ff_st_ack_c5
4115 (.din(st_ack_c4), .l1clk(l1clk),
4116 .scan_in(ff_st_ack_c5_scanin),
4117 .scan_out(ff_st_ack_c5_scanout),
4118 .dout(st_ack_c5),
4119 .siclk(siclk),
4120 .soclk(soclk)
4121);
4122
4123// BS and SR 11/12/03 N2 Xbar Packet format change :
4124l2t_tag_ctl_msff_ctl_macro__width_1 ff_inval_req_c4
4125 (.din(inval_req_c3), .l1clk(l1clk),
4126 .scan_in(ff_inval_req_c4_scanin),
4127 .scan_out(ff_inval_req_c4_scanout),
4128 .dout(inval_req_c4),
4129 .siclk(siclk),
4130 .soclk(soclk)
4131);
4132
4133l2t_tag_ctl_msff_ctl_macro__width_1 ff_inval_ack_c5
4134 (.din(inval_req_c4), .l1clk(l1clk),
4135 .scan_in(ff_inval_ack_c5_scanin),
4136 .scan_out(ff_inval_ack_c5_scanout),
4137 .dout(inval_req_c5),
4138 .siclk(siclk),
4139 .soclk(soclk)
4140);
4141
4142
4143assign tag_st_ack_c5 = st_ack_c5 ;
4144assign tag_inval_req_c5 = inval_req_c5; // BS and SR 11/12/03 N2 Xbar Packet format change
4145
4146
4147l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_hit_c4
4148 (.din(tag_hit_c3), .l1clk(l1clk),
4149 .scan_in(ff_tag_hit_c4_scanin),
4150 .scan_out(ff_tag_hit_c4_scanout),
4151 .dout(tag_hit_c4),
4152 .siclk(siclk),
4153 .soclk(soclk)
4154);
4155
4156l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_hit_c5
4157 (.din(tag_hit_c4), .l1clk(l1clk),
4158 .scan_in(ff_tag_hit_c5_scanin),
4159 .scan_out(ff_tag_hit_c5_scanout),
4160 .dout(tag_hit_c5),
4161 .siclk(siclk),
4162 .soclk(soclk)
4163);
4164
4165
4166
4167
4168///////////////////////
4169// the following signal is used in oqu to
4170// generate the correct request type.
4171///////////////////////
4172
4173assign st_req_c3 = st_ack_c3 | csr_wr_en_c4 |
4174 ( store_inst_c4 & diag_complete_c4 ) ;
4175
4176l2t_tag_ctl_msff_ctl_macro__width_1 ff_st_req_c4
4177 (.din(st_req_c3), .l1clk(l1clk),
4178 .scan_in(ff_st_req_c4_scanin),
4179 .scan_out(ff_st_req_c4_scanout),
4180 .dout(st_req_c4),
4181 .siclk(siclk),
4182 .soclk(soclk)
4183);
4184
4185l2t_tag_ctl_msff_ctl_macro__width_1 ff_st_req_c5
4186 (.din(st_req_c4), .l1clk(l1clk),
4187 .scan_in(ff_st_req_c5_scanin),
4188 .scan_out(ff_st_req_c5_scanout),
4189 .dout(st_req_c5),
4190 .siclk(siclk),
4191 .soclk(soclk)
4192);
4193
4194
4195assign tag_st_req_c5 = st_req_c5 ;
4196
4197//////////////////////////////////////////
4198// DIAG and store data select generation
4199//////////////////////////////////////////
4200
4201// BS and SR 12/22/03, store ack generation for diagnostic store
4202// diagnostic data select mux is being generated and taken out to
4203// l2t_arbdat_dp.sv. For a regular store ack the cpx request gets sent in c7
4204// but for diagnostic ack the cpx request gets sent in c8
4205// This mux select will select the c8 data in case of diagnostic ack or
4206// or c7 data for regular store ack
4207
4208assign sel_diag_store_data_c4 = csr_wr_en_c4 | ( store_inst_c4 & diag_complete_c4 ) ;
4209
4210l2t_tag_ctl_msff_ctl_macro__width_1 ff_sel_diag_store_data_c5
4211 (
4212 .scan_in(ff_sel_diag_store_data_c5_scanin),
4213 .scan_out(ff_sel_diag_store_data_c5_scanout),
4214 .dout (sel_diag_store_data_c5),
4215 .din (sel_diag_store_data_c4),
4216 .l1clk (l1clk),
4217 .siclk(siclk),
4218 .soclk(soclk)
4219
4220);
4221
4222// BS 03/11/04 extra cycle for mem access
4223
4224l2t_tag_ctl_msff_ctl_macro__width_1 ff_sel_diag_store_data_c52
4225 (
4226 .scan_in(ff_sel_diag_store_data_c52_scanin),
4227 .scan_out(ff_sel_diag_store_data_c52_scanout),
4228 .dout (sel_diag_store_data_c52),
4229 .din (sel_diag_store_data_c5),
4230 .l1clk (l1clk),
4231 .siclk(siclk),
4232 .soclk(soclk)
4233
4234);
4235
4236
4237l2t_tag_ctl_msff_ctl_macro__width_1 ff_sel_diag_store_data_c6
4238 (
4239 .scan_in(ff_sel_diag_store_data_c6_scanin),
4240 .scan_out(ff_sel_diag_store_data_c6_scanout),
4241 .dout (sel_diag_store_data_c6),
4242 .din (sel_diag_store_data_c52),
4243 .l1clk (l1clk),
4244 .siclk(siclk),
4245 .soclk(soclk)
4246
4247);
4248
4249l2t_tag_ctl_msff_ctl_macro__width_1 ff_sel_diag_store_data_c7
4250 (
4251 .scan_in(ff_sel_diag_store_data_c7_scanin),
4252 .scan_out(ff_sel_diag_store_data_c7_scanout),
4253 .dout (sel_diag_store_data_c7),
4254 .din (sel_diag_store_data_c6),
4255 .l1clk (l1clk),
4256 .siclk(siclk),
4257 .soclk(soclk)
4258
4259);
4260
4261//msff_ctl_macro ff_sel_diag_store_data_c8 (width=1)
4262// (
4263// .scan_in(ff_sel_diag_store_data_c8_scanin),
4264// .scan_out(ff_sel_diag_store_data_c8_scanout),
4265// .dout (sel_diag_store_data_c8),
4266// .din (sel_diag_store_data_c7),
4267// .l1clk (l1clk),
4268//
4269//);
4270//
4271
4272///////////////////////
4273// streaming store ack
4274///////////////////////
4275
4276assign strst_ack_c3 = strstore_inst_c3 & (ack_c3 | vuad_ce_instr_ack_c3);
4277
4278l2t_tag_ctl_msff_ctl_macro__width_1 ff_strst_ack_c4
4279 (.din(strst_ack_c3), .l1clk(l1clk),
4280 .scan_in(ff_strst_ack_c4_scanin),
4281 .scan_out(ff_strst_ack_c4_scanout),
4282 .dout(strst_ack_c4),
4283 .siclk(siclk),
4284 .soclk(soclk)
4285);
4286
4287l2t_tag_ctl_msff_ctl_macro__width_1 ff_strst_ack_c5
4288 (.din(strst_ack_c4), .l1clk(l1clk),
4289 .scan_in(ff_strst_ack_c5_scanin),
4290 .scan_out(ff_strst_ack_c5_scanout),
4291 .dout(strst_ack_c5),
4292 .siclk(siclk),
4293 .soclk(soclk)
4294);
4295
4296assign tag_strst_ack_c5 = strst_ack_c5 ;
4297
4298//////////////////////
4299// rmo store ack
4300/////////////////////
4301
4302assign rmo_st_ack_c3 = arb_decdp_rmo_st_c3 & (ack_c3 | vuad_ce_instr_ack_c3);
4303
4304l2t_tag_ctl_msff_ctl_macro__width_1 ff_rmo_st_ack_c4
4305 (.din(rmo_st_ack_c3), .l1clk(l1clk),
4306 .scan_in(ff_rmo_st_ack_c4_scanin),
4307 .scan_out(ff_rmo_st_ack_c4_scanout),
4308 .dout(rmo_st_ack_c4),
4309 .siclk(siclk),
4310 .soclk(soclk)
4311);
4312
4313l2t_tag_ctl_msff_ctl_macro__width_1 ff_rmo_st_ack_c5
4314 (.din(rmo_st_ack_c4), .l1clk(l1clk),
4315 .scan_in(ff_rmo_st_ack_c5_scanin),
4316 .scan_out(ff_rmo_st_ack_c5_scanout),
4317 .dout(rmo_st_ack_c5),
4318 .siclk(siclk),
4319 .soclk(soclk)
4320);
4321
4322assign tag_rmo_st_ack_c5 = rmo_st_ack_c5;
4323
4324
4325
4326///////////////////////
4327// diag or csr complete( non memory )
4328///////////////////////
4329
4330assign nonmem_comp_c4 = diag_complete_c4 |
4331 csr_wr_en_c4 |
4332 csr_rd_en_c4 ;
4333
4334l2t_tag_ctl_msff_ctl_macro__width_1 ff_nonmem_comp_c5
4335 (.din(nonmem_comp_c4), .l1clk(l1clk),
4336 .scan_in(ff_nonmem_comp_c5_scanin),
4337 .scan_out(ff_nonmem_comp_c5_scanout),
4338 .dout(nonmem_comp_c5),
4339 .siclk(siclk),
4340 .soclk(soclk)
4341);
4342
4343// BS 03/11/04 extra cycle for mem access
4344
4345l2t_tag_ctl_msff_ctl_macro__width_1 ff_nonmem_comp_c52
4346 (.din(nonmem_comp_c5), .l1clk(l1clk),
4347 .scan_in(ff_nonmem_comp_c52_scanin),
4348 .scan_out(ff_nonmem_comp_c52_scanout),
4349 .dout(nonmem_comp_c52),
4350 .siclk(siclk),
4351 .soclk(soclk)
4352);
4353
4354l2t_tag_ctl_msff_ctl_macro__width_1 ff_nonmem_comp_c6
4355 (.din(nonmem_comp_c52), .l1clk(l1clk),
4356 .scan_in(ff_nonmem_comp_c6_scanin),
4357 .scan_out(ff_nonmem_comp_c6_scanout),
4358 .dout(nonmem_comp_c6),
4359 .siclk(siclk),
4360 .soclk(soclk)
4361);
4362
4363assign tag_nonmem_comp_c6 = nonmem_comp_c6 ;
4364
4365////////////////////////////////////////////////////
4366//
4367// correctable and non correctable err ack
4368//
4369// - When a PST instruction makes its second pass
4370// an error indication is sent to spcX Ty.
4371//
4372// (Atomics are not included in this because
4373// the load part of the atomic sends an error similar
4374// to loads.)
4375//
4376// - A fill will also send an error indication
4377// to SPc0 T0 if the uncorr/err bit is set
4378// in filbuf
4379//
4380////////////////////////////////////////////////////
4381
4382// POST_2.0 additions.
4383// tagcl_?err_ack is asserted to
4384// send an error packet to a sparc
4385// for partial stores.
4386//
4387// Wr8s need to be excluded from this
4388// since they differ from regular stores
4389// in the following aspect.
4390// regular stores send an ack/inval packet
4391// when they make their first non-dependent
4392// pass down the pipe.
4393// wr8s send an invalidate(eviction) packet
4394// when they make their final pass down the pipe
4395// Hence the error indication needs to be sent
4396// along with a fill instead of being sent with
4397// the 2nd pass of a store.
4398
4399
4400
4401
4402l2t_tag_ctl_msff_ctl_macro__width_1 ff_st_with_ctrue_c3
4403 (.din(arb_decdp_st_with_ctrue_c2), .l1clk(l1clk),
4404 .scan_in(ff_st_with_ctrue_c3_scanin),
4405 .scan_out(ff_st_with_ctrue_c3_scanout),
4406 .dout(st_with_ctrue_c3),
4407 .siclk(siclk),
4408 .soclk(soclk)
4409);
4410
4411l2t_tag_ctl_msff_ctl_macro__width_2 ff_misbuf_uerr_c3
4412 (.din({misbuf_uncorr_err_c2,misbuf_notdata_err_c2}), .l1clk(l1clk),
4413 .scan_in(ff_misbuf_uerr_c3_scanin),
4414 .scan_out(ff_misbuf_uerr_c3_scanout),
4415 .dout({misbuf_uerr_c3,misbuf_nderr_c3}),
4416 .siclk(siclk),
4417 .soclk(soclk)
4418);
4419
4420l2t_tag_ctl_msff_ctl_macro__width_1 ff_misbuf_cerr_c3
4421 (.din(misbuf_corr_err_c2), .l1clk(l1clk),
4422 .scan_in(ff_misbuf_cerr_c3_scanin),
4423 .scan_out(ff_misbuf_cerr_c3_scanout),
4424 .dout(misbuf_cerr_c3),
4425 .siclk(siclk),
4426 .soclk(soclk)
4427);
4428
4429//
4430//msff_ctl_macro ff_arb_oqu_swap_cas2_req_c3 (width=1)
4431// (.din(arb_oqu_swap_cas2_req_c2), .l1clk(l1clk),
4432// .scan_in(ff_arb_oqu_swap_cas2_req_c3_scanin),
4433// .scan_out(ff_arb_oqu_swap_cas2_req_c3_scanout),
4434// .dout(arb_oqu_swap_cas2_req_c3),
4435//);
4436
4437
4438// tag_hit_c3 is used to qualify st_with_ctrue_c3.
4439// st_with_ctrue_c3 is qualfied everywhere else.
4440// Bug # 3528: 6/26/2003
4441// The qualification with tag_hit_c3 instead of tag_hit_l2orfb_c3 assumes that
4442// the $ is turned ON. THis causes ?err_ack_tmp_c3 to be deasserted for psts in OFF
4443// mode. This has been changed to tag_hit_l2orfb_c3 to solve the problem.
4444// Nodata would have both misbuf_uerr_c3,misbuf_cerr_c3 = 1.
4445
4446assign uerr_ack_tmp_c3 = ((misbuf_uerr_c3 | misbuf_nderr_c3) & st_with_ctrue_c3 & tag_hit_l2orfb_c3 &
4447 inst_vld_c3) | filbuf_dis_uerr_c3 | filbuf_dis_nderr_c3[1] ;
4448
4449l2t_tag_ctl_msff_ctl_macro__width_2 ff_uerr_ack_tmp_c4
4450 (.din({uerr_ack_tmp_c3,misbuf_nderr_c3}), .l1clk(l1clk),
4451 .scan_in(ff_uerr_ack_tmp_c4_scanin),
4452 .scan_out(ff_uerr_ack_tmp_c4_scanout),
4453 .dout({tag_uerr_ack_tmp_c4,misbuf_nderr_c4}),
4454 .siclk(siclk),
4455 .soclk(soclk)
4456);
4457
4458assign uerr_ack_c3 = uerr_ack_tmp_c3 & ~wr8_inst_c3 ;
4459
4460l2t_tag_ctl_msff_ctl_macro__width_1 ff_uerr_ack_c4
4461 (.din(uerr_ack_c3), .l1clk(l1clk),
4462 .scan_in(ff_uerr_ack_c4_scanin),
4463 .scan_out(ff_uerr_ack_c4_scanout),
4464 .dout(uerr_ack_c4),
4465 .siclk(siclk),
4466 .soclk(soclk)
4467);
4468
4469l2t_tag_ctl_msff_ctl_macro__width_2 ff_uerr_ack_c5
4470 (.din({misbuf_nderr_c4,uerr_ack_c4}), .l1clk(l1clk),
4471 .scan_in(ff_uerr_ack_c5_scanin),
4472 .scan_out(ff_uerr_ack_c5_scanout),
4473 .dout({misbuf_nderr_c5,uerr_ack_c5}),
4474 .siclk(siclk),
4475 .soclk(soclk)
4476);
4477
4478// Reporting of errors to the sparc depends on the csr_error_ceen
4479// and csr_error_nceen bits. If these bits are turned off, the spc
4480// does not reveive any errors from the L2.
4481// There is one caveat. The error that causes tag_uerr_ack_c5
4482// or tag_cerr_ack_c5 to go HIGH may have occurred before
4483// or after the changing of error_Ceen and csr_error_nceen bits.
4484
4485
4486l2t_tag_ctl_msff_ctl_macro__width_1 ff_error_ceen_d1
4487 (.dout (error_ceen_d1), .din (csr_error_ceen),
4488 .scan_in(ff_error_ceen_d1_scanin),
4489 .scan_out(ff_error_ceen_d1_scanout),
4490 .l1clk (l1clk),
4491 .siclk(siclk),
4492 .soclk(soclk)
4493 );
4494
4495l2t_tag_ctl_msff_ctl_macro__width_1 ff_error_nceen_d1
4496 (
4497 .scan_in(ff_error_nceen_d1_scanin),
4498 .scan_out(ff_error_nceen_d1_scanout),
4499 .dout (error_nceen_d1), .din (csr_error_nceen),
4500 .l1clk (l1clk),
4501 .siclk(siclk),
4502 .soclk(soclk)
4503 );
4504
4505
4506assign tag_uerr_ack_c5 = (uerr_ack_c5 & error_nceen_d1) |
4507 (misbuf_nderr_c5 | filbuf_dis_nderr_c5[1]) & error_nceen_d1;
4508
4509// tag_hit_c3 is used to qualify st_with_ctrue_c3.
4510// st_with_ctrue_c3 is qualfied everywhere else.
4511// Bug # 3528: 6/26/2003
4512// The qualification with tag_hit_c3 instead of tag_hit_l2orfb_c3 assumes that
4513// the $ is turned ON. THis causes ?err_ack_tmp_c3 to be deasserted for psts in OFF
4514// mode. This has been changed to tag_hit_l2orfb_c3 to solve the problem.
4515// Nodata would have both misbuf_uerr_c3,misbuf_cerr_c3 = 1.
4516//
4517//assign cerr_ack_tmp_c3 = (((misbuf_cerr_c3 & ~(misbuf_uerr_c3 & error_nceen_d1)) |
4518// misbuf_nderr_c3) & st_with_ctrue_c3 & tag_hit_l2orfb_c3 & inst_vld_c3 ) |
4519// (filbuf_dis_cerr_c3 & ~(filbuf_dis_uerr_c3 & error_nceen_d1)) | filbuf_dis_nderr_c3[0];
4520//
4521
4522
4523
4524assign cerr_ack_tmp_c3 = ((misbuf_cerr_c3 & ~(misbuf_uerr_c3 & error_nceen_d1))
4525 & st_with_ctrue_c3 & tag_hit_l2orfb_c3 & inst_vld_c3 ) |
4526 (filbuf_dis_cerr_c3 & ~(filbuf_dis_uerr_c3 & error_nceen_d1));
4527
4528
4529
4530
4531l2t_tag_ctl_msff_ctl_macro__width_1 ff_cerr_ack_tmp_c4
4532 (.din(cerr_ack_tmp_c3), .l1clk(l1clk),
4533 .scan_in(ff_cerr_ack_tmp_c4_scanin),
4534 .scan_out(ff_cerr_ack_tmp_c4_scanout),
4535 .dout(tag_cerr_ack_tmp_c4),
4536 .siclk(siclk),
4537 .soclk(soclk)
4538);
4539
4540assign cerr_ack_c3 = cerr_ack_tmp_c3 & ~wr8_inst_c3 ;
4541
4542l2t_tag_ctl_msff_ctl_macro__width_1 ff_cerr_ack_c4
4543 (.din(cerr_ack_c3), .l1clk(l1clk),
4544 .scan_in(ff_cerr_ack_c4_scanin),
4545 .scan_out(ff_cerr_ack_c4_scanout),
4546 .dout(cerr_ack_c4),
4547 .siclk(siclk),
4548 .soclk(soclk)
4549);
4550
4551l2t_tag_ctl_msff_ctl_macro__width_1 ff_cerr_ack_c5
4552 (.din(cerr_ack_c4), .l1clk(l1clk),
4553 .scan_in(ff_cerr_ack_c5_scanin),
4554 .scan_out(ff_cerr_ack_c5_scanout),
4555 .dout(cerr_ack_c5),
4556 .siclk(siclk),
4557 .soclk(soclk)
4558);
4559
4560assign tag_cerr_ack_c5 = (cerr_ack_c5 & error_ceen_d1) |
4561 (misbuf_nderr_c5 | filbuf_dis_nderr_c5[0]) & error_nceen_d1 ;
4562
4563
4564// computing notdata error reporting
4565
4566l2t_tag_ctl_msff_ctl_macro__width_4 ff_dis_nderr_c5
4567 (
4568 .scan_in(ff_dis_nderr_c5_scanin),
4569 .scan_out(ff_dis_nderr_c5_scanout),
4570 .din({filbuf_dis_nderr_c3[1:0],filbuf_dis_nderr_c4[1:0]}),
4571 .l1clk(l1clk),
4572 .dout({filbuf_dis_nderr_c4[1:0],filbuf_dis_nderr_c5[1:0]}),
4573 .siclk(siclk),
4574 .soclk(soclk)
4575 );
4576
4577
4578
4579//////////////////////
4580//
4581// interrupt acknowledgement
4582//
4583//////////////////////
4584
4585
4586l2t_tag_ctl_msff_ctl_macro__width_1 ff_inst_int_c3
4587 (.din(arb_decdp_inst_int_c2), .l1clk(l1clk),
4588 .scan_in(ff_inst_int_c3_scanin),
4589 .scan_out(ff_inst_int_c3_scanout),
4590 .dout(inst_int_c3),
4591 .siclk(siclk),
4592 .soclk(soclk)
4593);
4594
4595assign int_ack_c3 = inst_int_c3 & inst_vld_c3 ;
4596
4597l2t_tag_ctl_msff_ctl_macro__width_1 ff_int_ack_c4
4598 (.din(int_ack_c3), .l1clk(l1clk),
4599 .scan_in(ff_int_ack_c4_scanin),
4600 .scan_out(ff_int_ack_c4_scanout),
4601 .dout(int_ack_c4),
4602 .siclk(siclk),
4603 .soclk(soclk)
4604);
4605
4606l2t_tag_ctl_msff_ctl_macro__width_1 ff_int_ack_c5
4607 (.din(int_ack_c4), .l1clk(l1clk),
4608 .scan_in(ff_int_ack_c5_scanin),
4609 .scan_out(ff_int_ack_c5_scanout),
4610 .dout(int_ack_c5),
4611 .siclk(siclk),
4612 .soclk(soclk)
4613);
4614
4615assign tag_int_ack_c5 = int_ack_c5 ;
4616
4617///////////////////////
4618//
4619// fwd req return :
4620// 1. A diag fwd req will
4621// send a delayed(1cyc) reponse.
4622// 2. A non-diag fwd req will send its response
4623// similar to any other request in C8
4624//
4625///////////////////////
4626
4627
4628
4629
4630l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_c3
4631 (.din(arb_decdp_fwd_req_c2), .l1clk(l1clk),
4632 .scan_in(ff_fwd_req_c3_scanin),
4633 .scan_out(ff_fwd_req_c3_scanout),
4634 .dout(fwd_req_c3),
4635 .siclk(siclk),
4636 .soclk(soclk)
4637);
4638
4639assign fwd_req_vld_diag_c3 = fwd_req_c3 &
4640 inst_vld_c3 &
4641 inst_diag_c3 ;
4642
4643assign fwd_req_vld_diagn_c3 = fwd_req_c3 &
4644 inst_vld_c3 &
4645 ~inst_diag_c3 ;
4646
4647l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_vld_diag_c4
4648 (.din(fwd_req_vld_diag_c3), .l1clk(l1clk),
4649 .scan_in(ff_fwd_req_vld_diag_c4_scanin),
4650 .scan_out(ff_fwd_req_vld_diag_c4_scanout),
4651 .dout(fwd_req_vld_diag_c4),
4652 .siclk(siclk),
4653 .soclk(soclk)
4654);
4655
4656assign fwd_req_ret_c3 = fwd_req_vld_diag_c4 | fwd_req_vld_diagn_c3;
4657
4658
4659l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_ret_c4
4660 (.din(fwd_req_ret_c3), .l1clk(l1clk),
4661 .scan_in(ff_fwd_req_ret_c4_scanin),
4662 .scan_out(ff_fwd_req_ret_c4_scanout),
4663 .dout(fwd_req_ret_c4),
4664 .siclk(siclk),
4665 .soclk(soclk)
4666);
4667
4668l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_ret_c5
4669 (.din(fwd_req_ret_c4), .l1clk(l1clk),
4670 .scan_in(ff_fwd_req_ret_c5_scanin),
4671 .scan_out(ff_fwd_req_ret_c5_scanout),
4672 .dout(fwd_req_ret_c5),
4673 .siclk(siclk),
4674 .soclk(soclk)
4675);
4676
4677assign tag_fwd_req_ret_c5 = fwd_req_ret_c5 ;
4678
4679
4680// FWD req acks were earlier sent to cpu#0.
4681// Now, the ack is sent to the cpu that forwards the IOB request.
4682
4683// the following signal is high only for non-diag reads
4684assign fwd_req_ld_c3 = fwd_req_vld_diagn_c3 & ld_inst_c3 ;
4685
4686l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_ld_c4
4687 (.din(fwd_req_ld_c3), .l1clk(l1clk),
4688 .scan_in(ff_fwd_req_ld_c4_scanin),
4689 .scan_out(ff_fwd_req_ld_c4_scanout),
4690 .dout(fwd_req_ld_c4),
4691 .siclk(siclk),
4692 .soclk(soclk)
4693);
4694
4695l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_ld_c5
4696 (.din(fwd_req_ld_c4), .l1clk(l1clk),
4697 .scan_in(ff_fwd_req_ld_c5_scanin),
4698 .scan_out(ff_fwd_req_ld_c5_scanout),
4699 .dout(fwd_req_ld_c5),
4700 .siclk(siclk),
4701 .soclk(soclk)
4702);
4703
4704// BS 03/11/04 extra cycle for mem access
4705
4706l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_ld_c52
4707 (.din(fwd_req_ld_c5), .l1clk(l1clk),
4708 .scan_in(ff_fwd_req_ld_c52_scanin),
4709 .scan_out(ff_fwd_req_ld_c52_scanout),
4710 .dout(fwd_req_ld_c52),
4711 .siclk(siclk),
4712 .soclk(soclk)
4713);
4714
4715
4716l2t_tag_ctl_msff_ctl_macro__width_1 ff_fwd_req_ld_c6
4717 (.din(fwd_req_ld_c52), .l1clk(l1clk),
4718 .scan_in(ff_fwd_req_ld_c6_scanin),
4719 .scan_out(ff_fwd_req_ld_c6_scanout),
4720 .dout(fwd_req_ld_c6),
4721 .siclk(siclk),
4722 .soclk(soclk)
4723);
4724
4725assign tag_fwd_req_ld_c6 = fwd_req_ld_c6 ;
4726
4727
4728
4729
4730/////////////////////////////////////////////////////////////
4731//
4732// indicates that the rdma register
4733// is in use. This register has the following set
4734// reset conditions.
4735//
4736// Set in the C3 cycle of
4737// - WR8 and ~no_Ctrue hitting the $.
4738// - Wr64 hitting the $
4739// or missing the ($ and FB and MB and WB and rdma WB)
4740// - ld64 hitting the $ or Fb.
4741//
4742// Reset the rdma reg valid under the following conditions.
4743// - For a Ld64, rdma reg valid is deasserted when the counter
4744// reaches 17.
4745// _ For a store the rdma reg valid is deasserted when the
4746// OQ is able to make the invalidate request to the primary
4747// caches.
4748//
4749//
4750// ld rdma reg vld.
4751//-----------------------------------------------------------------------------------
4752// C3 c4 c5 c6 c7.... C14.. C16 c18 c19 c20
4753// start
4754// count_c3 count=1 count=15
4755//
4756//-----------------------------------------------------------------------------------
4757//
4758//reg_vld=1 allow
4759// arb sel rv_c2_p=0
4760// in next
4761// cyc, cnt=13
4762//
4763// allow
4764// mb pick.
4765// in next cyc
4766// count=11
4767//-----------------------------------------------------------------------------------
4768//
4769//OPeration B C2
4770//
4771//-----------------------------------------------------------------------------------
4772// => reg_vld_px2_p = 0, when count=13. = C16
4773// => reg_vld_px0_p = 0 when count = 11 = C14
4774//
4775// Since the occupation latency of the rdma interface for stores
4776// is not fixed, the counter is reset and rv_c2_p, rv_px2_p and rv_px0_p
4777// go low in the same cycle.
4778//
4779// *** rdma_reg_vld is a C4 flop whose results are consumed by a C2 instruction.
4780// However, this works fine because any rdma instruction causes a 1 cycle
4781// bubble in the pipe.
4782//
4783// *** a RD64 response can immediately be followed by a write response
4784// since the number of cycles that a read occupies the interface
4785// is static(17 cycles). However, a write response cannot be immediately
4786// followed by another response for atleast 7 cycles.
4787/////////////////////////////////////////////////////////////
4788
4789
4790l2t_tag_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c3
4791 (.din(ld64_inst_c2), .l1clk(l1clk),
4792 .scan_in(ff_ld64_inst_c3_scanin),
4793 .scan_out(ff_ld64_inst_c3_scanout),
4794 .dout(ld64_inst_c3),
4795 .siclk(siclk),
4796 .soclk(soclk)
4797);
4798
4799l2t_tag_ctl_msff_ctl_macro__width_1 ff_wr64_inst_c3
4800 (.din(arb_decdp_wr64_inst_c2), .l1clk(l1clk),
4801 .scan_in(ff_wr64_inst_c3_scanin),
4802 .scan_out(ff_wr64_inst_c3_scanout),
4803 .dout(wr64_inst_c3),
4804 .siclk(siclk),
4805 .soclk(soclk)
4806);
4807
4808l2t_tag_ctl_msff_ctl_macro__width_1 ff_wr8_inst_c3
4809 (.din(arb_decdp_wr8_inst_c2), .l1clk(l1clk),
4810 .scan_in(ff_wr8_inst_c3_scanin),
4811 .scan_out(ff_wr8_inst_c3_scanout),
4812 .dout(wr8_inst_c3),
4813 .siclk(siclk),
4814 .soclk(soclk)
4815);
4816
4817//msff_ctl_macro ff_arbdp_tag_pst_no_ctrue_c2 (width=1)
4818// (.din(arb_arbdp_tag_pst_no_ctrue_c2), .l1clk(l1clk),
4819// .dout(pst_no_ctrue_c3),
4820// .scan_in(),
4821// .scan_out()
4822//);
4823
4824//////////
4825// hit completion for
4826// all types of rdma instructions
4827// HIT is only asserted if rdma_reg_vld=0
4828//////////
4829assign rd64_complete_c3 = ( ld64_inst_c3 & tag_hit_l2orfb_c3 ) & ~arb_vuad_ce_err_c3;
4830assign wr64_hit_complete_c3 = ( wr64_inst_c3 & tag_hit_l2orfb_c3 ) & ~arb_vuad_ce_err_c3;
4831assign wr8_complete_c3 = ( wr8_inst_c3 & ~pst_no_ctrue_c3 &
4832 tag_hit_l2orfb_c3 ) & ~arb_vuad_ce_err_c3;
4833
4834//////////////////////////////////////
4835// select inval vector
4836// to oqu for selecting
4837// the results of the directory CAM
4838// for generating the request vector
4839// and invalidation packet.
4840//////////////////////////////////////
4841
4842
4843assign sel_rdma_inval_vec_c3 = ( wr8_inst_c3 | wr64_inst_c3 ) &
4844 tag_hit_l2orfb_c3;
4845
4846l2t_tag_ctl_msff_ctl_macro__width_1 ff_sel_rdma_inval_vec_c4
4847 (.din(sel_rdma_inval_vec_c3), .l1clk(l1clk),
4848 .scan_in(ff_sel_rdma_inval_vec_c4_scanin),
4849 .scan_out(ff_sel_rdma_inval_vec_c4_scanout),
4850 .dout(sel_rdma_inval_vec_c4),
4851 .siclk(siclk),
4852 .soclk(soclk)
4853);
4854
4855l2t_tag_ctl_msff_ctl_macro__width_1 ff_sel_rdma_inval_vec_c5
4856 (.din(sel_rdma_inval_vec_c4), .l1clk(l1clk),
4857 .scan_in(ff_sel_rdma_inval_vec_c5_scanin),
4858 .scan_out(ff_sel_rdma_inval_vec_c5_scanout),
4859 .dout(tag_sel_rdma_inval_vec_c5),
4860 .siclk(siclk),
4861 .soclk(soclk)
4862);
4863
4864
4865//////////
4866// tag_rdma_ev_en_c4 is used to
4867// set mcu_req in l2t_rdmat
4868/////////
4869
4870// int 5.0 changes
4871// 10/3/2003 : tagdp_tag_par_err_c3 qualification is
4872// needed for every expression that has misbuf_wr64_miss_comp_c3
4873// THis is because misbuf_wr64_miss_comp_c3 is now not qualified
4874// with tag_mbctl_par_err_c3.
4875
4876
4877//
4878// VUAD ecc change
4879// In case VUAD CE is found, we need to disable l2t_sii_wib_dequeue
4880// We do this by gating off tag_rdma_ev_en_c3 by arb_vuad_ce_err_c3
4881// So the IOWB does not get evicted to MCU
4882// The WR64 that found the CE would get moved to the MB and gets
4883// replayed. On replay it does not find VUAD CE anymore and
4884// this time upon completion it will assert l2t_sii_wib_dequeue
4885// and cause eviction of IOWB to happen
4886
4887
4888assign tag_rdma_ev_en_c3 = (( misbuf_wr64_miss_comp_c3 & ~tagdp_tag_par_err_c3) | // int 5.0 change
4889 wr64_hit_complete_c3) & ~arb_vuad_ce_err_c3 ;
4890
4891l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_rdma_ev_en_c3
4892 (.din(tag_rdma_ev_en_c3), .l1clk(l1clk),
4893 .scan_in(ff_tag_rdma_ev_en_c3_scanin),
4894 .scan_out(ff_tag_rdma_ev_en_c3_scanout),
4895 .dout(tag_rdma_ev_en_c4),
4896 .siclk(siclk),
4897 .soclk(soclk)
4898);
4899
4900assign tag_rdma_wr_comp_c3 = (misbuf_wr64_miss_comp_c3 & ~tagdp_tag_par_err_c3 & ~arb_vuad_ce_err_c3) | // int 5.0 change
4901 wr8_complete_c3 |
4902 wr64_hit_complete_c3 ;
4903
4904
4905//
4906// When a VUAD CE error occurs, we need to disable data returns and
4907// write acks to SIU. We do this by shutting off l2t_l2b_ctag_en_c7
4908// and l2t_l2b_req_en_c7.
4909// The SIU instruction will get replayed from MB, will not find the CE any more
4910// and will complete as normal sending back data and ack to SIU.
4911//
4912
4913
4914assign set_rdma_reg_vld_c3 = ( rd64_complete_c3 | tag_rdma_wr_comp_c3 ) & ~arb_vuad_ce_err_c3 ;
4915
4916
4917assign reset_rdma_reg_vld = ( &(rdma_cnt) | // reset for lds
4918 oqu_st_complete_c7 ) ; // reset for stores.
4919
4920assign rdma_reg_vld_in = ( rdma_reg_vld | set_rdma_reg_vld_c3 ) &
4921 ~reset_rdma_reg_vld ;
4922
4923l2t_tag_ctl_msff_ctl_macro__clr_1__dmsff_32x__width_2 ff_rdma_reg_vld // sync reset active low
4924 (.din({2{rdma_reg_vld_in}}), .l1clk(l1clk),
4925 .scan_in(ff_rdma_reg_vld_scanin),
4926 .scan_out(ff_rdma_reg_vld_scanout),
4927 .clr(~dbb_rst_l),
4928 .dout({rdma_reg_vld_cloned,rdma_reg_vld}),
4929 .siclk(siclk),
4930 .soclk(soclk)
4931);
4932
4933l2t_tag_ctl_msff_ctl_macro__width_1 ff_tag_rdma_wr_comp_c4
4934 (.din(tag_rdma_wr_comp_c3), .l1clk(l1clk),
4935 .scan_in(ff_tag_rdma_wr_comp_c4_scanin),
4936 .scan_out(ff_tag_rdma_wr_comp_c4_scanout),
4937 .dout(tag_rdma_wr_comp_c4),
4938 .siclk(siclk),
4939 .soclk(soclk)
4940);
4941
4942//////////
4943// tag_rdma_reg_vld_c2 is consumed by
4944// a C2 instruction.
4945//////////
4946l2t_tag_ctl_msff_ctl_macro__clr_1__width_1 ff_misbuf_rdma_reg_vld_c2 // sync reset active low
4947 (.din(rdma_reg_vld_in), .l1clk(l1clk),
4948 .scan_in(ff_misbuf_rdma_reg_vld_c2_scanin),
4949 .scan_out(ff_misbuf_rdma_reg_vld_c2_scanout),
4950 .clr(~dbb_rst_l),
4951 .dout(tag_misbuf_rdma_reg_vld_c2),
4952 .siclk(siclk),
4953 .soclk(soclk)
4954);
4955
4956
4957//////////////////////////
4958//
4959//tag_rdma_vld_px0_p:
4960//
4961// the following signal is high from the C4 cycle of an
4962// instruction setting rdma_reg_vld and will be reset
4963// when the rdma rd counter is 11 or when oqu_st_complete_c7
4964// is high
4965//
4966// It is used in misbuf to permit an L2 pick in the next
4967// cycle for an RDMA instruction. Pipeline is as follows
4968//--------------------------------------------------------------------------------
4969// cnt11 12 13 14 15 16 17
4970//-------------------------------------------------------------------------------
4971// rdma_reg_vld==0
4972// reset
4973// rdma_vld_px0_p pre pick read issue C1 C2
4974// cond mbuffer PX2
4975// L2 rdy
4976// in misbuf
4977//--------------------------------------------------------------------------------
4978
4979// Introduced a 1 cycle latency in the reintroduction of
4980// rdma instructions after the setting of rdma_reg_vld.
4981// This is to make sure that the rdma rd address is kept
4982// around until an error on the last packet is reported.
4983//
4984//////////////////////////
4985
4986assign reset_rdma_vld_px0_p_in = (rdma_cnt == 4'd11 )
4987 | oqu_st_complete_c7 ;
4988
4989assign rdma_vld_px0_p_in = ( set_rdma_reg_vld_c3 | rdma_vld_px0_p )
4990 & ~reset_rdma_vld_px0_p_in ;
4991
4992l2t_tag_ctl_msff_ctl_macro__clr_1__width_1 ff_rdma_vld_px0_p // sync reset active low
4993 (.din(rdma_vld_px0_p_in), .l1clk(l1clk),
4994 .scan_in(ff_rdma_vld_px0_p_scanin),
4995 .scan_out(ff_rdma_vld_px0_p_scanout),
4996 .clr(~dbb_rst_l),
4997 .dout(rdma_vld_px0_p),
4998 .siclk(siclk),
4999 .soclk(soclk)
5000);
5001
5002assign tag_rdma_vld_px0_p = rdma_vld_px0_p ;
5003
5004//////////////////////////
5005//
5006//tag_rdma_vld_px1:
5007//
5008// the following signal is high from the C4 cycle of an
5009// instruction setting rdma_reg_vld and will be reset
5010// when the rdma rd counter is 13 or when oqu_st_complete_c7
5011// is high
5012//
5013//--------------------------------------------------------------------------------
5014// cnt13 14 15 16 17
5015//-------------------------------------------------------------------------------
5016// rdma_reg_vld==0
5017// reset
5018// rdma_vld_px1 allow issue
5019// snp snp C1 C2
5020// selection PX2
5021// in arb
5022//--------------------------------------------------------------------------------
5023// It is used in arb to permit an RDMA instruction
5024// to be picked.
5025//
5026// Introduced a 1 cycle latency in the reintroduction of
5027// rdma instructions after the setting of rdma_reg_vld.
5028// This is to make sure that the rdma rd address is kept
5029// around until an error on the last packet is reported.
5030//
5031//////////////////////////
5032
5033
5034assign reset_rdma_vld_px1_in = (rdma_cnt == 4'd12 )
5035 | oqu_st_complete_c7 ;
5036
5037assign rdma_vld_px1_in = ( set_rdma_reg_vld_c3 | rdma_vld_px1 )
5038 & ~reset_rdma_vld_px1_in ;
5039
5040l2t_tag_ctl_msff_ctl_macro__clr_1__width_1 ff_rdma_vld_px1 // sync reset active low
5041 (.din(rdma_vld_px1_in), .l1clk(l1clk),
5042 .scan_in(ff_rdma_vld_px1_scanin),
5043 .scan_out(ff_rdma_vld_px1_scanout),
5044 .clr(~dbb_rst_l),
5045 .dout(rdma_vld_px1),
5046 .siclk(siclk),
5047 .soclk(soclk)
5048);
5049
5050assign tag_rdma_vld_px1 = rdma_vld_px1 ;
5051
5052////////////////////////////////////////////////////////////////////////
5053// Write the CTAG into the CTAG register in l2b
5054// if an instruction completes.
5055////////////////////////////////////////////////////////////////////////
5056
5057l2t_tag_ctl_msff_ctl_macro__width_1 ff_set_rdma_reg_vld_c4
5058 (.din(set_rdma_reg_vld_c3), .l1clk(l1clk),
5059 .scan_in(ff_set_rdma_reg_vld_c4_scanin),
5060 .scan_out(ff_set_rdma_reg_vld_c4_scanout),
5061 .dout(set_rdma_reg_vld_c4),
5062 .siclk(siclk),
5063 .soclk(soclk)
5064);
5065
5066assign tag_set_rdma_reg_vld_c4 = set_rdma_reg_vld_c4 ;
5067
5068////////////////////////////////////////////////////////////////////////
5069//
5070// request to siu:
5071// the above signal may or may not be synchronous with the setting
5072// of rdma_reg_vld.
5073// - For loads , this signal is sent in C7,
5074// - for store misses this is a C8 signal.
5075// - For stores that hit any L1$, this
5076// signal is transmitted only after all L1 $ invalidate packets are
5077// queued up in the CPX.
5078//
5079// The following FSM is used to perform the above function.
5080//
5081//--------------------------------------------------------------------------------
5082// STATES IDLE ST_REQ_ST LD_REQ_ST
5083//--------------------------------------------------------------------------------
5084// IDLE rst or set rdma_reg set rdma reg
5085// ~rdma_reg & WR8 or WR64 and LD64
5086//--------------------------------------------------------------------------------
5087// ST_REQ_ST oqu_st_ ~oqu_st_ -
5088// complete_c7 complete_c7
5089//--------------------------------------------------------------------------------
5090// LD_REQ_ST rdmardcount - rdmardcount!=15
5091// ==15
5092//--------------------------------------------------------------------------------
5093//
5094// req_en_c7 = 1 if LD_REQ_ST & rdmardcount=4;
5095// req_en_c7 = 1 if ST_REQ_ST & oqu_st_complete_c7;
5096//
5097// Note: Since the counter is a C4 flop whose results are consumed by
5098// a C2 instruction, there is no transition between ST_REQ_ST & LD_REQ_ST.
5099// After, IDLE state is reached, the FSM remains in that state for
5100// atleast two more cycles.
5101//
5102// ***rdma_reg_vld above is nothing but an OR of ST_REQ_ST and LD_REQ_ST states.
5103//
5104////////////////////////////////////////////////////////////////////////
5105
5106assign tag_siu_req_state_in[`IDLE] = ((tag_siu_req_state[`ST_REQ_ST]
5107 & oqu_st_complete_c7) | // STORE DONE
5108 ( tag_siu_req_state[`LD_REQ_ST]
5109 & (&(rdma_cnt)) ) | // LOAD DONE
5110 tag_siu_req_state[`IDLE] ) &
5111 ~set_rdma_reg_vld_c3 ;
5112
5113assign idle_state_in_l = ~tag_siu_req_state_in[`IDLE] ;
5114
5115l2t_tag_ctl_msff_ctl_macro__clr_1__width_1 ff_tag_siu_req_state_0 // sync reset active low
5116 (.din(idle_state_in_l), .l1clk(l1clk),
5117 .scan_in(ff_tag_siu_req_state_0_scanin),
5118 .scan_out(ff_tag_siu_req_state_0_scanout),
5119 .clr(~dbb_rst_l),
5120 .dout(idle_state_l),
5121 .siclk(siclk),
5122 .soclk(soclk)
5123);
5124
5125assign tag_siu_req_state[`IDLE] = ~idle_state_l ;
5126
5127
5128assign tag_siu_req_state_in[`ST_REQ_ST] = ((tag_siu_req_state[`IDLE] &
5129 set_rdma_reg_vld_c3 & ~ld64_inst_c3 ) | // NON LD REQ
5130 tag_siu_req_state[`ST_REQ_ST]) &
5131 ~oqu_st_complete_c7; // not ST_DONE
5132
5133
5134assign tag_siu_req_state_in[`LD_REQ_ST] = ((tag_siu_req_state[`IDLE] &
5135 set_rdma_reg_vld_c3 & ld64_inst_c3 ) | // LD REQ
5136 tag_siu_req_state[`LD_REQ_ST]) &
5137 ~(&(rdma_cnt)); // LD_DONE
5138
5139
5140l2t_tag_ctl_msff_ctl_macro__clr_1__width_2 ff_tag_siu_req_state // sync reset active low
5141 (.din(tag_siu_req_state_in[`LD_REQ_ST:`ST_REQ_ST]), .l1clk(l1clk),
5142 .scan_in(ff_tag_siu_req_state_scanin),
5143 .scan_out(ff_tag_siu_req_state_scanout),
5144 .clr(~dbb_rst_l),
5145 .dout(tag_siu_req_state[`LD_REQ_ST:`ST_REQ_ST]),
5146 .siclk(siclk),
5147 .soclk(soclk)
5148
5149);
5150
5151
5152assign tag_siu_req_en_c52 = ( tag_siu_req_state[`LD_REQ_ST] &
5153 ( rdma_cnt == 4'd3 ) ) |
5154 ( tag_siu_req_state[`ST_REQ_ST] &
5155 oqu_st_complete_c7 ) ;
5156
5157
5158
5159
5160
5161////////////////////////////////////
5162//
5163// rdma rd counter
5164// trigger the count
5165// in C3, and in C18
5166// the counter is reset
5167//
5168// The rdmard counter is a C4 flop.
5169//
5170/////////////////////////////////////
5171
5172assign inc_rdma_cnt_c3 = |(rdma_cnt) | rd64_complete_c3 ;
5173
5174l2t_tag_ctl_msff_ctl_macro__clr_1__width_1 ff_inc_rdma_cnt_c4 // sync reset active low
5175 (.din(inc_rdma_cnt_c3), .l1clk(l1clk),
5176 .scan_in(ff_inc_rdma_cnt_c4_scanin),
5177 .scan_out(ff_inc_rdma_cnt_c4_scanout),
5178 .clr(~dbb_rst_l),
5179 .dout(inc_rdma_cnt_c4),
5180 .siclk(siclk),
5181 .soclk(soclk)
5182);
5183
5184assign tag_inc_rdma_cnt_c4 = inc_rdma_cnt_c4 ;
5185
5186assign rdma_cnt_plus1 = rdma_cnt +4'b1 ;
5187
5188assign rdma_cnt_reset = ~dbb_rst_l ;
5189
5190l2t_tag_ctl_msff_ctl_macro__clr_1__en_1__width_4 ff_rdmard_cnt // sync reset active high
5191 (.din(rdma_cnt_plus1[3:0]),
5192 .scan_in(ff_rdmard_cnt_scanin),
5193 .scan_out(ff_rdmard_cnt_scanout),
5194 .en(inc_rdma_cnt_c3), .l1clk(l1clk), .clr(rdma_cnt_reset),
5195 .dout(rdma_cnt[3:0]),
5196 .siclk(siclk),
5197 .soclk(soclk)
5198);
5199
5200
5201
5202
5203////////////////////////////////////////////
5204// rdma rd pipeline For holding error state
5205// and address.
5206//
5207//
5208//c5: $ read cyc1
5209//c6: $ read cyc2
5210//c7: xmit inside l2d
5211//c8: xmit from l2d to l2b
5212//c9: mux data
5213//c10: perform ECC.
5214//c11: xmit data and xmit errors to l2t
5215// : HOLD the C11 address
5216// and C11 errors in filbuf.
5217//c12: flop errors in l2t.
5218//
5219//
5220// The hold signal in C11 is generated here.
5221//
5222////////////////////////////////////////////
5223
5224l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c4
5225 (.din(rd64_complete_c3), .l1clk(l1clk),
5226 .scan_in(ff_rd64_complete_c4_scanin),
5227 .scan_out(ff_rd64_complete_c4_scanout),
5228 .dout(rd64_complete_c4),
5229 .siclk(siclk),
5230 .soclk(soclk)
5231);
5232
5233l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c5
5234 (.din(rd64_complete_c4), .l1clk(l1clk),
5235 .scan_in(ff_rd64_complete_c5_scanin),
5236 .scan_out(ff_rd64_complete_c5_scanout),
5237 .dout(rd64_complete_c5),
5238 .siclk(siclk),
5239 .soclk(soclk)
5240);
5241
5242// BS 03/11/04 extra cycle for mem access
5243
5244l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c52
5245 (.din(rd64_complete_c5), .l1clk(l1clk),
5246 .scan_in(ff_rd64_complete_c52_scanin),
5247 .scan_out(ff_rd64_complete_c52_scanout),
5248 .dout(rd64_complete_c52),
5249 .siclk(siclk),
5250 .soclk(soclk)
5251);
5252
5253
5254l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c6
5255 (.din(rd64_complete_c52), .l1clk(l1clk),
5256 .scan_in(ff_rd64_complete_c6_scanin),
5257 .scan_out(ff_rd64_complete_c6_scanout),
5258 .dout(rd64_complete_c6),
5259 .siclk(siclk),
5260 .soclk(soclk)
5261);
5262
5263l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c7
5264 (.din(rd64_complete_c6), .l1clk(l1clk),
5265 .scan_in(ff_rd64_complete_c7_scanin),
5266 .scan_out(ff_rd64_complete_c7_scanout),
5267 .dout(rd64_complete_c7),
5268 .siclk(siclk),
5269 .soclk(soclk)
5270);
5271
5272l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c8
5273 (.din(rd64_complete_c7), .l1clk(l1clk),
5274 .scan_in(ff_rd64_complete_c8_scanin),
5275 .scan_out(ff_rd64_complete_c8_scanout),
5276 .dout(rd64_complete_c8),
5277 .siclk(siclk),
5278 .soclk(soclk)
5279);
5280
5281l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c9
5282 (.din(rd64_complete_c8), .l1clk(l1clk),
5283 .scan_in(ff_rd64_complete_c9_scanin),
5284 .scan_out(ff_rd64_complete_c9_scanout),
5285 .dout(rd64_complete_c9),
5286 .siclk(siclk),
5287 .soclk(soclk)
5288);
5289
5290l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c10
5291 (.din(rd64_complete_c9), .l1clk(l1clk),
5292 .scan_in(ff_rd64_complete_c10_scanin),
5293 .scan_out(ff_rd64_complete_c10_scanout),
5294 .dout(rd64_complete_c10),
5295 .siclk(siclk),
5296 .soclk(soclk)
5297);
5298
5299l2t_tag_ctl_msff_ctl_macro__width_1 ff_rd64_complete_c11
5300 (.din(rd64_complete_c10), .l1clk(l1clk),
5301 .scan_in(ff_rd64_complete_c11_scanin),
5302 .scan_out(ff_rd64_complete_c11_scanout),
5303 .dout(rd64_complete_c11),
5304 .siclk(siclk),
5305 .soclk(soclk)
5306);
5307
5308assign tag_rd64_complete_c11 = rd64_complete_c11 ;
5309
5310
5311
5312
5313// fixscan start:
5314assign spares_scanin = scan_in ;
5315assign reset_flop_scanin = spares_scanout ;
5316assign ff_mbist_run_scanin = reset_flop_scanout ;
5317assign ff_mbist_arb_l2d_en_d1_scanin = ff_mbist_run_scanout ;
5318assign ff_l2_bypass_mode_on_scanin = ff_mbist_arb_l2d_en_d1_scanout;
5319assign ff_fill_vld_c3_scanin = ff_l2_bypass_mode_on_scanout;
5320assign ff_ld64_inst_c2_scanin = ff_fill_vld_c3_scanout ;
5321assign ff_temp_way_sel_c2_scanin = ff_ld64_inst_c2_scanout ;
5322assign ff_evict_unqual_vld_c3_scanin = ff_temp_way_sel_c2_scanout;
5323assign ff_wr8_no_ctrue_c2_scanin = ff_evict_unqual_vld_c3_scanout;
5324assign ff_tag_hit_way_vld_c3_scanin = ff_wr8_no_ctrue_c2_scanout;
5325assign ff_tag_l2d_way_sel_c3_scanin = ff_tag_hit_way_vld_c3_scanout;
5326assign ff_way_sel_unqual_c3_scanin = ff_tag_l2d_way_sel_c3_scanout;
5327assign ff_filbuf_tag_evict_way_c4_scanin = ff_way_sel_unqual_c3_scanout;
5328assign ff_filbuf_tag_hit_c3_scanin = ff_filbuf_tag_evict_way_c4_scanout;
5329assign ff_tag_dir_l2way_sel_c4_scanin = ff_filbuf_tag_hit_c3_scanout;
5330assign ff_alt_tag_miss_unqual_c3_scanin = ff_tag_dir_l2way_sel_c4_scanout;
5331assign ff_tag_hit_c3_scanin = ff_alt_tag_miss_unqual_c3_scanout;
5332assign ff_tag_hit_l2orfb_c3_scanin = ff_tag_hit_c3_scanout ;
5333assign ff_tag_hit_not_comp_c3_scanin = ff_tag_hit_l2orfb_c3_scanout;
5334assign ff_encoded_lru_c4_scanin = ff_tag_hit_not_comp_c3_scanout;
5335assign ff_addr5to4_c2_scanin = ff_encoded_lru_c4_scanout;
5336assign ff_dec_col_offset_prev_c2_scanin = ff_addr5to4_c2_scanout ;
5337assign ff_col_offset_sel_c2_scanin = ff_dec_col_offset_prev_c2_scanout;
5338assign ff_imiss_tag_hit_c4_scanin = ff_col_offset_sel_c2_scanout;
5339assign ff_rdma_inst_c2_scanin = ff_imiss_tag_hit_c4_scanout;
5340assign ff_rdma_inst_c3_scanin = ff_rdma_inst_c2_scanout ;
5341assign ff_st_to_data_array_c3_scanin = ff_rdma_inst_c3_scanout ;
5342assign ff_tag_spc_rd_vld_c4_scanin = ff_st_to_data_array_c3_scanout;
5343assign ff_tag_spc_rd_vld_c5_scanin = ff_tag_spc_rd_vld_c4_scanout;
5344assign ff_tag_spc_rd_vld_c52_scanin = ff_tag_spc_rd_vld_c5_scanout;
5345assign ff_tag_spc_rd_vld_c6_scanin = ff_tag_spc_rd_vld_c52_scanout;
5346assign ff_tag_spc_rd_vld_c7_scanin = ff_tag_spc_rd_vld_c6_scanout;
5347assign ff_tag_bsc_rd_vld_c4_scanin = ff_tag_spc_rd_vld_c7_scanout;
5348assign ff_tag_bsc_rd_vld_c5_scanin = ff_tag_bsc_rd_vld_c4_scanout;
5349assign ff_tag_bsc_rd_vld_c52_scanin = ff_tag_bsc_rd_vld_c5_scanout;
5350assign ff_tag_bsc_rd_vld_c6_scanin = ff_tag_bsc_rd_vld_c52_scanout;
5351assign ff_tag_bsc_rd_vld_c7_scanin = ff_tag_bsc_rd_vld_c6_scanout;
5352assign ff_prev_rd_wr_c2_scanin = ff_tag_bsc_rd_vld_c7_scanout;
5353assign ff_pst_with_ctrue_c2_scanin = ff_prev_rd_wr_c2_scanout ;
5354assign ff_mb_errs_c2_scanin = ff_pst_with_ctrue_c2_scanout;
5355assign ff_prev_rd_wr_c2_1_scanin = ff_mb_errs_c2_scanout ;
5356assign ff_tag_st_to_data_array_c3_scanin = ff_prev_rd_wr_c2_1_scanout;
5357assign ff_prev_wen_c1_scanin = ff_tag_st_to_data_array_c3_scanout;
5358assign ff_sel_prev_wen_c2_scanin = ff_prev_wen_c1_scanout ;
5359assign ff_dec_word_addr_c2_scanin = ff_sel_prev_wen_c2_scanout;
5360assign ff_dec_word_enable_c2_scanin = ff_dec_word_addr_c2_scanout;
5361assign ff_tecc_c2_scanin = ff_dec_word_enable_c2_scanout;
5362assign ff_scrub_fsm_cnt_scanin = ff_tecc_c2_scanout ;
5363assign ff_scrub_addr_cnt_scanin = ff_scrub_fsm_cnt_scanout ;
5364assign ff_decc_tag_acc_en_px2_scanin = ff_scrub_addr_cnt_scanout;
5365assign ff_scrub_way_vld_c3_scanin = ff_decc_tag_acc_en_px2_scanout;
5366assign ff_scrub_way_vld_c4_scanin = ff_scrub_way_vld_c3_scanout;
5367assign ff_scrub_way_vld_c5_scanin = ff_scrub_way_vld_c4_scanout;
5368assign ff_scrub_way_vld_c52_scanin = ff_scrub_way_vld_c5_scanout;
5369assign ff_scrub_way_vld_c6_scanin = ff_scrub_way_vld_c52_scanout;
5370assign ff_scrub_way_vld_c7_scanin = ff_scrub_way_vld_c6_scanout;
5371assign ff_scrub_rd_vld_c8_scanin = ff_scrub_way_vld_c7_scanout;
5372assign ff_scrub_wr_disable_c9_scanin = ff_scrub_rd_vld_c8_scanout;
5373assign ff_l2b_fbwr_wen_r2_scanin = ff_scrub_wr_disable_c9_scanout;
5374assign ff_tag_l2b_fbd_stdatasel_c3_scanin = ff_l2b_fbwr_wen_r2_scanout;
5375assign ff_imiss_vld_c3_scanin = ff_tag_l2b_fbd_stdatasel_c3_scanout;
5376assign ff_imiss_hit_c4_scanin = ff_imiss_vld_c3_scanout ;
5377assign ff_imiss_hit_c5_scanin = ff_imiss_hit_c4_scanout ;
5378assign ff_swap_inst_c3_scanin = ff_imiss_hit_c5_scanout ;
5379assign ff_pst_no_ctrue_c3_scanin = ff_swap_inst_c3_scanout ;
5380assign ff_cas1_inst_c3_scanin = ff_pst_no_ctrue_c3_scanout;
5381assign ff_ld_inst_c3_scanin = ff_cas1_inst_c3_scanout ;
5382assign ff_ld_hit_c4_scanin = ff_ld_inst_c3_scanout ;
5383assign ff_ld_hit_c5_scanin = ff_ld_hit_c4_scanout ;
5384assign ff_inst_vld_c3_scanin = ff_ld_hit_c5_scanout ;
5385assign ff_inst_diag_c3_scanin = ff_inst_vld_c3_scanout ;
5386assign ff_inst_mb_c3_scanin = ff_inst_diag_c3_scanout ;
5387assign ff_inst_mb_c4_scanin = ff_inst_mb_c3_scanout ;
5388assign ff_inst_mb_c5_scanin = ff_inst_mb_c4_scanout ;
5389assign ff_misbuf_hit_unqual_c3_scanin = ff_inst_mb_c5_scanout ;
5390assign ff_inst_dep_c3_scanin = ff_misbuf_hit_unqual_c3_scanout;
5391assign ff_store_inst_c3_scanin = ff_inst_dep_c3_scanout ;
5392assign ff_store_inst_c4_scanin = ff_store_inst_c3_scanout ;
5393assign ff_store_inst_c5_scanin = ff_store_inst_c4_scanout ;
5394assign ff_cas2_from_mb_c3_scanin = ff_store_inst_c5_scanout ;
5395assign ff_pst_with_ctrue_c3_scanin = ff_cas2_from_mb_c3_scanout;
5396assign ff_inval_inst_c3_scanin = ff_pst_with_ctrue_c3_scanout;
5397assign ff_strstore_c3_scanin = ff_inval_inst_c3_scanout ;
5398assign ff_diag_rd_en_c3_scanin = ff_strstore_c3_scanout ;
5399assign ff_diag_wr_en_c3_scanin = ff_diag_rd_en_c3_scanout ;
5400assign ff_diag_complete_c4_scanin = ff_diag_wr_en_c3_scanout ;
5401assign ff_tecc_c3_scanin = ff_diag_complete_c4_scanout;
5402assign ff_tag_hit_unqual_c3_scanin = ff_tecc_c3_scanout ;
5403assign ff_st_ack_c4_scanin = ff_tag_hit_unqual_c3_scanout;
5404assign ff_st_ack_c5_scanin = ff_st_ack_c4_scanout ;
5405assign ff_inval_req_c4_scanin = ff_st_ack_c5_scanout ;
5406assign ff_inval_ack_c5_scanin = ff_inval_req_c4_scanout ;
5407assign ff_tag_hit_c4_scanin = ff_inval_ack_c5_scanout ;
5408assign ff_tag_hit_c5_scanin = ff_tag_hit_c4_scanout ;
5409assign ff_st_req_c4_scanin = ff_tag_hit_c5_scanout ;
5410assign ff_st_req_c5_scanin = ff_st_req_c4_scanout ;
5411assign ff_sel_diag_store_data_c5_scanin = ff_st_req_c5_scanout ;
5412assign ff_sel_diag_store_data_c52_scanin = ff_sel_diag_store_data_c5_scanout;
5413assign ff_sel_diag_store_data_c6_scanin = ff_sel_diag_store_data_c52_scanout;
5414assign ff_sel_diag_store_data_c7_scanin = ff_sel_diag_store_data_c6_scanout;
5415assign ff_strst_ack_c4_scanin = ff_sel_diag_store_data_c7_scanout;
5416assign ff_strst_ack_c5_scanin = ff_strst_ack_c4_scanout ;
5417assign ff_rmo_st_ack_c4_scanin = ff_strst_ack_c5_scanout ;
5418assign ff_rmo_st_ack_c5_scanin = ff_rmo_st_ack_c4_scanout ;
5419assign ff_nonmem_comp_c5_scanin = ff_rmo_st_ack_c5_scanout ;
5420assign ff_nonmem_comp_c52_scanin = ff_nonmem_comp_c5_scanout;
5421assign ff_nonmem_comp_c6_scanin = ff_nonmem_comp_c52_scanout;
5422assign ff_st_with_ctrue_c3_scanin = ff_nonmem_comp_c6_scanout;
5423assign ff_misbuf_uerr_c3_scanin = ff_st_with_ctrue_c3_scanout;
5424assign ff_misbuf_cerr_c3_scanin = ff_misbuf_uerr_c3_scanout;
5425assign ff_uerr_ack_tmp_c4_scanin = ff_misbuf_cerr_c3_scanout;
5426assign ff_uerr_ack_c4_scanin = ff_uerr_ack_tmp_c4_scanout;
5427assign ff_uerr_ack_c5_scanin = ff_uerr_ack_c4_scanout ;
5428assign ff_error_ceen_d1_scanin = ff_uerr_ack_c5_scanout ;
5429assign ff_error_nceen_d1_scanin = ff_error_ceen_d1_scanout ;
5430assign ff_cerr_ack_tmp_c4_scanin = ff_error_nceen_d1_scanout;
5431assign ff_cerr_ack_c4_scanin = ff_cerr_ack_tmp_c4_scanout;
5432assign ff_cerr_ack_c5_scanin = ff_cerr_ack_c4_scanout ;
5433assign ff_dis_nderr_c5_scanin = ff_cerr_ack_c5_scanout ;
5434assign ff_inst_int_c3_scanin = ff_dis_nderr_c5_scanout ;
5435assign ff_int_ack_c4_scanin = ff_inst_int_c3_scanout ;
5436assign ff_int_ack_c5_scanin = ff_int_ack_c4_scanout ;
5437assign ff_fwd_req_c3_scanin = ff_int_ack_c5_scanout ;
5438assign ff_fwd_req_vld_diag_c4_scanin = ff_fwd_req_c3_scanout ;
5439assign ff_fwd_req_ret_c4_scanin = ff_fwd_req_vld_diag_c4_scanout;
5440assign ff_fwd_req_ret_c5_scanin = ff_fwd_req_ret_c4_scanout;
5441assign ff_fwd_req_ld_c4_scanin = ff_fwd_req_ret_c5_scanout;
5442assign ff_fwd_req_ld_c5_scanin = ff_fwd_req_ld_c4_scanout ;
5443assign ff_fwd_req_ld_c52_scanin = ff_fwd_req_ld_c5_scanout ;
5444assign ff_fwd_req_ld_c6_scanin = ff_fwd_req_ld_c52_scanout;
5445assign ff_ld64_inst_c3_scanin = ff_fwd_req_ld_c6_scanout ;
5446assign ff_wr64_inst_c3_scanin = ff_ld64_inst_c3_scanout ;
5447assign ff_wr8_inst_c3_scanin = ff_wr64_inst_c3_scanout ;
5448assign ff_sel_rdma_inval_vec_c4_scanin = ff_wr8_inst_c3_scanout ;
5449assign ff_sel_rdma_inval_vec_c5_scanin = ff_sel_rdma_inval_vec_c4_scanout;
5450assign ff_tag_rdma_ev_en_c3_scanin = ff_sel_rdma_inval_vec_c5_scanout;
5451assign ff_rdma_reg_vld_scanin = ff_tag_rdma_ev_en_c3_scanout;
5452assign ff_tag_rdma_wr_comp_c4_scanin = ff_rdma_reg_vld_scanout ;
5453assign ff_misbuf_rdma_reg_vld_c2_scanin = ff_tag_rdma_wr_comp_c4_scanout;
5454assign ff_rdma_vld_px0_p_scanin = ff_misbuf_rdma_reg_vld_c2_scanout;
5455assign ff_rdma_vld_px1_scanin = ff_rdma_vld_px0_p_scanout;
5456assign ff_set_rdma_reg_vld_c4_scanin = ff_rdma_vld_px1_scanout ;
5457assign ff_tag_siu_req_state_0_scanin = ff_set_rdma_reg_vld_c4_scanout;
5458assign ff_tag_siu_req_state_scanin = ff_tag_siu_req_state_0_scanout;
5459assign ff_inc_rdma_cnt_c4_scanin = ff_tag_siu_req_state_scanout;
5460assign ff_rdmard_cnt_scanin = ff_inc_rdma_cnt_c4_scanout;
5461assign ff_rd64_complete_c4_scanin = ff_rdmard_cnt_scanout ;
5462assign ff_rd64_complete_c5_scanin = ff_rd64_complete_c4_scanout;
5463assign ff_rd64_complete_c52_scanin = ff_rd64_complete_c5_scanout;
5464assign ff_rd64_complete_c6_scanin = ff_rd64_complete_c52_scanout;
5465assign ff_rd64_complete_c7_scanin = ff_rd64_complete_c6_scanout;
5466assign ff_rd64_complete_c8_scanin = ff_rd64_complete_c7_scanout;
5467assign ff_rd64_complete_c9_scanin = ff_rd64_complete_c8_scanout;
5468assign ff_rd64_complete_c10_scanin = ff_rd64_complete_c9_scanout;
5469assign ff_rd64_complete_c11_scanin = ff_rd64_complete_c10_scanout;
5470assign scan_out = ff_rd64_complete_c11_scanout;
5471// fixscan end:
5472endmodule
5473
5474
5475
5476
5477
5478
5479
5480
5481// any PARAMS parms go into naming of macro
5482
5483module l2t_tag_ctl_l1clkhdr_ctl_macro (
5484 l2clk,
5485 l1en,
5486 pce_ov,
5487 stop,
5488 se,
5489 l1clk);
5490
5491
5492 input l2clk;
5493 input l1en;
5494 input pce_ov;
5495 input stop;
5496 input se;
5497 output l1clk;
5498
5499
5500
5501
5502
5503cl_sc1_l1hdr_8x c_0 (
5504
5505
5506 .l2clk(l2clk),
5507 .pce(l1en),
5508 .l1clk(l1clk),
5509 .se(se),
5510 .pce_ov(pce_ov),
5511 .stop(stop)
5512);
5513
5514
5515
5516endmodule
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526// Description: Spare gate macro for control blocks
5527//
5528// Param num controls the number of times the macro is added
5529// flops=0 can be used to use only combination spare logic
5530
5531
5532module l2t_tag_ctl_spare_ctl_macro__num_4 (
5533 l1clk,
5534 scan_in,
5535 siclk,
5536 soclk,
5537 scan_out);
5538wire si_0;
5539wire so_0;
5540wire spare0_flop_unused;
5541wire spare0_buf_32x_unused;
5542wire spare0_nand3_8x_unused;
5543wire spare0_inv_8x_unused;
5544wire spare0_aoi22_4x_unused;
5545wire spare0_buf_8x_unused;
5546wire spare0_oai22_4x_unused;
5547wire spare0_inv_16x_unused;
5548wire spare0_nand2_16x_unused;
5549wire spare0_nor3_4x_unused;
5550wire spare0_nand2_8x_unused;
5551wire spare0_buf_16x_unused;
5552wire spare0_nor2_16x_unused;
5553wire spare0_inv_32x_unused;
5554wire si_1;
5555wire so_1;
5556wire spare1_flop_unused;
5557wire spare1_buf_32x_unused;
5558wire spare1_nand3_8x_unused;
5559wire spare1_inv_8x_unused;
5560wire spare1_aoi22_4x_unused;
5561wire spare1_buf_8x_unused;
5562wire spare1_oai22_4x_unused;
5563wire spare1_inv_16x_unused;
5564wire spare1_nand2_16x_unused;
5565wire spare1_nor3_4x_unused;
5566wire spare1_nand2_8x_unused;
5567wire spare1_buf_16x_unused;
5568wire spare1_nor2_16x_unused;
5569wire spare1_inv_32x_unused;
5570wire si_2;
5571wire so_2;
5572wire spare2_flop_unused;
5573wire spare2_buf_32x_unused;
5574wire spare2_nand3_8x_unused;
5575wire spare2_inv_8x_unused;
5576wire spare2_aoi22_4x_unused;
5577wire spare2_buf_8x_unused;
5578wire spare2_oai22_4x_unused;
5579wire spare2_inv_16x_unused;
5580wire spare2_nand2_16x_unused;
5581wire spare2_nor3_4x_unused;
5582wire spare2_nand2_8x_unused;
5583wire spare2_buf_16x_unused;
5584wire spare2_nor2_16x_unused;
5585wire spare2_inv_32x_unused;
5586wire si_3;
5587wire so_3;
5588wire spare3_flop_unused;
5589wire spare3_buf_32x_unused;
5590wire spare3_nand3_8x_unused;
5591wire spare3_inv_8x_unused;
5592wire spare3_aoi22_4x_unused;
5593wire spare3_buf_8x_unused;
5594wire spare3_oai22_4x_unused;
5595wire spare3_inv_16x_unused;
5596wire spare3_nand2_16x_unused;
5597wire spare3_nor3_4x_unused;
5598wire spare3_nand2_8x_unused;
5599wire spare3_buf_16x_unused;
5600wire spare3_nor2_16x_unused;
5601wire spare3_inv_32x_unused;
5602
5603
5604input l1clk;
5605input scan_in;
5606input siclk;
5607input soclk;
5608output scan_out;
5609
5610cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
5611 .siclk(siclk),
5612 .soclk(soclk),
5613 .si(si_0),
5614 .so(so_0),
5615 .d(1'b0),
5616 .q(spare0_flop_unused));
5617assign si_0 = scan_in;
5618
5619cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
5620 .out(spare0_buf_32x_unused));
5621cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
5622 .in1(1'b1),
5623 .in2(1'b1),
5624 .out(spare0_nand3_8x_unused));
5625cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
5626 .out(spare0_inv_8x_unused));
5627cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
5628 .in01(1'b1),
5629 .in10(1'b1),
5630 .in11(1'b1),
5631 .out(spare0_aoi22_4x_unused));
5632cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
5633 .out(spare0_buf_8x_unused));
5634cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
5635 .in01(1'b1),
5636 .in10(1'b1),
5637 .in11(1'b1),
5638 .out(spare0_oai22_4x_unused));
5639cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
5640 .out(spare0_inv_16x_unused));
5641cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
5642 .in1(1'b1),
5643 .out(spare0_nand2_16x_unused));
5644cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
5645 .in1(1'b0),
5646 .in2(1'b0),
5647 .out(spare0_nor3_4x_unused));
5648cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
5649 .in1(1'b1),
5650 .out(spare0_nand2_8x_unused));
5651cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
5652 .out(spare0_buf_16x_unused));
5653cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
5654 .in1(1'b0),
5655 .out(spare0_nor2_16x_unused));
5656cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
5657 .out(spare0_inv_32x_unused));
5658
5659cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
5660 .siclk(siclk),
5661 .soclk(soclk),
5662 .si(si_1),
5663 .so(so_1),
5664 .d(1'b0),
5665 .q(spare1_flop_unused));
5666assign si_1 = so_0;
5667
5668cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
5669 .out(spare1_buf_32x_unused));
5670cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
5671 .in1(1'b1),
5672 .in2(1'b1),
5673 .out(spare1_nand3_8x_unused));
5674cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
5675 .out(spare1_inv_8x_unused));
5676cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
5677 .in01(1'b1),
5678 .in10(1'b1),
5679 .in11(1'b1),
5680 .out(spare1_aoi22_4x_unused));
5681cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
5682 .out(spare1_buf_8x_unused));
5683cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
5684 .in01(1'b1),
5685 .in10(1'b1),
5686 .in11(1'b1),
5687 .out(spare1_oai22_4x_unused));
5688cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
5689 .out(spare1_inv_16x_unused));
5690cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
5691 .in1(1'b1),
5692 .out(spare1_nand2_16x_unused));
5693cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
5694 .in1(1'b0),
5695 .in2(1'b0),
5696 .out(spare1_nor3_4x_unused));
5697cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
5698 .in1(1'b1),
5699 .out(spare1_nand2_8x_unused));
5700cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
5701 .out(spare1_buf_16x_unused));
5702cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
5703 .in1(1'b0),
5704 .out(spare1_nor2_16x_unused));
5705cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
5706 .out(spare1_inv_32x_unused));
5707
5708cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
5709 .siclk(siclk),
5710 .soclk(soclk),
5711 .si(si_2),
5712 .so(so_2),
5713 .d(1'b0),
5714 .q(spare2_flop_unused));
5715assign si_2 = so_1;
5716
5717cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
5718 .out(spare2_buf_32x_unused));
5719cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
5720 .in1(1'b1),
5721 .in2(1'b1),
5722 .out(spare2_nand3_8x_unused));
5723cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
5724 .out(spare2_inv_8x_unused));
5725cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
5726 .in01(1'b1),
5727 .in10(1'b1),
5728 .in11(1'b1),
5729 .out(spare2_aoi22_4x_unused));
5730cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
5731 .out(spare2_buf_8x_unused));
5732cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
5733 .in01(1'b1),
5734 .in10(1'b1),
5735 .in11(1'b1),
5736 .out(spare2_oai22_4x_unused));
5737cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
5738 .out(spare2_inv_16x_unused));
5739cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
5740 .in1(1'b1),
5741 .out(spare2_nand2_16x_unused));
5742cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
5743 .in1(1'b0),
5744 .in2(1'b0),
5745 .out(spare2_nor3_4x_unused));
5746cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
5747 .in1(1'b1),
5748 .out(spare2_nand2_8x_unused));
5749cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
5750 .out(spare2_buf_16x_unused));
5751cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
5752 .in1(1'b0),
5753 .out(spare2_nor2_16x_unused));
5754cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
5755 .out(spare2_inv_32x_unused));
5756
5757cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
5758 .siclk(siclk),
5759 .soclk(soclk),
5760 .si(si_3),
5761 .so(so_3),
5762 .d(1'b0),
5763 .q(spare3_flop_unused));
5764assign si_3 = so_2;
5765
5766cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
5767 .out(spare3_buf_32x_unused));
5768cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
5769 .in1(1'b1),
5770 .in2(1'b1),
5771 .out(spare3_nand3_8x_unused));
5772cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
5773 .out(spare3_inv_8x_unused));
5774cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
5775 .in01(1'b1),
5776 .in10(1'b1),
5777 .in11(1'b1),
5778 .out(spare3_aoi22_4x_unused));
5779cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
5780 .out(spare3_buf_8x_unused));
5781cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
5782 .in01(1'b1),
5783 .in10(1'b1),
5784 .in11(1'b1),
5785 .out(spare3_oai22_4x_unused));
5786cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
5787 .out(spare3_inv_16x_unused));
5788cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
5789 .in1(1'b1),
5790 .out(spare3_nand2_16x_unused));
5791cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
5792 .in1(1'b0),
5793 .in2(1'b0),
5794 .out(spare3_nor3_4x_unused));
5795cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
5796 .in1(1'b1),
5797 .out(spare3_nand2_8x_unused));
5798cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
5799 .out(spare3_buf_16x_unused));
5800cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
5801 .in1(1'b0),
5802 .out(spare3_nor2_16x_unused));
5803cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
5804 .out(spare3_inv_32x_unused));
5805assign scan_out = so_3;
5806
5807
5808
5809endmodule
5810
5811
5812
5813
5814
5815
5816// any PARAMS parms go into naming of macro
5817
5818module l2t_tag_ctl_msff_ctl_macro__width_1 (
5819 din,
5820 l1clk,
5821 scan_in,
5822 siclk,
5823 soclk,
5824 dout,
5825 scan_out);
5826wire [0:0] fdin;
5827
5828 input [0:0] din;
5829 input l1clk;
5830 input scan_in;
5831
5832
5833 input siclk;
5834 input soclk;
5835
5836 output [0:0] dout;
5837 output scan_out;
5838assign fdin[0:0] = din[0:0];
5839
5840
5841
5842
5843
5844
5845dff #(1) d0_0 (
5846.l1clk(l1clk),
5847.siclk(siclk),
5848.soclk(soclk),
5849.d(fdin[0:0]),
5850.si(scan_in),
5851.so(scan_out),
5852.q(dout[0:0])
5853);
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866endmodule
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880// any PARAMS parms go into naming of macro
5881
5882module l2t_tag_ctl_msffi_ctl_macro__width_1 (
5883 din,
5884 l1clk,
5885 scan_in,
5886 siclk,
5887 soclk,
5888 q_l,
5889 scan_out);
5890 input [0:0] din;
5891 input l1clk;
5892 input scan_in;
5893
5894
5895 input siclk;
5896 input soclk;
5897
5898 output [0:0] q_l;
5899 output scan_out;
5900
5901
5902
5903
5904
5905
5906msffi #(1) d0_0 (
5907.l1clk(l1clk),
5908.siclk(siclk),
5909.soclk(soclk),
5910.d(din[0:0]),
5911.si(scan_in),
5912.so(scan_out),
5913.q_l(q_l[0:0])
5914);
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927endmodule
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5938// also for pass-gate with decoder
5939
5940
5941
5942
5943
5944// any PARAMS parms go into naming of macro
5945
5946module l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 (
5947 din0,
5948 sel0,
5949 din1,
5950 sel1,
5951 dout);
5952 input [3:0] din0;
5953 input sel0;
5954 input [3:0] din1;
5955 input sel1;
5956 output [3:0] dout;
5957
5958
5959
5960
5961
5962assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
5963 ( {4{sel1}} & din1[3:0]);
5964
5965
5966
5967
5968
5969endmodule
5970
5971
5972// general mux macro for pass-gate and and-or muxes with/wout priority encoders
5973// also for pass-gate with decoder
5974
5975
5976
5977
5978
5979// any PARAMS parms go into naming of macro
5980
5981module l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 (
5982 din0,
5983 sel0,
5984 din1,
5985 sel1,
5986 dout);
5987 input [15:0] din0;
5988 input sel0;
5989 input [15:0] din1;
5990 input sel1;
5991 output [15:0] dout;
5992
5993
5994
5995
5996
5997assign dout[15:0] = ( {16{sel0}} & din0[15:0] ) |
5998 ( {16{sel1}} & din1[15:0]);
5999
6000
6001
6002
6003
6004endmodule
6005
6006
6007
6008
6009
6010
6011// any PARAMS parms go into naming of macro
6012
6013module l2t_tag_ctl_msff_ctl_macro__width_16 (
6014 din,
6015 l1clk,
6016 scan_in,
6017 siclk,
6018 soclk,
6019 dout,
6020 scan_out);
6021wire [15:0] fdin;
6022wire [14:0] so;
6023
6024 input [15:0] din;
6025 input l1clk;
6026 input scan_in;
6027
6028
6029 input siclk;
6030 input soclk;
6031
6032 output [15:0] dout;
6033 output scan_out;
6034assign fdin[15:0] = din[15:0];
6035
6036
6037
6038
6039
6040
6041dff #(16) d0_0 (
6042.l1clk(l1clk),
6043.siclk(siclk),
6044.soclk(soclk),
6045.d(fdin[15:0]),
6046.si({scan_in,so[14:0]}),
6047.so({so[14:0],scan_out}),
6048.q(dout[15:0])
6049);
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062endmodule
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076// any PARAMS parms go into naming of macro
6077
6078module l2t_tag_ctl_msff_ctl_macro__dmsff_32x__width_2 (
6079 din,
6080 l1clk,
6081 scan_in,
6082 siclk,
6083 soclk,
6084 dout,
6085 scan_out);
6086wire [1:0] fdin;
6087wire [0:0] so;
6088
6089 input [1:0] din;
6090 input l1clk;
6091 input scan_in;
6092
6093
6094 input siclk;
6095 input soclk;
6096
6097 output [1:0] dout;
6098 output scan_out;
6099assign fdin[1:0] = din[1:0];
6100
6101
6102
6103
6104
6105
6106dff #(2) d0_0 (
6107.l1clk(l1clk),
6108.siclk(siclk),
6109.soclk(soclk),
6110.d(fdin[1:0]),
6111.si({scan_in,so[0:0]}),
6112.so({so[0:0],scan_out}),
6113.q(dout[1:0])
6114);
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127endmodule
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141// any PARAMS parms go into naming of macro
6142
6143module l2t_tag_ctl_msff_ctl_macro__width_5 (
6144 din,
6145 l1clk,
6146 scan_in,
6147 siclk,
6148 soclk,
6149 dout,
6150 scan_out);
6151wire [4:0] fdin;
6152wire [3:0] so;
6153
6154 input [4:0] din;
6155 input l1clk;
6156 input scan_in;
6157
6158
6159 input siclk;
6160 input soclk;
6161
6162 output [4:0] dout;
6163 output scan_out;
6164assign fdin[4:0] = din[4:0];
6165
6166
6167
6168
6169
6170
6171dff #(5) d0_0 (
6172.l1clk(l1clk),
6173.siclk(siclk),
6174.soclk(soclk),
6175.d(fdin[4:0]),
6176.si({scan_in,so[3:0]}),
6177.so({so[3:0],scan_out}),
6178.q(dout[4:0])
6179);
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192endmodule
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6203// also for pass-gate with decoder
6204
6205
6206
6207
6208
6209// any PARAMS parms go into naming of macro
6210
6211module l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 (
6212 din0,
6213 sel0,
6214 din1,
6215 sel1,
6216 din2,
6217 sel2,
6218 dout);
6219 input [3:0] din0;
6220 input sel0;
6221 input [3:0] din1;
6222 input sel1;
6223 input [3:0] din2;
6224 input sel2;
6225 output [3:0] dout;
6226
6227
6228
6229
6230
6231assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
6232 ( {4{sel1}} & din1[3:0]) |
6233 ( {4{sel2}} & din2[3:0]);
6234
6235
6236
6237
6238
6239endmodule
6240
6241
6242
6243
6244
6245
6246// any PARAMS parms go into naming of macro
6247
6248module l2t_tag_ctl_msff_ctl_macro__width_4 (
6249 din,
6250 l1clk,
6251 scan_in,
6252 siclk,
6253 soclk,
6254 dout,
6255 scan_out);
6256wire [3:0] fdin;
6257wire [2:0] so;
6258
6259 input [3:0] din;
6260 input l1clk;
6261 input scan_in;
6262
6263
6264 input siclk;
6265 input soclk;
6266
6267 output [3:0] dout;
6268 output scan_out;
6269assign fdin[3:0] = din[3:0];
6270
6271
6272
6273
6274
6275
6276dff #(4) d0_0 (
6277.l1clk(l1clk),
6278.siclk(siclk),
6279.soclk(soclk),
6280.d(fdin[3:0]),
6281.si({scan_in,so[2:0]}),
6282.so({so[2:0],scan_out}),
6283.q(dout[3:0])
6284);
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297endmodule
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311// any PARAMS parms go into naming of macro
6312
6313module l2t_tag_ctl_msff_ctl_macro__width_2 (
6314 din,
6315 l1clk,
6316 scan_in,
6317 siclk,
6318 soclk,
6319 dout,
6320 scan_out);
6321wire [1:0] fdin;
6322wire [0:0] so;
6323
6324 input [1:0] din;
6325 input l1clk;
6326 input scan_in;
6327
6328
6329 input siclk;
6330 input soclk;
6331
6332 output [1:0] dout;
6333 output scan_out;
6334assign fdin[1:0] = din[1:0];
6335
6336
6337
6338
6339
6340
6341dff #(2) d0_0 (
6342.l1clk(l1clk),
6343.siclk(siclk),
6344.soclk(soclk),
6345.d(fdin[1:0]),
6346.si({scan_in,so[0:0]}),
6347.so({so[0:0],scan_out}),
6348.q(dout[1:0])
6349);
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362endmodule
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372// general mux macro for pass-gate and and-or muxes with/wout priority encoders
6373// also for pass-gate with decoder
6374
6375
6376
6377
6378
6379// any PARAMS parms go into naming of macro
6380
6381module l2t_tag_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 (
6382 din0,
6383 sel0,
6384 din1,
6385 sel1,
6386 dout);
6387 input [1:0] din0;
6388 input sel0;
6389 input [1:0] din1;
6390 input sel1;
6391 output [1:0] dout;
6392
6393
6394
6395
6396
6397assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) |
6398 ( {2{sel1}} & din1[1:0]);
6399
6400
6401
6402
6403
6404endmodule
6405
6406
6407
6408
6409
6410
6411// any PARAMS parms go into naming of macro
6412
6413module l2t_tag_ctl_msff_ctl_macro__dmsff_32x__width_16 (
6414 din,
6415 l1clk,
6416 scan_in,
6417 siclk,
6418 soclk,
6419 dout,
6420 scan_out);
6421wire [15:0] fdin;
6422wire [14:0] so;
6423
6424 input [15:0] din;
6425 input l1clk;
6426 input scan_in;
6427
6428
6429 input siclk;
6430 input soclk;
6431
6432 output [15:0] dout;
6433 output scan_out;
6434assign fdin[15:0] = din[15:0];
6435
6436
6437
6438
6439
6440
6441dff #(16) d0_0 (
6442.l1clk(l1clk),
6443.siclk(siclk),
6444.soclk(soclk),
6445.d(fdin[15:0]),
6446.si({scan_in,so[14:0]}),
6447.so({so[14:0],scan_out}),
6448.q(dout[15:0])
6449);
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462endmodule
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476// any PARAMS parms go into naming of macro
6477
6478module l2t_tag_ctl_msff_ctl_macro__clr_1__en_1__width_4 (
6479 din,
6480 en,
6481 clr,
6482 l1clk,
6483 scan_in,
6484 siclk,
6485 soclk,
6486 dout,
6487 scan_out);
6488wire [3:0] fdin;
6489wire [2:0] so;
6490
6491 input [3:0] din;
6492 input en;
6493 input clr;
6494 input l1clk;
6495 input scan_in;
6496
6497
6498 input siclk;
6499 input soclk;
6500
6501 output [3:0] dout;
6502 output scan_out;
6503assign fdin[3:0] = (din[3:0] & {4{en}} & ~{4{clr}}) | (dout[3:0] & ~{4{en}} & ~{4{clr}});
6504
6505
6506
6507
6508
6509
6510dff #(4) d0_0 (
6511.l1clk(l1clk),
6512.siclk(siclk),
6513.soclk(soclk),
6514.d(fdin[3:0]),
6515.si({scan_in,so[2:0]}),
6516.so({so[2:0],scan_out}),
6517.q(dout[3:0])
6518);
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531endmodule
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545// any PARAMS parms go into naming of macro
6546
6547module l2t_tag_ctl_msff_ctl_macro__clr_1__en_1__width_7 (
6548 din,
6549 en,
6550 clr,
6551 l1clk,
6552 scan_in,
6553 siclk,
6554 soclk,
6555 dout,
6556 scan_out);
6557wire [6:0] fdin;
6558wire [5:0] so;
6559
6560 input [6:0] din;
6561 input en;
6562 input clr;
6563 input l1clk;
6564 input scan_in;
6565
6566
6567 input siclk;
6568 input soclk;
6569
6570 output [6:0] dout;
6571 output scan_out;
6572assign fdin[6:0] = (din[6:0] & {7{en}} & ~{7{clr}}) | (dout[6:0] & ~{7{en}} & ~{7{clr}});
6573
6574
6575
6576
6577
6578
6579dff #(7) d0_0 (
6580.l1clk(l1clk),
6581.siclk(siclk),
6582.soclk(soclk),
6583.d(fdin[6:0]),
6584.si({scan_in,so[5:0]}),
6585.so({so[5:0],scan_out}),
6586.q(dout[6:0])
6587);
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600endmodule
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614// any PARAMS parms go into naming of macro
6615
6616module l2t_tag_ctl_msff_ctl_macro__clr_1__en_1__width_1 (
6617 din,
6618 en,
6619 clr,
6620 l1clk,
6621 scan_in,
6622 siclk,
6623 soclk,
6624 dout,
6625 scan_out);
6626wire [0:0] fdin;
6627
6628 input [0:0] din;
6629 input en;
6630 input clr;
6631 input l1clk;
6632 input scan_in;
6633
6634
6635 input siclk;
6636 input soclk;
6637
6638 output [0:0] dout;
6639 output scan_out;
6640assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}});
6641
6642
6643
6644
6645
6646
6647dff #(1) d0_0 (
6648.l1clk(l1clk),
6649.siclk(siclk),
6650.soclk(soclk),
6651.d(fdin[0:0]),
6652.si(scan_in),
6653.so(scan_out),
6654.q(dout[0:0])
6655);
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668endmodule
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682// any PARAMS parms go into naming of macro
6683
6684module l2t_tag_ctl_msff_ctl_macro__clr_1__dmsff_32x__width_2 (
6685 din,
6686 clr,
6687 l1clk,
6688 scan_in,
6689 siclk,
6690 soclk,
6691 dout,
6692 scan_out);
6693wire [1:0] fdin;
6694wire [0:0] so;
6695
6696 input [1:0] din;
6697 input clr;
6698 input l1clk;
6699 input scan_in;
6700
6701
6702 input siclk;
6703 input soclk;
6704
6705 output [1:0] dout;
6706 output scan_out;
6707assign fdin[1:0] = din[1:0] & ~{2{clr}};
6708
6709
6710
6711
6712
6713
6714dff #(2) d0_0 (
6715.l1clk(l1clk),
6716.siclk(siclk),
6717.soclk(soclk),
6718.d(fdin[1:0]),
6719.si({scan_in,so[0:0]}),
6720.so({so[0:0],scan_out}),
6721.q(dout[1:0])
6722);
6723
6724
6725
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735endmodule
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749// any PARAMS parms go into naming of macro
6750
6751module l2t_tag_ctl_msff_ctl_macro__clr_1__width_1 (
6752 din,
6753 clr,
6754 l1clk,
6755 scan_in,
6756 siclk,
6757 soclk,
6758 dout,
6759 scan_out);
6760wire [0:0] fdin;
6761
6762 input [0:0] din;
6763 input clr;
6764 input l1clk;
6765 input scan_in;
6766
6767
6768 input siclk;
6769 input soclk;
6770
6771 output [0:0] dout;
6772 output scan_out;
6773assign fdin[0:0] = din[0:0] & ~{1{clr}};
6774
6775
6776
6777
6778
6779
6780dff #(1) d0_0 (
6781.l1clk(l1clk),
6782.siclk(siclk),
6783.soclk(soclk),
6784.d(fdin[0:0]),
6785.si(scan_in),
6786.so(scan_out),
6787.q(dout[0:0])
6788);
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800
6801endmodule
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815// any PARAMS parms go into naming of macro
6816
6817module l2t_tag_ctl_msff_ctl_macro__clr_1__width_2 (
6818 din,
6819 clr,
6820 l1clk,
6821 scan_in,
6822 siclk,
6823 soclk,
6824 dout,
6825 scan_out);
6826wire [1:0] fdin;
6827wire [0:0] so;
6828
6829 input [1:0] din;
6830 input clr;
6831 input l1clk;
6832 input scan_in;
6833
6834
6835 input siclk;
6836 input soclk;
6837
6838 output [1:0] dout;
6839 output scan_out;
6840assign fdin[1:0] = din[1:0] & ~{2{clr}};
6841
6842
6843
6844
6845
6846
6847dff #(2) d0_0 (
6848.l1clk(l1clk),
6849.siclk(siclk),
6850.soclk(soclk),
6851.d(fdin[1:0]),
6852.si({scan_in,so[0:0]}),
6853.so({so[0:0],scan_out}),
6854.q(dout[1:0])
6855);
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868endmodule
6869
6870
6871
6872
6873
6874
6875
6876
Full OpenSPARC design & verification tarball including full HDL.