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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_tagdp_ctl.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_tagdp_ctl.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016module l2t_tagdp_ctl (
1017 tcu_pce_ov,
1018 tcu_aclk,
1019 tcu_bclk,
1020 tcu_scan_en,
1021 vlddir_vuad_valid_c2,
1022 tag_parity_c2,
1023 tag_way_sel_c2,
1024 tag_way_sel_c2_buff,
1025 vuaddp_vuad_tagd_sel_c2_d1,
1026 bist_way_px,
1027 bist_enable_px,
1028 tagdp_quad0_muxsel_c3,
1029 tagdp_quad1_muxsel_c3,
1030 tagdp_quad2_muxsel_c3,
1031 tagdp_quad3_muxsel_c3,
1032 tagdp_tag_quad_muxsel_c3,
1033 vuad_dp_diag_data_c7,
1034 tagdp_vuad_dp_diag_data_c7_buf,
1035 arbadr_arbdp_diag_wr_way_c2,
1036 arb_tecc_way_c2,
1037 arb_normal_tagacc_c2,
1038 arb_tagd_tecc_c2,
1039 arb_tagd_perr_vld_c2,
1040 misbuf_hit_c3,
1041 mbist_run,
1042 csr_l2_dir_map_on,
1043 arb_l2tag_vld_c4,
1044 arb_vuad_ce_err_c3,
1045 l2clk,
1046 scan_in,
1047 wmr_l,
1048 tagdp_misbuf_par_err_c3,
1049 tagdp_tag_par_err_c3,
1050 tagdp_arb_par_err_c3,
1051 tagdp_tag_error_c8,
1052 scan_out,
1053 usaloc_vuad_used_c2,
1054 usaloc_vuad_alloc_c2,
1055 tagdp_lru_way_sel_c3,
1056 arb_evict_vld_c2,
1057 arb_pf_ice_inst_c2,
1058 tagdp_evict_c3_1,
1059 tagdp_evict_c3_2,
1060 tagdp_invalid_evict_c3);
1061wire pce_ov;
1062wire stop;
1063wire siclk;
1064wire soclk;
1065wire se;
1066wire l1clk;
1067wire spares_scanin;
1068wire spares_scanout;
1069wire ff_tagdp_vuad_dp_diag_data_c7_scanin;
1070wire ff_tagdp_vuad_dp_diag_data_c7_scanout;
1071wire reset_flop_scanin;
1072wire reset_flop_scanout;
1073wire arb_pf_ice_evict_vld_c3;
1074wire ff_evict_c3_1_scanin;
1075wire ff_evict_c3_1_scanout;
1076wire arb_pf_ice_evict_vld_c2;
1077wire ff_evict_c3_2_scanin;
1078wire ff_evict_c3_2_scanout;
1079wire par_err_c3_n;
1080wire arb_pf_ice_evict_vld_c3_n;
1081wire ff_tagd_par_err_c3_scanin;
1082wire ff_tagd_par_err_c3_scanout;
1083wire ff_tagd_par_err_c3_2_scanin;
1084wire ff_tagd_par_err_c3_2_scanout;
1085wire ff_tagdp_misbuf_par_err_c3_scanin;
1086wire ff_tagdp_misbuf_par_err_c3_scanout;
1087wire ff_tagdp_tag_par_err_c3_scanin;
1088wire ff_tagdp_tag_par_err_c3_scanout;
1089wire ff_tagdp_arb_par_err_c3_scanin;
1090wire ff_tagdp_arb_par_err_c3_scanout;
1091wire ff_tagd_par_err_c4_scanin;
1092wire ff_tagd_par_err_c4_scanout;
1093wire ff_tagd_par_err_c5_scanin;
1094wire ff_tagd_par_err_c5_scanout;
1095wire ff_tagd_par_err_c52_scanin;
1096wire ff_tagd_par_err_c52_scanout;
1097wire ff_tag_error_c6_scanin;
1098wire ff_tag_error_c6_scanout;
1099wire ff_tag_error_c7_scanin;
1100wire ff_tag_error_c7_scanout;
1101wire ff_tag_error_c8_scanin;
1102wire ff_tag_error_c8_scanout;
1103wire ff_l2_dir_map_on_d1_scanin;
1104wire ff_l2_dir_map_on_d1_scanout;
1105wire ff_diag_way_c3_scanin;
1106wire ff_diag_way_c3_scanout;
1107wire ff_diag_way_c4_scanin;
1108wire ff_diag_way_c4_scanout;
1109wire ff_lru_quad_muxsel_c2_scanin;
1110wire ff_lru_quad_muxsel_c2_scanout;
1111wire ff_bist_way_c1_scanin;
1112wire ff_bist_way_c1_scanout;
1113wire ff_bist_way_c2_scanin;
1114wire ff_bist_way_c2_scanout;
1115wire ff_bist_enable_c1_scanin;
1116wire ff_bist_enable_c1_scanout;
1117wire ff_bist_enable_c2_scanin;
1118wire ff_bist_enable_c2_scanout;
1119wire ff_mbist_run_scanin;
1120wire ff_mbist_run_scanout;
1121wire mbist_run_r1;
1122wire ff_use_dec_sel_c3_scanin;
1123wire ff_use_dec_sel_c3_scanout;
1124wire ff_tag_quad0_muxsel_c2_scanin;
1125wire ff_tag_quad0_muxsel_c2_scanout;
1126wire ff_tag_quad1_muxsel_c2_scanin;
1127wire ff_tag_quad1_muxsel_c2_scanout;
1128wire ff_tag_quad2_muxsel_c2_scanin;
1129wire ff_tag_quad2_muxsel_c2_scanout;
1130wire ff_tag_quad3_muxsel_c2_scanin;
1131wire ff_tag_quad3_muxsel_c2_scanout;
1132wire ff_dir_quad_way_c3_scanin;
1133wire ff_dir_quad_way_c3_scanout;
1134wire ff_lru_state_scanin;
1135wire ff_lru_state_scanout;
1136wire ff_lru_state_quad0_scanin;
1137wire ff_lru_state_quad0_scanout;
1138wire ff_lru_state_quad1_scanin;
1139wire ff_lru_state_quad1_scanout;
1140wire ff_lru_state_quad2_scanin;
1141wire ff_lru_state_quad2_scanout;
1142wire ff_lru_state_quad3_scanin;
1143wire ff_lru_state_quad3_scanout;
1144wire ff_spec_alloc_c3_scanin;
1145wire ff_spec_alloc_c3_scanout;
1146wire sel_dir_way;
1147wire ff_lru_way_c3_scanin;
1148wire ff_lru_way_c3_scanout;
1149wire ff_lru_way_c3_1_scanin;
1150wire ff_lru_way_c3_1_scanout;
1151wire ff_valid_c3_scanin;
1152wire ff_valid_c3_scanout;
1153
1154
1155 input tcu_pce_ov;
1156 input tcu_aclk;
1157 input tcu_bclk;
1158 input tcu_scan_en;
1159
1160input [15:0] vlddir_vuad_valid_c2; // BS & SR 10/28/03
1161input [15:0] tag_parity_c2; // from tagd.needs to be mapped // BS & SR 10/28/03
1162 // @ the top level.
1163
1164input [15:0] tag_way_sel_c2; // This can be a delayed version of the way selects.POST_3.0, BS & SR 10/28/03
1165
1166output [15:0] tag_way_sel_c2_buff;
1167input vuaddp_vuad_tagd_sel_c2_d1; //POST_3.0
1168
1169// Adding all the mux control logic for tagd and tagl into
1170// this block.
1171// All bist inputs come from a PX2 flop in the bist controller.
1172input [3:0] bist_way_px; // from tagbist
1173input bist_enable_px; // from tagbist
1174
1175
1176 // calculations.
1177output [3:0] tagdp_quad0_muxsel_c3; // BS & SR 10/28/03
1178output [3:0] tagdp_quad1_muxsel_c3; // BS & SR 10/28/03
1179output [3:0] tagdp_quad2_muxsel_c3; // BS & SR 10/28/03
1180output [3:0] tagdp_quad3_muxsel_c3; // BS & SR 10/28/03
1181
1182output [3:0] tagdp_tag_quad_muxsel_c3 ; // to tagd
1183
1184// start int 5.0 change
1185//input [7:0] mbist_write_data; // int 5.0 changes
1186//input [8:0] mbist_l2v_index; // POST_4.2 signals
1187//input mbist_l2v_vd; // POST_4.2 signals
1188//input mbist_l2v_write; // POST_4.2 signals
1189input [38:0] vuad_dp_diag_data_c7 ; // POST_4.2 si
1190
1191//output [7:0] tagdp_bist_vuad_wr_data ;
1192//output [8:0] tagdp_bist_vuad_index; // POST_4.2 signals
1193//output tagdp_bist_vuad_vd; // POST_4.2 signals
1194//output tagdp_bist_vuad_write; // POST_4.2 signals
1195output [38:0] tagdp_vuad_dp_diag_data_c7_buf; // POST_4.2
1196// end int 5.0 change
1197
1198
1199input [3:0] arbadr_arbdp_diag_wr_way_c2 ; // Wr or read way for tag Diagnostic Accesses.
1200input [3:0] arb_tecc_way_c2;
1201input arb_normal_tagacc_c2 ; // indicates that lru way from vuad is used for
1202 // tag selection
1203input arb_tagd_tecc_c2; // NEW_PIN . sel tecc way
1204input arb_tagd_perr_vld_c2; // POST_2.0 PIN
1205input misbuf_hit_c3; // POST_2.0 PIN
1206input mbist_run; // POST_2.0 PIN
1207
1208input csr_l2_dir_map_on; // NEW_PIN from csr
1209input arb_l2tag_vld_c4; // from tag
1210input arb_vuad_ce_err_c3;
1211
1212input l2clk;
1213input scan_in;
1214input wmr_l;
1215
1216
1217
1218
1219output tagdp_misbuf_par_err_c3 ; // can be made a C3 signal.
1220output tagdp_tag_par_err_c3; // used to gate off eviction way
1221output tagdp_arb_par_err_c3; // used to gate off an eviction signal
1222
1223output tagdp_tag_error_c8; // to filbuf and csr.
1224
1225
1226output scan_out;
1227
1228input [15:0] usaloc_vuad_used_c2 ; // BS & SR 10/28/03
1229input [15:0] usaloc_vuad_alloc_c2 ; // BS & SR 10/28/03
1230
1231output [15:0] tagdp_lru_way_sel_c3; // BS & SR 10/28/03
1232
1233// to tagd
1234// All outputs are xmitted in C2 and used in C3.
1235// Buffer the following so that they can transmit to tagd.
1236
1237input arb_evict_vld_c2;
1238input arb_pf_ice_inst_c2;
1239
1240output tagdp_evict_c3_1;
1241output tagdp_evict_c3_2;
1242output tagdp_invalid_evict_c3;
1243
1244
1245
1246
1247wire par_err_c2, par_err_c3;
1248wire tagd_par_err_c4, tagd_par_err_c5, tagd_par_err_c52; // BS 03/11/04 extra cycle for mem access
1249wire tag_error_c6, tag_error_c7 ;
1250
1251
1252wire [3:0] lru_quad0_muxsel_c2 ; // BS & SR 10/28/03
1253wire [3:0] lru_quad1_muxsel_c2 ; // BS & SR 10/28/03
1254wire [3:0] lru_quad2_muxsel_c2 ; // BS & SR 10/28/03
1255wire [3:0] lru_quad3_muxsel_c2 ; // BS & SR 10/28/03
1256
1257
1258wire [3:0] diag_wr_way_c3;
1259wire [3:0] diag_wr_way_c4;
1260
1261wire [3:0] dec_lower_tag_way_c2;
1262wire [3:0] dec_high_tag_way_c2;
1263
1264wire [3:0] bist_way_c1;
1265wire [3:0] bist_way_c2;
1266wire bist_enable_c1;
1267wire bist_enable_c2;
1268
1269wire [3:0] lru_quad_muxsel_c2;
1270wire [3:0] lru_quad_muxsel_c3;
1271
1272wire [3:0] tag_quad0_muxsel_c2 ; // BS & SR 10/28/03
1273wire [3:0] tag_quad1_muxsel_c2 ; // BS & SR 10/28/03
1274wire [3:0] tag_quad2_muxsel_c2 ; // BS & SR 10/28/03
1275wire [3:0] tag_quad3_muxsel_c2 ; // BS & SR 10/28/03
1276
1277wire [3:0] dir_quad0_way_c2, dir_quad1_way_c2 ; // BS & SR 10/28/03
1278wire [3:0] dir_quad2_way_c2, dir_quad3_way_c2 ; // BS & SR 10/28/03
1279
1280wire [3:0] tag_quad0_muxsel_c3; // BS & SR 10/28/03
1281wire [3:0] tag_quad1_muxsel_c3; // BS & SR 10/28/03
1282wire [3:0] tag_quad2_muxsel_c3; // BS & SR 10/28/03
1283wire [3:0] tag_quad3_muxsel_c3; // BS & SR 10/28/03
1284
1285
1286wire [3:0] dir_quad_way_c2;
1287wire [3:0] dir_quad_way_c3;
1288wire sel_bist_way_c2 ;
1289wire sel_diag_way_c4 ;
1290wire sel_tecc_way_c2 ;
1291
1292wire [1:0] enc_high_tag_way_c2;
1293wire [1:0] enc_lower_tag_way_c2;
1294wire use_dec_sel_c2;
1295wire use_dec_sel_c3;
1296wire l2_dir_map_on_d1;
1297wire sel_dir_way_c2; // pick way indicated by addr<21:18>
1298
1299
1300wire [3:0] muxsel_quad0_way_c2 ; // BS & SR 10/28/03
1301wire [3:0] muxsel_quad1_way_c2 ; // BS & SR 10/28/03
1302wire [3:0] muxsel_quad2_way_c2 ; // BS & SR 10/28/03
1303wire [3:0] muxsel_quad3_way_c2 ; // BS & SR 10/28/03
1304wire nondep_tagd_par_err_c3;
1305wire evict_vld_c3_1, evict_vld_c3_2;
1306wire evict_c3_1;
1307
1308
1309wire dbb_rst_l;
1310wire par_err_c3_2;
1311
1312wire [15:0] lru_way_sel_c3_1; // BS & SR 10/28/03
1313wire [15:0] valid_c3; // BS & SR 10/28/03
1314
1315
1316
1317//////////////////////////////////////////////////
1318// L1 clk header
1319//////////////////////////////////////////////////
1320assign pce_ov = tcu_pce_ov;
1321assign stop = 1'b0;
1322assign siclk = tcu_aclk;
1323assign soclk = tcu_bclk;
1324assign se = tcu_scan_en;
1325
1326l2t_tagdp_ctl_l1clkhdr_ctl_macro clkgen (
1327 .l2clk(l2clk),
1328 .l1en(1'b1 ),
1329 .l1clk(l1clk),
1330 .pce_ov(pce_ov),
1331 .stop(stop),
1332 .se(se));
1333
1334//////////////////////////////////////////////////
1335
1336//////////////////////////////////////////
1337// Spare gate insertion
1338//////////////////////////////////////////
1339l2t_tagdp_ctl_spare_ctl_macro__num_4 spares (
1340 .scan_in(spares_scanin),
1341 .scan_out(spares_scanout),
1342 .l1clk (l1clk),
1343 .siclk(siclk),
1344 .soclk(soclk)
1345);
1346//////////////////////////////////////////
1347
1348
1349
1350// int 5.0 changes
1351// ----------------------\/ POST 4.2 repeater addition \/
1352//assign tagdp_bist_vuad_wr_data = mbist_write_data ;
1353//assign tagdp_bist_vuad_write = mbist_l2v_write ;
1354//assign tagdp_bist_vuad_vd = mbist_l2v_vd ;
1355//assign tagdp_bist_vuad_index = mbist_l2v_index ;
1356//assign tagdp_vuad_dp_diag_data_c7_buf = vuad_dp_diag_data_c7 ;
1357
1358
1359l2t_tagdp_ctl_msff_ctl_macro__width_39 ff_tagdp_vuad_dp_diag_data_c7
1360 (
1361 .scan_in(ff_tagdp_vuad_dp_diag_data_c7_scanin),
1362 .scan_out(ff_tagdp_vuad_dp_diag_data_c7_scanout),
1363 .dout (tagdp_vuad_dp_diag_data_c7_buf[38:0]),
1364 .din (vuad_dp_diag_data_c7[38:0]),
1365 .l1clk (l1clk),
1366 .siclk(siclk),
1367 .soclk(soclk)
1368 );
1369
1370
1371
1372
1373
1374
1375// ----------------------\/ POST 4.2 repeater addition \/
1376
1377///////////////////////////////////////////////////////////////////
1378// Reset flop
1379///////////////////////////////////////////////////////////////////
1380
1381l2t_tagdp_ctl_msff_ctl_macro__width_1 reset_flop
1382 (.dout(dbb_rst_l),
1383 .scan_in(reset_flop_scanin),
1384 .scan_out(reset_flop_scanout),
1385 .l1clk(l1clk),
1386 .din(wmr_l),
1387 .siclk(siclk),
1388 .soclk(soclk)
1389);
1390
1391l2t_tagdp_ctl_msff_ctl_macro__dmsff_32x__width_2 ff_evict_c3_1
1392 (.dout ({evict_vld_c3_1,arb_pf_ice_evict_vld_c3}),
1393 .scan_in(ff_evict_c3_1_scanin),
1394 .scan_out(ff_evict_c3_1_scanout),
1395 .din ({arb_evict_vld_c2,arb_pf_ice_evict_vld_c2}),
1396 .l1clk (l1clk),
1397 .siclk(siclk),
1398 .soclk(soclk)
1399 ) ;
1400l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_evict_c3_2
1401 (.dout (evict_vld_c3_2),
1402 .scan_in(ff_evict_c3_2_scanin),
1403 .scan_out(ff_evict_c3_2_scanout),
1404 .din (arb_evict_vld_c2),
1405 .l1clk (l1clk),
1406 .siclk(siclk),
1407 .soclk(soclk)
1408 ) ;
1409
1410/////////////////////
1411// bug id 93679
1412// In case of PF ice the allocate bits should not be set since
1413// there is no instruction filling that place.
1414
1415//timing optimized qualified in usaloc
1416
1417
1418cl_u1_inv_32x inv_par_err_c3_n
1419 (
1420 .out (par_err_c3_n),
1421 .in (par_err_c3)
1422 );
1423
1424cl_u1_inv_32x inv_arb_pf_ice_evict_vld_c3_n
1425 (
1426 .out (arb_pf_ice_evict_vld_c3_n),
1427 .in (arb_pf_ice_evict_vld_c3)
1428 );
1429
1430cl_u1_nand3_24x nand_tagdp_evict_c3_1
1431 (
1432 .in0 (par_err_c3_n),
1433 .in1 (evict_vld_c3_1),
1434 .in2 (arb_pf_ice_evict_vld_c3_n),
1435 .out (tagdp_evict_c3_1)
1436 );
1437
1438//assign tagdp_evict_c3_1 = ~(evict_vld_c3_1 & ~par_err_c3 & ~arb_pf_ice_evict_vld_c3); // & ~arb_vuad_ce_err_c3;
1439
1440assign tagdp_evict_c3_2 = evict_vld_c3_1 & ~par_err_c3 & ~arb_vuad_ce_err_c3; //& ~arb_pf_ice_evict_vld_c3;
1441
1442assign evict_c3_1 = evict_vld_c3_2 & ~par_err_c3_2 & ~arb_vuad_ce_err_c3;
1443
1444
1445// evict qualification is performed in arb.
1446assign tagdp_invalid_evict_c3 = |(lru_way_sel_c3_1 & ~valid_c3) ;
1447
1448
1449
1450////////////////////////////////////////////
1451// The tag compare operation is a 27 bit
1452// compare. The overall Parity bit is
1453// not part of the compare.
1454//
1455// An error in any bit of the tag will cause
1456// the lkup operation to fail except for
1457// that in the overall parity bit.
1458// In case of an error in P, we need to
1459// turn off signalling a parity error.
1460//
1461// That is done using the not_hit_way_c2 signal
1462//assign tagd_par_err_c2 = arb_tagd_perr_vld_c2 & // inst vld from arb
1463// (|( tag_parity_c2 & not_hit_way_c2 )) ;
1464////////////////////////////////////////////
1465
1466////////////////////////////////////////////
1467// An eviction is turned off if
1468// par_err_c3 is asserted. This is becuase
1469// the eviction could very well pick a way
1470// with a corrupted tag and this would end
1471// up in memory corruption.
1472////////////////////////////////////////////
1473
1474
1475// the following signal is used for reporting purposes only
1476assign par_err_c2 = arb_tagd_perr_vld_c2 & |(tag_parity_c2 & vlddir_vuad_valid_c2);
1477
1478
1479// the following signals are used for control in the pipeline.
1480// In misbuf, tag, vuad, arb this par err signal is used
1481// for different purposes. In all cases it is used only for
1482// an EVICT instruction or for a miss.
1483// In misbuf, it is used in the insertion expression provided
1484// the instruction also misses the $ and FB.
1485
1486l2t_tagdp_ctl_msff_ctl_macro__dmsff_32x__width_1 ff_tagd_par_err_c3
1487 (.din(par_err_c2), .l1clk(l1clk),
1488 .scan_in(ff_tagd_par_err_c3_scanin),
1489 .scan_out(ff_tagd_par_err_c3_scanout),
1490 .dout(par_err_c3),
1491 .siclk(siclk),
1492 .soclk(soclk)
1493);
1494
1495l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tagd_par_err_c3_2
1496 (.din(par_err_c2), .l1clk(l1clk),
1497 .scan_in(ff_tagd_par_err_c3_2_scanin),
1498 .scan_out(ff_tagd_par_err_c3_2_scanout),
1499 .dout(par_err_c3_2),
1500 .siclk(siclk),
1501 .soclk(soclk)
1502);
1503
1504l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tagdp_misbuf_par_err_c3
1505 (.din(par_err_c2), .l1clk(l1clk),
1506 .scan_in(ff_tagdp_misbuf_par_err_c3_scanin),
1507 .scan_out(ff_tagdp_misbuf_par_err_c3_scanout),
1508 .dout(tagdp_misbuf_par_err_c3),
1509 .siclk(siclk),
1510 .soclk(soclk)
1511);
1512
1513l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tagdp_tag_par_err_c3
1514 (.din(par_err_c2), .l1clk(l1clk),
1515 .scan_in(ff_tagdp_tag_par_err_c3_scanin),
1516 .scan_out(ff_tagdp_tag_par_err_c3_scanout),
1517 .dout(tagdp_tag_par_err_c3),
1518 .siclk(siclk),
1519 .soclk(soclk)
1520);
1521
1522l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tagdp_arb_par_err_c3
1523 (.din(par_err_c2), .l1clk(l1clk),
1524 .scan_in(ff_tagdp_arb_par_err_c3_scanin),
1525 .scan_out(ff_tagdp_arb_par_err_c3_scanout),
1526 .dout(tagdp_arb_par_err_c3),
1527 .siclk(siclk),
1528 .soclk(soclk)
1529);
1530
1531
1532// In all the destination blocks, vuad, tag, misbuf and arb, this
1533// par_err signal is used only for a non-dep instruction.
1534// Dependents will not report a parity error at all.
1535// Hovewer, reporting is enabled for all hit cases that encounter a
1536// tag corruption.
1537
1538
1539assign nondep_tagd_par_err_c3 = par_err_c3 & ~misbuf_hit_c3;
1540
1541
1542l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tagd_par_err_c4
1543 (.din(nondep_tagd_par_err_c3), .l1clk(l1clk),
1544 .scan_in(ff_tagd_par_err_c4_scanin),
1545 .scan_out(ff_tagd_par_err_c4_scanout),
1546 .dout(tagd_par_err_c4),
1547 .siclk(siclk),
1548 .soclk(soclk)
1549);
1550
1551l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tagd_par_err_c5
1552 (.din(tagd_par_err_c4), .l1clk(l1clk),
1553 .scan_in(ff_tagd_par_err_c5_scanin),
1554 .scan_out(ff_tagd_par_err_c5_scanout),
1555 .dout(tagd_par_err_c5),
1556 .siclk(siclk),
1557 .soclk(soclk)
1558);
1559
1560// BS 03/11/04 extra cycle for mem access
1561
1562l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tagd_par_err_c52
1563 (.din(tagd_par_err_c5), .l1clk(l1clk),
1564 .scan_in(ff_tagd_par_err_c52_scanin),
1565 .scan_out(ff_tagd_par_err_c52_scanout),
1566 .dout(tagd_par_err_c52),
1567 .siclk(siclk),
1568 .soclk(soclk)
1569);
1570
1571
1572l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tag_error_c6
1573 (.din(tagd_par_err_c52), .l1clk(l1clk),
1574 .scan_in(ff_tag_error_c6_scanin),
1575 .scan_out(ff_tag_error_c6_scanout),
1576 .dout(tag_error_c6),
1577 .siclk(siclk),
1578 .soclk(soclk)
1579);
1580
1581l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tag_error_c7
1582 (.din(tag_error_c6), .l1clk(l1clk),
1583 .scan_in(ff_tag_error_c7_scanin),
1584 .scan_out(ff_tag_error_c7_scanout),
1585 .dout(tag_error_c7),
1586 .siclk(siclk),
1587 .soclk(soclk)
1588);
1589
1590l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_tag_error_c8
1591 (.din(tag_error_c7), .l1clk(l1clk),
1592 .scan_in(ff_tag_error_c8_scanin),
1593 .scan_out(ff_tag_error_c8_scanout),
1594 .dout(tagdp_tag_error_c8),
1595 .siclk(siclk),
1596 .soclk(soclk)
1597);
1598
1599
1600
1601/////////////////////////////////////////////
1602// Mux select generation to read
1603// out the evicted tag &
1604// 16:1 muxing of the tag read
1605//
1606// In C2 we generate the muxselects for all the
1607// 4 quads.
1608// These mux selects are generated for the following
1609// 2 categories of accesses.
1610// I)Normal accesses: sels generated by vuad
1611// II) Direct Accesses: Diagnostic/direct mapped, BIST, tecc
1612//
1613// In C3 we generate the mux selects for the 4-1 mux in
1614// this block.
1615/////////////////////////////////////////////
1616
1617// BS 06/24/04 : support for Prefetch ICE.
1618// In case evict instruction is a Prefetch ICE, pick way from 21:18 of the address itself
1619
1620assign arb_pf_ice_evict_vld_c2 = arb_pf_ice_inst_c2 & arb_evict_vld_c2;
1621
1622l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_l2_dir_map_on_d1
1623 (.din(csr_l2_dir_map_on), .l1clk(l1clk),
1624 .scan_in(ff_l2_dir_map_on_d1_scanin),
1625 .scan_out(ff_l2_dir_map_on_d1_scanout),
1626 .dout(l2_dir_map_on_d1),
1627 .siclk(siclk),
1628 .soclk(soclk)
1629);
1630
1631l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_diag_way_c3
1632 (.din(arbadr_arbdp_diag_wr_way_c2[3:0]), .l1clk(l1clk),
1633 .scan_in(ff_diag_way_c3_scanin),
1634 .scan_out(ff_diag_way_c3_scanout),
1635 .dout(diag_wr_way_c3[3:0]),
1636 .siclk(siclk),
1637 .soclk(soclk)
1638);
1639
1640l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_diag_way_c4
1641 (.din(diag_wr_way_c3[3:0]), .l1clk(l1clk),
1642 .scan_in(ff_diag_way_c4_scanin),
1643 .scan_out(ff_diag_way_c4_scanout),
1644 .dout(diag_wr_way_c4[3:0]),
1645 .siclk(siclk),
1646 .soclk(soclk)
1647);
1648
1649l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_lru_quad_muxsel_c2
1650 (.din(lru_quad_muxsel_c2[3:0]), .l1clk(l1clk),
1651 .scan_in(ff_lru_quad_muxsel_c2_scanin),
1652 .scan_out(ff_lru_quad_muxsel_c2_scanout),
1653 .dout(lru_quad_muxsel_c3[3:0]),
1654 .siclk(siclk),
1655 .soclk(soclk)
1656);
1657
1658l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_bist_way_c1
1659 (.din(bist_way_px[3:0]), .l1clk(l1clk),
1660 .scan_in(ff_bist_way_c1_scanin),
1661 .scan_out(ff_bist_way_c1_scanout),
1662 .dout(bist_way_c1[3:0]),
1663 .siclk(siclk),
1664 .soclk(soclk)
1665);
1666
1667l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_bist_way_c2
1668 (.din(bist_way_c1[3:0]), .l1clk(l1clk),
1669 .scan_in(ff_bist_way_c2_scanin),
1670 .scan_out(ff_bist_way_c2_scanout),
1671 .dout(bist_way_c2[3:0]),
1672 .siclk(siclk),
1673 .soclk(soclk)
1674);
1675
1676l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_bist_enable_c1
1677 (.din(bist_enable_px), .l1clk(l1clk),
1678 .scan_in(ff_bist_enable_c1_scanin),
1679 .scan_out(ff_bist_enable_c1_scanout),
1680 .dout(bist_enable_c1),
1681 .siclk(siclk),
1682 .soclk(soclk)
1683);
1684
1685l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_bist_enable_c2
1686 (.din(bist_enable_c1), .l1clk(l1clk),
1687 .scan_in(ff_bist_enable_c2_scanin),
1688 .scan_out(ff_bist_enable_c2_scanout),
1689 .dout(bist_enable_c2),
1690 .siclk(siclk),
1691 .soclk(soclk)
1692);
1693
1694// BS 06/24/04 : support for Prefetch ICE.
1695// In case evict instruction is a Prefetch ICE, pick way from 21:18 of the address itself
1696
1697
1698assign sel_bist_way_c2 = bist_enable_c2 ;
1699assign sel_diag_way_c4 = ~bist_enable_c2 & arb_l2tag_vld_c4;
1700assign sel_tecc_way_c2 = ~bist_enable_c2 & ~arb_l2tag_vld_c4 &
1701 arb_tagd_tecc_c2 ;
1702assign sel_dir_way_c2 = ~arb_tagd_tecc_c2 & ~bist_enable_c2 &
1703 ~arb_l2tag_vld_c4 ;
1704
1705l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_2 mux_way_low
1706 ( .dout (enc_lower_tag_way_c2[1:0]),
1707 .din0(bist_way_c2[1:0]), // bist way c2
1708 .din1(diag_wr_way_c4[1:0]), // diag way c4
1709 .din2(arb_tecc_way_c2[1:0]),// tecc way c2( from a counter in arbdec)
1710 .din3(arbadr_arbdp_diag_wr_way_c2[1:0]),// addr_c2<19:18>
1711 .sel0(sel_bist_way_c2), // bist way sel
1712 .sel1(sel_diag_way_c4), // no bist way sel and diag sel.
1713 .sel2(sel_tecc_way_c2), // tecc way
1714 .sel3(sel_dir_way_c2)); // default is dir mapped way.
1715
1716assign dec_lower_tag_way_c2[0] =(enc_lower_tag_way_c2 == 2'd0 ) ;
1717assign dec_lower_tag_way_c2[1] =(enc_lower_tag_way_c2 == 2'd1 ) ;
1718assign dec_lower_tag_way_c2[2] =(enc_lower_tag_way_c2 == 2'd2 ) ;
1719assign dec_lower_tag_way_c2[3] =(enc_lower_tag_way_c2 == 2'd3 ) ;
1720
1721l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_2 mux_way_high
1722 (.dout (enc_high_tag_way_c2[1:0]),
1723 .din0(bist_way_c2[3:2]), // bist way c2
1724 .din1(diag_wr_way_c4[3:2]), // diag way c4
1725 .din2(arb_tecc_way_c2[3:2]), // tecc way c2( from a counter in arbdec)
1726 .din3(arbadr_arbdp_diag_wr_way_c2[3:2]),// addr_c2<21:20>
1727 .sel0(sel_bist_way_c2), // bist way sel
1728 .sel1(sel_diag_way_c4), // no bist way sel and diag sel.
1729 .sel2(sel_tecc_way_c2), // tecc
1730 .sel3(sel_dir_way_c2)); // default is dir mapped way.
1731
1732assign dec_high_tag_way_c2[0] = (enc_high_tag_way_c2 == 2'd0 ) ;
1733assign dec_high_tag_way_c2[1] = (enc_high_tag_way_c2 == 2'd1 ) ;
1734assign dec_high_tag_way_c2[2] = (enc_high_tag_way_c2 == 2'd2 ) ;
1735assign dec_high_tag_way_c2[3] = (enc_high_tag_way_c2 == 2'd3 ) ;
1736
1737// Quad0 muxselects // BS & SR 10/28/03
1738// Tags in Quad0 correspond to way=0,1,2,3 , // BS & SR 10/28/03
1739
1740assign dir_quad0_way_c2[0] = dec_high_tag_way_c2[0] &
1741 dec_lower_tag_way_c2[0] ; // 0000
1742assign dir_quad0_way_c2[1] = dec_high_tag_way_c2[0] &
1743 dec_lower_tag_way_c2[1] ; // 0001
1744assign dir_quad0_way_c2[2] = dec_high_tag_way_c2[0] &
1745 dec_lower_tag_way_c2[2] ; // 0010
1746assign dir_quad0_way_c2[3] = dec_high_tag_way_c2[0] &
1747 dec_lower_tag_way_c2[3] ; // 0011 // BS & SR 10/28/03
1748
1749
1750assign dir_quad_way_c2[0] = |( dir_quad0_way_c2 ) ; // BS & SR 10/28/03
1751
1752
1753assign muxsel_quad0_way_c2[2:0] = dir_quad0_way_c2[2:0]; // BS & SR 10/28/03
1754assign muxsel_quad0_way_c2[3] = ~( dir_quad0_way_c2[2] | dir_quad0_way_c2[1] |
1755 dir_quad0_way_c2[0] ) ; // BS & SR 10/28/03
1756
1757
1758// Quad1 muxselects // BS & SR 10/28/03
1759// Tags in Quad1 correspond to way=4,5,6,7 // BS & SR 10/28/03
1760
1761assign dir_quad1_way_c2[0] = dec_high_tag_way_c2[1] &
1762 dec_lower_tag_way_c2[0] ; // 0100 // BS & SR 10/28/03
1763
1764assign dir_quad1_way_c2[1] = dec_high_tag_way_c2[1] &
1765 dec_lower_tag_way_c2[1] ; // 0101 // BS & SR 10/28/03
1766
1767assign dir_quad1_way_c2[2] = dec_high_tag_way_c2[1] &
1768 dec_lower_tag_way_c2[2] ; // 0110 // BS & SR 10/28/03
1769
1770assign dir_quad1_way_c2[3] = dec_high_tag_way_c2[1] &
1771 dec_lower_tag_way_c2[3] ; // 0111 // BS & SR 10/28/03
1772
1773assign dir_quad_way_c2[1] = |( dir_quad1_way_c2 ) ; // BS & SR 10/28/03
1774
1775
1776assign muxsel_quad1_way_c2[2:0] = dir_quad1_way_c2[2:0]; // BS & SR 10/28/03
1777assign muxsel_quad1_way_c2[3] = ~( dir_quad1_way_c2[2] | dir_quad1_way_c2[1] |
1778 dir_quad1_way_c2[0] ) ; // BS & SR 10/28/03
1779
1780
1781
1782// Quad2 muxselects
1783// Tags in Quad2 correspond to way=8 ,9, 10,11
1784
1785assign dir_quad2_way_c2[0] = dec_high_tag_way_c2[2] &
1786 dec_lower_tag_way_c2[0] ; // 1000 BS & SR 10/28/03
1787
1788assign dir_quad2_way_c2[1] = dec_high_tag_way_c2[2] &
1789 dec_lower_tag_way_c2[1] ; // 1001 BS & SR 10/28/03
1790
1791assign dir_quad2_way_c2[2] = dec_high_tag_way_c2[2] &
1792 dec_lower_tag_way_c2[2] ; // 1010 BS & SR 10/28/03
1793
1794assign dir_quad2_way_c2[3] = dec_high_tag_way_c2[2] &
1795 dec_lower_tag_way_c2[3] ; // 1011 BS & SR 10/28/03
1796
1797
1798assign dir_quad_way_c2[2] = |( dir_quad2_way_c2 ) ;
1799
1800assign muxsel_quad2_way_c2[2:0] = dir_quad2_way_c2[2:0]; // BS & SR 10/28/03
1801assign muxsel_quad2_way_c2[3] = ~( dir_quad2_way_c2[2] | dir_quad2_way_c2[1] |
1802 dir_quad2_way_c2[0] ) ; // BS & SR 10/28/03
1803
1804// Quad3 muxselects
1805// Tags in Quad3 correspond to way=12, 13, 14, 15
1806
1807assign dir_quad3_way_c2[0] = dec_high_tag_way_c2[3] &
1808 dec_lower_tag_way_c2[0] ; // 1100 BS & SR 10/28/03
1809
1810assign dir_quad3_way_c2[1] = dec_high_tag_way_c2[3] &
1811 dec_lower_tag_way_c2[1] ; // 1101 BS & SR 10/28/03
1812
1813assign dir_quad3_way_c2[2] = dec_high_tag_way_c2[3] &
1814 dec_lower_tag_way_c2[2] ; // 1110 BS & SR 10/28/03
1815
1816assign dir_quad3_way_c2[3] = dec_high_tag_way_c2[3] &
1817 dec_lower_tag_way_c2[3] ; // 1111 BS & SR 10/28/03
1818
1819assign dir_quad_way_c2[3] = |( dir_quad3_way_c2 ) ;
1820
1821assign muxsel_quad3_way_c2[2:0] = dir_quad3_way_c2[2:0]; // BS & SR 10/28/03
1822assign muxsel_quad3_way_c2[3] = ~( dir_quad3_way_c2[2] | dir_quad3_way_c2[1] |
1823 dir_quad3_way_c2[0] ) ; // BS & SR 10/28/03
1824
1825// BS 06/24/04 : support for Prefetch ICE.
1826// In case evict instruction is a Prefetch ICE, pick way from 21:18 of the address itself
1827l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_mbist_run
1828 (
1829 .scan_in(ff_mbist_run_scanin),
1830 .scan_out(ff_mbist_run_scanout),
1831 .dout (mbist_run_r1),
1832 .din (mbist_run),
1833 .l1clk (l1clk),
1834 .siclk(siclk),
1835 .soclk(soclk)
1836 );
1837
1838//
1839//assign use_dec_sel_c2 = ((~arb_normal_tagacc_c2 | l2_dir_map_on_d1
1840// | arb_pf_ice_evict_vld_c2 ) & ~mbist_run_r1 )
1841// | (bist_enable_c2 & mbist_run_r1);
1842//
1843
1844assign use_dec_sel_c2 = mbist_run_r1? bist_enable_c2 :
1845 (~arb_normal_tagacc_c2 | l2_dir_map_on_d1 | arb_pf_ice_evict_vld_c2 );
1846
1847
1848
1849
1850l2t_tagdp_ctl_msff_ctl_macro__width_1 ff_use_dec_sel_c3
1851 (.din(use_dec_sel_c2), .l1clk(l1clk),
1852 .scan_in(ff_use_dec_sel_c3_scanin),
1853 .scan_out(ff_use_dec_sel_c3_scanout),
1854 .dout(use_dec_sel_c3),
1855 .siclk(siclk),
1856 .soclk(soclk)
1857);
1858
1859
1860/////////
1861// QUAD0 // BS & SR 10/28/03
1862/////////
1863
1864// Use a mux flop for the following to reduce the setup on lru_quad0_muxsel_c2
1865l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_tag_quad0_muxsel_c2 // BS & SR 10/28/03
1866 ( .dout (tag_quad0_muxsel_c2[3:0]),
1867 .din0(muxsel_quad0_way_c2[3:0]), // BS & SR 10/28/03
1868 .din1(lru_quad0_muxsel_c2[3:0]),
1869 .sel0(use_dec_sel_c2),
1870 .sel1(~use_dec_sel_c2));
1871
1872l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_tag_quad0_muxsel_c2 // BS & SR 10/28/03
1873 (.din(tag_quad0_muxsel_c2[3:0]), .l1clk(l1clk),
1874 .scan_in(ff_tag_quad0_muxsel_c2_scanin),
1875 .scan_out(ff_tag_quad0_muxsel_c2_scanout),
1876 .dout(tag_quad0_muxsel_c3[3:0]),
1877 .siclk(siclk),
1878 .soclk(soclk)
1879);
1880
1881assign tagdp_quad0_muxsel_c3[3:0] = tag_quad0_muxsel_c3[3:0]; // BS & SR 10/28/03
1882
1883
1884/////////
1885// QUAD1 // BS & SR 10/28/03
1886/////////
1887
1888// Use a mux flop for the following to reduce the setup on lru_quad1_muxsel_c2
1889l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_tag_quad1_muxsel_c2 // BS & SR 10/28/03
1890 ( .dout (tag_quad1_muxsel_c2[3:0]),
1891 .din0(muxsel_quad1_way_c2[3:0]), // BS & SR 10/28/03
1892 .din1(lru_quad1_muxsel_c2[3:0]),
1893 .sel0(use_dec_sel_c2),
1894 .sel1(~use_dec_sel_c2));
1895
1896l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_tag_quad1_muxsel_c2 // BS & SR 10/28/03
1897 (.din(tag_quad1_muxsel_c2[3:0]), .l1clk(l1clk),
1898 .scan_in(ff_tag_quad1_muxsel_c2_scanin),
1899 .scan_out(ff_tag_quad1_muxsel_c2_scanout),
1900 .dout(tag_quad1_muxsel_c3[3:0]),
1901 .siclk(siclk),
1902 .soclk(soclk)
1903 );
1904
1905assign tagdp_quad1_muxsel_c3[3:0] = tag_quad1_muxsel_c3[3:0] ; // BS & SR 10/28/03
1906
1907
1908
1909/////////
1910// QUAD2 // BS & SR 10/28/03
1911/////////
1912
1913// Use a mux flop for the following to reduce the setup on lru_quad2_muxsel_c2
1914l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_tag_quad2_muxsel_c2 // BS & SR 10/28/03
1915 ( .dout (tag_quad2_muxsel_c2[3:0]),
1916 .din0(muxsel_quad2_way_c2[3:0]), // BS & SR 10/28/03
1917 .din1(lru_quad2_muxsel_c2[3:0]),
1918 .sel0(use_dec_sel_c2),
1919 .sel1(~use_dec_sel_c2));
1920
1921l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_tag_quad2_muxsel_c2 // BS & SR 10/28/03
1922 (.din(tag_quad2_muxsel_c2[3:0]), .l1clk(l1clk),
1923 .scan_in(ff_tag_quad2_muxsel_c2_scanin),
1924 .scan_out(ff_tag_quad2_muxsel_c2_scanout),
1925 .dout(tag_quad2_muxsel_c3[3:0]),
1926 .siclk(siclk),
1927 .soclk(soclk)
1928);
1929
1930assign tagdp_quad2_muxsel_c3[3:0] = tag_quad2_muxsel_c3[3:0]; // BS & SR 10/28/03
1931
1932
1933
1934/////////
1935// QUAD3 // BS & SR 10/28/03
1936/////////
1937
1938// Use a mux flop for the following to reduce the setup on lru_quad3_muxsel_c2
1939l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_tag_quad3_muxsel_c2 // BS & SR 10/28/03
1940 ( .dout (tag_quad3_muxsel_c2[3:0]),
1941 .din0(muxsel_quad3_way_c2[3:0]), // BS & SR 10/28/03
1942 .din1(lru_quad3_muxsel_c2[3:0]),
1943 .sel0(use_dec_sel_c2),
1944 .sel1(~use_dec_sel_c2));
1945
1946l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_tag_quad3_muxsel_c2 // BS & SR 10/28/03
1947 (.din(tag_quad3_muxsel_c2[3:0]), .l1clk(l1clk),
1948 .scan_in(ff_tag_quad3_muxsel_c2_scanin),
1949 .scan_out(ff_tag_quad3_muxsel_c2_scanout),
1950 .dout(tag_quad3_muxsel_c3[3:0]),
1951 .siclk(siclk),
1952 .soclk(soclk)
1953);
1954
1955assign tagdp_quad3_muxsel_c3[3:0] = tag_quad3_muxsel_c3[3:0]; // BS & SR 10/28/03
1956
1957l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_dir_quad_way_c3
1958 (.din(dir_quad_way_c2[3:0]), .l1clk(l1clk),
1959 .scan_in(ff_dir_quad_way_c3_scanin),
1960 .scan_out(ff_dir_quad_way_c3_scanout),
1961 .dout(dir_quad_way_c3[3:0]),
1962 .siclk(siclk),
1963 .soclk(soclk)
1964);
1965
1966/////////
1967// QUAD
1968/////////
1969
1970// Use the C5 select from the diagnostic read/BIST or the C3 select from Lru.
1971//
1972assign tagdp_tag_quad_muxsel_c3[0] = use_dec_sel_c3 ? dir_quad_way_c3[0] : lru_quad_muxsel_c3[0];
1973assign tagdp_tag_quad_muxsel_c3[1] = use_dec_sel_c3 ? dir_quad_way_c3[1] : lru_quad_muxsel_c3[1];
1974assign tagdp_tag_quad_muxsel_c3[2] = use_dec_sel_c3 ? dir_quad_way_c3[2] : lru_quad_muxsel_c3[2];
1975assign tagdp_tag_quad_muxsel_c3[3] = use_dec_sel_c3 ? dir_quad_way_c3[3] : lru_quad_muxsel_c3[3];
1976
1977
1978
1979
1980//*****************************************************************************
1981// LRU state flop.
1982// * initialized to 1 on reset.
1983// * left shifted ( rotate) on every eviction.
1984// * else maintains its state.
1985//*****************************************************************************
1986
1987
1988wire lshift_lru_quad0;
1989wire no_lshift_lru_quad0;
1990wire [3:0] lru_state_lshift_quad0;
1991wire [3:0] lru_state_quad0 ;
1992wire [3:0] lru_state_quad0_p ;
1993
1994wire lshift_lru_quad1;
1995wire no_lshift_lru_quad1; // BS & SR 10/28/03
1996wire [3:0] lru_state_lshift_quad1;
1997wire [3:0] lru_state_quad1 ;
1998wire [3:0] lru_state_quad1_p ;
1999
2000wire lshift_lru_quad2;
2001wire no_lshift_lru_quad2;
2002wire [3:0] lru_state_lshift_quad2;
2003wire [3:0] lru_state_quad2 ;
2004wire [3:0] lru_state_quad2_p ;
2005
2006wire lshift_lru_quad3;
2007wire no_lshift_lru_quad3;
2008wire [3:0] lru_state_lshift_quad3;
2009wire [3:0] lru_state_quad3 ;
2010wire [3:0] lru_state_quad3_p ;
2011
2012wire pick_quad0;
2013wire pick_quad1;
2014wire pick_quad2;
2015wire pick_quad3;
2016
2017
2018wire [15:0] vec_unvuad_used_c2;
2019wire [15:0] vec_unvuad_alloc_c2;
2020wire sel_unvuad_used_c2;
2021
2022//wire vuad_way_avail_c2;
2023wire vec_unalloc0to3_c2;
2024wire vec_unalloc4to7_c2;
2025wire vec_unalloc8to11_c2;
2026wire vec_unalloc12to15_c2;
2027
2028wire vec_unused0to3_c2;
2029wire vec_unused4to7_c2;
2030wire vec_unused8to11_c2;
2031wire vec_unused12to15_c2;
2032
2033wire [3:0] used_lru_quad_c2;
2034
2035wire [3:0] used_lru_quad0_c2;
2036wire [3:0] used_lru_quad1_c2;
2037wire [3:0] used_lru_quad2_c2;
2038wire [3:0] used_lru_quad3_c2;
2039
2040wire [3:0] alloc_lru_quad_c2;
2041
2042wire [3:0] alloc_lru_quad0_c2;
2043wire [3:0] alloc_lru_quad1_c2;
2044wire [3:0] alloc_lru_quad2_c2;
2045wire [3:0] alloc_lru_quad3_c2;
2046
2047wire [3:0] used_quad0_tagsel_c2;
2048wire [3:0] alloc_quad0_tagsel_c2;
2049wire [3:0] lru_quad0_tagsel_c2;
2050wire [3:0] used_quad1_tagsel_c2;
2051wire [3:0] alloc_quad1_tagsel_c2;
2052wire [3:0] lru_quad1_tagsel_c2;
2053wire [3:0] used_quad2_tagsel_c2;
2054wire [3:0] alloc_quad2_tagsel_c2;
2055wire [3:0] lru_quad2_tagsel_c2;
2056wire [3:0] used_quad3_tagsel_c2;
2057wire [3:0] alloc_quad3_tagsel_c2;
2058wire [3:0] lru_quad3_tagsel_c2;
2059
2060wire [3:0] used_quad_sel_c2;
2061wire [3:0] alloc_quad_sel_c2;
2062wire [3:0] lru_quad_sel_c2;
2063
2064wire [15:0] lru_way_sel_c2;
2065
2066wire lshift_lru;
2067wire no_lshift_lru;
2068wire [3:0] lru_state_lshift;
2069wire [3:0] lru_state_p;
2070wire [3:0] lru_state;
2071
2072wire init_lru_state;
2073wire [3:0] dec_lo_dir_way_c2;
2074wire [3:0] dec_hi_dir_way_c2;
2075wire [15:0] dec_dir_way_c2;
2076wire [15:0] evict_way_sel_c2;
2077
2078wire [15:0] spec_alloc_c2, spec_alloc_c3;
2079wire [15:0] mod_alloc_c2;
2080
2081
2082////////////////////////////////////////////////////////////////////////////////
2083// LRU algorithm is used to select a way, out of 16 ways, to be evicted out of
2084// the L2 Cache. The algorithm used for the way select is not a tru LRU (Least
2085// Recently Used) algorithm but Round Robin arbitration. Round Robin arbitration
2086// is done in two stages by dividing 16 ways in 4 quads of 4 ways each
2087// quad0[3:0] = Way[3:0],
2088// quad1[3:0] = Way[7:4],
2089// quad2[3:0] = Way[11:8],
2090// quad3[3:0] = Way[15:12].
2091//
2092// First Round Robin is done within each quads to select one of the 4 ways
2093// and then Round Robin is done to select one of the four quads.
2094// A 4 bit one hot shift register maintains the state of the arbiter. An one
2095// at the bit location corresponding to a way represents highest priority for
2096// that way. Everytime an eviction takes place, state register is updated by
2097// shifting it left by one bit otherwise state of the register does not change.
2098// State register is used in C2 for the way selection and it is updated in the
2099// C3. On reset state rtegister is initialized to a state such that way0 has the
2100// highest priority.
2101//
2102// Way selection algorithm depends on the Used and Allocate bit of the VUAD
2103// array, read during C1, for the way selection. First priority is given to the
2104// ways that has not been Used and has not been Allocated for the eviction in
2105// the previous cycle. If there is no Unused and Unallocated way then a way that
2106// has not been previously Allocated is given preference.
2107// Note : Invalid bit is not used for the way selection as if a way is Invalid
2108// then its Used bit will not be set, so checking Invalid bit is
2109// redundant.
2110////////////////////////////////////////////////////////////////////////////////
2111
2112
2113// QUAD ANCHOR
2114
2115assign init_lru_state = ~dbb_rst_l; // piped warm reset
2116
2117
2118assign lshift_lru = evict_c3_1 & ~init_lru_state;
2119assign no_lshift_lru = ~evict_c3_1 & ~init_lru_state ;
2120assign lru_state_lshift = { lru_state[2:0], lru_state[3] } ;
2121
2122l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_lru_st
2123 (.dout (lru_state_p[3:0]),
2124 .din0(4'b0001),
2125 .din1(lru_state_lshift[3:0]),
2126 .din2(lru_state[3:0]),
2127 .sel0(init_lru_state),
2128 .sel1(lshift_lru),
2129 .sel2(no_lshift_lru));
2130
2131
2132l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_lru_state
2133 (.din(lru_state_p[3:0]),
2134 .scan_in(ff_lru_state_scanin),
2135 .scan_out(ff_lru_state_scanout),
2136 .l1clk(l1clk),
2137 .dout(lru_state[3:0]),
2138 .siclk(siclk),
2139 .soclk(soclk)
2140
2141
2142
2143);
2144
2145
2146// Quad0 ANCHOR
2147assign lshift_lru_quad0 = evict_c3_1 & pick_quad0 & ~init_lru_state; // BS & SR 10/28/03
2148assign no_lshift_lru_quad0 = ~( evict_c3_1 & pick_quad0 ) & ~init_lru_state ; // BS & SR 10/28/03
2149assign lru_state_lshift_quad0 = { lru_state_quad0[2:0], lru_state_quad0[3]} ; // BS & SR 10/28/03
2150
2151l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_lru_st_quad0 // BS & SR 10/28/03
2152 (.dout (lru_state_quad0_p[3:0]),
2153 .din0(4'b0001),
2154 .din1(lru_state_lshift_quad0[3:0]),
2155 .din2(lru_state_quad0[3:0]),
2156 .sel0(init_lru_state),
2157 .sel1(lshift_lru_quad0),
2158 .sel2(no_lshift_lru_quad0));
2159
2160
2161l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_lru_state_quad0 // BS & SR 10/28/03
2162 (.din(lru_state_quad0_p[3:0]),
2163 .scan_in(ff_lru_state_quad0_scanin),
2164 .scan_out(ff_lru_state_quad0_scanout),
2165 .l1clk(l1clk),
2166 .dout(lru_state_quad0[3:0]),
2167 .siclk(siclk),
2168 .soclk(soclk)
2169
2170
2171);
2172
2173
2174// Quad1 ANCHOR
2175assign lshift_lru_quad1 = evict_c3_1 & pick_quad1 & ~init_lru_state; // BS & SR 10/28/03
2176assign no_lshift_lru_quad1 = ~( evict_c3_1 & pick_quad1 ) & ~init_lru_state ; // BS & SR 10/28/03
2177assign lru_state_lshift_quad1 = { lru_state_quad1[2:0], lru_state_quad1[3] } ; // BS & SR 10/28/03
2178
2179l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_lru_st_quad1 // BS & SR 10/28/03
2180 (.dout (lru_state_quad1_p[3:0]),
2181 .din0(4'b0001),
2182 .din1(lru_state_lshift_quad1[3:0]),
2183 .din2(lru_state_quad1[3:0]),
2184 .sel0(init_lru_state),
2185 .sel1(lshift_lru_quad1),
2186 .sel2(no_lshift_lru_quad1));
2187
2188
2189l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_lru_state_quad1 // BS & SR 10/28/03
2190 (.din(lru_state_quad1_p[3:0]),
2191 .scan_in(ff_lru_state_quad1_scanin),
2192 .scan_out(ff_lru_state_quad1_scanout),
2193 .l1clk(l1clk),
2194 .dout(lru_state_quad1[3:0]),
2195 .siclk(siclk),
2196 .soclk(soclk)
2197
2198
2199);
2200
2201// Quad2 ANCHOR
2202assign lshift_lru_quad2 = evict_c3_1 & pick_quad2 & ~init_lru_state; // BS & SR 10/28/03
2203assign no_lshift_lru_quad2 = ~( evict_c3_1 & pick_quad2 ) & ~init_lru_state ; // BS & SR 10/28/03
2204assign lru_state_lshift_quad2 = { lru_state_quad2[2:0], lru_state_quad2[3] } ; // BS & SR 10/28/03
2205
2206l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_lru_st_quad2 // BS & SR 10/28/03
2207 (.dout (lru_state_quad2_p[3:0]),
2208 .din0(4'b0001),
2209 .din1(lru_state_lshift_quad2[3:0]),
2210 .din2(lru_state_quad2[3:0]),
2211 .sel0(init_lru_state),
2212 .sel1(lshift_lru_quad2),
2213 .sel2(no_lshift_lru_quad2));
2214
2215
2216l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_lru_state_quad2 // BS & SR 10/28/03
2217 (.din(lru_state_quad2_p[3:0]),
2218 .scan_in(ff_lru_state_quad2_scanin),
2219 .scan_out(ff_lru_state_quad2_scanout),
2220 .l1clk(l1clk),
2221 .dout(lru_state_quad2[3:0]),
2222 .siclk(siclk),
2223 .soclk(soclk)
2224
2225
2226);
2227
2228
2229// Quad3 ANCHOR
2230assign lshift_lru_quad3 = evict_c3_1 & pick_quad3 & ~init_lru_state; // BS & SR 10/28/03
2231assign no_lshift_lru_quad3 = ~( evict_c3_1 & pick_quad3 ) & ~init_lru_state ; // BS & SR 10/28/03
2232assign lru_state_lshift_quad3 = { lru_state_quad3[2:0], lru_state_quad3[3] } ; // BS & SR 10/28/03
2233
2234l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_lru_st_quad3 // BS & SR 10/28/03
2235 (.dout (lru_state_quad3_p[3:0]),
2236 .din0(4'b0001),
2237 .din1(lru_state_lshift_quad3[3:0]),
2238 .din2(lru_state_quad3[3:0]),
2239 .sel0(init_lru_state),
2240 .sel1(lshift_lru_quad3),
2241 .sel2(no_lshift_lru_quad3));
2242
2243
2244l2t_tagdp_ctl_msff_ctl_macro__width_4 ff_lru_state_quad3 // BS & SR 10/28/03
2245 (.din(lru_state_quad3_p[3:0]),
2246 .scan_in(ff_lru_state_quad3_scanin),
2247 .scan_out(ff_lru_state_quad3_scanout),
2248 .l1clk(l1clk),
2249 .dout(lru_state_quad3[3:0]),
2250 .siclk(siclk),
2251 .soclk(soclk)
2252
2253
2254);
2255
2256
2257
2258
2259//************************************************************************************
2260// LRU algorithm
2261// * 3 vectors are computed ( Invalid[15:0], Unused[15:0], Unallocated[15:0] )
2262// * On vector is selected based on the 3 select bits read out of the array in C1,
2263// invalid, unused, unallocated
2264// * A state register is used to decide which quadrant to pick.
2265// * The same state register picks a way in each of the 4 quadrants.
2266//************************************************************************************
2267
2268//
2269// If an instruction in C2 sets the alloc bit, it needs to be bypassed
2270// to the instruction that immediately follows it. This is done speculatively
2271// using the spec_alloc_c3 signal if the instruction in C2 is to the same index
2272// as an instruction in C3.
2273
2274assign tag_way_sel_c2_buff[15:0] = tag_way_sel_c2[15:0];
2275
2276assign spec_alloc_c2 = ( tag_way_sel_c2_buff & vlddir_vuad_valid_c2 ) ;
2277
2278l2t_tagdp_ctl_msff_ctl_macro__width_16 ff_spec_alloc_c3 // BS & SR 10/28/03
2279 (.din(spec_alloc_c2[15:0]),
2280 .scan_in(ff_spec_alloc_c3_scanin),
2281 .scan_out(ff_spec_alloc_c3_scanout),
2282 .l1clk(l1clk), .dout(spec_alloc_c3[15:0]),
2283 .siclk(siclk),
2284 .soclk(soclk)
2285
2286);
2287
2288assign mod_alloc_c2 = ( usaloc_vuad_alloc_c2 |
2289 ( spec_alloc_c3 & {16{vuaddp_vuad_tagd_sel_c2_d1}} ) ); // BS & SR 10/28/03
2290
2291// 2-3 gates.
2292assign vec_unvuad_used_c2 = ~usaloc_vuad_used_c2 & ~mod_alloc_c2 ;
2293assign vec_unvuad_alloc_c2 = ~mod_alloc_c2 ;
2294
2295assign sel_unvuad_used_c2 = |( vec_unvuad_used_c2) ; // WAY lock will be ORED to this
2296
2297// 2-3 gates.
2298assign vec_unused0to3_c2 = |(vec_unvuad_used_c2[3:0]); // BS & SR 10/28/03
2299assign vec_unused4to7_c2 = |(vec_unvuad_used_c2[7:4]); // BS & SR 10/28/03
2300assign vec_unused8to11_c2 = |(vec_unvuad_used_c2[11:8]); // BS & SR 10/28/03
2301assign vec_unused12to15_c2 = |(vec_unvuad_used_c2[15:12]); // BS & SR 10/28/03
2302
2303// vec_unallocxtoxc2 is used to select one of the four quads.
2304assign vec_unalloc0to3_c2 = |(vec_unvuad_alloc_c2[3:0]); // BS & SR 10/28/03
2305assign vec_unalloc4to7_c2 = |(vec_unvuad_alloc_c2[7:4]); // BS & SR 10/28/03
2306assign vec_unalloc8to11_c2 = |(vec_unvuad_alloc_c2[11:8]); // BS & SR 10/28/03
2307assign vec_unalloc12to15_c2 = |(vec_unvuad_alloc_c2[15:12]); // BS & SR 10/28/03
2308
2309
2310/////////////////////////////
2311//UNUSED ROUND ROBIN PICK
2312/////////////////////////////
2313assign used_lru_quad_c2 = { vec_unused12to15_c2, vec_unused8to11_c2, vec_unused4to7_c2, vec_unused0to3_c2 } ;
2314
2315assign used_lru_quad0_c2 = vec_unvuad_used_c2[3:0] ; // BS & SR 10/28/03
2316assign used_lru_quad1_c2 = vec_unvuad_used_c2[7:4] ; // BS & SR 10/28/03
2317assign used_lru_quad2_c2 = vec_unvuad_used_c2[11:8] ; // BS & SR 10/28/03
2318assign used_lru_quad3_c2 = vec_unvuad_used_c2[15:12] ; // BS & SR 10/28/03
2319
2320/////////////////////////////
2321//UNALLOC ROUND ROBIN PICK
2322/////////////////////////////
2323assign alloc_lru_quad_c2 = { vec_unalloc12to15_c2, vec_unalloc8to11_c2, vec_unalloc4to7_c2, vec_unalloc0to3_c2 } ;
2324
2325assign alloc_lru_quad0_c2 = vec_unvuad_alloc_c2[3:0] ; // BS & SR 10/28/03
2326assign alloc_lru_quad1_c2 = vec_unvuad_alloc_c2[7:4] ; // BS & SR 10/28/03
2327assign alloc_lru_quad2_c2 = vec_unvuad_alloc_c2[11:8] ; // BS & SR 10/28/03
2328assign alloc_lru_quad3_c2 = vec_unvuad_alloc_c2[15:12] ; // BS & SR 10/28/03
2329
2330/************ LRU way within quad0 ************************/
2331
2332
2333assign used_quad0_tagsel_c2[0] = used_lru_quad0_c2[0] &
2334 ( lru_state_quad0[0] |
2335 ( lru_state_quad0[1] & ~( used_lru_quad0_c2[1] | used_lru_quad0_c2[2] | used_lru_quad0_c2[3]) ) |
2336 ( lru_state_quad0[2] & ~(used_lru_quad0_c2[2] | used_lru_quad0_c2[3]) ) |
2337 ( lru_state_quad0[3] & ~(used_lru_quad0_c2[3]) ) ) ; // BS & SR 10/28/03
2338
2339assign used_quad0_tagsel_c2[1] = used_lru_quad0_c2[1] &
2340 ( lru_state_quad0[1] |
2341 ( lru_state_quad0[2] & ~( used_lru_quad0_c2[2] | used_lru_quad0_c2[0] | used_lru_quad0_c2[3] )) |
2342 ( lru_state_quad0[3] & ~( used_lru_quad0_c2[3] | used_lru_quad0_c2[0] )) |
2343 ( lru_state_quad0[0] & ~used_lru_quad0_c2[0]) ) ; // BS & SR 10/28/03
2344
2345assign used_quad0_tagsel_c2[2] = used_lru_quad0_c2[2] &
2346 ( lru_state_quad0[2] |
2347 ( lru_state_quad0[3] & ~(used_lru_quad0_c2[0] | used_lru_quad0_c2[1] | used_lru_quad0_c2[3])) |
2348 ( lru_state_quad0[0] & ~(used_lru_quad0_c2[0] | used_lru_quad0_c2[1] )) |
2349 ( lru_state_quad0[1] & ~used_lru_quad0_c2[1] ) ) ; // BS & SR 10/28/03
2350
2351
2352assign used_quad0_tagsel_c2[3] = used_lru_quad0_c2[3] &
2353 ( lru_state_quad0[3] |
2354 ( lru_state_quad0[0] & ~(used_lru_quad0_c2[0] | used_lru_quad0_c2[1] | used_lru_quad0_c2[2])) |
2355 ( lru_state_quad0[1] & ~(used_lru_quad0_c2[2] | used_lru_quad0_c2[1] )) |
2356 ( lru_state_quad0[2] & ~used_lru_quad0_c2[2] ) ) ; // BS & SR 10/28/03
2357
2358
2359
2360assign alloc_quad0_tagsel_c2[0] = alloc_lru_quad0_c2[0] &
2361 ( lru_state_quad0[0] |
2362 ( lru_state_quad0[1] & ~( alloc_lru_quad0_c2[1] | alloc_lru_quad0_c2[2] | alloc_lru_quad0_c2[3] ) ) |
2363 ( lru_state_quad0[2] & ~( alloc_lru_quad0_c2[2] | alloc_lru_quad0_c2[3]) ) |
2364 ( lru_state_quad0[3] & ~alloc_lru_quad0_c2[3] ) ) ; // BS & SR 10/28/03
2365
2366assign alloc_quad0_tagsel_c2[1] = alloc_lru_quad0_c2[1] &
2367 ( lru_state_quad0[1] |
2368 ( lru_state_quad0[2] & ~( alloc_lru_quad0_c2[2] | alloc_lru_quad0_c2[3] | alloc_lru_quad0_c2[0] )) |
2369 ( lru_state_quad0[3] & ~( alloc_lru_quad0_c2[3] | alloc_lru_quad0_c2[0] )) |
2370 ( lru_state_quad0[0] & ~alloc_lru_quad0_c2[0]) ) ; // BS & SR 10/28/03
2371
2372assign alloc_quad0_tagsel_c2[2] = alloc_lru_quad0_c2[2] &
2373 ( lru_state_quad0[2] |
2374 ( lru_state_quad0[3] & ~( alloc_lru_quad0_c2[3] | alloc_lru_quad0_c2[0] | alloc_lru_quad0_c2[1] )) |
2375 ( lru_state_quad0[0] & ~(alloc_lru_quad0_c2[0] | alloc_lru_quad0_c2[1])) |
2376 ( lru_state_quad0[1] & ~alloc_lru_quad0_c2[1] ) ) ; // BS & SR 10/28/03
2377
2378assign alloc_quad0_tagsel_c2[3] = alloc_lru_quad0_c2[3] &
2379 ( lru_state_quad0[3] |
2380 ( lru_state_quad0[0] & ~( alloc_lru_quad0_c2[0] | alloc_lru_quad0_c2[1] | alloc_lru_quad0_c2[2] )) |
2381 ( lru_state_quad0[1] & ~(alloc_lru_quad0_c2[1] | alloc_lru_quad0_c2[2])) |
2382 ( lru_state_quad0[2] & ~alloc_lru_quad0_c2[2] ) ) ; // BS & SR 10/28/03
2383
2384
2385l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_used_lru_quad0 // BS & SR 10/28/03
2386 (.dout (lru_quad0_tagsel_c2[3:0]),
2387 .din0(used_quad0_tagsel_c2[3:0]),
2388 .din1(alloc_quad0_tagsel_c2[3:0]),
2389 .sel0(sel_unvuad_used_c2),
2390 .sel1(~sel_unvuad_used_c2));
2391
2392
2393assign lru_quad0_muxsel_c2[2:0] = lru_quad0_tagsel_c2[2:0] ; // BS & SR Int 5.0 changes
2394assign lru_quad0_muxsel_c2[3] = ~(lru_quad0_tagsel_c2[2] | lru_quad0_tagsel_c2[1] | lru_quad0_tagsel_c2[0]) ; // BS & SR Int 5.0 changes
2395
2396
2397/************ LRU way within Quad1 ************************/
2398
2399
2400assign used_quad1_tagsel_c2[0] = used_lru_quad1_c2[0] &
2401 ( lru_state_quad1[0] |
2402 ( lru_state_quad1[1] & ~( used_lru_quad1_c2[1] | used_lru_quad1_c2[2] | used_lru_quad1_c2[3] ) ) |
2403 ( lru_state_quad1[2] & ~(used_lru_quad1_c2[2] | used_lru_quad1_c2[3] ) ) |
2404 ( lru_state_quad1[3] & ~(used_lru_quad1_c2[3]) ) ) ; // BS & SR 10/28/03
2405
2406assign used_quad1_tagsel_c2[1] = used_lru_quad1_c2[1] &
2407 ( lru_state_quad1[1] |
2408 ( lru_state_quad1[2] & ~( used_lru_quad1_c2[2] | used_lru_quad1_c2[3] | used_lru_quad1_c2[0] )) |
2409 ( lru_state_quad1[3] & ~( used_lru_quad1_c2[3] | used_lru_quad1_c2[0] )) |
2410 ( lru_state_quad1[0] & ~used_lru_quad1_c2[0]) ) ; // BS & SR 10/28/03
2411
2412assign used_quad1_tagsel_c2[2] = used_lru_quad1_c2[2] &
2413 ( lru_state_quad1[2] |
2414 ( lru_state_quad1[3] & ~( used_lru_quad1_c2[3] | used_lru_quad1_c2[0] | used_lru_quad1_c2[1] )) |
2415 ( lru_state_quad1[0] & ~(used_lru_quad1_c2[0] | used_lru_quad1_c2[1])) |
2416 ( lru_state_quad1[1] & ~used_lru_quad1_c2[1] ) ) ; // BS & SR 10/28/03
2417
2418assign used_quad1_tagsel_c2[3] = used_lru_quad1_c2[3] &
2419 ( lru_state_quad1[3] |
2420 ( lru_state_quad1[0] & ~( used_lru_quad1_c2[0] | used_lru_quad1_c2[1] | used_lru_quad1_c2[2] )) |
2421 ( lru_state_quad1[1] & ~(used_lru_quad1_c2[1] | used_lru_quad1_c2[2])) |
2422 ( lru_state_quad1[2] & ~used_lru_quad1_c2[2] ) ) ; // BS & SR 10/28/03
2423
2424
2425
2426
2427assign alloc_quad1_tagsel_c2[0] = alloc_lru_quad1_c2[0] &
2428 ( lru_state_quad1[0] |
2429 ( lru_state_quad1[1] & ~( alloc_lru_quad1_c2[1] | alloc_lru_quad1_c2[2] | alloc_lru_quad1_c2[3] ) ) |
2430 ( lru_state_quad1[2] & ~( alloc_lru_quad1_c2[2] | alloc_lru_quad1_c2[3] ) ) |
2431 ( lru_state_quad1[3] & ~alloc_lru_quad1_c2[3] ) ) ; // BS & SR 10/28/03
2432
2433assign alloc_quad1_tagsel_c2[1] = alloc_lru_quad1_c2[1] &
2434 ( lru_state_quad1[1] |
2435 ( lru_state_quad1[2] & ~( alloc_lru_quad1_c2[2] | alloc_lru_quad1_c2[3] | alloc_lru_quad1_c2[0] )) |
2436 ( lru_state_quad1[3] & ~( alloc_lru_quad1_c2[3] | alloc_lru_quad1_c2[0] ) ) |
2437 ( lru_state_quad1[0] & ~alloc_lru_quad1_c2[0]) ) ; // BS & SR 10/28/03
2438
2439assign alloc_quad1_tagsel_c2[2] = alloc_lru_quad1_c2[2] &
2440 ( lru_state_quad1[2] |
2441 ( lru_state_quad1[3] & ~( alloc_lru_quad1_c2[3] | alloc_lru_quad1_c2[0] | alloc_lru_quad1_c2[1] ) ) |
2442 ( lru_state_quad1[0] & ~(alloc_lru_quad1_c2[0] | alloc_lru_quad1_c2[1])) |
2443 ( lru_state_quad1[1] & ~alloc_lru_quad1_c2[1] ) ) ; // BS & SR 10/28/03
2444
2445assign alloc_quad1_tagsel_c2[3] = alloc_lru_quad1_c2[3] &
2446 ( lru_state_quad1[3] |
2447 ( lru_state_quad1[0] & ~( alloc_lru_quad1_c2[0] | alloc_lru_quad1_c2[1] | alloc_lru_quad1_c2[2] ) ) |
2448 ( lru_state_quad1[1] & ~(alloc_lru_quad1_c2[2] | alloc_lru_quad1_c2[1])) |
2449 ( lru_state_quad1[2] & ~alloc_lru_quad1_c2[2] ) ) ; // BS & SR 10/28/03
2450
2451
2452
2453l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_used_lru_quad1 // BS & SR 10/28/03
2454 (.dout (lru_quad1_tagsel_c2[3:0]),
2455 .din0(used_quad1_tagsel_c2[3:0]),
2456 .din1(alloc_quad1_tagsel_c2[3:0]),
2457 .sel0(sel_unvuad_used_c2),
2458 .sel1(~sel_unvuad_used_c2));
2459
2460
2461assign lru_quad1_muxsel_c2[2:0] = lru_quad1_tagsel_c2[2:0] ; // BS & SR Int 5.0 changes
2462assign lru_quad1_muxsel_c2[3] = ~(lru_quad1_tagsel_c2[2] | lru_quad1_tagsel_c2[1] | lru_quad1_tagsel_c2[0]) ; // BS & SR Int 5.0 changes
2463
2464/************ LRU way within Quad2 ************************/
2465
2466
2467assign used_quad2_tagsel_c2[0] = used_lru_quad2_c2[0] &
2468 ( lru_state_quad2[0] |
2469 ( lru_state_quad2[1] & ~( used_lru_quad2_c2[1] | used_lru_quad2_c2[2] | used_lru_quad2_c2[3] ) ) |
2470 ( lru_state_quad2[2] & ~( used_lru_quad2_c2[2] | used_lru_quad2_c2[3] ) ) |
2471 ( lru_state_quad2[3] & ~used_lru_quad2_c2[3] ) ) ; // BS & SR 10/28/03
2472
2473assign used_quad2_tagsel_c2[1] = used_lru_quad2_c2[1] &
2474 ( lru_state_quad2[1] |
2475 ( lru_state_quad2[2] & ~( used_lru_quad2_c2[2] | used_lru_quad2_c2[3] | used_lru_quad2_c2[0] )) |
2476 ( lru_state_quad2[3] & ~( used_lru_quad2_c2[3] | used_lru_quad2_c2[0] ) ) |
2477 ( lru_state_quad2[0] & ~used_lru_quad2_c2[0]) ) ; // BS & SR 10/28/03
2478
2479assign used_quad2_tagsel_c2[2] = used_lru_quad2_c2[2] &
2480 ( lru_state_quad2[2] |
2481 ( lru_state_quad2[3] & ~(used_lru_quad2_c2[0] | used_lru_quad2_c2[1] | used_lru_quad2_c2[3])) |
2482 ( lru_state_quad2[0] & ~(used_lru_quad2_c2[0] | used_lru_quad2_c2[1])) |
2483 ( lru_state_quad2[1] & ~used_lru_quad2_c2[1] ) ) ; // BS & SR 10/28/03
2484
2485assign used_quad2_tagsel_c2[3] = used_lru_quad2_c2[3] &
2486 ( lru_state_quad2[3] |
2487 ( lru_state_quad2[0] & ~(used_lru_quad2_c2[0] | used_lru_quad2_c2[1] | used_lru_quad2_c2[2])) |
2488 ( lru_state_quad2[1] & ~(used_lru_quad2_c2[2] | used_lru_quad2_c2[1])) |
2489 ( lru_state_quad2[2] & ~used_lru_quad2_c2[2] ) ) ; // BS & SR 10/28/03
2490
2491
2492assign alloc_quad2_tagsel_c2[0] = alloc_lru_quad2_c2[0] &
2493 ( lru_state_quad2[0] |
2494 ( lru_state_quad2[1] & ~( alloc_lru_quad2_c2[1] | alloc_lru_quad2_c2[2] | alloc_lru_quad2_c2[3] ) ) |
2495 ( lru_state_quad2[2] & ~( alloc_lru_quad2_c2[2] | alloc_lru_quad2_c2[3] ) ) |
2496 ( lru_state_quad2[3] & ~alloc_lru_quad2_c2[3] ) ) ; // BS & SR 10/28/03
2497
2498assign alloc_quad2_tagsel_c2[1] = alloc_lru_quad2_c2[1] &
2499 ( lru_state_quad2[1] |
2500 ( lru_state_quad2[2] & ~( alloc_lru_quad2_c2[2] | alloc_lru_quad2_c2[0] | alloc_lru_quad2_c2[3])) |
2501 ( lru_state_quad2[3] & ~( alloc_lru_quad2_c2[3] | alloc_lru_quad2_c2[0] )) |
2502 ( lru_state_quad2[0] & ~alloc_lru_quad2_c2[0]) ) ; // BS & SR 10/28/03
2503
2504assign alloc_quad2_tagsel_c2[2] = alloc_lru_quad2_c2[2] &
2505 ( lru_state_quad2[2] |
2506 ( lru_state_quad2[3] & ~(alloc_lru_quad2_c2[3] | alloc_lru_quad2_c2[1] | alloc_lru_quad2_c2[0] )) |
2507 ( lru_state_quad2[0] & ~(alloc_lru_quad2_c2[0] | alloc_lru_quad2_c2[1] )) |
2508 ( lru_state_quad2[1] & ~alloc_lru_quad2_c2[1] ) ) ; // BS & SR 10/28/03
2509
2510assign alloc_quad2_tagsel_c2[3] = alloc_lru_quad2_c2[3] &
2511 ( lru_state_quad2[3] |
2512 ( lru_state_quad2[0] & ~(alloc_lru_quad2_c2[2] | alloc_lru_quad2_c2[1] | alloc_lru_quad2_c2[0] )) |
2513 ( lru_state_quad2[1] & ~(alloc_lru_quad2_c2[2] | alloc_lru_quad2_c2[1] )) |
2514 ( lru_state_quad2[2] & ~alloc_lru_quad2_c2[2] ) ) ; // BS & SR 10/28/03
2515
2516
2517l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_used_lru_quad2 // BS & SR 10/28/03
2518 (.dout (lru_quad2_tagsel_c2[3:0]),
2519 .din0(used_quad2_tagsel_c2[3:0]),
2520 .din1(alloc_quad2_tagsel_c2[3:0]),
2521 .sel0(sel_unvuad_used_c2),
2522 .sel1(~sel_unvuad_used_c2));
2523
2524
2525assign lru_quad2_muxsel_c2[2:0] = lru_quad2_tagsel_c2[2:0] ; // BS & SR Int 5.0 changes
2526assign lru_quad2_muxsel_c2[3] = ~(lru_quad2_tagsel_c2[2] | lru_quad2_tagsel_c2[1] | lru_quad2_tagsel_c2[0]) ; // BS & SR Int 5.0 changes
2527
2528/************ LRU way within Quad3 ************************/
2529
2530
2531assign used_quad3_tagsel_c2[0] = used_lru_quad3_c2[0] &
2532 ( lru_state_quad3[0] |
2533 ( lru_state_quad3[1] & ~( used_lru_quad3_c2[1] | used_lru_quad3_c2[2] | used_lru_quad3_c2[3] ) ) |
2534 ( lru_state_quad3[2] & ~( used_lru_quad3_c2[3] | used_lru_quad3_c2[2] ) ) |
2535 ( lru_state_quad3[3] & ~used_lru_quad3_c2[3] ) ) ; // BS & SR 10/28/03
2536
2537assign used_quad3_tagsel_c2[1] = used_lru_quad3_c2[1] &
2538 ( lru_state_quad3[1] |
2539 ( lru_state_quad3[2] & ~( used_lru_quad3_c2[2] | used_lru_quad3_c2[0] | used_lru_quad3_c2[3] )) |
2540 ( lru_state_quad3[3] & ~( used_lru_quad3_c2[3] | used_lru_quad3_c2[0] )) |
2541 ( lru_state_quad3[0] & ~used_lru_quad3_c2[0]) ) ; // BS & SR 10/28/03
2542
2543assign used_quad3_tagsel_c2[2] = used_lru_quad3_c2[2] &
2544 ( lru_state_quad3[2] |
2545 ( lru_state_quad3[3] & ~(used_lru_quad3_c2[0] | used_lru_quad3_c2[1] | used_lru_quad3_c2[3] )) |
2546 ( lru_state_quad3[0] & ~(used_lru_quad3_c2[0] | used_lru_quad3_c2[1])) |
2547 ( lru_state_quad3[1] & ~used_lru_quad3_c2[1] ) ) ; // BS & SR 10/28/03
2548
2549assign used_quad3_tagsel_c2[3] = used_lru_quad3_c2[3] &
2550 ( lru_state_quad3[3] |
2551 ( lru_state_quad3[0] & ~(used_lru_quad3_c2[0] | used_lru_quad3_c2[1] | used_lru_quad3_c2[2] )) |
2552 ( lru_state_quad3[1] & ~(used_lru_quad3_c2[1] | used_lru_quad3_c2[2])) |
2553 ( lru_state_quad3[2] & ~used_lru_quad3_c2[2] ) ) ; // BS & SR 10/28/03
2554
2555
2556assign alloc_quad3_tagsel_c2[0] = alloc_lru_quad3_c2[0] &
2557 ( lru_state_quad3[0] |
2558 ( lru_state_quad3[1] & ~( alloc_lru_quad3_c2[1] | alloc_lru_quad3_c2[2] | alloc_lru_quad3_c2[3] ) ) |
2559 ( lru_state_quad3[2] & ~( alloc_lru_quad3_c2[3] | alloc_lru_quad3_c2[2] ) ) |
2560 ( lru_state_quad3[3] & ~alloc_lru_quad3_c2[3] ) ) ; // BS & SR 10/28/03
2561
2562assign alloc_quad3_tagsel_c2[1] = alloc_lru_quad3_c2[1] &
2563 ( lru_state_quad3[1] |
2564 ( lru_state_quad3[2] & ~( alloc_lru_quad3_c2[2] | alloc_lru_quad3_c2[0] | alloc_lru_quad3_c2[3] )) |
2565 ( lru_state_quad3[3] & ~( alloc_lru_quad3_c2[3] | alloc_lru_quad3_c2[0] )) |
2566 ( lru_state_quad3[0] & ~alloc_lru_quad3_c2[0]) ) ; // BS & SR 10/28/03
2567
2568assign alloc_quad3_tagsel_c2[2] = alloc_lru_quad3_c2[2] &
2569 ( lru_state_quad3[2] |
2570 ( lru_state_quad3[3] & ~(alloc_lru_quad3_c2[3] | alloc_lru_quad3_c2[1] | alloc_lru_quad3_c2[0])) |
2571 ( lru_state_quad3[0] & ~(alloc_lru_quad3_c2[0] | alloc_lru_quad3_c2[1])) |
2572 ( lru_state_quad3[1] & ~alloc_lru_quad3_c2[1] ) ) ; // BS & SR 10/28/03
2573
2574assign alloc_quad3_tagsel_c2[3] = alloc_lru_quad3_c2[3] &
2575 ( lru_state_quad3[3] |
2576 ( lru_state_quad3[0] & ~(alloc_lru_quad3_c2[0] | alloc_lru_quad3_c2[1] | alloc_lru_quad3_c2[2])) |
2577 ( lru_state_quad3[1] & ~(alloc_lru_quad3_c2[1] | alloc_lru_quad3_c2[2])) |
2578 ( lru_state_quad3[2] & ~alloc_lru_quad3_c2[2] ) ) ; // BS & SR 10/28/03
2579
2580
2581l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_used_lru_quad3 // BS & SR 10/28/03
2582 (.dout (lru_quad3_tagsel_c2[3:0]),
2583 .din0(used_quad3_tagsel_c2[3:0]),
2584 .din1(alloc_quad3_tagsel_c2[3:0]),
2585 .sel0(sel_unvuad_used_c2),
2586 .sel1(~sel_unvuad_used_c2));
2587
2588
2589assign lru_quad3_muxsel_c2[2:0] = lru_quad3_tagsel_c2[2:0] ; // BS & SR Int 5.0 changes
2590assign lru_quad3_muxsel_c2[3] = ~(lru_quad3_tagsel_c2[2] | lru_quad3_tagsel_c2[1] | lru_quad3_tagsel_c2[0]) ; // BS & SR Int 5.0 changes
2591
2592/************ LRU quad ************************/
2593
2594
2595assign used_quad_sel_c2[0] = used_lru_quad_c2[0] &
2596 ( lru_state[0] |
2597 ( lru_state[1] & ~( used_lru_quad_c2[1] | used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
2598 ( lru_state[2] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
2599 ( lru_state[3] & ~(used_lru_quad_c2[3] )) ) ;
2600
2601assign used_quad_sel_c2[1] = used_lru_quad_c2[1] &
2602 ( lru_state[1] |
2603 ( lru_state[2] & ~( used_lru_quad_c2[0] | used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
2604 ( lru_state[3] & ~( used_lru_quad_c2[3] | used_lru_quad_c2[0] )) |
2605 ( lru_state[0] & ~(used_lru_quad_c2[0] )) ) ;
2606
2607assign used_quad_sel_c2[2] = used_lru_quad_c2[2] &
2608 ( lru_state[2] |
2609 ( lru_state[3] & ~( used_lru_quad_c2[0] | used_lru_quad_c2[1] | used_lru_quad_c2[3] )) |
2610 ( lru_state[0] & ~( used_lru_quad_c2[0] | used_lru_quad_c2[1] )) |
2611 ( lru_state[1] & ~(used_lru_quad_c2[1] )) ) ;
2612
2613assign used_quad_sel_c2[3] = used_lru_quad_c2[3] &
2614 ( lru_state[3] |
2615 ( lru_state[0] & ~( used_lru_quad_c2[0] | used_lru_quad_c2[1] | used_lru_quad_c2[2] )) |
2616 ( lru_state[1] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[1] )) |
2617 ( lru_state[2] & ~(used_lru_quad_c2[2] )) ) ;
2618
2619
2620assign alloc_quad_sel_c2[0] = alloc_lru_quad_c2[0] &
2621 ( lru_state[0] |
2622 ( lru_state[1] & ~( alloc_lru_quad_c2[1] | alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
2623 ( lru_state[2] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
2624 ( lru_state[3] & ~(alloc_lru_quad_c2[3] )) ) ;
2625
2626assign alloc_quad_sel_c2[1] = alloc_lru_quad_c2[1] &
2627 ( lru_state[1] |
2628 ( lru_state[2] & ~( alloc_lru_quad_c2[0] | alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
2629 ( lru_state[3] & ~( alloc_lru_quad_c2[3] | alloc_lru_quad_c2[0] )) |
2630 ( lru_state[0] & ~(alloc_lru_quad_c2[0] )) ) ;
2631
2632assign alloc_quad_sel_c2[2] = alloc_lru_quad_c2[2] &
2633 ( lru_state[2] |
2634 ( lru_state[3] & ~( alloc_lru_quad_c2[0] | alloc_lru_quad_c2[1] | alloc_lru_quad_c2[3] )) |
2635 ( lru_state[0] & ~( alloc_lru_quad_c2[0] | alloc_lru_quad_c2[1] )) |
2636 ( lru_state[1] & ~(alloc_lru_quad_c2[1] )) ) ;
2637
2638assign alloc_quad_sel_c2[3] = alloc_lru_quad_c2[3] &
2639 ( lru_state[3] |
2640 ( lru_state[0] & ~( alloc_lru_quad_c2[0] | alloc_lru_quad_c2[1] | alloc_lru_quad_c2[2] )) |
2641 ( lru_state[1] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[1] )) |
2642 ( lru_state[2] & ~(alloc_lru_quad_c2[2] )) ) ;
2643
2644l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_used_lru_quad
2645 (.dout (lru_quad_sel_c2[3:0]),
2646 .din0(used_quad_sel_c2[3:0]),
2647 .din1(alloc_quad_sel_c2[3:0]),
2648 .sel0(sel_unvuad_used_c2),
2649 .sel1(~sel_unvuad_used_c2));
2650
2651
2652assign lru_quad_muxsel_c2[2:0] = lru_quad_sel_c2[2:0] ; // BS & SR Int 5.0 changes
2653assign lru_quad_muxsel_c2[3] = ~(lru_quad_sel_c2[2] | lru_quad_sel_c2[1] | lru_quad_sel_c2[0]) ; // BS & SR Int 5.0 changes
2654
2655// lru_way_sel_c2 takes 14-15 gates to compute.
2656assign lru_way_sel_c2[3:0] = lru_quad0_tagsel_c2 & {4{lru_quad_sel_c2[0]}} ; // BS & SR 10/28/03
2657assign lru_way_sel_c2[7:4] = lru_quad1_tagsel_c2 & {4{lru_quad_sel_c2[1]}} ; // BS & SR 10/28/03
2658assign lru_way_sel_c2[11:8] = lru_quad2_tagsel_c2 & {4{lru_quad_sel_c2[2]}} ; // BS & SR 10/28/03
2659assign lru_way_sel_c2[15:12] = lru_quad3_tagsel_c2 & {4{lru_quad_sel_c2[3]}} ; // BS & SR 10/28/03
2660
2661
2662assign dec_lo_dir_way_c2[0] = ( arbadr_arbdp_diag_wr_way_c2[1:0]==2'd0 ) ;
2663assign dec_lo_dir_way_c2[1] = ( arbadr_arbdp_diag_wr_way_c2[1:0]==2'd1 ) ;
2664assign dec_lo_dir_way_c2[2] = ( arbadr_arbdp_diag_wr_way_c2[1:0]==2'd2 ) ;
2665assign dec_lo_dir_way_c2[3] = ( arbadr_arbdp_diag_wr_way_c2[1:0]==2'd3 ) ;
2666
2667
2668assign dec_hi_dir_way_c2[0] = ( arbadr_arbdp_diag_wr_way_c2[3:2]==2'd0 ) ;
2669assign dec_hi_dir_way_c2[1] = ( arbadr_arbdp_diag_wr_way_c2[3:2]==2'd1 ) ;
2670assign dec_hi_dir_way_c2[2] = ( arbadr_arbdp_diag_wr_way_c2[3:2]==2'd2 ) ;
2671assign dec_hi_dir_way_c2[3] = ( arbadr_arbdp_diag_wr_way_c2[3:2]==2'd3 ) ;
2672
2673
2674assign dec_dir_way_c2[0] = dec_hi_dir_way_c2[0] & dec_lo_dir_way_c2[0] ; // 0000
2675assign dec_dir_way_c2[1] = dec_hi_dir_way_c2[0] & dec_lo_dir_way_c2[1] ; // 0001
2676assign dec_dir_way_c2[2] = dec_hi_dir_way_c2[0] & dec_lo_dir_way_c2[2] ; // 0010
2677assign dec_dir_way_c2[3] = dec_hi_dir_way_c2[0] & dec_lo_dir_way_c2[3] ; // 0011 // BS & SR 10/28/03
2678assign dec_dir_way_c2[4] = dec_hi_dir_way_c2[1] & dec_lo_dir_way_c2[0] ; // 0100
2679assign dec_dir_way_c2[5] = dec_hi_dir_way_c2[1] & dec_lo_dir_way_c2[1] ; // 0101 // BS & SR 10/28/03
2680assign dec_dir_way_c2[6] = dec_hi_dir_way_c2[1] & dec_lo_dir_way_c2[2] ; // 0110
2681assign dec_dir_way_c2[7] = dec_hi_dir_way_c2[1] & dec_lo_dir_way_c2[3] ; // 0111 // BS & SR 10/28/03
2682assign dec_dir_way_c2[8] = dec_hi_dir_way_c2[2] & dec_lo_dir_way_c2[0] ; // 1000
2683assign dec_dir_way_c2[9] = dec_hi_dir_way_c2[2] & dec_lo_dir_way_c2[1] ; // 1001
2684assign dec_dir_way_c2[10] = dec_hi_dir_way_c2[2] & dec_lo_dir_way_c2[2] ; // 1010
2685assign dec_dir_way_c2[11] = dec_hi_dir_way_c2[2] & dec_lo_dir_way_c2[3] ; // 1011
2686assign dec_dir_way_c2[12] = dec_hi_dir_way_c2[3] & dec_lo_dir_way_c2[0] ; // 1100 // BS & SR 10/28/03
2687assign dec_dir_way_c2[13] = dec_hi_dir_way_c2[3] & dec_lo_dir_way_c2[1] ; // 1101 // BS & SR 10/28/03
2688assign dec_dir_way_c2[14] = dec_hi_dir_way_c2[3] & dec_lo_dir_way_c2[2] ; // 1110 // BS & SR 10/28/03
2689assign dec_dir_way_c2[15] = dec_hi_dir_way_c2[3] & dec_lo_dir_way_c2[3] ; // 1111 // BS & SR 10/28/03
2690
2691
2692// BS 06/24/04 : support for Prefetch ICE.
2693// In case evict instruction is a Prefetch ICE, pick way from 21:18 of the address itself
2694
2695assign sel_dir_way = (arb_pf_ice_evict_vld_c2 | l2_dir_map_on_d1);
2696
2697
2698l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_evict_way_sel_c2 // BS & SR 10/28/03
2699 (.dout (evict_way_sel_c2[15:0]),
2700 .din0 (dec_dir_way_c2[15:0]), .sel0 (sel_dir_way),
2701 .din1 (lru_way_sel_c2[15:0]), .sel1 (~sel_dir_way)
2702 ) ;
2703
2704
2705l2t_tagdp_ctl_msff_ctl_macro__width_16 ff_lru_way_c3 // BS & SR 10/28/03
2706 (.din(evict_way_sel_c2[15:0]),
2707 .scan_in(ff_lru_way_c3_scanin),
2708 .scan_out(ff_lru_way_c3_scanout),
2709 .l1clk(l1clk),
2710 .dout(tagdp_lru_way_sel_c3[15:0]),
2711 .siclk(siclk),
2712 .soclk(soclk)
2713
2714
2715);
2716
2717l2t_tagdp_ctl_msff_ctl_macro__width_16 ff_lru_way_c3_1 // BS & SR 10/28/03
2718 (.din(evict_way_sel_c2[15:0]),
2719 .scan_in(ff_lru_way_c3_1_scanin),
2720 .scan_out(ff_lru_way_c3_1_scanout),
2721 .l1clk(l1clk),
2722 .dout(lru_way_sel_c3_1[15:0]),
2723 .siclk(siclk),
2724 .soclk(soclk)
2725
2726
2727);
2728
2729l2t_tagdp_ctl_msff_ctl_macro__width_16 ff_valid_c3 // BS & SR 10/28/03
2730 (.din(vlddir_vuad_valid_c2[15:0]),
2731 .scan_in(ff_valid_c3_scanin),
2732 .scan_out(ff_valid_c3_scanout),
2733 .l1clk(l1clk),
2734 .dout(valid_c3[15:0]),
2735 .siclk(siclk),
2736 .soclk(soclk)
2737
2738
2739);
2740
2741assign pick_quad0 = |(lru_way_sel_c3_1[3:0] ) ; // BS & SR 10/28/03
2742assign pick_quad1 = |(lru_way_sel_c3_1[7:4] ) ; // BS & SR 10/28/03
2743assign pick_quad2 = |(lru_way_sel_c3_1[11:8] ) ; // BS & SR 10/28/03
2744assign pick_quad3 = |(lru_way_sel_c3_1[15:12]) ; // BS & SR 10/28/03
2745
2746
2747// fixscan start:
2748assign spares_scanin = scan_in ;
2749assign ff_tagdp_vuad_dp_diag_data_c7_scanin = spares_scanout ;
2750assign reset_flop_scanin = ff_tagdp_vuad_dp_diag_data_c7_scanout;
2751assign ff_evict_c3_1_scanin = reset_flop_scanout ;
2752assign ff_evict_c3_2_scanin = ff_evict_c3_1_scanout ;
2753assign ff_tagd_par_err_c3_scanin = ff_evict_c3_2_scanout ;
2754assign ff_tagd_par_err_c3_2_scanin = ff_tagd_par_err_c3_scanout;
2755assign ff_tagdp_misbuf_par_err_c3_scanin = ff_tagd_par_err_c3_2_scanout;
2756assign ff_tagdp_tag_par_err_c3_scanin = ff_tagdp_misbuf_par_err_c3_scanout;
2757assign ff_tagdp_arb_par_err_c3_scanin = ff_tagdp_tag_par_err_c3_scanout;
2758assign ff_tagd_par_err_c4_scanin = ff_tagdp_arb_par_err_c3_scanout;
2759assign ff_tagd_par_err_c5_scanin = ff_tagd_par_err_c4_scanout;
2760assign ff_tagd_par_err_c52_scanin = ff_tagd_par_err_c5_scanout;
2761assign ff_tag_error_c6_scanin = ff_tagd_par_err_c52_scanout;
2762assign ff_tag_error_c7_scanin = ff_tag_error_c6_scanout ;
2763assign ff_tag_error_c8_scanin = ff_tag_error_c7_scanout ;
2764assign ff_l2_dir_map_on_d1_scanin = ff_tag_error_c8_scanout ;
2765assign ff_diag_way_c3_scanin = ff_l2_dir_map_on_d1_scanout;
2766assign ff_diag_way_c4_scanin = ff_diag_way_c3_scanout ;
2767assign ff_lru_quad_muxsel_c2_scanin = ff_diag_way_c4_scanout ;
2768assign ff_bist_way_c1_scanin = ff_lru_quad_muxsel_c2_scanout;
2769assign ff_bist_way_c2_scanin = ff_bist_way_c1_scanout ;
2770assign ff_bist_enable_c1_scanin = ff_bist_way_c2_scanout ;
2771assign ff_bist_enable_c2_scanin = ff_bist_enable_c1_scanout;
2772assign ff_mbist_run_scanin = ff_bist_enable_c2_scanout;
2773assign ff_use_dec_sel_c3_scanin = ff_mbist_run_scanout ;
2774assign ff_tag_quad0_muxsel_c2_scanin = ff_use_dec_sel_c3_scanout;
2775assign ff_tag_quad1_muxsel_c2_scanin = ff_tag_quad0_muxsel_c2_scanout;
2776assign ff_tag_quad2_muxsel_c2_scanin = ff_tag_quad1_muxsel_c2_scanout;
2777assign ff_tag_quad3_muxsel_c2_scanin = ff_tag_quad2_muxsel_c2_scanout;
2778assign ff_dir_quad_way_c3_scanin = ff_tag_quad3_muxsel_c2_scanout;
2779assign ff_lru_state_scanin = ff_dir_quad_way_c3_scanout;
2780assign ff_lru_state_quad0_scanin = ff_lru_state_scanout ;
2781assign ff_lru_state_quad1_scanin = ff_lru_state_quad0_scanout;
2782assign ff_lru_state_quad2_scanin = ff_lru_state_quad1_scanout;
2783assign ff_lru_state_quad3_scanin = ff_lru_state_quad2_scanout;
2784assign ff_spec_alloc_c3_scanin = ff_lru_state_quad3_scanout;
2785assign ff_lru_way_c3_scanin = ff_spec_alloc_c3_scanout ;
2786assign ff_lru_way_c3_1_scanin = ff_lru_way_c3_scanout ;
2787assign ff_valid_c3_scanin = ff_lru_way_c3_1_scanout ;
2788assign scan_out = ff_valid_c3_scanout ;
2789// fixscan end:
2790endmodule
2791
2792
2793
2794
2795
2796
2797
2798// any PARAMS parms go into naming of macro
2799
2800module l2t_tagdp_ctl_l1clkhdr_ctl_macro (
2801 l2clk,
2802 l1en,
2803 pce_ov,
2804 stop,
2805 se,
2806 l1clk);
2807
2808
2809 input l2clk;
2810 input l1en;
2811 input pce_ov;
2812 input stop;
2813 input se;
2814 output l1clk;
2815
2816
2817
2818
2819
2820cl_sc1_l1hdr_8x c_0 (
2821
2822
2823 .l2clk(l2clk),
2824 .pce(l1en),
2825 .l1clk(l1clk),
2826 .se(se),
2827 .pce_ov(pce_ov),
2828 .stop(stop)
2829);
2830
2831
2832
2833endmodule
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843// Description: Spare gate macro for control blocks
2844//
2845// Param num controls the number of times the macro is added
2846// flops=0 can be used to use only combination spare logic
2847
2848
2849module l2t_tagdp_ctl_spare_ctl_macro__num_4 (
2850 l1clk,
2851 scan_in,
2852 siclk,
2853 soclk,
2854 scan_out);
2855wire si_0;
2856wire so_0;
2857wire spare0_flop_unused;
2858wire spare0_buf_32x_unused;
2859wire spare0_nand3_8x_unused;
2860wire spare0_inv_8x_unused;
2861wire spare0_aoi22_4x_unused;
2862wire spare0_buf_8x_unused;
2863wire spare0_oai22_4x_unused;
2864wire spare0_inv_16x_unused;
2865wire spare0_nand2_16x_unused;
2866wire spare0_nor3_4x_unused;
2867wire spare0_nand2_8x_unused;
2868wire spare0_buf_16x_unused;
2869wire spare0_nor2_16x_unused;
2870wire spare0_inv_32x_unused;
2871wire si_1;
2872wire so_1;
2873wire spare1_flop_unused;
2874wire spare1_buf_32x_unused;
2875wire spare1_nand3_8x_unused;
2876wire spare1_inv_8x_unused;
2877wire spare1_aoi22_4x_unused;
2878wire spare1_buf_8x_unused;
2879wire spare1_oai22_4x_unused;
2880wire spare1_inv_16x_unused;
2881wire spare1_nand2_16x_unused;
2882wire spare1_nor3_4x_unused;
2883wire spare1_nand2_8x_unused;
2884wire spare1_buf_16x_unused;
2885wire spare1_nor2_16x_unused;
2886wire spare1_inv_32x_unused;
2887wire si_2;
2888wire so_2;
2889wire spare2_flop_unused;
2890wire spare2_buf_32x_unused;
2891wire spare2_nand3_8x_unused;
2892wire spare2_inv_8x_unused;
2893wire spare2_aoi22_4x_unused;
2894wire spare2_buf_8x_unused;
2895wire spare2_oai22_4x_unused;
2896wire spare2_inv_16x_unused;
2897wire spare2_nand2_16x_unused;
2898wire spare2_nor3_4x_unused;
2899wire spare2_nand2_8x_unused;
2900wire spare2_buf_16x_unused;
2901wire spare2_nor2_16x_unused;
2902wire spare2_inv_32x_unused;
2903wire si_3;
2904wire so_3;
2905wire spare3_flop_unused;
2906wire spare3_buf_32x_unused;
2907wire spare3_nand3_8x_unused;
2908wire spare3_inv_8x_unused;
2909wire spare3_aoi22_4x_unused;
2910wire spare3_buf_8x_unused;
2911wire spare3_oai22_4x_unused;
2912wire spare3_inv_16x_unused;
2913wire spare3_nand2_16x_unused;
2914wire spare3_nor3_4x_unused;
2915wire spare3_nand2_8x_unused;
2916wire spare3_buf_16x_unused;
2917wire spare3_nor2_16x_unused;
2918wire spare3_inv_32x_unused;
2919
2920
2921input l1clk;
2922input scan_in;
2923input siclk;
2924input soclk;
2925output scan_out;
2926
2927cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
2928 .siclk(siclk),
2929 .soclk(soclk),
2930 .si(si_0),
2931 .so(so_0),
2932 .d(1'b0),
2933 .q(spare0_flop_unused));
2934assign si_0 = scan_in;
2935
2936cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
2937 .out(spare0_buf_32x_unused));
2938cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
2939 .in1(1'b1),
2940 .in2(1'b1),
2941 .out(spare0_nand3_8x_unused));
2942cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
2943 .out(spare0_inv_8x_unused));
2944cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
2945 .in01(1'b1),
2946 .in10(1'b1),
2947 .in11(1'b1),
2948 .out(spare0_aoi22_4x_unused));
2949cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
2950 .out(spare0_buf_8x_unused));
2951cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
2952 .in01(1'b1),
2953 .in10(1'b1),
2954 .in11(1'b1),
2955 .out(spare0_oai22_4x_unused));
2956cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
2957 .out(spare0_inv_16x_unused));
2958cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
2959 .in1(1'b1),
2960 .out(spare0_nand2_16x_unused));
2961cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
2962 .in1(1'b0),
2963 .in2(1'b0),
2964 .out(spare0_nor3_4x_unused));
2965cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
2966 .in1(1'b1),
2967 .out(spare0_nand2_8x_unused));
2968cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
2969 .out(spare0_buf_16x_unused));
2970cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
2971 .in1(1'b0),
2972 .out(spare0_nor2_16x_unused));
2973cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
2974 .out(spare0_inv_32x_unused));
2975
2976cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
2977 .siclk(siclk),
2978 .soclk(soclk),
2979 .si(si_1),
2980 .so(so_1),
2981 .d(1'b0),
2982 .q(spare1_flop_unused));
2983assign si_1 = so_0;
2984
2985cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
2986 .out(spare1_buf_32x_unused));
2987cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
2988 .in1(1'b1),
2989 .in2(1'b1),
2990 .out(spare1_nand3_8x_unused));
2991cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
2992 .out(spare1_inv_8x_unused));
2993cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
2994 .in01(1'b1),
2995 .in10(1'b1),
2996 .in11(1'b1),
2997 .out(spare1_aoi22_4x_unused));
2998cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
2999 .out(spare1_buf_8x_unused));
3000cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
3001 .in01(1'b1),
3002 .in10(1'b1),
3003 .in11(1'b1),
3004 .out(spare1_oai22_4x_unused));
3005cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
3006 .out(spare1_inv_16x_unused));
3007cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
3008 .in1(1'b1),
3009 .out(spare1_nand2_16x_unused));
3010cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
3011 .in1(1'b0),
3012 .in2(1'b0),
3013 .out(spare1_nor3_4x_unused));
3014cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
3015 .in1(1'b1),
3016 .out(spare1_nand2_8x_unused));
3017cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
3018 .out(spare1_buf_16x_unused));
3019cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
3020 .in1(1'b0),
3021 .out(spare1_nor2_16x_unused));
3022cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
3023 .out(spare1_inv_32x_unused));
3024
3025cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
3026 .siclk(siclk),
3027 .soclk(soclk),
3028 .si(si_2),
3029 .so(so_2),
3030 .d(1'b0),
3031 .q(spare2_flop_unused));
3032assign si_2 = so_1;
3033
3034cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
3035 .out(spare2_buf_32x_unused));
3036cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
3037 .in1(1'b1),
3038 .in2(1'b1),
3039 .out(spare2_nand3_8x_unused));
3040cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
3041 .out(spare2_inv_8x_unused));
3042cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
3043 .in01(1'b1),
3044 .in10(1'b1),
3045 .in11(1'b1),
3046 .out(spare2_aoi22_4x_unused));
3047cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
3048 .out(spare2_buf_8x_unused));
3049cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
3050 .in01(1'b1),
3051 .in10(1'b1),
3052 .in11(1'b1),
3053 .out(spare2_oai22_4x_unused));
3054cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
3055 .out(spare2_inv_16x_unused));
3056cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
3057 .in1(1'b1),
3058 .out(spare2_nand2_16x_unused));
3059cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
3060 .in1(1'b0),
3061 .in2(1'b0),
3062 .out(spare2_nor3_4x_unused));
3063cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
3064 .in1(1'b1),
3065 .out(spare2_nand2_8x_unused));
3066cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
3067 .out(spare2_buf_16x_unused));
3068cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
3069 .in1(1'b0),
3070 .out(spare2_nor2_16x_unused));
3071cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
3072 .out(spare2_inv_32x_unused));
3073
3074cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
3075 .siclk(siclk),
3076 .soclk(soclk),
3077 .si(si_3),
3078 .so(so_3),
3079 .d(1'b0),
3080 .q(spare3_flop_unused));
3081assign si_3 = so_2;
3082
3083cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
3084 .out(spare3_buf_32x_unused));
3085cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
3086 .in1(1'b1),
3087 .in2(1'b1),
3088 .out(spare3_nand3_8x_unused));
3089cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
3090 .out(spare3_inv_8x_unused));
3091cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
3092 .in01(1'b1),
3093 .in10(1'b1),
3094 .in11(1'b1),
3095 .out(spare3_aoi22_4x_unused));
3096cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
3097 .out(spare3_buf_8x_unused));
3098cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
3099 .in01(1'b1),
3100 .in10(1'b1),
3101 .in11(1'b1),
3102 .out(spare3_oai22_4x_unused));
3103cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
3104 .out(spare3_inv_16x_unused));
3105cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
3106 .in1(1'b1),
3107 .out(spare3_nand2_16x_unused));
3108cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
3109 .in1(1'b0),
3110 .in2(1'b0),
3111 .out(spare3_nor3_4x_unused));
3112cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
3113 .in1(1'b1),
3114 .out(spare3_nand2_8x_unused));
3115cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
3116 .out(spare3_buf_16x_unused));
3117cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
3118 .in1(1'b0),
3119 .out(spare3_nor2_16x_unused));
3120cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
3121 .out(spare3_inv_32x_unused));
3122assign scan_out = so_3;
3123
3124
3125
3126endmodule
3127
3128
3129
3130
3131
3132
3133// any PARAMS parms go into naming of macro
3134
3135module l2t_tagdp_ctl_msff_ctl_macro__width_39 (
3136 din,
3137 l1clk,
3138 scan_in,
3139 siclk,
3140 soclk,
3141 dout,
3142 scan_out);
3143wire [38:0] fdin;
3144wire [37:0] so;
3145
3146 input [38:0] din;
3147 input l1clk;
3148 input scan_in;
3149
3150
3151 input siclk;
3152 input soclk;
3153
3154 output [38:0] dout;
3155 output scan_out;
3156assign fdin[38:0] = din[38:0];
3157
3158
3159
3160
3161
3162
3163dff #(39) d0_0 (
3164.l1clk(l1clk),
3165.siclk(siclk),
3166.soclk(soclk),
3167.d(fdin[38:0]),
3168.si({scan_in,so[37:0]}),
3169.so({so[37:0],scan_out}),
3170.q(dout[38:0])
3171);
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184endmodule
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198// any PARAMS parms go into naming of macro
3199
3200module l2t_tagdp_ctl_msff_ctl_macro__width_1 (
3201 din,
3202 l1clk,
3203 scan_in,
3204 siclk,
3205 soclk,
3206 dout,
3207 scan_out);
3208wire [0:0] fdin;
3209
3210 input [0:0] din;
3211 input l1clk;
3212 input scan_in;
3213
3214
3215 input siclk;
3216 input soclk;
3217
3218 output [0:0] dout;
3219 output scan_out;
3220assign fdin[0:0] = din[0:0];
3221
3222
3223
3224
3225
3226
3227dff #(1) d0_0 (
3228.l1clk(l1clk),
3229.siclk(siclk),
3230.soclk(soclk),
3231.d(fdin[0:0]),
3232.si(scan_in),
3233.so(scan_out),
3234.q(dout[0:0])
3235);
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248endmodule
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262// any PARAMS parms go into naming of macro
3263
3264module l2t_tagdp_ctl_msff_ctl_macro__dmsff_32x__width_2 (
3265 din,
3266 l1clk,
3267 scan_in,
3268 siclk,
3269 soclk,
3270 dout,
3271 scan_out);
3272wire [1:0] fdin;
3273wire [0:0] so;
3274
3275 input [1:0] din;
3276 input l1clk;
3277 input scan_in;
3278
3279
3280 input siclk;
3281 input soclk;
3282
3283 output [1:0] dout;
3284 output scan_out;
3285assign fdin[1:0] = din[1:0];
3286
3287
3288
3289
3290
3291
3292dff #(2) d0_0 (
3293.l1clk(l1clk),
3294.siclk(siclk),
3295.soclk(soclk),
3296.d(fdin[1:0]),
3297.si({scan_in,so[0:0]}),
3298.so({so[0:0],scan_out}),
3299.q(dout[1:0])
3300);
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313endmodule
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327// any PARAMS parms go into naming of macro
3328
3329module l2t_tagdp_ctl_msff_ctl_macro__dmsff_32x__width_1 (
3330 din,
3331 l1clk,
3332 scan_in,
3333 siclk,
3334 soclk,
3335 dout,
3336 scan_out);
3337wire [0:0] fdin;
3338
3339 input [0:0] din;
3340 input l1clk;
3341 input scan_in;
3342
3343
3344 input siclk;
3345 input soclk;
3346
3347 output [0:0] dout;
3348 output scan_out;
3349assign fdin[0:0] = din[0:0];
3350
3351
3352
3353
3354
3355
3356dff #(1) d0_0 (
3357.l1clk(l1clk),
3358.siclk(siclk),
3359.soclk(soclk),
3360.d(fdin[0:0]),
3361.si(scan_in),
3362.so(scan_out),
3363.q(dout[0:0])
3364);
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377endmodule
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391// any PARAMS parms go into naming of macro
3392
3393module l2t_tagdp_ctl_msff_ctl_macro__width_4 (
3394 din,
3395 l1clk,
3396 scan_in,
3397 siclk,
3398 soclk,
3399 dout,
3400 scan_out);
3401wire [3:0] fdin;
3402wire [2:0] so;
3403
3404 input [3:0] din;
3405 input l1clk;
3406 input scan_in;
3407
3408
3409 input siclk;
3410 input soclk;
3411
3412 output [3:0] dout;
3413 output scan_out;
3414assign fdin[3:0] = din[3:0];
3415
3416
3417
3418
3419
3420
3421dff #(4) d0_0 (
3422.l1clk(l1clk),
3423.siclk(siclk),
3424.soclk(soclk),
3425.d(fdin[3:0]),
3426.si({scan_in,so[2:0]}),
3427.so({so[2:0],scan_out}),
3428.q(dout[3:0])
3429);
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442endmodule
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3453// also for pass-gate with decoder
3454
3455
3456
3457
3458
3459// any PARAMS parms go into naming of macro
3460
3461module l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_2 (
3462 din0,
3463 sel0,
3464 din1,
3465 sel1,
3466 din2,
3467 sel2,
3468 din3,
3469 sel3,
3470 dout);
3471 input [1:0] din0;
3472 input sel0;
3473 input [1:0] din1;
3474 input sel1;
3475 input [1:0] din2;
3476 input sel2;
3477 input [1:0] din3;
3478 input sel3;
3479 output [1:0] dout;
3480
3481
3482
3483
3484
3485assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) |
3486 ( {2{sel1}} & din1[1:0]) |
3487 ( {2{sel2}} & din2[1:0]) |
3488 ( {2{sel3}} & din3[1:0]);
3489
3490
3491
3492
3493
3494endmodule
3495
3496
3497// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3498// also for pass-gate with decoder
3499
3500
3501
3502
3503
3504// any PARAMS parms go into naming of macro
3505
3506module l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 (
3507 din0,
3508 sel0,
3509 din1,
3510 sel1,
3511 dout);
3512 input [3:0] din0;
3513 input sel0;
3514 input [3:0] din1;
3515 input sel1;
3516 output [3:0] dout;
3517
3518
3519
3520
3521
3522assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
3523 ( {4{sel1}} & din1[3:0]);
3524
3525
3526
3527
3528
3529endmodule
3530
3531
3532// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3533// also for pass-gate with decoder
3534
3535
3536
3537
3538
3539// any PARAMS parms go into naming of macro
3540
3541module l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 (
3542 din0,
3543 sel0,
3544 din1,
3545 sel1,
3546 din2,
3547 sel2,
3548 dout);
3549 input [3:0] din0;
3550 input sel0;
3551 input [3:0] din1;
3552 input sel1;
3553 input [3:0] din2;
3554 input sel2;
3555 output [3:0] dout;
3556
3557
3558
3559
3560
3561assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
3562 ( {4{sel1}} & din1[3:0]) |
3563 ( {4{sel2}} & din2[3:0]);
3564
3565
3566
3567
3568
3569endmodule
3570
3571
3572
3573
3574
3575
3576// any PARAMS parms go into naming of macro
3577
3578module l2t_tagdp_ctl_msff_ctl_macro__width_16 (
3579 din,
3580 l1clk,
3581 scan_in,
3582 siclk,
3583 soclk,
3584 dout,
3585 scan_out);
3586wire [15:0] fdin;
3587wire [14:0] so;
3588
3589 input [15:0] din;
3590 input l1clk;
3591 input scan_in;
3592
3593
3594 input siclk;
3595 input soclk;
3596
3597 output [15:0] dout;
3598 output scan_out;
3599assign fdin[15:0] = din[15:0];
3600
3601
3602
3603
3604
3605
3606dff #(16) d0_0 (
3607.l1clk(l1clk),
3608.siclk(siclk),
3609.soclk(soclk),
3610.d(fdin[15:0]),
3611.si({scan_in,so[14:0]}),
3612.so({so[14:0],scan_out}),
3613.q(dout[15:0])
3614);
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627endmodule
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637// general mux macro for pass-gate and and-or muxes with/wout priority encoders
3638// also for pass-gate with decoder
3639
3640
3641
3642
3643
3644// any PARAMS parms go into naming of macro
3645
3646module l2t_tagdp_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 (
3647 din0,
3648 sel0,
3649 din1,
3650 sel1,
3651 dout);
3652 input [15:0] din0;
3653 input sel0;
3654 input [15:0] din1;
3655 input sel1;
3656 output [15:0] dout;
3657
3658
3659
3660
3661
3662assign dout[15:0] = ( {16{sel0}} & din0[15:0] ) |
3663 ( {16{sel1}} & din1[15:0]);
3664
3665
3666
3667
3668
3669endmodule
3670
Full OpenSPARC design & verification tarball including full HDL.