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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_tagl_dp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_tagl_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016module l2t_tagl_dp (
1017 tcu_pce_ov,
1018 tcu_aclk,
1019 tcu_bclk,
1020 tcu_scan_en,
1021 tcu_clk_stop,
1022 tcu_muxtest,
1023 tcu_dectest,
1024 way0_tag_c2,
1025 way1_tag_c2,
1026 way2_tag_c2,
1027 way3_tag_c2,
1028 way4_tag_c2,
1029 way5_tag_c2,
1030 way6_tag_c2,
1031 way7_tag_c2,
1032 l2clk,
1033 scan_in,
1034 scan_out,
1035 tagl_parity_c2,
1036 tagl_tag_quad0_c3,
1037 tagl_tag_quad1_c3,
1038 tagdp_quad0_muxsel_c3,
1039 tagdp_quad1_muxsel_c3);
1040wire stop;
1041wire pce_ov;
1042wire siclk;
1043wire soclk;
1044wire se;
1045wire muxtst;
1046wire test;
1047wire ff_tag_way0_4_c3_scanin;
1048wire ff_tag_way0_4_c3_scanout;
1049wire ff_tag_way1_5_c3_scanin;
1050wire ff_tag_way1_5_c3_scanout;
1051wire ff_tag_way2_6_c3_scanin;
1052wire ff_tag_way2_6_c3_scanout;
1053wire ff_tag_way3_7_c3_scanin;
1054wire ff_tag_way3_7_c3_scanout;
1055
1056
1057 input tcu_pce_ov;
1058 input tcu_aclk;
1059 input tcu_bclk;
1060 input tcu_scan_en;
1061 input tcu_clk_stop;
1062 input tcu_muxtest;
1063 input tcu_dectest;
1064
1065input [`TAG_WIDTH-1:0] way0_tag_c2; // tag rd
1066input [`TAG_WIDTH-1:0] way1_tag_c2;// tag rd
1067input [`TAG_WIDTH-1:0] way2_tag_c2;// tag rd
1068input [`TAG_WIDTH-1:0] way3_tag_c2;// tag rd
1069input [`TAG_WIDTH-1:0] way4_tag_c2;// tag rd
1070input [`TAG_WIDTH-1:0] way5_tag_c2;// tag rd
1071input [`TAG_WIDTH-1:0] way6_tag_c2;// tag rd, BS & SR 10/28/03
1072input [`TAG_WIDTH-1:0] way7_tag_c2;// tag rd, BS & SR 10/28/03
1073
1074
1075input l2clk;
1076input scan_in;
1077
1078output scan_out;
1079
1080output [7:0] tagl_parity_c2; // BS & SR 10/28/03
1081output [`TAG_WIDTH-1:0] tagl_tag_quad0_c3;
1082output [`TAG_WIDTH-1:0] tagl_tag_quad1_c3;
1083
1084
1085input [3:0] tagdp_quad0_muxsel_c3; // BS & SR 10/28/03
1086input [3:0] tagdp_quad1_muxsel_c3; // BS & SR 10/28/03
1087
1088
1089assign stop = tcu_clk_stop;
1090assign pce_ov = tcu_pce_ov;
1091assign siclk = tcu_aclk;
1092assign soclk = tcu_bclk;
1093assign se = tcu_scan_en;
1094assign muxtst = tcu_muxtest;
1095assign test = tcu_dectest;
1096
1097
1098//assign scan_out = 1'b0;
1099
1100
1101// All tag bits are staged into C3
1102
1103wire [`TAG_WIDTH-1:0] way0_tag_c3;
1104wire [`TAG_WIDTH-1:0] way1_tag_c3;
1105wire [`TAG_WIDTH-1:0] way2_tag_c3;
1106wire [`TAG_WIDTH-1:0] way3_tag_c3;
1107wire [`TAG_WIDTH-1:0] way4_tag_c3;
1108wire [`TAG_WIDTH-1:0] way5_tag_c3;
1109wire [`TAG_WIDTH-1:0] way6_tag_c3;// BS & SR 10/28/03
1110wire [`TAG_WIDTH-1:0] way7_tag_c3;// BS & SR 10/28/03
1111
1112
1113
1114// This data path is 32 bits wide/
1115
1116
1117
1118//zzpar32 p0_way0 ( .z(tagl_parity_c2[0]), .d({4'b0,way0_tag_c2[`TAG_WIDTH-1:0]}));
1119
1120l2t_tagl_dp_prty_macro__width_32 p0_way0
1121 (
1122 .din ({4'b0,way0_tag_c2[`TAG_WIDTH-1:0]}),
1123 .dout (tagl_parity_c2[0])
1124 );
1125
1126
1127l2t_tagl_dp_msff_macro__minbuff_1__stack_56c__width_56 ff_tag_way0_4_c3
1128 (
1129 .scan_in(ff_tag_way0_4_c3_scanin),
1130 .scan_out(ff_tag_way0_4_c3_scanout),
1131 .din ({way0_tag_c2[`TAG_WIDTH-1:0],way4_tag_c2[`TAG_WIDTH-1:0]}),
1132 .clk (l2clk),
1133 .dout ({way0_tag_c3[`TAG_WIDTH-1:0],way4_tag_c3[`TAG_WIDTH-1:0]}),
1134 .en (1'b1),
1135 .se(se),
1136 .siclk(siclk),
1137 .soclk(soclk),
1138 .pce_ov(pce_ov),
1139 .stop(stop)
1140
1141
1142
1143 );
1144
1145//zzpar32 p0_way1 ( .z(tagl_parity_c2[1]), .d({4'b0,way1_tag_c2[`TAG_WIDTH-1:0]}));
1146
1147l2t_tagl_dp_prty_macro__width_32 p0_way1
1148 (
1149 .din ({4'b0,way1_tag_c2[`TAG_WIDTH-1:0]}),
1150 .dout (tagl_parity_c2[1])
1151 );
1152
1153
1154//zzpar32 p0_way2 ( .z(tagl_parity_c2[2]), .d({4'b0,way2_tag_c2[`TAG_WIDTH-1:0]}));
1155
1156l2t_tagl_dp_prty_macro__width_32 p0_way2
1157 (
1158 .din ({4'b0,way2_tag_c2[`TAG_WIDTH-1:0]}),
1159 .dout (tagl_parity_c2[2])
1160 );
1161
1162
1163l2t_tagl_dp_msff_macro__minbuff_1__stack_56c__width_56 ff_tag_way1_5_c3
1164 (
1165 .scan_in(ff_tag_way1_5_c3_scanin),
1166 .scan_out(ff_tag_way1_5_c3_scanout),
1167 .din ({way1_tag_c2[`TAG_WIDTH-1:0],way5_tag_c2[`TAG_WIDTH-1:0]}),
1168 .clk (l2clk),
1169 .dout ({way1_tag_c3[`TAG_WIDTH-1:0],way5_tag_c3[`TAG_WIDTH-1:0]}),
1170 .en (1'b1),
1171 .se(se),
1172 .siclk(siclk),
1173 .soclk(soclk),
1174 .pce_ov(pce_ov),
1175 .stop(stop)
1176
1177
1178
1179 );
1180
1181
1182//zzpar32 p0_way3 ( .z(tagl_parity_c2[3]), .d({4'b0,way3_tag_c2[`TAG_WIDTH-1:0]}));
1183
1184l2t_tagl_dp_prty_macro__width_32 p0_way3
1185 (
1186 .din ({4'b0,way3_tag_c2[`TAG_WIDTH-1:0]}),
1187 .dout (tagl_parity_c2[3])
1188 );
1189
1190
1191//zzpar32 p0_way4 ( .z(tagl_parity_c2[4]), .d({4'b0,way4_tag_c2[`TAG_WIDTH-1:0]}));
1192
1193l2t_tagl_dp_prty_macro__width_32 p0_way4
1194 (
1195 .din ({4'b0,way4_tag_c2[`TAG_WIDTH-1:0]}),
1196 .dout (tagl_parity_c2[4])
1197 );
1198
1199
1200l2t_tagl_dp_msff_macro__minbuff_1__stack_56c__width_56 ff_tag_way2_6_c3
1201 (
1202 .scan_in(ff_tag_way2_6_c3_scanin),
1203 .scan_out(ff_tag_way2_6_c3_scanout),
1204 .din ({way2_tag_c2[`TAG_WIDTH-1:0],way6_tag_c2[`TAG_WIDTH-1:0]}),
1205 .clk (l2clk),
1206 .dout ({way2_tag_c3[`TAG_WIDTH-1:0],way6_tag_c3[`TAG_WIDTH-1:0]}),
1207 .en (1'b1),
1208 .se(se),
1209 .siclk(siclk),
1210 .soclk(soclk),
1211 .pce_ov(pce_ov),
1212 .stop(stop)
1213
1214
1215
1216 );
1217
1218//zzpar32 p0_way5 ( .z(tagl_parity_c2[5]), .d({4'b0,way5_tag_c2[`TAG_WIDTH-1:0]}));
1219
1220l2t_tagl_dp_prty_macro__width_32 p0_way5
1221 (
1222 .din ({4'b0,way5_tag_c2[`TAG_WIDTH-1:0]}),
1223 .dout (tagl_parity_c2[5])
1224 );
1225
1226
1227// BS & SR 10/28/03
1228l2t_tagl_dp_prty_macro__width_32 p0_way6
1229 (
1230 .din ({4'b0,way6_tag_c2[`TAG_WIDTH-1:0]}),
1231 .dout (tagl_parity_c2[6])
1232 );
1233
1234
1235l2t_tagl_dp_msff_macro__minbuff_1__stack_56c__width_56 ff_tag_way3_7_c3
1236 (
1237 .scan_in(ff_tag_way3_7_c3_scanin),
1238 .scan_out(ff_tag_way3_7_c3_scanout),
1239 .din ({way3_tag_c2[`TAG_WIDTH-1:0],way7_tag_c2[`TAG_WIDTH-1:0]}),
1240 .clk (l2clk),
1241 .dout ({way3_tag_c3[`TAG_WIDTH-1:0],way7_tag_c3[`TAG_WIDTH-1:0]}),
1242 .en (1'b1),
1243 .se(se),
1244 .siclk(siclk),
1245 .soclk(soclk),
1246 .pce_ov(pce_ov),
1247 .stop(stop)
1248
1249
1250
1251 );
1252
1253l2t_tagl_dp_prty_macro__width_32 p0_way7
1254 (
1255 .din ({4'b0,way7_tag_c2[`TAG_WIDTH-1:0]}),
1256 .dout (tagl_parity_c2[7])
1257 );
1258
1259
1260// BS & SR 10/28/03
1261
1262l2t_tagl_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_28r__width_28 mux_tag_quad0 // ATPG CLEANUP
1263 (
1264 .dout (tagl_tag_quad0_c3[`TAG_WIDTH-1:0]),
1265 .din0 (way0_tag_c3[`TAG_WIDTH-1:0]),
1266 .din1 (way1_tag_c3[`TAG_WIDTH-1:0]),
1267 .din2 (way2_tag_c3[`TAG_WIDTH-1:0]),
1268 .din3 (way3_tag_c3[`TAG_WIDTH-1:0]),
1269 .sel0 (tagdp_quad0_muxsel_c3[0]),
1270 .sel1 (tagdp_quad0_muxsel_c3[1]),
1271 .sel2 (tagdp_quad0_muxsel_c3[2]),
1272 .muxtst(muxtst),
1273 .test(test)
1274 );
1275
1276l2t_tagl_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_28l__width_28 mux_tag_quad1 // ATPG CLEANUP
1277 (
1278 .dout (tagl_tag_quad1_c3[`TAG_WIDTH-1:0]),
1279 .din0 (way4_tag_c3[`TAG_WIDTH-1:0]),
1280 .din1 (way5_tag_c3[`TAG_WIDTH-1:0]),
1281 .din2 (way6_tag_c3[`TAG_WIDTH-1:0]),
1282 .din3 (way7_tag_c3[`TAG_WIDTH-1:0]),
1283 .sel0 (tagdp_quad1_muxsel_c3[0]),
1284 .sel1 (tagdp_quad1_muxsel_c3[1]),
1285 .sel2 (tagdp_quad1_muxsel_c3[2]),
1286 .muxtst(muxtst),
1287 .test(test)
1288 );
1289
1290
1291
1292// fixscan start:
1293assign ff_tag_way0_4_c3_scanin = scan_in ;
1294assign ff_tag_way1_5_c3_scanin = ff_tag_way0_4_c3_scanout ;
1295assign ff_tag_way2_6_c3_scanin = ff_tag_way1_5_c3_scanout ;
1296assign ff_tag_way3_7_c3_scanin = ff_tag_way2_6_c3_scanout ;
1297assign scan_out = ff_tag_way3_7_c3_scanout ;
1298// fixscan end:
1299endmodule
1300
1301
1302
1303//
1304// parity macro (even parity)
1305//
1306//
1307
1308
1309
1310
1311
1312module l2t_tagl_dp_prty_macro__width_32 (
1313 din,
1314 dout);
1315 input [31:0] din;
1316 output dout;
1317
1318
1319
1320
1321
1322
1323
1324prty #(32) m0_0 (
1325.in(din[31:0]),
1326.out(dout)
1327);
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338endmodule
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348// any PARAMS parms go into naming of macro
1349
1350module l2t_tagl_dp_msff_macro__minbuff_1__stack_56c__width_56 (
1351 din,
1352 clk,
1353 en,
1354 se,
1355 scan_in,
1356 siclk,
1357 soclk,
1358 pce_ov,
1359 stop,
1360 dout,
1361 scan_out);
1362wire l1clk;
1363wire siclk_out;
1364wire soclk_out;
1365wire [54:0] so;
1366
1367 input [55:0] din;
1368
1369
1370 input clk;
1371 input en;
1372 input se;
1373 input scan_in;
1374 input siclk;
1375 input soclk;
1376 input pce_ov;
1377 input stop;
1378
1379
1380
1381 output [55:0] dout;
1382
1383
1384 output scan_out;
1385
1386
1387
1388
1389cl_dp1_l1hdr_8x c0_0 (
1390.l2clk(clk),
1391.pce(en),
1392.aclk(siclk),
1393.bclk(soclk),
1394.l1clk(l1clk),
1395 .se(se),
1396 .pce_ov(pce_ov),
1397 .stop(stop),
1398 .siclk_out(siclk_out),
1399 .soclk_out(soclk_out)
1400);
1401dff #(56) d0_0 (
1402.l1clk(l1clk),
1403.siclk(siclk_out),
1404.soclk(soclk_out),
1405.d(din[55:0]),
1406.si({scan_in,so[54:0]}),
1407.so({so[54:0],scan_out}),
1408.q(dout[55:0])
1409);
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430endmodule
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440// general mux macro for pass-gate and and-or muxes with/wout priority encoders
1441// also for pass-gate with decoder
1442
1443
1444
1445
1446
1447// any PARAMS parms go into naming of macro
1448
1449module l2t_tagl_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_28r__width_28 (
1450 din0,
1451 din1,
1452 din2,
1453 din3,
1454 sel0,
1455 sel1,
1456 sel2,
1457 muxtst,
1458 test,
1459 dout);
1460wire psel0;
1461wire psel1;
1462wire psel2;
1463wire psel3;
1464
1465 input [27:0] din0;
1466 input [27:0] din1;
1467 input [27:0] din2;
1468 input [27:0] din3;
1469 input sel0;
1470 input sel1;
1471 input sel2;
1472 input muxtst;
1473 input test;
1474 output [27:0] dout;
1475
1476
1477
1478
1479
1480cl_dp1_penc4_8x c0_0 (
1481 .sel0(sel0),
1482 .sel1(sel1),
1483 .sel2(sel2),
1484 .psel0(psel0),
1485 .psel1(psel1),
1486 .psel2(psel2),
1487 .psel3(psel3),
1488 .test(test)
1489);
1490
1491mux4 #(28) d0_0 (
1492 .sel0(psel0),
1493 .sel1(psel1),
1494 .sel2(psel2),
1495 .sel3(psel3),
1496 .in0(din0[27:0]),
1497 .in1(din1[27:0]),
1498 .in2(din2[27:0]),
1499 .in3(din3[27:0]),
1500.dout(dout[27:0]),
1501 .muxtst(muxtst)
1502);
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516endmodule
1517
1518
1519// general mux macro for pass-gate and and-or muxes with/wout priority encoders
1520// also for pass-gate with decoder
1521
1522
1523
1524
1525
1526// any PARAMS parms go into naming of macro
1527
1528module l2t_tagl_dp_mux_macro__dmux_32x__mux_pgpe__ports_4__stack_28l__width_28 (
1529 din0,
1530 din1,
1531 din2,
1532 din3,
1533 sel0,
1534 sel1,
1535 sel2,
1536 muxtst,
1537 test,
1538 dout);
1539wire psel0;
1540wire psel1;
1541wire psel2;
1542wire psel3;
1543
1544 input [27:0] din0;
1545 input [27:0] din1;
1546 input [27:0] din2;
1547 input [27:0] din3;
1548 input sel0;
1549 input sel1;
1550 input sel2;
1551 input muxtst;
1552 input test;
1553 output [27:0] dout;
1554
1555
1556
1557
1558
1559cl_dp1_penc4_8x c0_0 (
1560 .sel0(sel0),
1561 .sel1(sel1),
1562 .sel2(sel2),
1563 .psel0(psel0),
1564 .psel1(psel1),
1565 .psel2(psel2),
1566 .psel3(psel3),
1567 .test(test)
1568);
1569
1570mux4 #(28) d0_0 (
1571 .sel0(psel0),
1572 .sel1(psel1),
1573 .sel2(psel2),
1574 .sel3(psel3),
1575 .in0(din0[27:0]),
1576 .in1(din1[27:0]),
1577 .in2(din2[27:0]),
1578 .in3(din3[27:0]),
1579.dout(dout[27:0]),
1580 .muxtst(muxtst)
1581);
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595endmodule
1596
Full OpenSPARC design & verification tarball including full HDL.