Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_vuadpm_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_vuadpm_dp ( | |
36 | tcu_pce_ov, | |
37 | tcu_aclk, | |
38 | tcu_bclk, | |
39 | tcu_scan_en, | |
40 | tcu_clk_stop, | |
41 | l2clk, | |
42 | scan_in, | |
43 | scan_out, | |
44 | vuadpm_bistordiag_ua_data, | |
45 | vuadpm_bistordiag_vd_data, | |
46 | usaloc_diag_rd_ua_out, | |
47 | vlddir_diag_rd_vd_out, | |
48 | arb_acc_ua_c2, | |
49 | vuadpm_vuad_diag_data_c7, | |
50 | usaloc_ua_synd_c9, | |
51 | vlddir_vd_synd_c9, | |
52 | vuadpm_vd_ue_c4, | |
53 | vuadpm_ua_ue_c4, | |
54 | usaloc_ua_ue_c2, | |
55 | vlddir_vd_ue_c2, | |
56 | usaloc_ua_synd_c2, | |
57 | vlddir_vd_synd_c2, | |
58 | usaloc_ua_ce_c2, | |
59 | vlddir_vd_ce_c2, | |
60 | arbdat_arbdata_wr_data_c2, | |
61 | bist_vuad_data_in, | |
62 | vuaddp_sel_diag1_data_wr_c3, | |
63 | vuaddp_sel_diag0_data_wr_c3, | |
64 | mbist_write_data, | |
65 | bist_vuad_rd_en_px1, | |
66 | mbist_l2vuad_fail); | |
67 | wire stop; | |
68 | wire pce_ov; | |
69 | wire siclk; | |
70 | wire soclk; | |
71 | wire se; | |
72 | wire arb_acc_ua_c2_n; | |
73 | wire ff_diag_out_c3_scanin; | |
74 | wire ff_diag_out_c3_scanout; | |
75 | wire ff_mbist_write_data_scanin; | |
76 | wire ff_mbist_write_data_scanout; | |
77 | wire [7:0] mbist_write_data_px2; | |
78 | wire bist_vuad_rd_en_px2; | |
79 | wire [7:0] mbist_write_data_r1; | |
80 | wire bist_vuad_rd_en_r1; | |
81 | wire [7:0] mbist_write_data_r2; | |
82 | wire bist_vuad_rd_en_r2; | |
83 | wire [7:0] mbist_write_data_r3; | |
84 | wire bist_vuad_rd_en_r3; | |
85 | wire mbist_l2vuad_fail_unreg; | |
86 | wire vuad_fail1; | |
87 | wire vuad_fail2; | |
88 | wire mbist_l2vuad_fail_raw; | |
89 | wire bist_vuad_rd_en_r3_n; | |
90 | wire ff_diag_out_c4_scanin; | |
91 | wire ff_diag_out_c4_scanout; | |
92 | wire ff_diag_out_c5_scanin; | |
93 | wire ff_diag_out_c5_scanout; | |
94 | wire ff_diag_out_c52_scanin; | |
95 | wire ff_diag_out_c52_scanout; | |
96 | wire ff_diag_out_c6_scanin; | |
97 | wire ff_diag_out_c6_scanout; | |
98 | wire ff_diag_out_c7_scanin; | |
99 | wire ff_diag_out_c7_scanout; | |
100 | wire ff_ue_fifo_scanin; | |
101 | wire ff_ue_fifo_scanout; | |
102 | wire vd_ue_c3; | |
103 | wire ua_ue_c3; | |
104 | wire vd_ue_c4; | |
105 | wire ua_ue_c4; | |
106 | wire ff_ua_synd_fifo_scanin; | |
107 | wire ff_ua_synd_fifo_scanout; | |
108 | wire ff_vd_synd_fifo_scanin; | |
109 | wire ff_vd_synd_fifo_scanout; | |
110 | wire [6:0] vlddir_vd_synd_52; | |
111 | wire ff_arbdata_wr_data_c3_scanin; | |
112 | wire ff_arbdata_wr_data_c3_scanout; | |
113 | wire vuaddp_sel_diag1_data_wr_c3_n; | |
114 | wire ff_bistordiag_ua_data_scanin; | |
115 | wire ff_bistordiag_ua_data_scanout; | |
116 | wire vuaddp_sel_diag0_data_wr_c3_n; | |
117 | wire ff_bistordiag_vd_data_scanin; | |
118 | wire ff_bistordiag_vd_data_scanout; | |
119 | ||
120 | ||
121 | input tcu_pce_ov; | |
122 | input tcu_aclk; | |
123 | input tcu_bclk; | |
124 | input tcu_scan_en; | |
125 | input tcu_clk_stop; | |
126 | ||
127 | input l2clk; | |
128 | input scan_in; | |
129 | output scan_out; | |
130 | ||
131 | output [38:0] vuadpm_bistordiag_ua_data; // Left // BS and SR VUAD ECC Change 8/9/04 | |
132 | output [38:0] vuadpm_bistordiag_vd_data; // Right // BS and SR VUAD ECC Change 8/9/04 | |
133 | ||
134 | input [38:0] usaloc_diag_rd_ua_out ; // Left // BS and SR VUAD ECC Change 8/9/04 | |
135 | input [38:0] vlddir_diag_rd_vd_out ; // Right // BS and SR VUAD ECC Change 8/9/04 | |
136 | input arb_acc_ua_c2; // TOP | |
137 | ||
138 | output [38:0] vuadpm_vuad_diag_data_c7; // BS and SR VUAD ECC Change 8/9/04 | |
139 | ||
140 | // New ports VUAD ECC Change | |
141 | output [6:0] usaloc_ua_synd_c9; | |
142 | output [6:0] vlddir_vd_synd_c9; | |
143 | output vuadpm_vd_ue_c4; | |
144 | output vuadpm_ua_ue_c4; | |
145 | ||
146 | input usaloc_ua_ue_c2; | |
147 | input vlddir_vd_ue_c2; | |
148 | input [5:0] usaloc_ua_synd_c2; | |
149 | input [5:0] vlddir_vd_synd_c2; | |
150 | input usaloc_ua_ce_c2; | |
151 | input vlddir_vd_ce_c2; | |
152 | ||
153 | ||
154 | input [38:0] arbdat_arbdata_wr_data_c2; // Top // BS and SR VUAD ECC Change 8/9/04 | |
155 | input [7:0] bist_vuad_data_in; // Top | |
156 | input vuaddp_sel_diag1_data_wr_c3; // Top | |
157 | input vuaddp_sel_diag0_data_wr_c3; // Top | |
158 | ||
159 | input [7:0] mbist_write_data; | |
160 | input bist_vuad_rd_en_px1; | |
161 | ||
162 | output mbist_l2vuad_fail; | |
163 | ||
164 | assign stop = tcu_clk_stop; | |
165 | assign pce_ov = tcu_pce_ov; | |
166 | assign siclk = tcu_aclk; | |
167 | assign soclk = tcu_bclk; | |
168 | assign se = tcu_scan_en; | |
169 | ||
170 | ||
171 | //assign scan_out = 1'b0; | |
172 | ||
173 | ||
174 | // BS and SR VUAD ECC Change 8/9/04 | |
175 | wire [38:0] diag_out_c2; | |
176 | wire [38:0] diag_out_c3; | |
177 | wire [38:0] diag_out_c4; | |
178 | wire [38:0] diag_out_c5; | |
179 | wire [38:0] diag_out_c52; // BS 03/11/04 extra cycle for mem access | |
180 | wire [38:0] diag_out_c6; | |
181 | wire [38:0] diag_out_c7; | |
182 | wire [38:0] diag_out_c8; | |
183 | ||
184 | wire [38:0] bist_data_c3; | |
185 | wire [38:0] arbdata_wr_data_c3; | |
186 | wire [38:0] bistordiag_ua_data_in, bistordiag_vd_data_in; | |
187 | ||
188 | wire [6:0] vlddir_vd_synd_c3; | |
189 | wire [6:0] vlddir_vd_synd_c4; | |
190 | wire [6:0] vlddir_vd_synd_c5; | |
191 | wire [6:0] vlddir_vd_synd_c52; | |
192 | wire [6:0] vlddir_vd_synd_c6; | |
193 | wire [6:0] vlddir_vd_synd_c7; | |
194 | wire [6:0] vlddir_vd_synd_c8; | |
195 | ||
196 | wire [6:0] usaloc_ua_synd_c3; | |
197 | wire [6:0] usaloc_ua_synd_c4; | |
198 | wire [6:0] usaloc_ua_synd_c5; | |
199 | wire [6:0] usaloc_ua_synd_c52; | |
200 | wire [6:0] usaloc_ua_synd_c6; | |
201 | wire [6:0] usaloc_ua_synd_c7; | |
202 | wire [6:0] usaloc_ua_synd_c8; | |
203 | ||
204 | ////////////////////////////// | |
205 | // This is a 39 bit datapath | |
206 | ////////////////////////////// | |
207 | ||
208 | ////////////////////////////// | |
209 | // Use the 26 lfetmost dp pitches for this | |
210 | ////////////////////////////// | |
211 | ||
212 | // Use a 2-1 mux flop to reduce the setup on arb_acc_ua_c2 | |
213 | ||
214 | l2t_vuadpm_dp_inv_macro__width_1 arb_acc_ua_c2_inv_slice ( | |
215 | .dout (arb_acc_ua_c2_n), | |
216 | .din (arb_acc_ua_c2) | |
217 | ); | |
218 | ||
219 | l2t_vuadpm_dp_mux_macro__mux_aonpe__ports_2__stack_39c__width_39 mux_diag_out_c2 // BS and SR VUAD ECC Change 8/9/04 | |
220 | ( | |
221 | .dout (diag_out_c2[38:0]), | |
222 | .din0 (usaloc_diag_rd_ua_out[38:0]), | |
223 | .din1 (vlddir_diag_rd_vd_out[38:0]), | |
224 | .sel0 (arb_acc_ua_c2), | |
225 | .sel1 (arb_acc_ua_c2_n) | |
226 | ); | |
227 | ||
228 | l2t_vuadpm_dp_msff_macro__stack_39c__width_39 ff_diag_out_c3 // VUAD ECC Change | |
229 | ( | |
230 | .scan_in(ff_diag_out_c3_scanin), | |
231 | .scan_out(ff_diag_out_c3_scanout), | |
232 | .dout (diag_out_c3[38:0]), | |
233 | .din (diag_out_c2[38:0]), | |
234 | .clk (l2clk), | |
235 | .en (1'b1), | |
236 | .se(se), | |
237 | .siclk(siclk), | |
238 | .soclk(soclk), | |
239 | .pce_ov(pce_ov), | |
240 | .stop(stop) | |
241 | ) ; | |
242 | ||
243 | ||
244 | l2t_vuadpm_dp_msff_macro__stack_38c__width_37 ff_mbist_write_data | |
245 | ( | |
246 | .scan_in(ff_mbist_write_data_scanin), | |
247 | .scan_out(ff_mbist_write_data_scanout), | |
248 | .dout ({mbist_write_data_px2[7:0],bist_vuad_rd_en_px2, | |
249 | mbist_write_data_r1[7:0],bist_vuad_rd_en_r1, | |
250 | mbist_write_data_r2[7:0],bist_vuad_rd_en_r2, | |
251 | mbist_write_data_r3[7:0],bist_vuad_rd_en_r3,mbist_l2vuad_fail}), | |
252 | .din ({mbist_write_data[7:0],bist_vuad_rd_en_px1, | |
253 | mbist_write_data_px2[7:0],bist_vuad_rd_en_px2, | |
254 | mbist_write_data_r1[7:0],bist_vuad_rd_en_r1, | |
255 | mbist_write_data_r2[7:0],bist_vuad_rd_en_r2,mbist_l2vuad_fail_unreg}), | |
256 | .clk (l2clk), | |
257 | .en (1'b1), | |
258 | .se(se), | |
259 | .siclk(siclk), | |
260 | .soclk(soclk), | |
261 | .pce_ov(pce_ov), | |
262 | .stop(stop) | |
263 | ) ; | |
264 | ||
265 | ||
266 | l2t_vuadpm_dp_cmp_macro__width_32 cmp_mbist_data_cmp0 | |
267 | ( | |
268 | .dout (vuad_fail1), | |
269 | .din0 (diag_out_c3[31:0]), | |
270 | .din1 ({4{mbist_write_data_r3[7:0]}}) | |
271 | ); | |
272 | ||
273 | l2t_vuadpm_dp_cmp_macro__width_8 cmp_mbist_data_cmp1 | |
274 | ( | |
275 | .dout (vuad_fail2), | |
276 | .din0 ({1'b0,diag_out_c3[38:32]}), | |
277 | .din1 ({1'b0,mbist_write_data_r3[6:0]}) | |
278 | ); | |
279 | ||
280 | //assign mbist_l2vuad_fail = vuad_fail1 | vuad_fail2; | |
281 | ||
282 | l2t_vuadpm_dp_and_macro__width_1 and_mbist_l2vuad_fail | |
283 | ( | |
284 | .dout (mbist_l2vuad_fail_raw), | |
285 | .din0 (vuad_fail1), | |
286 | .din1 (vuad_fail2) | |
287 | ); | |
288 | ||
289 | l2t_vuadpm_dp_inv_macro__width_1 inv_bist_vuad_rd_en_r3_n | |
290 | ( | |
291 | .dout (bist_vuad_rd_en_r3_n), | |
292 | .din (bist_vuad_rd_en_r3) | |
293 | ); | |
294 | ||
295 | l2t_vuadpm_dp_mux_macro__mux_aonpe__ports_2__width_1 mux_mbdata_fail_unreg | |
296 | ( | |
297 | .dout (mbist_l2vuad_fail_unreg), | |
298 | .din0 (mbist_l2vuad_fail_raw), | |
299 | .din1 (1'b1), | |
300 | .sel0 (bist_vuad_rd_en_r3), | |
301 | .sel1 (bist_vuad_rd_en_r3_n) | |
302 | ); | |
303 | ||
304 | ||
305 | ||
306 | ||
307 | l2t_vuadpm_dp_msff_macro__dmsff_4x__stack_39c__width_39 ff_diag_out_c4 // VUAD ECC Change | |
308 | ( | |
309 | .scan_in(ff_diag_out_c4_scanin), | |
310 | .scan_out(ff_diag_out_c4_scanout), | |
311 | .dout (diag_out_c4[38:0]), | |
312 | .din (diag_out_c3[38:0]), | |
313 | .clk (l2clk), | |
314 | .en (1'b1), | |
315 | .se(se), | |
316 | .siclk(siclk), | |
317 | .soclk(soclk), | |
318 | .pce_ov(pce_ov), | |
319 | .stop(stop) | |
320 | ) ; | |
321 | ||
322 | l2t_vuadpm_dp_msff_macro__dmsff_4x__stack_39c__width_39 ff_diag_out_c5 // VUAD ECC Change | |
323 | ( | |
324 | .scan_in(ff_diag_out_c5_scanin), | |
325 | .scan_out(ff_diag_out_c5_scanout), | |
326 | .dout (diag_out_c5[38:0]), | |
327 | .din (diag_out_c4[38:0]), | |
328 | .clk (l2clk), | |
329 | .en (1'b1), | |
330 | .se(se), | |
331 | .siclk(siclk), | |
332 | .soclk(soclk), | |
333 | .pce_ov(pce_ov), | |
334 | .stop(stop) | |
335 | ) ; | |
336 | ||
337 | // BS 03/11/04 extra cycle for mem access | |
338 | ||
339 | l2t_vuadpm_dp_msff_macro__dmsff_4x__stack_39c__width_39 ff_diag_out_c52 // VUAD ECC Change | |
340 | ( | |
341 | .scan_in(ff_diag_out_c52_scanin), | |
342 | .scan_out(ff_diag_out_c52_scanout), | |
343 | .dout (diag_out_c52[38:0]), | |
344 | .din (diag_out_c5[38:0]), | |
345 | .clk (l2clk), | |
346 | .en (1'b1), | |
347 | .se(se), | |
348 | .siclk(siclk), | |
349 | .soclk(soclk), | |
350 | .pce_ov(pce_ov), | |
351 | .stop(stop) | |
352 | ) ; | |
353 | ||
354 | ||
355 | l2t_vuadpm_dp_msff_macro__dmsff_4x__stack_39c__width_39 ff_diag_out_c6 // VUAD ECC Change | |
356 | ( | |
357 | .scan_in(ff_diag_out_c6_scanin), | |
358 | .scan_out(ff_diag_out_c6_scanout), | |
359 | .dout (diag_out_c6[38:0]), | |
360 | .din (diag_out_c52[38:0]), | |
361 | .clk (l2clk), | |
362 | .en (1'b1), | |
363 | .se(se), | |
364 | .siclk(siclk), | |
365 | .soclk(soclk), | |
366 | .pce_ov(pce_ov), | |
367 | .stop(stop) | |
368 | ); | |
369 | ||
370 | l2t_vuadpm_dp_msff_macro__dmsff_32x__stack_39c__width_39 ff_diag_out_c7 // VUAD ECC Change | |
371 | ( | |
372 | .scan_in(ff_diag_out_c7_scanin), | |
373 | .scan_out(ff_diag_out_c7_scanout), | |
374 | .dout (diag_out_c7[38:0]), | |
375 | .din (diag_out_c6[38:0]), | |
376 | .clk (l2clk), | |
377 | .en (1'b1), | |
378 | .se(se), | |
379 | .siclk(siclk), | |
380 | .soclk(soclk), | |
381 | .pce_ov(pce_ov), | |
382 | .stop(stop) | |
383 | ) ; | |
384 | ||
385 | //msff_macro ff_diag_out_c8 (width=39,stack=39c,dmsff=4x) // VUAD ECC Change | |
386 | // ( | |
387 | // .scan_in(ff_diag_out_c8_scanin), | |
388 | // .scan_out(ff_diag_out_c8_scanout), | |
389 | // .dout (diag_out_c8[38:0]), | |
390 | // .din (diag_out_c7[38:0]), | |
391 | // .clk (l2clk), | |
392 | // .en (1'b1) | |
393 | // ) ; | |
394 | // | |
395 | // eventhough the suffix says c7 this is actually c8 data | |
396 | // sent to decc. THis data gets muxed with other diagnostic | |
397 | // data and inval data in C8 and is transmitted to the | |
398 | // requesting sparc in the next cycle. | |
399 | ||
400 | assign vuadpm_vuad_diag_data_c7 = diag_out_c7 ; | |
401 | ||
402 | ////////////////////////////// | |
403 | // Use the 4 rightmost dp pitches for this | |
404 | ////////////////////////////// | |
405 | ||
406 | l2t_vuadpm_dp_msff_macro__stack_4c__width_4 ff_ue_fifo | |
407 | ( | |
408 | .scan_in(ff_ue_fifo_scanin), | |
409 | .scan_out(ff_ue_fifo_scanout), | |
410 | .dout ({vd_ue_c3, ua_ue_c3, | |
411 | vd_ue_c4, ua_ue_c4}), | |
412 | .din ({ vlddir_vd_ue_c2,usaloc_ua_ue_c2, | |
413 | vd_ue_c3, ua_ue_c3}), | |
414 | .clk (l2clk), | |
415 | .en (1'b1), | |
416 | .se(se), | |
417 | .siclk(siclk), | |
418 | .soclk(soclk), | |
419 | .pce_ov(pce_ov), | |
420 | .stop(stop) | |
421 | ) ; | |
422 | ||
423 | assign vuadpm_vd_ue_c4 = vd_ue_c4; | |
424 | assign vuadpm_ua_ue_c4 = ua_ue_c4; | |
425 | ||
426 | l2t_vuadpm_dp_msff_macro__stack_56c__width_56 ff_ua_synd_fifo | |
427 | ( | |
428 | .scan_in(ff_ua_synd_fifo_scanin), | |
429 | .scan_out(ff_ua_synd_fifo_scanout), | |
430 | .dout ({ usaloc_ua_synd_c3[6:0], | |
431 | usaloc_ua_synd_c4[6:0], | |
432 | usaloc_ua_synd_c5[6:0], | |
433 | usaloc_ua_synd_c52[6:0], | |
434 | usaloc_ua_synd_c6[6:0], | |
435 | usaloc_ua_synd_c7[6:0], | |
436 | usaloc_ua_synd_c8[6:0], | |
437 | usaloc_ua_synd_c9[6:0]}), | |
438 | .din ({ {usaloc_ua_ce_c2,usaloc_ua_synd_c2[5:0]}, | |
439 | usaloc_ua_synd_c3[6:0], | |
440 | usaloc_ua_synd_c4[6:0], | |
441 | usaloc_ua_synd_c5[6:0], | |
442 | usaloc_ua_synd_c52[6:0], | |
443 | usaloc_ua_synd_c6[6:0], | |
444 | usaloc_ua_synd_c7[6:0], | |
445 | usaloc_ua_synd_c8[6:0]}), | |
446 | .clk (l2clk), | |
447 | .en (1'b1), | |
448 | .se(se), | |
449 | .siclk(siclk), | |
450 | .soclk(soclk), | |
451 | .pce_ov(pce_ov), | |
452 | .stop(stop) | |
453 | ) ; | |
454 | ||
455 | l2t_vuadpm_dp_msff_macro__stack_56c__width_56 ff_vd_synd_fifo | |
456 | ( | |
457 | .scan_in(ff_vd_synd_fifo_scanin), | |
458 | .scan_out(ff_vd_synd_fifo_scanout), | |
459 | .dout ({ vlddir_vd_synd_c3[6:0], | |
460 | vlddir_vd_synd_c4[6:0], | |
461 | vlddir_vd_synd_c5[6:0], | |
462 | vlddir_vd_synd_52[6:0], | |
463 | vlddir_vd_synd_c6[6:0], | |
464 | vlddir_vd_synd_c7[6:0], | |
465 | vlddir_vd_synd_c8[6:0], | |
466 | vlddir_vd_synd_c9[6:0]}), | |
467 | .din ({ {vlddir_vd_ce_c2,vlddir_vd_synd_c2[5:0]}, | |
468 | vlddir_vd_synd_c3[6:0], | |
469 | vlddir_vd_synd_c4[6:0], | |
470 | vlddir_vd_synd_c5[6:0], | |
471 | vlddir_vd_synd_52[6:0], | |
472 | vlddir_vd_synd_c6[6:0], | |
473 | vlddir_vd_synd_c7[6:0], | |
474 | vlddir_vd_synd_c8[6:0]}), | |
475 | .clk (l2clk), | |
476 | .en (1'b1), | |
477 | .se(se), | |
478 | .siclk(siclk), | |
479 | .soclk(soclk), | |
480 | .pce_ov(pce_ov), | |
481 | .stop(stop) | |
482 | ) ; | |
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | // Bist data flops | |
489 | ||
490 | ||
491 | // 34 bits from 8 bits. | |
492 | assign bist_data_c3 = { bist_vuad_data_in[6:0], {4{bist_vuad_data_in[7:0]}}}; | |
493 | ||
494 | ||
495 | //Diagnostic WR data mux | |
496 | l2t_vuadpm_dp_msff_macro__stack_39c__width_39 ff_arbdata_wr_data_c3 // VUAD ECC Change | |
497 | ( | |
498 | .scan_in(ff_arbdata_wr_data_c3_scanin), | |
499 | .scan_out(ff_arbdata_wr_data_c3_scanout), | |
500 | .dout (arbdata_wr_data_c3[38:0]), | |
501 | .din (arbdat_arbdata_wr_data_c2[38:0]), | |
502 | .clk (l2clk), | |
503 | .en (1'b1), | |
504 | .se(se), | |
505 | .siclk(siclk), | |
506 | .soclk(soclk), | |
507 | .pce_ov(pce_ov), | |
508 | .stop(stop) | |
509 | ) ; | |
510 | ||
511 | // Use a 2-1 mux flop for vuadpm_bistordiag_ua_data | |
512 | ||
513 | l2t_vuadpm_dp_inv_macro__width_1 vuaddp_sel_diag1_data_wr_c3_inv_slice ( | |
514 | .dout (vuaddp_sel_diag1_data_wr_c3_n), | |
515 | .din (vuaddp_sel_diag1_data_wr_c3) | |
516 | ); | |
517 | ||
518 | l2t_vuadpm_dp_mux_macro__mux_aonpe__ports_2__stack_39c__width_39 mux_lhs_bistordiag_data | |
519 | ( | |
520 | .dout (bistordiag_ua_data_in[38:0]), | |
521 | .din0 (arbdata_wr_data_c3[38:0]), | |
522 | .din1 (bist_data_c3[38:0]), | |
523 | .sel0 (vuaddp_sel_diag1_data_wr_c3), | |
524 | .sel1 (vuaddp_sel_diag1_data_wr_c3_n) | |
525 | ) ; | |
526 | ||
527 | l2t_vuadpm_dp_msff_macro__stack_39c__width_39 ff_bistordiag_ua_data | |
528 | ( | |
529 | .scan_in(ff_bistordiag_ua_data_scanin), | |
530 | .scan_out(ff_bistordiag_ua_data_scanout), | |
531 | .dout (vuadpm_bistordiag_ua_data[38:0]), | |
532 | .din (bistordiag_ua_data_in[38:0]), | |
533 | .clk (l2clk), | |
534 | .en (1'b1), | |
535 | .se(se), | |
536 | .siclk(siclk), | |
537 | .soclk(soclk), | |
538 | .pce_ov(pce_ov), | |
539 | .stop(stop) | |
540 | ) ; | |
541 | ||
542 | ||
543 | // Use a 2-1 mux flop for vuadpm_bistordiag_vd_data | |
544 | l2t_vuadpm_dp_inv_macro__width_1 vuaddp_sel_diag0_data_wr_c3_inv_slice ( | |
545 | .dout (vuaddp_sel_diag0_data_wr_c3_n), | |
546 | .din (vuaddp_sel_diag0_data_wr_c3) | |
547 | ); | |
548 | ||
549 | ||
550 | ||
551 | l2t_vuadpm_dp_mux_macro__mux_aonpe__ports_2__stack_39c__width_39 mux_rhs_bistordiag_data | |
552 | ( | |
553 | .dout (bistordiag_vd_data_in[38:0]), | |
554 | .din0 (arbdata_wr_data_c3[38:0]), | |
555 | .din1 (bist_data_c3[38:0]), | |
556 | .sel0 (vuaddp_sel_diag0_data_wr_c3), | |
557 | .sel1 (vuaddp_sel_diag0_data_wr_c3_n) | |
558 | ); | |
559 | ||
560 | l2t_vuadpm_dp_msff_macro__stack_39c__width_39 ff_bistordiag_vd_data // VUAD ECC Change | |
561 | ( | |
562 | .scan_in(ff_bistordiag_vd_data_scanin), | |
563 | .scan_out(ff_bistordiag_vd_data_scanout), | |
564 | .dout (vuadpm_bistordiag_vd_data[38:0]), | |
565 | .din (bistordiag_vd_data_in[38:0]), | |
566 | .clk (l2clk), | |
567 | .en (1'b1), | |
568 | .se(se), | |
569 | .siclk(siclk), | |
570 | .soclk(soclk), | |
571 | .pce_ov(pce_ov), | |
572 | .stop(stop) | |
573 | ) ; | |
574 | ||
575 | ||
576 | // fixscan start: | |
577 | assign ff_diag_out_c3_scanin = scan_in ; | |
578 | assign ff_mbist_write_data_scanin = ff_diag_out_c3_scanout ; | |
579 | assign ff_diag_out_c4_scanin = ff_mbist_write_data_scanout; | |
580 | assign ff_diag_out_c5_scanin = ff_diag_out_c4_scanout ; | |
581 | assign ff_diag_out_c52_scanin = ff_diag_out_c5_scanout ; | |
582 | assign ff_diag_out_c6_scanin = ff_diag_out_c52_scanout ; | |
583 | assign ff_diag_out_c7_scanin = ff_diag_out_c6_scanout ; | |
584 | assign ff_ue_fifo_scanin = ff_diag_out_c7_scanout ; | |
585 | assign ff_ua_synd_fifo_scanin = ff_ue_fifo_scanout ; | |
586 | assign ff_vd_synd_fifo_scanin = ff_ua_synd_fifo_scanout ; | |
587 | assign ff_arbdata_wr_data_c3_scanin = ff_vd_synd_fifo_scanout ; | |
588 | assign ff_bistordiag_ua_data_scanin = ff_arbdata_wr_data_c3_scanout; | |
589 | assign ff_bistordiag_vd_data_scanin = ff_bistordiag_ua_data_scanout; | |
590 | assign scan_out = ff_bistordiag_vd_data_scanout; | |
591 | // fixscan end: | |
592 | endmodule | |
593 | ||
594 | ||
595 | ||
596 | // | |
597 | // invert macro | |
598 | // | |
599 | // | |
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | module l2t_vuadpm_dp_inv_macro__width_1 ( | |
606 | din, | |
607 | dout); | |
608 | input [0:0] din; | |
609 | output [0:0] dout; | |
610 | ||
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | inv #(1) d0_0 ( | |
617 | .in(din[0:0]), | |
618 | .out(dout[0:0]) | |
619 | ); | |
620 | ||
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | endmodule | |
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
636 | // also for pass-gate with decoder | |
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | // any PARAMS parms go into naming of macro | |
643 | ||
644 | module l2t_vuadpm_dp_mux_macro__mux_aonpe__ports_2__stack_39c__width_39 ( | |
645 | din0, | |
646 | sel0, | |
647 | din1, | |
648 | sel1, | |
649 | dout); | |
650 | wire buffout0; | |
651 | wire buffout1; | |
652 | ||
653 | input [38:0] din0; | |
654 | input sel0; | |
655 | input [38:0] din1; | |
656 | input sel1; | |
657 | output [38:0] dout; | |
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | cl_dp1_muxbuff2_8x c0_0 ( | |
664 | .in0(sel0), | |
665 | .in1(sel1), | |
666 | .out0(buffout0), | |
667 | .out1(buffout1) | |
668 | ); | |
669 | mux2s #(39) d0_0 ( | |
670 | .sel0(buffout0), | |
671 | .sel1(buffout1), | |
672 | .in0(din0[38:0]), | |
673 | .in1(din1[38:0]), | |
674 | .dout(dout[38:0]) | |
675 | ); | |
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | ||
689 | endmodule | |
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | // any PARAMS parms go into naming of macro | |
697 | ||
698 | module l2t_vuadpm_dp_msff_macro__stack_39c__width_39 ( | |
699 | din, | |
700 | clk, | |
701 | en, | |
702 | se, | |
703 | scan_in, | |
704 | siclk, | |
705 | soclk, | |
706 | pce_ov, | |
707 | stop, | |
708 | dout, | |
709 | scan_out); | |
710 | wire l1clk; | |
711 | wire siclk_out; | |
712 | wire soclk_out; | |
713 | wire [37:0] so; | |
714 | ||
715 | input [38:0] din; | |
716 | ||
717 | ||
718 | input clk; | |
719 | input en; | |
720 | input se; | |
721 | input scan_in; | |
722 | input siclk; | |
723 | input soclk; | |
724 | input pce_ov; | |
725 | input stop; | |
726 | ||
727 | ||
728 | ||
729 | output [38:0] dout; | |
730 | ||
731 | ||
732 | output scan_out; | |
733 | ||
734 | ||
735 | ||
736 | ||
737 | cl_dp1_l1hdr_8x c0_0 ( | |
738 | .l2clk(clk), | |
739 | .pce(en), | |
740 | .aclk(siclk), | |
741 | .bclk(soclk), | |
742 | .l1clk(l1clk), | |
743 | .se(se), | |
744 | .pce_ov(pce_ov), | |
745 | .stop(stop), | |
746 | .siclk_out(siclk_out), | |
747 | .soclk_out(soclk_out) | |
748 | ); | |
749 | dff #(39) d0_0 ( | |
750 | .l1clk(l1clk), | |
751 | .siclk(siclk_out), | |
752 | .soclk(soclk_out), | |
753 | .d(din[38:0]), | |
754 | .si({scan_in,so[37:0]}), | |
755 | .so({so[37:0],scan_out}), | |
756 | .q(dout[38:0]) | |
757 | ); | |
758 | ||
759 | ||
760 | ||
761 | ||
762 | ||
763 | ||
764 | ||
765 | ||
766 | ||
767 | ||
768 | ||
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | endmodule | |
779 | ||
780 | ||
781 | ||
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 | ||
788 | ||
789 | ||
790 | ||
791 | ||
792 | // any PARAMS parms go into naming of macro | |
793 | ||
794 | module l2t_vuadpm_dp_msff_macro__stack_38c__width_37 ( | |
795 | din, | |
796 | clk, | |
797 | en, | |
798 | se, | |
799 | scan_in, | |
800 | siclk, | |
801 | soclk, | |
802 | pce_ov, | |
803 | stop, | |
804 | dout, | |
805 | scan_out); | |
806 | wire l1clk; | |
807 | wire siclk_out; | |
808 | wire soclk_out; | |
809 | wire [35:0] so; | |
810 | ||
811 | input [36:0] din; | |
812 | ||
813 | ||
814 | input clk; | |
815 | input en; | |
816 | input se; | |
817 | input scan_in; | |
818 | input siclk; | |
819 | input soclk; | |
820 | input pce_ov; | |
821 | input stop; | |
822 | ||
823 | ||
824 | ||
825 | output [36:0] dout; | |
826 | ||
827 | ||
828 | output scan_out; | |
829 | ||
830 | ||
831 | ||
832 | ||
833 | cl_dp1_l1hdr_8x c0_0 ( | |
834 | .l2clk(clk), | |
835 | .pce(en), | |
836 | .aclk(siclk), | |
837 | .bclk(soclk), | |
838 | .l1clk(l1clk), | |
839 | .se(se), | |
840 | .pce_ov(pce_ov), | |
841 | .stop(stop), | |
842 | .siclk_out(siclk_out), | |
843 | .soclk_out(soclk_out) | |
844 | ); | |
845 | dff #(37) d0_0 ( | |
846 | .l1clk(l1clk), | |
847 | .siclk(siclk_out), | |
848 | .soclk(soclk_out), | |
849 | .d(din[36:0]), | |
850 | .si({scan_in,so[35:0]}), | |
851 | .so({so[35:0],scan_out}), | |
852 | .q(dout[36:0]) | |
853 | ); | |
854 | ||
855 | ||
856 | ||
857 | ||
858 | ||
859 | ||
860 | ||
861 | ||
862 | ||
863 | ||
864 | ||
865 | ||
866 | ||
867 | ||
868 | ||
869 | ||
870 | ||
871 | ||
872 | ||
873 | ||
874 | endmodule | |
875 | ||
876 | ||
877 | ||
878 | ||
879 | ||
880 | ||
881 | ||
882 | ||
883 | ||
884 | // | |
885 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
886 | // | |
887 | // | |
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | module l2t_vuadpm_dp_cmp_macro__width_32 ( | |
894 | din0, | |
895 | din1, | |
896 | dout); | |
897 | input [31:0] din0; | |
898 | input [31:0] din1; | |
899 | output dout; | |
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | ||
906 | cmp #(32) m0_0 ( | |
907 | .in0(din0[31:0]), | |
908 | .in1(din1[31:0]), | |
909 | .out(dout) | |
910 | ); | |
911 | ||
912 | ||
913 | ||
914 | ||
915 | ||
916 | ||
917 | ||
918 | ||
919 | ||
920 | ||
921 | endmodule | |
922 | ||
923 | ||
924 | ||
925 | ||
926 | ||
927 | // | |
928 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
929 | // | |
930 | // | |
931 | ||
932 | ||
933 | ||
934 | ||
935 | ||
936 | module l2t_vuadpm_dp_cmp_macro__width_8 ( | |
937 | din0, | |
938 | din1, | |
939 | dout); | |
940 | input [7:0] din0; | |
941 | input [7:0] din1; | |
942 | output dout; | |
943 | ||
944 | ||
945 | ||
946 | ||
947 | ||
948 | ||
949 | cmp #(8) m0_0 ( | |
950 | .in0(din0[7:0]), | |
951 | .in1(din1[7:0]), | |
952 | .out(dout) | |
953 | ); | |
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | ||
960 | ||
961 | ||
962 | ||
963 | ||
964 | endmodule | |
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | // | |
971 | // and macro for ports = 2,3,4 | |
972 | // | |
973 | // | |
974 | ||
975 | ||
976 | ||
977 | ||
978 | ||
979 | module l2t_vuadpm_dp_and_macro__width_1 ( | |
980 | din0, | |
981 | din1, | |
982 | dout); | |
983 | input [0:0] din0; | |
984 | input [0:0] din1; | |
985 | output [0:0] dout; | |
986 | ||
987 | ||
988 | ||
989 | ||
990 | ||
991 | ||
992 | and2 #(1) d0_0 ( | |
993 | .in0(din0[0:0]), | |
994 | .in1(din1[0:0]), | |
995 | .out(dout[0:0]) | |
996 | ); | |
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | endmodule | |
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1013 | // also for pass-gate with decoder | |
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | // any PARAMS parms go into naming of macro | |
1020 | ||
1021 | module l2t_vuadpm_dp_mux_macro__mux_aonpe__ports_2__width_1 ( | |
1022 | din0, | |
1023 | sel0, | |
1024 | din1, | |
1025 | sel1, | |
1026 | dout); | |
1027 | wire buffout0; | |
1028 | wire buffout1; | |
1029 | ||
1030 | input [0:0] din0; | |
1031 | input sel0; | |
1032 | input [0:0] din1; | |
1033 | input sel1; | |
1034 | output [0:0] dout; | |
1035 | ||
1036 | ||
1037 | ||
1038 | ||
1039 | ||
1040 | cl_dp1_muxbuff2_8x c0_0 ( | |
1041 | .in0(sel0), | |
1042 | .in1(sel1), | |
1043 | .out0(buffout0), | |
1044 | .out1(buffout1) | |
1045 | ); | |
1046 | mux2s #(1) d0_0 ( | |
1047 | .sel0(buffout0), | |
1048 | .sel1(buffout1), | |
1049 | .in0(din0[0:0]), | |
1050 | .in1(din1[0:0]), | |
1051 | .dout(dout[0:0]) | |
1052 | ); | |
1053 | ||
1054 | ||
1055 | ||
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | ||
1061 | ||
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | endmodule | |
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | // any PARAMS parms go into naming of macro | |
1074 | ||
1075 | module l2t_vuadpm_dp_msff_macro__dmsff_4x__stack_39c__width_39 ( | |
1076 | din, | |
1077 | clk, | |
1078 | en, | |
1079 | se, | |
1080 | scan_in, | |
1081 | siclk, | |
1082 | soclk, | |
1083 | pce_ov, | |
1084 | stop, | |
1085 | dout, | |
1086 | scan_out); | |
1087 | wire l1clk; | |
1088 | wire siclk_out; | |
1089 | wire soclk_out; | |
1090 | wire [37:0] so; | |
1091 | ||
1092 | input [38:0] din; | |
1093 | ||
1094 | ||
1095 | input clk; | |
1096 | input en; | |
1097 | input se; | |
1098 | input scan_in; | |
1099 | input siclk; | |
1100 | input soclk; | |
1101 | input pce_ov; | |
1102 | input stop; | |
1103 | ||
1104 | ||
1105 | ||
1106 | output [38:0] dout; | |
1107 | ||
1108 | ||
1109 | output scan_out; | |
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | cl_dp1_l1hdr_8x c0_0 ( | |
1115 | .l2clk(clk), | |
1116 | .pce(en), | |
1117 | .aclk(siclk), | |
1118 | .bclk(soclk), | |
1119 | .l1clk(l1clk), | |
1120 | .se(se), | |
1121 | .pce_ov(pce_ov), | |
1122 | .stop(stop), | |
1123 | .siclk_out(siclk_out), | |
1124 | .soclk_out(soclk_out) | |
1125 | ); | |
1126 | dff #(39) d0_0 ( | |
1127 | .l1clk(l1clk), | |
1128 | .siclk(siclk_out), | |
1129 | .soclk(soclk_out), | |
1130 | .d(din[38:0]), | |
1131 | .si({scan_in,so[37:0]}), | |
1132 | .so({so[37:0],scan_out}), | |
1133 | .q(dout[38:0]) | |
1134 | ); | |
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | ||
1141 | ||
1142 | ||
1143 | ||
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | endmodule | |
1156 | ||
1157 | ||
1158 | ||
1159 | ||
1160 | ||
1161 | ||
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | // any PARAMS parms go into naming of macro | |
1170 | ||
1171 | module l2t_vuadpm_dp_msff_macro__dmsff_32x__stack_39c__width_39 ( | |
1172 | din, | |
1173 | clk, | |
1174 | en, | |
1175 | se, | |
1176 | scan_in, | |
1177 | siclk, | |
1178 | soclk, | |
1179 | pce_ov, | |
1180 | stop, | |
1181 | dout, | |
1182 | scan_out); | |
1183 | wire l1clk; | |
1184 | wire siclk_out; | |
1185 | wire soclk_out; | |
1186 | wire [37:0] so; | |
1187 | ||
1188 | input [38:0] din; | |
1189 | ||
1190 | ||
1191 | input clk; | |
1192 | input en; | |
1193 | input se; | |
1194 | input scan_in; | |
1195 | input siclk; | |
1196 | input soclk; | |
1197 | input pce_ov; | |
1198 | input stop; | |
1199 | ||
1200 | ||
1201 | ||
1202 | output [38:0] dout; | |
1203 | ||
1204 | ||
1205 | output scan_out; | |
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | cl_dp1_l1hdr_8x c0_0 ( | |
1211 | .l2clk(clk), | |
1212 | .pce(en), | |
1213 | .aclk(siclk), | |
1214 | .bclk(soclk), | |
1215 | .l1clk(l1clk), | |
1216 | .se(se), | |
1217 | .pce_ov(pce_ov), | |
1218 | .stop(stop), | |
1219 | .siclk_out(siclk_out), | |
1220 | .soclk_out(soclk_out) | |
1221 | ); | |
1222 | dff #(39) d0_0 ( | |
1223 | .l1clk(l1clk), | |
1224 | .siclk(siclk_out), | |
1225 | .soclk(soclk_out), | |
1226 | .d(din[38:0]), | |
1227 | .si({scan_in,so[37:0]}), | |
1228 | .so({so[37:0],scan_out}), | |
1229 | .q(dout[38:0]) | |
1230 | ); | |
1231 | ||
1232 | ||
1233 | ||
1234 | ||
1235 | ||
1236 | ||
1237 | ||
1238 | ||
1239 | ||
1240 | ||
1241 | ||
1242 | ||
1243 | ||
1244 | ||
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | ||
1250 | ||
1251 | endmodule | |
1252 | ||
1253 | ||
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | // any PARAMS parms go into naming of macro | |
1266 | ||
1267 | module l2t_vuadpm_dp_msff_macro__stack_4c__width_4 ( | |
1268 | din, | |
1269 | clk, | |
1270 | en, | |
1271 | se, | |
1272 | scan_in, | |
1273 | siclk, | |
1274 | soclk, | |
1275 | pce_ov, | |
1276 | stop, | |
1277 | dout, | |
1278 | scan_out); | |
1279 | wire l1clk; | |
1280 | wire siclk_out; | |
1281 | wire soclk_out; | |
1282 | wire [2:0] so; | |
1283 | ||
1284 | input [3:0] din; | |
1285 | ||
1286 | ||
1287 | input clk; | |
1288 | input en; | |
1289 | input se; | |
1290 | input scan_in; | |
1291 | input siclk; | |
1292 | input soclk; | |
1293 | input pce_ov; | |
1294 | input stop; | |
1295 | ||
1296 | ||
1297 | ||
1298 | output [3:0] dout; | |
1299 | ||
1300 | ||
1301 | output scan_out; | |
1302 | ||
1303 | ||
1304 | ||
1305 | ||
1306 | cl_dp1_l1hdr_8x c0_0 ( | |
1307 | .l2clk(clk), | |
1308 | .pce(en), | |
1309 | .aclk(siclk), | |
1310 | .bclk(soclk), | |
1311 | .l1clk(l1clk), | |
1312 | .se(se), | |
1313 | .pce_ov(pce_ov), | |
1314 | .stop(stop), | |
1315 | .siclk_out(siclk_out), | |
1316 | .soclk_out(soclk_out) | |
1317 | ); | |
1318 | dff #(4) d0_0 ( | |
1319 | .l1clk(l1clk), | |
1320 | .siclk(siclk_out), | |
1321 | .soclk(soclk_out), | |
1322 | .d(din[3:0]), | |
1323 | .si({scan_in,so[2:0]}), | |
1324 | .so({so[2:0],scan_out}), | |
1325 | .q(dout[3:0]) | |
1326 | ); | |
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | endmodule | |
1348 | ||
1349 | ||
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | // any PARAMS parms go into naming of macro | |
1362 | ||
1363 | module l2t_vuadpm_dp_msff_macro__stack_56c__width_56 ( | |
1364 | din, | |
1365 | clk, | |
1366 | en, | |
1367 | se, | |
1368 | scan_in, | |
1369 | siclk, | |
1370 | soclk, | |
1371 | pce_ov, | |
1372 | stop, | |
1373 | dout, | |
1374 | scan_out); | |
1375 | wire l1clk; | |
1376 | wire siclk_out; | |
1377 | wire soclk_out; | |
1378 | wire [54:0] so; | |
1379 | ||
1380 | input [55:0] din; | |
1381 | ||
1382 | ||
1383 | input clk; | |
1384 | input en; | |
1385 | input se; | |
1386 | input scan_in; | |
1387 | input siclk; | |
1388 | input soclk; | |
1389 | input pce_ov; | |
1390 | input stop; | |
1391 | ||
1392 | ||
1393 | ||
1394 | output [55:0] dout; | |
1395 | ||
1396 | ||
1397 | output scan_out; | |
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | cl_dp1_l1hdr_8x c0_0 ( | |
1403 | .l2clk(clk), | |
1404 | .pce(en), | |
1405 | .aclk(siclk), | |
1406 | .bclk(soclk), | |
1407 | .l1clk(l1clk), | |
1408 | .se(se), | |
1409 | .pce_ov(pce_ov), | |
1410 | .stop(stop), | |
1411 | .siclk_out(siclk_out), | |
1412 | .soclk_out(soclk_out) | |
1413 | ); | |
1414 | dff #(56) d0_0 ( | |
1415 | .l1clk(l1clk), | |
1416 | .siclk(siclk_out), | |
1417 | .soclk(soclk_out), | |
1418 | .d(din[55:0]), | |
1419 | .si({scan_in,so[54:0]}), | |
1420 | .so({so[54:0],scan_out}), | |
1421 | .q(dout[55:0]) | |
1422 | ); | |
1423 | ||
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | ||
1435 | ||
1436 | ||
1437 | ||
1438 | ||
1439 | ||
1440 | ||
1441 | ||
1442 | ||
1443 | endmodule | |
1444 | ||
1445 | ||
1446 | ||
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 |