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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / mac / rtl / mac.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mac.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35// ##########################################################
36// # File Name : mac.v
37// # Author Name : John Lo
38// # Description :
39// #
40// #
41// # Parent Module:
42// # Child Module:
43// # Interface Mod:
44// # Date Created : 5/5/05
45// #
46// # Copyright (c) 2020, Sun Microsystems, Inc.
47// # Sun Proprietary and Confidential
48// ##########################################################
49
50// VPERL: PERL_BEG
51//
52// $VPERL_PORT_COMM = 1;
53// $VPERL_INST_COMM = 2;
54//
55// &MODULE ("mac");
56// &DECLARE ("wire", "aclk");
57// &DECLARE ("wire", "bclk");
58// &DECLARE ("wire", "pce_ov");
59// &DECLARE ("wire", "tcu_clk_stop");
60// # declare outputs
61// &DECLARE ("output", "mdclk");
62// #
63// &INSTANCE ("/vobs/neptune/design/niu/mac/rtl/mac_core.v", "mac_core");
64// &INSTANCE ("/vobs/neptune/design/niu/mac/rtl/hedwig.v", "hedwig");
65// &INSTANCE ("/vobs/neptune/design/niu/mac/rtl/clkgen_mac.v", "clkgen_mac");
66// &INSTANCE ("/vobs/neptune/design/niu/mac/rtl/esr_bscan.v", "esr_bscan");
67
68// &CONNECT ("mac_core.tcu_mac_125rx_clk_stop", "tcu_clk_stop");
69// &CONNECT ("mac_core.tcu_mac_125tx_clk_stop", "tcu_clk_stop");
70// &CONNECT ("mac_core.tcu_mac_156rx_clk_stop", "tcu_clk_stop");
71// &CONNECT ("mac_core.tcu_mac_156tx_clk_stop", "tcu_clk_stop");
72// &CONNECT ("mac_core.tcu_mac_312rx_clk_stop", "tcu_clk_stop");
73// &CONNECT ("mac_core.tcu_mac_312tx_clk_stop", "tcu_clk_stop");
74// &CONNECT ("hedwig.gl_mac_io_clk_stop", "tcu_clk_stop");
75
76// &ENDMODULE;
77
78// VPERL: PERL_END
79// VPERL: GENERATED_BEG
80
81module mac (
82 mdclk, // output (mac_core) => (hedwig)
83 cluster_arst_l, // input (clkgen_mac) <= ()
84 cmp_gclk_c1_mac, // input (clkgen_mac) <= ()
85 esr_mac_rclk_0, // input (hedwig,mac_core) <= ()
86 esr_mac_rclk_1, // input (hedwig,mac_core) <= ()
87 esr_mac_rxd0_0, // input (mac_core) <= ()
88 esr_mac_rxd0_1, // input (mac_core) <= ()
89 esr_mac_rxd1_0, // input (mac_core) <= ()
90 esr_mac_rxd1_1, // input (mac_core) <= ()
91 esr_mac_rxd2_0, // input (mac_core) <= ()
92 esr_mac_rxd2_1, // input (mac_core) <= ()
93 esr_mac_rxd3_0, // input (mac_core) <= ()
94 esr_mac_rxd3_1, // input (mac_core) <= ()
95 esr_mac_tclk_0, // input (hedwig,mac_core) <= ()
96 esr_mac_tclk_1, // input (hedwig,mac_core) <= ()
97 gl_mac_, // input (clkgen_mac) <= ()
98 gl_mac_io_clk_stop, // input (clkgen_mac) <= ()
99 gl_mac_io_out, // input (clkgen_mac) <= ()
100 mac_125rx_test_clk, // input (hedwig,mac_core) <= ()
101 mac_125tx_test_clk, // input (mac_core) <= ()
102 mac_156rx_test_clk, // input (mac_core) <= ()
103 mac_156tx_test_clk, // input (mac_core) <= ()
104 mac_312rx_test_clk, // input (mac_core) <= ()
105 mac_312tx_test_clk, // input (mac_core) <= ()
106 mac_reset0, // input (mac_core) <= ()
107 mac_reset1, // input (mac_core) <= ()
108 mdi, // input (mac_core) <= ()
109 peu_mac_sbs_input, // input (esr_bscan) <= ()
110 pio_clients_addr, // input (mac_core) <= ()
111 pio_clients_rd, // input (mac_core) <= ()
112 pio_clients_wdata, // input (mac_core) <= ()
113 pio_mac_sel, // input (mac_core) <= ()
114 rxc_mac_req0, // input (mac_core) <= ()
115 rxc_mac_req1, // input (mac_core) <= ()
116 scan_in, // input (clkgen_mac) <= ()
117 stspll_0, // input (hedwig) <= ()
118 stspll_1, // input (hedwig) <= ()
119 stsrx0_0, // input (hedwig) <= ()
120 stsrx0_1, // input (hedwig) <= ()
121 stsrx1_0, // input (hedwig) <= ()
122 stsrx1_1, // input (hedwig) <= ()
123 stsrx2_0, // input (hedwig) <= ()
124 stsrx2_1, // input (hedwig) <= ()
125 stsrx3_0, // input (hedwig) <= ()
126 stsrx3_1, // input (hedwig) <= ()
127 ststx0_0, // input (hedwig) <= ()
128 ststx0_1, // input (hedwig) <= ()
129 ststx1_0, // input (hedwig) <= ()
130 ststx1_1, // input (hedwig) <= ()
131 ststx2_0, // input (hedwig) <= ()
132 ststx2_1, // input (hedwig) <= ()
133 ststx3_0, // input (hedwig) <= ()
134 ststx3_1, // input (hedwig) <= ()
135 tcu_aclk, // input (clkgen_mac) <= ()
136 tcu_atpg_mode, // input (clkgen_mac) <= ()
137 tcu_bclk, // input (clkgen_mac) <= ()
138 tcu_div_bypass, // input (clkgen_mac) <= ()
139 tcu_pce_ov, // input (clkgen_mac) <= ()
140 tcu_sbs_aclk, // input (esr_bscan) <= ()
141 tcu_sbs_acmode, // input (esr_bscan) <= ()
142 tcu_sbs_actestsignal, // input (esr_bscan) <= ()
143 tcu_sbs_bclk, // input (esr_bscan) <= ()
144 tcu_sbs_clk, // input (esr_bscan) <= ()
145 tcu_sbs_enbspt, // input (hedwig) <= ()
146 tcu_sbs_enbsrx, // input (hedwig) <= ()
147 tcu_sbs_enbstx, // input (hedwig) <= ()
148 tcu_sbs_scan_en, // input (esr_bscan) <= ()
149 tcu_sbs_uclk, // input (esr_bscan) <= ()
150 tcu_scan_en, // input (clkgen_mac,hedwig,mac_core) <= ()
151 tcu_scan_mode, // input (clkgen_mac,hedwig,mac_core) <= ()
152 tcu_wr_inhibit, // input (clkgen_mac) <= ()
153 txc_mac_abort0, // input (mac_core) <= ()
154 txc_mac_abort1, // input (mac_core) <= ()
155 txc_mac_ack0, // input (mac_core) <= ()
156 txc_mac_ack1, // input (mac_core) <= ()
157 txc_mac_data0, // input (mac_core) <= ()
158 txc_mac_data1, // input (mac_core) <= ()
159 txc_mac_stat0, // input (mac_core) <= ()
160 txc_mac_stat1, // input (mac_core) <= ()
161 txc_mac_tag0, // input (mac_core) <= ()
162 txc_mac_tag1, // input (mac_core) <= ()
163 xaui_mdint0_l, // input (mac_core) <= ()
164 xaui_mdint1_l, // input (mac_core) <= ()
165 cfgpll_0, // output (hedwig) => ()
166 cfgpll_1, // output (hedwig) => ()
167 cfgrx0_0, // output (hedwig) => ()
168 cfgrx0_1, // output (hedwig) => ()
169 cfgrx1_0, // output (hedwig) => ()
170 cfgrx1_1, // output (hedwig) => ()
171 cfgrx2_0, // output (hedwig) => ()
172 cfgrx2_1, // output (hedwig) => ()
173 cfgrx3_0, // output (hedwig) => ()
174 cfgrx3_1, // output (hedwig) => ()
175 cfgtx0_0, // output (hedwig) => ()
176 cfgtx0_1, // output (hedwig) => ()
177 cfgtx1_0, // output (hedwig) => ()
178 cfgtx1_1, // output (hedwig) => ()
179 cfgtx2_0, // output (hedwig) => ()
180 cfgtx2_1, // output (hedwig) => ()
181 cfgtx3_0, // output (hedwig) => ()
182 cfgtx3_1, // output (hedwig) => ()
183 mac_debug_port, // output (mac_core) => ()
184 mac_esr_tclk_0, // output (mac_core) => ()
185 mac_esr_tclk_1, // output (mac_core) => ()
186 mac_esr_txd0_0, // output (mac_core) => ()
187 mac_esr_txd0_1, // output (mac_core) => ()
188 mac_esr_txd1_0, // output (mac_core) => ()
189 mac_esr_txd1_1, // output (mac_core) => ()
190 mac_esr_txd2_0, // output (mac_core) => ()
191 mac_esr_txd2_1, // output (mac_core) => ()
192 mac_esr_txd3_0, // output (mac_core) => ()
193 mac_esr_txd3_1, // output (mac_core) => ()
194 mac_mcu_3_sbs_output, // output (esr_bscan) => ()
195 mac_pio_ack, // output (mac_core) => ()
196 mac_pio_err, // output (mac_core) => ()
197 mac_pio_intr0, // output (mac_core) => ()
198 mac_pio_intr1, // output (mac_core) => ()
199 mac_pio_rdata, // output (mac_core) => ()
200 mac_rxc_ack0, // output (mac_core) => ()
201 mac_rxc_ack1, // output (mac_core) => ()
202 mac_rxc_ctrl0, // output (mac_core) => ()
203 mac_rxc_ctrl1, // output (mac_core) => ()
204 mac_rxc_data0, // output (mac_core) => ()
205 mac_rxc_data1, // output (mac_core) => ()
206 mac_rxc_stat0, // output (mac_core) => ()
207 mac_rxc_stat1, // output (mac_core) => ()
208 mac_rxc_tag0, // output (mac_core) => ()
209 mac_rxc_tag1, // output (mac_core) => ()
210 mac_txc_req0, // output (mac_core) => ()
211 mac_txc_req1, // output (mac_core) => ()
212 mdoe, // output (mac_core) => ()
213 mif_pio_intr, // output (mac_core) => ()
214 scan_out, // output (clkgen_mac) => ()
215 testcfg_0, // output (hedwig) => ()
216 testcfg_1, // output (hedwig) => ()
217 xaui_act_led_0, // output (mac_core) => ()
218 xaui_act_led_1, // output (mac_core) => ()
219 xaui_link_led_0, // output (mac_core) => ()
220 xaui_link_led_1 // output (mac_core) => ()
221 );
222
223input cluster_arst_l;
224input cmp_gclk_c1_mac; // global clk - this is either cmp or dr
225input [3:0] esr_mac_rclk_0; // To phy_clock_2ports of phy_clock_2ports.v
226input [3:0] esr_mac_rclk_1; // To phy_clock_2ports of phy_clock_2ports.v
227input [9:0] esr_mac_rxd0_0; // To mac_2ports of mac_2ports.v
228input [9:0] esr_mac_rxd0_1; // To mac_2ports of mac_2ports.v
229input [9:0] esr_mac_rxd1_0; // To mac_2ports of mac_2ports.v
230input [9:0] esr_mac_rxd1_1; // To mac_2ports of mac_2ports.v
231input [9:0] esr_mac_rxd2_0; // To mac_2ports of mac_2ports.v
232input [9:0] esr_mac_rxd2_1; // To mac_2ports of mac_2ports.v
233input [9:0] esr_mac_rxd3_0; // To mac_2ports of mac_2ports.v
234input [9:0] esr_mac_rxd3_1; // To mac_2ports of mac_2ports.v
235input esr_mac_tclk_0; // To phy_clock_2ports of phy_clock_2ports.v
236input esr_mac_tclk_1; // To phy_clock_2ports of phy_clock_2ports.v
237input gl_mac_;
238input gl_mac_io_clk_stop;
239input gl_mac_io_out; // phase signal from ccu (div/4 or div/2)
240input mac_125rx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v
241input mac_125tx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v
242input mac_156rx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v
243input mac_156tx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v
244input mac_312rx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v
245input mac_312tx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v
246input mac_reset0; // To mac_2ports of mac_2ports.v
247input mac_reset1; // To mac_2ports of mac_2ports.v
248input mdi; // To mac_2ports of mac_2ports.v
249input peu_mac_sbs_input;
250input [19:0] pio_clients_addr; // To mac_2ports of mac_2ports.v
251input pio_clients_rd; // To mac_2ports of mac_2ports.v
252input [31:0] pio_clients_wdata; // To mac_2ports of mac_2ports.v
253input pio_mac_sel; // To mac_2ports of mac_2ports.v
254input rxc_mac_req0; // To mac_2ports of mac_2ports.v
255input rxc_mac_req1; // To mac_2ports of mac_2ports.v
256input scan_in;
257input [3:0] stspll_0; // from malfoy
258input [3:0] stspll_1; // from malfoy
259input [7:0] stsrx0_0; // from malfoy
260input [7:0] stsrx0_1; // from malfoy
261input [7:0] stsrx1_0; // from malfoy
262input [7:0] stsrx1_1; // from malfoy
263input [7:0] stsrx2_0; // from malfoy
264input [7:0] stsrx2_1; // from malfoy
265input [7:0] stsrx3_0; // from malfoy
266input [7:0] stsrx3_1; // from malfoy
267input [3:0] ststx0_0; // from malfoy
268input [3:0] ststx0_1; // from malfoy
269input [3:0] ststx1_0; // from malfoy
270input [3:0] ststx1_1; // from malfoy
271input [3:0] ststx2_0; // from malfoy
272input [3:0] ststx2_1; // from malfoy
273input [3:0] ststx3_0; // from malfoy
274input [3:0] ststx3_1; // from malfoy
275input tcu_aclk;
276input tcu_atpg_mode;
277input tcu_bclk;
278input tcu_div_bypass; // bypasses clk divider to mux in ext clk
279input tcu_pce_ov;
280input tcu_sbs_aclk; // from tcu
281input tcu_sbs_acmode; // from tcu
282input tcu_sbs_actestsignal; // from tcu
283input tcu_sbs_bclk; // from tcu
284input tcu_sbs_clk; // from tcu
285input tcu_sbs_enbspt;
286input tcu_sbs_enbsrx; // from tcu
287input tcu_sbs_enbstx; // from tcu
288input tcu_sbs_scan_en; // from tcu
289input tcu_sbs_uclk; // from tcu
290input tcu_scan_en; // To mac_2ports of mac_2ports.v
291input tcu_scan_mode; // To mac_2ports of mac_2ports.v, ...
292input tcu_wr_inhibit;
293input txc_mac_abort0; // To mac_2ports of mac_2ports.v
294input txc_mac_abort1; // To mac_2ports of mac_2ports.v
295input txc_mac_ack0; // To mac_2ports of mac_2ports.v
296input txc_mac_ack1; // To mac_2ports of mac_2ports.v
297input [63:0] txc_mac_data0; // To mac_2ports of mac_2ports.v
298input [63:0] txc_mac_data1; // To mac_2ports of mac_2ports.v
299input [3:0] txc_mac_stat0; // To mac_2ports of mac_2ports.v
300input [3:0] txc_mac_stat1; // To mac_2ports of mac_2ports.v
301input txc_mac_tag0; // To mac_2ports of mac_2ports.v
302input txc_mac_tag1; // To mac_2ports of mac_2ports.v
303input xaui_mdint0_l; // To mac_2ports of mac_2ports.v
304input xaui_mdint1_l; // To mac_2ports of mac_2ports.v
305output [11:0] cfgpll_0; // to malfoy
306output [11:0] cfgpll_1; // to malfoy
307output [27:0] cfgrx0_0; // to malfoy
308output [27:0] cfgrx0_1; // to malfoy
309output [27:0] cfgrx1_0; // to malfoy
310output [27:0] cfgrx1_1; // to malfoy
311output [27:0] cfgrx2_0; // to malfoy
312output [27:0] cfgrx2_1; // to malfoy
313output [27:0] cfgrx3_0; // to malfoy
314output [27:0] cfgrx3_1; // to malfoy
315output [19:0] cfgtx0_0; // to malfoy
316output [19:0] cfgtx0_1; // to malfoy
317output [19:0] cfgtx1_0; // to malfoy
318output [19:0] cfgtx1_1; // to malfoy
319output [19:0] cfgtx2_0; // to malfoy
320output [19:0] cfgtx2_1; // to malfoy
321output [19:0] cfgtx3_0; // to malfoy
322output [19:0] cfgtx3_1; // to malfoy
323output [31:0] mac_debug_port; // From mac_2ports of mac_2ports.v
324output [3:0] mac_esr_tclk_0; // From mac_2ports of mac_2ports.v
325output [3:0] mac_esr_tclk_1; // From mac_2ports of mac_2ports.v
326output [9:0] mac_esr_txd0_0; // From mac_2ports of mac_2ports.v
327output [9:0] mac_esr_txd0_1; // From mac_2ports of mac_2ports.v
328output [9:0] mac_esr_txd1_0; // From mac_2ports of mac_2ports.v
329output [9:0] mac_esr_txd1_1; // From mac_2ports of mac_2ports.v
330output [9:0] mac_esr_txd2_0; // From mac_2ports of mac_2ports.v
331output [9:0] mac_esr_txd2_1; // From mac_2ports of mac_2ports.v
332output [9:0] mac_esr_txd3_0; // From mac_2ports of mac_2ports.v
333output [9:0] mac_esr_txd3_1; // From mac_2ports of mac_2ports.v
334output mac_mcu_3_sbs_output;
335output mac_pio_ack; // From mac_2ports of mac_2ports.v
336output mac_pio_err; // From mac_2ports of mac_2ports.v
337output mac_pio_intr0; // From mac_2ports of mac_2ports.v
338output mac_pio_intr1; // From mac_2ports of mac_2ports.v
339output [63:0] mac_pio_rdata; // From mac_2ports of mac_2ports.v
340output mac_rxc_ack0; // From mac_2ports of mac_2ports.v
341output mac_rxc_ack1; // From mac_2ports of mac_2ports.v
342output mac_rxc_ctrl0; // From mac_2ports of mac_2ports.v
343output mac_rxc_ctrl1; // From mac_2ports of mac_2ports.v
344output [63:0] mac_rxc_data0; // From mac_2ports of mac_2ports.v
345output [63:0] mac_rxc_data1; // From mac_2ports of mac_2ports.v
346output [22:0] mac_rxc_stat0; // From mac_2ports of mac_2ports.v
347output [22:0] mac_rxc_stat1; // From mac_2ports of mac_2ports.v
348output mac_rxc_tag0; // From mac_2ports of mac_2ports.v
349output mac_rxc_tag1; // From mac_2ports of mac_2ports.v
350output mac_txc_req0; // From mac_2ports of mac_2ports.v
351output mac_txc_req1; // From mac_2ports of mac_2ports.v
352output mdoe; // From mac_2ports of mac_2ports.v
353output mif_pio_intr; // From mac_2ports of mac_2ports.v
354output scan_out;
355output [15:0] testcfg_0; // to malfoy
356output [15:0] testcfg_1; // to malfoy
357output xaui_act_led_0; // From mac_2ports of mac_2ports.v
358output xaui_act_led_1; // From mac_2ports of mac_2ports.v
359output xaui_link_led_0; // From mac_2ports of mac_2ports.v
360output xaui_link_led_1; // From mac_2ports of mac_2ports.v
361
362wire BSRXN0_0;
363wire BSRXN0_1;
364wire BSRXN1_0;
365wire BSRXN1_1;
366wire BSRXN2_0;
367wire BSRXN2_1;
368wire BSRXN3_0;
369wire BSRXN3_1;
370wire BSRXP0_0;
371wire BSRXP0_1;
372wire BSRXP1_0;
373wire BSRXP1_1;
374wire BSRXP2_0;
375wire BSRXP2_1;
376wire BSRXP3_0;
377wire BSRXP3_1;
378wire [1:0] cfgrx0_0_b25_b24;
379wire [1:0] cfgrx0_1_b25_b24;
380wire [1:0] cfgrx1_0_b25_b24;
381wire [1:0] cfgrx1_1_b25_b24;
382wire [1:0] cfgrx2_0_b25_b24;
383wire [1:0] cfgrx2_1_b25_b24;
384wire [1:0] cfgrx3_0_b25_b24;
385wire [1:0] cfgrx3_1_b25_b24;
386wire cfgtx0_0_17;
387wire cfgtx0_1_17;
388wire cfgtx1_0_17;
389wire cfgtx1_1_17;
390wire cfgtx2_0_17;
391wire cfgtx2_1_17;
392wire cfgtx3_0_17;
393wire cfgtx3_1_17;
394wire esr_mac_lock_0;
395wire esr_mac_lock_1;
396wire [3:0] esr_mac_los_0;
397wire [3:0] esr_mac_los_1;
398wire esr_mac_oddcg0_0;
399wire esr_mac_oddcg0_1;
400wire mdi_0;
401wire mdi_1;
402wire mdo;
403wire niu_clk;
404wire niu_reset_l;
405wire serdes_reset_0;
406wire serdes_reset_1;
407wire aclk; // buffered version of aclk
408wire bclk; // buffered version of bclk
409wire pce_ov; // buffered version of pce_ov
410wire tcu_clk_stop;
411output mdclk; // From mac_2ports of mac_2ports.v
412
413mac_core mac_core (
414 .esr_mac_lock_0 (esr_mac_lock_0), // input (mac_core) <= (hedwig)
415 .esr_mac_lock_1 (esr_mac_lock_1), // input (mac_core) <= (hedwig)
416 .esr_mac_los_0 (esr_mac_los_0[3:0]), // input (mac_core) <= (hedwig)
417 .esr_mac_los_1 (esr_mac_los_1[3:0]), // input (mac_core) <= (hedwig)
418 .esr_mac_oddcg0_0 (esr_mac_oddcg0_0), // input (mac_core) <= (hedwig)
419 .esr_mac_oddcg0_1 (esr_mac_oddcg0_1), // input (mac_core) <= (hedwig)
420 .esr_mac_rclk_0 (esr_mac_rclk_0[3:0]), // input (hedwig,mac_core) <= ()
421 .esr_mac_rclk_1 (esr_mac_rclk_1[3:0]), // input (hedwig,mac_core) <= ()
422 .esr_mac_rxd0_0 (esr_mac_rxd0_0[9:0]), // input (mac_core) <= ()
423 .esr_mac_rxd0_1 (esr_mac_rxd0_1[9:0]), // input (mac_core) <= ()
424 .esr_mac_rxd1_0 (esr_mac_rxd1_0[9:0]), // input (mac_core) <= ()
425 .esr_mac_rxd1_1 (esr_mac_rxd1_1[9:0]), // input (mac_core) <= ()
426 .esr_mac_rxd2_0 (esr_mac_rxd2_0[9:0]), // input (mac_core) <= ()
427 .esr_mac_rxd2_1 (esr_mac_rxd2_1[9:0]), // input (mac_core) <= ()
428 .esr_mac_rxd3_0 (esr_mac_rxd3_0[9:0]), // input (mac_core) <= ()
429 .esr_mac_rxd3_1 (esr_mac_rxd3_1[9:0]), // input (mac_core) <= ()
430 .esr_mac_tclk_0 (esr_mac_tclk_0), // input (hedwig,mac_core) <= ()
431 .esr_mac_tclk_1 (esr_mac_tclk_1), // input (hedwig,mac_core) <= ()
432 .mac_125rx_test_clk (mac_125rx_test_clk), // input (hedwig,mac_core) <= ()
433 .mac_125tx_test_clk (mac_125tx_test_clk), // input (mac_core) <= ()
434 .mac_156rx_test_clk (mac_156rx_test_clk), // input (mac_core) <= ()
435 .mac_156tx_test_clk (mac_156tx_test_clk), // input (mac_core) <= ()
436 .mac_312rx_test_clk (mac_312rx_test_clk), // input (mac_core) <= ()
437 .mac_312tx_test_clk (mac_312tx_test_clk), // input (mac_core) <= ()
438 .mac_reset0 (mac_reset0), // input (mac_core) <= ()
439 .mac_reset1 (mac_reset1), // input (mac_core) <= ()
440 .mdi (mdi), // input (mac_core) <= ()
441 .mdi_0 (mdi_0), // input (mac_core) <= (hedwig)
442 .mdi_1 (mdi_1), // input (mac_core) <= (hedwig)
443 .niu_clk (niu_clk), // input (mac_core) <= (clkgen_mac)
444 .niu_reset_l (niu_reset_l), // input (hedwig,mac_core) <= (clkgen_mac)
445 .pio_clients_addr (pio_clients_addr[19:0]), // input (mac_core) <= ()
446 .pio_clients_rd (pio_clients_rd), // input (mac_core) <= ()
447 .pio_clients_wdata (pio_clients_wdata[31:0]), // input (mac_core) <= ()
448 .pio_mac_sel (pio_mac_sel), // input (mac_core) <= ()
449 .rxc_mac_req0 (rxc_mac_req0), // input (mac_core) <= ()
450 .rxc_mac_req1 (rxc_mac_req1), // input (mac_core) <= ()
451 .tcu_mac_125rx_clk_stop (tcu_clk_stop), // input (hedwig,mac_core) <= (clkgen_mac)
452 .tcu_mac_125tx_clk_stop (tcu_clk_stop), // input (hedwig,mac_core) <= (clkgen_mac)
453 .tcu_mac_156rx_clk_stop (tcu_clk_stop), // input (hedwig,mac_core) <= (clkgen_mac)
454 .tcu_mac_156tx_clk_stop (tcu_clk_stop), // input (hedwig,mac_core) <= (clkgen_mac)
455 .tcu_mac_312rx_clk_stop (tcu_clk_stop), // input (hedwig,mac_core) <= (clkgen_mac)
456 .tcu_mac_312tx_clk_stop (tcu_clk_stop), // input (hedwig,mac_core) <= (clkgen_mac)
457 .tcu_scan_en (tcu_scan_en), // input (clkgen_mac,hedwig,mac_core) <= ()
458 .tcu_scan_mode (tcu_scan_mode), // input (clkgen_mac,hedwig,mac_core) <= ()
459 .txc_mac_abort0 (txc_mac_abort0), // input (mac_core) <= ()
460 .txc_mac_abort1 (txc_mac_abort1), // input (mac_core) <= ()
461 .txc_mac_ack0 (txc_mac_ack0), // input (mac_core) <= ()
462 .txc_mac_ack1 (txc_mac_ack1), // input (mac_core) <= ()
463 .txc_mac_data0 (txc_mac_data0[63:0]), // input (mac_core) <= ()
464 .txc_mac_data1 (txc_mac_data1[63:0]), // input (mac_core) <= ()
465 .txc_mac_stat0 (txc_mac_stat0[3:0]), // input (mac_core) <= ()
466 .txc_mac_stat1 (txc_mac_stat1[3:0]), // input (mac_core) <= ()
467 .txc_mac_tag0 (txc_mac_tag0), // input (mac_core) <= ()
468 .txc_mac_tag1 (txc_mac_tag1), // input (mac_core) <= ()
469 .xaui_mdint0_l (xaui_mdint0_l), // input (mac_core) <= ()
470 .xaui_mdint1_l (xaui_mdint1_l), // input (mac_core) <= ()
471 .mac_debug_port (mac_debug_port[31:0]), // output (mac_core) => ()
472 .mac_esr_tclk_0 (mac_esr_tclk_0[3:0]), // output (mac_core) => ()
473 .mac_esr_tclk_1 (mac_esr_tclk_1[3:0]), // output (mac_core) => ()
474 .mac_esr_txd0_0 (mac_esr_txd0_0[9:0]), // output (mac_core) => ()
475 .mac_esr_txd0_1 (mac_esr_txd0_1[9:0]), // output (mac_core) => ()
476 .mac_esr_txd1_0 (mac_esr_txd1_0[9:0]), // output (mac_core) => ()
477 .mac_esr_txd1_1 (mac_esr_txd1_1[9:0]), // output (mac_core) => ()
478 .mac_esr_txd2_0 (mac_esr_txd2_0[9:0]), // output (mac_core) => ()
479 .mac_esr_txd2_1 (mac_esr_txd2_1[9:0]), // output (mac_core) => ()
480 .mac_esr_txd3_0 (mac_esr_txd3_0[9:0]), // output (mac_core) => ()
481 .mac_esr_txd3_1 (mac_esr_txd3_1[9:0]), // output (mac_core) => ()
482 .mac_pio_ack (mac_pio_ack), // output (mac_core) => ()
483 .mac_pio_err (mac_pio_err), // output (mac_core) => ()
484 .mac_pio_intr0 (mac_pio_intr0), // output (mac_core) => ()
485 .mac_pio_intr1 (mac_pio_intr1), // output (mac_core) => ()
486 .mac_pio_rdata (mac_pio_rdata[63:0]), // output (mac_core) => ()
487 .mac_rxc_ack0 (mac_rxc_ack0), // output (mac_core) => ()
488 .mac_rxc_ack1 (mac_rxc_ack1), // output (mac_core) => ()
489 .mac_rxc_ctrl0 (mac_rxc_ctrl0), // output (mac_core) => ()
490 .mac_rxc_ctrl1 (mac_rxc_ctrl1), // output (mac_core) => ()
491 .mac_rxc_data0 (mac_rxc_data0[63:0]), // output (mac_core) => ()
492 .mac_rxc_data1 (mac_rxc_data1[63:0]), // output (mac_core) => ()
493 .mac_rxc_stat0 (mac_rxc_stat0[22:0]), // output (mac_core) => ()
494 .mac_rxc_stat1 (mac_rxc_stat1[22:0]), // output (mac_core) => ()
495 .mac_rxc_tag0 (mac_rxc_tag0), // output (mac_core) => ()
496 .mac_rxc_tag1 (mac_rxc_tag1), // output (mac_core) => ()
497 .mac_txc_req0 (mac_txc_req0), // output (mac_core) => ()
498 .mac_txc_req1 (mac_txc_req1), // output (mac_core) => ()
499 .mdclk (mdclk), // output (mac_core) => (hedwig)
500 .mdo (mdo), // output (mac_core) => (hedwig)
501 .mdoe (mdoe), // output (mac_core) => ()
502 .mif_pio_intr (mif_pio_intr), // output (mac_core) => ()
503 .serdes_reset_0 (serdes_reset_0), // output (mac_core) => (hedwig)
504 .serdes_reset_1 (serdes_reset_1), // output (mac_core) => (hedwig)
505 .xaui_act_led_0 (xaui_act_led_0), // output (mac_core) => ()
506 .xaui_act_led_1 (xaui_act_led_1), // output (mac_core) => ()
507 .xaui_link_led_0 (xaui_link_led_0), // output (mac_core) => ()
508 .xaui_link_led_1 (xaui_link_led_1) // output (mac_core) => ()
509 );
510
511hedwig hedwig (
512 .cfgtx0_0 (cfgtx0_0[19:0]), // output (hedwig) => ()
513 .cfgtx1_0 (cfgtx1_0[19:0]), // output (hedwig) => ()
514 .cfgtx2_0 (cfgtx2_0[19:0]), // output (hedwig) => ()
515 .cfgtx3_0 (cfgtx3_0[19:0]), // output (hedwig) => ()
516 .cfgrx0_0 (cfgrx0_0[27:0]), // output (hedwig) => ()
517 .cfgrx1_0 (cfgrx1_0[27:0]), // output (hedwig) => ()
518 .cfgrx2_0 (cfgrx2_0[27:0]), // output (hedwig) => ()
519 .cfgrx3_0 (cfgrx3_0[27:0]), // output (hedwig) => ()
520 .cfgpll_0 (cfgpll_0[11:0]), // output (hedwig) => ()
521 .testcfg_0 (testcfg_0[15:0]), // output (hedwig) => ()
522 .ststx0_0 (ststx0_0[3:0]), // input (hedwig) <= ()
523 .ststx1_0 (ststx1_0[3:0]), // input (hedwig) <= ()
524 .ststx2_0 (ststx2_0[3:0]), // input (hedwig) <= ()
525 .ststx3_0 (ststx3_0[3:0]), // input (hedwig) <= ()
526 .stsrx0_0 (stsrx0_0[7:0]), // input (hedwig) <= ()
527 .stsrx1_0 (stsrx1_0[7:0]), // input (hedwig) <= ()
528 .stsrx2_0 (stsrx2_0[7:0]), // input (hedwig) <= ()
529 .stsrx3_0 (stsrx3_0[7:0]), // input (hedwig) <= ()
530 .stspll_0 (stspll_0[3:0]), // input (hedwig) <= ()
531 .esr_mac_rclk_0 (esr_mac_rclk_0[3:0]), // input (hedwig,mac_core) <= ()
532 .esr_mac_tclk_0 (esr_mac_tclk_0), // input (hedwig,mac_core) <= ()
533 .serdes_reset_0 (serdes_reset_0), // input (hedwig) <= (mac_core)
534 .cfgtx0_1 (cfgtx0_1[19:0]), // output (hedwig) => ()
535 .cfgtx1_1 (cfgtx1_1[19:0]), // output (hedwig) => ()
536 .cfgtx2_1 (cfgtx2_1[19:0]), // output (hedwig) => ()
537 .cfgtx3_1 (cfgtx3_1[19:0]), // output (hedwig) => ()
538 .cfgrx0_1 (cfgrx0_1[27:0]), // output (hedwig) => ()
539 .cfgrx1_1 (cfgrx1_1[27:0]), // output (hedwig) => ()
540 .cfgrx2_1 (cfgrx2_1[27:0]), // output (hedwig) => ()
541 .cfgrx3_1 (cfgrx3_1[27:0]), // output (hedwig) => ()
542 .cfgpll_1 (cfgpll_1[11:0]), // output (hedwig) => ()
543 .testcfg_1 (testcfg_1[15:0]), // output (hedwig) => ()
544 .ststx0_1 (ststx0_1[3:0]), // input (hedwig) <= ()
545 .ststx1_1 (ststx1_1[3:0]), // input (hedwig) <= ()
546 .ststx2_1 (ststx2_1[3:0]), // input (hedwig) <= ()
547 .ststx3_1 (ststx3_1[3:0]), // input (hedwig) <= ()
548 .stsrx0_1 (stsrx0_1[7:0]), // input (hedwig) <= ()
549 .stsrx1_1 (stsrx1_1[7:0]), // input (hedwig) <= ()
550 .stsrx2_1 (stsrx2_1[7:0]), // input (hedwig) <= ()
551 .stsrx3_1 (stsrx3_1[7:0]), // input (hedwig) <= ()
552 .stspll_1 (stspll_1[3:0]), // input (hedwig) <= ()
553 .esr_mac_rclk_1 (esr_mac_rclk_1[3:0]), // input (hedwig,mac_core) <= ()
554 .esr_mac_tclk_1 (esr_mac_tclk_1), // input (hedwig,mac_core) <= ()
555 .serdes_reset_1 (serdes_reset_1), // input (hedwig) <= (mac_core)
556 .esr_mac_oddcg0_0 (esr_mac_oddcg0_0), // output (hedwig) => (mac_core)
557 .esr_mac_los_0 (esr_mac_los_0[3:0]), // output (hedwig) => (mac_core)
558 .esr_mac_lock_0 (esr_mac_lock_0), // output (hedwig) => (mac_core)
559 .esr_mac_oddcg0_1 (esr_mac_oddcg0_1), // output (hedwig) => (mac_core)
560 .esr_mac_los_1 (esr_mac_los_1[3:0]), // output (hedwig) => (mac_core)
561 .esr_mac_lock_1 (esr_mac_lock_1), // output (hedwig) => (mac_core)
562 .tcu_sbs_enbstx (tcu_sbs_enbstx), // input (hedwig) <= ()
563 .tcu_sbs_enbsrx (tcu_sbs_enbsrx), // input (hedwig) <= ()
564 .cfgtx0_0_17 (cfgtx0_0_17), // input (hedwig) <= (esr_bscan)
565 .cfgtx1_0_17 (cfgtx1_0_17), // input (hedwig) <= (esr_bscan)
566 .cfgtx2_0_17 (cfgtx2_0_17), // input (hedwig) <= (esr_bscan)
567 .cfgtx3_0_17 (cfgtx3_0_17), // input (hedwig) <= (esr_bscan)
568 .cfgtx0_1_17 (cfgtx0_1_17), // input (hedwig) <= (esr_bscan)
569 .cfgtx1_1_17 (cfgtx1_1_17), // input (hedwig) <= (esr_bscan)
570 .cfgtx2_1_17 (cfgtx2_1_17), // input (hedwig) <= (esr_bscan)
571 .cfgtx3_1_17 (cfgtx3_1_17), // input (hedwig) <= (esr_bscan)
572 .cfgrx0_0_b25_b24 (cfgrx0_0_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
573 .cfgrx1_0_b25_b24 (cfgrx1_0_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
574 .cfgrx2_0_b25_b24 (cfgrx2_0_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
575 .cfgrx3_0_b25_b24 (cfgrx3_0_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
576 .cfgrx0_1_b25_b24 (cfgrx0_1_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
577 .cfgrx1_1_b25_b24 (cfgrx1_1_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
578 .cfgrx2_1_b25_b24 (cfgrx2_1_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
579 .cfgrx3_1_b25_b24 (cfgrx3_1_b25_b24[1:0]), // input (hedwig) <= (esr_bscan)
580 .tcu_scan_mode (tcu_scan_mode), // input (clkgen_mac,hedwig,mac_core) <= ()
581 .gl_mac_io_clk_stop (tcu_clk_stop), // input (hedwig,mac_core) <= (clkgen_mac)
582 .tcu_scan_en (tcu_scan_en), // input (clkgen_mac,hedwig,mac_core) <= ()
583 .tcu_sbs_enbspt (tcu_sbs_enbspt), // input (hedwig) <= ()
584 .mac_125rx_test_clk (mac_125rx_test_clk), // input (hedwig,mac_core) <= ()
585 .BSRXP0_0 (BSRXP0_0), // output (hedwig) => (esr_bscan)
586 .BSRXP1_0 (BSRXP1_0), // output (hedwig) => (esr_bscan)
587 .BSRXP2_0 (BSRXP2_0), // output (hedwig) => (esr_bscan)
588 .BSRXP3_0 (BSRXP3_0), // output (hedwig) => (esr_bscan)
589 .BSRXN0_0 (BSRXN0_0), // output (hedwig) => (esr_bscan)
590 .BSRXN1_0 (BSRXN1_0), // output (hedwig) => (esr_bscan)
591 .BSRXN2_0 (BSRXN2_0), // output (hedwig) => (esr_bscan)
592 .BSRXN3_0 (BSRXN3_0), // output (hedwig) => (esr_bscan)
593 .BSRXP0_1 (BSRXP0_1), // output (hedwig) => (esr_bscan)
594 .BSRXP1_1 (BSRXP1_1), // output (hedwig) => (esr_bscan)
595 .BSRXP2_1 (BSRXP2_1), // output (hedwig) => (esr_bscan)
596 .BSRXP3_1 (BSRXP3_1), // output (hedwig) => (esr_bscan)
597 .BSRXN0_1 (BSRXN0_1), // output (hedwig) => (esr_bscan)
598 .BSRXN1_1 (BSRXN1_1), // output (hedwig) => (esr_bscan)
599 .BSRXN2_1 (BSRXN2_1), // output (hedwig) => (esr_bscan)
600 .BSRXN3_1 (BSRXN3_1), // output (hedwig) => (esr_bscan)
601 .niu_reset_l (niu_reset_l), // input (hedwig,mac_core) <= (clkgen_mac)
602 .mdclk (mdclk), // input (hedwig) <= (mac_core)
603 .mdo (mdo), // input (hedwig) <= (mac_core)
604 .mdi_0 (mdi_0), // output (hedwig) => (mac_core)
605 .mdi_1 (mdi_1) // output (hedwig) => (mac_core)
606 );
607
608clkgen_mac clkgen_mac (
609 .niu_clk (niu_clk), // output (clkgen_mac) => (mac_core)
610 .aclk (aclk), // output (clkgen_mac) => ()
611 .bclk (bclk), // output (clkgen_mac) => ()
612 .scan_out (scan_out), // output (clkgen_mac) => ()
613 .pce_ov (pce_ov), // output (clkgen_mac) => ()
614 .tcu_clk_stop (tcu_clk_stop), // output (clkgen_mac) => (hedwig,mac_core)
615 .niu_reset_l (niu_reset_l), // output (clkgen_mac) => (hedwig,mac_core)
616 .tcu_pce_ov (tcu_pce_ov), // input (clkgen_mac) <= ()
617 .tcu_div_bypass (tcu_div_bypass), // input (clkgen_mac) <= ()
618 .tcu_scan_en (tcu_scan_en), // input (clkgen_mac,hedwig,mac_core) <= ()
619 .gl_mac_io_clk_stop (gl_mac_io_clk_stop), // input (clkgen_mac) <= ()
620 .scan_in (scan_in), // input (clkgen_mac) <= ()
621 .tcu_wr_inhibit (tcu_wr_inhibit), // input (clkgen_mac) <= ()
622 .tcu_atpg_mode (tcu_atpg_mode), // input (clkgen_mac) <= ()
623 .tcu_scan_mode (tcu_scan_mode), // input (clkgen_mac,hedwig,mac_core) <= ()
624 .gl_mac_io_out (gl_mac_io_out), // input (clkgen_mac) <= ()
625 .cmp_gclk_c1_mac (cmp_gclk_c1_mac), // input (clkgen_mac) <= ()
626 .tcu_aclk (tcu_aclk), // input (clkgen_mac) <= ()
627 .tcu_bclk (tcu_bclk), // input (clkgen_mac) <= ()
628 .cluster_arst_l (cluster_arst_l), // input (clkgen_mac) <= ()
629 .gl_mac_ (gl_mac_) // input (clkgen_mac) <= ()
630 );
631
632esr_bscan esr_bscan (
633 .peu_mac_sbs_input (peu_mac_sbs_input), // input (esr_bscan) <= ()
634 .mac_mcu_3_sbs_output (mac_mcu_3_sbs_output), // output (esr_bscan) => ()
635 .tcu_sbs_scan_en (tcu_sbs_scan_en), // input (esr_bscan) <= ()
636 .tcu_sbs_aclk (tcu_sbs_aclk), // input (esr_bscan) <= ()
637 .tcu_sbs_bclk (tcu_sbs_bclk), // input (esr_bscan) <= ()
638 .tcu_sbs_clk (tcu_sbs_clk), // input (esr_bscan) <= ()
639 .tcu_sbs_uclk (tcu_sbs_uclk), // input (esr_bscan) <= ()
640 .tcu_sbs_acmode (tcu_sbs_acmode), // input (esr_bscan) <= ()
641 .tcu_sbs_actestsignal (tcu_sbs_actestsignal), // input (esr_bscan) <= ()
642 .BSRXP0_0 (BSRXP0_0), // input (esr_bscan) <= (hedwig)
643 .BSRXP1_0 (BSRXP1_0), // input (esr_bscan) <= (hedwig)
644 .BSRXP2_0 (BSRXP2_0), // input (esr_bscan) <= (hedwig)
645 .BSRXP3_0 (BSRXP3_0), // input (esr_bscan) <= (hedwig)
646 .BSRXN0_0 (BSRXN0_0), // input (esr_bscan) <= (hedwig)
647 .BSRXN1_0 (BSRXN1_0), // input (esr_bscan) <= (hedwig)
648 .BSRXN2_0 (BSRXN2_0), // input (esr_bscan) <= (hedwig)
649 .BSRXN3_0 (BSRXN3_0), // input (esr_bscan) <= (hedwig)
650 .BSRXP0_1 (BSRXP0_1), // input (esr_bscan) <= (hedwig)
651 .BSRXP1_1 (BSRXP1_1), // input (esr_bscan) <= (hedwig)
652 .BSRXP2_1 (BSRXP2_1), // input (esr_bscan) <= (hedwig)
653 .BSRXP3_1 (BSRXP3_1), // input (esr_bscan) <= (hedwig)
654 .BSRXN0_1 (BSRXN0_1), // input (esr_bscan) <= (hedwig)
655 .BSRXN1_1 (BSRXN1_1), // input (esr_bscan) <= (hedwig)
656 .BSRXN2_1 (BSRXN2_1), // input (esr_bscan) <= (hedwig)
657 .BSRXN3_1 (BSRXN3_1), // input (esr_bscan) <= (hedwig)
658 .cfgtx0_0_17 (cfgtx0_0_17), // output (esr_bscan) => (hedwig)
659 .cfgtx1_0_17 (cfgtx1_0_17), // output (esr_bscan) => (hedwig)
660 .cfgtx2_0_17 (cfgtx2_0_17), // output (esr_bscan) => (hedwig)
661 .cfgtx3_0_17 (cfgtx3_0_17), // output (esr_bscan) => (hedwig)
662 .cfgtx0_1_17 (cfgtx0_1_17), // output (esr_bscan) => (hedwig)
663 .cfgtx1_1_17 (cfgtx1_1_17), // output (esr_bscan) => (hedwig)
664 .cfgtx2_1_17 (cfgtx2_1_17), // output (esr_bscan) => (hedwig)
665 .cfgtx3_1_17 (cfgtx3_1_17), // output (esr_bscan) => (hedwig)
666 .cfgrx0_0_b25_b24 (cfgrx0_0_b25_b24[1:0]), // output (esr_bscan) => (hedwig)
667 .cfgrx1_0_b25_b24 (cfgrx1_0_b25_b24[1:0]), // output (esr_bscan) => (hedwig)
668 .cfgrx2_0_b25_b24 (cfgrx2_0_b25_b24[1:0]), // output (esr_bscan) => (hedwig)
669 .cfgrx3_0_b25_b24 (cfgrx3_0_b25_b24[1:0]), // output (esr_bscan) => (hedwig)
670 .cfgrx0_1_b25_b24 (cfgrx0_1_b25_b24[1:0]), // output (esr_bscan) => (hedwig)
671 .cfgrx1_1_b25_b24 (cfgrx1_1_b25_b24[1:0]), // output (esr_bscan) => (hedwig)
672 .cfgrx2_1_b25_b24 (cfgrx2_1_b25_b24[1:0]), // output (esr_bscan) => (hedwig)
673 .cfgrx3_1_b25_b24 (cfgrx3_1_b25_b24[1:0]) // output (esr_bscan) => (hedwig)
674 );
675
676endmodule
677
678// VPERL: GENERATED_END
679
Full OpenSPARC design & verification tarball including full HDL.