Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / mcu / mcu_crcn_ctl / synopsys / script / user_cfg.scr

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: user_cfg.scr
# Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
# 4150 Network Circle, Santa Clara, California 95054, U.S.A.
#
# * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
#
# For the avoidance of doubt, and except that if any non-GPL license 
# choice is available it will apply instead, Sun elects to use only 
# the General Public License version 2 (GPLv2) at this time for any 
# software where a choice of GPL license versions is made 
# available with the language indicating that GPLv2 or any later version 
# may be used, or where a choice of which version of the GPL is applied is 
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# ========== Copyright Header End ============================================
source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_u1gb/cl_u1gb.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_u1lvt/cl_u1lvt.behV

libs/clk/rtl/clkgen_mcu_cmp.v
libs/clk/rtl/clkgen_mcu_dr.v
libs/clk/rtl/clkgen_mcu_io.v

design/sys/iop/mcu/rtl/mcu.v
design/sys/iop/mcu/rtl/mcu_addrdp_dp.v
design/sys/iop/mcu/rtl/mcu_adrgen_ctl.v
design/sys/iop/mcu/rtl/mcu_adrq_dp.v
design/sys/iop/mcu/rtl/mcu_algnbf_dp.v
design/sys/iop/mcu/rtl/mcu_bnksm_ctl.v
design/sys/iop/mcu/rtl/mcu_bscan_ctl.v
design/sys/iop/mcu/rtl/mcu_crcn_ctl.v
design/sys/iop/mcu/rtl/mcu_crcnd_ctl.v
design/sys/iop/mcu/rtl/mcu_crcndf_ctl.v
design/sys/iop/mcu/rtl/mcu_crcs_ctl.v
design/sys/iop/mcu/rtl/mcu_crcsc_ctl.v
design/sys/iop/mcu/rtl/mcu_crcscf_ctl.v
design/sys/iop/mcu/rtl/mcu_crcsd_ctl.v
design/sys/iop/mcu/rtl/mcu_crcsdf_ctl.v
design/sys/iop/mcu/rtl/mcu_dmmdly_ctl.v
design/sys/iop/mcu/rtl/mcu_drif_ctl.v
design/sys/iop/mcu/rtl/mcu_drq_ctl.v
design/sys/iop/mcu/rtl/mcu_eccgen_dp.v
design/sys/iop/mcu/rtl/mcu_errq_ctl.v
design/sys/iop/mcu/rtl/mcu_fbd_dp.v
design/sys/iop/mcu/rtl/mcu_fbdic_ctl.v
design/sys/iop/mcu/rtl/mcu_fbdird_dp.v
design/sys/iop/mcu/rtl/mcu_fbdiwr_dp.v
design/sys/iop/mcu/rtl/mcu_fbdtm_ctl.v
design/sys/iop/mcu/rtl/mcu_fdoklu_ctl.v
design/sys/iop/mcu/rtl/mcu_fdout_ctl.v
design/sys/iop/mcu/rtl/mcu_frdbuf_dp.v
design/sys/iop/mcu/rtl/mcu_ibist_ctl.v
design/sys/iop/mcu/rtl/mcu_ibrx_ctl.v
design/sys/iop/mcu/rtl/mcu_ibtx_ctl.v
design/sys/iop/mcu/rtl/mcu_l2ecc_dp.v
design/sys/iop/mcu/rtl/mcu_l2if_ctl.v
design/sys/iop/mcu/rtl/mcu_l2rdmx_dp.v
design/sys/iop/mcu/rtl/mcu_latq_ctl.v
design/sys/iop/mcu/rtl/mcu_lndskw_dp.v
design/sys/iop/mcu/rtl/mcu_mbist_ctl.v
design/sys/iop/mcu/rtl/mcu_nibcor_dp.v
design/sys/iop/mcu/rtl/mcu_otq_ctl.v
design/sys/iop/mcu/rtl/mcu_pdmc_ctl.v
design/sys/iop/mcu/rtl/mcu_pdmchi_ctl.v
design/sys/iop/mcu/rtl/mcu_rdata_ctl.v
design/sys/iop/mcu/rtl/mcu_rdpctl_ctl.v
design/sys/iop/mcu/rtl/mcu_readdp_dp.v
design/sys/iop/mcu/rtl/mcu_reqq_ctl.v
design/sys/iop/mcu/rtl/mcu_ucb_ctl.v
design/sys/iop/mcu/rtl/mcu_ucbbuf_ctl.v
design/sys/iop/mcu/rtl/mcu_ucbin_ctl.v
design/sys/iop/mcu/rtl/mcu_ucbout_ctl.v
design/sys/iop/mcu/rtl/mcu_woq_ctl.v
design/sys/iop/mcu/rtl/mcu_wrdp_dp.v
}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module mcu_crcn_ctl

set include_paths {\
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk dr_gclk
set default_clk_freq  400
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { drl2clk           400.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}