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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_algnbf_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define DRIF_MCU_STATE_00 5'd0 | |
36 | `define DRIF_MCU_STATE_01 5'd1 | |
37 | `define DRIF_MCU_STATE_02 5'd2 | |
38 | `define DRIF_MCU_STATE_03 5'd3 | |
39 | `define DRIF_MCU_STATE_04 5'd4 | |
40 | `define DRIF_MCU_STATE_05 5'd5 | |
41 | `define DRIF_MCU_STATE_06 5'd6 | |
42 | `define DRIF_MCU_STATE_07 5'd7 | |
43 | `define DRIF_MCU_STATE_08 5'd8 | |
44 | `define DRIF_MCU_STATE_09 5'd9 | |
45 | `define DRIF_MCU_STATE_10 5'd10 | |
46 | `define DRIF_MCU_STATE_11 5'd11 | |
47 | `define DRIF_MCU_STATE_12 5'd12 | |
48 | `define DRIF_MCU_STATE_13 5'd13 | |
49 | `define DRIF_MCU_STATE_14 5'd14 | |
50 | `define DRIF_MCU_STATE_15 5'd15 | |
51 | `define DRIF_MCU_STATE_16 5'd16 | |
52 | `define DRIF_MCU_STATE_17 5'd17 | |
53 | `define DRIF_MCU_STATE_18 5'd18 | |
54 | `define DRIF_MCU_STATE_19 5'd19 | |
55 | `define DRIF_MCU_STATE_20 5'd20 | |
56 | `define DRIF_MCU_STATE_21 5'd21 | |
57 | `define DRIF_MCU_STATE_22 5'd22 | |
58 | `define DRIF_MCU_STATE_23 5'd23 | |
59 | `define DRIF_MCU_STATE_24 5'd24 | |
60 | `define DRIF_MCU_STATE_25 5'd25 | |
61 | `define DRIF_MCU_STATE_26 5'd26 | |
62 | ||
63 | `define DRIF_MCU_STATE_MAX 4 | |
64 | `define DRIF_MCU_STATE_WIDTH 5 | |
65 | ||
66 | // | |
67 | // UCB Packet Type | |
68 | // =============== | |
69 | // | |
70 | `define UCB_READ_NACK 4'b0000 // ack/nack types | |
71 | `define UCB_READ_ACK 4'b0001 | |
72 | `define UCB_WRITE_ACK 4'b0010 | |
73 | `define UCB_IFILL_ACK 4'b0011 | |
74 | `define UCB_IFILL_NACK 4'b0111 | |
75 | ||
76 | `define UCB_READ_REQ 4'b0100 // req types | |
77 | `define UCB_WRITE_REQ 4'b0101 | |
78 | `define UCB_IFILL_REQ 4'b0110 | |
79 | ||
80 | `define UCB_INT 4'b1000 // plain interrupt | |
81 | `define UCB_INT_VEC 4'b1100 // interrupt with vector | |
82 | `define UCB_RESET_VEC 4'b1101 // reset with vector | |
83 | `define UCB_IDLE_VEC 4'b1110 // idle with vector | |
84 | `define UCB_RESUME_VEC 4'b1111 // resume with vector | |
85 | ||
86 | ||
87 | // | |
88 | // UCB Data Packet Format | |
89 | // ====================== | |
90 | // | |
91 | `define UCB_NOPAY_PKT_WIDTH 64 // packet without payload | |
92 | `define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload | |
93 | `define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload | |
94 | ||
95 | `define UCB_DATA_EXT_HI 191 // (64) extended data | |
96 | `define UCB_DATA_EXT_LO 128 | |
97 | `define UCB_DATA_HI 127 // (64) data | |
98 | `define UCB_DATA_LO 64 | |
99 | `define UCB_RSV_HI 63 // (9) reserved bits | |
100 | `define UCB_RSV_LO 55 | |
101 | `define UCB_ADDR_HI 54 // (40) bit address | |
102 | `define UCB_ADDR_LO 15 | |
103 | `define UCB_SIZE_HI 14 // (3) request size | |
104 | `define UCB_SIZE_LO 12 | |
105 | `define UCB_BUF_HI 11 // (2) buffer ID | |
106 | `define UCB_BUF_LO 10 | |
107 | `define UCB_THR_HI 9 // (6) cpu/thread ID | |
108 | `define UCB_THR_LO 4 | |
109 | `define UCB_PKT_HI 3 // (4) packet type | |
110 | `define UCB_PKT_LO 0 | |
111 | ||
112 | `define UCB_DATA_EXT_WIDTH 64 | |
113 | `define UCB_DATA_WIDTH 64 | |
114 | `define UCB_RSV_WIDTH 9 | |
115 | `define UCB_ADDR_WIDTH 40 | |
116 | `define UCB_SIZE_WIDTH 3 | |
117 | `define UCB_BUF_WIDTH 2 | |
118 | `define UCB_THR_WIDTH 6 | |
119 | `define UCB_PKT_WIDTH 4 | |
120 | ||
121 | // Size encoding for the UCB_SIZE_HI/LO field | |
122 | // 000 - byte | |
123 | // 001 - half-word | |
124 | // 010 - word | |
125 | // 011 - double-word | |
126 | `define UCB_SIZE_1B 3'b000 | |
127 | `define UCB_SIZE_2B 3'b001 | |
128 | `define UCB_SIZE_4B 3'b010 | |
129 | `define UCB_SIZE_8B 3'b011 | |
130 | `define UCB_SIZE_16B 3'b100 | |
131 | ||
132 | ||
133 | // | |
134 | // UCB Interrupt Packet Format | |
135 | // =========================== | |
136 | // | |
137 | `define UCB_INT_PKT_WIDTH 64 | |
138 | ||
139 | `define UCB_INT_RSV_HI 63 // (7) reserved bits | |
140 | `define UCB_INT_RSV_LO 57 | |
141 | `define UCB_INT_VEC_HI 56 // (6) interrupt vector | |
142 | `define UCB_INT_VEC_LO 51 | |
143 | `define UCB_INT_STAT_HI 50 // (32) interrupt status | |
144 | `define UCB_INT_STAT_LO 19 | |
145 | `define UCB_INT_DEV_HI 18 // (9) device ID | |
146 | `define UCB_INT_DEV_LO 10 | |
147 | //`define UCB_THR_HI 9 // (6) cpu/thread ID shared with | |
148 | //`define UCB_THR_LO 4 data packet format | |
149 | //`define UCB_PKT_HI 3 // (4) packet type shared with | |
150 | //`define UCB_PKT_LO 0 // data packet format | |
151 | ||
152 | `define UCB_INT_RSV_WIDTH 7 | |
153 | `define UCB_INT_VEC_WIDTH 6 | |
154 | `define UCB_INT_STAT_WIDTH 32 | |
155 | `define UCB_INT_DEV_WIDTH 9 | |
156 | ||
157 | ||
158 | `define MCU_CAS_BIT2_SEL_PA10 4'h1 | |
159 | `define MCU_CAS_BIT2_SEL_PA32 4'h2 | |
160 | `define MCU_CAS_BIT2_SEL_PA33 4'h4 | |
161 | `define MCU_CAS_BIT2_SEL_PA34 4'h8 | |
162 | ||
163 | `define MCU_CAS_BIT3_SEL_PA11 4'h1 | |
164 | `define MCU_CAS_BIT3_SEL_PA33 4'h2 | |
165 | `define MCU_CAS_BIT3_SEL_PA34 4'h4 | |
166 | `define MCU_CAS_BIT3_SEL_PA35 4'h8 | |
167 | ||
168 | `define MCU_CAS_BIT4_SEL_PA12 3'h1 | |
169 | `define MCU_CAS_BIT4_SEL_PA35 3'h2 | |
170 | `define MCU_CAS_BIT4_SEL_PA36 3'h4 | |
171 | ||
172 | `define MCU_DIMMHI_SEL_ZERO 6'h01 | |
173 | `define MCU_DIMMHI_SEL_PA32 6'h02 | |
174 | `define MCU_DIMMHI_SEL_PA33 6'h04 | |
175 | `define MCU_DIMMHI_SEL_PA34 6'h08 | |
176 | `define MCU_DIMMHI_SEL_PA35 6'h10 | |
177 | `define MCU_DIMMHI_SEL_PA36 6'h20 | |
178 | ||
179 | `define MCU_DIMMLO_SEL_ZERO 4'h1 | |
180 | `define MCU_DIMMLO_SEL_PA10 4'h2 | |
181 | `define MCU_DIMMLO_SEL_PA11 4'h4 | |
182 | `define MCU_DIMMLO_SEL_PA12 4'h8 | |
183 | ||
184 | `define MCU_RANK_SEL_ZERO 7'h01 | |
185 | `define MCU_RANK_SEL_PA32 7'h02 | |
186 | `define MCU_RANK_SEL_PA33 7'h04 | |
187 | `define MCU_RANK_SEL_PA34 7'h08 | |
188 | `define MCU_RANK_SEL_PA35 7'h10 | |
189 | `define MCU_RANK_SEL_PA10 7'h20 | |
190 | `define MCU_RANK_SEL_PA11 7'h40 | |
191 | ||
192 | `define MCU_ADDR_ERR_SEL_39_32 6'h01 | |
193 | `define MCU_ADDR_ERR_SEL_39_33 6'h02 | |
194 | `define MCU_ADDR_ERR_SEL_39_34 6'h04 | |
195 | `define MCU_ADDR_ERR_SEL_39_35 6'h08 | |
196 | `define MCU_ADDR_ERR_SEL_39_36 6'h10 | |
197 | `define MCU_ADDR_ERR_SEL_39_37 6'h20 | |
198 | ||
199 | `define DRIF_ERR_IDLE 0 | |
200 | `define DRIF_ERR_IDLE_ST 5'h1 | |
201 | `define DRIF_ERR_READ0 1 | |
202 | `define DRIF_ERR_READ0_ST 5'h2 | |
203 | `define DRIF_ERR_WRITE 2 | |
204 | `define DRIF_ERR_WRITE_ST 5'h4 | |
205 | `define DRIF_ERR_READ1 3 | |
206 | `define DRIF_ERR_READ1_ST 5'h8 | |
207 | `define DRIF_ERR_CRC_FR 4 | |
208 | `define DRIF_ERR_CRC_FR_ST 5'h10 | |
209 | ||
210 | `define MCU_WDQ_RF_DATA_WIDTH 72 | |
211 | `define MCU_WDQ_RF_ADDR_WIDTH 5 | |
212 | `define MCU_WDQ_RF_DEPTH 32 | |
213 | ||
214 | // FBDIMM header defines | |
215 | `define FBD_TS0_HDR 12'hbfe | |
216 | `define FBD_TS1_HDR 12'hffe | |
217 | `define FBD_TS2_HDR 12'h7fe | |
218 | `define FBD_TS3_HDR 12'h3fe | |
219 | ||
220 | // MCU FBDIMM Channel commands | |
221 | `define FBD_DRAM_CMD_NOP 3'h0 | |
222 | `define FBD_DRAM_CMD_OTHER 3'h1 | |
223 | `define FBD_DRAM_CMD_RD 3'h2 | |
224 | `define FBD_DRAM_CMD_WR 3'h3 | |
225 | `define FBD_DRAM_CMD_ACT 3'h4 | |
226 | `define FBD_DRAM_CMD_WDATA 3'h5 | |
227 | ||
228 | `define FBD_DRAM_CMD_OTHER_REF 3'h5 | |
229 | `define FBD_DRAM_CMD_OTHER_SRE 3'h4 | |
230 | `define FBD_DRAM_CMD_OTHER_PDE 3'h2 | |
231 | `define FBD_DRAM_CMD_OTHER_SRPDX 3'h3 | |
232 | ||
233 | `define FBD_CHNL_CMD_NOP 2'h0 | |
234 | `define FBD_CHNL_CMD_SYNC 2'h1 | |
235 | `define FBD_CHNL_CMD_SCRST 2'h2 | |
236 | ||
237 | `define FBDIC_ERR_IDLE_ST 7'h01 | |
238 | `define FBDIC_ERR_IDLE 0 | |
239 | ||
240 | `define FBDIC_ERR_STS_ST 7'h02 | |
241 | `define FBDIC_ERR_STS 1 | |
242 | ||
243 | `define FBDIC_ERR_SCRST_ST 7'h04 | |
244 | `define FBDIC_ERR_SCRST 2 | |
245 | ||
246 | `define FBDIC_ERR_SCRST_STS_ST 7'h08 | |
247 | `define FBDIC_ERR_SCRST_STS 3 | |
248 | ||
249 | `define FBDIC_ERR_STS2_ST 7'h10 | |
250 | `define FBDIC_ERR_STS2 4 | |
251 | ||
252 | `define FBDIC_ERR_FASTRST_ST 7'h20 | |
253 | `define FBDIC_ERR_FASTRST 5 | |
254 | ||
255 | `define FBDIC_ERR_FASTRST_STS_ST 7'h40 | |
256 | `define FBDIC_ERR_FASTRST_STS 6 | |
257 | ||
258 | ||
259 | // IBIST DEFINITION | |
260 | ||
261 | `define L_2_0 12'h555 | |
262 | `define L_2_1 12'h555 | |
263 | `define L_4_0 12'h333 | |
264 | `define L_4_1 12'h333 | |
265 | `define L_6_0 12'h1c7 | |
266 | `define L_6_1 12'h1c7 | |
267 | `define L_8_0 12'h0f0 | |
268 | `define L_8_1 12'hf0f | |
269 | `define L_24_0 12'h000 | |
270 | `define L_24_1 12'hfff | |
271 | ||
272 | `define idle 4'h0 | |
273 | ||
274 | `define error_0 4'h1 | |
275 | `define error_1 4'h2 | |
276 | ||
277 | `define start1_0 4'h3 | |
278 | `define start1_1 4'h4 | |
279 | `define start2_0 4'h5 | |
280 | `define start2_1 4'h6 | |
281 | ||
282 | `define pat1_0 4'h7 | |
283 | `define pat1_1 4'h8 | |
284 | ||
285 | `define clkpat_0 4'h9 | |
286 | `define clkpat_1 4'ha | |
287 | ||
288 | `define const_0 4'hb | |
289 | `define const_1 4'hc | |
290 | ||
291 | `define stop1_0 4'h1 | |
292 | `define stop1_1 4'h2 | |
293 | ||
294 | `define stop2_0 4'hd | |
295 | `define stop2_1 4'he | |
296 | `define error 4'hf | |
297 | ||
298 | `define IBTX_STATE_IDLE 0 | |
299 | `define IBTX_STATE_PATT 1 | |
300 | `define IBTX_STATE_MODN 2 | |
301 | `define IBTX_STATE_CONST 3 | |
302 | ||
303 | `define IBRX_STATE_IDLE 0 | |
304 | `define IBRX_STATE_PATT 1 | |
305 | `define IBRX_STATE_MODN 2 | |
306 | `define IBRX_STATE_CONST 3 | |
307 | ||
308 | ||
309 | ||
310 | module mcu_algnbf_dp ( | |
311 | dout, | |
312 | ts0_hdr_match, | |
313 | status_parity, | |
314 | idle_match, | |
315 | alert_match, | |
316 | alert_asserted, | |
317 | nbde, | |
318 | thermal_trip, | |
319 | din, | |
320 | inc_rptr, | |
321 | inc_wptr, | |
322 | clr_ptrs, | |
323 | lfsr_bit, | |
324 | drl2clk, | |
325 | scan_in, | |
326 | scan_out, | |
327 | tcu_pce_ov, | |
328 | tcu_aclk, | |
329 | tcu_bclk, | |
330 | tcu_scan_en, | |
331 | wmr_scan_in, | |
332 | wmr_scan_out, | |
333 | aclk_wmr); | |
334 | wire pce_ov; | |
335 | wire stop; | |
336 | wire siclk; | |
337 | wire soclk; | |
338 | wire se; | |
339 | wire sp_2_0; | |
340 | wire [1:0] lfsr_bit_l; | |
341 | wire rptr_sl5; | |
342 | wire buf5_en; | |
343 | wire rptr_sl5_inc; | |
344 | wire buf5_en_inc; | |
345 | wire clr_rd_ptr; | |
346 | wire clr_wr_ptr; | |
347 | wire [2:0] rptr; | |
348 | wire unused1; | |
349 | wire [2:0] rptr_in; | |
350 | wire unused; | |
351 | wire inv_clr_rd_ptr; | |
352 | wire inv_clr_wr_ptr; | |
353 | wire inv_clr_ptrs; | |
354 | wire [2:0] clr_rptr_in; | |
355 | wire [2:0] wptr; | |
356 | wire unused3; | |
357 | wire [2:0] mux_inc; | |
358 | wire unused2; | |
359 | wire [2:0] wptr_in; | |
360 | wire [0:0] wptr_next; | |
361 | wire [2:0] rptr_l; | |
362 | wire rptr_sl0; | |
363 | wire rptr_sl1; | |
364 | wire rptr_sl2; | |
365 | wire rptr_sl3; | |
366 | wire rptr_sl4; | |
367 | wire [11:0] buf0; | |
368 | wire [11:0] buf1; | |
369 | wire [11:0] buf2; | |
370 | wire [11:0] buf3; | |
371 | wire [11:0] buf4; | |
372 | wire [11:0] buf5; | |
373 | wire [2:0] wptr_l; | |
374 | wire [11:0] clr_din; | |
375 | wire buf0_en; | |
376 | wire buf1_en; | |
377 | wire buf2_en; | |
378 | wire buf3_en; | |
379 | wire buf4_en; | |
380 | wire ff_buf0_scanin; | |
381 | wire ff_buf0_scanout; | |
382 | wire ff_buf1_scanin; | |
383 | wire ff_buf1_scanout; | |
384 | wire ff_buf2_scanin; | |
385 | wire ff_buf2_scanout; | |
386 | wire ff_buf3_scanin; | |
387 | wire ff_buf3_scanout; | |
388 | wire ff_buf4_scanin; | |
389 | wire ff_buf4_scanout; | |
390 | wire ff_buf5_scanin; | |
391 | wire ff_buf5_scanout; | |
392 | wire ff_rptr_wptr_wmr_scanin; | |
393 | wire ff_rptr_wptr_wmr_scanout; | |
394 | ||
395 | ||
396 | output [11:0] dout; | |
397 | output ts0_hdr_match; | |
398 | output status_parity; | |
399 | output idle_match; | |
400 | output alert_match; | |
401 | output alert_asserted; | |
402 | output nbde; | |
403 | output [1:0] thermal_trip; | |
404 | ||
405 | input [11:0] din; | |
406 | input inc_rptr; | |
407 | input inc_wptr; | |
408 | input clr_ptrs; | |
409 | input [1:0] lfsr_bit; | |
410 | ||
411 | input drl2clk; | |
412 | input scan_in; | |
413 | output scan_out; | |
414 | input tcu_pce_ov; | |
415 | input tcu_aclk; | |
416 | input tcu_bclk; | |
417 | input tcu_scan_en; | |
418 | ||
419 | input wmr_scan_in; | |
420 | output wmr_scan_out; | |
421 | input aclk_wmr; | |
422 | ||
423 | assign pce_ov = tcu_pce_ov; | |
424 | assign stop = 1'b0; | |
425 | assign siclk = tcu_aclk; | |
426 | assign soclk = tcu_bclk; | |
427 | assign se = tcu_scan_en; | |
428 | ||
429 | mcu_algnbf_dp_cmp_macro__width_12 m_ts0_hdr_match ( | |
430 | .din0( `FBD_TS0_HDR ), | |
431 | .din1( dout[11:0] ), | |
432 | .dout( ts0_hdr_match )); | |
433 | ||
434 | mcu_algnbf_dp_xor_macro__ports_3 m_status_parity2_0 ( | |
435 | .din0( dout[0] ), | |
436 | .din1( dout[1] ), | |
437 | .din2( dout[2] ), | |
438 | .dout( sp_2_0 )); | |
439 | ||
440 | mcu_algnbf_dp_xor_macro__ports_3 m_status_parity4_0 ( | |
441 | .din0( sp_2_0 ), | |
442 | .din1( dout[3] ), | |
443 | .din2( dout[4] ), | |
444 | .dout( status_parity )); | |
445 | ||
446 | mcu_algnbf_dp_cmp_macro__width_12 m_idle_match ( | |
447 | .din0( dout[11:0] ), | |
448 | .din1( { {6{lfsr_bit[1]}}, {6{lfsr_bit[0]}} } ), | |
449 | .dout( idle_match )); | |
450 | ||
451 | mcu_algnbf_dp_inv_macro__width_2 m_inv_lfsr_bit ( | |
452 | .din( lfsr_bit[1:0] ), | |
453 | .dout( lfsr_bit_l[1:0] )); | |
454 | ||
455 | mcu_algnbf_dp_cmp_macro__width_12 m_alert_match ( | |
456 | .din0( dout[11:0] ), | |
457 | .din1( { {6{lfsr_bit_l[1]}}, {6{lfsr_bit_l[0]}} } ), | |
458 | .dout( alert_match )); | |
459 | ||
460 | mcu_algnbf_dp_and_macro__width_1 m_alert_asserted ( | |
461 | .din0( dout[0] ), | |
462 | .din1( status_parity ), | |
463 | .dout( alert_asserted )); | |
464 | ||
465 | mcu_algnbf_dp_and_macro__width_1 m_nbde ( | |
466 | .din0( dout[3] ), | |
467 | .din1( status_parity ), | |
468 | .dout( nbde )); | |
469 | ||
470 | mcu_algnbf_dp_and_macro__width_2 m_thermal_trip ( | |
471 | .din0( dout[2:1] ), | |
472 | .din1( {2{status_parity}} ), | |
473 | .dout( thermal_trip[1:0] )); | |
474 | ||
475 | // assign clr_rd_ptr = clr_ptrs | rptr_sl5 & inc_rptr; | |
476 | // assign clr_wr_ptr = clr_ptrs | buf5_en & inc_wptr; | |
477 | ||
478 | mcu_algnbf_dp_and_macro__width_2 m_inc0_ptrs ( | |
479 | .din0({ inc_rptr, inc_wptr }), | |
480 | .din1({ rptr_sl5, buf5_en }), | |
481 | .dout({ rptr_sl5_inc, buf5_en_inc })); | |
482 | ||
483 | mcu_algnbf_dp_or_macro__width_2 m_clr_ptrs ( | |
484 | .din0({2{ clr_ptrs }}), | |
485 | .din1({ rptr_sl5_inc, buf5_en_inc }), | |
486 | .dout({ clr_rd_ptr, clr_wr_ptr })); | |
487 | ||
488 | ////csret 11/15/2004 | |
489 | //asign rptr_in[2:0] = rptr[2:0] + 3'h1; | |
490 | mcu_algnbf_dp_increment_macro__width_4 m_rptr_inc ( | |
491 | .din ( {1'b0,rptr[2:0]} ), | |
492 | .cin ( inc_rptr ), | |
493 | .dout ( {unused1, rptr_in[2:0]} ), | |
494 | .cout ( unused ) ); | |
495 | ||
496 | mcu_algnbf_dp_inv_macro__width_3 m_inv_clr_ptrs ( | |
497 | .din ( {clr_rd_ptr, clr_wr_ptr, clr_ptrs } ), | |
498 | .dout( {inv_clr_rd_ptr, inv_clr_wr_ptr, inv_clr_ptrs} ) ); | |
499 | ||
500 | mcu_algnbf_dp_and_macro__ports_2__width_3 m_and_rptr_clr_in ( | |
501 | .din0 ( {3{inv_clr_rd_ptr}} ), | |
502 | .din1 ( rptr_in[2:0] ), | |
503 | .dout ( clr_rptr_in[2:0] ) ); | |
504 | ||
505 | ////csret 11/15/2004 | |
506 | //asign wptr_in[2:0] = clr_ptrs ? 3'h1 : inc_wptr ? wptr[2:0] + 3'h1 : wptr[2:0]; | |
507 | mcu_algnbf_dp_increment_macro__width_4 m_wptr_inc ( | |
508 | .din ( {1'b0, wptr[2:0]} ), | |
509 | .cin ( inc_wptr ), | |
510 | .dout ( {unused3, mux_inc[2:0]} ), | |
511 | .cout ( unused2 )); | |
512 | mcu_algnbf_dp_and_macro__ports_2__width_3 m_wptr_in ( | |
513 | .dout ( {wptr_in[2:1], wptr_next[0]} ), | |
514 | .din0 ( {3{inv_clr_wr_ptr}} ), | |
515 | .din1 ( mux_inc[2:0] )); | |
516 | mcu_algnbf_dp_or_macro__ports_2__width_1 m_wptr_in_0 ( | |
517 | .dout ( wptr_in[0] ), | |
518 | .din0 ( clr_ptrs ), | |
519 | .din1 ( wptr_next[0] )); | |
520 | ||
521 | ////csret 11/15/2004 | |
522 | //asign dout[11:0] = | |
523 | // {12{rptr[2:0] == 0}} & buf0[11:0] | | |
524 | // {12{rptr[2:0] == 1}} & buf1[11:0] | | |
525 | // {12{rptr[2:0] == 2}} & buf2[11:0] | | |
526 | // {12{rptr[2:0] == 3}} & buf3[11:0] | | |
527 | // {12{rptr[2:0] == 4}} & buf4[11:0] | | |
528 | // {12{rptr[2:0] == 5}} & buf5[11:0] | | |
529 | // {12{rptr[2:0] == 6}} & buf6[11:0] | | |
530 | // {12{rptr[2:0] == 7}} & buf7[11:0]; | |
531 | mcu_algnbf_dp_inv_macro__width_3 m_inv_rptr ( | |
532 | .din ( rptr[2:0] ), | |
533 | .dout ( rptr_l[2:0] )); | |
534 | mcu_algnbf_dp_nor_macro__ports_3 m_dec_rptr_0 ( | |
535 | .dout ( rptr_sl0 ), | |
536 | .din0 ( rptr[0] ), | |
537 | .din1 ( rptr[1] ), | |
538 | .din2 ( rptr[2] )); | |
539 | mcu_algnbf_dp_nor_macro__ports_3 m_dec_rptr_1 ( | |
540 | .dout ( rptr_sl1 ), | |
541 | .din0 ( rptr_l[0] ), | |
542 | .din1 ( rptr[1] ), | |
543 | .din2 ( rptr[2] )); | |
544 | mcu_algnbf_dp_nor_macro__ports_3 m_dec_rptr_2 ( | |
545 | .dout ( rptr_sl2 ), | |
546 | .din0 ( rptr[0] ), | |
547 | .din1 ( rptr_l[1] ), | |
548 | .din2 ( rptr[2] )); | |
549 | mcu_algnbf_dp_nor_macro__ports_3 m_dec_rptr_3 ( | |
550 | .dout ( rptr_sl3 ), | |
551 | .din0 ( rptr_l[0] ), | |
552 | .din1 ( rptr_l[1] ), | |
553 | .din2 ( rptr[2] )); | |
554 | mcu_algnbf_dp_nor_macro__ports_3 m_dec_rptr_4 ( | |
555 | .dout ( rptr_sl4 ), | |
556 | .din0 ( rptr[0] ), | |
557 | .din1 ( rptr[1] ), | |
558 | .din2 ( rptr_l[2] )); | |
559 | mcu_algnbf_dp_nor_macro__ports_3 m_dec_rptr_5 ( | |
560 | .dout ( rptr_sl5 ), | |
561 | .din0 ( rptr_l[0] ), | |
562 | .din1 ( rptr[1] ), | |
563 | .din2 ( rptr_l[2] )); | |
564 | mcu_algnbf_dp_mux_macro__mux_aonpe__ports_6__stack_12r__width_12 m_mux_rptr ( | |
565 | .dout ( dout[11:0] ), | |
566 | .din0 ( buf0[11:0] ), | |
567 | .din1 ( buf1[11:0] ), | |
568 | .din2 ( buf2[11:0] ), | |
569 | .din3 ( buf3[11:0] ), | |
570 | .din4 ( buf4[11:0] ), | |
571 | .din5 ( buf5[11:0] ), | |
572 | .sel0 ( rptr_sl0 ), | |
573 | .sel1 ( rptr_sl1 ), | |
574 | .sel2 ( rptr_sl2 ), | |
575 | .sel3 ( rptr_sl3 ), | |
576 | .sel4 ( rptr_sl4 ), | |
577 | .sel5 ( rptr_sl5 )); | |
578 | ////csret 11/15/2004 | |
579 | //asign buf0_en = wptr[2:0] == 3'h0; | |
580 | mcu_algnbf_dp_inv_macro__width_3 m_inv_wptr ( | |
581 | .din(wptr[2:0]), | |
582 | .dout(wptr_l[2:0])); | |
583 | mcu_algnbf_dp_and_macro__ports_2__width_12 m_and_clr_din ( | |
584 | .din0 ( {12{inv_clr_ptrs}} ), | |
585 | .din1 ( din[11:0] ), | |
586 | .dout ( clr_din[11:0] ) ); | |
587 | ||
588 | mcu_algnbf_dp_nor_macro__ports_3 m_buf0_en ( | |
589 | .dout ( buf0_en ), | |
590 | .din0 ( wptr[0] ), | |
591 | .din1 ( wptr[1] ), | |
592 | .din2 ( wptr[2] ) ); | |
593 | ////csret 11/15/2004 | |
594 | //asign buf1_en = wptr[2:0] == 3'h1; | |
595 | mcu_algnbf_dp_nor_macro__ports_3 m_buf1_en ( | |
596 | .dout ( buf1_en ), | |
597 | .din0 ( wptr_l[0] ), | |
598 | .din1 ( wptr[1] ), | |
599 | .din2 ( wptr[2] ) | |
600 | ); | |
601 | ||
602 | ////csret 11/15/2004 | |
603 | //asign buf2_en = wptr[2:0] == 3'h2; | |
604 | mcu_algnbf_dp_nor_macro__ports_3 m_buf2_en ( | |
605 | .dout ( buf2_en ), | |
606 | .din0 ( wptr[0] ), | |
607 | .din1 ( wptr_l[1] ), | |
608 | .din2 ( wptr[2] ) | |
609 | ); | |
610 | ||
611 | ////csret 11/15/2004 | |
612 | //asign buf3_en = wptr[2:0] == 3'h3; | |
613 | mcu_algnbf_dp_nor_macro__ports_3 m_buf3_en ( | |
614 | .dout ( buf3_en ), | |
615 | .din0 ( wptr_l[0] ), | |
616 | .din1 ( wptr_l[1] ), | |
617 | .din2 ( wptr[2] ) ); | |
618 | ||
619 | ////csret 11/15/2004 | |
620 | //asign buf4_en = wptr[2:0] == 3'h4; | |
621 | mcu_algnbf_dp_nor_macro__ports_3 m_buf4_en ( | |
622 | .dout ( buf4_en ), | |
623 | .din0 ( wptr[0] ), | |
624 | .din1 ( wptr[1] ), | |
625 | .din2 ( wptr_l[2] ) | |
626 | ); | |
627 | ||
628 | ////csret 11/15/2004 | |
629 | //asign buf5_en = wptr[2:0] == 3'h5; | |
630 | mcu_algnbf_dp_nor_macro__ports_3 m_buf5_en ( | |
631 | .dout ( buf5_en ), | |
632 | .din0 ( wptr_l[0] ), | |
633 | .din1 ( wptr[1] ), | |
634 | .din2 ( wptr_l[2] ) ); | |
635 | ||
636 | // flops for fifo entries | |
637 | mcu_algnbf_dp_msff_macro__stack_12r__width_12 ff_buf0 ( | |
638 | .scan_in(ff_buf0_scanin), | |
639 | .scan_out(ff_buf0_scanout), | |
640 | .din(clr_din[11:0]), | |
641 | .dout(buf0[11:0]), | |
642 | .en(buf0_en), | |
643 | .clk(drl2clk), | |
644 | .se(se), | |
645 | .siclk(siclk), | |
646 | .soclk(soclk), | |
647 | .pce_ov(pce_ov), | |
648 | .stop(stop)); | |
649 | ||
650 | mcu_algnbf_dp_msff_macro__stack_12r__width_12 ff_buf1 ( | |
651 | .scan_in(ff_buf1_scanin), | |
652 | .scan_out(ff_buf1_scanout), | |
653 | .din(clr_din[11:0]), | |
654 | .dout(buf1[11:0]), | |
655 | .en(buf1_en), | |
656 | .clk(drl2clk), | |
657 | .se(se), | |
658 | .siclk(siclk), | |
659 | .soclk(soclk), | |
660 | .pce_ov(pce_ov), | |
661 | .stop(stop)); | |
662 | ||
663 | mcu_algnbf_dp_msff_macro__stack_12r__width_12 ff_buf2 ( | |
664 | .scan_in(ff_buf2_scanin), | |
665 | .scan_out(ff_buf2_scanout), | |
666 | .din(clr_din[11:0]), | |
667 | .dout(buf2[11:0]), | |
668 | .en(buf2_en), | |
669 | .clk(drl2clk), | |
670 | .se(se), | |
671 | .siclk(siclk), | |
672 | .soclk(soclk), | |
673 | .pce_ov(pce_ov), | |
674 | .stop(stop)); | |
675 | ||
676 | mcu_algnbf_dp_msff_macro__stack_12r__width_12 ff_buf3 ( | |
677 | .scan_in(ff_buf3_scanin), | |
678 | .scan_out(ff_buf3_scanout), | |
679 | .din(clr_din[11:0]), | |
680 | .dout(buf3[11:0]), | |
681 | .en(buf3_en), | |
682 | .clk(drl2clk), | |
683 | .se(se), | |
684 | .siclk(siclk), | |
685 | .soclk(soclk), | |
686 | .pce_ov(pce_ov), | |
687 | .stop(stop)); | |
688 | ||
689 | mcu_algnbf_dp_msff_macro__stack_12r__width_12 ff_buf4 ( | |
690 | .scan_in(ff_buf4_scanin), | |
691 | .scan_out(ff_buf4_scanout), | |
692 | .din(clr_din[11:0]), | |
693 | .dout(buf4[11:0]), | |
694 | .en(buf4_en), | |
695 | .clk(drl2clk), | |
696 | .se(se), | |
697 | .siclk(siclk), | |
698 | .soclk(soclk), | |
699 | .pce_ov(pce_ov), | |
700 | .stop(stop)); | |
701 | ||
702 | mcu_algnbf_dp_msff_macro__stack_12r__width_12 ff_buf5 ( | |
703 | .scan_in(ff_buf5_scanin), | |
704 | .scan_out(ff_buf5_scanout), | |
705 | .din(clr_din[11:0]), | |
706 | .dout(buf5[11:0]), | |
707 | .en(buf5_en), | |
708 | .clk(drl2clk), | |
709 | .se(se), | |
710 | .siclk(siclk), | |
711 | .soclk(soclk), | |
712 | .pce_ov(pce_ov), | |
713 | .stop(stop)); | |
714 | ||
715 | // flops for read and write pointers | |
716 | mcu_algnbf_dp_msff_macro__stack_12r__width_6 ff_rptr_wptr ( // FS:wmr_protect | |
717 | .scan_in(ff_rptr_wptr_wmr_scanin), | |
718 | .scan_out(ff_rptr_wptr_wmr_scanout), | |
719 | .siclk(aclk_wmr), | |
720 | .din({clr_rptr_in[2:0],wptr_in[2:0]}), | |
721 | .dout({rptr[2:0],wptr[2:0]}), | |
722 | .en(1'b1), | |
723 | .clk(drl2clk), | |
724 | .se(se), | |
725 | .soclk(soclk), | |
726 | .pce_ov(pce_ov), | |
727 | .stop(stop)); | |
728 | ||
729 | // fixscan start: | |
730 | assign ff_buf0_scanin = scan_in ; | |
731 | assign ff_buf1_scanin = ff_buf0_scanout ; | |
732 | assign ff_buf2_scanin = ff_buf1_scanout ; | |
733 | assign ff_buf3_scanin = ff_buf2_scanout ; | |
734 | assign ff_buf4_scanin = ff_buf3_scanout ; | |
735 | assign ff_buf5_scanin = ff_buf4_scanout ; | |
736 | assign scan_out = ff_buf5_scanout ; | |
737 | ||
738 | assign ff_rptr_wptr_wmr_scanin = wmr_scan_in ; | |
739 | assign wmr_scan_out = ff_rptr_wptr_wmr_scanout ; | |
740 | // fixscan end: | |
741 | endmodule | |
742 | ||
743 | ||
744 | // | |
745 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
746 | // | |
747 | // | |
748 | ||
749 | ||
750 | ||
751 | ||
752 | ||
753 | module mcu_algnbf_dp_cmp_macro__width_12 ( | |
754 | din0, | |
755 | din1, | |
756 | dout); | |
757 | input [11:0] din0; | |
758 | input [11:0] din1; | |
759 | output dout; | |
760 | ||
761 | ||
762 | ||
763 | ||
764 | ||
765 | ||
766 | cmp #(12) m0_0 ( | |
767 | .in0(din0[11:0]), | |
768 | .in1(din1[11:0]), | |
769 | .out(dout) | |
770 | ); | |
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | ||
781 | endmodule | |
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 | // | |
788 | // xor macro for ports = 2,3 | |
789 | // | |
790 | // | |
791 | ||
792 | ||
793 | ||
794 | ||
795 | ||
796 | module mcu_algnbf_dp_xor_macro__ports_3 ( | |
797 | din0, | |
798 | din1, | |
799 | din2, | |
800 | dout); | |
801 | input [0:0] din0; | |
802 | input [0:0] din1; | |
803 | input [0:0] din2; | |
804 | output [0:0] dout; | |
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | xor3 #(1) d0_0 ( | |
811 | .in0(din0[0:0]), | |
812 | .in1(din1[0:0]), | |
813 | .in2(din2[0:0]), | |
814 | .out(dout[0:0]) | |
815 | ); | |
816 | ||
817 | ||
818 | ||
819 | ||
820 | ||
821 | ||
822 | ||
823 | ||
824 | endmodule | |
825 | ||
826 | ||
827 | ||
828 | ||
829 | ||
830 | // | |
831 | // invert macro | |
832 | // | |
833 | // | |
834 | ||
835 | ||
836 | ||
837 | ||
838 | ||
839 | module mcu_algnbf_dp_inv_macro__width_2 ( | |
840 | din, | |
841 | dout); | |
842 | input [1:0] din; | |
843 | output [1:0] dout; | |
844 | ||
845 | ||
846 | ||
847 | ||
848 | ||
849 | ||
850 | inv #(2) d0_0 ( | |
851 | .in(din[1:0]), | |
852 | .out(dout[1:0]) | |
853 | ); | |
854 | ||
855 | ||
856 | ||
857 | ||
858 | ||
859 | ||
860 | ||
861 | ||
862 | ||
863 | endmodule | |
864 | ||
865 | ||
866 | ||
867 | ||
868 | ||
869 | // | |
870 | // and macro for ports = 2,3,4 | |
871 | // | |
872 | // | |
873 | ||
874 | ||
875 | ||
876 | ||
877 | ||
878 | module mcu_algnbf_dp_and_macro__width_1 ( | |
879 | din0, | |
880 | din1, | |
881 | dout); | |
882 | input [0:0] din0; | |
883 | input [0:0] din1; | |
884 | output [0:0] dout; | |
885 | ||
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | and2 #(1) d0_0 ( | |
892 | .in0(din0[0:0]), | |
893 | .in1(din1[0:0]), | |
894 | .out(dout[0:0]) | |
895 | ); | |
896 | ||
897 | ||
898 | ||
899 | ||
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | endmodule | |
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | // | |
912 | // and macro for ports = 2,3,4 | |
913 | // | |
914 | // | |
915 | ||
916 | ||
917 | ||
918 | ||
919 | ||
920 | module mcu_algnbf_dp_and_macro__width_2 ( | |
921 | din0, | |
922 | din1, | |
923 | dout); | |
924 | input [1:0] din0; | |
925 | input [1:0] din1; | |
926 | output [1:0] dout; | |
927 | ||
928 | ||
929 | ||
930 | ||
931 | ||
932 | ||
933 | and2 #(2) d0_0 ( | |
934 | .in0(din0[1:0]), | |
935 | .in1(din1[1:0]), | |
936 | .out(dout[1:0]) | |
937 | ); | |
938 | ||
939 | ||
940 | ||
941 | ||
942 | ||
943 | ||
944 | ||
945 | ||
946 | ||
947 | endmodule | |
948 | ||
949 | ||
950 | ||
951 | ||
952 | ||
953 | // | |
954 | // or macro for ports = 2,3 | |
955 | // | |
956 | // | |
957 | ||
958 | ||
959 | ||
960 | ||
961 | ||
962 | module mcu_algnbf_dp_or_macro__width_2 ( | |
963 | din0, | |
964 | din1, | |
965 | dout); | |
966 | input [1:0] din0; | |
967 | input [1:0] din1; | |
968 | output [1:0] dout; | |
969 | ||
970 | ||
971 | ||
972 | ||
973 | ||
974 | ||
975 | or2 #(2) d0_0 ( | |
976 | .in0(din0[1:0]), | |
977 | .in1(din1[1:0]), | |
978 | .out(dout[1:0]) | |
979 | ); | |
980 | ||
981 | ||
982 | ||
983 | ||
984 | ||
985 | ||
986 | ||
987 | ||
988 | ||
989 | endmodule | |
990 | ||
991 | ||
992 | ||
993 | ||
994 | ||
995 | // | |
996 | // increment macro | |
997 | // | |
998 | // | |
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | ||
1004 | module mcu_algnbf_dp_increment_macro__width_4 ( | |
1005 | din, | |
1006 | cin, | |
1007 | dout, | |
1008 | cout); | |
1009 | input [3:0] din; | |
1010 | input cin; | |
1011 | output [3:0] dout; | |
1012 | output cout; | |
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | incr #(4) m0_0 ( | |
1020 | .cin(cin), | |
1021 | .in(din[3:0]), | |
1022 | .out(dout[3:0]), | |
1023 | .cout(cout) | |
1024 | ); | |
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | ||
1032 | ||
1033 | ||
1034 | ||
1035 | ||
1036 | endmodule | |
1037 | ||
1038 | ||
1039 | ||
1040 | ||
1041 | ||
1042 | // | |
1043 | // invert macro | |
1044 | // | |
1045 | // | |
1046 | ||
1047 | ||
1048 | ||
1049 | ||
1050 | ||
1051 | module mcu_algnbf_dp_inv_macro__width_3 ( | |
1052 | din, | |
1053 | dout); | |
1054 | input [2:0] din; | |
1055 | output [2:0] dout; | |
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | ||
1061 | ||
1062 | inv #(3) d0_0 ( | |
1063 | .in(din[2:0]), | |
1064 | .out(dout[2:0]) | |
1065 | ); | |
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | endmodule | |
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | // | |
1082 | // and macro for ports = 2,3,4 | |
1083 | // | |
1084 | // | |
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | module mcu_algnbf_dp_and_macro__ports_2__width_3 ( | |
1091 | din0, | |
1092 | din1, | |
1093 | dout); | |
1094 | input [2:0] din0; | |
1095 | input [2:0] din1; | |
1096 | output [2:0] dout; | |
1097 | ||
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | and2 #(3) d0_0 ( | |
1104 | .in0(din0[2:0]), | |
1105 | .in1(din1[2:0]), | |
1106 | .out(dout[2:0]) | |
1107 | ); | |
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | ||
1117 | endmodule | |
1118 | ||
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | // | |
1124 | // or macro for ports = 2,3 | |
1125 | // | |
1126 | // | |
1127 | ||
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | module mcu_algnbf_dp_or_macro__ports_2__width_1 ( | |
1133 | din0, | |
1134 | din1, | |
1135 | dout); | |
1136 | input [0:0] din0; | |
1137 | input [0:0] din1; | |
1138 | output [0:0] dout; | |
1139 | ||
1140 | ||
1141 | ||
1142 | ||
1143 | ||
1144 | ||
1145 | or2 #(1) d0_0 ( | |
1146 | .in0(din0[0:0]), | |
1147 | .in1(din1[0:0]), | |
1148 | .out(dout[0:0]) | |
1149 | ); | |
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | ||
1159 | endmodule | |
1160 | ||
1161 | ||
1162 | ||
1163 | ||
1164 | ||
1165 | // | |
1166 | // nor macro for ports = 2,3 | |
1167 | // | |
1168 | // | |
1169 | ||
1170 | ||
1171 | ||
1172 | ||
1173 | ||
1174 | module mcu_algnbf_dp_nor_macro__ports_3 ( | |
1175 | din0, | |
1176 | din1, | |
1177 | din2, | |
1178 | dout); | |
1179 | input [0:0] din0; | |
1180 | input [0:0] din1; | |
1181 | input [0:0] din2; | |
1182 | output [0:0] dout; | |
1183 | ||
1184 | ||
1185 | ||
1186 | ||
1187 | ||
1188 | ||
1189 | nor3 #(1) d0_0 ( | |
1190 | .in0(din0[0:0]), | |
1191 | .in1(din1[0:0]), | |
1192 | .in2(din2[0:0]), | |
1193 | .out(dout[0:0]) | |
1194 | ); | |
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | endmodule | |
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1209 | // also for pass-gate with decoder | |
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | // any PARAMS parms go into naming of macro | |
1216 | ||
1217 | module mcu_algnbf_dp_mux_macro__mux_aonpe__ports_6__stack_12r__width_12 ( | |
1218 | din0, | |
1219 | sel0, | |
1220 | din1, | |
1221 | sel1, | |
1222 | din2, | |
1223 | sel2, | |
1224 | din3, | |
1225 | sel3, | |
1226 | din4, | |
1227 | sel4, | |
1228 | din5, | |
1229 | sel5, | |
1230 | dout); | |
1231 | wire buffout0; | |
1232 | wire buffout1; | |
1233 | wire buffout2; | |
1234 | wire buffout3; | |
1235 | wire buffout4; | |
1236 | wire buffout5; | |
1237 | ||
1238 | input [11:0] din0; | |
1239 | input sel0; | |
1240 | input [11:0] din1; | |
1241 | input sel1; | |
1242 | input [11:0] din2; | |
1243 | input sel2; | |
1244 | input [11:0] din3; | |
1245 | input sel3; | |
1246 | input [11:0] din4; | |
1247 | input sel4; | |
1248 | input [11:0] din5; | |
1249 | input sel5; | |
1250 | output [11:0] dout; | |
1251 | ||
1252 | ||
1253 | ||
1254 | ||
1255 | ||
1256 | cl_dp1_muxbuff6_8x c0_0 ( | |
1257 | .in0(sel0), | |
1258 | .in1(sel1), | |
1259 | .in2(sel2), | |
1260 | .in3(sel3), | |
1261 | .in4(sel4), | |
1262 | .in5(sel5), | |
1263 | .out0(buffout0), | |
1264 | .out1(buffout1), | |
1265 | .out2(buffout2), | |
1266 | .out3(buffout3), | |
1267 | .out4(buffout4), | |
1268 | .out5(buffout5) | |
1269 | ); | |
1270 | mux6s #(12) d0_0 ( | |
1271 | .sel0(buffout0), | |
1272 | .sel1(buffout1), | |
1273 | .sel2(buffout2), | |
1274 | .sel3(buffout3), | |
1275 | .sel4(buffout4), | |
1276 | .sel5(buffout5), | |
1277 | .in0(din0[11:0]), | |
1278 | .in1(din1[11:0]), | |
1279 | .in2(din2[11:0]), | |
1280 | .in3(din3[11:0]), | |
1281 | .in4(din4[11:0]), | |
1282 | .in5(din5[11:0]), | |
1283 | .dout(dout[11:0]) | |
1284 | ); | |
1285 | ||
1286 | ||
1287 | ||
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | endmodule | |
1299 | ||
1300 | ||
1301 | // | |
1302 | // and macro for ports = 2,3,4 | |
1303 | // | |
1304 | // | |
1305 | ||
1306 | ||
1307 | ||
1308 | ||
1309 | ||
1310 | module mcu_algnbf_dp_and_macro__ports_2__width_12 ( | |
1311 | din0, | |
1312 | din1, | |
1313 | dout); | |
1314 | input [11:0] din0; | |
1315 | input [11:0] din1; | |
1316 | output [11:0] dout; | |
1317 | ||
1318 | ||
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | and2 #(12) d0_0 ( | |
1324 | .in0(din0[11:0]), | |
1325 | .in1(din1[11:0]), | |
1326 | .out(dout[11:0]) | |
1327 | ); | |
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | endmodule | |
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | // any PARAMS parms go into naming of macro | |
1348 | ||
1349 | module mcu_algnbf_dp_msff_macro__stack_12r__width_12 ( | |
1350 | din, | |
1351 | clk, | |
1352 | en, | |
1353 | se, | |
1354 | scan_in, | |
1355 | siclk, | |
1356 | soclk, | |
1357 | pce_ov, | |
1358 | stop, | |
1359 | dout, | |
1360 | scan_out); | |
1361 | wire l1clk; | |
1362 | wire siclk_out; | |
1363 | wire soclk_out; | |
1364 | wire [10:0] so; | |
1365 | ||
1366 | input [11:0] din; | |
1367 | ||
1368 | ||
1369 | input clk; | |
1370 | input en; | |
1371 | input se; | |
1372 | input scan_in; | |
1373 | input siclk; | |
1374 | input soclk; | |
1375 | input pce_ov; | |
1376 | input stop; | |
1377 | ||
1378 | ||
1379 | ||
1380 | output [11:0] dout; | |
1381 | ||
1382 | ||
1383 | output scan_out; | |
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | cl_dp1_l1hdr_8x c0_0 ( | |
1389 | .l2clk(clk), | |
1390 | .pce(en), | |
1391 | .aclk(siclk), | |
1392 | .bclk(soclk), | |
1393 | .l1clk(l1clk), | |
1394 | .se(se), | |
1395 | .pce_ov(pce_ov), | |
1396 | .stop(stop), | |
1397 | .siclk_out(siclk_out), | |
1398 | .soclk_out(soclk_out) | |
1399 | ); | |
1400 | dff #(12) d0_0 ( | |
1401 | .l1clk(l1clk), | |
1402 | .siclk(siclk_out), | |
1403 | .soclk(soclk_out), | |
1404 | .d(din[11:0]), | |
1405 | .si({scan_in,so[10:0]}), | |
1406 | .so({so[10:0],scan_out}), | |
1407 | .q(dout[11:0]) | |
1408 | ); | |
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | ||
1429 | endmodule | |
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | ||
1435 | ||
1436 | ||
1437 | ||
1438 | ||
1439 | ||
1440 | ||
1441 | ||
1442 | ||
1443 | // any PARAMS parms go into naming of macro | |
1444 | ||
1445 | module mcu_algnbf_dp_msff_macro__stack_12r__width_6 ( | |
1446 | din, | |
1447 | clk, | |
1448 | en, | |
1449 | se, | |
1450 | scan_in, | |
1451 | siclk, | |
1452 | soclk, | |
1453 | pce_ov, | |
1454 | stop, | |
1455 | dout, | |
1456 | scan_out); | |
1457 | wire l1clk; | |
1458 | wire siclk_out; | |
1459 | wire soclk_out; | |
1460 | wire [4:0] so; | |
1461 | ||
1462 | input [5:0] din; | |
1463 | ||
1464 | ||
1465 | input clk; | |
1466 | input en; | |
1467 | input se; | |
1468 | input scan_in; | |
1469 | input siclk; | |
1470 | input soclk; | |
1471 | input pce_ov; | |
1472 | input stop; | |
1473 | ||
1474 | ||
1475 | ||
1476 | output [5:0] dout; | |
1477 | ||
1478 | ||
1479 | output scan_out; | |
1480 | ||
1481 | ||
1482 | ||
1483 | ||
1484 | cl_dp1_l1hdr_8x c0_0 ( | |
1485 | .l2clk(clk), | |
1486 | .pce(en), | |
1487 | .aclk(siclk), | |
1488 | .bclk(soclk), | |
1489 | .l1clk(l1clk), | |
1490 | .se(se), | |
1491 | .pce_ov(pce_ov), | |
1492 | .stop(stop), | |
1493 | .siclk_out(siclk_out), | |
1494 | .soclk_out(soclk_out) | |
1495 | ); | |
1496 | dff #(6) d0_0 ( | |
1497 | .l1clk(l1clk), | |
1498 | .siclk(siclk_out), | |
1499 | .soclk(soclk_out), | |
1500 | .d(din[5:0]), | |
1501 | .si({scan_in,so[4:0]}), | |
1502 | .so({so[4:0],scan_out}), | |
1503 | .q(dout[5:0]) | |
1504 | ); | |
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | ||
1511 | ||
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | endmodule | |
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | ||
1533 |