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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_crcs_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_crcs_ctl ( | |
36 | crcsc_crc, | |
37 | crcscf_crc, | |
38 | crcsd0_crc, | |
39 | crcsdf0_crc, | |
40 | crcsd1_crc, | |
41 | crcsdf1_crc, | |
42 | bc, | |
43 | bd0, | |
44 | bd1, | |
45 | drl2clk, | |
46 | scan_in, | |
47 | scan_out, | |
48 | tcu_pce_ov, | |
49 | tcu_aclk, | |
50 | tcu_bclk, | |
51 | tcu_scan_en); | |
52 | wire pce_ov; | |
53 | wire siclk; | |
54 | wire soclk; | |
55 | wire se; | |
56 | wire l1clk; | |
57 | wire spares_scanin; | |
58 | wire spares_scanout; | |
59 | ||
60 | ||
61 | output [13:0] crcsc_crc; | |
62 | output [9:0] crcscf_crc; | |
63 | ||
64 | output [21:0] crcsd0_crc; | |
65 | output [9:0] crcsdf0_crc; | |
66 | ||
67 | output [21:0] crcsd1_crc; | |
68 | output [9:0] crcsdf1_crc; | |
69 | ||
70 | input [25:0] bc; | |
71 | input [71:0] bd0; | |
72 | input [71:0] bd1; | |
73 | ||
74 | input drl2clk; | |
75 | input scan_in; | |
76 | output scan_out; | |
77 | input tcu_pce_ov; | |
78 | input tcu_aclk; | |
79 | input tcu_bclk; | |
80 | input tcu_scan_en; | |
81 | ||
82 | // Code | |
83 | assign pce_ov = tcu_pce_ov; | |
84 | assign siclk = tcu_aclk; | |
85 | assign soclk = tcu_bclk; | |
86 | assign se = tcu_scan_en; | |
87 | ||
88 | // 0in set_clock drl2clk -default | |
89 | mcu_crcs_ctl_l1clkhdr_ctl_macro clkgen ( | |
90 | .l2clk(drl2clk), | |
91 | .l1en (1'b1 ), | |
92 | .stop(1'b0), | |
93 | .l1clk(l1clk), | |
94 | .pce_ov(pce_ov), | |
95 | .se(se)); | |
96 | ||
97 | mcu_crcsc_ctl u_crcsc ( | |
98 | .in(bc[25:0]), | |
99 | .crc(crcsc_crc[13:0]) | |
100 | ); | |
101 | ||
102 | mcu_crcscf_ctl u_crcscf ( | |
103 | .in(bc[25:0]), | |
104 | .crc(crcscf_crc[9:0]) | |
105 | ); | |
106 | ||
107 | mcu_crcsd_ctl u_crcsd0 ( | |
108 | .in(bd0[71:0]), | |
109 | .crc(crcsd0_crc[21:0]) | |
110 | ); | |
111 | ||
112 | mcu_crcsdf_ctl u_crcsdf0 ( | |
113 | .in(bd0[71:0]), | |
114 | .crc(crcsdf0_crc[9:0]) | |
115 | ); | |
116 | ||
117 | mcu_crcsd_ctl u_crcsd1 ( | |
118 | .in(bd1[71:0]), | |
119 | .crc(crcsd1_crc[21:0]) | |
120 | ); | |
121 | ||
122 | mcu_crcsdf_ctl u_crcsdf1 ( | |
123 | .in(bd1[71:0]), | |
124 | .crc(crcsdf1_crc[9:0]) | |
125 | ); | |
126 | ||
127 | mcu_crcs_ctl_spare_ctl_macro__num_1 spares ( | |
128 | .scan_in(spares_scanin), | |
129 | .scan_out(spares_scanout), | |
130 | .l1clk(l1clk), | |
131 | .siclk(siclk), | |
132 | .soclk(soclk) | |
133 | ); | |
134 | ||
135 | // fixscan start: | |
136 | assign spares_scanin = scan_in ; | |
137 | assign scan_out = spares_scanout ; | |
138 | // fixscan end: | |
139 | endmodule | |
140 | ||
141 | ||
142 | ||
143 | ||
144 | ||
145 | ||
146 | // any PARAMS parms go into naming of macro | |
147 | ||
148 | module mcu_crcs_ctl_l1clkhdr_ctl_macro ( | |
149 | l2clk, | |
150 | l1en, | |
151 | pce_ov, | |
152 | stop, | |
153 | se, | |
154 | l1clk); | |
155 | ||
156 | ||
157 | input l2clk; | |
158 | input l1en; | |
159 | input pce_ov; | |
160 | input stop; | |
161 | input se; | |
162 | output l1clk; | |
163 | ||
164 | ||
165 | ||
166 | ||
167 | ||
168 | cl_sc1_l1hdr_8x c_0 ( | |
169 | ||
170 | ||
171 | .l2clk(l2clk), | |
172 | .pce(l1en), | |
173 | .l1clk(l1clk), | |
174 | .se(se), | |
175 | .pce_ov(pce_ov), | |
176 | .stop(stop) | |
177 | ); | |
178 | ||
179 | endmodule | |
180 | ||
181 | ||
182 | ||
183 | // Description: Spare gate macro for control blocks | |
184 | // | |
185 | // Param num controls the number of times the macro is added | |
186 | // flops=0 can be used to use only combination spare logic | |
187 | ||
188 | ||
189 | module mcu_crcs_ctl_spare_ctl_macro__num_1 ( | |
190 | l1clk, | |
191 | scan_in, | |
192 | siclk, | |
193 | soclk, | |
194 | scan_out); | |
195 | wire si_0; | |
196 | wire so_0; | |
197 | wire spare0_flop_unused; | |
198 | wire spare0_buf_32x_unused; | |
199 | wire spare0_nand3_8x_unused; | |
200 | wire spare0_inv_8x_unused; | |
201 | wire spare0_aoi22_4x_unused; | |
202 | wire spare0_buf_8x_unused; | |
203 | wire spare0_oai22_4x_unused; | |
204 | wire spare0_inv_16x_unused; | |
205 | wire spare0_nand2_16x_unused; | |
206 | wire spare0_nor3_4x_unused; | |
207 | wire spare0_nand2_8x_unused; | |
208 | wire spare0_buf_16x_unused; | |
209 | wire spare0_nor2_16x_unused; | |
210 | wire spare0_inv_32x_unused; | |
211 | ||
212 | ||
213 | input l1clk; | |
214 | input scan_in; | |
215 | input siclk; | |
216 | input soclk; | |
217 | output scan_out; | |
218 | ||
219 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
220 | .siclk(siclk), | |
221 | .soclk(soclk), | |
222 | .si(si_0), | |
223 | .so(so_0), | |
224 | .d(1'b0), | |
225 | .q(spare0_flop_unused)); | |
226 | assign si_0 = scan_in; | |
227 | ||
228 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
229 | .out(spare0_buf_32x_unused)); | |
230 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
231 | .in1(1'b1), | |
232 | .in2(1'b1), | |
233 | .out(spare0_nand3_8x_unused)); | |
234 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
235 | .out(spare0_inv_8x_unused)); | |
236 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
237 | .in01(1'b1), | |
238 | .in10(1'b1), | |
239 | .in11(1'b1), | |
240 | .out(spare0_aoi22_4x_unused)); | |
241 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
242 | .out(spare0_buf_8x_unused)); | |
243 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
244 | .in01(1'b1), | |
245 | .in10(1'b1), | |
246 | .in11(1'b1), | |
247 | .out(spare0_oai22_4x_unused)); | |
248 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
249 | .out(spare0_inv_16x_unused)); | |
250 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
251 | .in1(1'b1), | |
252 | .out(spare0_nand2_16x_unused)); | |
253 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
254 | .in1(1'b0), | |
255 | .in2(1'b0), | |
256 | .out(spare0_nor3_4x_unused)); | |
257 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
258 | .in1(1'b1), | |
259 | .out(spare0_nand2_8x_unused)); | |
260 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
261 | .out(spare0_buf_16x_unused)); | |
262 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
263 | .in1(1'b0), | |
264 | .out(spare0_nor2_16x_unused)); | |
265 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
266 | .out(spare0_inv_32x_unused)); | |
267 | assign scan_out = so_0; | |
268 | ||
269 | ||
270 | ||
271 | endmodule | |
272 |