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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_drif_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define DRIF_MCU_STATE_00 5'd0 | |
36 | `define DRIF_MCU_STATE_01 5'd1 | |
37 | `define DRIF_MCU_STATE_02 5'd2 | |
38 | `define DRIF_MCU_STATE_03 5'd3 | |
39 | `define DRIF_MCU_STATE_04 5'd4 | |
40 | `define DRIF_MCU_STATE_05 5'd5 | |
41 | `define DRIF_MCU_STATE_06 5'd6 | |
42 | `define DRIF_MCU_STATE_07 5'd7 | |
43 | `define DRIF_MCU_STATE_08 5'd8 | |
44 | `define DRIF_MCU_STATE_09 5'd9 | |
45 | `define DRIF_MCU_STATE_10 5'd10 | |
46 | `define DRIF_MCU_STATE_11 5'd11 | |
47 | `define DRIF_MCU_STATE_12 5'd12 | |
48 | `define DRIF_MCU_STATE_13 5'd13 | |
49 | `define DRIF_MCU_STATE_14 5'd14 | |
50 | `define DRIF_MCU_STATE_15 5'd15 | |
51 | `define DRIF_MCU_STATE_16 5'd16 | |
52 | `define DRIF_MCU_STATE_17 5'd17 | |
53 | `define DRIF_MCU_STATE_18 5'd18 | |
54 | `define DRIF_MCU_STATE_19 5'd19 | |
55 | `define DRIF_MCU_STATE_20 5'd20 | |
56 | `define DRIF_MCU_STATE_21 5'd21 | |
57 | `define DRIF_MCU_STATE_22 5'd22 | |
58 | `define DRIF_MCU_STATE_23 5'd23 | |
59 | `define DRIF_MCU_STATE_24 5'd24 | |
60 | `define DRIF_MCU_STATE_25 5'd25 | |
61 | `define DRIF_MCU_STATE_26 5'd26 | |
62 | ||
63 | `define DRIF_MCU_STATE_MAX 4 | |
64 | `define DRIF_MCU_STATE_WIDTH 5 | |
65 | ||
66 | // | |
67 | // UCB Packet Type | |
68 | // =============== | |
69 | // | |
70 | `define UCB_READ_NACK 4'b0000 // ack/nack types | |
71 | `define UCB_READ_ACK 4'b0001 | |
72 | `define UCB_WRITE_ACK 4'b0010 | |
73 | `define UCB_IFILL_ACK 4'b0011 | |
74 | `define UCB_IFILL_NACK 4'b0111 | |
75 | ||
76 | `define UCB_READ_REQ 4'b0100 // req types | |
77 | `define UCB_WRITE_REQ 4'b0101 | |
78 | `define UCB_IFILL_REQ 4'b0110 | |
79 | ||
80 | `define UCB_INT 4'b1000 // plain interrupt | |
81 | `define UCB_INT_VEC 4'b1100 // interrupt with vector | |
82 | `define UCB_RESET_VEC 4'b1101 // reset with vector | |
83 | `define UCB_IDLE_VEC 4'b1110 // idle with vector | |
84 | `define UCB_RESUME_VEC 4'b1111 // resume with vector | |
85 | ||
86 | ||
87 | // | |
88 | // UCB Data Packet Format | |
89 | // ====================== | |
90 | // | |
91 | `define UCB_NOPAY_PKT_WIDTH 64 // packet without payload | |
92 | `define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload | |
93 | `define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload | |
94 | ||
95 | `define UCB_DATA_EXT_HI 191 // (64) extended data | |
96 | `define UCB_DATA_EXT_LO 128 | |
97 | `define UCB_DATA_HI 127 // (64) data | |
98 | `define UCB_DATA_LO 64 | |
99 | `define UCB_RSV_HI 63 // (9) reserved bits | |
100 | `define UCB_RSV_LO 55 | |
101 | `define UCB_ADDR_HI 54 // (40) bit address | |
102 | `define UCB_ADDR_LO 15 | |
103 | `define UCB_SIZE_HI 14 // (3) request size | |
104 | `define UCB_SIZE_LO 12 | |
105 | `define UCB_BUF_HI 11 // (2) buffer ID | |
106 | `define UCB_BUF_LO 10 | |
107 | `define UCB_THR_HI 9 // (6) cpu/thread ID | |
108 | `define UCB_THR_LO 4 | |
109 | `define UCB_PKT_HI 3 // (4) packet type | |
110 | `define UCB_PKT_LO 0 | |
111 | ||
112 | `define UCB_DATA_EXT_WIDTH 64 | |
113 | `define UCB_DATA_WIDTH 64 | |
114 | `define UCB_RSV_WIDTH 9 | |
115 | `define UCB_ADDR_WIDTH 40 | |
116 | `define UCB_SIZE_WIDTH 3 | |
117 | `define UCB_BUF_WIDTH 2 | |
118 | `define UCB_THR_WIDTH 6 | |
119 | `define UCB_PKT_WIDTH 4 | |
120 | ||
121 | // Size encoding for the UCB_SIZE_HI/LO field | |
122 | // 000 - byte | |
123 | // 001 - half-word | |
124 | // 010 - word | |
125 | // 011 - double-word | |
126 | `define UCB_SIZE_1B 3'b000 | |
127 | `define UCB_SIZE_2B 3'b001 | |
128 | `define UCB_SIZE_4B 3'b010 | |
129 | `define UCB_SIZE_8B 3'b011 | |
130 | `define UCB_SIZE_16B 3'b100 | |
131 | ||
132 | ||
133 | // | |
134 | // UCB Interrupt Packet Format | |
135 | // =========================== | |
136 | // | |
137 | `define UCB_INT_PKT_WIDTH 64 | |
138 | ||
139 | `define UCB_INT_RSV_HI 63 // (7) reserved bits | |
140 | `define UCB_INT_RSV_LO 57 | |
141 | `define UCB_INT_VEC_HI 56 // (6) interrupt vector | |
142 | `define UCB_INT_VEC_LO 51 | |
143 | `define UCB_INT_STAT_HI 50 // (32) interrupt status | |
144 | `define UCB_INT_STAT_LO 19 | |
145 | `define UCB_INT_DEV_HI 18 // (9) device ID | |
146 | `define UCB_INT_DEV_LO 10 | |
147 | //`define UCB_THR_HI 9 // (6) cpu/thread ID shared with | |
148 | //`define UCB_THR_LO 4 data packet format | |
149 | //`define UCB_PKT_HI 3 // (4) packet type shared with | |
150 | //`define UCB_PKT_LO 0 // data packet format | |
151 | ||
152 | `define UCB_INT_RSV_WIDTH 7 | |
153 | `define UCB_INT_VEC_WIDTH 6 | |
154 | `define UCB_INT_STAT_WIDTH 32 | |
155 | `define UCB_INT_DEV_WIDTH 9 | |
156 | ||
157 | ||
158 | `define MCU_CAS_BIT2_SEL_PA10 4'h1 | |
159 | `define MCU_CAS_BIT2_SEL_PA32 4'h2 | |
160 | `define MCU_CAS_BIT2_SEL_PA33 4'h4 | |
161 | `define MCU_CAS_BIT2_SEL_PA34 4'h8 | |
162 | ||
163 | `define MCU_CAS_BIT3_SEL_PA11 4'h1 | |
164 | `define MCU_CAS_BIT3_SEL_PA33 4'h2 | |
165 | `define MCU_CAS_BIT3_SEL_PA34 4'h4 | |
166 | `define MCU_CAS_BIT3_SEL_PA35 4'h8 | |
167 | ||
168 | `define MCU_CAS_BIT4_SEL_PA12 3'h1 | |
169 | `define MCU_CAS_BIT4_SEL_PA35 3'h2 | |
170 | `define MCU_CAS_BIT4_SEL_PA36 3'h4 | |
171 | ||
172 | `define MCU_DIMMHI_SEL_ZERO 6'h01 | |
173 | `define MCU_DIMMHI_SEL_PA32 6'h02 | |
174 | `define MCU_DIMMHI_SEL_PA33 6'h04 | |
175 | `define MCU_DIMMHI_SEL_PA34 6'h08 | |
176 | `define MCU_DIMMHI_SEL_PA35 6'h10 | |
177 | `define MCU_DIMMHI_SEL_PA36 6'h20 | |
178 | ||
179 | `define MCU_DIMMLO_SEL_ZERO 4'h1 | |
180 | `define MCU_DIMMLO_SEL_PA10 4'h2 | |
181 | `define MCU_DIMMLO_SEL_PA11 4'h4 | |
182 | `define MCU_DIMMLO_SEL_PA12 4'h8 | |
183 | ||
184 | `define MCU_RANK_SEL_ZERO 7'h01 | |
185 | `define MCU_RANK_SEL_PA32 7'h02 | |
186 | `define MCU_RANK_SEL_PA33 7'h04 | |
187 | `define MCU_RANK_SEL_PA34 7'h08 | |
188 | `define MCU_RANK_SEL_PA35 7'h10 | |
189 | `define MCU_RANK_SEL_PA10 7'h20 | |
190 | `define MCU_RANK_SEL_PA11 7'h40 | |
191 | ||
192 | `define MCU_ADDR_ERR_SEL_39_32 6'h01 | |
193 | `define MCU_ADDR_ERR_SEL_39_33 6'h02 | |
194 | `define MCU_ADDR_ERR_SEL_39_34 6'h04 | |
195 | `define MCU_ADDR_ERR_SEL_39_35 6'h08 | |
196 | `define MCU_ADDR_ERR_SEL_39_36 6'h10 | |
197 | `define MCU_ADDR_ERR_SEL_39_37 6'h20 | |
198 | ||
199 | `define DRIF_ERR_IDLE 0 | |
200 | `define DRIF_ERR_IDLE_ST 5'h1 | |
201 | `define DRIF_ERR_READ0 1 | |
202 | `define DRIF_ERR_READ0_ST 5'h2 | |
203 | `define DRIF_ERR_WRITE 2 | |
204 | `define DRIF_ERR_WRITE_ST 5'h4 | |
205 | `define DRIF_ERR_READ1 3 | |
206 | `define DRIF_ERR_READ1_ST 5'h8 | |
207 | `define DRIF_ERR_CRC_FR 4 | |
208 | `define DRIF_ERR_CRC_FR_ST 5'h10 | |
209 | ||
210 | `define MCU_WDQ_RF_DATA_WIDTH 72 | |
211 | `define MCU_WDQ_RF_ADDR_WIDTH 5 | |
212 | `define MCU_WDQ_RF_DEPTH 32 | |
213 | ||
214 | // FBDIMM header defines | |
215 | `define FBD_TS0_HDR 12'hbfe | |
216 | `define FBD_TS1_HDR 12'hffe | |
217 | `define FBD_TS2_HDR 12'h7fe | |
218 | `define FBD_TS3_HDR 12'h3fe | |
219 | ||
220 | // MCU FBDIMM Channel commands | |
221 | `define FBD_DRAM_CMD_NOP 3'h0 | |
222 | `define FBD_DRAM_CMD_OTHER 3'h1 | |
223 | `define FBD_DRAM_CMD_RD 3'h2 | |
224 | `define FBD_DRAM_CMD_WR 3'h3 | |
225 | `define FBD_DRAM_CMD_ACT 3'h4 | |
226 | `define FBD_DRAM_CMD_WDATA 3'h5 | |
227 | ||
228 | `define FBD_DRAM_CMD_OTHER_REF 3'h5 | |
229 | `define FBD_DRAM_CMD_OTHER_SRE 3'h4 | |
230 | `define FBD_DRAM_CMD_OTHER_PDE 3'h2 | |
231 | `define FBD_DRAM_CMD_OTHER_SRPDX 3'h3 | |
232 | ||
233 | `define FBD_CHNL_CMD_NOP 2'h0 | |
234 | `define FBD_CHNL_CMD_SYNC 2'h1 | |
235 | `define FBD_CHNL_CMD_SCRST 2'h2 | |
236 | ||
237 | `define FBDIC_ERR_IDLE_ST 7'h01 | |
238 | `define FBDIC_ERR_IDLE 0 | |
239 | ||
240 | `define FBDIC_ERR_STS_ST 7'h02 | |
241 | `define FBDIC_ERR_STS 1 | |
242 | ||
243 | `define FBDIC_ERR_SCRST_ST 7'h04 | |
244 | `define FBDIC_ERR_SCRST 2 | |
245 | ||
246 | `define FBDIC_ERR_SCRST_STS_ST 7'h08 | |
247 | `define FBDIC_ERR_SCRST_STS 3 | |
248 | ||
249 | `define FBDIC_ERR_STS2_ST 7'h10 | |
250 | `define FBDIC_ERR_STS2 4 | |
251 | ||
252 | `define FBDIC_ERR_FASTRST_ST 7'h20 | |
253 | `define FBDIC_ERR_FASTRST 5 | |
254 | ||
255 | `define FBDIC_ERR_FASTRST_STS_ST 7'h40 | |
256 | `define FBDIC_ERR_FASTRST_STS 6 | |
257 | ||
258 | ||
259 | // IBIST DEFINITION | |
260 | ||
261 | `define L_2_0 12'h555 | |
262 | `define L_2_1 12'h555 | |
263 | `define L_4_0 12'h333 | |
264 | `define L_4_1 12'h333 | |
265 | `define L_6_0 12'h1c7 | |
266 | `define L_6_1 12'h1c7 | |
267 | `define L_8_0 12'h0f0 | |
268 | `define L_8_1 12'hf0f | |
269 | `define L_24_0 12'h000 | |
270 | `define L_24_1 12'hfff | |
271 | ||
272 | `define idle 4'h0 | |
273 | ||
274 | `define error_0 4'h1 | |
275 | `define error_1 4'h2 | |
276 | ||
277 | `define start1_0 4'h3 | |
278 | `define start1_1 4'h4 | |
279 | `define start2_0 4'h5 | |
280 | `define start2_1 4'h6 | |
281 | ||
282 | `define pat1_0 4'h7 | |
283 | `define pat1_1 4'h8 | |
284 | ||
285 | `define clkpat_0 4'h9 | |
286 | `define clkpat_1 4'ha | |
287 | ||
288 | `define const_0 4'hb | |
289 | `define const_1 4'hc | |
290 | ||
291 | `define stop1_0 4'h1 | |
292 | `define stop1_1 4'h2 | |
293 | ||
294 | `define stop2_0 4'hd | |
295 | `define stop2_1 4'he | |
296 | `define error 4'hf | |
297 | ||
298 | `define IBTX_STATE_IDLE 0 | |
299 | `define IBTX_STATE_PATT 1 | |
300 | `define IBTX_STATE_MODN 2 | |
301 | `define IBTX_STATE_CONST 3 | |
302 | ||
303 | `define IBRX_STATE_IDLE 0 | |
304 | `define IBRX_STATE_PATT 1 | |
305 | `define IBRX_STATE_MODN 2 | |
306 | `define IBRX_STATE_CONST 3 | |
307 | ||
308 | ||
309 | ||
310 | module mcu_drif_ctl ( | |
311 | drif_fail_over_mode, | |
312 | drif_fail_over_mask, | |
313 | drif_fail_over_mask_l, | |
314 | drq0_rdq_free, | |
315 | drq1_rdq_free, | |
316 | woq0_wdq_entry_free, | |
317 | woq1_wdq_entry_free, | |
318 | drif_num_dimms, | |
319 | drif_addr_bank_low_sel, | |
320 | drif_mem_type, | |
321 | drif_stacked_dimm, | |
322 | drif_single_channel_mode, | |
323 | drif_branch_disabled, | |
324 | drif_wdata_sel, | |
325 | drif_rdata_ack_vld, | |
326 | drif_rdata_nack_vld, | |
327 | drif_rdata_data, | |
328 | drif_err_inj_enable, | |
329 | drif_err_mask_reg, | |
330 | drif_send_info_val, | |
331 | drif_send_info, | |
332 | drif0_wdq_rd, | |
333 | drif1_wdq_rd, | |
334 | drif_wdq_radr, | |
335 | drif_rascas_adr_sel, | |
336 | drif_rascas_wr1_adr_sel, | |
337 | drif_rascas_wr2_adr_sel, | |
338 | drif_scrub_addr, | |
339 | drq0_rd_adr_queue7_en, | |
340 | drq0_rd_adr_queue6_en, | |
341 | drq0_rd_adr_queue5_en, | |
342 | drq0_rd_adr_queue4_en, | |
343 | drq0_rd_adr_queue3_en, | |
344 | drq0_rd_adr_queue2_en, | |
345 | drq0_rd_adr_queue1_en, | |
346 | drq0_rd_adr_queue0_en, | |
347 | drq1_rd_adr_queue7_en, | |
348 | drq1_rd_adr_queue6_en, | |
349 | drq1_rd_adr_queue5_en, | |
350 | drq1_rd_adr_queue4_en, | |
351 | drq1_rd_adr_queue3_en, | |
352 | drq1_rd_adr_queue2_en, | |
353 | drq1_rd_adr_queue1_en, | |
354 | drq1_rd_adr_queue0_en, | |
355 | drq0_wr_adr_queue7_en, | |
356 | drq0_wr_adr_queue6_en, | |
357 | drq0_wr_adr_queue5_en, | |
358 | drq0_wr_adr_queue4_en, | |
359 | drq0_wr_adr_queue3_en, | |
360 | drq0_wr_adr_queue2_en, | |
361 | drq0_wr_adr_queue1_en, | |
362 | drq0_wr_adr_queue0_en, | |
363 | drq1_wr_adr_queue7_en, | |
364 | drq1_wr_adr_queue6_en, | |
365 | drq1_wr_adr_queue5_en, | |
366 | drq1_wr_adr_queue4_en, | |
367 | drq1_wr_adr_queue3_en, | |
368 | drq1_wr_adr_queue2_en, | |
369 | drq1_wr_adr_queue1_en, | |
370 | drq1_wr_adr_queue0_en, | |
371 | drif0_rd_adr_queue_sel, | |
372 | drif1_rd_adr_queue_sel, | |
373 | woq_wr_adr_queue_sel, | |
374 | woq_wr1_adr_queue_sel, | |
375 | woq_wr2_adr_queue_sel, | |
376 | drif0_req_rdwr_addr_sel, | |
377 | drif1_req_rdwr_addr_sel, | |
378 | drif_l2poison_qw, | |
379 | drif_wadr_parity, | |
380 | mcu_pt_sync_out, | |
381 | drif_scrub_rwen, | |
382 | drif_io_wdata_sel, | |
383 | drif_ucb_wr_req_vld, | |
384 | drif_ucb_rd_req_vld, | |
385 | drif_ucb_addr, | |
386 | drif_ucb_data, | |
387 | drif_err_sts_reg_ld, | |
388 | drif_err_addr_reg_ld, | |
389 | drif_err_cnt_reg_ld, | |
390 | drif_err_loc_reg_ld, | |
391 | drif_err_retry_reg_ld, | |
392 | drif_dbg_trig_reg_ld, | |
393 | drif_dram_cmd_a, | |
394 | drif_dram_addr_a, | |
395 | drif_dram_bank_a, | |
396 | drif_dram_rank_a, | |
397 | drif_dram_dimm_a, | |
398 | drif_dram_cmd_b, | |
399 | drif_dram_addr_b, | |
400 | drif_dram_bank_b, | |
401 | drif_dram_rank_b, | |
402 | drif_dram_dimm_b, | |
403 | drif_dram_cmd_c, | |
404 | drif_dram_addr_c, | |
405 | drif_dram_bank_c, | |
406 | drif_dram_rank_c, | |
407 | drif_dram_dimm_c, | |
408 | drif_wdata_wsn, | |
409 | woq_err_st_wait_free, | |
410 | drif_crc_rd_picked, | |
411 | drif_err_fifo_empty, | |
412 | woq_err_fifo_empty, | |
413 | woq_wr_req_out, | |
414 | drif_mcu_error_mode, | |
415 | drif_err_state_crc_fr, | |
416 | drif_mcu_idle, | |
417 | drif_cke_reg, | |
418 | rdata_drif_rd_req_vld, | |
419 | rdata_drif_wr_req_vld, | |
420 | rdata_drif_addr, | |
421 | rdata_drif_data, | |
422 | rdata_mcu_selfrsh, | |
423 | rdpctl_err_addr_reg, | |
424 | rdpctl_err_sts_reg, | |
425 | rdpctl_err_loc, | |
426 | rdpctl_err_cnt, | |
427 | rdpctl_err_retry_reg, | |
428 | rdpctl_dbg_trig_enable, | |
429 | rdpctl_kp_lnk_up, | |
430 | rdpctl_mask_err, | |
431 | rdpctl_dtm_mask_chnl, | |
432 | rdpctl_dtm_atspeed, | |
433 | rdpctl_drq0_clear_ent, | |
434 | rdpctl_drq1_clear_ent, | |
435 | rdpctl_scrub_wren, | |
436 | rdpctl_scrub_addrinc_en, | |
437 | readdp_ecc_multi_err, | |
438 | addrdp_ras_adr_queue, | |
439 | addrdp_cas_adr_queue, | |
440 | addrdp_rd_req_id_queue, | |
441 | addrdp_ras_wr1_adr_queue, | |
442 | addrdp_cas_wr1_adr_queue, | |
443 | addrdp_ras_wr2_adr_queue, | |
444 | addrdp_cas_wr2_adr_queue, | |
445 | l2b0_rd_rank_adr, | |
446 | l2b0_rd_dimm_adr, | |
447 | l2b0_rd_bank_adr, | |
448 | l2b0_rd_addr_err, | |
449 | l2b0_rd_addr_par, | |
450 | l2b1_rd_rank_adr, | |
451 | l2b1_rd_dimm_adr, | |
452 | l2b1_rd_bank_adr, | |
453 | l2b1_rd_addr_err, | |
454 | l2b1_rd_addr_par, | |
455 | l2b0_wr_rank_adr, | |
456 | l2b0_wr_dimm_adr, | |
457 | l2b0_wr_bank_adr, | |
458 | l2b0_wr_addr_err, | |
459 | l2b0_wr_addr_par, | |
460 | l2b1_wr_rank_adr, | |
461 | l2b1_wr_dimm_adr, | |
462 | l2b1_wr_bank_adr, | |
463 | l2b1_wr_addr_err, | |
464 | l2b1_wr_addr_par, | |
465 | l2if0_rd_req, | |
466 | l2if0_wr_req, | |
467 | l2if0_data_wr_addr, | |
468 | l2if0_wdq_rd_inh, | |
469 | l2if0_wdq_in_cntr, | |
470 | l2if1_rd_req, | |
471 | l2if1_wr_req, | |
472 | l2if1_data_wr_addr, | |
473 | l2if1_wdq_rd_inh, | |
474 | l2if1_wdq_in_cntr, | |
475 | mcu_pt_sync_in0, | |
476 | mcu_pt_sync_in1, | |
477 | mcu_pt_sync_in2, | |
478 | addrdp0_rd_wr_adr0_eq, | |
479 | addrdp0_rd_wr_adr1_eq, | |
480 | addrdp0_rd_wr_adr2_eq, | |
481 | addrdp0_rd_wr_adr3_eq, | |
482 | addrdp0_rd_wr_adr4_eq, | |
483 | addrdp0_rd_wr_adr5_eq, | |
484 | addrdp0_rd_wr_adr6_eq, | |
485 | addrdp0_rd_wr_adr7_eq, | |
486 | addrdp1_rd_wr_adr0_eq, | |
487 | addrdp1_rd_wr_adr1_eq, | |
488 | addrdp1_rd_wr_adr2_eq, | |
489 | addrdp1_rd_wr_adr3_eq, | |
490 | addrdp1_rd_wr_adr4_eq, | |
491 | addrdp1_rd_wr_adr5_eq, | |
492 | addrdp1_rd_wr_adr6_eq, | |
493 | addrdp1_rd_wr_adr7_eq, | |
494 | rdpctl_scrub_read_done, | |
495 | wdqrf00_data_mecc, | |
496 | wdqrf01_data_mecc, | |
497 | wdqrf10_data_mecc, | |
498 | wdqrf11_data_mecc, | |
499 | rdpctl_err_fifo_enq, | |
500 | rdpctl_err_fifo_data, | |
501 | rdpctl_fifo_empty, | |
502 | rdpctl_fifo_full, | |
503 | rdpctl_no_crc_err, | |
504 | rdpctl_crc_err, | |
505 | fbdic_ucb_rd_data, | |
506 | fbdic_sync_frame_req_early3, | |
507 | fbdic_sync_frame_req_early2, | |
508 | fbdic_sync_frame_req_early1, | |
509 | fbdic_sync_frame_req, | |
510 | fbdic_scr_frame_req_d4, | |
511 | fbdic_l0_state, | |
512 | fbdic_woq_free, | |
513 | fbdic_clear_wrq_ent, | |
514 | fbdic_error_mode, | |
515 | fbdic_l0s_lfsr_stall, | |
516 | fbdic_err_fast_reset_done, | |
517 | fbdic_chnl_reset_error_mode, | |
518 | fbdic_mcu_idle, | |
519 | drl2clk, | |
520 | scan_in, | |
521 | scan_out, | |
522 | wmr_scan_in, | |
523 | wmr_scan_out, | |
524 | tcu_pce_ov, | |
525 | tcu_aclk, | |
526 | tcu_bclk, | |
527 | aclk_wmr, | |
528 | tcu_scan_en, | |
529 | wmr_protect); | |
530 | wire pce_ov; | |
531 | wire siclk; | |
532 | wire soclk; | |
533 | wire se; | |
534 | wire l1clk; | |
535 | wire ff_ucb_req_scanin; | |
536 | wire ff_ucb_req_scanout; | |
537 | wire ff_hw_selfref_scanin; | |
538 | wire ff_hw_selfref_scanout; | |
539 | wire drif_hw_selfrsh; | |
540 | wire fbdic_sync_frame_req_l; | |
541 | wire fbdic_sync_frame_req_early3_l; | |
542 | wire fbdic_sync_frame_req_early1_l; | |
543 | wire ff_sync_frame_req_l_scanin; | |
544 | wire ff_sync_frame_req_l_scanout; | |
545 | wire drif_sync_frame_req_l; | |
546 | wire drif_sync_frame_req_early3_l; | |
547 | wire drif_sync_frame_req_early1_l; | |
548 | wire dmmdly0_scanin; | |
549 | wire dmmdly0_scanout; | |
550 | wire [7:0] drif_dmm_rd_ras_picked; | |
551 | wire [7:0] drif_dmm_wr_ras_picked; | |
552 | wire [7:0] drif_dmm_wrbc_ras_picked; | |
553 | wire [7:0] rrd_cnt_is_zero; | |
554 | wire [7:0] rtw_cnt_is_zero; | |
555 | wire [7:0] wtr_cnt_is_zero; | |
556 | wire [7:0] rtr_cnt_is_zero; | |
557 | wire [7:0] wtw_cnt_is_zero; | |
558 | wire [7:0] dmmdly_4_activate_stall; | |
559 | wire dmmdly1_scanin; | |
560 | wire dmmdly1_scanout; | |
561 | wire dmmdly2_scanin; | |
562 | wire dmmdly2_scanout; | |
563 | wire dmmdly3_scanin; | |
564 | wire dmmdly3_scanout; | |
565 | wire dmmdly4_scanin; | |
566 | wire dmmdly4_scanout; | |
567 | wire dmmdly5_scanin; | |
568 | wire dmmdly5_scanout; | |
569 | wire dmmdly6_scanin; | |
570 | wire dmmdly6_scanout; | |
571 | wire dmmdly7_scanin; | |
572 | wire dmmdly7_scanout; | |
573 | wire [6:0] rfc_cnt_next; | |
574 | wire drif_refresh_req_picked; | |
575 | wire [6:0] rfc_reg; | |
576 | wire [6:0] rfc_cnt; | |
577 | wire ff_rfc_cnt_scanin; | |
578 | wire ff_rfc_cnt_scanout; | |
579 | wire rfc_cnt_is_zero; | |
580 | wire [1:0] rd_rrd_cnt_next; | |
581 | wire drif0_rd_picked; | |
582 | wire drif0_raw_hazard; | |
583 | wire drif1_rd_picked; | |
584 | wire drif1_raw_hazard; | |
585 | wire drif_scrub_picked; | |
586 | wire drif_err_rd_picked; | |
587 | wire rd_rrd_cnt_is_zero; | |
588 | wire [1:0] rd_rrd_cnt; | |
589 | wire ff_rd_rrd_cnt_scanin; | |
590 | wire ff_rd_rrd_cnt_scanout; | |
591 | wire bnksm0_scanin; | |
592 | wire bnksm0_scanout; | |
593 | wire [15:0] drif_abnk_ras_picked; | |
594 | wire [15:0] drif_abnk_cas_picked; | |
595 | wire [15:0] drif_bcbnk_ras_picked; | |
596 | wire [15:0] drif_bcbnk_cas_picked; | |
597 | wire b0_rcd_cnt_is_zero; | |
598 | wire b0_rc_cnt_is_zero; | |
599 | wire b0_dal_cnt_is_zero; | |
600 | wire bnksm1_scanin; | |
601 | wire bnksm1_scanout; | |
602 | wire b1_rcd_cnt_is_zero; | |
603 | wire b1_rc_cnt_is_zero; | |
604 | wire b1_dal_cnt_is_zero; | |
605 | wire bnksm2_scanin; | |
606 | wire bnksm2_scanout; | |
607 | wire b2_rcd_cnt_is_zero; | |
608 | wire b2_rc_cnt_is_zero; | |
609 | wire b2_dal_cnt_is_zero; | |
610 | wire bnksm3_scanin; | |
611 | wire bnksm3_scanout; | |
612 | wire b3_rcd_cnt_is_zero; | |
613 | wire b3_rc_cnt_is_zero; | |
614 | wire b3_dal_cnt_is_zero; | |
615 | wire bnksm4_scanin; | |
616 | wire bnksm4_scanout; | |
617 | wire b4_rcd_cnt_is_zero; | |
618 | wire b4_rc_cnt_is_zero; | |
619 | wire b4_dal_cnt_is_zero; | |
620 | wire bnksm5_scanin; | |
621 | wire bnksm5_scanout; | |
622 | wire b5_rcd_cnt_is_zero; | |
623 | wire b5_rc_cnt_is_zero; | |
624 | wire b5_dal_cnt_is_zero; | |
625 | wire bnksm6_scanin; | |
626 | wire bnksm6_scanout; | |
627 | wire b6_rcd_cnt_is_zero; | |
628 | wire b6_rc_cnt_is_zero; | |
629 | wire b6_dal_cnt_is_zero; | |
630 | wire bnksm7_scanin; | |
631 | wire bnksm7_scanout; | |
632 | wire b7_rcd_cnt_is_zero; | |
633 | wire b7_rc_cnt_is_zero; | |
634 | wire b7_dal_cnt_is_zero; | |
635 | wire bnksm8_scanin; | |
636 | wire bnksm8_scanout; | |
637 | wire b8_rcd_cnt_is_zero; | |
638 | wire b8_rc_cnt_is_zero; | |
639 | wire b8_dal_cnt_is_zero; | |
640 | wire bnksm9_scanin; | |
641 | wire bnksm9_scanout; | |
642 | wire b9_rcd_cnt_is_zero; | |
643 | wire b9_rc_cnt_is_zero; | |
644 | wire b9_dal_cnt_is_zero; | |
645 | wire bnksm10_scanin; | |
646 | wire bnksm10_scanout; | |
647 | wire b10_rcd_cnt_is_zero; | |
648 | wire b10_rc_cnt_is_zero; | |
649 | wire b10_dal_cnt_is_zero; | |
650 | wire bnksm11_scanin; | |
651 | wire bnksm11_scanout; | |
652 | wire b11_rcd_cnt_is_zero; | |
653 | wire b11_rc_cnt_is_zero; | |
654 | wire b11_dal_cnt_is_zero; | |
655 | wire bnksm12_scanin; | |
656 | wire bnksm12_scanout; | |
657 | wire b12_rcd_cnt_is_zero; | |
658 | wire b12_rc_cnt_is_zero; | |
659 | wire b12_dal_cnt_is_zero; | |
660 | wire bnksm13_scanin; | |
661 | wire bnksm13_scanout; | |
662 | wire b13_rcd_cnt_is_zero; | |
663 | wire b13_rc_cnt_is_zero; | |
664 | wire b13_dal_cnt_is_zero; | |
665 | wire bnksm14_scanin; | |
666 | wire bnksm14_scanout; | |
667 | wire b14_rcd_cnt_is_zero; | |
668 | wire b14_rc_cnt_is_zero; | |
669 | wire b14_dal_cnt_is_zero; | |
670 | wire bnksm15_scanin; | |
671 | wire bnksm15_scanout; | |
672 | wire b15_rcd_cnt_is_zero; | |
673 | wire b15_rc_cnt_is_zero; | |
674 | wire b15_dal_cnt_is_zero; | |
675 | wire [15:0] drif0_rd_bank_valids; | |
676 | wire [15:0] drq0_rd_entry0_val; | |
677 | wire [15:0] drq0_rd_entry1_val; | |
678 | wire [15:0] drq0_rd_entry2_val; | |
679 | wire [15:0] drq0_rd_entry3_val; | |
680 | wire [15:0] drq0_rd_entry4_val; | |
681 | wire [15:0] drq0_rd_entry5_val; | |
682 | wire [15:0] drq0_rd_entry6_val; | |
683 | wire [15:0] drq0_rd_entry7_val; | |
684 | wire [15:0] drif1_rd_bank_valids; | |
685 | wire [15:0] drq1_rd_entry0_val; | |
686 | wire [15:0] drq1_rd_entry1_val; | |
687 | wire [15:0] drq1_rd_entry2_val; | |
688 | wire [15:0] drq1_rd_entry3_val; | |
689 | wire [15:0] drq1_rd_entry4_val; | |
690 | wire [15:0] drq1_rd_entry5_val; | |
691 | wire [15:0] drq1_rd_entry6_val; | |
692 | wire [15:0] drq1_rd_entry7_val; | |
693 | wire [15:0] drif_wr_bank_valids; | |
694 | wire [15:0] woq_entry0_val; | |
695 | wire [15:0] woq_entry1_val; | |
696 | wire [15:0] drif_bank_available; | |
697 | wire [7:0] drif_dimm_rd_available; | |
698 | wire [7:0] drif_dimm_wr_available; | |
699 | wire drif0_rd_ready; | |
700 | wire drif1_rd_ready; | |
701 | wire drif_rd_ready; | |
702 | wire drif_rd_pending; | |
703 | wire [15:0] drq0_rd_bank_val; | |
704 | wire [15:0] drq1_rd_bank_val; | |
705 | wire drif_rd_stall; | |
706 | wire drif_blk_new_openbank; | |
707 | wire drif_wr_pending; | |
708 | wire drif_pick_wr_first; | |
709 | wire drif_wr_entry_pend; | |
710 | wire drif_scrub_ready; | |
711 | wire drif_cas_picked; | |
712 | wire woq_wr_error_mode; | |
713 | wire [7:0] drif_mcu_state; | |
714 | wire [7:0] drif0_rd_entry_ready; | |
715 | wire drif_rank_wait; | |
716 | wire [3:0] drif_last_rank_picked; | |
717 | wire [2:0] drq0_rd_entry0_dimm; | |
718 | wire drq0_rd_entry0_rank; | |
719 | wire [2:0] drq0_rd_entry1_dimm; | |
720 | wire drq0_rd_entry1_rank; | |
721 | wire [2:0] drq0_rd_entry2_dimm; | |
722 | wire drq0_rd_entry2_rank; | |
723 | wire [2:0] drq0_rd_entry3_dimm; | |
724 | wire drq0_rd_entry3_rank; | |
725 | wire [2:0] drq0_rd_entry4_dimm; | |
726 | wire drq0_rd_entry4_rank; | |
727 | wire [2:0] drq0_rd_entry5_dimm; | |
728 | wire drq0_rd_entry5_rank; | |
729 | wire [2:0] drq0_rd_entry6_dimm; | |
730 | wire drq0_rd_entry6_rank; | |
731 | wire [2:0] drq0_rd_entry7_dimm; | |
732 | wire drq0_rd_entry7_rank; | |
733 | wire [7:0] drif1_rd_entry_ready; | |
734 | wire [2:0] drq1_rd_entry0_dimm; | |
735 | wire drq1_rd_entry0_rank; | |
736 | wire [2:0] drq1_rd_entry1_dimm; | |
737 | wire drq1_rd_entry1_rank; | |
738 | wire [2:0] drq1_rd_entry2_dimm; | |
739 | wire drq1_rd_entry2_rank; | |
740 | wire [2:0] drq1_rd_entry3_dimm; | |
741 | wire drq1_rd_entry3_rank; | |
742 | wire [2:0] drq1_rd_entry4_dimm; | |
743 | wire drq1_rd_entry4_rank; | |
744 | wire [2:0] drq1_rd_entry5_dimm; | |
745 | wire drq1_rd_entry5_rank; | |
746 | wire [2:0] drq1_rd_entry6_dimm; | |
747 | wire drq1_rd_entry6_rank; | |
748 | wire [2:0] drq1_rd_entry7_dimm; | |
749 | wire drq1_rd_entry7_rank; | |
750 | wire drif_wr_ready; | |
751 | wire [15:0] woq_wr_bank_val; | |
752 | wire drif_wr_stall; | |
753 | wire [2:0] drif_wr_entry_ready; | |
754 | wire [15:0] woq_entry0; | |
755 | wire woq0_wdq_rd; | |
756 | wire woq1_wdq_rd; | |
757 | wire drif_wdq_sel; | |
758 | wire drif_wdq_sel_d1; | |
759 | wire drif_cmd_b_val; | |
760 | wire drif_pd_mode_pending; | |
761 | wire [15:0] woq_entry1; | |
762 | wire [7:0] drif0_rd_entry_picked_in; | |
763 | wire drif_entry_priority; | |
764 | wire [7:0] drif1_rd_entry_picked_in; | |
765 | wire [7:0] drif0_rd_entry_picked; | |
766 | wire [7:0] drif1_rd_entry_picked; | |
767 | wire [2:0] drif_wr_entry_picked; | |
768 | wire drif_rd_picked; | |
769 | wire drif0_wr_picked; | |
770 | wire drif1_wr_picked; | |
771 | wire drif0_wr1_picked; | |
772 | wire drif1_wr1_picked; | |
773 | wire drif0_wr2_picked; | |
774 | wire drif1_wr2_picked; | |
775 | wire drif0_err_rd_picked; | |
776 | wire drif0_err_wr_picked; | |
777 | wire drif_err_fifo_scrub; | |
778 | wire drif_entry_priority_in; | |
779 | wire ff_entry_priority_scanin; | |
780 | wire ff_entry_priority_scanout; | |
781 | wire [9:0] drq0_rd_addr_picked; | |
782 | wire [9:0] drq1_rd_addr_picked; | |
783 | wire drif_wr_picked; | |
784 | wire [9:0] woq_wr_addr_picked; | |
785 | wire [15:0] drif_scrub_entry_val; | |
786 | wire drif_err_wr_picked; | |
787 | wire [15:0] drif_err_entry_val; | |
788 | wire drif_wr1_picked; | |
789 | wire [9:0] woq_wr1_addr_picked; | |
790 | wire drif_wr2_picked; | |
791 | wire [9:0] woq_wr2_addr_picked; | |
792 | wire ff_cas_abnk_picked_scanin; | |
793 | wire ff_cas_abnk_picked_scanout; | |
794 | wire ff_cas_bcbnk_picked_scanin; | |
795 | wire ff_cas_bcbnk_picked_scanout; | |
796 | wire [15:0] drif_bnk_ras_picked; | |
797 | wire [15:0] drif_bnk_cas_picked; | |
798 | wire drif_any_ras_picked; | |
799 | wire [15:0] drif_ras_picked; | |
800 | wire [2:0] drif_scrub_dimm_adr; | |
801 | wire [2:0] drif_err_fifo_dimm_adr; | |
802 | wire drif_last_rank_picked_en; | |
803 | wire [3:0] drif_phy_bank_picked; | |
804 | wire drif_phy_bank_picked_en; | |
805 | wire ff_rank_dimm_picked_scanin; | |
806 | wire ff_rank_dimm_picked_scanout; | |
807 | wire drif_rank_adr; | |
808 | wire [2:0] drif_dimm_adr; | |
809 | wire drif_ras_picked_d2_in; | |
810 | wire ff_ras_picked_d2_scanin; | |
811 | wire ff_ras_picked_d2_scanout; | |
812 | wire drif_ras_picked_d2; | |
813 | wire drif_ras_picked_d3; | |
814 | wire drif_ras_picked_d4; | |
815 | wire [15:0] drif_scrub_bank_valid; | |
816 | wire [4:0] drif_refresh_rank; | |
817 | wire drif_scrub_rank_adr; | |
818 | wire drif_init; | |
819 | wire [15:0] drif_scrub_rank_avail; | |
820 | wire drif_err_fifo_empty_d1; | |
821 | wire drif_4_activate_stall_scrub; | |
822 | wire rtr_cnt_is_zero_scrub; | |
823 | wire wtr_cnt_is_zero_scrub; | |
824 | wire [8:0] drif_rd_addr_picked; | |
825 | wire [2:0] drif_rd_index_picked; | |
826 | wire [2:0] drq0_rd_index_picked; | |
827 | wire [2:0] drq1_rd_index_picked; | |
828 | wire [7:0] drif0_raw_match_in; | |
829 | wire [7:0] drq0_pending_wr_req; | |
830 | wire [7:0] drif1_raw_match_in; | |
831 | wire [7:0] drq1_pending_wr_req; | |
832 | wire drif_wr_entry_pend_in; | |
833 | wire drif_wr_entry_pend_en; | |
834 | wire drif_wr_entry_pend_clr; | |
835 | wire drif0_haz_rd; | |
836 | wire [7:0] drif_raw_match; | |
837 | wire ff_wr_entry_pend_scanin; | |
838 | wire ff_wr_entry_pend_scanout; | |
839 | wire drif0_haz_rd_in; | |
840 | wire [7:0] drif_raw_match_in; | |
841 | wire drif_raw_match_en; | |
842 | wire ff_raw_match_scanin; | |
843 | wire ff_raw_match_scanout; | |
844 | wire [8:0] drif_rdwr_addr_picked; | |
845 | wire drif_rdwr_cmd_picked; | |
846 | wire [2:0] drif_rdwr_index_picked; | |
847 | wire [2:0] woq_wr_index_picked; | |
848 | wire [3:0] drif_scrub_sched_bank_adr; | |
849 | wire drif_eight_bank_mode_mod; | |
850 | wire [2:0] drif_scrub_bank_adr; | |
851 | wire drif_scrub_read_pending; | |
852 | wire [8:0] drif_scrub_addr_picked; | |
853 | wire drif_scrub_addr_parity; | |
854 | wire drif_scrub_addr_err; | |
855 | wire drif_err_fifo_parity; | |
856 | wire drif_err_fifo_rank_adr; | |
857 | wire [3:0] drif_err_fifo_bank_adr; | |
858 | wire drif_addr_parity; | |
859 | wire drif_addr_err; | |
860 | wire [2:0] drif_bank_adr; | |
861 | wire [2:0] drif_index_picked; | |
862 | wire [2:0] drif_err_fifo_rdq_entry; | |
863 | wire drif_cmd_picked; | |
864 | wire ff_cmd_picked_d1_scanin; | |
865 | wire ff_cmd_picked_d1_scanout; | |
866 | wire drif_cmd_picked_d1; | |
867 | wire ff_scrub_picked_d1_scanin; | |
868 | wire ff_scrub_picked_d1_scanout; | |
869 | wire drif_scrub_picked_d1; | |
870 | wire ff_addr_parity_d1_scanin; | |
871 | wire ff_addr_parity_d1_scanout; | |
872 | wire drif_addr_parity_d1; | |
873 | wire ff_addr_err_d1_scanin; | |
874 | wire ff_addr_err_d1_scanout; | |
875 | wire drif_addr_err_d1; | |
876 | wire drif0_wr_starve_cnt_reset; | |
877 | wire drif0_pick_wr_first; | |
878 | wire drif0_pick_wr_first_in; | |
879 | wire [5:0] drif0_wr_starve_cnt_in; | |
880 | wire [5:0] drif0_wr_starve_cnt; | |
881 | wire ff_wr_starve_cnt0_scanin; | |
882 | wire ff_wr_starve_cnt0_scanout; | |
883 | wire drif0_pick_wr_first_reset; | |
884 | wire ff_pick_wr_first0_scanin; | |
885 | wire ff_pick_wr_first0_scanout; | |
886 | wire drif1_wr_starve_cnt_reset; | |
887 | wire drif1_pick_wr_first; | |
888 | wire drif1_pick_wr_first_in; | |
889 | wire [5:0] drif1_wr_starve_cnt_in; | |
890 | wire [5:0] drif1_wr_starve_cnt; | |
891 | wire ff_wr_starve_cnt1_scanin; | |
892 | wire ff_wr_starve_cnt1_scanout; | |
893 | wire drif1_pick_wr_first_reset; | |
894 | wire ff_pick_wr_first1_scanin; | |
895 | wire ff_pick_wr_first1_scanout; | |
896 | wire drif_bnk_cas_picked_or; | |
897 | wire ff_cas_picked_scanin; | |
898 | wire ff_cas_picked_scanout; | |
899 | wire drif_cas_picked_io_d1; | |
900 | wire [15:0] drif_ras_picked_io_d1; | |
901 | wire [14:0] drif_ras_adr; | |
902 | wire [14:0] drif_scrub_ras_adr; | |
903 | wire ff_ras_adr_d1_scanin; | |
904 | wire ff_ras_adr_d1_scanout; | |
905 | wire [14:0] drif_ras_adr_d1_out; | |
906 | wire [14:0] drif_ras_adr_d1; | |
907 | wire [3:0] drif_cas_addr_bits; | |
908 | wire [10:0] drif_cas_adr_d1_out; | |
909 | wire [10:0] drif_cas_adr; | |
910 | wire [10:0] drif_scrub_cas_adr; | |
911 | wire ff_cas_adr_d1_scanin; | |
912 | wire ff_cas_adr_d1_scanout; | |
913 | wire ff_req_id_d1_scanin; | |
914 | wire ff_req_id_d1_scanout; | |
915 | wire [2:0] drif_rd_req_id_d1; | |
916 | wire [10:0] drif_cas_adr_d1; | |
917 | wire ff_cas_adr_d2_scanin; | |
918 | wire ff_cas_adr_d2_scanout; | |
919 | wire [10:0] drif_cas_adr_d2; | |
920 | wire ff_bank_adr_scanin; | |
921 | wire ff_bank_adr_scanout; | |
922 | wire [2:0] drif_bank_adr_d1; | |
923 | wire [2:0] drif_bank_adr_d1_out; | |
924 | wire [2:0] drif_bank_adr_d2; | |
925 | wire ff_dimm_adr_scanin; | |
926 | wire ff_dimm_adr_scanout; | |
927 | wire [2:0] drif_dimm_adr_d1; | |
928 | wire [2:0] drif_dimm_adr_d2; | |
929 | wire ff_rank_adr_scanin; | |
930 | wire ff_rank_adr_scanout; | |
931 | wire drif_rank_adr_d1; | |
932 | wire drif_rank_adr_d2; | |
933 | wire drif_mux_write_en; | |
934 | wire ff_mux_wr_en_scanin; | |
935 | wire ff_mux_wr_en_scanout; | |
936 | wire drif_mux_write_en_d1; | |
937 | wire drif_write_en_int; | |
938 | wire drif_cmd_a_val; | |
939 | wire drif_cmd_a_val_d1; | |
940 | wire drif_cmd_a_val_in; | |
941 | wire ff_cmd_val_scanin; | |
942 | wire ff_cmd_val_scanout; | |
943 | wire drif_cmd_c_val; | |
944 | wire drif_wr_bc_stall; | |
945 | wire ff_cmd_val_d1_scanin; | |
946 | wire ff_cmd_val_d1_scanout; | |
947 | wire drif_cmd_b_val_d1; | |
948 | wire drif_cmd_c_val_d1; | |
949 | wire ff_wr1_adr_d1_scanin; | |
950 | wire ff_wr1_adr_d1_scanout; | |
951 | wire [14:0] drif_ras_wr1_adr_d1_out; | |
952 | wire [10:0] drif_cas_wr1_adr_d1_out; | |
953 | wire ff_write1_data_scanin; | |
954 | wire ff_write1_data_scanout; | |
955 | wire drif_rank_wr1_adr_d1; | |
956 | wire [2:0] drif_dimm_wr1_adr_d1; | |
957 | wire [2:0] drif_bank_wr1_adr_d1_out; | |
958 | wire [14:0] drif_ras_wr1_adr_d1; | |
959 | wire [10:0] drif_cas_wr1_adr_d1; | |
960 | wire [2:0] drif_bank_wr1_adr_d1; | |
961 | wire ff_wr1_adr_d2_scanin; | |
962 | wire ff_wr1_adr_d2_scanout; | |
963 | wire [10:0] drif_cas_wr1_adr_d2; | |
964 | wire drif_rank_wr1_adr_d2; | |
965 | wire [2:0] drif_dimm_wr1_adr_d2; | |
966 | wire [2:0] drif_bank_wr1_adr_d2; | |
967 | wire ff_write2_data_scanin; | |
968 | wire ff_write2_data_scanout; | |
969 | wire drif_rank_wr2_adr_d1; | |
970 | wire [2:0] drif_dimm_wr2_adr_d1; | |
971 | wire [2:0] drif_bank_wr2_adr_d1_out; | |
972 | wire ff_wr2_adr_d1_scanin; | |
973 | wire ff_wr2_adr_d1_scanout; | |
974 | wire [14:0] drif_ras_wr2_adr_d1_out; | |
975 | wire [10:0] drif_cas_wr2_adr_d1_out; | |
976 | wire [14:0] drif_ras_wr2_adr_d1; | |
977 | wire [10:0] drif_cas_wr2_adr_d1; | |
978 | wire [2:0] drif_bank_wr2_adr_d1; | |
979 | wire ff_wr2_adr_d2_scanin; | |
980 | wire ff_wr2_adr_d2_scanout; | |
981 | wire [10:0] drif_cas_wr2_adr_d2; | |
982 | wire drif_rank_wr2_adr_d2; | |
983 | wire [2:0] drif_dimm_wr2_adr_d2; | |
984 | wire [2:0] drif_bank_wr2_adr_d2; | |
985 | wire drif_scrub_data_rden_en_d1; | |
986 | wire drif_enter_self_refresh; | |
987 | wire drif_exit_self_refresh; | |
988 | wire drif_pd_mode_exit_pending; | |
989 | wire drif_pd_mode_enter_pending; | |
990 | wire drif_pd_mode_exit_rank; | |
991 | wire drif_pd_mode_enter_rank; | |
992 | wire [2:0] drif_pd_mode_exit_dimm; | |
993 | wire [2:0] drif_pd_mode_enter_dimm; | |
994 | wire drif_scrub_wsn; | |
995 | wire [2:0] drif_scrub_data_rden; | |
996 | wire drif_scrub_data_rden_en; | |
997 | wire drif_wdata_wsn_out; | |
998 | wire ff_wdata_wsn_scanin; | |
999 | wire ff_wdata_wsn_scanout; | |
1000 | wire woq_wdata_wsn; | |
1001 | wire ff_rd_wr_picked_d1_scanin; | |
1002 | wire ff_rd_wr_picked_d1_scanout; | |
1003 | wire [2:0] woq1_wr_picked; | |
1004 | wire drif1_rd_picked_d1; | |
1005 | wire drif1_wr2_picked_d1; | |
1006 | wire drif1_wr1_picked_d1; | |
1007 | wire drif1_wr_picked_d1; | |
1008 | wire [4:0] drif0_wdq_radr; | |
1009 | wire [4:0] woq_wdq_radr; | |
1010 | wire [4:0] drif1_wdq_radr; | |
1011 | wire drif0_wdq_sel_in; | |
1012 | wire drif1_wdq_sel_in; | |
1013 | wire [4:0] drif_err_state; | |
1014 | wire drif0_wdq_rd_inh; | |
1015 | wire [2:0] drif0_cpu_wr_addr; | |
1016 | wire drif1_wdq_rd_inh; | |
1017 | wire [2:0] drif1_cpu_wr_addr; | |
1018 | wire ff0_wr_entry0_scanin; | |
1019 | wire ff0_wr_entry0_scanout; | |
1020 | wire ff1_wr_entry0_scanin; | |
1021 | wire ff1_wr_entry0_scanout; | |
1022 | wire ff_wdq_sel_scanin; | |
1023 | wire ff_wdq_sel_scanout; | |
1024 | wire drif0_wdq_sel; | |
1025 | wire drif1_wdq_sel; | |
1026 | wire [2:0] drif_scrub_data_rden_in; | |
1027 | wire drif_scrub_buffer_full; | |
1028 | wire drif_multi_err; | |
1029 | wire ff_scrub_data_rden_scanin; | |
1030 | wire ff_scrub_data_rden_scanout; | |
1031 | wire [1:0] drif_scrub_buffer_cnt; | |
1032 | wire [1:0] drif_scrub_buffer_cnt_in; | |
1033 | wire drif_scrub_wren_d2; | |
1034 | wire ff_scrub_buffer_cnt_scanin; | |
1035 | wire ff_scrub_buffer_cnt_scanout; | |
1036 | wire drif_multi_err_in; | |
1037 | wire drif_scrub_wren; | |
1038 | wire ff_multi_err_scanin; | |
1039 | wire ff_multi_err_scanout; | |
1040 | wire [1:0] drif_woq_free; | |
1041 | wire drif_error_write_flag; | |
1042 | wire drif_error_write_flag_in; | |
1043 | wire ff_error_write_flag_scanin; | |
1044 | wire ff_error_write_flag_scanout; | |
1045 | wire ff_scrub_data_rden_en_d1_scanin; | |
1046 | wire ff_scrub_data_rden_en_d1_scanout; | |
1047 | wire drif_scrub_data_rden0_d1; | |
1048 | wire drif_err_wrdata_ready_in; | |
1049 | wire drif_err_wrdata_ready; | |
1050 | wire ff_err_wrdata_ready_scanin; | |
1051 | wire ff_err_wrdata_ready_scanout; | |
1052 | wire [1:0] woq_io_wdata_sel; | |
1053 | wire drif_wadr_parity_p2; | |
1054 | wire woq_wadr_parity; | |
1055 | wire ff_wadr_parity_scanin; | |
1056 | wire ff_wadr_parity_scanout; | |
1057 | wire drif_wadr_parity_p1; | |
1058 | wire ff_rd_index_d1_scanin; | |
1059 | wire ff_rd_index_d1_scanout; | |
1060 | wire [2:0] woq_wr_wdq_index_picked; | |
1061 | wire [2:0] drif_rd_index_d1; | |
1062 | wire [2:0] drif_wr_index_d1; | |
1063 | wire [2:0] drif_wr_wdq_index_d1; | |
1064 | wire ff_err_fifo_err_type_d1_scanin; | |
1065 | wire ff_err_fifo_err_type_d1_scanout; | |
1066 | wire drif_err_fifo_err_type; | |
1067 | wire drif_err_fifo_err_type_d1; | |
1068 | wire drif_err_rd_picked_d1; | |
1069 | wire drif_err_fifo_crc_d1; | |
1070 | wire [2:0] drif_err_fifo_rdq_entry_d1; | |
1071 | wire drif_err_fifo_l2bank; | |
1072 | wire [4:0] drif_mcu_state_enc; | |
1073 | wire ff_mcu_state_enc_scanin; | |
1074 | wire ff_mcu_state_enc_scanout; | |
1075 | wire [4:0] dal_reg; | |
1076 | wire drif_ref_go; | |
1077 | wire [4:0] ral_reg; | |
1078 | wire [4:0] rc_reg; | |
1079 | wire ff_cyc_cnt_scanin; | |
1080 | wire ff_cyc_cnt_scanout; | |
1081 | wire [1:0] mrd_cnt_next; | |
1082 | wire mrd_cnt_is_zero; | |
1083 | wire [1:0] mrd_reg; | |
1084 | wire [1:0] mrd_cnt; | |
1085 | wire ff_mrd_cnt_scanin; | |
1086 | wire ff_mrd_cnt_scanout; | |
1087 | wire [3:0] rp_cnt_next; | |
1088 | wire [3:0] rp_reg; | |
1089 | wire [3:0] rp_cnt; | |
1090 | wire ff_rp_cnt_scanin; | |
1091 | wire ff_rp_cnt_scanout; | |
1092 | wire rp_cnt_is_zero; | |
1093 | wire ff_bank_idle_cnt_scanin; | |
1094 | wire ff_bank_idle_cnt_scanout; | |
1095 | wire ff_refresh_rank_scanin; | |
1096 | wire ff_refresh_rank_scanout; | |
1097 | wire drif_enter_self_refresh_in; | |
1098 | wire ff_enter_self_refresh_scanin; | |
1099 | wire ff_enter_self_refresh_scanout; | |
1100 | wire drif_exit_self_refresh_in; | |
1101 | wire ff_exit_self_refresh_scanin; | |
1102 | wire ff_exit_self_refresh_scanout; | |
1103 | wire drif_l2poison_qw_in; | |
1104 | wire ff_l2_poison_qw_scanin; | |
1105 | wire ff_l2_poison_qw_scanout; | |
1106 | wire sch_mode_reg_en; | |
1107 | wire [6:4] mode_reg_in; | |
1108 | wire [6:0] mode_reg; | |
1109 | wire [5:4] inv_mode_reg_in; | |
1110 | wire [5:4] inv_mode_reg; | |
1111 | wire pff_mode_reg_wmr_scanin; | |
1112 | wire pff_mode_reg_wmr_scanout; | |
1113 | wire sch_ext_mode_reg1_en; | |
1114 | wire [14:0] ext_mode_reg1_in; | |
1115 | wire [4:3] inv_ext_mode_reg1_in; | |
1116 | wire [14:0] ext_mode_reg1; | |
1117 | wire [4:3] inv_ext_mode_reg1; | |
1118 | wire pff_ext_mode_reg1_wmr_scanin; | |
1119 | wire pff_ext_mode_reg1_wmr_scanout; | |
1120 | wire sch_ext_mode_reg2_en; | |
1121 | wire [14:0] ext_mode_reg2_in; | |
1122 | wire pff_ext_mode_reg2_wmr_scanin; | |
1123 | wire pff_ext_mode_reg2_wmr_scanout; | |
1124 | wire [14:0] ext_mode_reg2; | |
1125 | wire sch_ext_mode_reg3_en; | |
1126 | wire [14:0] ext_mode_reg3_in; | |
1127 | wire pff_ext_mode_reg3_wmr_scanin; | |
1128 | wire pff_ext_mode_reg3_wmr_scanout; | |
1129 | wire [14:0] ext_mode_reg3; | |
1130 | wire drif_stacked_dimm_en; | |
1131 | wire drif_stacked_dimm_in; | |
1132 | wire pff_stacked_dimm_wmr_scanin; | |
1133 | wire pff_stacked_dimm_wmr_scanout; | |
1134 | wire drif_cas_addr_bits_en; | |
1135 | wire [3:0] drif_cas_addr_bits_in; | |
1136 | wire [2:0] inv_drif_cas_addr_bits_in; | |
1137 | wire [2:0] inv_drif_cas_addr_bits; | |
1138 | wire pff_cas_addr_bits_wmr_scanin; | |
1139 | wire pff_cas_addr_bits_wmr_scanout; | |
1140 | wire drif_ras_addr_bits_en; | |
1141 | wire [3:0] drif_ras_addr_bits_in; | |
1142 | wire [3:0] inv_drif_ras_addr_bits_in; | |
1143 | wire [3:0] drif_ras_addr_bits; | |
1144 | wire [3:0] inv_drif_ras_addr_bits; | |
1145 | wire pff_ras_addr_bits_wmr_scanin; | |
1146 | wire pff_ras_addr_bits_wmr_scanout; | |
1147 | wire [1:0] drif_row_addr_bits; | |
1148 | wire [1:0] drif_mem_type_in; | |
1149 | wire drif_eight_bank_mode_nomod; | |
1150 | wire ff_mem_type_scanin; | |
1151 | wire ff_mem_type_scanout; | |
1152 | wire drif_freq_scrub_en; | |
1153 | wire [11:0] drif_freq_scrub_in; | |
1154 | wire [11:0] inv_drif_freq_scrub_in; | |
1155 | wire [11:0] drif_freq_scrub; | |
1156 | wire [11:0] inv_drif_freq_scrub; | |
1157 | wire pff_freq_scrub_wmr_scanin; | |
1158 | wire pff_freq_scrub_wmr_scanout; | |
1159 | wire drif_dimms_present_en; | |
1160 | wire [3:0] drif_dimms_present_in; | |
1161 | wire [0:0] inv_drif_dimms_present_in; | |
1162 | wire [3:0] drif_dimms_present; | |
1163 | wire [0:0] inv_drif_dimms_present; | |
1164 | wire pff_dimms_present_wmr_scanin; | |
1165 | wire pff_dimms_present_wmr_scanout; | |
1166 | wire drif_branch_disabled_en; | |
1167 | wire drif_branch_disabled_in; | |
1168 | wire pff_branch_disabled_wmr_scanin; | |
1169 | wire pff_branch_disabled_wmr_scanout; | |
1170 | wire drif_init_en; | |
1171 | wire drif_init_in; | |
1172 | wire inv_drif_init_in; | |
1173 | wire inv_drif_init; | |
1174 | wire ff_init_scanin; | |
1175 | wire ff_init_scanout; | |
1176 | wire drif_addr_bank_low_sel_en; | |
1177 | wire drif_addr_bank_low_sel_in; | |
1178 | wire pff_bank_low_sel_wmr_scanin; | |
1179 | wire pff_bank_low_sel_wmr_scanout; | |
1180 | wire drif_eight_bank_mode_en; | |
1181 | wire drif_eight_bank_mode_in; | |
1182 | wire inv_drif_eight_bank_mode_in; | |
1183 | wire drif_eight_bank_mode; | |
1184 | wire inv_drif_eight_bank_mode; | |
1185 | wire pff_eight_bank_present_wmr_scanin; | |
1186 | wire pff_eight_bank_present_wmr_scanout; | |
1187 | wire drif_single_channel_mode_en; | |
1188 | wire drif_single_channel_mode_in; | |
1189 | wire pff_single_channel_mode_wmr_scanin; | |
1190 | wire pff_single_channel_mode_wmr_scanout; | |
1191 | wire drif_single_channel_mode_pend_clr; | |
1192 | wire ff_single_channel_mode_pend_scanin; | |
1193 | wire ff_single_channel_mode_pend_scanout; | |
1194 | wire drif_single_channel_mode_pend; | |
1195 | wire drif_fail_over_mode_en; | |
1196 | wire drif_fail_over_mode_in; | |
1197 | wire pff_fail_over_mode_wmr_scanin; | |
1198 | wire pff_fail_over_mode_wmr_scanout; | |
1199 | wire drif_cke_en; | |
1200 | wire drif_cke_in; | |
1201 | wire ff_cke_enable_scanin; | |
1202 | wire ff_cke_enable_scanout; | |
1203 | wire drif_fail_over_mask_en; | |
1204 | wire [34:0] drif_fail_over_mask_in; | |
1205 | wire pff_fail_over_mask_wmr_scanin; | |
1206 | wire pff_fail_over_mask_wmr_scanout; | |
1207 | wire sch_rrd_reg_en; | |
1208 | wire [3:0] rrd_reg_in; | |
1209 | wire [1:1] inv_rrd_reg_in; | |
1210 | wire [3:0] rrd_reg; | |
1211 | wire [1:1] inv_rrd_reg; | |
1212 | wire pff_rrd_reg_wmr_scanin; | |
1213 | wire pff_rrd_reg_wmr_scanout; | |
1214 | wire sch_rcd_reg_en; | |
1215 | wire [3:0] rcd_reg_in; | |
1216 | wire [1:0] inv_rcd_reg_in; | |
1217 | wire [3:0] rcd_reg; | |
1218 | wire [1:0] inv_rcd_reg; | |
1219 | wire pff_rcd_reg_wmr_scanin; | |
1220 | wire pff_rcd_reg_wmr_scanout; | |
1221 | wire sch_iwtr_reg_en; | |
1222 | wire [1:0] iwtr_reg_in; | |
1223 | wire [1:1] inv_iwtr_reg_in; | |
1224 | wire [1:0] iwtr_reg; | |
1225 | wire [1:1] inv_iwtr_reg; | |
1226 | wire pff_iwtr_reg_wmr_scanin; | |
1227 | wire pff_iwtr_reg_wmr_scanout; | |
1228 | wire sch_wtr_reg_en; | |
1229 | wire [3:0] wtr_reg_in; | |
1230 | wire pff_wtr_reg_wmr_scanin; | |
1231 | wire pff_wtr_reg_wmr_scanout; | |
1232 | wire [3:0] wtr_dly_reg; | |
1233 | wire [3:0] wtr_reg; | |
1234 | wire sch_rtw_reg_en; | |
1235 | wire [3:0] rtw_reg_in; | |
1236 | wire pff_rtw_reg_wmr_scanin; | |
1237 | wire pff_rtw_reg_wmr_scanout; | |
1238 | wire [3:0] rtw_dly_reg; | |
1239 | wire [3:0] rtw_reg; | |
1240 | wire [4:0] dal_reg_in; | |
1241 | wire [3:0] wr_reg; | |
1242 | wire ff_dal_reg_scanin; | |
1243 | wire ff_dal_reg_scanout; | |
1244 | wire [4:0] al_plus_bl_2; | |
1245 | wire cmp0; | |
1246 | wire [3:0] ras_reg; | |
1247 | wire cmp1; | |
1248 | wire [2:0] rtp_reg; | |
1249 | wire cmp2; | |
1250 | wire [4:0] max_ral_delay; | |
1251 | wire [4:0] ral_reg_in; | |
1252 | wire ff_ral_reg_scanin; | |
1253 | wire ff_ral_reg_scanout; | |
1254 | wire sch_rtp_reg_en; | |
1255 | wire [2:0] rtp_reg_in; | |
1256 | wire [1:1] inv_rtp_reg_in; | |
1257 | wire [1:1] inv_rtp_reg; | |
1258 | wire pff_rtp_reg_wmr_scanin; | |
1259 | wire pff_rtp_reg_wmr_scanout; | |
1260 | wire sch_ras_reg_en; | |
1261 | wire [3:0] ras_reg_in; | |
1262 | wire [1:0] inv_ras_reg_in; | |
1263 | wire [1:0] inv_ras_reg; | |
1264 | wire pff_ras_reg_wmr_scanin; | |
1265 | wire pff_ras_reg_wmr_scanout; | |
1266 | wire sch_rp_reg_en; | |
1267 | wire [3:0] rp_reg_in; | |
1268 | wire [1:0] inv_rp_reg_in; | |
1269 | wire [1:0] inv_rp_reg; | |
1270 | wire pff_rp_reg_wmr_scanin; | |
1271 | wire pff_rp_reg_wmr_scanout; | |
1272 | wire sch_rc_reg_en; | |
1273 | wire [4:0] rc_reg_in; | |
1274 | wire [3:2] inv_rc_reg_in; | |
1275 | wire [3:2] inv_rc_reg; | |
1276 | wire pff_rc_reg_wmr_scanin; | |
1277 | wire pff_rc_reg_wmr_scanout; | |
1278 | wire sch_wr_reg_en; | |
1279 | wire [3:0] wr_reg_in; | |
1280 | wire [1:0] inv_wr_reg_in; | |
1281 | wire [1:0] inv_wr_reg; | |
1282 | wire pff_wr_reg_wmr_scanin; | |
1283 | wire pff_wr_reg_wmr_scanout; | |
1284 | wire sch_rfc_reg_en; | |
1285 | wire [6:0] rfc_reg_in; | |
1286 | wire [6:0] rfc_reg_reset_val_in; | |
1287 | wire [6:0] rfc_reg_reset_val; | |
1288 | wire pff_rfc_reg_wmr_scanin; | |
1289 | wire pff_rfc_reg_wmr_scanout; | |
1290 | wire sch_mrd_reg_en; | |
1291 | wire [1:0] mrd_reg_in; | |
1292 | wire [1:1] inv_mrd_reg_in; | |
1293 | wire [1:1] inv_mrd_reg; | |
1294 | wire pff_mrd_reg_wmr_scanin; | |
1295 | wire pff_mrd_reg_wmr_scanout; | |
1296 | wire faw_reg_en; | |
1297 | wire [4:0] faw_reg_in; | |
1298 | wire [1:0] inv_faw_reg_in; | |
1299 | wire [4:0] faw_reg; | |
1300 | wire [1:0] inv_faw_reg; | |
1301 | wire pff_faw_reg_wmr_scanin; | |
1302 | wire pff_faw_reg_wmr_scanout; | |
1303 | wire drif_precharge_wait_en; | |
1304 | wire [7:0] drif_precharge_wait_in; | |
1305 | wire [7:0] drif_precharge_wait_reset_val_in; | |
1306 | wire [7:0] drif_precharge_wait_reset_val; | |
1307 | wire ff_precharge_wait_scanin; | |
1308 | wire ff_precharge_wait_scanout; | |
1309 | wire drif_err_inj_reg_en; | |
1310 | wire drif_sshot_err_reg; | |
1311 | wire drif_err_injected; | |
1312 | wire drif_err_inj_reg_in; | |
1313 | wire pff_err_inj_wmr_scanin; | |
1314 | wire pff_err_inj_wmr_scanout; | |
1315 | wire drif_err_inj_reg; | |
1316 | wire drif_sshot_err_reg_en; | |
1317 | wire drif_sshot_err_reg_in; | |
1318 | wire pff_sshot_wmr_scanin; | |
1319 | wire pff_sshot_wmr_scanout; | |
1320 | wire drif_err_mask_reg_en; | |
1321 | wire [15:0] drif_err_mask_reg_in; | |
1322 | wire pff_err_mask_wmr_scanin; | |
1323 | wire pff_err_mask_wmr_scanout; | |
1324 | wire ff_wdq_sel_d1_scanin; | |
1325 | wire ff_wdq_sel_d1_scanout; | |
1326 | wire [12:0] drif_ref_freq_reset_val; | |
1327 | wire drif_ref_freq_en; | |
1328 | wire [12:0] drif_ref_freq_in; | |
1329 | wire [12:0] drif_ref_freq; | |
1330 | wire [12:0] drif_ref_freq_out; | |
1331 | wire pff_ref_freq_wmr_scanin; | |
1332 | wire pff_ref_freq_wmr_scanout; | |
1333 | wire [15:0] drif_refresh_rank_dec; | |
1334 | wire [15:0] pdmc_rank_avail; | |
1335 | wire [12:0] drif_ref_cnt_in; | |
1336 | wire ff_ref_cnt_scanin; | |
1337 | wire ff_ref_cnt_scanout; | |
1338 | wire fbdic_l0_state_d1; | |
1339 | wire ff_l0_state_d1_scanin; | |
1340 | wire ff_l0_state_d1_scanout; | |
1341 | wire drif_data_scrub_en; | |
1342 | wire drif_data_scrub_en_in; | |
1343 | wire pff_data_scrub_wmr_scanin; | |
1344 | wire pff_data_scrub_wmr_scanout; | |
1345 | wire drif_data_scrub_enabled; | |
1346 | wire [11:0] drif_scrub_cnt_in; | |
1347 | wire [11:0] drif_scrub_cnt; | |
1348 | wire drif_scrub_cnt_reset; | |
1349 | wire drif_init_mcu_done; | |
1350 | wire drif_scrub_cnt_en; | |
1351 | wire ff_scrub_cnt_scanin; | |
1352 | wire ff_scrub_cnt_scanout; | |
1353 | wire drif_scrub_read_pending_in; | |
1354 | wire drif_scrub_read_pending_en; | |
1355 | wire drif_scrub_read_outstanding; | |
1356 | wire drif_scrub_read_pending_reset; | |
1357 | wire ff_scrub_read_pending_scanin; | |
1358 | wire ff_scrub_read_pending_scanout; | |
1359 | wire ff_scrub_read_out_scanin; | |
1360 | wire ff_scrub_read_out_scanout; | |
1361 | wire ff_scrub_read_pending_en_d1_scanin; | |
1362 | wire ff_scrub_read_pending_en_d1_scanout; | |
1363 | wire drif_scrub_read_pending_en_d1; | |
1364 | wire drif_scrub_time; | |
1365 | wire pt_max_banks_open_en; | |
1366 | wire [16:0] pt_max_banks_open_in; | |
1367 | wire [16:0] inv_pt_max_banks_open_in; | |
1368 | wire [16:0] pt_max_banks_open; | |
1369 | wire [16:0] inv_pt_max_banks_open; | |
1370 | wire pff_max_banks_open_wmr_scanin; | |
1371 | wire pff_max_banks_open_wmr_scanout; | |
1372 | wire pt_max_time_en; | |
1373 | wire [15:0] pt_max_time_in; | |
1374 | wire [15:0] inv_pt_max_time_in; | |
1375 | wire [15:0] pt_max_time; | |
1376 | wire [15:0] inv_pt_max_time; | |
1377 | wire pff_max_time_wmr_scanin; | |
1378 | wire pff_max_time_wmr_scanout; | |
1379 | wire pt_sync_out; | |
1380 | wire ff_pt_sync_out_d1_scanin; | |
1381 | wire ff_pt_sync_out_d1_scanout; | |
1382 | wire pt_sync_out_d1; | |
1383 | wire mcu_pt_sync_out_in; | |
1384 | wire ff_pt_sync_out_scanin; | |
1385 | wire ff_pt_sync_out_scanout; | |
1386 | wire ff_pt_sync_scanin; | |
1387 | wire ff_pt_sync_scanout; | |
1388 | wire [3:0] pt_sync; | |
1389 | wire pt_reset; | |
1390 | wire [15:0] pt_time_cntr; | |
1391 | wire pt_banks_open_en; | |
1392 | wire [16:0] pt_banks_open_in; | |
1393 | wire [16:0] pt_banks_open; | |
1394 | wire ff_banks_open_scanin; | |
1395 | wire ff_banks_open_scanout; | |
1396 | wire [15:0] pt_time_cntr_in; | |
1397 | wire ff_time_cntr_scanin; | |
1398 | wire ff_time_cntr_scanout; | |
1399 | wire drif_blk_new_openbank_in; | |
1400 | wire ff_blk_openbank_scanin; | |
1401 | wire ff_blk_openbank_scanout; | |
1402 | wire drif_wr_mode_reg_done_in; | |
1403 | wire drif_wr_mode_reg_done; | |
1404 | wire wr_mode_reg_done_reset; | |
1405 | wire ff_wr_mode_reg_scanin; | |
1406 | wire ff_wr_mode_reg_scanout; | |
1407 | wire drif_init_mcu_done_in; | |
1408 | wire ff_init_done_scanin; | |
1409 | wire ff_init_done_scanout; | |
1410 | wire drif_init_status_reg_in; | |
1411 | wire drif_init_status_reg; | |
1412 | wire int_status_reg_reset; | |
1413 | wire ff_init_status_reg_scanin; | |
1414 | wire ff_init_status_reg_scanout; | |
1415 | wire drif_rdata_nack_vld_in; | |
1416 | wire drif_rdata_ack_vld_in; | |
1417 | wire [63:0] drif_rdata_data_in; | |
1418 | wire [65:0] drif_read_ucb_info; | |
1419 | wire ff_ucb_data_scanin; | |
1420 | wire ff_ucb_data_scanout; | |
1421 | wire drif_pd_mode_enable_en; | |
1422 | wire drif_pd_mode_enable_in; | |
1423 | wire ff_pd_mode_enable_scanin; | |
1424 | wire ff_pd_mode_enable_scanout; | |
1425 | wire drif_pd_mode_enable; | |
1426 | wire drif_perf_cntl_reg_en; | |
1427 | wire [7:0] drif_perf_cntl_reg_in; | |
1428 | wire ff_perf_cntl_reg_scanin; | |
1429 | wire ff_perf_cntl_reg_scanout; | |
1430 | wire [7:0] drif_perf_cntl_reg; | |
1431 | wire ff_crit_sig_scanin; | |
1432 | wire ff_crit_sig_scanout; | |
1433 | wire drif_rd_xaction_picked; | |
1434 | wire drif_wr_xaction_picked; | |
1435 | wire drif_bank_busy_stall; | |
1436 | wire [4:0] drif_rd_que_latency; | |
1437 | wire [4:0] drif_wr_que_latency; | |
1438 | wire drif_writeback_buf_hit; | |
1439 | wire drif_rd_que_latency_adj; | |
1440 | wire drif_wr_que_latency_adj; | |
1441 | wire drif_rd_xaction_picked_d1; | |
1442 | wire drif_wr_xaction_picked_d1; | |
1443 | wire drif_bank_busy_stall_d1; | |
1444 | wire [4:0] drif_rd_que_latency_noadj_d1; | |
1445 | wire [4:0] drif_wr_que_latency_noadj_d1; | |
1446 | wire drif_writeback_buf_hit_d1; | |
1447 | wire drif_rd_que_latency_adj_d1; | |
1448 | wire drif_wr_que_latency_adj_d1; | |
1449 | wire [4:0] drif_rd_que_latency_d1; | |
1450 | wire [4:0] drif_wr_que_latency_d1; | |
1451 | wire drif_perf_cnt0_reg_en; | |
1452 | wire [31:0] drif_perf_cnt0_reg_in; | |
1453 | wire [31:0] drif_perf0_adder_out; | |
1454 | wire [31:0] drif_perf_cnt0_reg; | |
1455 | wire [31:0] drif_perf0_adder_in; | |
1456 | wire drif_rd_or_wr_xaction_picked_d1; | |
1457 | wire [5:0] drif_rd_or_wr_que_latency_d1; | |
1458 | wire ff_perf_cnt0_reg_scanin; | |
1459 | wire ff_perf_cnt0_reg_scanout; | |
1460 | wire drif_perf_cnt1_reg_en; | |
1461 | wire [31:0] drif_perf_cnt1_reg_in; | |
1462 | wire [31:0] drif_perf1_adder_out; | |
1463 | wire [31:0] drif_perf_cnt1_reg; | |
1464 | wire [31:0] drif_perf1_adder_in; | |
1465 | wire ff_perf_cnt1_reg_scanin; | |
1466 | wire ff_perf_cnt1_reg_scanout; | |
1467 | wire drif_cmd_write; | |
1468 | wire ff_raw_hazard_d1_scanin; | |
1469 | wire ff_raw_hazard_d1_scanout; | |
1470 | wire drif_raw_hazard_d1; | |
1471 | wire [7:0] drq0_rdbuf_valids; | |
1472 | wire [7:0] drq1_rdbuf_valids; | |
1473 | wire [7:0] drq0_wrbuf_valids; | |
1474 | wire [7:0] drq1_wrbuf_valids; | |
1475 | wire [3:0] drq0_read_queue_cnt; | |
1476 | wire [3:0] drq1_read_queue_cnt; | |
1477 | wire [3:0] drq0_write_queue_cnt; | |
1478 | wire [3:0] drq1_write_queue_cnt; | |
1479 | wire ff_scrub_wren_scanin; | |
1480 | wire ff_scrub_wren_scanout; | |
1481 | wire drif_scrub_wren_d1; | |
1482 | wire drif_err_fifo_deq; | |
1483 | wire drif_err_fifo_crc; | |
1484 | wire drif_scrub_addr_incr; | |
1485 | wire errq_scanin; | |
1486 | wire errq_scanout; | |
1487 | wire [14:0] drif_err_fifo_ent0; | |
1488 | wire drif_err_fifo_full; | |
1489 | wire ff_err_fifo_empty_d1_scanin; | |
1490 | wire ff_err_fifo_empty_d1_scanout; | |
1491 | wire [7:0] drif_drq0_clear_ent; | |
1492 | wire [7:0] drif_drq1_clear_ent; | |
1493 | wire drq0_req_rdwr_addr_sel; | |
1494 | wire [7:0] drq0_rd_adr_queue_sel; | |
1495 | wire [7:0] drif_err_rd_adr_queue_sel; | |
1496 | wire drq1_req_rdwr_addr_sel; | |
1497 | wire [7:0] drq1_rd_adr_queue_sel; | |
1498 | wire drif_err_ready; | |
1499 | wire drif_crc_retry_wait; | |
1500 | wire woq_empty; | |
1501 | wire woq_owr_empty; | |
1502 | wire [15:0] drif_err_rank_avail; | |
1503 | wire woq_wdata_send; | |
1504 | wire drif_err_rd_ready; | |
1505 | wire [7:0] drif_dimm_err_rd_avail; | |
1506 | wire drif_err_wr_ready; | |
1507 | wire rtr_cnt_is_zero_err; | |
1508 | wire wtr_cnt_is_zero_err; | |
1509 | wire wtw_cnt_is_zero_err; | |
1510 | wire rtw_cnt_is_zero_err; | |
1511 | wire [15:0] drif_err_bank_valid; | |
1512 | wire drif1_err_rd_picked; | |
1513 | wire drif1_err_wr_picked; | |
1514 | wire ff_err_rd_picked_d1_scanin; | |
1515 | wire ff_err_rd_picked_d1_scanout; | |
1516 | wire ff_err_fifo_d1_scanin; | |
1517 | wire ff_err_fifo_d1_scanout; | |
1518 | wire drif_crc_retry_wait_in; | |
1519 | wire ff_crc_retry_wait_scanin; | |
1520 | wire ff_crc_retry_wait_scanout; | |
1521 | wire [0:0] inv_drif_err_state_next; | |
1522 | wire [4:0] drif_err_state_next; | |
1523 | wire [0:0] inv_drif_err_state; | |
1524 | wire ff_err_state_scanin; | |
1525 | wire ff_err_state_scanout; | |
1526 | wire drif_mcu_error_mode_in; | |
1527 | wire ff_mcu_error_mode_scanin; | |
1528 | wire ff_mcu_error_mode_scanout; | |
1529 | wire reqq_scanin; | |
1530 | wire reqq_scanout; | |
1531 | wire [31:0] drif_scrub_addr_in; | |
1532 | wire drif_scrub_addr_en; | |
1533 | wire drif_scrub_addr_clr; | |
1534 | wire ff_scrub_addr_scanin; | |
1535 | wire ff_scrub_addr_scanout; | |
1536 | wire adrgen_scanin; | |
1537 | wire adrgen_scanout; | |
1538 | wire drif_scrub_addr_err_out; | |
1539 | wire [15:0] drif_pd_mode_scrub_rank; | |
1540 | wire [15:0] drif_pd_mode_scrub_incr; | |
1541 | wire [15:0] drif_pd_mode_scrub_decr; | |
1542 | wire [15:0] drif_pd_mode_err_incr; | |
1543 | wire [15:0] drif_pd_mode_err_decr; | |
1544 | wire [15:0] drif_pd_mode_err_rank; | |
1545 | wire [15:0] pdmc_pdx_pending; | |
1546 | wire [15:0] pdmc_pde_pending; | |
1547 | wire [15:0] drif_pdx_issued; | |
1548 | wire [15:0] pdmc_pdx_pending_priority; | |
1549 | wire [15:0] drif_pde_issued; | |
1550 | wire [15:0] pdmc_pde_pending_priority; | |
1551 | wire [7:0] drif_num_dimm_dec; | |
1552 | wire [15:0] drif_pdmc_enable; | |
1553 | wire [15:0] drif_refresh_mode; | |
1554 | wire [15:0] pdmc_rank_avail_out; | |
1555 | wire pdmc0_scanin; | |
1556 | wire pdmc0_scanout; | |
1557 | wire [15:0] drq0_pd_mode_rd_incr; | |
1558 | wire [15:0] drq1_pd_mode_rd_incr; | |
1559 | wire [15:0] drq0_pd_mode_wr_incr; | |
1560 | wire [15:0] drq1_pd_mode_wr_incr; | |
1561 | wire [15:0] drq0_pd_mode_rd_decr; | |
1562 | wire [15:0] drq1_pd_mode_rd_decr; | |
1563 | wire [15:0] woq_pd_mode_wr_decr; | |
1564 | wire [15:0] woq_err_pdm_wr_decr; | |
1565 | wire [15:0] woq_err_pdm_wr_incr; | |
1566 | wire pdmc1_scanin; | |
1567 | wire pdmc1_scanout; | |
1568 | wire pdmc2_scanin; | |
1569 | wire pdmc2_scanout; | |
1570 | wire pdmc3_scanin; | |
1571 | wire pdmc3_scanout; | |
1572 | wire pdmc4_scanin; | |
1573 | wire pdmc4_scanout; | |
1574 | wire pdmc5_scanin; | |
1575 | wire pdmc5_scanout; | |
1576 | wire pdmc6_scanin; | |
1577 | wire pdmc6_scanout; | |
1578 | wire pdmc7_scanin; | |
1579 | wire pdmc7_scanout; | |
1580 | wire pdmc8_scanin; | |
1581 | wire pdmc8_scanout; | |
1582 | wire pdmc9_scanin; | |
1583 | wire pdmc9_scanout; | |
1584 | wire pdmc10_scanin; | |
1585 | wire pdmc10_scanout; | |
1586 | wire pdmc11_scanin; | |
1587 | wire pdmc11_scanout; | |
1588 | wire pdmc12_scanin; | |
1589 | wire pdmc12_scanout; | |
1590 | wire pdmc13_scanin; | |
1591 | wire pdmc13_scanout; | |
1592 | wire pdmc14_scanin; | |
1593 | wire pdmc14_scanout; | |
1594 | wire pdmc15_scanin; | |
1595 | wire pdmc15_scanout; | |
1596 | wire drif_pdmc_idle; | |
1597 | wire drif_pdmc_idle_d0; | |
1598 | wire drif_pdmc_idle_d1; | |
1599 | wire drq0_rd_req; | |
1600 | wire drq0_wr_req; | |
1601 | wire drq1_rd_req; | |
1602 | wire drq1_wr_req; | |
1603 | wire drq0_empty; | |
1604 | wire drq1_empty; | |
1605 | wire si_0; | |
1606 | wire so_0; | |
1607 | wire spares_scanin; | |
1608 | wire spare0_buf_32x_unused; | |
1609 | wire spare0_nand3_8x_unused; | |
1610 | wire spare0_inv_8x_unused; | |
1611 | wire spare0_aoi22_4x_unused; | |
1612 | wire spare0_buf_8x_unused; | |
1613 | wire spare0_oai22_4x_unused; | |
1614 | wire spare0_inv_16x_unused; | |
1615 | wire spare0_nand2_16x_unused; | |
1616 | wire spare0_nor3_4x_unused; | |
1617 | wire spare0_nand2_8x_unused; | |
1618 | wire spare0_buf_16x_unused; | |
1619 | wire spare0_nor2_16x_unused; | |
1620 | wire spare0_inv_32x_unused; | |
1621 | wire si_1; | |
1622 | wire so_1; | |
1623 | wire spare1_flop_unused; | |
1624 | wire spare1_buf_32x_unused; | |
1625 | wire spare1_nand3_8x_unused; | |
1626 | wire spare1_inv_8x_unused; | |
1627 | wire spare1_aoi22_4x_unused; | |
1628 | wire spare1_buf_8x_unused; | |
1629 | wire spare1_oai22_4x_unused; | |
1630 | wire spare1_inv_16x_unused; | |
1631 | wire spare1_nand2_16x_unused; | |
1632 | wire spare1_nor3_4x_unused; | |
1633 | wire spare1_nand2_8x_unused; | |
1634 | wire spare1_buf_16x_unused; | |
1635 | wire spare1_nor2_16x_unused; | |
1636 | wire spare1_inv_32x_unused; | |
1637 | wire si_2; | |
1638 | wire so_2; | |
1639 | wire spare2_flop_unused; | |
1640 | wire spare2_buf_32x_unused; | |
1641 | wire spare2_nand3_8x_unused; | |
1642 | wire spare2_inv_8x_unused; | |
1643 | wire spare2_aoi22_4x_unused; | |
1644 | wire spare2_buf_8x_unused; | |
1645 | wire spare2_oai22_4x_unused; | |
1646 | wire spare2_inv_16x_unused; | |
1647 | wire spare2_nand2_16x_unused; | |
1648 | wire spare2_nor3_4x_unused; | |
1649 | wire spare2_nand2_8x_unused; | |
1650 | wire spare2_buf_16x_unused; | |
1651 | wire spare2_nor2_16x_unused; | |
1652 | wire spare2_inv_32x_unused; | |
1653 | wire si_3; | |
1654 | wire so_3; | |
1655 | wire spare3_flop_unused; | |
1656 | wire spare3_buf_32x_unused; | |
1657 | wire spare3_nand3_8x_unused; | |
1658 | wire spare3_inv_8x_unused; | |
1659 | wire spare3_aoi22_4x_unused; | |
1660 | wire spare3_buf_8x_unused; | |
1661 | wire spare3_oai22_4x_unused; | |
1662 | wire spare3_inv_16x_unused; | |
1663 | wire spare3_nand2_16x_unused; | |
1664 | wire spare3_nor3_4x_unused; | |
1665 | wire spare3_nand2_8x_unused; | |
1666 | wire spare3_buf_16x_unused; | |
1667 | wire spare3_nor2_16x_unused; | |
1668 | wire spare3_inv_32x_unused; | |
1669 | wire si_4; | |
1670 | wire so_4; | |
1671 | wire spare4_flop_unused; | |
1672 | wire spare4_buf_32x_unused; | |
1673 | wire spare4_nand3_8x_unused; | |
1674 | wire spare4_inv_8x_unused; | |
1675 | wire spare4_aoi22_4x_unused; | |
1676 | wire spare4_buf_8x_unused; | |
1677 | wire spare4_oai22_4x_unused; | |
1678 | wire spare4_inv_16x_unused; | |
1679 | wire spare4_nand2_16x_unused; | |
1680 | wire spare4_nor3_4x_unused; | |
1681 | wire spare4_nand2_8x_unused; | |
1682 | wire spare4_buf_16x_unused; | |
1683 | wire spare4_nor2_16x_unused; | |
1684 | wire spare4_inv_32x_unused; | |
1685 | wire si_5; | |
1686 | wire so_5; | |
1687 | wire spare5_flop_unused; | |
1688 | wire spare5_buf_32x_unused; | |
1689 | wire spare5_nand3_8x_unused; | |
1690 | wire spare5_inv_8x_unused; | |
1691 | wire spare5_aoi22_4x_unused; | |
1692 | wire spare5_buf_8x_unused; | |
1693 | wire spare5_oai22_4x_unused; | |
1694 | wire spare5_inv_16x_unused; | |
1695 | wire spare5_nand2_16x_unused; | |
1696 | wire spare5_nor3_4x_unused; | |
1697 | wire spare5_nand2_8x_unused; | |
1698 | wire spare5_buf_16x_unused; | |
1699 | wire spare5_nor2_16x_unused; | |
1700 | wire spare5_inv_32x_unused; | |
1701 | wire si_6; | |
1702 | wire so_6; | |
1703 | wire spare6_flop_unused; | |
1704 | wire spare6_buf_32x_unused; | |
1705 | wire spare6_nand3_8x_unused; | |
1706 | wire spare6_inv_8x_unused; | |
1707 | wire spare6_aoi22_4x_unused; | |
1708 | wire spare6_buf_8x_unused; | |
1709 | wire spare6_oai22_4x_unused; | |
1710 | wire spare6_inv_16x_unused; | |
1711 | wire spare6_nand2_16x_unused; | |
1712 | wire spare6_nor3_4x_unused; | |
1713 | wire spare6_nand2_8x_unused; | |
1714 | wire spare6_buf_16x_unused; | |
1715 | wire spare6_nor2_16x_unused; | |
1716 | wire spare6_inv_32x_unused; | |
1717 | wire si_7; | |
1718 | wire so_7; | |
1719 | wire spare7_flop_unused; | |
1720 | wire spare7_buf_32x_unused; | |
1721 | wire spare7_nand3_8x_unused; | |
1722 | wire spare7_inv_8x_unused; | |
1723 | wire spare7_aoi22_4x_unused; | |
1724 | wire spare7_buf_8x_unused; | |
1725 | wire spare7_oai22_4x_unused; | |
1726 | wire spare7_inv_16x_unused; | |
1727 | wire spare7_nand2_16x_unused; | |
1728 | wire spare7_nor3_4x_unused; | |
1729 | wire spare7_nand2_8x_unused; | |
1730 | wire spare7_buf_16x_unused; | |
1731 | wire spare7_nor2_16x_unused; | |
1732 | wire spare7_inv_32x_unused; | |
1733 | wire si_8; | |
1734 | wire so_8; | |
1735 | wire spare8_flop_unused; | |
1736 | wire spare8_buf_32x_unused; | |
1737 | wire spare8_nand3_8x_unused; | |
1738 | wire spare8_inv_8x_unused; | |
1739 | wire spare8_aoi22_4x_unused; | |
1740 | wire spare8_buf_8x_unused; | |
1741 | wire spare8_oai22_4x_unused; | |
1742 | wire spare8_inv_16x_unused; | |
1743 | wire spare8_nand2_16x_unused; | |
1744 | wire spare8_nor3_4x_unused; | |
1745 | wire spare8_nand2_8x_unused; | |
1746 | wire spare8_buf_16x_unused; | |
1747 | wire spare8_nor2_16x_unused; | |
1748 | wire spare8_inv_32x_unused; | |
1749 | wire si_9; | |
1750 | wire so_9; | |
1751 | wire spare9_flop_unused; | |
1752 | wire spare9_buf_32x_unused; | |
1753 | wire spare9_nand3_8x_unused; | |
1754 | wire spare9_inv_8x_unused; | |
1755 | wire spare9_aoi22_4x_unused; | |
1756 | wire spare9_buf_8x_unused; | |
1757 | wire spare9_oai22_4x_unused; | |
1758 | wire spare9_inv_16x_unused; | |
1759 | wire spare9_nand2_16x_unused; | |
1760 | wire spare9_nor3_4x_unused; | |
1761 | wire spare9_nand2_8x_unused; | |
1762 | wire spare9_buf_16x_unused; | |
1763 | wire spare9_nor2_16x_unused; | |
1764 | wire spare9_inv_32x_unused; | |
1765 | wire si_10; | |
1766 | wire so_10; | |
1767 | wire spare10_flop_unused; | |
1768 | wire spare10_buf_32x_unused; | |
1769 | wire spare10_nand3_8x_unused; | |
1770 | wire spare10_inv_8x_unused; | |
1771 | wire spare10_aoi22_4x_unused; | |
1772 | wire spare10_buf_8x_unused; | |
1773 | wire spare10_oai22_4x_unused; | |
1774 | wire spare10_inv_16x_unused; | |
1775 | wire spare10_nand2_16x_unused; | |
1776 | wire spare10_nor3_4x_unused; | |
1777 | wire spare10_nand2_8x_unused; | |
1778 | wire spare10_buf_16x_unused; | |
1779 | wire spare10_nor2_16x_unused; | |
1780 | wire spare10_inv_32x_unused; | |
1781 | wire si_11; | |
1782 | wire so_11; | |
1783 | wire spare11_flop_unused; | |
1784 | wire spare11_buf_32x_unused; | |
1785 | wire spare11_nand3_8x_unused; | |
1786 | wire spare11_inv_8x_unused; | |
1787 | wire spare11_aoi22_4x_unused; | |
1788 | wire spare11_buf_8x_unused; | |
1789 | wire spare11_oai22_4x_unused; | |
1790 | wire spare11_inv_16x_unused; | |
1791 | wire spare11_nand2_16x_unused; | |
1792 | wire spare11_nor3_4x_unused; | |
1793 | wire spare11_nand2_8x_unused; | |
1794 | wire spare11_buf_16x_unused; | |
1795 | wire spare11_nor2_16x_unused; | |
1796 | wire spare11_inv_32x_unused; | |
1797 | wire si_12; | |
1798 | wire so_12; | |
1799 | wire spare12_flop_unused; | |
1800 | wire spare12_buf_32x_unused; | |
1801 | wire spare12_nand3_8x_unused; | |
1802 | wire spare12_inv_8x_unused; | |
1803 | wire spare12_aoi22_4x_unused; | |
1804 | wire spare12_buf_8x_unused; | |
1805 | wire spare12_oai22_4x_unused; | |
1806 | wire spare12_inv_16x_unused; | |
1807 | wire spare12_nand2_16x_unused; | |
1808 | wire spare12_nor3_4x_unused; | |
1809 | wire spare12_nand2_8x_unused; | |
1810 | wire spare12_buf_16x_unused; | |
1811 | wire spare12_nor2_16x_unused; | |
1812 | wire spare12_inv_32x_unused; | |
1813 | wire si_13; | |
1814 | wire so_13; | |
1815 | wire spare13_flop_unused; | |
1816 | wire spare13_buf_32x_unused; | |
1817 | wire spare13_nand3_8x_unused; | |
1818 | wire spare13_inv_8x_unused; | |
1819 | wire spare13_aoi22_4x_unused; | |
1820 | wire spare13_buf_8x_unused; | |
1821 | wire spare13_oai22_4x_unused; | |
1822 | wire spare13_inv_16x_unused; | |
1823 | wire spare13_nand2_16x_unused; | |
1824 | wire spare13_nor3_4x_unused; | |
1825 | wire spare13_nand2_8x_unused; | |
1826 | wire spare13_buf_16x_unused; | |
1827 | wire spare13_nor2_16x_unused; | |
1828 | wire spare13_inv_32x_unused; | |
1829 | wire si_14; | |
1830 | wire so_14; | |
1831 | wire spare14_flop_unused; | |
1832 | wire spare14_buf_32x_unused; | |
1833 | wire spare14_nand3_8x_unused; | |
1834 | wire spare14_inv_8x_unused; | |
1835 | wire spare14_aoi22_4x_unused; | |
1836 | wire spare14_buf_8x_unused; | |
1837 | wire spare14_oai22_4x_unused; | |
1838 | wire spare14_inv_16x_unused; | |
1839 | wire spare14_nand2_16x_unused; | |
1840 | wire spare14_nor3_4x_unused; | |
1841 | wire spare14_nand2_8x_unused; | |
1842 | wire spare14_buf_16x_unused; | |
1843 | wire spare14_nor2_16x_unused; | |
1844 | wire spare14_inv_32x_unused; | |
1845 | wire si_15; | |
1846 | wire so_15; | |
1847 | wire spare15_flop_unused; | |
1848 | wire spare15_buf_32x_unused; | |
1849 | wire spare15_nand3_8x_unused; | |
1850 | wire spare15_inv_8x_unused; | |
1851 | wire spare15_aoi22_4x_unused; | |
1852 | wire spare15_buf_8x_unused; | |
1853 | wire spare15_oai22_4x_unused; | |
1854 | wire spare15_inv_16x_unused; | |
1855 | wire spare15_nand2_16x_unused; | |
1856 | wire spare15_nor3_4x_unused; | |
1857 | wire spare15_nand2_8x_unused; | |
1858 | wire spare15_buf_16x_unused; | |
1859 | wire spare15_nor2_16x_unused; | |
1860 | wire spare15_inv_32x_unused; | |
1861 | wire si_16; | |
1862 | wire so_16; | |
1863 | wire spare16_flop_unused; | |
1864 | wire spare16_buf_32x_unused; | |
1865 | wire spare16_nand3_8x_unused; | |
1866 | wire spare16_inv_8x_unused; | |
1867 | wire spare16_aoi22_4x_unused; | |
1868 | wire spare16_buf_8x_unused; | |
1869 | wire spare16_oai22_4x_unused; | |
1870 | wire spare16_inv_16x_unused; | |
1871 | wire spare16_nand2_16x_unused; | |
1872 | wire spare16_nor3_4x_unused; | |
1873 | wire spare16_nand2_8x_unused; | |
1874 | wire spare16_buf_16x_unused; | |
1875 | wire spare16_nor2_16x_unused; | |
1876 | wire spare16_inv_32x_unused; | |
1877 | wire si_17; | |
1878 | wire so_17; | |
1879 | wire spare17_flop_unused; | |
1880 | wire spare17_buf_32x_unused; | |
1881 | wire spare17_nand3_8x_unused; | |
1882 | wire spare17_inv_8x_unused; | |
1883 | wire spare17_aoi22_4x_unused; | |
1884 | wire spare17_buf_8x_unused; | |
1885 | wire spare17_oai22_4x_unused; | |
1886 | wire spare17_inv_16x_unused; | |
1887 | wire spare17_nand2_16x_unused; | |
1888 | wire spare17_nor3_4x_unused; | |
1889 | wire spare17_nand2_8x_unused; | |
1890 | wire spare17_buf_16x_unused; | |
1891 | wire spare17_nor2_16x_unused; | |
1892 | wire spare17_inv_32x_unused; | |
1893 | wire si_18; | |
1894 | wire so_18; | |
1895 | wire spare18_flop_unused; | |
1896 | wire spare18_buf_32x_unused; | |
1897 | wire spare18_nand3_8x_unused; | |
1898 | wire spare18_inv_8x_unused; | |
1899 | wire spare18_aoi22_4x_unused; | |
1900 | wire spare18_buf_8x_unused; | |
1901 | wire spare18_oai22_4x_unused; | |
1902 | wire spare18_inv_16x_unused; | |
1903 | wire spare18_nand2_16x_unused; | |
1904 | wire spare18_nor3_4x_unused; | |
1905 | wire spare18_nand2_8x_unused; | |
1906 | wire spare18_buf_16x_unused; | |
1907 | wire spare18_nor2_16x_unused; | |
1908 | wire spare18_inv_32x_unused; | |
1909 | wire si_19; | |
1910 | wire so_19; | |
1911 | wire spare19_flop_unused; | |
1912 | wire spare19_buf_32x_unused; | |
1913 | wire spare19_nand3_8x_unused; | |
1914 | wire spare19_inv_8x_unused; | |
1915 | wire spare19_aoi22_4x_unused; | |
1916 | wire spare19_buf_8x_unused; | |
1917 | wire spare19_oai22_4x_unused; | |
1918 | wire spare19_inv_16x_unused; | |
1919 | wire spare19_nand2_16x_unused; | |
1920 | wire spare19_nor3_4x_unused; | |
1921 | wire spare19_nand2_8x_unused; | |
1922 | wire spare19_buf_16x_unused; | |
1923 | wire spare19_nor2_16x_unused; | |
1924 | wire spare19_inv_32x_unused; | |
1925 | wire si_20; | |
1926 | wire so_20; | |
1927 | wire spare20_flop_unused; | |
1928 | wire spare20_buf_32x_unused; | |
1929 | wire spare20_nand3_8x_unused; | |
1930 | wire spare20_inv_8x_unused; | |
1931 | wire spare20_aoi22_4x_unused; | |
1932 | wire spare20_buf_8x_unused; | |
1933 | wire spare20_oai22_4x_unused; | |
1934 | wire spare20_inv_16x_unused; | |
1935 | wire spare20_nand2_16x_unused; | |
1936 | wire spare20_nor3_4x_unused; | |
1937 | wire spare20_nand2_8x_unused; | |
1938 | wire spare20_buf_16x_unused; | |
1939 | wire spare20_nor2_16x_unused; | |
1940 | wire spare20_inv_32x_unused; | |
1941 | wire si_21; | |
1942 | wire so_21; | |
1943 | wire spare21_flop_unused; | |
1944 | wire spare21_buf_32x_unused; | |
1945 | wire spare21_nand3_8x_unused; | |
1946 | wire spare21_inv_8x_unused; | |
1947 | wire spare21_aoi22_4x_unused; | |
1948 | wire spare21_buf_8x_unused; | |
1949 | wire spare21_oai22_4x_unused; | |
1950 | wire spare21_inv_16x_unused; | |
1951 | wire spare21_nand2_16x_unused; | |
1952 | wire spare21_nor3_4x_unused; | |
1953 | wire spare21_nand2_8x_unused; | |
1954 | wire spare21_buf_16x_unused; | |
1955 | wire spare21_nor2_16x_unused; | |
1956 | wire spare21_inv_32x_unused; | |
1957 | wire si_22; | |
1958 | wire so_22; | |
1959 | wire spare22_flop_unused; | |
1960 | wire spare22_buf_32x_unused; | |
1961 | wire spare22_nand3_8x_unused; | |
1962 | wire spare22_inv_8x_unused; | |
1963 | wire spare22_aoi22_4x_unused; | |
1964 | wire spare22_buf_8x_unused; | |
1965 | wire spare22_oai22_4x_unused; | |
1966 | wire spare22_inv_16x_unused; | |
1967 | wire spare22_nand2_16x_unused; | |
1968 | wire spare22_nor3_4x_unused; | |
1969 | wire spare22_nand2_8x_unused; | |
1970 | wire spare22_buf_16x_unused; | |
1971 | wire spare22_nor2_16x_unused; | |
1972 | wire spare22_inv_32x_unused; | |
1973 | wire si_23; | |
1974 | wire so_23; | |
1975 | wire spare23_flop_unused; | |
1976 | wire spare23_buf_32x_unused; | |
1977 | wire spare23_nand3_8x_unused; | |
1978 | wire spare23_inv_8x_unused; | |
1979 | wire spare23_aoi22_4x_unused; | |
1980 | wire spare23_buf_8x_unused; | |
1981 | wire spare23_oai22_4x_unused; | |
1982 | wire spare23_inv_16x_unused; | |
1983 | wire spare23_nand2_16x_unused; | |
1984 | wire spare23_nor3_4x_unused; | |
1985 | wire spare23_nand2_8x_unused; | |
1986 | wire spare23_buf_16x_unused; | |
1987 | wire spare23_nor2_16x_unused; | |
1988 | wire spare23_inv_32x_unused; | |
1989 | wire si_24; | |
1990 | wire so_24; | |
1991 | wire spare24_flop_unused; | |
1992 | wire spare24_buf_32x_unused; | |
1993 | wire spare24_nand3_8x_unused; | |
1994 | wire spare24_inv_8x_unused; | |
1995 | wire spare24_aoi22_4x_unused; | |
1996 | wire spare24_buf_8x_unused; | |
1997 | wire spare24_oai22_4x_unused; | |
1998 | wire spare24_inv_16x_unused; | |
1999 | wire spare24_nand2_16x_unused; | |
2000 | wire spare24_nor3_4x_unused; | |
2001 | wire spare24_nand2_8x_unused; | |
2002 | wire spare24_buf_16x_unused; | |
2003 | wire spare24_nor2_16x_unused; | |
2004 | wire spare24_inv_32x_unused; | |
2005 | wire si_25; | |
2006 | wire so_25; | |
2007 | wire spare25_flop_unused; | |
2008 | wire spare25_buf_32x_unused; | |
2009 | wire spare25_nand3_8x_unused; | |
2010 | wire spare25_inv_8x_unused; | |
2011 | wire spare25_aoi22_4x_unused; | |
2012 | wire spare25_buf_8x_unused; | |
2013 | wire spare25_oai22_4x_unused; | |
2014 | wire spare25_inv_16x_unused; | |
2015 | wire spare25_nand2_16x_unused; | |
2016 | wire spare25_nor3_4x_unused; | |
2017 | wire spare25_nand2_8x_unused; | |
2018 | wire spare25_buf_16x_unused; | |
2019 | wire spare25_nor2_16x_unused; | |
2020 | wire spare25_inv_32x_unused; | |
2021 | wire si_26; | |
2022 | wire so_26; | |
2023 | wire spare26_flop_unused; | |
2024 | wire spare26_buf_32x_unused; | |
2025 | wire spare26_nand3_8x_unused; | |
2026 | wire spare26_inv_8x_unused; | |
2027 | wire spare26_aoi22_4x_unused; | |
2028 | wire spare26_buf_8x_unused; | |
2029 | wire spare26_oai22_4x_unused; | |
2030 | wire spare26_inv_16x_unused; | |
2031 | wire spare26_nand2_16x_unused; | |
2032 | wire spare26_nor3_4x_unused; | |
2033 | wire spare26_nand2_8x_unused; | |
2034 | wire spare26_buf_16x_unused; | |
2035 | wire spare26_nor2_16x_unused; | |
2036 | wire spare26_inv_32x_unused; | |
2037 | wire si_27; | |
2038 | wire so_27; | |
2039 | wire spare27_flop_unused; | |
2040 | wire spare27_buf_32x_unused; | |
2041 | wire spare27_nand3_8x_unused; | |
2042 | wire spare27_inv_8x_unused; | |
2043 | wire spare27_aoi22_4x_unused; | |
2044 | wire spare27_buf_8x_unused; | |
2045 | wire spare27_oai22_4x_unused; | |
2046 | wire spare27_inv_16x_unused; | |
2047 | wire spare27_nand2_16x_unused; | |
2048 | wire spare27_nor3_4x_unused; | |
2049 | wire spare27_nand2_8x_unused; | |
2050 | wire spare27_buf_16x_unused; | |
2051 | wire spare27_nor2_16x_unused; | |
2052 | wire spare27_inv_32x_unused; | |
2053 | wire si_28; | |
2054 | wire so_28; | |
2055 | wire spare28_flop_unused; | |
2056 | wire spare28_buf_32x_unused; | |
2057 | wire spare28_nand3_8x_unused; | |
2058 | wire spare28_inv_8x_unused; | |
2059 | wire spare28_aoi22_4x_unused; | |
2060 | wire spare28_buf_8x_unused; | |
2061 | wire spare28_oai22_4x_unused; | |
2062 | wire spare28_inv_16x_unused; | |
2063 | wire spare28_nand2_16x_unused; | |
2064 | wire spare28_nor3_4x_unused; | |
2065 | wire spare28_nand2_8x_unused; | |
2066 | wire spare28_buf_16x_unused; | |
2067 | wire spare28_nor2_16x_unused; | |
2068 | wire spare28_inv_32x_unused; | |
2069 | wire si_29; | |
2070 | wire so_29; | |
2071 | wire spare29_flop_unused; | |
2072 | wire spare29_buf_32x_unused; | |
2073 | wire spare29_nand3_8x_unused; | |
2074 | wire spare29_inv_8x_unused; | |
2075 | wire spare29_aoi22_4x_unused; | |
2076 | wire spare29_buf_8x_unused; | |
2077 | wire spare29_oai22_4x_unused; | |
2078 | wire spare29_inv_16x_unused; | |
2079 | wire spare29_nand2_16x_unused; | |
2080 | wire spare29_nor3_4x_unused; | |
2081 | wire spare29_nand2_8x_unused; | |
2082 | wire spare29_buf_16x_unused; | |
2083 | wire spare29_nor2_16x_unused; | |
2084 | wire spare29_inv_32x_unused; | |
2085 | wire si_30; | |
2086 | wire so_30; | |
2087 | wire spare30_flop_unused; | |
2088 | wire spare30_buf_32x_unused; | |
2089 | wire spare30_nand3_8x_unused; | |
2090 | wire spare30_inv_8x_unused; | |
2091 | wire spare30_aoi22_4x_unused; | |
2092 | wire spare30_buf_8x_unused; | |
2093 | wire spare30_oai22_4x_unused; | |
2094 | wire spare30_inv_16x_unused; | |
2095 | wire spare30_nand2_16x_unused; | |
2096 | wire spare30_nor3_4x_unused; | |
2097 | wire spare30_nand2_8x_unused; | |
2098 | wire spare30_buf_16x_unused; | |
2099 | wire spare30_nor2_16x_unused; | |
2100 | wire spare30_inv_32x_unused; | |
2101 | wire si_31; | |
2102 | wire so_31; | |
2103 | wire spare31_flop_unused; | |
2104 | wire spare31_buf_32x_unused; | |
2105 | wire spare31_nand3_8x_unused; | |
2106 | wire spare31_inv_8x_unused; | |
2107 | wire spare31_aoi22_4x_unused; | |
2108 | wire spare31_buf_8x_unused; | |
2109 | wire spare31_oai22_4x_unused; | |
2110 | wire spare31_inv_16x_unused; | |
2111 | wire spare31_nand2_16x_unused; | |
2112 | wire spare31_nor3_4x_unused; | |
2113 | wire spare31_nand2_8x_unused; | |
2114 | wire spare31_buf_16x_unused; | |
2115 | wire spare31_nor2_16x_unused; | |
2116 | wire spare31_inv_32x_unused; | |
2117 | wire si_32; | |
2118 | wire so_32; | |
2119 | wire spare32_flop_unused; | |
2120 | wire spare32_buf_32x_unused; | |
2121 | wire spare32_nand3_8x_unused; | |
2122 | wire spare32_inv_8x_unused; | |
2123 | wire spare32_aoi22_4x_unused; | |
2124 | wire spare32_buf_8x_unused; | |
2125 | wire spare32_oai22_4x_unused; | |
2126 | wire spare32_inv_16x_unused; | |
2127 | wire spare32_nand2_16x_unused; | |
2128 | wire spare32_nor3_4x_unused; | |
2129 | wire spare32_nand2_8x_unused; | |
2130 | wire spare32_buf_16x_unused; | |
2131 | wire spare32_nor2_16x_unused; | |
2132 | wire spare32_inv_32x_unused; | |
2133 | wire si_33; | |
2134 | wire so_33; | |
2135 | wire spare33_flop_unused; | |
2136 | wire spare33_buf_32x_unused; | |
2137 | wire spare33_nand3_8x_unused; | |
2138 | wire spare33_inv_8x_unused; | |
2139 | wire spare33_aoi22_4x_unused; | |
2140 | wire spare33_buf_8x_unused; | |
2141 | wire spare33_oai22_4x_unused; | |
2142 | wire spare33_inv_16x_unused; | |
2143 | wire spare33_nand2_16x_unused; | |
2144 | wire spare33_nor3_4x_unused; | |
2145 | wire spare33_nand2_8x_unused; | |
2146 | wire spare33_buf_16x_unused; | |
2147 | wire spare33_nor2_16x_unused; | |
2148 | wire spare33_inv_32x_unused; | |
2149 | wire si_34; | |
2150 | wire so_34; | |
2151 | wire spare34_flop_unused; | |
2152 | wire spare34_buf_32x_unused; | |
2153 | wire spare34_nand3_8x_unused; | |
2154 | wire spare34_inv_8x_unused; | |
2155 | wire spare34_aoi22_4x_unused; | |
2156 | wire spare34_buf_8x_unused; | |
2157 | wire spare34_oai22_4x_unused; | |
2158 | wire spare34_inv_16x_unused; | |
2159 | wire spare34_nand2_16x_unused; | |
2160 | wire spare34_nor3_4x_unused; | |
2161 | wire spare34_nand2_8x_unused; | |
2162 | wire spare34_buf_16x_unused; | |
2163 | wire spare34_nor2_16x_unused; | |
2164 | wire spare34_inv_32x_unused; | |
2165 | wire si_35; | |
2166 | wire so_35; | |
2167 | wire spare35_flop_unused; | |
2168 | wire spare35_buf_32x_unused; | |
2169 | wire spare35_nand3_8x_unused; | |
2170 | wire spare35_inv_8x_unused; | |
2171 | wire spare35_aoi22_4x_unused; | |
2172 | wire spare35_buf_8x_unused; | |
2173 | wire spare35_oai22_4x_unused; | |
2174 | wire spare35_inv_16x_unused; | |
2175 | wire spare35_nand2_16x_unused; | |
2176 | wire spare35_nor3_4x_unused; | |
2177 | wire spare35_nand2_8x_unused; | |
2178 | wire spare35_buf_16x_unused; | |
2179 | wire spare35_nor2_16x_unused; | |
2180 | wire spare35_inv_32x_unused; | |
2181 | wire si_36; | |
2182 | wire so_36; | |
2183 | wire spare36_flop_unused; | |
2184 | wire spare36_buf_32x_unused; | |
2185 | wire spare36_nand3_8x_unused; | |
2186 | wire spare36_inv_8x_unused; | |
2187 | wire spare36_aoi22_4x_unused; | |
2188 | wire spare36_buf_8x_unused; | |
2189 | wire spare36_oai22_4x_unused; | |
2190 | wire spare36_inv_16x_unused; | |
2191 | wire spare36_nand2_16x_unused; | |
2192 | wire spare36_nor3_4x_unused; | |
2193 | wire spare36_nand2_8x_unused; | |
2194 | wire spare36_buf_16x_unused; | |
2195 | wire spare36_nor2_16x_unused; | |
2196 | wire spare36_inv_32x_unused; | |
2197 | wire si_37; | |
2198 | wire so_37; | |
2199 | wire spare37_flop_unused; | |
2200 | wire spare37_buf_32x_unused; | |
2201 | wire spare37_nand3_8x_unused; | |
2202 | wire spare37_inv_8x_unused; | |
2203 | wire spare37_aoi22_4x_unused; | |
2204 | wire spare37_buf_8x_unused; | |
2205 | wire spare37_oai22_4x_unused; | |
2206 | wire spare37_inv_16x_unused; | |
2207 | wire spare37_nand2_16x_unused; | |
2208 | wire spare37_nor3_4x_unused; | |
2209 | wire spare37_nand2_8x_unused; | |
2210 | wire spare37_buf_16x_unused; | |
2211 | wire spare37_nor2_16x_unused; | |
2212 | wire spare37_inv_32x_unused; | |
2213 | wire si_38; | |
2214 | wire so_38; | |
2215 | wire spare38_flop_unused; | |
2216 | wire spare38_buf_32x_unused; | |
2217 | wire spare38_nand3_8x_unused; | |
2218 | wire spare38_inv_8x_unused; | |
2219 | wire spare38_aoi22_4x_unused; | |
2220 | wire spare38_buf_8x_unused; | |
2221 | wire spare38_oai22_4x_unused; | |
2222 | wire spare38_inv_16x_unused; | |
2223 | wire spare38_nand2_16x_unused; | |
2224 | wire spare38_nor3_4x_unused; | |
2225 | wire spare38_nand2_8x_unused; | |
2226 | wire spare38_buf_16x_unused; | |
2227 | wire spare38_nor2_16x_unused; | |
2228 | wire spare38_inv_32x_unused; | |
2229 | wire si_39; | |
2230 | wire so_39; | |
2231 | wire spare39_flop_unused; | |
2232 | wire spare39_buf_32x_unused; | |
2233 | wire spare39_nand3_8x_unused; | |
2234 | wire spare39_inv_8x_unused; | |
2235 | wire spare39_aoi22_4x_unused; | |
2236 | wire spare39_buf_8x_unused; | |
2237 | wire spare39_oai22_4x_unused; | |
2238 | wire spare39_inv_16x_unused; | |
2239 | wire spare39_nand2_16x_unused; | |
2240 | wire spare39_nor3_4x_unused; | |
2241 | wire spare39_nand2_8x_unused; | |
2242 | wire spare39_buf_16x_unused; | |
2243 | wire spare39_nor2_16x_unused; | |
2244 | wire spare39_inv_32x_unused; | |
2245 | wire si_40; | |
2246 | wire so_40; | |
2247 | wire spare40_flop_unused; | |
2248 | wire spare40_buf_32x_unused; | |
2249 | wire spare40_nand3_8x_unused; | |
2250 | wire spare40_inv_8x_unused; | |
2251 | wire spare40_aoi22_4x_unused; | |
2252 | wire spare40_buf_8x_unused; | |
2253 | wire spare40_oai22_4x_unused; | |
2254 | wire spare40_inv_16x_unused; | |
2255 | wire spare40_nand2_16x_unused; | |
2256 | wire spare40_nor3_4x_unused; | |
2257 | wire spare40_nand2_8x_unused; | |
2258 | wire spare40_buf_16x_unused; | |
2259 | wire spare40_nor2_16x_unused; | |
2260 | wire spare40_inv_32x_unused; | |
2261 | wire si_41; | |
2262 | wire so_41; | |
2263 | wire spare41_flop_unused; | |
2264 | wire spare41_buf_32x_unused; | |
2265 | wire spare41_nand3_8x_unused; | |
2266 | wire spare41_inv_8x_unused; | |
2267 | wire spare41_aoi22_4x_unused; | |
2268 | wire spare41_buf_8x_unused; | |
2269 | wire spare41_oai22_4x_unused; | |
2270 | wire spare41_inv_16x_unused; | |
2271 | wire spare41_nand2_16x_unused; | |
2272 | wire spare41_nor3_4x_unused; | |
2273 | wire spare41_nand2_8x_unused; | |
2274 | wire spare41_buf_16x_unused; | |
2275 | wire spare41_nor2_16x_unused; | |
2276 | wire spare41_inv_32x_unused; | |
2277 | wire si_42; | |
2278 | wire so_42; | |
2279 | wire spare42_flop_unused; | |
2280 | wire spare42_buf_32x_unused; | |
2281 | wire spare42_nand3_8x_unused; | |
2282 | wire spare42_inv_8x_unused; | |
2283 | wire spare42_aoi22_4x_unused; | |
2284 | wire spare42_buf_8x_unused; | |
2285 | wire spare42_oai22_4x_unused; | |
2286 | wire spare42_inv_16x_unused; | |
2287 | wire spare42_nand2_16x_unused; | |
2288 | wire spare42_nor3_4x_unused; | |
2289 | wire spare42_nand2_8x_unused; | |
2290 | wire spare42_buf_16x_unused; | |
2291 | wire spare42_nor2_16x_unused; | |
2292 | wire spare42_inv_32x_unused; | |
2293 | wire si_43; | |
2294 | wire so_43; | |
2295 | wire spare43_flop_unused; | |
2296 | wire spare43_buf_32x_unused; | |
2297 | wire spare43_nand3_8x_unused; | |
2298 | wire spare43_inv_8x_unused; | |
2299 | wire spare43_aoi22_4x_unused; | |
2300 | wire spare43_buf_8x_unused; | |
2301 | wire spare43_oai22_4x_unused; | |
2302 | wire spare43_inv_16x_unused; | |
2303 | wire spare43_nand2_16x_unused; | |
2304 | wire spare43_nor3_4x_unused; | |
2305 | wire spare43_nand2_8x_unused; | |
2306 | wire spare43_buf_16x_unused; | |
2307 | wire spare43_nor2_16x_unused; | |
2308 | wire spare43_inv_32x_unused; | |
2309 | wire si_44; | |
2310 | wire so_44; | |
2311 | wire spare44_flop_unused; | |
2312 | wire spare44_buf_32x_unused; | |
2313 | wire spare44_nand3_8x_unused; | |
2314 | wire spare44_inv_8x_unused; | |
2315 | wire spare44_aoi22_4x_unused; | |
2316 | wire spare44_buf_8x_unused; | |
2317 | wire spare44_oai22_4x_unused; | |
2318 | wire spare44_inv_16x_unused; | |
2319 | wire spare44_nand2_16x_unused; | |
2320 | wire spare44_nor3_4x_unused; | |
2321 | wire spare44_nand2_8x_unused; | |
2322 | wire spare44_buf_16x_unused; | |
2323 | wire spare44_nor2_16x_unused; | |
2324 | wire spare44_inv_32x_unused; | |
2325 | wire si_45; | |
2326 | wire so_45; | |
2327 | wire spare45_flop_unused; | |
2328 | wire spare45_buf_32x_unused; | |
2329 | wire spare45_nand3_8x_unused; | |
2330 | wire spare45_inv_8x_unused; | |
2331 | wire spare45_aoi22_4x_unused; | |
2332 | wire spare45_buf_8x_unused; | |
2333 | wire spare45_oai22_4x_unused; | |
2334 | wire spare45_inv_16x_unused; | |
2335 | wire spare45_nand2_16x_unused; | |
2336 | wire spare45_nor3_4x_unused; | |
2337 | wire spare45_nand2_8x_unused; | |
2338 | wire spare45_buf_16x_unused; | |
2339 | wire spare45_nor2_16x_unused; | |
2340 | wire spare45_inv_32x_unused; | |
2341 | wire si_46; | |
2342 | wire so_46; | |
2343 | wire spare46_flop_unused; | |
2344 | wire spare46_buf_32x_unused; | |
2345 | wire spare46_nand3_8x_unused; | |
2346 | wire spare46_inv_8x_unused; | |
2347 | wire spare46_aoi22_4x_unused; | |
2348 | wire spare46_buf_8x_unused; | |
2349 | wire spare46_oai22_4x_unused; | |
2350 | wire spare46_inv_16x_unused; | |
2351 | wire spare46_nand2_16x_unused; | |
2352 | wire spare46_nor3_4x_unused; | |
2353 | wire spare46_nand2_8x_unused; | |
2354 | wire spare46_buf_16x_unused; | |
2355 | wire spare46_nor2_16x_unused; | |
2356 | wire spare46_inv_32x_unused; | |
2357 | wire si_47; | |
2358 | wire so_47; | |
2359 | wire spare47_flop_unused; | |
2360 | wire spare47_buf_32x_unused; | |
2361 | wire spare47_nand3_8x_unused; | |
2362 | wire spare47_inv_8x_unused; | |
2363 | wire spare47_aoi22_4x_unused; | |
2364 | wire spare47_buf_8x_unused; | |
2365 | wire spare47_oai22_4x_unused; | |
2366 | wire spare47_inv_16x_unused; | |
2367 | wire spare47_nand2_16x_unused; | |
2368 | wire spare47_nor3_4x_unused; | |
2369 | wire spare47_nand2_8x_unused; | |
2370 | wire spare47_buf_16x_unused; | |
2371 | wire spare47_nor2_16x_unused; | |
2372 | wire spare47_inv_32x_unused; | |
2373 | wire si_48; | |
2374 | wire so_48; | |
2375 | wire spare48_flop_unused; | |
2376 | wire spare48_buf_32x_unused; | |
2377 | wire spare48_nand3_8x_unused; | |
2378 | wire spare48_inv_8x_unused; | |
2379 | wire spare48_aoi22_4x_unused; | |
2380 | wire spare48_buf_8x_unused; | |
2381 | wire spare48_oai22_4x_unused; | |
2382 | wire spare48_inv_16x_unused; | |
2383 | wire spare48_nand2_16x_unused; | |
2384 | wire spare48_nor3_4x_unused; | |
2385 | wire spare48_nand2_8x_unused; | |
2386 | wire spare48_buf_16x_unused; | |
2387 | wire spare48_nor2_16x_unused; | |
2388 | wire spare48_inv_32x_unused; | |
2389 | wire spares_scanout; | |
2390 | wire drif_scrub_write_req; | |
2391 | wire [2:0] drif_tot_ranks; | |
2392 | wire drif_power_down_mode; | |
2393 | wire mcu_ddp_clk_enable; | |
2394 | wire [2:0] woq_entry_valid; | |
2395 | wire [2:0] woq_wr1_index_picked; | |
2396 | wire [2:0] woq_wr2_index_picked; | |
2397 | wire [2:0] woq_wr1_wdq_index_picked; | |
2398 | wire [2:0] woq_wr2_wdq_index_picked; | |
2399 | wire drq0_wr_entry0_rank; | |
2400 | wire drq0_wr_entry1_rank; | |
2401 | wire drq0_wr_entry2_rank; | |
2402 | wire drq0_wr_entry3_rank; | |
2403 | wire drq0_wr_entry4_rank; | |
2404 | wire drq0_wr_entry5_rank; | |
2405 | wire drq0_wr_entry6_rank; | |
2406 | wire drq0_wr_entry7_rank; | |
2407 | wire [2:0] drq0_wr_entry0_dimm; | |
2408 | wire [2:0] drq0_wr_entry1_dimm; | |
2409 | wire [2:0] drq0_wr_entry2_dimm; | |
2410 | wire [2:0] drq0_wr_entry3_dimm; | |
2411 | wire [2:0] drq0_wr_entry4_dimm; | |
2412 | wire [2:0] drq0_wr_entry5_dimm; | |
2413 | wire [2:0] drq0_wr_entry6_dimm; | |
2414 | wire [2:0] drq0_wr_entry7_dimm; | |
2415 | wire drq0_rdq_full; | |
2416 | wire [2:0] drq0_wr_index_picked; | |
2417 | wire [2:0] drq0_wr_id_picked; | |
2418 | wire drq1_wr_entry0_rank; | |
2419 | wire drq1_wr_entry1_rank; | |
2420 | wire drq1_wr_entry2_rank; | |
2421 | wire drq1_wr_entry3_rank; | |
2422 | wire drq1_wr_entry4_rank; | |
2423 | wire drq1_wr_entry5_rank; | |
2424 | wire drq1_wr_entry6_rank; | |
2425 | wire drq1_wr_entry7_rank; | |
2426 | wire [2:0] drq1_wr_entry0_dimm; | |
2427 | wire [2:0] drq1_wr_entry1_dimm; | |
2428 | wire [2:0] drq1_wr_entry2_dimm; | |
2429 | wire [2:0] drq1_wr_entry3_dimm; | |
2430 | wire [2:0] drq1_wr_entry4_dimm; | |
2431 | wire [2:0] drq1_wr_entry5_dimm; | |
2432 | wire [2:0] drq1_wr_entry6_dimm; | |
2433 | wire [2:0] drq1_wr_entry7_dimm; | |
2434 | wire drq1_rdq_full; | |
2435 | wire [2:0] drq1_wr_index_picked; | |
2436 | wire [2:0] drq1_wr_id_picked; | |
2437 | ||
2438 | ||
2439 | // PAD interface | |
2440 | output drif_fail_over_mode; // indicates writedp and readdp in failover mode | |
2441 | output [34:0] drif_fail_over_mask; // mask and complement for failover mode | |
2442 | output [34:0] drif_fail_over_mask_l; | |
2443 | output drq0_rdq_free; // entry freed in read request queue0 | |
2444 | output drq1_rdq_free; // entry freed in read request queue1 | |
2445 | output [7:0] woq0_wdq_entry_free; | |
2446 | output [7:0] woq1_wdq_entry_free; | |
2447 | ||
2448 | // addressing mode info to rdpctl | |
2449 | output [2:0] drif_num_dimms; | |
2450 | output drif_addr_bank_low_sel; | |
2451 | output [1:0] drif_mem_type; | |
2452 | output drif_stacked_dimm; | |
2453 | output drif_single_channel_mode; | |
2454 | output drif_branch_disabled; | |
2455 | ||
2456 | output [3:0] drif_wdata_sel; // writedp select between wdq0, wdq1 and scrub data | |
2457 | ||
2458 | // register read data to rdata_ctl | |
2459 | output drif_rdata_ack_vld; | |
2460 | output drif_rdata_nack_vld; | |
2461 | output [63:0] drif_rdata_data; | |
2462 | ||
2463 | // error injection info to write dp | |
2464 | output drif_err_inj_enable; | |
2465 | output [15:0] drif_err_mask_reg; | |
2466 | ||
2467 | output drif_send_info_val; // read return information valid | |
2468 | output [19:0] drif_send_info; // read return information (l2bank, parity, etc.) | |
2469 | ||
2470 | // Read enables and addresses for write data queues | |
2471 | output drif0_wdq_rd; | |
2472 | output drif1_wdq_rd; | |
2473 | output [4:0] drif_wdq_radr; | |
2474 | ||
2475 | output [1:0] drif_rascas_adr_sel; // select between bank 0 and 1 request queues | |
2476 | output [1:0] drif_rascas_wr1_adr_sel; // select between bank 0 and 1 request queues | |
2477 | output [1:0] drif_rascas_wr2_adr_sel; // select between bank 0 and 1 request queues | |
2478 | ||
2479 | output [31:0] drif_scrub_addr; | |
2480 | ||
2481 | // bank 0 and 1 read request queue load enables | |
2482 | output drq0_rd_adr_queue7_en; | |
2483 | output drq0_rd_adr_queue6_en; | |
2484 | output drq0_rd_adr_queue5_en; | |
2485 | output drq0_rd_adr_queue4_en; | |
2486 | output drq0_rd_adr_queue3_en; | |
2487 | output drq0_rd_adr_queue2_en; | |
2488 | output drq0_rd_adr_queue1_en; | |
2489 | output drq0_rd_adr_queue0_en; | |
2490 | output drq1_rd_adr_queue7_en; | |
2491 | output drq1_rd_adr_queue6_en; | |
2492 | output drq1_rd_adr_queue5_en; | |
2493 | output drq1_rd_adr_queue4_en; | |
2494 | output drq1_rd_adr_queue3_en; | |
2495 | output drq1_rd_adr_queue2_en; | |
2496 | output drq1_rd_adr_queue1_en; | |
2497 | output drq1_rd_adr_queue0_en; | |
2498 | ||
2499 | // bank 0 and 1 write request queue load enables | |
2500 | output drq0_wr_adr_queue7_en; | |
2501 | output drq0_wr_adr_queue6_en; | |
2502 | output drq0_wr_adr_queue5_en; | |
2503 | output drq0_wr_adr_queue4_en; | |
2504 | output drq0_wr_adr_queue3_en; | |
2505 | output drq0_wr_adr_queue2_en; | |
2506 | output drq0_wr_adr_queue1_en; | |
2507 | output drq0_wr_adr_queue0_en; | |
2508 | output drq1_wr_adr_queue7_en; | |
2509 | output drq1_wr_adr_queue6_en; | |
2510 | output drq1_wr_adr_queue5_en; | |
2511 | output drq1_wr_adr_queue4_en; | |
2512 | output drq1_wr_adr_queue3_en; | |
2513 | output drq1_wr_adr_queue2_en; | |
2514 | output drq1_wr_adr_queue1_en; | |
2515 | output drq1_wr_adr_queue0_en; | |
2516 | ||
2517 | // read and write request queue output selects | |
2518 | output [7:0] drif0_rd_adr_queue_sel; | |
2519 | output [7:0] drif1_rd_adr_queue_sel; | |
2520 | output [7:0] woq_wr_adr_queue_sel; | |
2521 | output [7:0] woq_wr1_adr_queue_sel; | |
2522 | output [7:0] woq_wr2_adr_queue_sel; | |
2523 | ||
2524 | // select between read and write request queues for a bank | |
2525 | output [1:0] drif0_req_rdwr_addr_sel; | |
2526 | output [1:0] drif1_req_rdwr_addr_sel; | |
2527 | ||
2528 | output drif_l2poison_qw; // data poison information to writedp | |
2529 | output drif_wadr_parity; // address parity for writedp | |
2530 | ||
2531 | output mcu_pt_sync_out; // power throttling sync; resets power | |
2532 | // throttling counters in all mcu banks | |
2533 | // when any power throttling register is | |
2534 | // written | |
2535 | ||
2536 | output drif_scrub_rwen; // shift data in/out of scrub buffer in wrdp | |
2537 | output [1:0] drif_io_wdata_sel; // selects between double words for single DIMM mode in wrdp | |
2538 | ||
2539 | // ucb addr and data bits to rdpctl and fbdic for registers in those block | |
2540 | output drif_ucb_wr_req_vld; | |
2541 | output drif_ucb_rd_req_vld; | |
2542 | output [12:0] drif_ucb_addr; | |
2543 | output [63:0] drif_ucb_data; | |
2544 | ||
2545 | // register load signals for register in rdpctl | |
2546 | output drif_err_sts_reg_ld; | |
2547 | output drif_err_addr_reg_ld; | |
2548 | output drif_err_cnt_reg_ld; | |
2549 | output drif_err_loc_reg_ld; | |
2550 | output drif_err_retry_reg_ld; | |
2551 | output drif_dbg_trig_reg_ld; | |
2552 | ||
2553 | // FBDIC interface | |
2554 | output [2:0] drif_dram_cmd_a; | |
2555 | output [15:0] drif_dram_addr_a; | |
2556 | output [2:0] drif_dram_bank_a; | |
2557 | output drif_dram_rank_a; | |
2558 | output [2:0] drif_dram_dimm_a; | |
2559 | ||
2560 | output [2:0] drif_dram_cmd_b; | |
2561 | output [15:0] drif_dram_addr_b; | |
2562 | output [2:0] drif_dram_bank_b; | |
2563 | output drif_dram_rank_b; | |
2564 | output [2:0] drif_dram_dimm_b; | |
2565 | ||
2566 | output [2:0] drif_dram_cmd_c; | |
2567 | output [15:0] drif_dram_addr_c; | |
2568 | output [2:0] drif_dram_bank_c; | |
2569 | output drif_dram_rank_c; | |
2570 | output [2:0] drif_dram_dimm_c; | |
2571 | ||
2572 | output drif_wdata_wsn; | |
2573 | output woq_err_st_wait_free; | |
2574 | output drif_crc_rd_picked; | |
2575 | output drif_err_fifo_empty; | |
2576 | output woq_err_fifo_empty; | |
2577 | output [1:0] woq_wr_req_out; | |
2578 | ||
2579 | output drif_mcu_error_mode; | |
2580 | output drif_err_state_crc_fr; | |
2581 | output drif_mcu_idle; | |
2582 | output drif_cke_reg; | |
2583 | ||
2584 | // UCB register rd/wr request information | |
2585 | input rdata_drif_rd_req_vld; | |
2586 | input rdata_drif_wr_req_vld; | |
2587 | input [12:0] rdata_drif_addr; | |
2588 | input [63:0] rdata_drif_data; | |
2589 | ||
2590 | input rdata_mcu_selfrsh; // puts mcu in self refresh mode | |
2591 | ||
2592 | // error status registers from rdpctl | |
2593 | input [35:0] rdpctl_err_addr_reg; | |
2594 | input [25:0] rdpctl_err_sts_reg; | |
2595 | input [35:0] rdpctl_err_loc; | |
2596 | input [15:0] rdpctl_err_cnt; | |
2597 | input [36:0] rdpctl_err_retry_reg; | |
2598 | input rdpctl_dbg_trig_enable; // debug mode trigger | |
2599 | input rdpctl_kp_lnk_up; | |
2600 | input rdpctl_mask_err; | |
2601 | input [1:0] rdpctl_dtm_mask_chnl; | |
2602 | input rdpctl_dtm_atspeed; | |
2603 | ||
2604 | // read request queue entry clear signals | |
2605 | input [7:0] rdpctl_drq0_clear_ent; | |
2606 | input [7:0] rdpctl_drq1_clear_ent; | |
2607 | ||
2608 | // write request queue entry clear signals | |
2609 | input rdpctl_scrub_wren; // write enable for scrub buffer, gets OR'ed with drif's | |
2610 | // read enable before being sent to wrdp | |
2611 | input rdpctl_scrub_addrinc_en; | |
2612 | input [1:0] readdp_ecc_multi_err; // multi bit error signal for error handling state machine | |
2613 | ||
2614 | // ras, cas, and rd_req_id info from request queues | |
2615 | input [14:0] addrdp_ras_adr_queue; | |
2616 | input [10:0] addrdp_cas_adr_queue; | |
2617 | input [2:0] addrdp_rd_req_id_queue; | |
2618 | input [14:0] addrdp_ras_wr1_adr_queue; | |
2619 | input [10:0] addrdp_cas_wr1_adr_queue; | |
2620 | input [14:0] addrdp_ras_wr2_adr_queue; | |
2621 | input [10:0] addrdp_cas_wr2_adr_queue; | |
2622 | ||
2623 | // rank, bank, err, and parity for incoming read requests | |
2624 | input l2b0_rd_rank_adr; | |
2625 | input [2:0] l2b0_rd_dimm_adr; | |
2626 | input [2:0] l2b0_rd_bank_adr; | |
2627 | input l2b0_rd_addr_err; | |
2628 | input l2b0_rd_addr_par; | |
2629 | input l2b1_rd_rank_adr; | |
2630 | input [2:0] l2b1_rd_dimm_adr; | |
2631 | input [2:0] l2b1_rd_bank_adr; | |
2632 | input l2b1_rd_addr_err; | |
2633 | input l2b1_rd_addr_par; | |
2634 | ||
2635 | // rank, bank, err, and parity for incoming write requests | |
2636 | input l2b0_wr_rank_adr; | |
2637 | input [2:0] l2b0_wr_dimm_adr; | |
2638 | input [2:0] l2b0_wr_bank_adr; | |
2639 | input l2b0_wr_addr_err; | |
2640 | input l2b0_wr_addr_par; | |
2641 | input l2b1_wr_rank_adr; | |
2642 | input [2:0] l2b1_wr_dimm_adr; | |
2643 | input [2:0] l2b1_wr_bank_adr; | |
2644 | input l2b1_wr_addr_err; | |
2645 | input l2b1_wr_addr_par; | |
2646 | ||
2647 | ||
2648 | input l2if0_rd_req; // incoming read request | |
2649 | input l2if0_wr_req; // incoming write request | |
2650 | input [2:0] l2if0_data_wr_addr; // wdq entry for write request | |
2651 | input l2if0_wdq_rd_inh; | |
2652 | input [3:0] l2if0_wdq_in_cntr; // incremented by l2if when all data for a write is in wdq | |
2653 | ||
2654 | input l2if1_rd_req; // incoming read request | |
2655 | input l2if1_wr_req; // incoming write request | |
2656 | input [2:0] l2if1_data_wr_addr; // wdq entry for write request | |
2657 | input l2if1_wdq_rd_inh; | |
2658 | input [3:0] l2if1_wdq_in_cntr; // incremented by l2if when all data for a write is in wdq | |
2659 | ||
2660 | // incoming power throttling sync signals from other MCUs | |
2661 | input mcu_pt_sync_in0; | |
2662 | input mcu_pt_sync_in1; | |
2663 | input mcu_pt_sync_in2; | |
2664 | ||
2665 | // read-write queue match signals for RAW hazard detection | |
2666 | input addrdp0_rd_wr_adr0_eq; | |
2667 | input addrdp0_rd_wr_adr1_eq; | |
2668 | input addrdp0_rd_wr_adr2_eq; | |
2669 | input addrdp0_rd_wr_adr3_eq; | |
2670 | input addrdp0_rd_wr_adr4_eq; | |
2671 | input addrdp0_rd_wr_adr5_eq; | |
2672 | input addrdp0_rd_wr_adr6_eq; | |
2673 | input addrdp0_rd_wr_adr7_eq; | |
2674 | input addrdp1_rd_wr_adr0_eq; | |
2675 | input addrdp1_rd_wr_adr1_eq; | |
2676 | input addrdp1_rd_wr_adr2_eq; | |
2677 | input addrdp1_rd_wr_adr3_eq; | |
2678 | input addrdp1_rd_wr_adr4_eq; | |
2679 | input addrdp1_rd_wr_adr5_eq; | |
2680 | input addrdp1_rd_wr_adr6_eq; | |
2681 | input addrdp1_rd_wr_adr7_eq; | |
2682 | ||
2683 | input rdpctl_scrub_read_done; // resets outstanding scrub flop | |
2684 | ||
2685 | // data poison bits from wdqrf's for writedp | |
2686 | input wdqrf00_data_mecc; | |
2687 | input wdqrf01_data_mecc; | |
2688 | input wdqrf10_data_mecc; | |
2689 | input wdqrf11_data_mecc; | |
2690 | ||
2691 | // error fifo data for ecc error transactions | |
2692 | input rdpctl_err_fifo_enq; | |
2693 | input [14:0] rdpctl_err_fifo_data; | |
2694 | input rdpctl_fifo_empty; | |
2695 | input rdpctl_fifo_full; | |
2696 | input rdpctl_no_crc_err; | |
2697 | input rdpctl_crc_err; | |
2698 | ||
2699 | input [65:0] fbdic_ucb_rd_data; | |
2700 | input fbdic_sync_frame_req_early3; | |
2701 | input fbdic_sync_frame_req_early2; | |
2702 | input fbdic_sync_frame_req_early1; | |
2703 | input fbdic_sync_frame_req; | |
2704 | input fbdic_scr_frame_req_d4; | |
2705 | input fbdic_l0_state; | |
2706 | input [1:0] fbdic_woq_free; | |
2707 | input fbdic_clear_wrq_ent; | |
2708 | input fbdic_error_mode; | |
2709 | input fbdic_l0s_lfsr_stall; | |
2710 | input fbdic_err_fast_reset_done; | |
2711 | input fbdic_chnl_reset_error_mode; | |
2712 | ||
2713 | input fbdic_mcu_idle; | |
2714 | ||
2715 | input drl2clk; | |
2716 | input scan_in; | |
2717 | output scan_out; | |
2718 | input wmr_scan_in; | |
2719 | output wmr_scan_out; | |
2720 | input tcu_pce_ov; | |
2721 | input tcu_aclk; | |
2722 | input tcu_bclk; | |
2723 | input aclk_wmr; | |
2724 | input tcu_scan_en; | |
2725 | input wmr_protect; | |
2726 | ||
2727 | // Code | |
2728 | assign pce_ov = tcu_pce_ov; | |
2729 | assign siclk = tcu_aclk; | |
2730 | assign soclk = tcu_bclk; | |
2731 | assign se = tcu_scan_en; | |
2732 | ||
2733 | // need to define these wires here so 'always' blocks won't cause errors | |
2734 | wire [7:0] drif_precharge_wait; | |
2735 | wire [12:0] drif_ref_cnt; | |
2736 | wire [3:0] drif_last_rank; | |
2737 | wire [7:0] drif_cyc_cnt; | |
2738 | wire [4:0] drif_bank_idle_cnt; | |
2739 | wire drif_mclk_en; | |
2740 | ||
2741 | reg [`DRIF_MCU_STATE_MAX:0] drif_mcu_state_next; | |
2742 | reg [7:0] drif_cyc_cnt_next; | |
2743 | reg [4:0] drif_bank_idle_cnt_next; | |
2744 | reg [4:0] drif_refresh_rank_in; | |
2745 | reg set_drif_enter_self_refresh; | |
2746 | reg set_drif_exit_self_refresh; | |
2747 | ||
2748 | // 0in set_clock drl2clk -default | |
2749 | mcu_drif_ctl_l1clkhdr_ctl_macro clkgen ( | |
2750 | .l2clk(drl2clk), | |
2751 | .l1en (1'b1 ), | |
2752 | .stop(1'b0), | |
2753 | .l1clk(l1clk), | |
2754 | .pce_ov(pce_ov), | |
2755 | .se(se)); | |
2756 | ||
2757 | // Register incoming signals | |
2758 | ||
2759 | mcu_drif_ctl_msff_ctl_macro__width_79 ff_ucb_req ( | |
2760 | .scan_in(ff_ucb_req_scanin), | |
2761 | .scan_out(ff_ucb_req_scanout), | |
2762 | .din({rdata_drif_rd_req_vld, rdata_drif_wr_req_vld, rdata_drif_addr[12:0], rdata_drif_data[63:0]}), | |
2763 | .dout({drif_ucb_rd_req_vld, drif_ucb_wr_req_vld, drif_ucb_addr[12:0], drif_ucb_data[63:0]}), | |
2764 | .l1clk(l1clk), | |
2765 | .siclk(siclk), | |
2766 | .soclk(soclk)); | |
2767 | ||
2768 | mcu_drif_ctl_msff_ctl_macro__width_1 ff_hw_selfref ( | |
2769 | .scan_in(ff_hw_selfref_scanin), | |
2770 | .scan_out(ff_hw_selfref_scanout), | |
2771 | .din(rdata_mcu_selfrsh), | |
2772 | .dout(drif_hw_selfrsh), | |
2773 | .l1clk(l1clk), | |
2774 | .siclk(siclk), | |
2775 | .soclk(soclk)); | |
2776 | ||
2777 | assign fbdic_sync_frame_req_l = ~fbdic_sync_frame_req; | |
2778 | assign fbdic_sync_frame_req_early3_l = ~fbdic_sync_frame_req_early3; | |
2779 | assign fbdic_sync_frame_req_early1_l = ~fbdic_sync_frame_req_early1; | |
2780 | ||
2781 | mcu_drif_ctl_msff_ctl_macro__width_3 ff_sync_frame_req_l ( | |
2782 | .scan_in(ff_sync_frame_req_l_scanin), | |
2783 | .scan_out(ff_sync_frame_req_l_scanout), | |
2784 | .din({fbdic_sync_frame_req_l,fbdic_sync_frame_req_early3_l,fbdic_sync_frame_req_early1_l}), | |
2785 | .dout({drif_sync_frame_req_l,drif_sync_frame_req_early3_l,drif_sync_frame_req_early1_l}), | |
2786 | .l1clk(l1clk), | |
2787 | .siclk(siclk), | |
2788 | .soclk(soclk)); | |
2789 | ||
2790 | ////////////////////////////////////////////////////////////////// | |
2791 | // delay timers for scheduling transactions | |
2792 | ////////////////////////////////////////////////////////////////// | |
2793 | ||
2794 | mcu_dmmdly_ctl dmmdly0 ( | |
2795 | .scan_in(dmmdly0_scanin), | |
2796 | .scan_out(dmmdly0_scanout), | |
2797 | .l1clk(l1clk), | |
2798 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[0]), | |
2799 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[0]), | |
2800 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[0]), | |
2801 | .rrd_cnt_is_zero(rrd_cnt_is_zero[0]), | |
2802 | .rtw_cnt_is_zero(rtw_cnt_is_zero[0]), | |
2803 | .wtr_cnt_is_zero(wtr_cnt_is_zero[0]), | |
2804 | .rtr_cnt_is_zero(rtr_cnt_is_zero[0]), | |
2805 | .wtw_cnt_is_zero(wtw_cnt_is_zero[0]), | |
2806 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[0]), | |
2807 | .rrd_reg(rrd_reg[3:0]), | |
2808 | .rtw_reg(rtw_reg[3:0]), | |
2809 | .wtr_reg(wtr_reg[3:0]), | |
2810 | .faw_reg(faw_reg[4:0]), | |
2811 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2812 | .tcu_aclk(tcu_aclk), | |
2813 | .tcu_bclk(tcu_bclk), | |
2814 | .tcu_scan_en(tcu_scan_en) | |
2815 | ); | |
2816 | ||
2817 | mcu_dmmdly_ctl dmmdly1 ( | |
2818 | .scan_in(dmmdly1_scanin), | |
2819 | .scan_out(dmmdly1_scanout), | |
2820 | .l1clk(l1clk), | |
2821 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[1]), | |
2822 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[1]), | |
2823 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[1]), | |
2824 | .rrd_cnt_is_zero(rrd_cnt_is_zero[1]), | |
2825 | .rtw_cnt_is_zero(rtw_cnt_is_zero[1]), | |
2826 | .wtr_cnt_is_zero(wtr_cnt_is_zero[1]), | |
2827 | .rtr_cnt_is_zero(rtr_cnt_is_zero[1]), | |
2828 | .wtw_cnt_is_zero(wtw_cnt_is_zero[1]), | |
2829 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[1]), | |
2830 | .rrd_reg(rrd_reg[3:0]), | |
2831 | .rtw_reg(rtw_reg[3:0]), | |
2832 | .wtr_reg(wtr_reg[3:0]), | |
2833 | .faw_reg(faw_reg[4:0]), | |
2834 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2835 | .tcu_aclk(tcu_aclk), | |
2836 | .tcu_bclk(tcu_bclk), | |
2837 | .tcu_scan_en(tcu_scan_en) | |
2838 | ); | |
2839 | ||
2840 | mcu_dmmdly_ctl dmmdly2 ( | |
2841 | .scan_in(dmmdly2_scanin), | |
2842 | .scan_out(dmmdly2_scanout), | |
2843 | .l1clk(l1clk), | |
2844 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[2]), | |
2845 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[2]), | |
2846 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[2]), | |
2847 | .rrd_cnt_is_zero(rrd_cnt_is_zero[2]), | |
2848 | .rtw_cnt_is_zero(rtw_cnt_is_zero[2]), | |
2849 | .wtr_cnt_is_zero(wtr_cnt_is_zero[2]), | |
2850 | .rtr_cnt_is_zero(rtr_cnt_is_zero[2]), | |
2851 | .wtw_cnt_is_zero(wtw_cnt_is_zero[2]), | |
2852 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[2]), | |
2853 | .rrd_reg(rrd_reg[3:0]), | |
2854 | .rtw_reg(rtw_reg[3:0]), | |
2855 | .wtr_reg(wtr_reg[3:0]), | |
2856 | .faw_reg(faw_reg[4:0]), | |
2857 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2858 | .tcu_aclk(tcu_aclk), | |
2859 | .tcu_bclk(tcu_bclk), | |
2860 | .tcu_scan_en(tcu_scan_en) | |
2861 | ); | |
2862 | ||
2863 | mcu_dmmdly_ctl dmmdly3 ( | |
2864 | .scan_in(dmmdly3_scanin), | |
2865 | .scan_out(dmmdly3_scanout), | |
2866 | .l1clk(l1clk), | |
2867 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[3]), | |
2868 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[3]), | |
2869 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[3]), | |
2870 | .rrd_cnt_is_zero(rrd_cnt_is_zero[3]), | |
2871 | .rtw_cnt_is_zero(rtw_cnt_is_zero[3]), | |
2872 | .wtr_cnt_is_zero(wtr_cnt_is_zero[3]), | |
2873 | .rtr_cnt_is_zero(rtr_cnt_is_zero[3]), | |
2874 | .wtw_cnt_is_zero(wtw_cnt_is_zero[3]), | |
2875 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[3]), | |
2876 | .rrd_reg(rrd_reg[3:0]), | |
2877 | .rtw_reg(rtw_reg[3:0]), | |
2878 | .wtr_reg(wtr_reg[3:0]), | |
2879 | .faw_reg(faw_reg[4:0]), | |
2880 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2881 | .tcu_aclk(tcu_aclk), | |
2882 | .tcu_bclk(tcu_bclk), | |
2883 | .tcu_scan_en(tcu_scan_en) | |
2884 | ); | |
2885 | ||
2886 | mcu_dmmdly_ctl dmmdly4 ( | |
2887 | .scan_in(dmmdly4_scanin), | |
2888 | .scan_out(dmmdly4_scanout), | |
2889 | .l1clk(l1clk), | |
2890 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[4]), | |
2891 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[4]), | |
2892 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[4]), | |
2893 | .rrd_cnt_is_zero(rrd_cnt_is_zero[4]), | |
2894 | .rtw_cnt_is_zero(rtw_cnt_is_zero[4]), | |
2895 | .wtr_cnt_is_zero(wtr_cnt_is_zero[4]), | |
2896 | .rtr_cnt_is_zero(rtr_cnt_is_zero[4]), | |
2897 | .wtw_cnt_is_zero(wtw_cnt_is_zero[4]), | |
2898 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[4]), | |
2899 | .rrd_reg(rrd_reg[3:0]), | |
2900 | .rtw_reg(rtw_reg[3:0]), | |
2901 | .wtr_reg(wtr_reg[3:0]), | |
2902 | .faw_reg(faw_reg[4:0]), | |
2903 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2904 | .tcu_aclk(tcu_aclk), | |
2905 | .tcu_bclk(tcu_bclk), | |
2906 | .tcu_scan_en(tcu_scan_en) | |
2907 | ); | |
2908 | ||
2909 | mcu_dmmdly_ctl dmmdly5 ( | |
2910 | .scan_in(dmmdly5_scanin), | |
2911 | .scan_out(dmmdly5_scanout), | |
2912 | .l1clk(l1clk), | |
2913 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[5]), | |
2914 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[5]), | |
2915 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[5]), | |
2916 | .rrd_cnt_is_zero(rrd_cnt_is_zero[5]), | |
2917 | .rtw_cnt_is_zero(rtw_cnt_is_zero[5]), | |
2918 | .wtr_cnt_is_zero(wtr_cnt_is_zero[5]), | |
2919 | .rtr_cnt_is_zero(rtr_cnt_is_zero[5]), | |
2920 | .wtw_cnt_is_zero(wtw_cnt_is_zero[5]), | |
2921 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[5]), | |
2922 | .rrd_reg(rrd_reg[3:0]), | |
2923 | .rtw_reg(rtw_reg[3:0]), | |
2924 | .wtr_reg(wtr_reg[3:0]), | |
2925 | .faw_reg(faw_reg[4:0]), | |
2926 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2927 | .tcu_aclk(tcu_aclk), | |
2928 | .tcu_bclk(tcu_bclk), | |
2929 | .tcu_scan_en(tcu_scan_en) | |
2930 | ); | |
2931 | ||
2932 | mcu_dmmdly_ctl dmmdly6 ( | |
2933 | .scan_in(dmmdly6_scanin), | |
2934 | .scan_out(dmmdly6_scanout), | |
2935 | .l1clk(l1clk), | |
2936 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[6]), | |
2937 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[6]), | |
2938 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[6]), | |
2939 | .rrd_cnt_is_zero(rrd_cnt_is_zero[6]), | |
2940 | .rtw_cnt_is_zero(rtw_cnt_is_zero[6]), | |
2941 | .wtr_cnt_is_zero(wtr_cnt_is_zero[6]), | |
2942 | .rtr_cnt_is_zero(rtr_cnt_is_zero[6]), | |
2943 | .wtw_cnt_is_zero(wtw_cnt_is_zero[6]), | |
2944 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[6]), | |
2945 | .rrd_reg(rrd_reg[3:0]), | |
2946 | .rtw_reg(rtw_reg[3:0]), | |
2947 | .wtr_reg(wtr_reg[3:0]), | |
2948 | .faw_reg(faw_reg[4:0]), | |
2949 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2950 | .tcu_aclk(tcu_aclk), | |
2951 | .tcu_bclk(tcu_bclk), | |
2952 | .tcu_scan_en(tcu_scan_en) | |
2953 | ); | |
2954 | ||
2955 | mcu_dmmdly_ctl dmmdly7 ( | |
2956 | .scan_in(dmmdly7_scanin), | |
2957 | .scan_out(dmmdly7_scanout), | |
2958 | .l1clk(l1clk), | |
2959 | .drif_rd_ras_picked(drif_dmm_rd_ras_picked[7]), | |
2960 | .drif_wr_ras_picked(drif_dmm_wr_ras_picked[7]), | |
2961 | .drif_wrbc_ras_picked(drif_dmm_wrbc_ras_picked[7]), | |
2962 | .rrd_cnt_is_zero(rrd_cnt_is_zero[7]), | |
2963 | .rtw_cnt_is_zero(rtw_cnt_is_zero[7]), | |
2964 | .wtr_cnt_is_zero(wtr_cnt_is_zero[7]), | |
2965 | .rtr_cnt_is_zero(rtr_cnt_is_zero[7]), | |
2966 | .wtw_cnt_is_zero(wtw_cnt_is_zero[7]), | |
2967 | .dmmdly_4_activate_stall(dmmdly_4_activate_stall[7]), | |
2968 | .rrd_reg(rrd_reg[3:0]), | |
2969 | .rtw_reg(rtw_reg[3:0]), | |
2970 | .wtr_reg(wtr_reg[3:0]), | |
2971 | .faw_reg(faw_reg[4:0]), | |
2972 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
2973 | .tcu_aclk(tcu_aclk), | |
2974 | .tcu_bclk(tcu_bclk), | |
2975 | .tcu_scan_en(tcu_scan_en) | |
2976 | ); | |
2977 | ||
2978 | // Refresh to Active delay timer | |
2979 | // wait for tRFC count | |
2980 | assign rfc_cnt_next[6:0] = drif_refresh_req_picked & fbdic_sync_frame_req_l ? rfc_reg[6:0] : | |
2981 | (rfc_cnt[6:0] == 7'h0) ? 7'h0 : rfc_cnt[6:0] - 7'h1; | |
2982 | ||
2983 | mcu_drif_ctl_msff_ctl_macro__width_7 ff_rfc_cnt ( | |
2984 | .scan_in(ff_rfc_cnt_scanin), | |
2985 | .scan_out(ff_rfc_cnt_scanout), | |
2986 | .din(rfc_cnt_next[6:0]), | |
2987 | .dout(rfc_cnt[6:0]), | |
2988 | .l1clk(l1clk), | |
2989 | .siclk(siclk), | |
2990 | .soclk(soclk)); | |
2991 | ||
2992 | assign rfc_cnt_is_zero = (rfc_cnt[6:0] == 7'h0); | |
2993 | ||
2994 | // RAS-to-RAS delay counter for all reads so data doesn't collide on NB channel | |
2995 | assign rd_rrd_cnt_next[1:0] = (drif0_rd_picked & ~drif0_raw_hazard | drif1_rd_picked & ~drif1_raw_hazard | | |
2996 | drif_scrub_picked | drif_err_rd_picked) & rd_rrd_cnt_is_zero ? {drif_single_channel_mode, 1'b1} : | |
2997 | rd_rrd_cnt[1:0] == 2'h0 ? 2'h0 : | |
2998 | fbdic_sync_frame_req_l ? rd_rrd_cnt[1:0] - 2'h1 : rd_rrd_cnt[1:0]; | |
2999 | ||
3000 | mcu_drif_ctl_msff_ctl_macro__width_2 ff_rd_rrd_cnt ( | |
3001 | .scan_in(ff_rd_rrd_cnt_scanin), | |
3002 | .scan_out(ff_rd_rrd_cnt_scanout), | |
3003 | .din(rd_rrd_cnt_next[1:0]), | |
3004 | .dout(rd_rrd_cnt[1:0]), | |
3005 | .l1clk(l1clk), | |
3006 | .siclk(siclk), | |
3007 | .soclk(soclk)); | |
3008 | ||
3009 | assign rd_rrd_cnt_is_zero = rd_rrd_cnt[1:0] == 2'h0; | |
3010 | ||
3011 | ////////////////////////////////////////////////////////////////// | |
3012 | // DRAM BANK delay timers | |
3013 | // There is one set of timers for each DRAM bank. They keep track of the | |
3014 | // commands issued to them and generate appropriate signals to | |
3015 | // DRAM state machine. | |
3016 | ////////////////////////////////////////////////////////////////// | |
3017 | ||
3018 | mcu_bnksm_ctl bnksm0 ( | |
3019 | .scan_in(bnksm0_scanin), | |
3020 | .scan_out(bnksm0_scanout), | |
3021 | .l1clk(l1clk), | |
3022 | .drif_abnk_ras_picked(drif_abnk_ras_picked[0]), | |
3023 | .drif_abnk_cas_picked(drif_abnk_cas_picked[0]), | |
3024 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[0]), | |
3025 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[0]), | |
3026 | .rcd_cnt_is_zero(b0_rcd_cnt_is_zero), | |
3027 | .rc_cnt_is_zero(b0_rc_cnt_is_zero), | |
3028 | .dal_cnt_is_zero(b0_dal_cnt_is_zero), | |
3029 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3030 | .rcd_reg(rcd_reg[3:0]), | |
3031 | .rc_reg(rc_reg[4:0]), | |
3032 | .dal_reg(dal_reg[4:0]), | |
3033 | .ral_reg(ral_reg[4:0]), | |
3034 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3035 | .tcu_aclk(tcu_aclk), | |
3036 | .tcu_bclk(tcu_bclk), | |
3037 | .tcu_scan_en(tcu_scan_en) | |
3038 | ); | |
3039 | ||
3040 | mcu_bnksm_ctl bnksm1 ( | |
3041 | .scan_in(bnksm1_scanin), | |
3042 | .scan_out(bnksm1_scanout), | |
3043 | .l1clk(l1clk), | |
3044 | .drif_abnk_ras_picked(drif_abnk_ras_picked[1]), | |
3045 | .drif_abnk_cas_picked(drif_abnk_cas_picked[1]), | |
3046 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[1]), | |
3047 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[1]), | |
3048 | .rcd_cnt_is_zero(b1_rcd_cnt_is_zero), | |
3049 | .rc_cnt_is_zero(b1_rc_cnt_is_zero), | |
3050 | .dal_cnt_is_zero(b1_dal_cnt_is_zero), | |
3051 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3052 | .rcd_reg(rcd_reg[3:0]), | |
3053 | .rc_reg(rc_reg[4:0]), | |
3054 | .dal_reg(dal_reg[4:0]), | |
3055 | .ral_reg(ral_reg[4:0]), | |
3056 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3057 | .tcu_aclk(tcu_aclk), | |
3058 | .tcu_bclk(tcu_bclk), | |
3059 | .tcu_scan_en(tcu_scan_en) | |
3060 | ); | |
3061 | ||
3062 | mcu_bnksm_ctl bnksm2 ( | |
3063 | .scan_in(bnksm2_scanin), | |
3064 | .scan_out(bnksm2_scanout), | |
3065 | .l1clk(l1clk), | |
3066 | .drif_abnk_ras_picked(drif_abnk_ras_picked[2]), | |
3067 | .drif_abnk_cas_picked(drif_abnk_cas_picked[2]), | |
3068 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[2]), | |
3069 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[2]), | |
3070 | .rcd_cnt_is_zero(b2_rcd_cnt_is_zero), | |
3071 | .rc_cnt_is_zero(b2_rc_cnt_is_zero), | |
3072 | .dal_cnt_is_zero(b2_dal_cnt_is_zero), | |
3073 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3074 | .rcd_reg(rcd_reg[3:0]), | |
3075 | .rc_reg(rc_reg[4:0]), | |
3076 | .dal_reg(dal_reg[4:0]), | |
3077 | .ral_reg(ral_reg[4:0]), | |
3078 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3079 | .tcu_aclk(tcu_aclk), | |
3080 | .tcu_bclk(tcu_bclk), | |
3081 | .tcu_scan_en(tcu_scan_en) | |
3082 | ); | |
3083 | ||
3084 | mcu_bnksm_ctl bnksm3 ( | |
3085 | .scan_in(bnksm3_scanin), | |
3086 | .scan_out(bnksm3_scanout), | |
3087 | .l1clk(l1clk), | |
3088 | .drif_abnk_ras_picked(drif_abnk_ras_picked[3]), | |
3089 | .drif_abnk_cas_picked(drif_abnk_cas_picked[3]), | |
3090 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[3]), | |
3091 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[3]), | |
3092 | .rcd_cnt_is_zero(b3_rcd_cnt_is_zero), | |
3093 | .rc_cnt_is_zero(b3_rc_cnt_is_zero), | |
3094 | .dal_cnt_is_zero(b3_dal_cnt_is_zero), | |
3095 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3096 | .rcd_reg(rcd_reg[3:0]), | |
3097 | .rc_reg(rc_reg[4:0]), | |
3098 | .dal_reg(dal_reg[4:0]), | |
3099 | .ral_reg(ral_reg[4:0]), | |
3100 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3101 | .tcu_aclk(tcu_aclk), | |
3102 | .tcu_bclk(tcu_bclk), | |
3103 | .tcu_scan_en(tcu_scan_en) | |
3104 | ); | |
3105 | ||
3106 | mcu_bnksm_ctl bnksm4 ( | |
3107 | .scan_in(bnksm4_scanin), | |
3108 | .scan_out(bnksm4_scanout), | |
3109 | .l1clk(l1clk), | |
3110 | .drif_abnk_ras_picked(drif_abnk_ras_picked[4]), | |
3111 | .drif_abnk_cas_picked(drif_abnk_cas_picked[4]), | |
3112 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[4]), | |
3113 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[4]), | |
3114 | .rcd_cnt_is_zero(b4_rcd_cnt_is_zero), | |
3115 | .rc_cnt_is_zero(b4_rc_cnt_is_zero), | |
3116 | .dal_cnt_is_zero(b4_dal_cnt_is_zero), | |
3117 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3118 | .rcd_reg(rcd_reg[3:0]), | |
3119 | .rc_reg(rc_reg[4:0]), | |
3120 | .dal_reg(dal_reg[4:0]), | |
3121 | .ral_reg(ral_reg[4:0]), | |
3122 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3123 | .tcu_aclk(tcu_aclk), | |
3124 | .tcu_bclk(tcu_bclk), | |
3125 | .tcu_scan_en(tcu_scan_en) | |
3126 | ); | |
3127 | ||
3128 | mcu_bnksm_ctl bnksm5 ( | |
3129 | .scan_in(bnksm5_scanin), | |
3130 | .scan_out(bnksm5_scanout), | |
3131 | .l1clk(l1clk), | |
3132 | .drif_abnk_ras_picked(drif_abnk_ras_picked[5]), | |
3133 | .drif_abnk_cas_picked(drif_abnk_cas_picked[5]), | |
3134 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[5]), | |
3135 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[5]), | |
3136 | .rcd_cnt_is_zero(b5_rcd_cnt_is_zero), | |
3137 | .rc_cnt_is_zero(b5_rc_cnt_is_zero), | |
3138 | .dal_cnt_is_zero(b5_dal_cnt_is_zero), | |
3139 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3140 | .rcd_reg(rcd_reg[3:0]), | |
3141 | .rc_reg(rc_reg[4:0]), | |
3142 | .dal_reg(dal_reg[4:0]), | |
3143 | .ral_reg(ral_reg[4:0]), | |
3144 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3145 | .tcu_aclk(tcu_aclk), | |
3146 | .tcu_bclk(tcu_bclk), | |
3147 | .tcu_scan_en(tcu_scan_en) | |
3148 | ); | |
3149 | ||
3150 | mcu_bnksm_ctl bnksm6 ( | |
3151 | .scan_in(bnksm6_scanin), | |
3152 | .scan_out(bnksm6_scanout), | |
3153 | .l1clk(l1clk), | |
3154 | .drif_abnk_ras_picked(drif_abnk_ras_picked[6]), | |
3155 | .drif_abnk_cas_picked(drif_abnk_cas_picked[6]), | |
3156 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[6]), | |
3157 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[6]), | |
3158 | .rcd_cnt_is_zero(b6_rcd_cnt_is_zero), | |
3159 | .rc_cnt_is_zero(b6_rc_cnt_is_zero), | |
3160 | .dal_cnt_is_zero(b6_dal_cnt_is_zero), | |
3161 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3162 | .rcd_reg(rcd_reg[3:0]), | |
3163 | .rc_reg(rc_reg[4:0]), | |
3164 | .dal_reg(dal_reg[4:0]), | |
3165 | .ral_reg(ral_reg[4:0]), | |
3166 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3167 | .tcu_aclk(tcu_aclk), | |
3168 | .tcu_bclk(tcu_bclk), | |
3169 | .tcu_scan_en(tcu_scan_en) | |
3170 | ); | |
3171 | ||
3172 | mcu_bnksm_ctl bnksm7 ( | |
3173 | .scan_in(bnksm7_scanin), | |
3174 | .scan_out(bnksm7_scanout), | |
3175 | .l1clk(l1clk), | |
3176 | .drif_abnk_ras_picked(drif_abnk_ras_picked[7]), | |
3177 | .drif_abnk_cas_picked(drif_abnk_cas_picked[7]), | |
3178 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[7]), | |
3179 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[7]), | |
3180 | .rcd_cnt_is_zero(b7_rcd_cnt_is_zero), | |
3181 | .rc_cnt_is_zero(b7_rc_cnt_is_zero), | |
3182 | .dal_cnt_is_zero(b7_dal_cnt_is_zero), | |
3183 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3184 | .rcd_reg(rcd_reg[3:0]), | |
3185 | .rc_reg(rc_reg[4:0]), | |
3186 | .dal_reg(dal_reg[4:0]), | |
3187 | .ral_reg(ral_reg[4:0]), | |
3188 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3189 | .tcu_aclk(tcu_aclk), | |
3190 | .tcu_bclk(tcu_bclk), | |
3191 | .tcu_scan_en(tcu_scan_en) | |
3192 | ); | |
3193 | ||
3194 | mcu_bnksm_ctl bnksm8 ( | |
3195 | .scan_in(bnksm8_scanin), | |
3196 | .scan_out(bnksm8_scanout), | |
3197 | .l1clk(l1clk), | |
3198 | .drif_abnk_ras_picked(drif_abnk_ras_picked[8]), | |
3199 | .drif_abnk_cas_picked(drif_abnk_cas_picked[8]), | |
3200 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[8]), | |
3201 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[8]), | |
3202 | .rcd_cnt_is_zero(b8_rcd_cnt_is_zero), | |
3203 | .rc_cnt_is_zero(b8_rc_cnt_is_zero), | |
3204 | .dal_cnt_is_zero(b8_dal_cnt_is_zero), | |
3205 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3206 | .rcd_reg(rcd_reg[3:0]), | |
3207 | .rc_reg(rc_reg[4:0]), | |
3208 | .dal_reg(dal_reg[4:0]), | |
3209 | .ral_reg(ral_reg[4:0]), | |
3210 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3211 | .tcu_aclk(tcu_aclk), | |
3212 | .tcu_bclk(tcu_bclk), | |
3213 | .tcu_scan_en(tcu_scan_en) | |
3214 | ); | |
3215 | ||
3216 | mcu_bnksm_ctl bnksm9 ( | |
3217 | .scan_in(bnksm9_scanin), | |
3218 | .scan_out(bnksm9_scanout), | |
3219 | .l1clk(l1clk), | |
3220 | .drif_abnk_ras_picked(drif_abnk_ras_picked[9]), | |
3221 | .drif_abnk_cas_picked(drif_abnk_cas_picked[9]), | |
3222 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[9]), | |
3223 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[9]), | |
3224 | .rcd_cnt_is_zero(b9_rcd_cnt_is_zero), | |
3225 | .rc_cnt_is_zero(b9_rc_cnt_is_zero), | |
3226 | .dal_cnt_is_zero(b9_dal_cnt_is_zero), | |
3227 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3228 | .rcd_reg(rcd_reg[3:0]), | |
3229 | .rc_reg(rc_reg[4:0]), | |
3230 | .dal_reg(dal_reg[4:0]), | |
3231 | .ral_reg(ral_reg[4:0]), | |
3232 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3233 | .tcu_aclk(tcu_aclk), | |
3234 | .tcu_bclk(tcu_bclk), | |
3235 | .tcu_scan_en(tcu_scan_en) | |
3236 | ); | |
3237 | ||
3238 | mcu_bnksm_ctl bnksm10 ( | |
3239 | .scan_in(bnksm10_scanin), | |
3240 | .scan_out(bnksm10_scanout), | |
3241 | .l1clk(l1clk), | |
3242 | .drif_abnk_ras_picked(drif_abnk_ras_picked[10]), | |
3243 | .drif_abnk_cas_picked(drif_abnk_cas_picked[10]), | |
3244 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[10]), | |
3245 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[10]), | |
3246 | .rcd_cnt_is_zero(b10_rcd_cnt_is_zero), | |
3247 | .rc_cnt_is_zero(b10_rc_cnt_is_zero), | |
3248 | .dal_cnt_is_zero(b10_dal_cnt_is_zero), | |
3249 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3250 | .rcd_reg(rcd_reg[3:0]), | |
3251 | .rc_reg(rc_reg[4:0]), | |
3252 | .dal_reg(dal_reg[4:0]), | |
3253 | .ral_reg(ral_reg[4:0]), | |
3254 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3255 | .tcu_aclk(tcu_aclk), | |
3256 | .tcu_bclk(tcu_bclk), | |
3257 | .tcu_scan_en(tcu_scan_en) | |
3258 | ); | |
3259 | ||
3260 | mcu_bnksm_ctl bnksm11 ( | |
3261 | .scan_in(bnksm11_scanin), | |
3262 | .scan_out(bnksm11_scanout), | |
3263 | .l1clk(l1clk), | |
3264 | .drif_abnk_ras_picked(drif_abnk_ras_picked[11]), | |
3265 | .drif_abnk_cas_picked(drif_abnk_cas_picked[11]), | |
3266 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[11]), | |
3267 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[11]), | |
3268 | .rcd_cnt_is_zero(b11_rcd_cnt_is_zero), | |
3269 | .rc_cnt_is_zero(b11_rc_cnt_is_zero), | |
3270 | .dal_cnt_is_zero(b11_dal_cnt_is_zero), | |
3271 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3272 | .rcd_reg(rcd_reg[3:0]), | |
3273 | .rc_reg(rc_reg[4:0]), | |
3274 | .dal_reg(dal_reg[4:0]), | |
3275 | .ral_reg(ral_reg[4:0]), | |
3276 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3277 | .tcu_aclk(tcu_aclk), | |
3278 | .tcu_bclk(tcu_bclk), | |
3279 | .tcu_scan_en(tcu_scan_en) | |
3280 | ); | |
3281 | ||
3282 | mcu_bnksm_ctl bnksm12 ( | |
3283 | .scan_in(bnksm12_scanin), | |
3284 | .scan_out(bnksm12_scanout), | |
3285 | .l1clk(l1clk), | |
3286 | .drif_abnk_ras_picked(drif_abnk_ras_picked[12]), | |
3287 | .drif_abnk_cas_picked(drif_abnk_cas_picked[12]), | |
3288 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[12]), | |
3289 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[12]), | |
3290 | .rcd_cnt_is_zero(b12_rcd_cnt_is_zero), | |
3291 | .rc_cnt_is_zero(b12_rc_cnt_is_zero), | |
3292 | .dal_cnt_is_zero(b12_dal_cnt_is_zero), | |
3293 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3294 | .rcd_reg(rcd_reg[3:0]), | |
3295 | .rc_reg(rc_reg[4:0]), | |
3296 | .dal_reg(dal_reg[4:0]), | |
3297 | .ral_reg(ral_reg[4:0]), | |
3298 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3299 | .tcu_aclk(tcu_aclk), | |
3300 | .tcu_bclk(tcu_bclk), | |
3301 | .tcu_scan_en(tcu_scan_en) | |
3302 | ); | |
3303 | ||
3304 | mcu_bnksm_ctl bnksm13 ( | |
3305 | .scan_in(bnksm13_scanin), | |
3306 | .scan_out(bnksm13_scanout), | |
3307 | .l1clk(l1clk), | |
3308 | .drif_abnk_ras_picked(drif_abnk_ras_picked[13]), | |
3309 | .drif_abnk_cas_picked(drif_abnk_cas_picked[13]), | |
3310 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[13]), | |
3311 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[13]), | |
3312 | .rcd_cnt_is_zero(b13_rcd_cnt_is_zero), | |
3313 | .rc_cnt_is_zero(b13_rc_cnt_is_zero), | |
3314 | .dal_cnt_is_zero(b13_dal_cnt_is_zero), | |
3315 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3316 | .rcd_reg(rcd_reg[3:0]), | |
3317 | .rc_reg(rc_reg[4:0]), | |
3318 | .dal_reg(dal_reg[4:0]), | |
3319 | .ral_reg(ral_reg[4:0]), | |
3320 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3321 | .tcu_aclk(tcu_aclk), | |
3322 | .tcu_bclk(tcu_bclk), | |
3323 | .tcu_scan_en(tcu_scan_en) | |
3324 | ); | |
3325 | ||
3326 | mcu_bnksm_ctl bnksm14 ( | |
3327 | .scan_in(bnksm14_scanin), | |
3328 | .scan_out(bnksm14_scanout), | |
3329 | .l1clk(l1clk), | |
3330 | .drif_abnk_ras_picked(drif_abnk_ras_picked[14]), | |
3331 | .drif_abnk_cas_picked(drif_abnk_cas_picked[14]), | |
3332 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[14]), | |
3333 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[14]), | |
3334 | .rcd_cnt_is_zero(b14_rcd_cnt_is_zero), | |
3335 | .rc_cnt_is_zero(b14_rc_cnt_is_zero), | |
3336 | .dal_cnt_is_zero(b14_dal_cnt_is_zero), | |
3337 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3338 | .rcd_reg(rcd_reg[3:0]), | |
3339 | .rc_reg(rc_reg[4:0]), | |
3340 | .dal_reg(dal_reg[4:0]), | |
3341 | .ral_reg(ral_reg[4:0]), | |
3342 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3343 | .tcu_aclk(tcu_aclk), | |
3344 | .tcu_bclk(tcu_bclk), | |
3345 | .tcu_scan_en(tcu_scan_en) | |
3346 | ); | |
3347 | ||
3348 | mcu_bnksm_ctl bnksm15 ( | |
3349 | .scan_in(bnksm15_scanin), | |
3350 | .scan_out(bnksm15_scanout), | |
3351 | .l1clk(l1clk), | |
3352 | .drif_abnk_ras_picked(drif_abnk_ras_picked[15]), | |
3353 | .drif_abnk_cas_picked(drif_abnk_cas_picked[15]), | |
3354 | .drif_bcbnk_ras_picked(drif_bcbnk_ras_picked[15]), | |
3355 | .drif_bcbnk_cas_picked(drif_bcbnk_cas_picked[15]), | |
3356 | .rcd_cnt_is_zero(b15_rcd_cnt_is_zero), | |
3357 | .rc_cnt_is_zero(b15_rc_cnt_is_zero), | |
3358 | .dal_cnt_is_zero(b15_dal_cnt_is_zero), | |
3359 | .drif_cmd_picked_d1(drif_cmd_picked_d1), | |
3360 | .rcd_reg(rcd_reg[3:0]), | |
3361 | .rc_reg(rc_reg[4:0]), | |
3362 | .dal_reg(dal_reg[4:0]), | |
3363 | .ral_reg(ral_reg[4:0]), | |
3364 | .fbdic_sync_frame_req_l(fbdic_sync_frame_req_l), | |
3365 | .tcu_aclk(tcu_aclk), | |
3366 | .tcu_bclk(tcu_bclk), | |
3367 | .tcu_scan_en(tcu_scan_en) | |
3368 | ); | |
3369 | ||
3370 | ////////////////////////////////////////////////////////////////// | |
3371 | // Performing ARBITRATION for RAS and CAS reqeust based on previous | |
3372 | // valids generated | |
3373 | ////////////////////////////////////////////////////////////////// | |
3374 | ||
3375 | assign drif0_rd_bank_valids[15:0] = drq0_rd_entry0_val[15:0] | drq0_rd_entry1_val[15:0] | | |
3376 | drq0_rd_entry2_val[15:0] | drq0_rd_entry3_val[15:0] | | |
3377 | drq0_rd_entry4_val[15:0] | drq0_rd_entry5_val[15:0] | | |
3378 | drq0_rd_entry6_val[15:0] | drq0_rd_entry7_val[15:0]; | |
3379 | ||
3380 | assign drif1_rd_bank_valids[15:0] = drq1_rd_entry0_val[15:0] | drq1_rd_entry1_val[15:0] | | |
3381 | drq1_rd_entry2_val[15:0] | drq1_rd_entry3_val[15:0] | | |
3382 | drq1_rd_entry4_val[15:0] | drq1_rd_entry5_val[15:0] | | |
3383 | drq1_rd_entry6_val[15:0] | drq1_rd_entry7_val[15:0]; | |
3384 | ||
3385 | assign drif_wr_bank_valids[15:0] = woq_entry0_val[15:0] | woq_entry1_val[15:0]; | |
3386 | ||
3387 | assign drif_bank_available[15] = b15_rc_cnt_is_zero & b15_dal_cnt_is_zero; | |
3388 | assign drif_bank_available[14] = b14_rc_cnt_is_zero & b14_dal_cnt_is_zero; | |
3389 | assign drif_bank_available[13] = b13_rc_cnt_is_zero & b13_dal_cnt_is_zero; | |
3390 | assign drif_bank_available[12] = b12_rc_cnt_is_zero & b12_dal_cnt_is_zero; | |
3391 | assign drif_bank_available[11] = b11_rc_cnt_is_zero & b11_dal_cnt_is_zero; | |
3392 | assign drif_bank_available[10] = b10_rc_cnt_is_zero & b10_dal_cnt_is_zero; | |
3393 | assign drif_bank_available[9] = b9_rc_cnt_is_zero & b9_dal_cnt_is_zero; | |
3394 | assign drif_bank_available[8] = b8_rc_cnt_is_zero & b8_dal_cnt_is_zero; | |
3395 | assign drif_bank_available[7] = b7_rc_cnt_is_zero & b7_dal_cnt_is_zero; | |
3396 | assign drif_bank_available[6] = b6_rc_cnt_is_zero & b6_dal_cnt_is_zero; | |
3397 | assign drif_bank_available[5] = b5_rc_cnt_is_zero & b5_dal_cnt_is_zero; | |
3398 | assign drif_bank_available[4] = b4_rc_cnt_is_zero & b4_dal_cnt_is_zero; | |
3399 | assign drif_bank_available[3] = b3_rc_cnt_is_zero & b3_dal_cnt_is_zero; | |
3400 | assign drif_bank_available[2] = b2_rc_cnt_is_zero & b2_dal_cnt_is_zero; | |
3401 | assign drif_bank_available[1] = b1_rc_cnt_is_zero & b1_dal_cnt_is_zero; | |
3402 | assign drif_bank_available[0] = b0_rc_cnt_is_zero & b0_dal_cnt_is_zero; | |
3403 | ||
3404 | assign drif_dimm_rd_available[7] = rtr_cnt_is_zero[7] & wtr_cnt_is_zero[7] & rrd_cnt_is_zero[7] & ~dmmdly_4_activate_stall[7]; | |
3405 | assign drif_dimm_rd_available[6] = rtr_cnt_is_zero[6] & wtr_cnt_is_zero[6] & rrd_cnt_is_zero[6] & ~dmmdly_4_activate_stall[6]; | |
3406 | assign drif_dimm_rd_available[5] = rtr_cnt_is_zero[5] & wtr_cnt_is_zero[5] & rrd_cnt_is_zero[5] & ~dmmdly_4_activate_stall[5]; | |
3407 | assign drif_dimm_rd_available[4] = rtr_cnt_is_zero[4] & wtr_cnt_is_zero[4] & rrd_cnt_is_zero[4] & ~dmmdly_4_activate_stall[4]; | |
3408 | assign drif_dimm_rd_available[3] = rtr_cnt_is_zero[3] & wtr_cnt_is_zero[3] & rrd_cnt_is_zero[3] & ~dmmdly_4_activate_stall[3]; | |
3409 | assign drif_dimm_rd_available[2] = rtr_cnt_is_zero[2] & wtr_cnt_is_zero[2] & rrd_cnt_is_zero[2] & ~dmmdly_4_activate_stall[2]; | |
3410 | assign drif_dimm_rd_available[1] = rtr_cnt_is_zero[1] & wtr_cnt_is_zero[1] & rrd_cnt_is_zero[1] & ~dmmdly_4_activate_stall[1]; | |
3411 | assign drif_dimm_rd_available[0] = rtr_cnt_is_zero[0] & wtr_cnt_is_zero[0] & rrd_cnt_is_zero[0] & ~dmmdly_4_activate_stall[0]; | |
3412 | ||
3413 | assign drif_dimm_wr_available[7] = rtw_cnt_is_zero[7] & wtw_cnt_is_zero[7] & rrd_cnt_is_zero[7] & ~dmmdly_4_activate_stall[7]; | |
3414 | assign drif_dimm_wr_available[6] = rtw_cnt_is_zero[6] & wtw_cnt_is_zero[6] & rrd_cnt_is_zero[6] & ~dmmdly_4_activate_stall[6]; | |
3415 | assign drif_dimm_wr_available[5] = rtw_cnt_is_zero[5] & wtw_cnt_is_zero[5] & rrd_cnt_is_zero[5] & ~dmmdly_4_activate_stall[5]; | |
3416 | assign drif_dimm_wr_available[4] = rtw_cnt_is_zero[4] & wtw_cnt_is_zero[4] & rrd_cnt_is_zero[4] & ~dmmdly_4_activate_stall[4]; | |
3417 | assign drif_dimm_wr_available[3] = rtw_cnt_is_zero[3] & wtw_cnt_is_zero[3] & rrd_cnt_is_zero[3] & ~dmmdly_4_activate_stall[3]; | |
3418 | assign drif_dimm_wr_available[2] = rtw_cnt_is_zero[2] & wtw_cnt_is_zero[2] & rrd_cnt_is_zero[2] & ~dmmdly_4_activate_stall[2]; | |
3419 | assign drif_dimm_wr_available[1] = rtw_cnt_is_zero[1] & wtw_cnt_is_zero[1] & rrd_cnt_is_zero[1] & ~dmmdly_4_activate_stall[1]; | |
3420 | assign drif_dimm_wr_available[0] = rtw_cnt_is_zero[0] & wtw_cnt_is_zero[0] & rrd_cnt_is_zero[0] & ~dmmdly_4_activate_stall[0]; | |
3421 | ||
3422 | // determine which reads are ready for issuing | |
3423 | assign drif0_rd_ready = |(drif_bank_available[15:0] & drif0_rd_bank_valids[15:0]); | |
3424 | assign drif1_rd_ready = |(drif_bank_available[15:0] & drif1_rd_bank_valids[15:0]); | |
3425 | assign drif_rd_ready = drif0_rd_ready | drif1_rd_ready; | |
3426 | assign drif_rd_pending = |(drif_bank_available[15:0] & drq0_rd_bank_val[15:0]) | | |
3427 | (|(drif_bank_available[15:0] & drq1_rd_bank_val[15:0])); | |
3428 | ||
3429 | assign drif_rd_stall = drif_blk_new_openbank | drif_mcu_error_mode | ~rd_rrd_cnt_is_zero | ~drif_err_fifo_empty | | |
3430 | drif_wr_pending & drif_pick_wr_first | drif_wr_entry_pend | drif_scrub_ready | | |
3431 | ~(fbdic_l0_state | fbdic_chnl_reset_error_mode) | drif_cas_picked | fbdic_sync_frame_req | | |
3432 | fbdic_l0s_lfsr_stall | fbdic_error_mode | woq_wr_error_mode | drif_mcu_state[3] | | |
3433 | rdpctl_fifo_full; | |
3434 | ||
3435 | assign drif0_rd_entry_ready[0] = |(drif_bank_available[15:0] & drq0_rd_entry0_val[15:0]) & ~drif_rd_stall & | |
3436 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry0_dimm[2:0] | | |
3437 | drif_last_rank_picked[3:0] == {drq0_rd_entry0_rank,drq0_rd_entry0_dimm[2:0]}); | |
3438 | assign drif0_rd_entry_ready[1] = |(drif_bank_available[15:0] & drq0_rd_entry1_val[15:0]) & ~drif_rd_stall & | |
3439 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry1_dimm[2:0] | | |
3440 | drif_last_rank_picked[3:0] == {drq0_rd_entry1_rank,drq0_rd_entry1_dimm[2:0]}); | |
3441 | assign drif0_rd_entry_ready[2] = |(drif_bank_available[15:0] & drq0_rd_entry2_val[15:0]) & ~drif_rd_stall & | |
3442 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry2_dimm[2:0] | | |
3443 | drif_last_rank_picked[3:0] == {drq0_rd_entry2_rank,drq0_rd_entry2_dimm[2:0]}); | |
3444 | assign drif0_rd_entry_ready[3] = |(drif_bank_available[15:0] & drq0_rd_entry3_val[15:0]) & ~drif_rd_stall & | |
3445 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry3_dimm[2:0] | | |
3446 | drif_last_rank_picked[3:0] == {drq0_rd_entry3_rank,drq0_rd_entry3_dimm[2:0]}); | |
3447 | assign drif0_rd_entry_ready[4] = |(drif_bank_available[15:0] & drq0_rd_entry4_val[15:0]) & ~drif_rd_stall & | |
3448 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry4_dimm[2:0] | | |
3449 | drif_last_rank_picked[3:0] == {drq0_rd_entry4_rank,drq0_rd_entry4_dimm[2:0]}); | |
3450 | assign drif0_rd_entry_ready[5] = |(drif_bank_available[15:0] & drq0_rd_entry5_val[15:0]) & ~drif_rd_stall & | |
3451 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry5_dimm[2:0] | | |
3452 | drif_last_rank_picked[3:0] == {drq0_rd_entry5_rank,drq0_rd_entry5_dimm[2:0]}); | |
3453 | assign drif0_rd_entry_ready[6] = |(drif_bank_available[15:0] & drq0_rd_entry6_val[15:0]) & ~drif_rd_stall & | |
3454 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry6_dimm[2:0] | | |
3455 | drif_last_rank_picked[3:0] == {drq0_rd_entry6_rank,drq0_rd_entry6_dimm[2:0]}); | |
3456 | assign drif0_rd_entry_ready[7] = |(drif_bank_available[15:0] & drq0_rd_entry7_val[15:0]) & ~drif_rd_stall & | |
3457 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq0_rd_entry7_dimm[2:0] | | |
3458 | drif_last_rank_picked[3:0] == {drq0_rd_entry7_rank,drq0_rd_entry7_dimm[2:0]}); | |
3459 | ||
3460 | assign drif1_rd_entry_ready[0] = |(drif_bank_available[15:0] & drq1_rd_entry0_val[15:0]) & ~drif_rd_stall & | |
3461 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry0_dimm[2:0] | | |
3462 | drif_last_rank_picked[3:0] == {drq1_rd_entry0_rank,drq1_rd_entry0_dimm[2:0]}); | |
3463 | assign drif1_rd_entry_ready[1] = |(drif_bank_available[15:0] & drq1_rd_entry1_val[15:0]) & ~drif_rd_stall & | |
3464 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry1_dimm[2:0] | | |
3465 | drif_last_rank_picked[3:0] == {drq1_rd_entry1_rank,drq1_rd_entry1_dimm[2:0]}); | |
3466 | assign drif1_rd_entry_ready[2] = |(drif_bank_available[15:0] & drq1_rd_entry2_val[15:0]) & ~drif_rd_stall & | |
3467 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry2_dimm[2:0] | | |
3468 | drif_last_rank_picked[3:0] == {drq1_rd_entry2_rank,drq1_rd_entry2_dimm[2:0]}); | |
3469 | assign drif1_rd_entry_ready[3] = |(drif_bank_available[15:0] & drq1_rd_entry3_val[15:0]) & ~drif_rd_stall & | |
3470 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry3_dimm[2:0] | | |
3471 | drif_last_rank_picked[3:0] == {drq1_rd_entry3_rank,drq1_rd_entry3_dimm[2:0]}); | |
3472 | assign drif1_rd_entry_ready[4] = |(drif_bank_available[15:0] & drq1_rd_entry4_val[15:0]) & ~drif_rd_stall & | |
3473 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry4_dimm[2:0] | | |
3474 | drif_last_rank_picked[3:0] == {drq1_rd_entry4_rank,drq1_rd_entry4_dimm[2:0]}); | |
3475 | assign drif1_rd_entry_ready[5] = |(drif_bank_available[15:0] & drq1_rd_entry5_val[15:0]) & ~drif_rd_stall & | |
3476 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry5_dimm[2:0] | | |
3477 | drif_last_rank_picked[3:0] == {drq1_rd_entry5_rank,drq1_rd_entry5_dimm[2:0]}); | |
3478 | assign drif1_rd_entry_ready[6] = |(drif_bank_available[15:0] & drq1_rd_entry6_val[15:0]) & ~drif_rd_stall & | |
3479 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry6_dimm[2:0] | | |
3480 | drif_last_rank_picked[3:0] == {drq1_rd_entry6_rank,drq1_rd_entry6_dimm[2:0]}); | |
3481 | assign drif1_rd_entry_ready[7] = |(drif_bank_available[15:0] & drq1_rd_entry7_val[15:0]) & ~drif_rd_stall & | |
3482 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drq1_rd_entry7_dimm[2:0] | | |
3483 | drif_last_rank_picked[3:0] == {drq1_rd_entry7_rank,drq1_rd_entry7_dimm[2:0]}); | |
3484 | ||
3485 | // determine which writes are ready for issuing | |
3486 | assign drif_wr_ready = |(drif_bank_available[15:0] & drif_wr_bank_valids[15:0]); | |
3487 | assign drif_wr_pending = |(drif_bank_available[15:0] & woq_wr_bank_val[15:0]); | |
3488 | ||
3489 | assign drif_wr_stall = (drif_rd_pending & ~drif_pick_wr_first & ~drif_wr_entry_pend & drif_err_fifo_empty & | |
3490 | ~woq_wr_error_mode) | | |
3491 | drif_scrub_ready | ~(fbdic_l0_state | fbdic_chnl_reset_error_mode) | fbdic_sync_frame_req | | |
3492 | drif_cas_picked | drif_blk_new_openbank | fbdic_l0s_lfsr_stall | fbdic_error_mode; | |
3493 | ||
3494 | assign drif_wr_entry_ready[0] = |(drif_bank_available[15:0] & woq_entry0_val[15:0]) & ~drif_wr_stall & | |
3495 | (~drif_rank_wait | drif_last_rank_picked[3:0] == woq_entry0[6:3]); | |
3496 | ||
3497 | assign drif_wr_entry_ready[1] = ~drif_wr_entry_ready[0] & |(drif_bank_available[15:0] & woq_entry0_val[15:0]) & | |
3498 | (~drif_rank_wait | drif_last_rank_picked[3:0] == woq_entry0[6:3]) & | |
3499 | ~(woq0_wdq_rd | woq1_wdq_rd | drif_wdq_sel | drif_wdq_sel_d1) & | |
3500 | ~drif_blk_new_openbank & ~drif_cmd_b_val & drif_err_fifo_empty & | |
3501 | ~drif_pd_mode_pending & ~fbdic_error_mode & ~drif_mcu_state[2] & ~woq_wr_error_mode; | |
3502 | assign drif_wr_entry_ready[2] = |(drif_bank_available[15:0] & woq_entry1_val[15:0]) & | |
3503 | (~drif_rank_wait | drif_last_rank_picked[3:0] == woq_entry1[6:3]) & | |
3504 | drif_wr_entry_ready[1] & (woq_entry0[5:3] != woq_entry1[5:3]); | |
3505 | ||
3506 | // pick a read or a write to issue based on first-come-first-served policy | |
3507 | assign drif0_rd_entry_picked_in[0] = (~drif1_rd_ready | ~drif_entry_priority) & drif0_rd_entry_ready[0]; | |
3508 | assign drif0_rd_entry_picked_in[1] = (~drif1_rd_ready | ~drif_entry_priority) & (drif0_rd_entry_ready[1:0] == 2'h2); | |
3509 | assign drif0_rd_entry_picked_in[2] = (~drif1_rd_ready | ~drif_entry_priority) & (drif0_rd_entry_ready[2:0] == 3'h4); | |
3510 | assign drif0_rd_entry_picked_in[3] = (~drif1_rd_ready | ~drif_entry_priority) & (drif0_rd_entry_ready[3:0] == 4'h8); | |
3511 | assign drif0_rd_entry_picked_in[4] = (~drif1_rd_ready | ~drif_entry_priority) & (drif0_rd_entry_ready[4:0] == 5'h10); | |
3512 | assign drif0_rd_entry_picked_in[5] = (~drif1_rd_ready | ~drif_entry_priority) & (drif0_rd_entry_ready[5:0] == 6'h20); | |
3513 | assign drif0_rd_entry_picked_in[6] = (~drif1_rd_ready | ~drif_entry_priority) & (drif0_rd_entry_ready[6:0] == 7'h40); | |
3514 | assign drif0_rd_entry_picked_in[7] = (~drif1_rd_ready | ~drif_entry_priority) & (drif0_rd_entry_ready[7:0] == 8'h80); | |
3515 | ||
3516 | assign drif1_rd_entry_picked_in[0] = (~drif0_rd_ready | drif_entry_priority) & drif1_rd_entry_ready[0]; | |
3517 | assign drif1_rd_entry_picked_in[1] = (~drif0_rd_ready | drif_entry_priority) & (drif1_rd_entry_ready[1:0] == 2'h2); | |
3518 | assign drif1_rd_entry_picked_in[2] = (~drif0_rd_ready | drif_entry_priority) & (drif1_rd_entry_ready[2:0] == 3'h4); | |
3519 | assign drif1_rd_entry_picked_in[3] = (~drif0_rd_ready | drif_entry_priority) & (drif1_rd_entry_ready[3:0] == 4'h8); | |
3520 | assign drif1_rd_entry_picked_in[4] = (~drif0_rd_ready | drif_entry_priority) & (drif1_rd_entry_ready[4:0] == 5'h10); | |
3521 | assign drif1_rd_entry_picked_in[5] = (~drif0_rd_ready | drif_entry_priority) & (drif1_rd_entry_ready[5:0] == 6'h20); | |
3522 | assign drif1_rd_entry_picked_in[6] = (~drif0_rd_ready | drif_entry_priority) & (drif1_rd_entry_ready[6:0] == 7'h40); | |
3523 | assign drif1_rd_entry_picked_in[7] = (~drif0_rd_ready | drif_entry_priority) & (drif1_rd_entry_ready[7:0] == 8'h80); | |
3524 | ||
3525 | assign drif0_rd_entry_picked[7:0] = drif0_rd_entry_picked_in[7:0] & {8{~drif_scrub_picked & drif_sync_frame_req_l}}; | |
3526 | assign drif1_rd_entry_picked[7:0] = drif1_rd_entry_picked_in[7:0] & {8{~drif_scrub_picked & drif_sync_frame_req_l}}; | |
3527 | assign drif0_rd_picked = |drif0_rd_entry_picked[7:0]; | |
3528 | assign drif1_rd_picked = |drif1_rd_entry_picked[7:0]; | |
3529 | ||
3530 | assign drif_wr_entry_picked[0] = drif_wr_entry_ready[0] & fbdic_sync_frame_req_l & drif_sync_frame_req_l & | |
3531 | ~drif_scrub_picked; | |
3532 | assign drif_wr_entry_picked[1] = drif_wr_entry_ready[1] & fbdic_sync_frame_req_l & drif_sync_frame_req_l & | |
3533 | ~drif_scrub_picked & ~drif_rd_picked & ~fbdic_sync_frame_req_early2 & | |
3534 | ~fbdic_sync_frame_req_early1; | |
3535 | assign drif_wr_entry_picked[2] = drif_wr_entry_ready[2] & fbdic_sync_frame_req_l & drif_sync_frame_req_l & | |
3536 | ~drif_scrub_picked & ~drif_rd_picked & ~fbdic_sync_frame_req_early2 & | |
3537 | ~fbdic_sync_frame_req_early1; | |
3538 | assign drif0_wr_picked = drif_wr_entry_picked[0] & ~woq_entry0[15]; | |
3539 | assign drif1_wr_picked = drif_wr_entry_picked[0] & woq_entry0[15]; | |
3540 | assign drif0_wr1_picked = drif_wr_entry_picked[1] & ~woq_entry0[15]; | |
3541 | assign drif1_wr1_picked = drif_wr_entry_picked[1] & woq_entry0[15]; | |
3542 | assign drif0_wr2_picked = drif_wr_entry_picked[2] & ~woq_entry1[15]; | |
3543 | assign drif1_wr2_picked = drif_wr_entry_picked[2] & woq_entry1[15]; | |
3544 | ||
3545 | assign drif_rascas_adr_sel[1:0] = | |
3546 | (drif0_wr_picked | drif0_rd_picked | (drif0_err_rd_picked | drif0_err_wr_picked) & ~drif_err_fifo_scrub) ? 2'h1 : 2'h2; | |
3547 | assign drif_rascas_wr1_adr_sel[1:0] = drif0_wr1_picked ? 2'h1 : 2'h2; | |
3548 | assign drif_rascas_wr2_adr_sel[1:0] = drif0_wr2_picked ? 2'h1 : 2'h2; | |
3549 | ||
3550 | // round robin priority between l2_0 and l2_1 banks | |
3551 | assign drif_entry_priority_in = drif0_rd_picked & ~drif0_raw_hazard ? 1'b1 : | |
3552 | drif1_rd_picked & ~drif1_raw_hazard ? 1'b0 : drif_entry_priority; | |
3553 | ||
3554 | mcu_drif_ctl_msff_ctl_macro ff_entry_priority ( | |
3555 | .scan_in(ff_entry_priority_scanin), | |
3556 | .scan_out(ff_entry_priority_scanout), | |
3557 | .din(drif_entry_priority_in), | |
3558 | .dout(drif_entry_priority), | |
3559 | .l1clk(l1clk), | |
3560 | .siclk(siclk), | |
3561 | .soclk(soclk)); | |
3562 | ||
3563 | // determine which bank the selected transaction is going to and ensure there is no RAW hazard | |
3564 | assign drif_abnk_ras_picked[0] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h0) | | |
3565 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h0) | | |
3566 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h0) | | |
3567 | drif_scrub_picked & drif_scrub_entry_val[0] | | |
3568 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[0]; | |
3569 | assign drif_abnk_ras_picked[1] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h1) | | |
3570 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h1) | | |
3571 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h1) | | |
3572 | drif_scrub_picked & drif_scrub_entry_val[1] | | |
3573 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[1]; | |
3574 | assign drif_abnk_ras_picked[2] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h2) | | |
3575 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h2) | | |
3576 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h2) | | |
3577 | drif_scrub_picked & drif_scrub_entry_val[2] | | |
3578 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[2]; | |
3579 | assign drif_abnk_ras_picked[3] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h3) | | |
3580 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h3) | | |
3581 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h3) | | |
3582 | drif_scrub_picked & drif_scrub_entry_val[3] | | |
3583 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[3]; | |
3584 | assign drif_abnk_ras_picked[4] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h4) | | |
3585 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h4) | | |
3586 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h4) | | |
3587 | drif_scrub_picked & drif_scrub_entry_val[4] | | |
3588 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[4]; | |
3589 | assign drif_abnk_ras_picked[5] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h5) | | |
3590 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h5) | | |
3591 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h5) | | |
3592 | drif_scrub_picked & drif_scrub_entry_val[5] | | |
3593 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[5]; | |
3594 | assign drif_abnk_ras_picked[6] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h6) | | |
3595 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h6) | | |
3596 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h6) | | |
3597 | drif_scrub_picked & drif_scrub_entry_val[6] | | |
3598 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[6]; | |
3599 | assign drif_abnk_ras_picked[7] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h7) | | |
3600 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h7) | | |
3601 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h7) | | |
3602 | drif_scrub_picked & drif_scrub_entry_val[7] | | |
3603 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[7]; | |
3604 | assign drif_abnk_ras_picked[8] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h8) | | |
3605 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h8) | | |
3606 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h8) | | |
3607 | drif_scrub_picked & drif_scrub_entry_val[8] | | |
3608 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[8] ; | |
3609 | assign drif_abnk_ras_picked[9] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'h9) | | |
3610 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'h9) | | |
3611 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'h9) | | |
3612 | drif_scrub_picked & drif_scrub_entry_val[9] | | |
3613 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[9]; | |
3614 | assign drif_abnk_ras_picked[10] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'ha) | | |
3615 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'ha) | | |
3616 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'ha) | | |
3617 | drif_scrub_picked & drif_scrub_entry_val[10] | | |
3618 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[10]; | |
3619 | assign drif_abnk_ras_picked[11] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'hb) | | |
3620 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'hb) | | |
3621 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'hb) | | |
3622 | drif_scrub_picked & drif_scrub_entry_val[11] | | |
3623 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[11]; | |
3624 | assign drif_abnk_ras_picked[12] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'hc) | | |
3625 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'hc) | | |
3626 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'hc) | | |
3627 | drif_scrub_picked & drif_scrub_entry_val[12] | | |
3628 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[12]; | |
3629 | assign drif_abnk_ras_picked[13] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'hd) | | |
3630 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'hd) | | |
3631 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'hd) | | |
3632 | drif_scrub_picked & drif_scrub_entry_val[13] | | |
3633 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[13]; | |
3634 | assign drif_abnk_ras_picked[14] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'he) | | |
3635 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'he) | | |
3636 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'he) | | |
3637 | drif_scrub_picked & drif_scrub_entry_val[14] | | |
3638 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[14]; | |
3639 | assign drif_abnk_ras_picked[15] = drif0_rd_picked & (drq0_rd_addr_picked[3:0] == 4'hf) | | |
3640 | drif1_rd_picked & (drq1_rd_addr_picked[3:0] == 4'hf) | | |
3641 | drif_wr_picked & (woq_wr_addr_picked[3:0] == 4'hf) | | |
3642 | drif_scrub_picked & drif_scrub_entry_val[15] | | |
3643 | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_entry_val[15]; | |
3644 | assign drif_bcbnk_ras_picked[0] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h0) | | |
3645 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h0); | |
3646 | assign drif_bcbnk_ras_picked[1] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h1) | | |
3647 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h1); | |
3648 | assign drif_bcbnk_ras_picked[2] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h2) | | |
3649 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h2); | |
3650 | assign drif_bcbnk_ras_picked[3] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h3) | | |
3651 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h3); | |
3652 | assign drif_bcbnk_ras_picked[4] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h4) | | |
3653 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h4); | |
3654 | assign drif_bcbnk_ras_picked[5] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h5) | | |
3655 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h5); | |
3656 | assign drif_bcbnk_ras_picked[6] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h6) | | |
3657 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h6); | |
3658 | assign drif_bcbnk_ras_picked[7] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h7) | | |
3659 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h7); | |
3660 | assign drif_bcbnk_ras_picked[8] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h8) | | |
3661 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h8); | |
3662 | assign drif_bcbnk_ras_picked[9] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'h9) | | |
3663 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'h9); | |
3664 | assign drif_bcbnk_ras_picked[10] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'ha) | | |
3665 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'ha); | |
3666 | assign drif_bcbnk_ras_picked[11] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'hb) | | |
3667 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'hb); | |
3668 | assign drif_bcbnk_ras_picked[12] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'hc) | | |
3669 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'hc); | |
3670 | assign drif_bcbnk_ras_picked[13] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'hd) | | |
3671 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'hd); | |
3672 | assign drif_bcbnk_ras_picked[14] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'he) | | |
3673 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'he); | |
3674 | assign drif_bcbnk_ras_picked[15] = drif_wr1_picked & (woq_wr1_addr_picked[3:0] == 4'hf) | | |
3675 | drif_wr2_picked & (woq_wr2_addr_picked[3:0] == 4'hf); | |
3676 | ||
3677 | // cas_picked is ras_picked_d1 since using posted-cas | |
3678 | mcu_drif_ctl_msff_ctl_macro__en_1__width_16 ff_cas_abnk_picked ( | |
3679 | .scan_in(ff_cas_abnk_picked_scanin), | |
3680 | .scan_out(ff_cas_abnk_picked_scanout), | |
3681 | .din(drif_abnk_ras_picked[15:0]), | |
3682 | .dout(drif_abnk_cas_picked[15:0]), | |
3683 | .en(fbdic_sync_frame_req_l), | |
3684 | .l1clk(l1clk), | |
3685 | .siclk(siclk), | |
3686 | .soclk(soclk)); | |
3687 | ||
3688 | mcu_drif_ctl_msff_ctl_macro__en_1__width_16 ff_cas_bcbnk_picked ( | |
3689 | .scan_in(ff_cas_bcbnk_picked_scanin), | |
3690 | .scan_out(ff_cas_bcbnk_picked_scanout), | |
3691 | .din(drif_bcbnk_ras_picked[15:0]), | |
3692 | .dout(drif_bcbnk_cas_picked[15:0]), | |
3693 | .en(fbdic_sync_frame_req_l), | |
3694 | .l1clk(l1clk), | |
3695 | .siclk(siclk), | |
3696 | .soclk(soclk)); | |
3697 | ||
3698 | assign drif_bnk_ras_picked[15:0] = drif_abnk_ras_picked[15:0] | drif_bcbnk_ras_picked[15:0]; | |
3699 | assign drif_bnk_cas_picked[15:0] = drif_abnk_cas_picked[15:0] | drif_bcbnk_cas_picked[15:0]; | |
3700 | assign drif_cas_picked = |drif_bnk_cas_picked[15:0]; | |
3701 | assign drif_any_ras_picked = |drif_ras_picked[15:0]; | |
3702 | ||
3703 | assign drif_dmm_rd_ras_picked[0] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h0) | | |
3704 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h0) | | |
3705 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h0) | | |
3706 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h0); | |
3707 | assign drif_dmm_wr_ras_picked[0] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h0) | | |
3708 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h0); | |
3709 | assign drif_dmm_wrbc_ras_picked[0] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h0) | | |
3710 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h0); | |
3711 | ||
3712 | assign drif_dmm_rd_ras_picked[1] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h1) | | |
3713 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h1) | | |
3714 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h1) | | |
3715 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h1); | |
3716 | assign drif_dmm_wr_ras_picked[1] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h1) | | |
3717 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h1); | |
3718 | assign drif_dmm_wrbc_ras_picked[1] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h1) | | |
3719 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h1); | |
3720 | ||
3721 | assign drif_dmm_rd_ras_picked[2] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h2) | | |
3722 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h2) | | |
3723 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h2) | | |
3724 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h2); | |
3725 | assign drif_dmm_wr_ras_picked[2] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h2) | | |
3726 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h2); | |
3727 | assign drif_dmm_wrbc_ras_picked[2] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h2) | | |
3728 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h2); | |
3729 | ||
3730 | assign drif_dmm_rd_ras_picked[3] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h3) | | |
3731 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h3) | | |
3732 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h3) | | |
3733 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h3); | |
3734 | assign drif_dmm_wr_ras_picked[3] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h3) | | |
3735 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h3); | |
3736 | assign drif_dmm_wrbc_ras_picked[3] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h3) | | |
3737 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h3); | |
3738 | ||
3739 | assign drif_dmm_rd_ras_picked[4] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h4) | | |
3740 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h4) | | |
3741 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h4) | | |
3742 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h4); | |
3743 | assign drif_dmm_wr_ras_picked[4] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h4) | | |
3744 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h4); | |
3745 | assign drif_dmm_wrbc_ras_picked[4] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h4) | | |
3746 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h4); | |
3747 | ||
3748 | assign drif_dmm_rd_ras_picked[5] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h5) | | |
3749 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h5) | | |
3750 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h5) | | |
3751 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h5); | |
3752 | assign drif_dmm_wr_ras_picked[5] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h5) | | |
3753 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h5); | |
3754 | assign drif_dmm_wrbc_ras_picked[5] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h5) | | |
3755 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h5); | |
3756 | ||
3757 | assign drif_dmm_rd_ras_picked[6] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h6) | | |
3758 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h6) | | |
3759 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h6) | | |
3760 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h6); | |
3761 | assign drif_dmm_wr_ras_picked[6] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h6) | | |
3762 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h6); | |
3763 | assign drif_dmm_wrbc_ras_picked[6] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h6) | | |
3764 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h6); | |
3765 | ||
3766 | assign drif_dmm_rd_ras_picked[7] = drif0_rd_picked & (drq0_rd_addr_picked[6:4] == 3'h7) | | |
3767 | drif1_rd_picked & (drq1_rd_addr_picked[6:4] == 3'h7) | | |
3768 | drif_scrub_picked & (drif_scrub_dimm_adr[2:0] == 3'h7) | | |
3769 | drif_err_rd_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h7); | |
3770 | assign drif_dmm_wr_ras_picked[7] = drif_wr_picked & (woq_wr_addr_picked[6:4] == 3'h7) | | |
3771 | drif_err_wr_picked & (drif_err_fifo_dimm_adr[2:0] == 3'h7); | |
3772 | assign drif_dmm_wrbc_ras_picked[7] = drif_wr1_picked & (woq_wr1_addr_picked[6:4] == 3'h7) | | |
3773 | drif_wr2_picked & (woq_wr2_addr_picked[6:4] == 3'h7); | |
3774 | ||
3775 | // Last rank picked is kept track of here | |
3776 | // It is used to insert a dead cycle if successive transaction goes to | |
3777 | // opposite rank of last dimm picked | |
3778 | assign drif_last_rank_picked_en = |drif_ras_picked[15:0]; | |
3779 | assign drif_phy_bank_picked[3:0] = drif_last_rank_picked[3:0]; | |
3780 | assign drif_phy_bank_picked_en = drif_last_rank_picked_en; | |
3781 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 ff_rank_dimm_picked ( | |
3782 | .scan_in(ff_rank_dimm_picked_scanin), | |
3783 | .scan_out(ff_rank_dimm_picked_scanout), | |
3784 | .din({drif_rank_adr,drif_dimm_adr[2:0]}), | |
3785 | .dout(drif_last_rank_picked[3:0]), | |
3786 | .en(drif_last_rank_picked_en), | |
3787 | .l1clk(l1clk), | |
3788 | .siclk(siclk), | |
3789 | .soclk(soclk)); | |
3790 | ||
3791 | assign drif_ras_picked_d2_in = drif_cas_picked; | |
3792 | ||
3793 | mcu_drif_ctl_msff_ctl_macro__width_3 ff_ras_picked_d2 ( | |
3794 | .scan_in(ff_ras_picked_d2_scanin), | |
3795 | .scan_out(ff_ras_picked_d2_scanout), | |
3796 | .din({drif_ras_picked_d2_in,drif_ras_picked_d2,drif_ras_picked_d3}), | |
3797 | .dout({drif_ras_picked_d2,drif_ras_picked_d3,drif_ras_picked_d4}), | |
3798 | .l1clk(l1clk), | |
3799 | .siclk(siclk), | |
3800 | .soclk(soclk)); | |
3801 | ||
3802 | assign drif_rank_wait = drif_single_channel_mode ? drif_ras_picked_d4 : drif_ras_picked_d2; | |
3803 | ||
3804 | ////////////////////////////////////////////////////////////////// | |
3805 | // Generate signals necessary for Muxing RAS and CAS address - RAS PICKED | |
3806 | // Error transaction has priority, then scrub, then l2$ transaction | |
3807 | ////////////////////////////////////////////////////////////////// | |
3808 | ||
3809 | assign drif_scrub_entry_val[15:0] = drif_scrub_bank_valid[15:0] & | |
3810 | {16{(((drif_refresh_rank[3:0] != {drif_scrub_rank_adr,drif_scrub_dimm_adr[2:0]}) & | |
3811 | (drif_mcu_state[2] | drif_mcu_state[4]) & ~drif_init) | drif_mcu_state[1])}}; | |
3812 | ||
3813 | assign drif_ras_picked[15:0] = drif_abnk_ras_picked[15:0] | drif_bcbnk_ras_picked[15:0]; | |
3814 | ||
3815 | assign drif_scrub_ready = |(drif_bank_available[15:0] & drif_scrub_entry_val[15:0]) & (|drif_scrub_rank_avail[15:0]) & | |
3816 | ~drif_blk_new_openbank & drif_err_fifo_empty & drif_err_fifo_empty_d1 & | |
3817 | ~drif_4_activate_stall_scrub & fbdic_sync_frame_req_l & ~drif_cas_picked & | |
3818 | ~fbdic_l0s_lfsr_stall & ~rdpctl_fifo_full & ~fbdic_error_mode & ~rdpctl_kp_lnk_up; | |
3819 | ||
3820 | assign rtr_cnt_is_zero_scrub = drif_scrub_dimm_adr[2:0] == 3'h0 & rtr_cnt_is_zero[0] | | |
3821 | drif_scrub_dimm_adr[2:0] == 3'h1 & rtr_cnt_is_zero[1] | | |
3822 | drif_scrub_dimm_adr[2:0] == 3'h2 & rtr_cnt_is_zero[2] | | |
3823 | drif_scrub_dimm_adr[2:0] == 3'h3 & rtr_cnt_is_zero[3] | | |
3824 | drif_scrub_dimm_adr[2:0] == 3'h4 & rtr_cnt_is_zero[4] | | |
3825 | drif_scrub_dimm_adr[2:0] == 3'h5 & rtr_cnt_is_zero[5] | | |
3826 | drif_scrub_dimm_adr[2:0] == 3'h6 & rtr_cnt_is_zero[6] | | |
3827 | drif_scrub_dimm_adr[2:0] == 3'h7 & rtr_cnt_is_zero[7]; | |
3828 | ||
3829 | ||
3830 | assign wtr_cnt_is_zero_scrub = drif_scrub_dimm_adr[2:0] == 3'h0 & wtr_cnt_is_zero[0] | | |
3831 | drif_scrub_dimm_adr[2:0] == 3'h1 & wtr_cnt_is_zero[1] | | |
3832 | drif_scrub_dimm_adr[2:0] == 3'h2 & wtr_cnt_is_zero[2] | | |
3833 | drif_scrub_dimm_adr[2:0] == 3'h3 & wtr_cnt_is_zero[3] | | |
3834 | drif_scrub_dimm_adr[2:0] == 3'h4 & wtr_cnt_is_zero[4] | | |
3835 | drif_scrub_dimm_adr[2:0] == 3'h5 & wtr_cnt_is_zero[5] | | |
3836 | drif_scrub_dimm_adr[2:0] == 3'h6 & wtr_cnt_is_zero[6] | | |
3837 | drif_scrub_dimm_adr[2:0] == 3'h7 & wtr_cnt_is_zero[7]; | |
3838 | ||
3839 | assign drif_4_activate_stall_scrub = drif_scrub_dimm_adr[2:0] == 3'h0 & dmmdly_4_activate_stall[0] | | |
3840 | drif_scrub_dimm_adr[2:0] == 3'h1 & dmmdly_4_activate_stall[1] | | |
3841 | drif_scrub_dimm_adr[2:0] == 3'h2 & dmmdly_4_activate_stall[2] | | |
3842 | drif_scrub_dimm_adr[2:0] == 3'h3 & dmmdly_4_activate_stall[3] | | |
3843 | drif_scrub_dimm_adr[2:0] == 3'h4 & dmmdly_4_activate_stall[4] | | |
3844 | drif_scrub_dimm_adr[2:0] == 3'h5 & dmmdly_4_activate_stall[5] | | |
3845 | drif_scrub_dimm_adr[2:0] == 3'h6 & dmmdly_4_activate_stall[6] | | |
3846 | drif_scrub_dimm_adr[2:0] == 3'h7 & dmmdly_4_activate_stall[7]; | |
3847 | ||
3848 | assign drif_scrub_picked = drif_scrub_ready & rtr_cnt_is_zero_scrub & wtr_cnt_is_zero_scrub & rd_rrd_cnt_is_zero & | |
3849 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drif_scrub_dimm_adr[2:0] | | |
3850 | drif_last_rank_picked[3:0] == {drif_scrub_rank_adr,drif_scrub_dimm_adr[2:0]}); | |
3851 | ||
3852 | assign drif_rd_picked = drif0_rd_picked | drif1_rd_picked; | |
3853 | assign drif_wr_picked = drif0_wr_picked | drif1_wr_picked; | |
3854 | assign drif_wr1_picked = drif0_wr1_picked | drif1_wr1_picked; | |
3855 | assign drif_wr2_picked = drif0_wr2_picked | drif1_wr2_picked; | |
3856 | ||
3857 | assign drif_rd_addr_picked[8:0] = (|drif0_rd_entry_picked[7:0]) ? {drq0_rd_addr_picked[9:4],drq0_rd_addr_picked[2:0]} : | |
3858 | {drq1_rd_addr_picked[9:4],drq1_rd_addr_picked[2:0]}; | |
3859 | assign drif_rd_index_picked[2:0] = (|drif0_rd_entry_picked[7:0]) ? drq0_rd_index_picked[2:0] : drq1_rd_index_picked[2:0]; | |
3860 | ||
3861 | // Check for RAW hazards | |
3862 | ||
3863 | // matches between picked read and all valid writes | |
3864 | assign drif0_raw_match_in[7:0] = drq0_pending_wr_req[7:0] & {addrdp0_rd_wr_adr7_eq,addrdp0_rd_wr_adr6_eq, | |
3865 | addrdp0_rd_wr_adr5_eq, addrdp0_rd_wr_adr4_eq, | |
3866 | addrdp0_rd_wr_adr3_eq, addrdp0_rd_wr_adr2_eq, | |
3867 | addrdp0_rd_wr_adr1_eq, addrdp0_rd_wr_adr0_eq}; | |
3868 | ||
3869 | assign drif1_raw_match_in[7:0] = drq1_pending_wr_req[7:0] & {addrdp1_rd_wr_adr7_eq,addrdp1_rd_wr_adr6_eq, | |
3870 | addrdp1_rd_wr_adr5_eq, addrdp1_rd_wr_adr4_eq, | |
3871 | addrdp1_rd_wr_adr3_eq, addrdp1_rd_wr_adr2_eq, | |
3872 | addrdp1_rd_wr_adr1_eq, addrdp1_rd_wr_adr0_eq}; | |
3873 | ||
3874 | assign drif0_raw_hazard = |drif0_raw_match_in[7:0]; | |
3875 | assign drif1_raw_hazard = |drif1_raw_match_in[7:0]; | |
3876 | ||
3877 | // if there is a RAW hazard, give priority to writes until appropriate write queue entry has been picked | |
3878 | // if there are multiple matches, flushes until all are issued | |
3879 | assign drif_wr_entry_pend_in = drif0_raw_hazard & drif0_rd_picked | drif1_raw_hazard & drif1_rd_picked; | |
3880 | assign drif_wr_entry_pend_en = drif_wr_entry_pend_in; | |
3881 | assign drif_wr_entry_pend_clr = (drif0_haz_rd & drif0_wr_picked & (|(woq_wr_adr_queue_sel[7:0] & drif_raw_match[7:0])) | | |
3882 | drif0_haz_rd & drif0_wr1_picked & (|(woq_wr1_adr_queue_sel[7:0] & drif_raw_match[7:0])) | | |
3883 | drif0_haz_rd & drif0_wr2_picked & (|(woq_wr2_adr_queue_sel[7:0] & drif_raw_match[7:0])) | | |
3884 | ~drif0_haz_rd & drif1_wr_picked & (|(woq_wr_adr_queue_sel[7:0] & drif_raw_match[7:0])) | | |
3885 | ~drif0_haz_rd & drif1_wr1_picked & (|(woq_wr1_adr_queue_sel[7:0] & drif_raw_match[7:0])) | | |
3886 | ~drif0_haz_rd & drif1_wr2_picked & (|(woq_wr2_adr_queue_sel[7:0] & drif_raw_match[7:0]))); | |
3887 | ||
3888 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_wr_entry_pend ( | |
3889 | .scan_in(ff_wr_entry_pend_scanin), | |
3890 | .scan_out(ff_wr_entry_pend_scanout), | |
3891 | .din(drif_wr_entry_pend_in), | |
3892 | .dout(drif_wr_entry_pend), | |
3893 | .en(drif_wr_entry_pend_en), | |
3894 | .clr(drif_wr_entry_pend_clr), | |
3895 | .l1clk(l1clk), | |
3896 | .siclk(siclk), | |
3897 | .soclk(soclk)); | |
3898 | ||
3899 | assign drif0_haz_rd_in = drif_wr_entry_pend_en ? drif0_rd_picked : drif0_haz_rd; | |
3900 | assign drif_raw_match_in[7:0] = {8{drif_wr_entry_pend_en}} & | |
3901 | (drif0_rd_picked ? drif0_raw_match_in[7:0] : drif1_raw_match_in[7:0]); | |
3902 | ||
3903 | assign drif_raw_match_en = drif_wr_entry_pend_en | drif_wr_entry_pend_clr; | |
3904 | ||
3905 | mcu_drif_ctl_msff_ctl_macro__en_1__width_9 ff_raw_match ( | |
3906 | .scan_in(ff_raw_match_scanin), | |
3907 | .scan_out(ff_raw_match_scanout), | |
3908 | .din({drif0_haz_rd_in,drif_raw_match_in[7:0]}), | |
3909 | .dout({drif0_haz_rd,drif_raw_match[7:0]}), | |
3910 | .en(drif_raw_match_en), | |
3911 | .l1clk(l1clk), | |
3912 | .siclk(siclk), | |
3913 | .soclk(soclk)); | |
3914 | ||
3915 | // Priority picking of reads and writes | |
3916 | assign drif_rdwr_addr_picked[8:0] = (drif_pick_wr_first & drif_wr_picked) ? {woq_wr_addr_picked[9:4],woq_wr_addr_picked[2:0]} : | |
3917 | (|drif0_rd_entry_picked[7:0]) | (|drif1_rd_entry_picked[7:0]) ? drif_rd_addr_picked[8:0] : | |
3918 | drif_wr_picked ? {woq_wr_addr_picked[9:4],woq_wr_addr_picked[2:0]} : 9'h0; | |
3919 | ||
3920 | assign drif_rdwr_cmd_picked = (drif_pick_wr_first & drif_wr_picked) ? 1'b1 : | |
3921 | drif_rd_picked ? 1'b0 : | |
3922 | drif_wr_picked ? 1'b1 : 1'b0; | |
3923 | ||
3924 | assign drif_rdwr_index_picked[2:0] = (drif_pick_wr_first & drif_wr_picked) ? woq_wr_index_picked[2:0] : | |
3925 | drif_rd_picked ? drif_rd_index_picked[2:0] : | |
3926 | drif_wr_picked ? woq_wr_index_picked[2:0] : 3'h0; | |
3927 | ||
3928 | // when in 4-bank mode, use rank information for bank bit 2 when scheduling requests | |
3929 | assign drif_scrub_sched_bank_adr[3] = drif_eight_bank_mode_mod ? (drif_stacked_dimm ? drif_scrub_rank_adr : | |
3930 | drif_scrub_dimm_adr[0]) : | |
3931 | (drif_stacked_dimm ? drif_scrub_dimm_adr[0] : | |
3932 | drif_scrub_dimm_adr[1]); | |
3933 | assign drif_scrub_sched_bank_adr[2] = drif_eight_bank_mode_mod ? drif_scrub_bank_adr[2] : | |
3934 | drif_stacked_dimm ? drif_scrub_rank_adr : drif_scrub_dimm_adr[0]; | |
3935 | assign drif_scrub_sched_bank_adr[1:0] = drif_scrub_bank_adr[1:0]; | |
3936 | ||
3937 | assign drif_scrub_bank_valid[15:0] = {16{drif_scrub_read_pending}} & | |
3938 | {drif_scrub_sched_bank_adr[3:0] == 4'hf, drif_scrub_sched_bank_adr[3:0] == 4'he, | |
3939 | drif_scrub_sched_bank_adr[3:0] == 4'hd, drif_scrub_sched_bank_adr[3:0] == 4'hc, | |
3940 | drif_scrub_sched_bank_adr[3:0] == 4'hb, drif_scrub_sched_bank_adr[3:0] == 4'ha, | |
3941 | drif_scrub_sched_bank_adr[3:0] == 4'h9, drif_scrub_sched_bank_adr[3:0] == 4'h8, | |
3942 | drif_scrub_sched_bank_adr[3:0] == 4'h7, drif_scrub_sched_bank_adr[3:0] == 4'h6, | |
3943 | drif_scrub_sched_bank_adr[3:0] == 4'h5, drif_scrub_sched_bank_adr[3:0] == 4'h4, | |
3944 | drif_scrub_sched_bank_adr[3:0] == 4'h3, drif_scrub_sched_bank_adr[3:0] == 4'h2, | |
3945 | drif_scrub_sched_bank_adr[3:0] == 4'h1, drif_scrub_sched_bank_adr[3:0] == 4'h0}; | |
3946 | ||
3947 | assign drif_scrub_addr_picked[8:0] = drif_scrub_picked ? {drif_scrub_addr_parity,drif_scrub_addr_err,drif_scrub_rank_adr, | |
3948 | drif_scrub_dimm_adr[2:0],drif_scrub_sched_bank_adr[2:0]} : | |
3949 | (drif_err_rd_picked | drif_err_wr_picked) ? {drif_err_fifo_parity, 1'b0, | |
3950 | drif_err_fifo_rank_adr, | |
3951 | drif_err_fifo_dimm_adr[2:0], | |
3952 | drif_err_fifo_bank_adr[2:0]} : | |
3953 | drif_rdwr_addr_picked[8:0]; | |
3954 | ||
3955 | // Generate bank, ras, cas and addr error signals for wr addr. | |
3956 | assign drif_addr_parity = drif_scrub_addr_picked[8]; | |
3957 | assign drif_addr_err = drif_scrub_addr_picked[7]; | |
3958 | assign drif_rank_adr = drif_scrub_addr_picked[6]; | |
3959 | assign drif_dimm_adr[2:0] = drif_scrub_addr_picked[5:3]; | |
3960 | assign drif_bank_adr[2:0] = drif_scrub_addr_picked[2:0]; | |
3961 | assign drif_index_picked[2:0] = (drif_err_rd_picked | drif_err_wr_picked) ? drif_err_fifo_rdq_entry[2:0] : drif_rdwr_index_picked[2:0]; | |
3962 | assign drif_cmd_picked = drif_err_wr_picked ? 1'b1 : (drif_scrub_picked | drif_err_rd_picked) ? 1'b0 : drif_rdwr_cmd_picked; | |
3963 | ||
3964 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_cmd_picked_d1 ( | |
3965 | .scan_in(ff_cmd_picked_d1_scanin), | |
3966 | .scan_out(ff_cmd_picked_d1_scanout), | |
3967 | .din(drif_cmd_picked), | |
3968 | .dout(drif_cmd_picked_d1), | |
3969 | .en(fbdic_sync_frame_req_l), | |
3970 | .l1clk(l1clk), | |
3971 | .siclk(siclk), | |
3972 | .soclk(soclk)); | |
3973 | ||
3974 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_scrub_picked_d1 ( | |
3975 | .scan_in(ff_scrub_picked_d1_scanin), | |
3976 | .scan_out(ff_scrub_picked_d1_scanout), | |
3977 | .din(drif_scrub_picked), | |
3978 | .dout(drif_scrub_picked_d1), | |
3979 | .en(fbdic_sync_frame_req_l), | |
3980 | .l1clk(l1clk), | |
3981 | .siclk(siclk), | |
3982 | .soclk(soclk)); | |
3983 | ||
3984 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_addr_parity_d1 ( | |
3985 | .scan_in(ff_addr_parity_d1_scanin), | |
3986 | .scan_out(ff_addr_parity_d1_scanout), | |
3987 | .din(drif_addr_parity), | |
3988 | .dout(drif_addr_parity_d1), | |
3989 | .en(fbdic_sync_frame_req_l), | |
3990 | .l1clk(l1clk), | |
3991 | .siclk(siclk), | |
3992 | .soclk(soclk)); | |
3993 | ||
3994 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_addr_err_d1 ( | |
3995 | .scan_in(ff_addr_err_d1_scanin), | |
3996 | .scan_out(ff_addr_err_d1_scanout), | |
3997 | .din(drif_addr_err), | |
3998 | .dout(drif_addr_err_d1), | |
3999 | .en(fbdic_sync_frame_req_l), | |
4000 | .l1clk(l1clk), | |
4001 | .siclk(siclk), | |
4002 | .soclk(soclk)); | |
4003 | ||
4004 | // Making sure stores are not starved | |
4005 | // Keep a counter that triggers on drq_pending_wr_req all set | |
4006 | // and reaches a max cnt. Then give writes pref over reads | |
4007 | // till it counts down to 0. | |
4008 | ||
4009 | assign drif0_wr_starve_cnt_reset = ~(&drq0_pending_wr_req[7:0]) & ~drif0_pick_wr_first & ~drif0_pick_wr_first_in; | |
4010 | assign drif0_wr_starve_cnt_in[5:0] = | |
4011 | drif0_pick_wr_first & (drif0_wr_starve_cnt[5:0] != 6'h0) ? drif0_wr_starve_cnt[5:0] - 6'h1 : | |
4012 | ~drif0_pick_wr_first & (drif0_wr_starve_cnt[5:0] != 6'h3f) ? drif0_wr_starve_cnt[5:0] + 6'h1 : | |
4013 | drif0_wr_starve_cnt[5:0]; | |
4014 | mcu_drif_ctl_msff_ctl_macro__clr_1__width_6 ff_wr_starve_cnt0 ( | |
4015 | .scan_in(ff_wr_starve_cnt0_scanin), | |
4016 | .scan_out(ff_wr_starve_cnt0_scanout), | |
4017 | .din(drif0_wr_starve_cnt_in[5:0]), | |
4018 | .dout(drif0_wr_starve_cnt[5:0]), | |
4019 | .clr(drif0_wr_starve_cnt_reset), | |
4020 | .l1clk(l1clk), | |
4021 | .siclk(siclk), | |
4022 | .soclk(soclk)); | |
4023 | ||
4024 | assign drif0_pick_wr_first_in = (drif0_wr_starve_cnt[5:0] == 6'h3f); | |
4025 | assign drif0_pick_wr_first_reset = drif0_wr_starve_cnt[5:0] == 6'h0; | |
4026 | ||
4027 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_pick_wr_first0 ( | |
4028 | .scan_in(ff_pick_wr_first0_scanin), | |
4029 | .scan_out(ff_pick_wr_first0_scanout), | |
4030 | .din(drif0_pick_wr_first_in), | |
4031 | .dout(drif0_pick_wr_first), | |
4032 | .en(drif0_pick_wr_first_in), | |
4033 | .clr(drif0_pick_wr_first_reset), | |
4034 | .l1clk(l1clk), | |
4035 | .siclk(siclk), | |
4036 | .soclk(soclk)); | |
4037 | ||
4038 | assign drif1_wr_starve_cnt_reset = ~(&drq1_pending_wr_req[7:0]) & ~drif1_pick_wr_first & ~drif1_pick_wr_first_in; | |
4039 | assign drif1_wr_starve_cnt_in[5:0] = | |
4040 | drif1_pick_wr_first & (drif1_wr_starve_cnt[5:0] != 6'h0) ? drif1_wr_starve_cnt[5:0] - 6'h1 : | |
4041 | ~drif1_pick_wr_first & (drif1_wr_starve_cnt[5:0] != 6'h3f) ? drif1_wr_starve_cnt[5:0] + 6'h1 : | |
4042 | drif1_wr_starve_cnt[5:0]; | |
4043 | mcu_drif_ctl_msff_ctl_macro__clr_1__width_6 ff_wr_starve_cnt1 ( | |
4044 | .scan_in(ff_wr_starve_cnt1_scanin), | |
4045 | .scan_out(ff_wr_starve_cnt1_scanout), | |
4046 | .din(drif1_wr_starve_cnt_in[5:0]), | |
4047 | .dout(drif1_wr_starve_cnt[5:0]), | |
4048 | .clr(drif1_wr_starve_cnt_reset), | |
4049 | .l1clk(l1clk), | |
4050 | .siclk(siclk), | |
4051 | .soclk(soclk)); | |
4052 | ||
4053 | assign drif1_pick_wr_first_in = (drif1_wr_starve_cnt[5:0] == 6'h3f); | |
4054 | assign drif1_pick_wr_first_reset = drif1_wr_starve_cnt[5:0] == 6'h0; | |
4055 | ||
4056 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_pick_wr_first1 ( | |
4057 | .scan_in(ff_pick_wr_first1_scanin), | |
4058 | .scan_out(ff_pick_wr_first1_scanout), | |
4059 | .din(drif1_pick_wr_first_in), | |
4060 | .dout(drif1_pick_wr_first), | |
4061 | .en(drif1_pick_wr_first_in), | |
4062 | .clr(drif1_pick_wr_first_reset), | |
4063 | .l1clk(l1clk), | |
4064 | .siclk(siclk), | |
4065 | .soclk(soclk)); | |
4066 | ||
4067 | assign drif_pick_wr_first = drif0_pick_wr_first | drif1_pick_wr_first; | |
4068 | ||
4069 | ////////////////////////////////////////////////////////////////// | |
4070 | // Generating the signals to the pads | |
4071 | ////////////////////////////////////////////////////////////////// | |
4072 | assign drif_bnk_cas_picked_or = |drif_bnk_cas_picked[15:0]; | |
4073 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_cas_picked ( | |
4074 | .scan_in(ff_cas_picked_scanin), | |
4075 | .scan_out(ff_cas_picked_scanout), | |
4076 | .din(drif_bnk_cas_picked_or), | |
4077 | .dout(drif_cas_picked_io_d1), | |
4078 | .en(fbdic_sync_frame_req_l), | |
4079 | .l1clk(l1clk), | |
4080 | .siclk(siclk), | |
4081 | .soclk(soclk)); | |
4082 | ||
4083 | assign drif_ras_picked_io_d1[15:0] = drif_bnk_cas_picked[15:0]; | |
4084 | ||
4085 | assign drif_ras_adr[14:0] = drif_scrub_picked | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_fifo_scrub ? | |
4086 | drif_scrub_ras_adr[14:0] : addrdp_ras_adr_queue[14:0]; | |
4087 | ||
4088 | mcu_drif_ctl_msff_ctl_macro__en_1__width_15 ff_ras_adr_d1 ( | |
4089 | .scan_in(ff_ras_adr_d1_scanin), | |
4090 | .scan_out(ff_ras_adr_d1_scanout), | |
4091 | .din(drif_ras_adr[14:0]), | |
4092 | .dout(drif_ras_adr_d1_out[14:0]), | |
4093 | .en(fbdic_sync_frame_req_l), | |
4094 | .l1clk(l1clk), | |
4095 | .siclk(siclk), | |
4096 | .soclk(soclk)); | |
4097 | ||
4098 | assign drif_ras_adr_d1[14] = drif_mem_type[1:0] == 2'h2 & ~drif_cas_addr_bits[0] ? drif_cas_adr_d1_out[10] : | |
4099 | drif_ras_adr_d1_out[14]; | |
4100 | assign drif_ras_adr_d1[13] = drif_mem_type[1:0] == 2'h0 & ~drif_cas_addr_bits[0] ? drif_cas_adr_d1_out[10] : | |
4101 | drif_ras_adr_d1_out[13]; | |
4102 | assign drif_ras_adr_d1[12:0] = drif_ras_adr_d1_out[12:0]; | |
4103 | ||
4104 | assign drif_cas_adr[10:0] = drif_scrub_picked | (drif_err_rd_picked | drif_err_wr_picked) & drif_err_fifo_scrub ? | |
4105 | drif_scrub_cas_adr[10:0] : addrdp_cas_adr_queue[10:0]; | |
4106 | ||
4107 | // bit 10 is forced to 1 for autoprecharge | |
4108 | mcu_drif_ctl_msff_ctl_macro__en_1__width_11 ff_cas_adr_d1 ( | |
4109 | .scan_in(ff_cas_adr_d1_scanin), | |
4110 | .scan_out(ff_cas_adr_d1_scanout), | |
4111 | .din(drif_cas_adr[10:0]), | |
4112 | .dout(drif_cas_adr_d1_out[10:0]), | |
4113 | .en(fbdic_sync_frame_req_l), | |
4114 | .l1clk(l1clk), | |
4115 | .siclk(siclk), | |
4116 | .soclk(soclk)); | |
4117 | ||
4118 | mcu_drif_ctl_msff_ctl_macro__en_1__width_3 ff_req_id_d1 ( | |
4119 | .scan_in(ff_req_id_d1_scanin), | |
4120 | .scan_out(ff_req_id_d1_scanout), | |
4121 | .din({addrdp_rd_req_id_queue[2:0]}), | |
4122 | .dout(drif_rd_req_id_d1[2:0]), | |
4123 | .en(fbdic_sync_frame_req_l), | |
4124 | .l1clk(l1clk), | |
4125 | .siclk(siclk), | |
4126 | .soclk(soclk)); | |
4127 | ||
4128 | ||
4129 | assign drif_cas_adr_d1[10:0] = {drif_cas_adr_d1_out[10] & drif_cas_addr_bits[0], drif_cas_adr_d1_out[9:0]}; | |
4130 | ||
4131 | mcu_drif_ctl_msff_ctl_macro__en_1__width_11 ff_cas_adr_d2 ( | |
4132 | .scan_in(ff_cas_adr_d2_scanin), | |
4133 | .scan_out(ff_cas_adr_d2_scanout), | |
4134 | .din(drif_cas_adr_d1[10:0]), | |
4135 | .dout(drif_cas_adr_d2[10:0]), | |
4136 | .en(fbdic_sync_frame_req_l), | |
4137 | .l1clk(l1clk), | |
4138 | .siclk(siclk), | |
4139 | .soclk(soclk)); | |
4140 | ||
4141 | mcu_drif_ctl_msff_ctl_macro__en_1__width_6 ff_bank_adr ( | |
4142 | .scan_in(ff_bank_adr_scanin), | |
4143 | .scan_out(ff_bank_adr_scanout), | |
4144 | .din({drif_bank_adr[2:0],drif_bank_adr_d1[2:0]}), | |
4145 | .dout({drif_bank_adr_d1_out[2:0],drif_bank_adr_d2[2:0]}), | |
4146 | .en(fbdic_sync_frame_req_l), | |
4147 | .l1clk(l1clk), | |
4148 | .siclk(siclk), | |
4149 | .soclk(soclk)); | |
4150 | ||
4151 | assign drif_bank_adr_d1[2] = drif_mem_type[1:0] == 2'h1 & ~drif_cas_addr_bits[0] ? drif_cas_adr_d1_out[10] : | |
4152 | drif_bank_adr_d1_out[2]; | |
4153 | assign drif_bank_adr_d1[1:0] = drif_bank_adr_d1_out[1:0]; | |
4154 | ||
4155 | mcu_drif_ctl_msff_ctl_macro__en_1__width_6 ff_dimm_adr ( | |
4156 | .scan_in(ff_dimm_adr_scanin), | |
4157 | .scan_out(ff_dimm_adr_scanout), | |
4158 | .din({drif_dimm_adr[2:0],drif_dimm_adr_d1[2:0]}), | |
4159 | .dout({drif_dimm_adr_d1[2:0],drif_dimm_adr_d2[2:0]}), | |
4160 | .en(fbdic_sync_frame_req_l), | |
4161 | .l1clk(l1clk), | |
4162 | .siclk(siclk), | |
4163 | .soclk(soclk)); | |
4164 | ||
4165 | mcu_drif_ctl_msff_ctl_macro__en_1__width_2 ff_rank_adr ( | |
4166 | .scan_in(ff_rank_adr_scanin), | |
4167 | .scan_out(ff_rank_adr_scanout), | |
4168 | .din({drif_rank_adr,drif_rank_adr_d1}), | |
4169 | .dout({drif_rank_adr_d1,drif_rank_adr_d2}), | |
4170 | .en(fbdic_sync_frame_req_l), | |
4171 | .l1clk(l1clk), | |
4172 | .siclk(siclk), | |
4173 | .soclk(soclk)); | |
4174 | ||
4175 | assign drif_mux_write_en = drif_cmd_picked_d1; | |
4176 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_mux_wr_en ( | |
4177 | .scan_in(ff_mux_wr_en_scanin), | |
4178 | .scan_out(ff_mux_wr_en_scanout), | |
4179 | .din(drif_mux_write_en), | |
4180 | .dout(drif_mux_write_en_d1), | |
4181 | .en(fbdic_sync_frame_req_l), | |
4182 | .l1clk(l1clk), | |
4183 | .siclk(siclk), | |
4184 | .soclk(soclk)); | |
4185 | ||
4186 | assign drif_write_en_int = drif_mux_write_en_d1 & drif_cas_picked_io_d1; | |
4187 | ||
4188 | // Command A | |
4189 | assign drif_dram_cmd_a[2:0] = drif_cmd_a_val ? `FBD_DRAM_CMD_ACT : | |
4190 | drif_cmd_a_val_d1 & drif_write_en_int ? `FBD_DRAM_CMD_WR : | |
4191 | drif_cmd_a_val_d1 & ~drif_write_en_int ? `FBD_DRAM_CMD_RD : `FBD_DRAM_CMD_NOP; | |
4192 | ||
4193 | assign drif_dram_addr_a[15:0] = drif_cmd_a_val ? {1'b0,drif_ras_adr_d1[14:0]} : | |
4194 | {4'h0,drif_cas_adr_d2[10],1'b1,drif_cas_adr_d2[9:0]}; | |
4195 | ||
4196 | assign drif_dram_bank_a[2:0] = drif_cmd_a_val ? drif_bank_adr_d1[2:0] & {drif_eight_bank_mode_mod,2'h3} : | |
4197 | drif_bank_adr_d2[2:0] & {drif_eight_bank_mode_mod,2'h3}; | |
4198 | ||
4199 | assign drif_dram_rank_a = drif_cmd_a_val ? drif_rank_adr_d1 : drif_rank_adr_d2; | |
4200 | assign drif_dram_dimm_a[2:0] = drif_cmd_a_val ? drif_dimm_adr_d1[2:0] : drif_dimm_adr_d2[2:0]; | |
4201 | ||
4202 | // delay address for B and C commands | |
4203 | assign drif_cmd_a_val_in = (drif0_rd_picked & ~drif0_raw_hazard) | (drif1_rd_picked & ~drif1_raw_hazard) | | |
4204 | drif_wr_picked | drif_scrub_picked | drif_err_rd_picked | drif_err_wr_picked; | |
4205 | mcu_drif_ctl_msff_ctl_macro__en_1__width_3 ff_cmd_val ( | |
4206 | .scan_in(ff_cmd_val_scanin), | |
4207 | .scan_out(ff_cmd_val_scanout), | |
4208 | .din({drif_cmd_a_val_in,drif_wr_entry_picked[1],drif_wr_entry_picked[2]}), | |
4209 | .dout({drif_cmd_a_val,drif_cmd_b_val,drif_cmd_c_val}), | |
4210 | .en(fbdic_sync_frame_req_l), | |
4211 | .l1clk(l1clk), | |
4212 | .siclk(siclk), | |
4213 | .soclk(soclk)); | |
4214 | ||
4215 | // stall sending write data after write command if sync frame needs to be sent | |
4216 | assign drif_wr_bc_stall = drif_cmd_b_val & fbdic_sync_frame_req; | |
4217 | ||
4218 | mcu_drif_ctl_msff_ctl_macro__en_1__width_3 ff_cmd_val_d1 ( | |
4219 | .scan_in(ff_cmd_val_d1_scanin), | |
4220 | .scan_out(ff_cmd_val_d1_scanout), | |
4221 | .din({drif_cmd_a_val,drif_cmd_b_val,drif_cmd_c_val}), | |
4222 | .dout({drif_cmd_a_val_d1,drif_cmd_b_val_d1,drif_cmd_c_val_d1}), | |
4223 | .en(fbdic_sync_frame_req_l), | |
4224 | .l1clk(l1clk), | |
4225 | .siclk(siclk), | |
4226 | .soclk(soclk)); | |
4227 | ||
4228 | // B command RAS and CAS d1 | |
4229 | mcu_drif_ctl_msff_ctl_macro__en_1__width_26 ff_wr1_adr_d1 ( | |
4230 | .scan_in(ff_wr1_adr_d1_scanin), | |
4231 | .scan_out(ff_wr1_adr_d1_scanout), | |
4232 | .din({addrdp_ras_wr1_adr_queue[14:0],addrdp_cas_wr1_adr_queue[10:0]}), | |
4233 | .dout({drif_ras_wr1_adr_d1_out[14:0],drif_cas_wr1_adr_d1_out[10:0]}), | |
4234 | .en(fbdic_sync_frame_req_l), | |
4235 | .l1clk(l1clk), | |
4236 | .siclk(siclk), | |
4237 | .soclk(soclk)); | |
4238 | ||
4239 | mcu_drif_ctl_msff_ctl_macro__en_1__width_7 ff_write1_data ( | |
4240 | .scan_in(ff_write1_data_scanin), | |
4241 | .scan_out(ff_write1_data_scanout), | |
4242 | .din({woq_wr1_addr_picked[7:4],woq_wr1_addr_picked[2:0]}), | |
4243 | .dout({drif_rank_wr1_adr_d1,drif_dimm_wr1_adr_d1[2:0],drif_bank_wr1_adr_d1_out[2:0]}), | |
4244 | .en(fbdic_sync_frame_req_l), | |
4245 | .l1clk(l1clk), | |
4246 | .siclk(siclk), | |
4247 | .soclk(soclk)); | |
4248 | ||
4249 | assign drif_ras_wr1_adr_d1[14] = drif_mem_type[1:0] == 2'h2 & ~drif_cas_addr_bits[0] ? drif_cas_wr1_adr_d1_out[10] : | |
4250 | drif_ras_wr1_adr_d1_out[14]; | |
4251 | assign drif_ras_wr1_adr_d1[13] = drif_mem_type[1:0] == 2'h0 & ~drif_cas_addr_bits[0] ? drif_cas_wr1_adr_d1_out[10] : | |
4252 | drif_ras_wr1_adr_d1_out[13]; | |
4253 | assign drif_ras_wr1_adr_d1[12:0] = drif_ras_wr1_adr_d1_out[12:0]; | |
4254 | assign drif_cas_wr1_adr_d1[10:0] = {drif_cas_wr1_adr_d1_out[10] & drif_cas_addr_bits[0], drif_cas_wr1_adr_d1_out[9:0]}; | |
4255 | assign drif_bank_wr1_adr_d1[2] = drif_mem_type[1:0] == 2'h1 & ~drif_cas_addr_bits[0] ? drif_cas_wr1_adr_d1_out[10] : | |
4256 | drif_bank_wr1_adr_d1_out[2]; | |
4257 | assign drif_bank_wr1_adr_d1[1:0] = drif_bank_wr1_adr_d1_out[1:0]; | |
4258 | ||
4259 | // B command CAS rank, dimm, bank d2 | |
4260 | mcu_drif_ctl_msff_ctl_macro__en_1__width_18 ff_wr1_adr_d2 ( | |
4261 | .scan_in(ff_wr1_adr_d2_scanin), | |
4262 | .scan_out(ff_wr1_adr_d2_scanout), | |
4263 | .din({drif_cas_wr1_adr_d1[10:0],drif_rank_wr1_adr_d1,drif_dimm_wr1_adr_d1[2:0],drif_bank_wr1_adr_d1[2:0]}), | |
4264 | .dout({drif_cas_wr1_adr_d2[10:0],drif_rank_wr1_adr_d2,drif_dimm_wr1_adr_d2[2:0],drif_bank_wr1_adr_d2[2:0]}), | |
4265 | .en(fbdic_sync_frame_req_l), | |
4266 | .l1clk(l1clk), | |
4267 | .siclk(siclk), | |
4268 | .soclk(soclk)); | |
4269 | ||
4270 | // C command RAS and CAS d1 | |
4271 | mcu_drif_ctl_msff_ctl_macro__en_1__width_7 ff_write2_data ( | |
4272 | .scan_in(ff_write2_data_scanin), | |
4273 | .scan_out(ff_write2_data_scanout), | |
4274 | .din({woq_wr2_addr_picked[7:4],woq_wr2_addr_picked[2:0]}), | |
4275 | .dout({drif_rank_wr2_adr_d1,drif_dimm_wr2_adr_d1[2:0],drif_bank_wr2_adr_d1_out[2:0]}), | |
4276 | .en(fbdic_sync_frame_req_l), | |
4277 | .l1clk(l1clk), | |
4278 | .siclk(siclk), | |
4279 | .soclk(soclk)); | |
4280 | ||
4281 | mcu_drif_ctl_msff_ctl_macro__en_1__width_26 ff_wr2_adr_d1 ( | |
4282 | .scan_in(ff_wr2_adr_d1_scanin), | |
4283 | .scan_out(ff_wr2_adr_d1_scanout), | |
4284 | .din({addrdp_ras_wr2_adr_queue[14:0],addrdp_cas_wr2_adr_queue[10:0]}), | |
4285 | .dout({drif_ras_wr2_adr_d1_out[14:0],drif_cas_wr2_adr_d1_out[10:0]}), | |
4286 | .en(fbdic_sync_frame_req_l), | |
4287 | .l1clk(l1clk), | |
4288 | .siclk(siclk), | |
4289 | .soclk(soclk)); | |
4290 | ||
4291 | assign drif_ras_wr2_adr_d1[14] = drif_mem_type[1:0] == 2'h2 & ~drif_cas_addr_bits[0] ? drif_cas_wr2_adr_d1_out[10] : | |
4292 | drif_ras_wr2_adr_d1_out[14]; | |
4293 | assign drif_ras_wr2_adr_d1[13] = drif_mem_type[1:0] == 2'h0 & ~drif_cas_addr_bits[0] ? drif_cas_wr2_adr_d1_out[10] : | |
4294 | drif_ras_wr2_adr_d1_out[13]; | |
4295 | assign drif_ras_wr2_adr_d1[12:0] = drif_ras_wr2_adr_d1_out[12:0]; | |
4296 | assign drif_cas_wr2_adr_d1[10:0] = {drif_cas_wr2_adr_d1_out[10] & drif_cas_addr_bits[0], drif_cas_wr2_adr_d1_out[9:0]}; | |
4297 | assign drif_bank_wr2_adr_d1[2] = drif_mem_type[1:0] == 2'h1 & ~drif_cas_addr_bits[0] ? drif_cas_wr2_adr_d1_out[10] : | |
4298 | drif_bank_wr2_adr_d1_out[2]; | |
4299 | assign drif_bank_wr2_adr_d1[1:0] = drif_bank_wr2_adr_d1_out[1:0]; | |
4300 | ||
4301 | // C command CAS rank, dimm, bank d2 | |
4302 | mcu_drif_ctl_msff_ctl_macro__en_1__width_18 ff_wr2_adr_d2 ( | |
4303 | .scan_in(ff_wr2_adr_d2_scanin), | |
4304 | .scan_out(ff_wr2_adr_d2_scanout), | |
4305 | .din({drif_cas_wr2_adr_d1[10:0],drif_rank_wr2_adr_d1,drif_dimm_wr2_adr_d1[2:0],drif_bank_wr2_adr_d1[2:0]}), | |
4306 | .dout({drif_cas_wr2_adr_d2[10:0],drif_rank_wr2_adr_d2,drif_dimm_wr2_adr_d2[2:0],drif_bank_wr2_adr_d2[2:0]}), | |
4307 | .en(fbdic_sync_frame_req_l), | |
4308 | .l1clk(l1clk), | |
4309 | .siclk(siclk), | |
4310 | .soclk(soclk)); | |
4311 | ||
4312 | // Make sure Refresh is not issued to the same DIMM as an Activate, Read or Write | |
4313 | // 0in custom -fire (drif_dram_cmd_a[2:0] != 3'h0 & drif_dram_cmd_b[2:0] == 3'h1 & drif_dram_dimm_a[2:0] == drif_dram_dimm_b[2:0]) | |
4314 | ||
4315 | // Command B | |
4316 | assign drif_dram_cmd_b[2:0] = drif_refresh_req_picked ? `FBD_DRAM_CMD_OTHER : | |
4317 | drif_wdq_sel_d1 | drif_scrub_data_rden_en_d1 ? `FBD_DRAM_CMD_WDATA : | |
4318 | drif_cmd_b_val ? `FBD_DRAM_CMD_ACT : | |
4319 | drif_cmd_b_val_d1 ? `FBD_DRAM_CMD_WR : `FBD_DRAM_CMD_NOP; | |
4320 | assign drif_dram_addr_b[15:0] = drif_refresh_req_picked ? {13'h0, `FBD_DRAM_CMD_OTHER_REF} : | |
4321 | drif_cmd_b_val ? {1'b0,drif_ras_wr1_adr_d1[14:0]} : | |
4322 | {4'h0,drif_cas_wr1_adr_d2[10],1'b1,drif_cas_wr1_adr_d2[9:0]}; | |
4323 | assign drif_dram_bank_b[2:0] = drif_cmd_b_val ? drif_bank_wr1_adr_d1[2:0] & {drif_eight_bank_mode_mod,2'h3} : | |
4324 | drif_bank_wr1_adr_d2[2:0] & {drif_eight_bank_mode_mod,2'h3}; | |
4325 | assign drif_dram_rank_b = drif_refresh_req_picked ? drif_refresh_rank[3] : | |
4326 | drif_cmd_b_val ? drif_rank_wr1_adr_d1 : drif_rank_wr1_adr_d2; | |
4327 | assign drif_dram_dimm_b[2:0] = drif_refresh_req_picked ? drif_refresh_rank[2:0] : | |
4328 | drif_cmd_b_val ? drif_dimm_wr1_adr_d1[2:0] : drif_dimm_wr1_adr_d2[2:0]; | |
4329 | ||
4330 | // Make sure Power Down or Self Refresh command is not issued to the same DIMM as an Activate, Read or Write | |
4331 | /* 0in custom -fire (drif_dram_cmd_a[2:0] != 3'h0 & drif_dram_cmd_c[2:0] == 3'h1 & | |
4332 | drif_dram_dimm_a[2:0] == drif_dram_dimm_c[2:0] & drif_dram_cmd_b[2:0] != 3'h5) */ | |
4333 | ||
4334 | // Command C | |
4335 | assign drif_dram_cmd_c[2:0] = drif_cmd_c_val ? `FBD_DRAM_CMD_ACT : | |
4336 | drif_cmd_c_val_d1 ? `FBD_DRAM_CMD_WR : | |
4337 | drif_pd_mode_pending | (drif_enter_self_refresh | drif_exit_self_refresh) & | |
4338 | fbdic_sync_frame_req_l ? `FBD_DRAM_CMD_OTHER : `FBD_DRAM_CMD_NOP; | |
4339 | assign drif_dram_addr_c[15:0] = drif_cmd_c_val ? {1'b0,drif_ras_wr2_adr_d1[14:0]} : | |
4340 | drif_cmd_c_val_d1 ? {4'h0,drif_cas_wr2_adr_d2[10],1'b1,drif_cas_wr2_adr_d2[9:0]} : | |
4341 | drif_enter_self_refresh ? {13'h0, `FBD_DRAM_CMD_OTHER_SRE} : | |
4342 | drif_pd_mode_exit_pending | drif_exit_self_refresh ? {13'h0, `FBD_DRAM_CMD_OTHER_SRPDX} : | |
4343 | drif_pd_mode_enter_pending ? {13'h0, `FBD_DRAM_CMD_OTHER_PDE} : 16'h0; | |
4344 | assign drif_dram_bank_c[2:0] = drif_cmd_c_val ? drif_bank_wr2_adr_d1[2:0] & {drif_eight_bank_mode_mod,2'h3} : | |
4345 | drif_bank_wr2_adr_d2[2:0] & {drif_eight_bank_mode_mod,2'h3}; | |
4346 | assign drif_dram_rank_c = drif_cmd_c_val ? drif_rank_wr2_adr_d1 : | |
4347 | drif_cmd_c_val_d1 ? drif_rank_wr2_adr_d2 : | |
4348 | drif_enter_self_refresh | drif_exit_self_refresh ? drif_refresh_rank[3] : | |
4349 | drif_pd_mode_exit_pending ? drif_pd_mode_exit_rank : | |
4350 | drif_pd_mode_enter_pending ? drif_pd_mode_enter_rank : 1'b0; | |
4351 | assign drif_dram_dimm_c[2:0] = drif_cmd_c_val ? drif_dimm_wr2_adr_d1[2:0] : | |
4352 | drif_cmd_c_val_d1 ? drif_dimm_wr2_adr_d2[2:0] : | |
4353 | drif_enter_self_refresh | drif_exit_self_refresh ? drif_refresh_rank[2:0] : | |
4354 | drif_pd_mode_exit_pending ? drif_pd_mode_exit_dimm[2:0] : | |
4355 | drif_pd_mode_enter_pending ? drif_pd_mode_enter_dimm[2:0] : 3'h0; | |
4356 | ||
4357 | assign drif_scrub_wsn = (drif_scrub_data_rden[1:0] == 2'h1) & drif_err_fifo_dimm_adr[0] | | |
4358 | (drif_scrub_data_rden[1:0] == 2'h2) & drif_err_fifo_dimm_adr[1] | | |
4359 | (drif_scrub_data_rden[1:0] == 2'h3) & drif_err_fifo_dimm_adr[2]; | |
4360 | ||
4361 | assign drif_wdata_wsn = drif_scrub_data_rden_en | drif_scrub_data_rden_en_d1 ? | |
4362 | drif_scrub_wsn : drif_wdata_wsn_out; | |
4363 | mcu_drif_ctl_msff_ctl_macro__width_1 ff_wdata_wsn ( | |
4364 | .scan_in(ff_wdata_wsn_scanin), | |
4365 | .scan_out(ff_wdata_wsn_scanout), | |
4366 | .din(woq_wdata_wsn), | |
4367 | .dout(drif_wdata_wsn_out), | |
4368 | .l1clk(l1clk), | |
4369 | .siclk(siclk), | |
4370 | .soclk(soclk)); | |
4371 | ||
4372 | ////////////////////////////////////////////////////////////////// | |
4373 | // Generating the signals to store data buffer for READING DATA | |
4374 | ////////////////////////////////////////////////////////////////// | |
4375 | ||
4376 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 ff_rd_wr_picked_d1 ( | |
4377 | .scan_in(ff_rd_wr_picked_d1_scanin), | |
4378 | .scan_out(ff_rd_wr_picked_d1_scanout), | |
4379 | .din({drif1_rd_picked,woq1_wr_picked[2:0]}), | |
4380 | .dout({drif1_rd_picked_d1,drif1_wr2_picked_d1,drif1_wr1_picked_d1,drif1_wr_picked_d1}), | |
4381 | .en(fbdic_sync_frame_req_l), | |
4382 | .l1clk(l1clk), | |
4383 | .siclk(siclk), | |
4384 | .soclk(soclk)); | |
4385 | ||
4386 | assign drif0_wdq_radr[4:0] = woq_wdq_radr[4:0]; | |
4387 | assign drif1_wdq_radr[4:0] = drif0_wdq_radr[4:0]; | |
4388 | assign drif_wdq_radr[4:0] = drif1_wdq_radr[4:0]; | |
4389 | assign drif0_wdq_rd = drif0_wdq_sel_in; | |
4390 | assign drif1_wdq_rd = drif1_wdq_sel_in; | |
4391 | ||
4392 | // These 0in checks are for rd/wr conflict at memories | |
4393 | // 0in custom -fire (woq0_wdq_rd & drif0_wdq_rd_inh & drif0_cpu_wr_addr[2:0] == drif0_wdq_radr[4:2]) | |
4394 | // 0in custom -fire (woq1_wdq_rd & drif1_wdq_rd_inh & drif1_cpu_wr_addr[2:0] == drif1_wdq_radr[4:2]) | |
4395 | assign drif0_wdq_sel_in = woq0_wdq_rd & ~drif_err_state[`DRIF_ERR_READ1] & | |
4396 | ~(drif0_wdq_rd_inh & drif0_cpu_wr_addr[2:0] == drif0_wdq_radr[4:2]); | |
4397 | assign drif1_wdq_sel_in = woq1_wdq_rd & ~drif_err_state[`DRIF_ERR_READ1] & | |
4398 | ~(drif1_wdq_rd_inh & drif1_cpu_wr_addr[2:0] == drif1_wdq_radr[4:2]); | |
4399 | ||
4400 | mcu_drif_ctl_msff_ctl_macro__width_4 ff0_wr_entry0 ( | |
4401 | .scan_in(ff0_wr_entry0_scanin), | |
4402 | .scan_out(ff0_wr_entry0_scanout), | |
4403 | .din({l2if0_wdq_rd_inh,l2if0_data_wr_addr[2:0]}), | |
4404 | .dout({drif0_wdq_rd_inh,drif0_cpu_wr_addr[2:0]}), | |
4405 | .l1clk(l1clk), | |
4406 | .siclk(siclk), | |
4407 | .soclk(soclk)); | |
4408 | ||
4409 | mcu_drif_ctl_msff_ctl_macro__width_4 ff1_wr_entry0 ( | |
4410 | .scan_in(ff1_wr_entry0_scanin), | |
4411 | .scan_out(ff1_wr_entry0_scanout), | |
4412 | .din({l2if1_wdq_rd_inh,l2if1_data_wr_addr[2:0]}), | |
4413 | .dout({drif1_wdq_rd_inh,drif1_cpu_wr_addr[2:0]}), | |
4414 | .l1clk(l1clk), | |
4415 | .siclk(siclk), | |
4416 | .soclk(soclk)); | |
4417 | ||
4418 | // mux select for routing data from wdq to wrdp | |
4419 | mcu_drif_ctl_msff_ctl_macro__width_2 ff_wdq_sel ( | |
4420 | .scan_in(ff_wdq_sel_scanin), | |
4421 | .scan_out(ff_wdq_sel_scanout), | |
4422 | .din({drif0_wdq_sel_in,drif1_wdq_sel_in}), | |
4423 | .dout({drif0_wdq_sel,drif1_wdq_sel}), | |
4424 | .l1clk(l1clk), | |
4425 | .siclk(siclk), | |
4426 | .soclk(soclk)); | |
4427 | ||
4428 | // 0in one_hot -var drif_wdata_sel[3:0] | |
4429 | assign drif_wdata_sel[3:0] = ~drif_err_state[`DRIF_ERR_READ1] & drif0_wdq_sel ? 4'h1 : | |
4430 | ~drif_err_state[`DRIF_ERR_READ1] & drif1_wdq_sel ? 4'h2 : | |
4431 | drif_single_channel_mode ? {drif_scrub_data_rden[1],~drif_scrub_data_rden[1],2'h0} : | |
4432 | {drif_scrub_data_rden[0],~drif_scrub_data_rden[0],2'h0}; | |
4433 | ||
4434 | // Generate signal for sending scrub data to IOs | |
4435 | assign drif_scrub_rwen = rdpctl_scrub_wren | fbdic_sync_frame_req_early1_l & | |
4436 | (~drif_single_channel_mode & drif_scrub_data_rden[0] | | |
4437 | drif_single_channel_mode & drif_scrub_data_rden[1] & drif_scrub_data_rden[0]); | |
4438 | ||
4439 | assign drif_scrub_data_rden_in[2:0] = (drif_scrub_data_rden[2:0] == 3'h3) & ~drif_single_channel_mode ? 3'h0 : | |
4440 | drif_scrub_data_rden[2:0] + 3'h1; | |
4441 | assign drif_scrub_data_rden_en = (drif_scrub_buffer_full & ~drif_multi_err | (|drif_scrub_data_rden[2:0])) & | |
4442 | fbdic_sync_frame_req_early1_l & ~drif_refresh_req_picked & | |
4443 | ~(drif_mcu_state[2] & drif_scrub_data_rden[2:0] == 3'h0) & | |
4444 | ~drif_mcu_state[3]; | |
4445 | ||
4446 | mcu_drif_ctl_msff_ctl_macro__en_1__width_3 ff_scrub_data_rden ( | |
4447 | .scan_in(ff_scrub_data_rden_scanin), | |
4448 | .scan_out(ff_scrub_data_rden_scanout), | |
4449 | .din(drif_scrub_data_rden_in[2:0]), | |
4450 | .dout(drif_scrub_data_rden[2:0]), | |
4451 | .en(drif_scrub_data_rden_en), | |
4452 | .l1clk(l1clk), | |
4453 | .siclk(siclk), | |
4454 | .soclk(soclk)); | |
4455 | ||
4456 | // Show when data is in scrub buffer and ready to send to fbdimms | |
4457 | assign drif_scrub_buffer_full = drif_scrub_buffer_cnt[1:0] == 2'h2; | |
4458 | assign drif_scrub_buffer_cnt_in[1:0] = drif_scrub_wren_d2 ? drif_scrub_buffer_cnt[1:0] + 2'h1 : | |
4459 | drif_scrub_data_rden_en | drif_scrub_buffer_full & drif_multi_err ? 2'h0 : | |
4460 | drif_scrub_buffer_cnt[1:0]; | |
4461 | ||
4462 | mcu_drif_ctl_msff_ctl_macro__width_2 ff_scrub_buffer_cnt ( | |
4463 | .scan_in(ff_scrub_buffer_cnt_scanin), | |
4464 | .scan_out(ff_scrub_buffer_cnt_scanout), | |
4465 | .din(drif_scrub_buffer_cnt_in[1:0]), | |
4466 | .dout(drif_scrub_buffer_cnt[1:0]), | |
4467 | .l1clk(l1clk), | |
4468 | .siclk(siclk), | |
4469 | .soclk(soclk)); | |
4470 | ||
4471 | // if a multi-nibble error occurs, don't write data back to memory | |
4472 | assign drif_multi_err_in = (|readdp_ecc_multi_err[1:0]) & drif_scrub_wren ? 1'b1 : | |
4473 | drif_scrub_buffer_full & drif_multi_err ? 1'b0 : drif_multi_err; | |
4474 | mcu_drif_ctl_msff_ctl_macro ff_multi_err ( | |
4475 | .scan_in(ff_multi_err_scanin), | |
4476 | .scan_out(ff_multi_err_scanout), | |
4477 | .din(drif_multi_err_in), | |
4478 | .dout(drif_multi_err), | |
4479 | .l1clk(l1clk), | |
4480 | .siclk(siclk), | |
4481 | .soclk(soclk)); | |
4482 | ||
4483 | // set a flag when issuing an error write so mcu can ignore write complete status | |
4484 | assign drif_woq_free[1:0] = fbdic_woq_free[1:0] & {2{~drif_error_write_flag}}; | |
4485 | assign drif_error_write_flag_in = drif_scrub_data_rden_en ? 1'b1 : (|fbdic_woq_free[1:0]) ? 1'b0 : drif_error_write_flag; | |
4486 | mcu_drif_ctl_msff_ctl_macro ff_error_write_flag ( | |
4487 | .scan_in(ff_error_write_flag_scanin), | |
4488 | .scan_out(ff_error_write_flag_scanout), | |
4489 | .din(drif_error_write_flag_in), | |
4490 | .dout(drif_error_write_flag), | |
4491 | .l1clk(l1clk), | |
4492 | .siclk(siclk), | |
4493 | .soclk(soclk)); | |
4494 | ||
4495 | mcu_drif_ctl_msff_ctl_macro__width_2 ff_scrub_data_rden_en_d1 ( | |
4496 | .scan_in(ff_scrub_data_rden_en_d1_scanin), | |
4497 | .scan_out(ff_scrub_data_rden_en_d1_scanout), | |
4498 | .din({drif_scrub_data_rden_en,drif_scrub_data_rden[0]}), | |
4499 | .dout({drif_scrub_data_rden_en_d1,drif_scrub_data_rden0_d1}), | |
4500 | .l1clk(l1clk), | |
4501 | .siclk(siclk), | |
4502 | .soclk(soclk)); | |
4503 | ||
4504 | //`ifdef MCU_BUG_118947 | |
4505 | //assign drif_err_wrdata_ready_in = (&drif_scrub_data_rden[1:0]) & (drif_single_channel_mode & drif_scrub_data_rden[2] | | |
4506 | // ~drif_single_channel_mode) ? 1'b1 : | |
4507 | // drif_err_wr_picked | drif_scrub_wr_drop ? 1'b0 : drif_err_wrdata_ready; | |
4508 | //`else | |
4509 | assign drif_err_wrdata_ready_in = (&drif_scrub_data_rden[1:0]) & (drif_single_channel_mode & drif_scrub_data_rden[2] | | |
4510 | ~drif_single_channel_mode) ? 1'b1 : | |
4511 | drif_err_wr_picked ? 1'b0 : drif_err_wrdata_ready; | |
4512 | //`endif | |
4513 | ||
4514 | mcu_drif_ctl_msff_ctl_macro ff_err_wrdata_ready ( | |
4515 | .scan_in(ff_err_wrdata_ready_scanin), | |
4516 | .scan_out(ff_err_wrdata_ready_scanout), | |
4517 | .din(drif_err_wrdata_ready_in), | |
4518 | .dout(drif_err_wrdata_ready), | |
4519 | .l1clk(l1clk), | |
4520 | .siclk(siclk), | |
4521 | .soclk(soclk)); | |
4522 | ||
4523 | // select between upper and lower doublewords for single-dimm mode | |
4524 | assign drif_io_wdata_sel[1:0] = drif_err_state[`DRIF_ERR_WRITE] & drif_single_channel_mode ? | |
4525 | {drif_scrub_data_rden0_d1,~drif_scrub_data_rden0_d1} : woq_io_wdata_sel[1:0]; | |
4526 | ||
4527 | /////// | |
4528 | // Stage the address parity bit so that store data ecc can be XORed with this bit. | |
4529 | /////// | |
4530 | assign drif_wadr_parity_p2 = drif_err_state[`DRIF_ERR_IDLE] ? woq_wadr_parity : drif_err_fifo_parity; | |
4531 | mcu_drif_ctl_msff_ctl_macro__width_2 ff_wadr_parity ( | |
4532 | .scan_in(ff_wadr_parity_scanin), | |
4533 | .scan_out(ff_wadr_parity_scanout), | |
4534 | .din({drif_wadr_parity_p2,drif_wadr_parity_p1}), | |
4535 | .dout({drif_wadr_parity_p1,drif_wadr_parity}), | |
4536 | .l1clk(l1clk), | |
4537 | .siclk(siclk), | |
4538 | .soclk(soclk)); | |
4539 | ||
4540 | ////////////////////////////////////////////////////////////////// | |
4541 | // Store ID and the offset for read request response | |
4542 | ////////////////////////////////////////////////////////////////// | |
4543 | mcu_drif_ctl_msff_ctl_macro__en_1__width_9 ff_rd_index_d1 ( | |
4544 | .scan_in(ff_rd_index_d1_scanin), | |
4545 | .scan_out(ff_rd_index_d1_scanout), | |
4546 | .din({drif_rd_index_picked[2:0],woq_wr_index_picked[2:0],woq_wr_wdq_index_picked[2:0]}), | |
4547 | .dout({drif_rd_index_d1[2:0],drif_wr_index_d1[2:0],drif_wr_wdq_index_d1[2:0]}), | |
4548 | .en(drif_sync_frame_req_l), | |
4549 | .l1clk(l1clk), | |
4550 | .siclk(siclk), | |
4551 | .soclk(soclk)); | |
4552 | ||
4553 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_err_fifo_err_type_d1 ( | |
4554 | .scan_in(ff_err_fifo_err_type_d1_scanin), | |
4555 | .scan_out(ff_err_fifo_err_type_d1_scanout), | |
4556 | .din(drif_err_fifo_err_type), | |
4557 | .dout(drif_err_fifo_err_type_d1), | |
4558 | .en(drif_sync_frame_req_l), | |
4559 | .l1clk(l1clk), | |
4560 | .siclk(siclk), | |
4561 | .soclk(soclk)); | |
4562 | ||
4563 | // read/write data info for rdpctl | |
4564 | assign drif_send_info_val = drif_cmd_a_val & ~drif_mux_write_en & drif_sync_frame_req_l; | |
4565 | assign drif_send_info[19:0] = { drif_err_rd_picked_d1 & drif_err_fifo_crc_d1, | |
4566 | drif_err_rd_picked_d1 & ~drif_err_fifo_crc_d1, | |
4567 | drif_rank_adr_d1, | |
4568 | drif_dimm_adr_d1[2:0], | |
4569 | {drif_bank_adr_d1_out[2],drif_bank_adr_d1[1:0]}, | |
4570 | (drif_err_rd_picked_d1 & ~drif_err_fifo_crc_d1 ? drif_err_fifo_err_type_d1 : drif_addr_err_d1), | |
4571 | drif_addr_parity_d1, | |
4572 | (drif_err_rd_picked_d1 ? drif_err_fifo_scrub : drif_scrub_picked_d1), | |
4573 | (drif_err_rd_picked_d1 ? drif_err_fifo_rdq_entry_d1[2:0] : drif_rd_index_d1[2:0]), | |
4574 | (drif_err_rd_picked_d1 & ~drif_err_fifo_crc_d1 ? {2'h0,drif_err_state[`DRIF_ERR_IDLE]} : drif_rd_req_id_d1[2:0]), | |
4575 | (drif_single_channel_mode ? drif_cas_adr_d1[2] : drif_cas_adr_d1[1]), | |
4576 | (drif_err_rd_picked_d1 ? drif_err_fifo_l2bank : drif1_rd_picked_d1)}; | |
4577 | ||
4578 | ///////////////////////////////////////////////////////////// | |
4579 | // MAIN STATE MACHINE THAT KEEPS TRACK OF THE CONTROLLER STATE | |
4580 | ///////////////////////////////////////////////////////////// | |
4581 | ||
4582 | // 0in one_hot -var drif_mcu_state[7:0] | |
4583 | ||
4584 | assign drif_mcu_state[7:0] = { | |
4585 | drif_mcu_state_enc[4:0] == 5'd7, drif_mcu_state_enc[4:0] == 5'd6, | |
4586 | drif_mcu_state_enc[4:0] == 5'd5, drif_mcu_state_enc[4:0] == 5'd4, | |
4587 | drif_mcu_state_enc[4:0] == 5'd3, drif_mcu_state_enc[4:0] == 5'd2, | |
4588 | drif_mcu_state_enc[4:0] == 5'd1, drif_mcu_state_enc[4:0] == 5'd0}; | |
4589 | ||
4590 | mcu_drif_ctl_msff_ctl_macro__width_5 ff_mcu_state_enc ( | |
4591 | .scan_in(ff_mcu_state_enc_scanin), | |
4592 | .scan_out(ff_mcu_state_enc_scanout), | |
4593 | .din(drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0]), | |
4594 | .dout(drif_mcu_state_enc[`DRIF_MCU_STATE_MAX:0]), | |
4595 | .l1clk(l1clk), | |
4596 | .siclk(siclk), | |
4597 | .soclk(soclk)); | |
4598 | ||
4599 | always @(drif_stacked_dimm or dal_reg or drif_err_wr_picked or drif_bank_idle_cnt | |
4600 | or drif_cyc_cnt or drif_mcu_state_enc or drif_scrub_picked | |
4601 | or drif_hw_selfrsh or drif_init or drif_wr_picked or drif_rd_picked | |
4602 | or drif_ref_go or drif_refresh_rank or drif_last_rank or rfc_cnt_is_zero | |
4603 | or drif_err_rd_picked or ral_reg or rc_reg or fbdic_sync_frame_req_l | |
4604 | or drif_enter_self_refresh or drif_exit_self_refresh or drif_cmd_a_val | |
4605 | or drif_cmd_a_val_d1 or drif_dram_dimm_a or fbdic_error_mode or drif_wdq_sel_d1) | |
4606 | begin | |
4607 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = drif_mcu_state_enc[`DRIF_MCU_STATE_MAX:0]; | |
4608 | drif_cyc_cnt_next[7:0] = 8'h0; | |
4609 | drif_bank_idle_cnt_next[4:0] = drif_bank_idle_cnt[4:0]; | |
4610 | drif_refresh_rank_in[4:0] = drif_refresh_rank[4:0]; | |
4611 | set_drif_enter_self_refresh = 1'b0; | |
4612 | set_drif_exit_self_refresh = 1'b0; | |
4613 | ||
4614 | case (drif_mcu_state_enc[`DRIF_MCU_STATE_MAX:0]) | |
4615 | 5'd0: begin | |
4616 | if (drif_hw_selfrsh) begin | |
4617 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_05; | |
4618 | end | |
4619 | else if (~drif_init) begin | |
4620 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_01; | |
4621 | end | |
4622 | end | |
4623 | 5'd1: begin | |
4624 | // IN NORMAL operation but wait for refresh requests | |
4625 | if (drif_ref_go | drif_hw_selfrsh) | |
4626 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_02; | |
4627 | drif_bank_idle_cnt_next[4:0] = 5'h0; | |
4628 | end | |
4629 | 5'd2: begin | |
4630 | // compare to 2 less than reg because of 2 cycle delay for issuing command | |
4631 | if ((drif_bank_idle_cnt[4:0] >= (dal_reg[4:0] - 5'h2)) & | |
4632 | (drif_bank_idle_cnt[4:0] >= (ral_reg[4:0] - 5'h2)) & | |
4633 | (drif_bank_idle_cnt[4:0] >= (rc_reg[4:0] - 5'h2))) | |
4634 | begin | |
4635 | if (~drif_rd_picked & ~drif_wr_picked & ~drif_err_wr_picked & | |
4636 | ~drif_err_rd_picked & ~drif_scrub_picked & ~fbdic_error_mode) | |
4637 | begin | |
4638 | drif_bank_idle_cnt_next = 5'h0; | |
4639 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_03; | |
4640 | end | |
4641 | end | |
4642 | else begin | |
4643 | drif_bank_idle_cnt_next[4:0] = drif_bank_idle_cnt[4:0] + 5'h1; | |
4644 | end | |
4645 | end | |
4646 | 5'd3: begin | |
4647 | // SEND the AUTO refresh command | |
4648 | if (fbdic_sync_frame_req_l & (~drif_cmd_a_val & ~drif_cmd_a_val_d1 | | |
4649 | drif_dram_dimm_a[2:0] != drif_refresh_rank[2:0]) & ~drif_wdq_sel_d1) | |
4650 | begin | |
4651 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_04; | |
4652 | end | |
4653 | end | |
4654 | 5'd4: begin | |
4655 | // WAIT for tRFC and back to normal operation | |
4656 | if (rfc_cnt_is_zero) begin | |
4657 | if (drif_refresh_rank[4:0] == {1'b0,drif_last_rank[3:0]}) begin | |
4658 | // SW control to write mode regs | |
4659 | if (drif_hw_selfrsh) begin | |
4660 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_05; | |
4661 | set_drif_enter_self_refresh = 1'b1; | |
4662 | drif_refresh_rank_in[4:0] = 5'h0; | |
4663 | end | |
4664 | else if (drif_init) begin | |
4665 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_00; | |
4666 | end | |
4667 | else begin | |
4668 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_01; | |
4669 | end | |
4670 | drif_refresh_rank_in[4:0] = 5'h0; | |
4671 | end | |
4672 | else begin | |
4673 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_02; | |
4674 | drif_refresh_rank_in[4] = 1'b0; | |
4675 | drif_refresh_rank_in[3] = drif_refresh_rank[3] ^ drif_stacked_dimm; | |
4676 | drif_refresh_rank_in[2:0] = drif_refresh_rank[2:0] + | |
4677 | {2'h0, drif_refresh_rank[3] & drif_stacked_dimm | ~drif_stacked_dimm}; | |
4678 | end | |
4679 | end | |
4680 | end | |
4681 | 5'd5: begin | |
4682 | // Issue self refresh enter commands | |
4683 | if (drif_enter_self_refresh & fbdic_sync_frame_req_l) begin | |
4684 | drif_refresh_rank_in[4] = 1'b0; | |
4685 | drif_refresh_rank_in[3] = drif_refresh_rank[3] ^ drif_stacked_dimm; | |
4686 | drif_refresh_rank_in[2:0] = drif_refresh_rank[2:0] + | |
4687 | {2'h0, drif_refresh_rank[3] & drif_stacked_dimm | ~drif_stacked_dimm}; | |
4688 | end | |
4689 | ||
4690 | // WAIT till self refresh bit is unset | |
4691 | if (~drif_hw_selfrsh) begin | |
4692 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_06; | |
4693 | set_drif_exit_self_refresh = 1'b1; | |
4694 | drif_refresh_rank_in[4:0] = 5'h0; | |
4695 | end | |
4696 | end | |
4697 | 5'd6: begin | |
4698 | // Issue self refresh exit commands | |
4699 | if (drif_exit_self_refresh) begin | |
4700 | if (fbdic_sync_frame_req_l) begin | |
4701 | drif_refresh_rank_in[4] = 1'b0; | |
4702 | drif_refresh_rank_in[3] = drif_refresh_rank[3] ^ drif_stacked_dimm; | |
4703 | drif_refresh_rank_in[2:0] = drif_refresh_rank[2:0] + | |
4704 | {2'h0, drif_refresh_rank[3] & drif_stacked_dimm | ~drif_stacked_dimm}; | |
4705 | end | |
4706 | end | |
4707 | else begin | |
4708 | drif_cyc_cnt_next[7:0] = drif_cyc_cnt[7:0] + 8'h1; | |
4709 | end | |
4710 | ||
4711 | // WAIT for 200 cycles after coming out of self refresh for | |
4712 | // back to normal operation | |
4713 | if (drif_cyc_cnt[7:0] == 8'hC8) begin | |
4714 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_01; | |
4715 | drif_refresh_rank_in[4:0] = 5'h0; | |
4716 | end | |
4717 | end | |
4718 | default: begin | |
4719 | drif_mcu_state_next[`DRIF_MCU_STATE_MAX:0] = `DRIF_MCU_STATE_00; | |
4720 | end | |
4721 | endcase | |
4722 | end | |
4723 | ||
4724 | mcu_drif_ctl_msff_ctl_macro__width_8 ff_cyc_cnt ( | |
4725 | .scan_in(ff_cyc_cnt_scanin), | |
4726 | .scan_out(ff_cyc_cnt_scanout), | |
4727 | .din(drif_cyc_cnt_next[7:0]), | |
4728 | .dout(drif_cyc_cnt[7:0]), | |
4729 | .l1clk(l1clk), | |
4730 | .siclk(siclk), | |
4731 | .soclk(soclk)); | |
4732 | ||
4733 | // wait for tMRD count | |
4734 | assign mrd_cnt_next[1:0] = (drif_mcu_state[3] | drif_mcu_state[4]) & mrd_cnt_is_zero ? | |
4735 | mrd_reg[1:0] : ((mrd_cnt[1:0] == 2'h0) ? 2'h0 : mrd_cnt[1:0] - 2'h1); | |
4736 | ||
4737 | mcu_drif_ctl_msff_ctl_macro__width_2 ff_mrd_cnt ( | |
4738 | .scan_in(ff_mrd_cnt_scanin), | |
4739 | .scan_out(ff_mrd_cnt_scanout), | |
4740 | .din(mrd_cnt_next[1:0]), | |
4741 | .dout(mrd_cnt[1:0]), | |
4742 | .l1clk(l1clk), | |
4743 | .siclk(siclk), | |
4744 | .soclk(soclk)); | |
4745 | ||
4746 | assign mrd_cnt_is_zero = (mrd_cnt[1:0] == 2'h0); | |
4747 | ||
4748 | // wait for tRP count | |
4749 | assign rp_cnt_next[3:0] = (drif_mcu_state[5] & mrd_cnt_is_zero | drif_mcu_state[2]) ? | |
4750 | (drif_eight_bank_mode_mod ? ((rp_reg[3:0] != 4'hf) ? rp_reg[3:0] + 4'h1 : rp_reg[3:0]) : | |
4751 | rp_reg[3:0]) : ((rp_cnt[3:0] == 4'h0) ? 4'h0 : rp_cnt[3:0] - 4'h1); | |
4752 | ||
4753 | mcu_drif_ctl_msff_ctl_macro__width_4 ff_rp_cnt ( | |
4754 | .scan_in(ff_rp_cnt_scanin), | |
4755 | .scan_out(ff_rp_cnt_scanout), | |
4756 | .din(rp_cnt_next[3:0]), | |
4757 | .dout(rp_cnt[3:0]), | |
4758 | .l1clk(l1clk), | |
4759 | .siclk(siclk), | |
4760 | .soclk(soclk)); | |
4761 | ||
4762 | assign rp_cnt_is_zero = (rp_cnt[3:0] == 4'h0); | |
4763 | ||
4764 | // Count to clear all the requests to all banks so that refresh command could be issued. | |
4765 | mcu_drif_ctl_msff_ctl_macro__width_5 ff_bank_idle_cnt ( | |
4766 | .scan_in(ff_bank_idle_cnt_scanin), | |
4767 | .scan_out(ff_bank_idle_cnt_scanout), | |
4768 | .din(drif_bank_idle_cnt_next[4:0]), | |
4769 | .dout(drif_bank_idle_cnt[4:0]), | |
4770 | .l1clk(l1clk), | |
4771 | .siclk(siclk), | |
4772 | .soclk(soclk)); | |
4773 | ||
4774 | // number of the current rank being refreshed | |
4775 | mcu_drif_ctl_msff_ctl_macro__width_5 ff_refresh_rank ( | |
4776 | .scan_in(ff_refresh_rank_scanin), | |
4777 | .scan_out(ff_refresh_rank_scanout), | |
4778 | .din(drif_refresh_rank_in[4:0]), | |
4779 | .dout(drif_refresh_rank[4:0]), | |
4780 | .l1clk(l1clk), | |
4781 | .siclk(siclk), | |
4782 | .soclk(soclk)); | |
4783 | ||
4784 | // flag to issue self refresh enter commands to FBDIMMs | |
4785 | ||
4786 | assign drif_enter_self_refresh_in = | |
4787 | set_drif_enter_self_refresh ? 1'b1 : | |
4788 | (drif_refresh_rank[4:0] == {1'b0,drif_last_rank[3:0]}) & fbdic_sync_frame_req_l ? 1'b0 : drif_enter_self_refresh; | |
4789 | mcu_drif_ctl_msff_ctl_macro ff_enter_self_refresh ( | |
4790 | .scan_in(ff_enter_self_refresh_scanin), | |
4791 | .scan_out(ff_enter_self_refresh_scanout), | |
4792 | .din(drif_enter_self_refresh_in), | |
4793 | .dout(drif_enter_self_refresh), | |
4794 | .l1clk(l1clk), | |
4795 | .siclk(siclk), | |
4796 | .soclk(soclk)); | |
4797 | ||
4798 | // flag to issue self refresh exit commands to FBDIMMs | |
4799 | ||
4800 | assign drif_exit_self_refresh_in = | |
4801 | set_drif_exit_self_refresh ? 1'b1 : | |
4802 | (drif_refresh_rank[4:0] == {1'b0,drif_last_rank[3:0]}) & fbdic_sync_frame_req_l ? 1'b0 : drif_exit_self_refresh; | |
4803 | mcu_drif_ctl_msff_ctl_macro ff_exit_self_refresh ( | |
4804 | .scan_in(ff_exit_self_refresh_scanin), | |
4805 | .scan_out(ff_exit_self_refresh_scanout), | |
4806 | .din(drif_exit_self_refresh_in), | |
4807 | .dout(drif_exit_self_refresh), | |
4808 | .l1clk(l1clk), | |
4809 | .siclk(siclk), | |
4810 | .soclk(soclk)); | |
4811 | ||
4812 | // Poison bit for ECC bits in writedp | |
4813 | assign drif_l2poison_qw_in = ((wdqrf00_data_mecc | wdqrf01_data_mecc) & drif0_wdq_sel | | |
4814 | (wdqrf10_data_mecc | wdqrf11_data_mecc) & drif1_wdq_sel) & ~drif_err_state[`DRIF_ERR_READ1]; | |
4815 | ||
4816 | mcu_drif_ctl_msff_ctl_macro ff_l2_poison_qw ( | |
4817 | .scan_in(ff_l2_poison_qw_scanin), | |
4818 | .scan_out(ff_l2_poison_qw_scanout), | |
4819 | .din(drif_l2poison_qw_in), | |
4820 | .dout(drif_l2poison_qw), | |
4821 | .l1clk(l1clk), | |
4822 | .siclk(siclk), | |
4823 | .soclk(soclk)); | |
4824 | ||
4825 | ////////////////////////////////////////////////////////////////// | |
4826 | // SOFTWARE PROGRAMMABLE REGISTERS | |
4827 | ////////////////////////////////////////////////////////////////// | |
4828 | ////////////////////////////////////////////////////////////////// | |
4829 | // MODE REGISTER - reset to 7'h32 | |
4830 | ////////////////////////////////////////////////////////////////// | |
4831 | ||
4832 | assign sch_mode_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h10); | |
4833 | assign mode_reg_in[6:4] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h10) ? | |
4834 | drif_ucb_data[2:0] : mode_reg[6:4]; | |
4835 | ||
4836 | assign inv_mode_reg_in[5:4] = ~mode_reg_in[5:4]; | |
4837 | assign mode_reg[5:0] = {~inv_mode_reg[5:4], 4'h2}; | |
4838 | ||
4839 | mcu_drif_ctl_msff_ctl_macro__en_1__width_3 pff_mode_reg ( // FS:wmr_protect | |
4840 | .scan_in(pff_mode_reg_wmr_scanin), | |
4841 | .scan_out(pff_mode_reg_wmr_scanout), | |
4842 | .siclk(aclk_wmr), | |
4843 | .din({mode_reg_in[6],inv_mode_reg_in[5:4]}), | |
4844 | .en(sch_mode_reg_en), | |
4845 | .dout({mode_reg[6],inv_mode_reg[5:4]}), | |
4846 | .l1clk(l1clk), | |
4847 | .soclk(soclk)); | |
4848 | ||
4849 | ////////////////////////////////////////////////////////////////// | |
4850 | // EXTENDED MODE REGISTER 1 - reset to 15'h0018 | |
4851 | ////////////////////////////////////////////////////////////////// | |
4852 | ||
4853 | assign sch_ext_mode_reg1_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h118); | |
4854 | assign ext_mode_reg1_in[14:0] = drif_ucb_data[14:0]; | |
4855 | ||
4856 | assign inv_ext_mode_reg1_in[4:3] = ~ext_mode_reg1_in[4:3]; | |
4857 | assign ext_mode_reg1[4:3] = ~inv_ext_mode_reg1[4:3]; | |
4858 | ||
4859 | mcu_drif_ctl_msff_ctl_macro__en_1__width_15 pff_ext_mode_reg1 ( // FS:wmr_protect | |
4860 | .scan_in(pff_ext_mode_reg1_wmr_scanin), | |
4861 | .scan_out(pff_ext_mode_reg1_wmr_scanout), | |
4862 | .siclk(aclk_wmr), | |
4863 | .din({ext_mode_reg1_in[14:5],inv_ext_mode_reg1_in[4:3],ext_mode_reg1_in[2:0]}), | |
4864 | .dout({ext_mode_reg1[14:5],inv_ext_mode_reg1[4:3],ext_mode_reg1[2:0]}), | |
4865 | .en(sch_ext_mode_reg1_en), | |
4866 | .l1clk(l1clk), | |
4867 | .soclk(soclk)); | |
4868 | ||
4869 | ////////////////////////////////////////////////////////////////// | |
4870 | // EXTENDED MODE REGISTER 2 - reset to 15'h0000 | |
4871 | ////////////////////////////////////////////////////////////////// | |
4872 | ||
4873 | assign sch_ext_mode_reg2_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h110); | |
4874 | assign ext_mode_reg2_in[14:0] = drif_ucb_data[14:0]; | |
4875 | ||
4876 | mcu_drif_ctl_msff_ctl_macro__en_1__width_15 pff_ext_mode_reg2 ( // FS:wmr_protect | |
4877 | .scan_in(pff_ext_mode_reg2_wmr_scanin), | |
4878 | .scan_out(pff_ext_mode_reg2_wmr_scanout), | |
4879 | .siclk(aclk_wmr), | |
4880 | .din(ext_mode_reg2_in[14:0]), | |
4881 | .dout(ext_mode_reg2[14:0]), | |
4882 | .en(sch_ext_mode_reg2_en), | |
4883 | .l1clk(l1clk), | |
4884 | .soclk(soclk)); | |
4885 | ||
4886 | ////////////////////////////////////////////////////////////////// | |
4887 | // EXTENDED MODE REGISTER 3 - reset to 15'h0000 | |
4888 | ////////////////////////////////////////////////////////////////// | |
4889 | ||
4890 | assign sch_ext_mode_reg3_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h120); | |
4891 | assign ext_mode_reg3_in[14:0] = drif_ucb_data[14:0]; | |
4892 | ||
4893 | mcu_drif_ctl_msff_ctl_macro__en_1__width_15 pff_ext_mode_reg3 ( // FS:wmr_protect | |
4894 | .scan_in(pff_ext_mode_reg3_wmr_scanin), | |
4895 | .scan_out(pff_ext_mode_reg3_wmr_scanout), | |
4896 | .siclk(aclk_wmr), | |
4897 | .din(ext_mode_reg3_in[14:0]), | |
4898 | .dout(ext_mode_reg3[14:0]), | |
4899 | .en(sch_ext_mode_reg3_en), | |
4900 | .l1clk(l1clk), | |
4901 | .soclk(soclk)); | |
4902 | ||
4903 | ////////////////////////////////////////////////////////////////// | |
4904 | // stacked DIMMs used - reset to 0 | |
4905 | ////////////////////////////////////////////////////////////////// | |
4906 | ||
4907 | assign drif_stacked_dimm_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h108); | |
4908 | assign drif_stacked_dimm_in = drif_ucb_data[0]; | |
4909 | ||
4910 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_stacked_dimm ( // FS:wmr_protect | |
4911 | .scan_in(pff_stacked_dimm_wmr_scanin), | |
4912 | .scan_out(pff_stacked_dimm_wmr_scanout), | |
4913 | .siclk(aclk_wmr), | |
4914 | .din(drif_stacked_dimm_in), | |
4915 | .en(drif_stacked_dimm_en), | |
4916 | .dout(drif_stacked_dimm), | |
4917 | .l1clk(l1clk), | |
4918 | .soclk(soclk)); | |
4919 | ||
4920 | ////////////////////////////////////////////////////////////////// | |
4921 | // cas address bits - reset to 4'hb | |
4922 | ////////////////////////////////////////////////////////////////// | |
4923 | assign drif_cas_addr_bits_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h0); | |
4924 | assign drif_cas_addr_bits_in[3:0] = drif_ucb_data[3:0]; | |
4925 | ||
4926 | assign inv_drif_cas_addr_bits_in[2] = ~drif_cas_addr_bits_in[3]; | |
4927 | assign inv_drif_cas_addr_bits_in[1:0] = ~drif_cas_addr_bits_in[1:0]; | |
4928 | assign drif_cas_addr_bits[3] = ~inv_drif_cas_addr_bits[2]; | |
4929 | assign drif_cas_addr_bits[1:0] = ~inv_drif_cas_addr_bits[1:0]; | |
4930 | ||
4931 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_cas_addr_bits ( // FS:wmr_protect | |
4932 | .scan_in(pff_cas_addr_bits_wmr_scanin), | |
4933 | .scan_out(pff_cas_addr_bits_wmr_scanout), | |
4934 | .siclk(aclk_wmr), | |
4935 | .din({drif_cas_addr_bits_in[2],inv_drif_cas_addr_bits_in[2:0]}), | |
4936 | .en(drif_cas_addr_bits_en), | |
4937 | .dout({drif_cas_addr_bits[2],inv_drif_cas_addr_bits[2:0]}), | |
4938 | .l1clk(l1clk), | |
4939 | .soclk(soclk)); | |
4940 | ||
4941 | ////////////////////////////////////////////////////////////////// | |
4942 | // ras address bits - reset to 4'hf | |
4943 | ////////////////////////////////////////////////////////////////// | |
4944 | assign drif_ras_addr_bits_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h8); | |
4945 | assign drif_ras_addr_bits_in[3:0] = drif_ucb_data[3:0]; | |
4946 | ||
4947 | assign inv_drif_ras_addr_bits_in[3:0] = ~drif_ras_addr_bits_in[3:0]; | |
4948 | assign drif_ras_addr_bits[3:0] = ~inv_drif_ras_addr_bits[3:0]; | |
4949 | ||
4950 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_ras_addr_bits ( // FS:wmr_protect | |
4951 | .scan_in(pff_ras_addr_bits_wmr_scanin), | |
4952 | .scan_out(pff_ras_addr_bits_wmr_scanout), | |
4953 | .siclk(aclk_wmr), | |
4954 | .din(inv_drif_ras_addr_bits_in[3:0]), | |
4955 | .en(drif_ras_addr_bits_en), | |
4956 | .dout(inv_drif_ras_addr_bits[3:0]), | |
4957 | .l1clk(l1clk), | |
4958 | .soclk(soclk)); | |
4959 | ||
4960 | assign drif_row_addr_bits[1:0] = (drif_ras_addr_bits[3:0] == 4'he) ? 2'h2 : (drif_ras_addr_bits[3:0] == 4'hd) ? 2'h1 : 2'h3; | |
4961 | ||
4962 | // memory type for address mapping | |
4963 | ||
4964 | assign drif_mem_type_in[1:0] = drif_ras_addr_bits[3:0] == 4'd14 & ~drif_eight_bank_mode_nomod ? 2'h1 : | |
4965 | drif_ras_addr_bits[3:0] == 4'd14 & drif_eight_bank_mode_nomod ? 2'h2 : | |
4966 | drif_ras_addr_bits[3:0] == 4'd15 ? 2'h3 : 2'h0; | |
4967 | ||
4968 | mcu_drif_ctl_msff_ctl_macro__width_2 ff_mem_type ( | |
4969 | .scan_in(ff_mem_type_scanin), | |
4970 | .scan_out(ff_mem_type_scanout), | |
4971 | .din(drif_mem_type_in[1:0]), | |
4972 | .dout(drif_mem_type[1:0]), | |
4973 | .l1clk(l1clk), | |
4974 | .siclk(siclk), | |
4975 | .soclk(soclk)); | |
4976 | ||
4977 | ////////////////////////////////////////////////////////////////// | |
4978 | // scrub frequency - reset to 12'hfff | |
4979 | ////////////////////////////////////////////////////////////////// | |
4980 | assign drif_freq_scrub_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h18); | |
4981 | assign drif_freq_scrub_in[11:0] = drif_ucb_data[11:0]; | |
4982 | ||
4983 | assign inv_drif_freq_scrub_in[11:0] = ~drif_freq_scrub_in[11:0]; | |
4984 | assign drif_freq_scrub[11:0] = ~inv_drif_freq_scrub[11:0]; | |
4985 | ||
4986 | mcu_drif_ctl_msff_ctl_macro__en_1__width_12 pff_freq_scrub ( // FS:wmr_protect | |
4987 | .scan_in(pff_freq_scrub_wmr_scanin), | |
4988 | .scan_out(pff_freq_scrub_wmr_scanout), | |
4989 | .siclk(aclk_wmr), | |
4990 | .din(inv_drif_freq_scrub_in[11:0]), | |
4991 | .en(drif_freq_scrub_en), | |
4992 | .dout(inv_drif_freq_scrub[11:0]), | |
4993 | .l1clk(l1clk), | |
4994 | .soclk(soclk)); | |
4995 | ||
4996 | ////////////////////////////////////////////////////////////////// | |
4997 | // DIMMS per channel - reset to 4'h1 | |
4998 | ////////////////////////////////////////////////////////////////// | |
4999 | assign drif_dimms_present_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h218); | |
5000 | assign drif_dimms_present_in[3:0] = drif_ucb_data[3:0]; | |
5001 | ||
5002 | assign inv_drif_dimms_present_in[0] = ~drif_dimms_present_in[0]; | |
5003 | assign drif_dimms_present[0] = ~inv_drif_dimms_present[0]; | |
5004 | ||
5005 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_dimms_present ( // FS:wmr_protect | |
5006 | .scan_in(pff_dimms_present_wmr_scanin), | |
5007 | .scan_out(pff_dimms_present_wmr_scanout), | |
5008 | .siclk(aclk_wmr), | |
5009 | .din({drif_dimms_present_in[3:1],inv_drif_dimms_present_in[0]}), | |
5010 | .en(drif_dimms_present_en), | |
5011 | .dout({drif_dimms_present[3:1],inv_drif_dimms_present[0]}), | |
5012 | .l1clk(l1clk), | |
5013 | .soclk(soclk)); | |
5014 | ||
5015 | assign drif_num_dimms[2:0] = drif_dimms_present[2:0]; | |
5016 | ||
5017 | // branch disabled | |
5018 | assign drif_branch_disabled_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h138); | |
5019 | assign drif_branch_disabled_in = drif_ucb_data[0]; | |
5020 | ||
5021 | mcu_drif_ctl_msff_ctl_macro__en_1 pff_branch_disabled ( // FS:wmr_protect | |
5022 | .scan_in(pff_branch_disabled_wmr_scanin), | |
5023 | .scan_out(pff_branch_disabled_wmr_scanout), | |
5024 | .siclk(aclk_wmr), | |
5025 | .din(drif_branch_disabled_in), | |
5026 | .dout(drif_branch_disabled), | |
5027 | .en(drif_branch_disabled_en), | |
5028 | .l1clk(l1clk), | |
5029 | .soclk(soclk)); | |
5030 | ||
5031 | ////////////////////////////////////////////////////////////////// | |
5032 | // START INIT PROCESS AND SET MODE REGS - software should set to 0 when init is done | |
5033 | ////////////////////////////////////////////////////////////////// | |
5034 | assign drif_init_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h1a0); | |
5035 | assign drif_init_in = drif_ucb_data[0]; | |
5036 | ||
5037 | assign inv_drif_init_in = ~drif_init_in; | |
5038 | assign drif_init = ~inv_drif_init; | |
5039 | ||
5040 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_init ( | |
5041 | .scan_in(ff_init_scanin), | |
5042 | .scan_out(ff_init_scanout), | |
5043 | .din(inv_drif_init_in), | |
5044 | .dout(inv_drif_init), | |
5045 | .en(drif_init_en), | |
5046 | .l1clk(l1clk), | |
5047 | .siclk(siclk), | |
5048 | .soclk(soclk)); | |
5049 | ||
5050 | ////////////////////////////////////////////////////////////////// | |
5051 | // LAST RANK PRESENT - derived from dimms_present and stacked_dimm | |
5052 | ////////////////////////////////////////////////////////////////// | |
5053 | assign drif_last_rank[2:0] = drif_dimms_present[2:0] - 3'h1; | |
5054 | assign drif_last_rank[3] = drif_stacked_dimm; | |
5055 | ||
5056 | ////////////////////////////////////////////////////////////////// | |
5057 | // SELECT LOW ORDER BITS TO access ranks | |
5058 | ////////////////////////////////////////////////////////////////// | |
5059 | assign drif_addr_bank_low_sel_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h140); | |
5060 | assign drif_addr_bank_low_sel_in = drif_ucb_data[0]; | |
5061 | ||
5062 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_bank_low_sel ( // FS:wmr_protect | |
5063 | .scan_in(pff_bank_low_sel_wmr_scanin), | |
5064 | .scan_out(pff_bank_low_sel_wmr_scanout), | |
5065 | .siclk(aclk_wmr), | |
5066 | .din(drif_addr_bank_low_sel_in), | |
5067 | .en(drif_addr_bank_low_sel_en), | |
5068 | .dout(drif_addr_bank_low_sel), | |
5069 | .l1clk(l1clk), | |
5070 | .soclk(soclk)); | |
5071 | ||
5072 | ////////////////////////////////////////////////////////////////// | |
5073 | // EIGHT BANK MODE REG | |
5074 | ////////////////////////////////////////////////////////////////// | |
5075 | assign drif_eight_bank_mode_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h128); | |
5076 | assign drif_eight_bank_mode_in = drif_ucb_data[0]; | |
5077 | ||
5078 | assign inv_drif_eight_bank_mode_in = ~drif_eight_bank_mode_in; | |
5079 | assign drif_eight_bank_mode = ~inv_drif_eight_bank_mode; | |
5080 | assign drif_eight_bank_mode_nomod = drif_eight_bank_mode; | |
5081 | ||
5082 | assign drif_eight_bank_mode_mod = drif_eight_bank_mode | drif_cas_addr_bits[3:0] == 4'ha; | |
5083 | ||
5084 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_eight_bank_present ( // FS:wmr_protect | |
5085 | .scan_in(pff_eight_bank_present_wmr_scanin), | |
5086 | .scan_out(pff_eight_bank_present_wmr_scanout), | |
5087 | .siclk(aclk_wmr), | |
5088 | .din(inv_drif_eight_bank_mode_in), | |
5089 | .en(drif_eight_bank_mode_en), | |
5090 | .dout(inv_drif_eight_bank_mode), | |
5091 | .l1clk(l1clk), | |
5092 | .soclk(soclk)); | |
5093 | ||
5094 | ////////////////////////////////////////////////////////////////// | |
5095 | // SINGLE CHANNEL MODE | |
5096 | ////////////////////////////////////////////////////////////////// | |
5097 | assign drif_single_channel_mode_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h148); | |
5098 | assign drif_single_channel_mode_in = drif_ucb_data[0]; | |
5099 | ||
5100 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_single_channel_mode ( // FS:wmr_protect | |
5101 | .scan_in(pff_single_channel_mode_wmr_scanin), | |
5102 | .scan_out(pff_single_channel_mode_wmr_scanout), | |
5103 | .siclk(aclk_wmr), | |
5104 | .din(drif_single_channel_mode_in), | |
5105 | .dout(drif_single_channel_mode), | |
5106 | .en(drif_single_channel_mode_en), | |
5107 | .l1clk(l1clk), | |
5108 | .soclk(soclk)); | |
5109 | ||
5110 | // writes to the single dimm mode register generate MRS commands to the DIMMs to set the | |
5111 | // appropriate burst length. This shows that the MRS register write is pending. | |
5112 | assign drif_single_channel_mode_pend_clr = drif_mcu_state[7] & mrd_cnt_is_zero; | |
5113 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_single_channel_mode_pend ( | |
5114 | .scan_in(ff_single_channel_mode_pend_scanin), | |
5115 | .scan_out(ff_single_channel_mode_pend_scanout), | |
5116 | .din(1'b1), | |
5117 | .dout(drif_single_channel_mode_pend), | |
5118 | .en(drif_single_channel_mode_en), | |
5119 | .clr(drif_single_channel_mode_pend_clr), | |
5120 | .l1clk(l1clk), | |
5121 | .siclk(siclk), | |
5122 | .soclk(soclk)); | |
5123 | ||
5124 | ////////////////////////////////////////////////////////////////// | |
5125 | // FAIL OVER MODE BIT | |
5126 | ////////////////////////////////////////////////////////////////// | |
5127 | assign drif_fail_over_mode_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h220); | |
5128 | assign drif_fail_over_mode_in = drif_ucb_data[0]; | |
5129 | ||
5130 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_fail_over_mode ( // FS:wmr_protect | |
5131 | .scan_in(pff_fail_over_mode_wmr_scanin), | |
5132 | .scan_out(pff_fail_over_mode_wmr_scanout), | |
5133 | .siclk(aclk_wmr), | |
5134 | .din(drif_fail_over_mode_in), | |
5135 | .dout(drif_fail_over_mode), | |
5136 | .en(drif_fail_over_mode_en), | |
5137 | .l1clk(l1clk), | |
5138 | .soclk(soclk)); | |
5139 | ||
5140 | ////////////////////////////////////////////////////////////////// | |
5141 | // CKE ENABLE BIT - enables CKE to DIMMs | |
5142 | ////////////////////////////////////////////////////////////////// | |
5143 | assign drif_cke_en = (drif_mcu_state[6] & ~drif_hw_selfrsh) | drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h1a0); | |
5144 | assign drif_cke_in = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h1a0) ? drif_ucb_data[1] : 1'b1; | |
5145 | ||
5146 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ff_cke_enable ( | |
5147 | .scan_in(ff_cke_enable_scanin), | |
5148 | .scan_out(ff_cke_enable_scanout), | |
5149 | .din(drif_cke_in), | |
5150 | .dout(drif_cke_reg), | |
5151 | .en(drif_cke_en), | |
5152 | .l1clk(l1clk), | |
5153 | .siclk(siclk), | |
5154 | .soclk(soclk)); | |
5155 | ||
5156 | //////////////////////////////////////////////// | |
5157 | // MASK REG FOR MUXING DEAD CHIP ON DIMM | |
5158 | // The interpretation of the parity is as following ecc[15:0] = {p0,p1,p2,p3} where p3 is not used | |
5159 | // failover mode. | |
5160 | // The error location is as = {err_in_p3, err_in_p2, ... err_in_d2, err_in_d1, err_in_d0} | |
5161 | // If the error location bit is 1, and to create mask in failover mode set all the bits left of 1 to 1 | |
5162 | // (including the bit 1 set in err location) upto bit location 34. | |
5163 | //////////////////////////////////////////////// | |
5164 | ||
5165 | assign drif_fail_over_mask_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h228); | |
5166 | assign drif_fail_over_mask_in[34:0] = drif_ucb_data[34:0]; | |
5167 | ||
5168 | mcu_drif_ctl_msff_ctl_macro__en_1__width_35 pff_fail_over_mask ( // FS:wmr_protect | |
5169 | .scan_in(pff_fail_over_mask_wmr_scanin), | |
5170 | .scan_out(pff_fail_over_mask_wmr_scanout), | |
5171 | .siclk(aclk_wmr), | |
5172 | .din(drif_fail_over_mask_in[34:0]), | |
5173 | .dout(drif_fail_over_mask[34:0]), | |
5174 | .en(drif_fail_over_mask_en), | |
5175 | .l1clk(l1clk), | |
5176 | .soclk(soclk)); | |
5177 | ||
5178 | assign drif_fail_over_mask_l[34:0] = ~drif_fail_over_mask[34:0]; | |
5179 | ||
5180 | ////////////////////////////////////////////////////////////////// | |
5181 | // Ras to Ras Delay to different bank (RRD) REGISTER - reset to 4'h2 | |
5182 | ////////////////////////////////////////////////////////////////// | |
5183 | ||
5184 | assign sch_rrd_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h80); | |
5185 | assign rrd_reg_in[3:0] = drif_ucb_data[3:0]; | |
5186 | ||
5187 | assign inv_rrd_reg_in[1] = ~rrd_reg_in[1]; | |
5188 | assign rrd_reg[1] = ~inv_rrd_reg[1]; | |
5189 | ||
5190 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_rrd_reg ( // FS:wmr_protect | |
5191 | .scan_in(pff_rrd_reg_wmr_scanin), | |
5192 | .scan_out(pff_rrd_reg_wmr_scanout), | |
5193 | .siclk(aclk_wmr), | |
5194 | .din({rrd_reg_in[3:2],inv_rrd_reg_in[1],rrd_reg_in[0]}), | |
5195 | .en(sch_rrd_reg_en), | |
5196 | .dout({rrd_reg[3:2],inv_rrd_reg[1],rrd_reg[0]}), | |
5197 | .l1clk(l1clk), | |
5198 | .soclk(soclk)); | |
5199 | ||
5200 | ////////////////////////////////////////////////////////////////// | |
5201 | // Ras to Cas Delay (RCD) REGISTER - reset to 4'h3 | |
5202 | ////////////////////////////////////////////////////////////////// | |
5203 | ||
5204 | assign sch_rcd_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h90); | |
5205 | assign rcd_reg_in[3:0] = drif_ucb_data[3:0]; | |
5206 | ||
5207 | assign inv_rcd_reg_in[1:0] = ~rcd_reg_in[1:0]; | |
5208 | assign rcd_reg[1:0] = ~inv_rcd_reg[1:0]; | |
5209 | ||
5210 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_rcd_reg ( // FS:wmr_protect | |
5211 | .scan_in(pff_rcd_reg_wmr_scanin), | |
5212 | .scan_out(pff_rcd_reg_wmr_scanout), | |
5213 | .siclk(aclk_wmr), | |
5214 | .din({rcd_reg_in[3:2],inv_rcd_reg_in[1:0]}), | |
5215 | .en(sch_rcd_reg_en), | |
5216 | .dout({rcd_reg[3:2],inv_rcd_reg[1:0]}), | |
5217 | .l1clk(l1clk), | |
5218 | .soclk(soclk)); | |
5219 | ||
5220 | ////////////////////////////////////////////////////////////////// | |
5221 | // Internal write to read command delay (IWTR) REGISTER - reset to 2'h2 | |
5222 | ////////////////////////////////////////////////////////////////// | |
5223 | ||
5224 | // tWTR delay | |
5225 | assign sch_iwtr_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'he0); | |
5226 | assign iwtr_reg_in[1:0] = drif_ucb_data[1:0]; | |
5227 | ||
5228 | assign inv_iwtr_reg_in[1] = ~iwtr_reg_in[1]; | |
5229 | assign iwtr_reg[1] = ~inv_iwtr_reg[1]; | |
5230 | ||
5231 | mcu_drif_ctl_msff_ctl_macro__en_1__width_2 pff_iwtr_reg ( // FS:wmr_protect | |
5232 | .scan_in(pff_iwtr_reg_wmr_scanin), | |
5233 | .scan_out(pff_iwtr_reg_wmr_scanout), | |
5234 | .siclk(aclk_wmr), | |
5235 | .din({inv_iwtr_reg_in[1],iwtr_reg_in[0]}), | |
5236 | .en(sch_iwtr_reg_en), | |
5237 | .dout({inv_iwtr_reg[1],iwtr_reg[0]}), | |
5238 | .l1clk(l1clk), | |
5239 | .soclk(soclk)); | |
5240 | ||
5241 | ////////////////////////////////////////////////////////////////// | |
5242 | // Write to Read (CAS) Delay to any bank (WTR) REGISTER | |
5243 | ////////////////////////////////////////////////////////////////// | |
5244 | ||
5245 | // This is because CL - 1 + BL/2 + iwtr due to the WTR delay | |
5246 | assign sch_wtr_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h98); | |
5247 | assign wtr_reg_in[3:0] = drif_ucb_data[3:0]; | |
5248 | ||
5249 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_wtr_reg ( // FS:wmr_protect | |
5250 | .scan_in(pff_wtr_reg_wmr_scanin), | |
5251 | .scan_out(pff_wtr_reg_wmr_scanout), | |
5252 | .siclk(aclk_wmr), | |
5253 | .din(wtr_reg_in[3:0]), | |
5254 | .en(sch_wtr_reg_en), | |
5255 | .dout(wtr_dly_reg[3:0]), | |
5256 | .l1clk(l1clk), | |
5257 | .soclk(soclk)); | |
5258 | ||
5259 | assign wtr_reg[3:0] = wtr_dly_reg[3:0] + {1'h0, mode_reg[6:4]} + {2'h0, iwtr_reg[1:0]} + | |
5260 | (drif_single_channel_mode ? 4'h3 : 4'h1); | |
5261 | ||
5262 | ////////////////////////////////////////////////////////////////// | |
5263 | // Read to Write (CAS) Delay to any bank (RTW) REGISTER | |
5264 | ////////////////////////////////////////////////////////////////// | |
5265 | ||
5266 | // This is 4 for BL=4 or 6 for BL=8 | |
5267 | assign sch_rtw_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'ha0); | |
5268 | assign rtw_reg_in[3:0] = drif_ucb_data[3:0]; | |
5269 | ||
5270 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_rtw_reg ( // FS:wmr_protect | |
5271 | .scan_in(pff_rtw_reg_wmr_scanin), | |
5272 | .scan_out(pff_rtw_reg_wmr_scanout), | |
5273 | .siclk(aclk_wmr), | |
5274 | .din(rtw_reg_in[3:0]), | |
5275 | .en(sch_rtw_reg_en), | |
5276 | .dout(rtw_dly_reg[3:0]), | |
5277 | .l1clk(l1clk), | |
5278 | .soclk(soclk)); | |
5279 | ||
5280 | assign rtw_reg = rtw_dly_reg + (drif_single_channel_mode ? 4'h6 : 4'h4); | |
5281 | ||
5282 | ////////////////////////////////////////////////////////////////// | |
5283 | // For AUTO_PRECHARGE case, after write, the time tDAL (auto precharge | |
5284 | // write recovery + precharge time) has to be met. tDAL = tRP + tWR. | |
5285 | // We have these registers seperate as following. | |
5286 | ////////////////////////////////////////////////////////////////// | |
5287 | ||
5288 | ////////////////////////////////////////////////////////////////// | |
5289 | // Precharge command period for write (DAL) REGISTER | |
5290 | // Its CAS to RAS time period for same bank on a write with auto precharge. | |
5291 | // Normally tDAL = BL/2 + tRP + tWR + (Write Latency - 1) for data to be written. | |
5292 | // tRP starts from last chunk of data written. | |
5293 | ////////////////////////////////////////////////////////////////// | |
5294 | ||
5295 | assign dal_reg_in[4:0] = (drif_single_channel_mode ? 5'h4 : 5'h2) + {1'b0,rp_reg[3:0]} + {1'b0,wr_reg[3:0]} + | |
5296 | ({2'h0, mode_reg[6:4]} + {2'b0, ext_mode_reg1[5:3]} - 5'h1); | |
5297 | mcu_drif_ctl_msff_ctl_macro__width_5 ff_dal_reg ( | |
5298 | .scan_in(ff_dal_reg_scanin), | |
5299 | .scan_out(ff_dal_reg_scanout), | |
5300 | .din(dal_reg_in[4:0]), | |
5301 | .dout(dal_reg[4:0]), | |
5302 | .l1clk(l1clk), | |
5303 | .siclk(siclk), | |
5304 | .soclk(soclk)); | |
5305 | ||
5306 | ////////////////////////////////////////////////////////////////// | |
5307 | // Precharge command period for read (RAL) Register: => max(tRAS, tRTP, AL + BL/2) + tRP | |
5308 | // Its CAS to RAS time period for same bank on a read with auto precharge. | |
5309 | ////////////////////////////////////////////////////////////////// | |
5310 | assign al_plus_bl_2[4:0] = {2'b0, ext_mode_reg1[5:3]} + (drif_single_channel_mode ? 5'h4 : 5'h2); | |
5311 | ||
5312 | assign cmp0 = al_plus_bl_2[4:0] > {1'b0,ras_reg[3:0]}; | |
5313 | assign cmp1 = al_plus_bl_2[4:0] > {2'b0,rtp_reg[2:0]}; | |
5314 | assign cmp2 = {1'b0,ras_reg[3:0]} > {2'b0,rtp_reg[2:0]}; | |
5315 | ||
5316 | assign max_ral_delay[4:0] = ~cmp1 & ~cmp2 ? {2'b0,rtp_reg[2:0]} : | |
5317 | ~cmp0 & cmp2 ? {1'b0,ras_reg[3:0]} : al_plus_bl_2[4:0]; | |
5318 | ||
5319 | assign ral_reg_in[4:0] = max_ral_delay[4:0] + {1'b0,rp_reg[3:0]}; | |
5320 | ||
5321 | mcu_drif_ctl_msff_ctl_macro__width_5 ff_ral_reg ( | |
5322 | .scan_in(ff_ral_reg_scanin), | |
5323 | .scan_out(ff_ral_reg_scanout), | |
5324 | .din(ral_reg_in[4:0]), | |
5325 | .dout(ral_reg[4:0]), | |
5326 | .l1clk(l1clk), | |
5327 | .siclk(siclk), | |
5328 | .soclk(soclk)); | |
5329 | ||
5330 | ////////////////////////////////////////////////////////////////// | |
5331 | // Internal Read to Precharge command delay (tRTP) REGISTER - reset to 3'h2 | |
5332 | ////////////////////////////////////////////////////////////////// | |
5333 | ||
5334 | assign sch_rtp_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'ha8); | |
5335 | assign rtp_reg_in[2:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'ha8) & (drif_ucb_data[2:0] > 3'h2) ? | |
5336 | drif_ucb_data[2:0] : drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'ha8) ? | |
5337 | 3'h2 : rtp_reg[2:0]; | |
5338 | ||
5339 | assign inv_rtp_reg_in[1] = ~rtp_reg_in[1]; | |
5340 | assign rtp_reg[1] = ~inv_rtp_reg[1]; | |
5341 | ||
5342 | mcu_drif_ctl_msff_ctl_macro__en_1__width_3 pff_rtp_reg ( // FS:wmr_protect | |
5343 | .scan_in(pff_rtp_reg_wmr_scanin), | |
5344 | .scan_out(pff_rtp_reg_wmr_scanout), | |
5345 | .siclk(aclk_wmr), | |
5346 | .din({rtp_reg_in[2],inv_rtp_reg_in[1],rtp_reg_in[0]}), | |
5347 | .en(sch_rtp_reg_en), | |
5348 | .dout({rtp_reg[2],inv_rtp_reg[1],rtp_reg[0]}), | |
5349 | .l1clk(l1clk), | |
5350 | .soclk(soclk)); | |
5351 | ||
5352 | ////////////////////////////////////////////////////////////////// | |
5353 | // Active to Precharge command period (tRAS) REGISTER - reset to 4'h9 | |
5354 | ////////////////////////////////////////////////////////////////// | |
5355 | ||
5356 | assign sch_ras_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hb0); | |
5357 | assign ras_reg_in[3:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hb0) ? | |
5358 | drif_ucb_data[3:0] : ras_reg[3:0]; | |
5359 | ||
5360 | assign inv_ras_reg_in[1] = ~ras_reg_in[3]; | |
5361 | assign inv_ras_reg_in[0] = ~ras_reg_in[0]; | |
5362 | assign ras_reg[3] = ~inv_ras_reg[1]; | |
5363 | assign ras_reg[0] = ~inv_ras_reg[0]; | |
5364 | ||
5365 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_ras_reg ( // FS:wmr_protect | |
5366 | .scan_in(pff_ras_reg_wmr_scanin), | |
5367 | .scan_out(pff_ras_reg_wmr_scanout), | |
5368 | .siclk(aclk_wmr), | |
5369 | .din({ras_reg_in[2:1],inv_ras_reg_in[1:0]}), | |
5370 | .en(sch_ras_reg_en), | |
5371 | .dout({ras_reg[2:1],inv_ras_reg[1:0]}), | |
5372 | .l1clk(l1clk), | |
5373 | .soclk(soclk)); | |
5374 | ||
5375 | ////////////////////////////////////////////////////////////////// | |
5376 | // Precharge command period (RP) REGISTER - reset to 4'h3 | |
5377 | ////////////////////////////////////////////////////////////////// | |
5378 | ||
5379 | assign sch_rp_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hb8); | |
5380 | assign rp_reg_in[3:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hb8) ? | |
5381 | drif_ucb_data[3:0] : rp_reg; | |
5382 | ||
5383 | assign inv_rp_reg_in[1:0] = ~rp_reg_in[1:0]; | |
5384 | assign rp_reg[1:0] = ~inv_rp_reg[1:0]; | |
5385 | ||
5386 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_rp_reg ( // FS:wmr_protect | |
5387 | .scan_in(pff_rp_reg_wmr_scanin), | |
5388 | .scan_out(pff_rp_reg_wmr_scanout), | |
5389 | .siclk(aclk_wmr), | |
5390 | .din({rp_reg_in[3:2],inv_rp_reg_in[1:0]}), | |
5391 | .en(sch_rp_reg_en), | |
5392 | .dout({rp_reg[3:2],inv_rp_reg[1:0]}), | |
5393 | .l1clk(l1clk), | |
5394 | .soclk(soclk)); | |
5395 | ||
5396 | ////////////////////////////////////////////////////////////////// | |
5397 | // Ras to Ras Delay to same bank (RC) REGISTER = tRAS + tRP - reset to 5'hc | |
5398 | ////////////////////////////////////////////////////////////////// | |
5399 | ||
5400 | assign sch_rc_reg_en = sch_rp_reg_en | sch_ras_reg_en | drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h88); | |
5401 | assign rc_reg_in[4:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h88) ? drif_ucb_data[4:0] : | |
5402 | sch_rp_reg_en ? {1'b0,ras_reg[3:0]} + {1'b0,rp_reg_in[3:0]} : | |
5403 | sch_ras_reg_en ? {1'b0,rp_reg[3:0]} + {1'b0,ras_reg_in[3:0]} : rc_reg[4:0]; | |
5404 | ||
5405 | assign inv_rc_reg_in[3:2] = ~rc_reg_in[3:2]; | |
5406 | assign rc_reg[3:2] = ~inv_rc_reg[3:2]; | |
5407 | ||
5408 | mcu_drif_ctl_msff_ctl_macro__en_1__width_5 pff_rc_reg ( // FS:wmr_protect | |
5409 | .scan_in(pff_rc_reg_wmr_scanin), | |
5410 | .scan_out(pff_rc_reg_wmr_scanout), | |
5411 | .siclk(aclk_wmr), | |
5412 | .din({rc_reg_in[4],inv_rc_reg_in[3:2],rc_reg_in[1:0]}), | |
5413 | .en(sch_rc_reg_en), | |
5414 | .dout({rc_reg[4],inv_rc_reg[3:2],rc_reg[1:0]}), | |
5415 | .l1clk(l1clk), | |
5416 | .soclk(soclk)); | |
5417 | ||
5418 | ////////////////////////////////////////////////////////////////// | |
5419 | // Write recovery time period (WR) REGISTER - reset to 4'h3 | |
5420 | ////////////////////////////////////////////////////////////////// | |
5421 | ||
5422 | assign sch_wr_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hc0); | |
5423 | assign wr_reg_in[3:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hc0) ? | |
5424 | drif_ucb_data[3:0] : wr_reg; | |
5425 | ||
5426 | assign inv_wr_reg_in[1:0] = ~wr_reg_in[1:0]; | |
5427 | assign wr_reg[1:0] = ~inv_wr_reg[1:0]; | |
5428 | ||
5429 | mcu_drif_ctl_msff_ctl_macro__en_1__width_4 pff_wr_reg ( // FS:wmr_protect | |
5430 | .scan_in(pff_wr_reg_wmr_scanin), | |
5431 | .scan_out(pff_wr_reg_wmr_scanout), | |
5432 | .siclk(aclk_wmr), | |
5433 | .din({wr_reg_in[3:2],inv_wr_reg_in[1:0]}), | |
5434 | .en(sch_wr_reg_en), | |
5435 | .dout({wr_reg[3:2],inv_wr_reg[1:0]}), | |
5436 | .l1clk(l1clk), | |
5437 | .soclk(soclk)); | |
5438 | ||
5439 | ////////////////////////////////////////////////////////////////// | |
5440 | // Auto refresh to active time period (RFC) REGISTER - reset to 7'h27 | |
5441 | // 127.5 ns @ 333 MHz | |
5442 | ////////////////////////////////////////////////////////////////// | |
5443 | assign sch_rfc_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hc8); | |
5444 | assign rfc_reg_in[6:0] = drif_ucb_data[6:0]; | |
5445 | ||
5446 | assign rfc_reg_reset_val_in[6:0] = {rfc_reg_in[6], | |
5447 | ~rfc_reg_in[5], | |
5448 | rfc_reg_in[4], | |
5449 | rfc_reg_in[3], | |
5450 | ~rfc_reg_in[2], | |
5451 | ~rfc_reg_in[1], | |
5452 | ~rfc_reg_in[0]}; | |
5453 | ||
5454 | assign rfc_reg[6:0] = {rfc_reg_reset_val[6], | |
5455 | ~rfc_reg_reset_val[5], | |
5456 | rfc_reg_reset_val[4], | |
5457 | rfc_reg_reset_val[3], | |
5458 | ~rfc_reg_reset_val[2], | |
5459 | ~rfc_reg_reset_val[1], | |
5460 | ~rfc_reg_reset_val[0]}; | |
5461 | ||
5462 | mcu_drif_ctl_msff_ctl_macro__en_1__width_7 pff_rfc_reg ( // FS:wmr_protect | |
5463 | .scan_in(pff_rfc_reg_wmr_scanin), | |
5464 | .scan_out(pff_rfc_reg_wmr_scanout), | |
5465 | .siclk(aclk_wmr), | |
5466 | .din(rfc_reg_reset_val_in[6:0]), | |
5467 | .en(sch_rfc_reg_en), | |
5468 | .dout(rfc_reg_reset_val[6:0]), | |
5469 | .l1clk(l1clk), | |
5470 | .soclk(soclk)); | |
5471 | ||
5472 | ////////////////////////////////////////////////////////////////// | |
5473 | // MODE REGISTER SET command period (tMRD) REGISTER - reset to 2'h2 | |
5474 | ////////////////////////////////////////////////////////////////// | |
5475 | assign sch_mrd_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hd0); | |
5476 | assign mrd_reg_in[1:0] = drif_ucb_data[1:0]; | |
5477 | ||
5478 | assign inv_mrd_reg_in[1] = ~mrd_reg_in[1]; | |
5479 | assign mrd_reg[1] = ~inv_mrd_reg[1]; | |
5480 | ||
5481 | mcu_drif_ctl_msff_ctl_macro__en_1__width_2 pff_mrd_reg ( // FS:wmr_protect | |
5482 | .scan_in(pff_mrd_reg_wmr_scanin), | |
5483 | .scan_out(pff_mrd_reg_wmr_scanout), | |
5484 | .siclk(aclk_wmr), | |
5485 | .din({inv_mrd_reg_in[1],mrd_reg_in[0]}), | |
5486 | .en(sch_mrd_reg_en), | |
5487 | .dout({inv_mrd_reg[1],mrd_reg[0]}), | |
5488 | .l1clk(l1clk), | |
5489 | .soclk(soclk)); | |
5490 | ||
5491 | ////////////////////////////////////////////////////////////////// | |
5492 | // Four Activate Window (tFAW) REGISTER - reset to 5'ha | |
5493 | ////////////////////////////////////////////////////////////////// | |
5494 | assign faw_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'hd8); | |
5495 | assign faw_reg_in[4:0] = drif_ucb_data[4:0]; | |
5496 | ||
5497 | assign inv_faw_reg_in[1] = ~faw_reg_in[3]; | |
5498 | assign inv_faw_reg_in[0] = ~faw_reg_in[1]; | |
5499 | assign faw_reg[3] = ~inv_faw_reg[1]; | |
5500 | assign faw_reg[1] = ~inv_faw_reg[0]; | |
5501 | ||
5502 | mcu_drif_ctl_msff_ctl_macro__en_1__width_5 pff_faw_reg ( // FS:wmr_protect | |
5503 | .scan_in(pff_faw_reg_wmr_scanin), | |
5504 | .scan_out(pff_faw_reg_wmr_scanout), | |
5505 | .siclk(aclk_wmr), | |
5506 | .din({faw_reg_in[4],faw_reg_in[2],faw_reg_in[0],inv_faw_reg_in[1:0]}), | |
5507 | .dout({faw_reg[4],faw_reg[2],faw_reg[0],inv_faw_reg[1:0]}), | |
5508 | .en(faw_reg_en), | |
5509 | .l1clk(l1clk), | |
5510 | .soclk(soclk)); | |
5511 | ||
5512 | ////////////////////////////////////////////////////////////////// | |
5513 | // POWER ON INIT WAIT FOR PRECHARGE. Should be 400ns - implies | |
5514 | // 85 cycles (8'h55) w/ some margin at 200 MHz. | |
5515 | ////////////////////////////////////////////////////////////////// | |
5516 | assign drif_precharge_wait_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'he8); | |
5517 | assign drif_precharge_wait_in[7:0] = drif_ucb_data[7:0]; | |
5518 | ||
5519 | assign drif_precharge_wait_reset_val_in[7:0] = {drif_precharge_wait_in[7], | |
5520 | ~drif_precharge_wait_in[6], | |
5521 | drif_precharge_wait_in[5], | |
5522 | ~drif_precharge_wait_in[4], | |
5523 | drif_precharge_wait_in[3], | |
5524 | ~drif_precharge_wait_in[2], | |
5525 | drif_precharge_wait_in[1], | |
5526 | ~drif_precharge_wait_in[0]}; | |
5527 | ||
5528 | assign drif_precharge_wait[7:0] = {drif_precharge_wait_reset_val[7], | |
5529 | ~drif_precharge_wait_reset_val[6], | |
5530 | drif_precharge_wait_reset_val[5], | |
5531 | ~drif_precharge_wait_reset_val[4], | |
5532 | drif_precharge_wait_reset_val[3], | |
5533 | ~drif_precharge_wait_reset_val[2], | |
5534 | drif_precharge_wait_reset_val[1], | |
5535 | ~drif_precharge_wait_reset_val[0]}; | |
5536 | ||
5537 | mcu_drif_ctl_msff_ctl_macro__en_1__width_8 ff_precharge_wait ( | |
5538 | .scan_in(ff_precharge_wait_scanin), | |
5539 | .scan_out(ff_precharge_wait_scanout), | |
5540 | .din(drif_precharge_wait_reset_val_in[7:0]), | |
5541 | .en(drif_precharge_wait_en), | |
5542 | .dout(drif_precharge_wait_reset_val[7:0]), | |
5543 | .l1clk(l1clk), | |
5544 | .siclk(siclk), | |
5545 | .soclk(soclk)); | |
5546 | ||
5547 | ////////////////////////////////////////////////////// | |
5548 | // DRAM ERROR INJECTION REGISTER | |
5549 | ////////////////////////////////////////////////////// | |
5550 | ||
5551 | // error injection enable | |
5552 | assign drif_err_inj_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h290) | | |
5553 | drif_sshot_err_reg & drif_err_injected; | |
5554 | assign drif_err_inj_reg_in = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h290) ? drif_ucb_data[31] : 1'b0; | |
5555 | ||
5556 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_err_inj ( // FS:wmr_protect | |
5557 | .scan_in(pff_err_inj_wmr_scanin), | |
5558 | .scan_out(pff_err_inj_wmr_scanout), | |
5559 | .siclk(aclk_wmr), | |
5560 | .din(drif_err_inj_reg_in), | |
5561 | .en(drif_err_inj_reg_en), | |
5562 | .dout(drif_err_inj_reg), | |
5563 | .l1clk(l1clk), | |
5564 | .soclk(soclk)); | |
5565 | ||
5566 | // turn off error injection for scrub writes | |
5567 | assign drif_err_inj_enable = drif_err_inj_reg & ~drif_err_state[`DRIF_ERR_READ1]; | |
5568 | ||
5569 | // single shot vs. continuous error injection | |
5570 | assign drif_sshot_err_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h290) | drif_err_injected; | |
5571 | assign drif_sshot_err_reg_in = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h290) ? drif_ucb_data[30] : 1'b0; | |
5572 | ||
5573 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_sshot ( // FS:wmr_protect | |
5574 | .scan_in(pff_sshot_wmr_scanin), | |
5575 | .scan_out(pff_sshot_wmr_scanout), | |
5576 | .siclk(aclk_wmr), | |
5577 | .din(drif_sshot_err_reg_in), | |
5578 | .en(drif_sshot_err_reg_en), | |
5579 | .dout(drif_sshot_err_reg), | |
5580 | .l1clk(l1clk), | |
5581 | .soclk(soclk)); | |
5582 | ||
5583 | // mask to XOR with ECC bits | |
5584 | assign drif_err_mask_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h290); | |
5585 | assign drif_err_mask_reg_in[15:0] = drif_ucb_data[15:0]; | |
5586 | ||
5587 | mcu_drif_ctl_msff_ctl_macro__en_1__width_16 pff_err_mask ( // FS:wmr_protect | |
5588 | .scan_in(pff_err_mask_wmr_scanin), | |
5589 | .scan_out(pff_err_mask_wmr_scanout), | |
5590 | .siclk(aclk_wmr), | |
5591 | .din(drif_err_mask_reg_in[15:0]), | |
5592 | .en(drif_err_mask_reg_en), | |
5593 | .dout(drif_err_mask_reg[15:0]), | |
5594 | .l1clk(l1clk), | |
5595 | .soclk(soclk)); | |
5596 | ||
5597 | // Generation of "drif_err_injected" signal to reset when in single shot mode | |
5598 | ||
5599 | assign drif_wdq_sel = drif0_wdq_sel | drif1_wdq_sel; | |
5600 | ||
5601 | mcu_drif_ctl_msff_ctl_macro ff_wdq_sel_d1 ( | |
5602 | .scan_in(ff_wdq_sel_d1_scanin), | |
5603 | .scan_out(ff_wdq_sel_d1_scanout), | |
5604 | .din(drif_wdq_sel), | |
5605 | .dout(drif_wdq_sel_d1), | |
5606 | .l1clk(l1clk), | |
5607 | .siclk(siclk), | |
5608 | .soclk(soclk)); | |
5609 | ||
5610 | assign drif_err_injected = drif_wdq_sel_d1; | |
5611 | ||
5612 | ////////////////////////////////////////////////////////////////// | |
5613 | // REFRESH counters for 266MHz, 333, and 400MHz frequency. | |
5614 | // We have to have one refresh for every 7.8micro seconds | |
5615 | // for 266 MHz, count is 7.8micro/3.75 nano = 2080 (0x820) | |
5616 | // for 333 MHz, count is 7.8micro/3 nano = 2600 (0xA28) | |
5617 | // for 400 MHz, count is 7.8micro/2.5 nano = 3120 (0xC30) | |
5618 | // We can also post upto 8 refreshes at a time. | |
5619 | ////////////////////////////////////////////////////////////////// | |
5620 | assign drif_ref_freq_reset_val[12:0] = 13'h820; | |
5621 | ||
5622 | assign drif_ref_freq_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h20); | |
5623 | assign drif_ref_freq_in[12:0] = drif_ucb_data[12:0] ^ drif_ref_freq_reset_val[12:0]; | |
5624 | ||
5625 | assign drif_ref_freq[12:0] = drif_ref_freq_out[12:0] ^ drif_ref_freq_reset_val[12:0]; | |
5626 | ||
5627 | mcu_drif_ctl_msff_ctl_macro__en_1__width_13 pff_ref_freq ( // FS:wmr_protect | |
5628 | .scan_in(pff_ref_freq_wmr_scanin), | |
5629 | .scan_out(pff_ref_freq_wmr_scanout), | |
5630 | .siclk(aclk_wmr), | |
5631 | .din(drif_ref_freq_in[12:0]), | |
5632 | .dout(drif_ref_freq_out[12:0]), | |
5633 | .en(drif_ref_freq_en), | |
5634 | .l1clk(l1clk), | |
5635 | .soclk(soclk)); | |
5636 | ||
5637 | ////////////////////////////////////////////////////////////////// | |
5638 | // refresh counter register - refresh occurs when this reaches refresh | |
5639 | // frequency register value | |
5640 | ////////////////////////////////////////////////////////////////// | |
5641 | assign drif_refresh_req_picked = drif_mcu_state[3] & fbdic_sync_frame_req_l & (~drif_cmd_a_val & ~drif_cmd_a_val_d1 | | |
5642 | drif_dram_dimm_a[2:0] != drif_refresh_rank[2:0]) & ~drif_wdq_sel_d1 & | |
5643 | (|(drif_refresh_rank_dec[15:0] & pdmc_rank_avail[15:0])); | |
5644 | assign drif_ref_cnt_in[12:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h38) ? drif_ucb_data[12:0] : | |
5645 | (drif_ref_go | drif_ref_freq_en | ~fbdic_l0_state | drif_hw_selfrsh) ? 13'h0 : | |
5646 | drif_ref_cnt[12:0] + 13'h1; | |
5647 | ||
5648 | mcu_drif_ctl_msff_ctl_macro__width_13 ff_ref_cnt ( | |
5649 | .scan_in(ff_ref_cnt_scanin), | |
5650 | .scan_out(ff_ref_cnt_scanout), | |
5651 | .din(drif_ref_cnt_in[12:0]), | |
5652 | .dout(drif_ref_cnt[12:0]), | |
5653 | .l1clk(l1clk), | |
5654 | .siclk(siclk), | |
5655 | .soclk(soclk)); | |
5656 | ||
5657 | assign drif_ref_go = (drif_ref_cnt[12:0] >= drif_ref_freq[12:0]) | (fbdic_l0_state & ~fbdic_l0_state_d1); | |
5658 | ||
5659 | mcu_drif_ctl_msff_ctl_macro ff_l0_state_d1 ( | |
5660 | .scan_in(ff_l0_state_d1_scanin), | |
5661 | .scan_out(ff_l0_state_d1_scanout), | |
5662 | .din(fbdic_l0_state), | |
5663 | .dout(fbdic_l0_state_d1), | |
5664 | .l1clk(l1clk), | |
5665 | .siclk(siclk), | |
5666 | .soclk(soclk)); | |
5667 | ||
5668 | ////////////////////////////////////////////////////////////////// | |
5669 | // Logic that generates scrubbing for all address at periodic interval | |
5670 | ////////////////////////////////////////////////////////////////// | |
5671 | ||
5672 | // SCRUB ENABLE BIT | |
5673 | assign drif_data_scrub_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h40); | |
5674 | assign drif_data_scrub_en_in = drif_ucb_data[0]; | |
5675 | ||
5676 | mcu_drif_ctl_msff_ctl_macro__en_1__width_1 pff_data_scrub ( // FS:wmr_protect | |
5677 | .scan_in(pff_data_scrub_wmr_scanin), | |
5678 | .scan_out(pff_data_scrub_wmr_scanout), | |
5679 | .siclk(aclk_wmr), | |
5680 | .din(drif_data_scrub_en_in), | |
5681 | .en(drif_data_scrub_en), | |
5682 | .dout(drif_data_scrub_enabled), | |
5683 | .l1clk(l1clk), | |
5684 | .soclk(soclk)); | |
5685 | ||
5686 | // scrub count - scrub request is issued when this reaches scrub frequency value | |
5687 | assign drif_scrub_cnt_in[11:0] = drif_scrub_cnt[11:0] + 12'h1; | |
5688 | assign drif_scrub_cnt_reset = ((drif_scrub_picked & drif_scrub_read_pending) | ~drif_init_mcu_done); | |
5689 | ||
5690 | assign drif_scrub_cnt_en = drif_data_scrub_enabled & fbdic_l0_state & ~drif_hw_selfrsh; | |
5691 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_12 ff_scrub_cnt ( | |
5692 | .scan_in(ff_scrub_cnt_scanin), | |
5693 | .scan_out(ff_scrub_cnt_scanout), | |
5694 | .din(drif_scrub_cnt_in[11:0]), | |
5695 | .dout(drif_scrub_cnt[11:0]), | |
5696 | .en(drif_scrub_cnt_en), | |
5697 | .clr(drif_scrub_cnt_reset), | |
5698 | .l1clk(l1clk), | |
5699 | .siclk(siclk), | |
5700 | .soclk(soclk)); | |
5701 | ||
5702 | // Assert read valid when its time to scrub and there is no pending scrub write | |
5703 | // Reset the read valid when scrub read valid is picked | |
5704 | assign drif_scrub_read_pending_in = (drif_scrub_cnt[11:0] >= drif_freq_scrub[11:0]) & drif_data_scrub_enabled; | |
5705 | assign drif_scrub_read_pending_en = drif_scrub_read_pending_in & ~drif_scrub_read_outstanding & ~drif_scrub_addr_err & | |
5706 | drif_err_fifo_empty & drif_err_fifo_empty_d1; | |
5707 | assign drif_scrub_read_pending_reset = drif_scrub_read_pending & drif_scrub_picked; | |
5708 | ||
5709 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_scrub_read_pending ( | |
5710 | .scan_in(ff_scrub_read_pending_scanin), | |
5711 | .scan_out(ff_scrub_read_pending_scanout), | |
5712 | .din(drif_scrub_read_pending_in), | |
5713 | .dout(drif_scrub_read_pending), | |
5714 | .clr(drif_scrub_read_pending_reset), | |
5715 | .en(drif_scrub_read_pending_en), | |
5716 | .l1clk(l1clk), | |
5717 | .siclk(siclk), | |
5718 | .soclk(soclk)); | |
5719 | ||
5720 | // scrub outstanging - wait for signal from rdpctl that scrub request finished to reset | |
5721 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_scrub_read_out ( | |
5722 | .scan_in(ff_scrub_read_out_scanin), | |
5723 | .scan_out(ff_scrub_read_out_scanout), | |
5724 | .din(1'b1), | |
5725 | .dout(drif_scrub_read_outstanding), | |
5726 | .clr(rdpctl_scrub_read_done), | |
5727 | .en(drif_scrub_read_pending_reset), | |
5728 | .l1clk(l1clk), | |
5729 | .siclk(siclk), | |
5730 | .soclk(soclk)); | |
5731 | ||
5732 | // used for incrementing power down counter | |
5733 | mcu_drif_ctl_msff_ctl_macro ff_scrub_read_pending_en_d1 ( | |
5734 | .scan_in(ff_scrub_read_pending_en_d1_scanin), | |
5735 | .scan_out(ff_scrub_read_pending_en_d1_scanout), | |
5736 | .din(drif_scrub_read_pending_en), | |
5737 | .dout(drif_scrub_read_pending_en_d1), | |
5738 | .l1clk(l1clk), | |
5739 | .siclk(siclk), | |
5740 | .soclk(soclk)); | |
5741 | ||
5742 | assign drif_scrub_time = drif_scrub_read_pending_en & ~drif_scrub_read_pending_en_d1; | |
5743 | ||
5744 | ////////////////////////////////////// | |
5745 | // POWER THROTTLING LOGIC | |
5746 | ////////////////////////////////////// | |
5747 | ||
5748 | ////////////////////////////////////// | |
5749 | // Max banks open at any given time - reset to 17'h1ffff | |
5750 | ////////////////////////////////////// | |
5751 | ||
5752 | assign pt_max_banks_open_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h28); | |
5753 | assign pt_max_banks_open_in[16:0] = drif_ucb_data[16:0]; | |
5754 | ||
5755 | assign inv_pt_max_banks_open_in[16:0] = ~pt_max_banks_open_in[16:0]; | |
5756 | assign pt_max_banks_open[16:0] = ~inv_pt_max_banks_open[16:0]; | |
5757 | ||
5758 | mcu_drif_ctl_msff_ctl_macro__en_1__width_17 pff_max_banks_open ( // FS:wmr_protect | |
5759 | .scan_in(pff_max_banks_open_wmr_scanin), | |
5760 | .scan_out(pff_max_banks_open_wmr_scanout), | |
5761 | .siclk(aclk_wmr), | |
5762 | .din(inv_pt_max_banks_open_in[16:0]), | |
5763 | .dout(inv_pt_max_banks_open[16:0]), | |
5764 | .en(pt_max_banks_open_en), | |
5765 | .l1clk(l1clk), | |
5766 | .soclk(soclk)); | |
5767 | ||
5768 | ////////////////////////////////////// | |
5769 | // Max pt period time - reset to 16'hffff | |
5770 | ////////////////////////////////////// | |
5771 | ||
5772 | assign pt_max_time_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h48); | |
5773 | assign pt_max_time_in[15:0] = drif_ucb_data[15:0]; | |
5774 | ||
5775 | assign inv_pt_max_time_in[15:0] = ~pt_max_time_in[15:0]; | |
5776 | assign pt_max_time[15:0] = ~inv_pt_max_time[15:0]; | |
5777 | ||
5778 | mcu_drif_ctl_msff_ctl_macro__en_1__width_16 pff_max_time ( // FS:wmr_protect | |
5779 | .scan_in(pff_max_time_wmr_scanin), | |
5780 | .scan_out(pff_max_time_wmr_scanout), | |
5781 | .siclk(aclk_wmr), | |
5782 | .din(inv_pt_max_time_in[15:0]), | |
5783 | .dout(inv_pt_max_time[15:0]), | |
5784 | .en(pt_max_time_en), | |
5785 | .l1clk(l1clk), | |
5786 | .soclk(soclk)); | |
5787 | ||
5788 | // send sync signal to other MCU's to reset counters so all MCUs' power throttling is in sync | |
5789 | assign pt_sync_out = pt_max_time_en | pt_max_banks_open_en; | |
5790 | ||
5791 | // make it two cycles long so it will be valid with the clock enable | |
5792 | mcu_drif_ctl_msff_ctl_macro ff_pt_sync_out_d1 ( | |
5793 | .scan_in(ff_pt_sync_out_d1_scanin), | |
5794 | .scan_out(ff_pt_sync_out_d1_scanout), | |
5795 | .din(pt_sync_out), | |
5796 | .dout(pt_sync_out_d1), | |
5797 | .l1clk(l1clk), | |
5798 | .siclk(siclk), | |
5799 | .soclk(soclk)); | |
5800 | ||
5801 | assign mcu_pt_sync_out_in = pt_sync_out | pt_sync_out_d1; | |
5802 | mcu_drif_ctl_msff_ctl_macro__width_1 ff_pt_sync_out ( | |
5803 | .scan_in(ff_pt_sync_out_scanin), | |
5804 | .scan_out(ff_pt_sync_out_scanout), | |
5805 | .din(mcu_pt_sync_out_in), | |
5806 | .dout(mcu_pt_sync_out), | |
5807 | .l1clk(l1clk), | |
5808 | .siclk(siclk), | |
5809 | .soclk(soclk)); | |
5810 | ||
5811 | mcu_drif_ctl_msff_ctl_macro__width_4 ff_pt_sync ( | |
5812 | .scan_in(ff_pt_sync_scanin), | |
5813 | .scan_out(ff_pt_sync_scanout), | |
5814 | .din({mcu_pt_sync_in0, mcu_pt_sync_in1, mcu_pt_sync_in2, mcu_pt_sync_out}), | |
5815 | .dout(pt_sync[3:0]), | |
5816 | .l1clk(l1clk), | |
5817 | .siclk(siclk), | |
5818 | .soclk(soclk)); | |
5819 | ||
5820 | // reset counters when time period expires or incoming syncs from register updates | |
5821 | assign pt_reset = (pt_time_cntr[15:0] >= pt_max_time[15:0]) | (|pt_sync[3:0]); | |
5822 | ||
5823 | // number of opened banks - increment when RAS is picked for a read or write | |
5824 | assign pt_banks_open_en = drif_cas_picked | pt_reset; | |
5825 | assign pt_banks_open_in[16:0] = pt_reset ? 17'h0 : pt_banks_open[16:0] + 17'h1; | |
5826 | ||
5827 | mcu_drif_ctl_msff_ctl_macro__en_1__width_17 ff_banks_open ( | |
5828 | .scan_in(ff_banks_open_scanin), | |
5829 | .scan_out(ff_banks_open_scanout), | |
5830 | .din(pt_banks_open_in[16:0]), | |
5831 | .dout(pt_banks_open[16:0]), | |
5832 | .en(pt_banks_open_en), | |
5833 | .l1clk(l1clk), | |
5834 | .siclk(siclk), | |
5835 | .soclk(soclk)); | |
5836 | ||
5837 | // power throttling time period counter | |
5838 | assign pt_time_cntr_in[15:0] = pt_reset ? 16'h0 : pt_time_cntr[15:0] + 16'b1; | |
5839 | ||
5840 | mcu_drif_ctl_msff_ctl_macro__width_16 ff_time_cntr ( | |
5841 | .scan_in(ff_time_cntr_scanin), | |
5842 | .scan_out(ff_time_cntr_scanout), | |
5843 | .din(pt_time_cntr_in[15:0]), | |
5844 | .dout(pt_time_cntr[15:0]), | |
5845 | .l1clk(l1clk), | |
5846 | .siclk(siclk), | |
5847 | .soclk(soclk)); | |
5848 | ||
5849 | // blocks new requests from issuing once open bank threshold is reached | |
5850 | assign drif_blk_new_openbank_in = (pt_banks_open[16:0] >= pt_max_banks_open[16:0]); | |
5851 | ||
5852 | mcu_drif_ctl_msff_ctl_macro__width_1 ff_blk_openbank ( | |
5853 | .scan_in(ff_blk_openbank_scanin), | |
5854 | .scan_out(ff_blk_openbank_scanout), | |
5855 | .din(drif_blk_new_openbank_in), | |
5856 | .dout(drif_blk_new_openbank), | |
5857 | .l1clk(l1clk), | |
5858 | .siclk(siclk), | |
5859 | .soclk(soclk)); | |
5860 | ||
5861 | ////////////////////////////////////// | |
5862 | // Mode register write done | |
5863 | ////////////////////////////////////// | |
5864 | ||
5865 | assign drif_wr_mode_reg_done_in = drif_mcu_state[1] | drif_wr_mode_reg_done; | |
5866 | assign wr_mode_reg_done_reset = (drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h1a0) & drif_ucb_data[0]); | |
5867 | ||
5868 | mcu_drif_ctl_msff_ctl_macro__clr_1__width_1 ff_wr_mode_reg ( | |
5869 | .scan_in(ff_wr_mode_reg_scanin), | |
5870 | .scan_out(ff_wr_mode_reg_scanout), | |
5871 | .din(drif_wr_mode_reg_done_in), | |
5872 | .dout(drif_wr_mode_reg_done), | |
5873 | .clr(wr_mode_reg_done_reset), | |
5874 | .l1clk(l1clk), | |
5875 | .siclk(siclk), | |
5876 | .soclk(soclk)); | |
5877 | ||
5878 | ////////////////////////////////////// | |
5879 | // Intialization sequence done - reset when state[1] reached | |
5880 | ////////////////////////////////////// | |
5881 | assign drif_init_mcu_done_in = (drif_mcu_state_next[4:0] == 5'd1) | drif_init_mcu_done & ~drif_mcu_state[0]; | |
5882 | ||
5883 | mcu_drif_ctl_msff_ctl_macro__width_1 ff_init_done ( | |
5884 | .scan_in(ff_init_done_scanin), | |
5885 | .scan_out(ff_init_done_scanout), | |
5886 | .din(drif_init_mcu_done_in), | |
5887 | .dout(drif_init_mcu_done), | |
5888 | .l1clk(l1clk), | |
5889 | .siclk(siclk), | |
5890 | .soclk(soclk)); | |
5891 | ||
5892 | ////////////////////////////////////// | |
5893 | // DRAM INIT STATUS REG - reset to 0, cleared when DRAM init register is writen | |
5894 | ////////////////////////////////////// | |
5895 | assign drif_init_status_reg_in = (~drif_mcu_state[1] & (drif_mcu_state_next[4:0] == 5'd1)) | drif_init_status_reg; | |
5896 | assign int_status_reg_reset = (drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h1a0)); | |
5897 | ||
5898 | mcu_drif_ctl_msff_ctl_macro__clr_1__width_1 ff_init_status_reg ( | |
5899 | .scan_in(ff_init_status_reg_scanin), | |
5900 | .scan_out(ff_init_status_reg_scanout), | |
5901 | .din(drif_init_status_reg_in), | |
5902 | .dout(drif_init_status_reg), | |
5903 | .clr(int_status_reg_reset), | |
5904 | .l1clk(l1clk), | |
5905 | .siclk(siclk), | |
5906 | .soclk(soclk)); | |
5907 | ||
5908 | // Generate ack valid and flop both valid and data for register reads | |
5909 | assign {drif_rdata_nack_vld_in,drif_rdata_ack_vld_in,drif_rdata_data_in[63:0]} = drif_read_ucb_info[65:0] | fbdic_ucb_rd_data[65:0]; | |
5910 | ||
5911 | mcu_drif_ctl_msff_ctl_macro__width_66 ff_ucb_data ( | |
5912 | .scan_in(ff_ucb_data_scanin), | |
5913 | .scan_out(ff_ucb_data_scanout), | |
5914 | .din({drif_rdata_ack_vld_in, drif_rdata_nack_vld_in, drif_rdata_data_in[63:0]}), | |
5915 | .dout({drif_rdata_ack_vld, drif_rdata_nack_vld, drif_rdata_data[63:0]}), | |
5916 | .l1clk(l1clk), | |
5917 | .siclk(siclk), | |
5918 | .soclk(soclk)); | |
5919 | ||
5920 | ///////////////////////////////////////////////////////// | |
5921 | // Power down mode enable register | |
5922 | ///////////////////////////////////////////////////////// | |
5923 | assign drif_pd_mode_enable_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h238); | |
5924 | assign drif_pd_mode_enable_in = drif_ucb_data[0]; | |
5925 | ||
5926 | mcu_drif_ctl_msff_ctl_macro__en_1 ff_pd_mode_enable ( | |
5927 | .scan_in(ff_pd_mode_enable_scanin), | |
5928 | .scan_out(ff_pd_mode_enable_scanout), | |
5929 | .din(drif_pd_mode_enable_in), | |
5930 | .dout(drif_pd_mode_enable), | |
5931 | .en(drif_pd_mode_enable_en), | |
5932 | .l1clk(l1clk), | |
5933 | .siclk(siclk), | |
5934 | .soclk(soclk)); | |
5935 | ||
5936 | ///////////////////////////////////////////////////////// | |
5937 | // PERFORMANCE COUNTERS | |
5938 | ///////////////////////////////////////////////////////// | |
5939 | ||
5940 | assign drif_perf_cntl_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h400); | |
5941 | assign drif_perf_cntl_reg_in[7:0] = drif_ucb_data[7:0]; | |
5942 | ||
5943 | mcu_drif_ctl_msff_ctl_macro__en_1__width_8 ff_perf_cntl_reg ( | |
5944 | .scan_in(ff_perf_cntl_reg_scanin), | |
5945 | .scan_out(ff_perf_cntl_reg_scanout), | |
5946 | .din(drif_perf_cntl_reg_in[7:0]), | |
5947 | .en(drif_perf_cntl_reg_en), | |
5948 | .dout(drif_perf_cntl_reg[7:0]), | |
5949 | .l1clk(l1clk), | |
5950 | .siclk(siclk), | |
5951 | .soclk(soclk)); | |
5952 | ||
5953 | // Due to timing issues we have to flop some critical siganls and then do the increment | |
5954 | // of the perf counter in the following cycle. | |
5955 | ||
5956 | mcu_drif_ctl_msff_ctl_macro__width_16 ff_crit_sig ( | |
5957 | .scan_in(ff_crit_sig_scanin), | |
5958 | .scan_out(ff_crit_sig_scanout), | |
5959 | .din({drif_rd_xaction_picked, drif_wr_xaction_picked, drif_bank_busy_stall, | |
5960 | drif_rd_que_latency[4:0], drif_wr_que_latency[4:0], drif_writeback_buf_hit, | |
5961 | drif_rd_que_latency_adj, drif_wr_que_latency_adj}), | |
5962 | .dout({drif_rd_xaction_picked_d1, drif_wr_xaction_picked_d1, drif_bank_busy_stall_d1, | |
5963 | drif_rd_que_latency_noadj_d1[4:0], drif_wr_que_latency_noadj_d1[4:0], drif_writeback_buf_hit_d1, | |
5964 | drif_rd_que_latency_adj_d1, drif_wr_que_latency_adj_d1}), | |
5965 | .l1clk(l1clk), | |
5966 | .siclk(siclk), | |
5967 | .soclk(soclk)); | |
5968 | ||
5969 | assign drif_rd_que_latency_d1[4:0] = drif_rd_que_latency_noadj_d1[4:0] - {4'h0,drif_rd_que_latency_adj_d1}; | |
5970 | assign drif_wr_que_latency_d1[4:0] = drif_wr_que_latency_noadj_d1[4:0] - {4'h0,drif_wr_que_latency_adj_d1}; | |
5971 | ||
5972 | assign drif_perf_cnt0_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h408) | ~drif_perf_cntl_reg[7]; | |
5973 | assign drif_perf_cnt0_reg_in[31:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h408) ? drif_ucb_data[63:32] : | |
5974 | drif_perf0_adder_out[31:0]; | |
5975 | ||
5976 | assign drif_perf0_adder_out[31:0] = ({1'b0, drif_perf_cnt0_reg[30:0]} + drif_perf0_adder_in[31:0]) | | |
5977 | {drif_perf_cnt0_reg[31], 31'h0}; | |
5978 | ||
5979 | assign drif_perf0_adder_in[31:0] = {32{drif_perf_cntl_reg[7:4] == 4'h0}} & {31'h0, drif_rd_xaction_picked_d1} | | |
5980 | {32{drif_perf_cntl_reg[7:4] == 4'h1}} & {31'h0, drif_wr_xaction_picked_d1} | | |
5981 | {32{drif_perf_cntl_reg[7:4] == 4'h2}} & {31'h0, drif_rd_or_wr_xaction_picked_d1} | | |
5982 | {32{drif_perf_cntl_reg[7:4] == 4'h3}} & {31'h0, drif_bank_busy_stall_d1} | | |
5983 | {32{drif_perf_cntl_reg[7:4] == 4'h4}} & {27'h0, drif_rd_que_latency_d1[4:0]} | | |
5984 | {32{drif_perf_cntl_reg[7:4] == 4'h5}} & {27'h0, drif_wr_que_latency_d1[4:0]} | | |
5985 | {32{drif_perf_cntl_reg[7:4] == 4'h6}} & {26'h0, drif_rd_or_wr_que_latency_d1[5:0]} | | |
5986 | {32{drif_perf_cntl_reg[7:4] == 4'h7}} & {31'h0, drif_writeback_buf_hit_d1}; | |
5987 | ||
5988 | mcu_drif_ctl_msff_ctl_macro__en_1__width_32 ff_perf_cnt0_reg ( | |
5989 | .scan_in(ff_perf_cnt0_reg_scanin), | |
5990 | .scan_out(ff_perf_cnt0_reg_scanout), | |
5991 | .din(drif_perf_cnt0_reg_in), | |
5992 | .en(drif_perf_cnt0_reg_en), | |
5993 | .dout(drif_perf_cnt0_reg), | |
5994 | .l1clk(l1clk), | |
5995 | .siclk(siclk), | |
5996 | .soclk(soclk)); | |
5997 | ||
5998 | assign drif_perf_cnt1_reg_en = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h408) | ~drif_perf_cntl_reg[3]; | |
5999 | assign drif_perf_cnt1_reg_in[31:0] = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h408) ? drif_ucb_data[31:0] : | |
6000 | drif_perf1_adder_out[31:0]; | |
6001 | ||
6002 | assign drif_perf1_adder_out[31:0] = ({1'b0, drif_perf_cnt1_reg[30:0]} + drif_perf1_adder_in[31:0]) | | |
6003 | {drif_perf_cnt1_reg[31], 31'h0}; | |
6004 | ||
6005 | assign drif_perf1_adder_in[31:0] = {32{drif_perf_cntl_reg[3:0] == 4'h0}} & {31'h0, drif_rd_xaction_picked_d1} | | |
6006 | {32{drif_perf_cntl_reg[3:0] == 4'h1}} & {31'h0, drif_wr_xaction_picked_d1} | | |
6007 | {32{drif_perf_cntl_reg[3:0] == 4'h2}} & {31'h0, drif_rd_or_wr_xaction_picked_d1} | | |
6008 | {32{drif_perf_cntl_reg[3:0] == 4'h3}} & {31'h0, drif_bank_busy_stall_d1} | | |
6009 | {32{drif_perf_cntl_reg[3:0] == 4'h4}} & {27'h0, drif_rd_que_latency_d1[4:0]} | | |
6010 | {32{drif_perf_cntl_reg[3:0] == 4'h5}} & {27'h0, drif_wr_que_latency_d1[4:0]} | | |
6011 | {32{drif_perf_cntl_reg[3:0] == 4'h6}} & {26'h0, drif_rd_or_wr_que_latency_d1[5:0]} | | |
6012 | {32{drif_perf_cntl_reg[3:0] == 4'h7}} & {31'h0, drif_writeback_buf_hit_d1}; | |
6013 | ||
6014 | mcu_drif_ctl_msff_ctl_macro__en_1__width_32 ff_perf_cnt1_reg ( | |
6015 | .scan_in(ff_perf_cnt1_reg_scanin), | |
6016 | .scan_out(ff_perf_cnt1_reg_scanout), | |
6017 | .din(drif_perf_cnt1_reg_in), | |
6018 | .en(drif_perf_cnt1_reg_en), | |
6019 | .dout(drif_perf_cnt1_reg), | |
6020 | .l1clk(l1clk), | |
6021 | .siclk(siclk), | |
6022 | .soclk(soclk)); | |
6023 | ||
6024 | // This CAS PICKED is generated to cover 2 ch mode case too! | |
6025 | assign drif_cmd_write = drif_mux_write_en; | |
6026 | ||
6027 | // READ XACTION | |
6028 | mcu_drif_ctl_msff_ctl_macro ff_raw_hazard_d1 ( | |
6029 | .scan_in(ff_raw_hazard_d1_scanin), | |
6030 | .scan_out(ff_raw_hazard_d1_scanout), | |
6031 | .din(drif_wr_entry_pend_in), | |
6032 | .dout(drif_raw_hazard_d1), | |
6033 | .l1clk(l1clk), | |
6034 | .siclk(siclk), | |
6035 | .soclk(soclk)); | |
6036 | ||
6037 | assign drif_rd_xaction_picked = drif_cas_picked & ~drif_cmd_write & ~fbdic_sync_frame_req & ~drif_raw_hazard_d1 & | |
6038 | (drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[4]); | |
6039 | ||
6040 | // WRITE XACTION | |
6041 | assign drif_wr_xaction_picked = drif_cas_picked & drif_cmd_write & ~fbdic_sync_frame_req & | |
6042 | (drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[4]); | |
6043 | ||
6044 | // READ OR WRITE XACTION | |
6045 | assign drif_rd_or_wr_xaction_picked_d1 = drif_rd_xaction_picked_d1 | drif_wr_xaction_picked_d1; | |
6046 | ||
6047 | // BANK BUSY STALLS | |
6048 | assign drif_bank_busy_stall = (|(drq0_rdbuf_valids[7:0] | drq1_rdbuf_valids[7:0] | | |
6049 | drq0_wrbuf_valids[7:0] | drq1_wrbuf_valids[7:0])) & | |
6050 | ~( (|drif_ras_picked[15:0]) | drif_cas_picked ) & | |
6051 | (drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[4]) & drif_init_status_reg; | |
6052 | ||
6053 | // READ QUE LATENCY | |
6054 | assign drif_rd_que_latency[4:0] = ({1'b0,drq0_read_queue_cnt[3:0]} + {1'b0,drq1_read_queue_cnt[3:0]}) & | |
6055 | {5{(drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[3] | drif_mcu_state[4])}} & | |
6056 | {5{drif_init_status_reg}}; | |
6057 | ||
6058 | assign drif_rd_que_latency_adj = (|drif_ras_picked[15:0]) & ~drif_cmd_picked & ~drif_scrub_picked & | |
6059 | (drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[3] | drif_mcu_state[4]) & | |
6060 | drif_init_status_reg; | |
6061 | ||
6062 | // WRITE QUE LATENCY | |
6063 | assign drif_wr_que_latency[4:0] = ({1'b0,drq0_write_queue_cnt[3:0]} + {1'b0,drq1_write_queue_cnt[3:0]}) & | |
6064 | {5{(drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[3] | drif_mcu_state[4])}} & | |
6065 | {5{drif_init_status_reg}}; | |
6066 | ||
6067 | assign drif_wr_que_latency_adj = (|drif_ras_picked[15:0]) & drif_cmd_picked & ~drif_scrub_picked & | |
6068 | (drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[3] | drif_mcu_state[4]) & | |
6069 | drif_init_status_reg; | |
6070 | ||
6071 | // READ OR WRITE QUE LATENCY | |
6072 | assign drif_rd_or_wr_que_latency_d1[5:0] = {1'b0, drif_rd_que_latency_d1[4:0]} + {1'b0, drif_wr_que_latency_d1[4:0]}; | |
6073 | ||
6074 | // WRITEBACK BUFFER HITS | |
6075 | assign drif_writeback_buf_hit = drif_wr_entry_pend_in & drif_init_status_reg & | |
6076 | (drif_mcu_state[1] | drif_mcu_state[2] | drif_mcu_state[4]); | |
6077 | ||
6078 | // Register read logic | |
6079 | assign drif_read_ucb_info[65] = drif_ucb_rd_req_vld & ~drif_ucb_addr[11] & ~drif_read_ucb_info[64]; | |
6080 | ||
6081 | assign drif_read_ucb_info[64:0] = {65{drif_ucb_rd_req_vld}} & | |
6082 | {{65{(drif_ucb_addr[12:0] == 13'h0)}} & {1'b1, 60'h0, drif_cas_addr_bits[3:0]} | | |
6083 | {65{(drif_ucb_addr[12:0] == 13'h8)}} & {1'b1, 60'h0, drif_ras_addr_bits[3:0]} | | |
6084 | {65{(drif_ucb_addr[12:0] == 13'h10)}} & {1'b1, 61'h0, mode_reg[6:4]} | | |
6085 | {65{(drif_ucb_addr[12:0] == 13'h18)}} & {1'b1, 52'h0, drif_freq_scrub[11:0]} | | |
6086 | {65{(drif_ucb_addr[12:0] == 13'h20)}} & {1'b1, 51'h0, drif_ref_freq[12:0]} | | |
6087 | {65{(drif_ucb_addr[12:0] == 13'h28)}} & {1'b1, 47'h0, pt_max_banks_open[16:0]} | | |
6088 | {65{(drif_ucb_addr[12:0] == 13'h38)}} & {1'b1, 51'h0, drif_ref_cnt[12:0]} | | |
6089 | {65{(drif_ucb_addr[12:0] == 13'h40)}} & {1'b1, 63'h0, drif_data_scrub_enabled} | | |
6090 | {65{(drif_ucb_addr[12:0] == 13'h48)}} & {1'b1, 48'h0, pt_max_time[15:0]} | | |
6091 | {65{(drif_ucb_addr[12:0] == 13'h80)}} & {1'b1, 60'h0, rrd_reg[3:0]} | | |
6092 | {65{(drif_ucb_addr[12:0] == 13'h88)}} & {1'b1, 59'h0, rc_reg[4:0]} | | |
6093 | {65{(drif_ucb_addr[12:0] == 13'h90)}} & {1'b1, 60'h0, rcd_reg[3:0]} | | |
6094 | {65{(drif_ucb_addr[12:0] == 13'h98)}} & {1'b1, 60'h0, wtr_dly_reg[3:0]} | | |
6095 | {65{(drif_ucb_addr[12:0] == 13'ha0)}} & {1'b1, 60'h0, rtw_dly_reg[3:0]} | | |
6096 | {65{(drif_ucb_addr[12:0] == 13'ha8)}} & {1'b1, 61'h0, rtp_reg[2:0]} | | |
6097 | {65{(drif_ucb_addr[12:0] == 13'hb0)}} & {1'b1, 60'h0, ras_reg[3:0]} | | |
6098 | {65{(drif_ucb_addr[12:0] == 13'hb8)}} & {1'b1, 60'h0, rp_reg[3:0]} | | |
6099 | {65{(drif_ucb_addr[12:0] == 13'hc0)}} & {1'b1, 60'h0, wr_reg[3:0]} | | |
6100 | {65{(drif_ucb_addr[12:0] == 13'hc8)}} & {1'b1, 57'h0, rfc_reg[6:0]} | | |
6101 | {65{(drif_ucb_addr[12:0] == 13'hd0)}} & {1'b1, 62'h0, mrd_reg[1:0]} | | |
6102 | {65{(drif_ucb_addr[12:0] == 13'hd8)}} & {1'b1, 59'h0, faw_reg[4:0]} | | |
6103 | {65{(drif_ucb_addr[12:0] == 13'he0)}} & {1'b1, 62'h0, iwtr_reg[1:0]} | | |
6104 | {65{(drif_ucb_addr[12:0] == 13'he8)}} & {1'b1, 56'h0, drif_precharge_wait[7:0]} | | |
6105 | {65{(drif_ucb_addr[12:0] == 13'h108)}} & {1'b1, 63'h0, drif_stacked_dimm} | | |
6106 | {65{(drif_ucb_addr[12:0] == 13'h110)}} & {1'b1, 49'h0, ext_mode_reg2[14:0]} | | |
6107 | {65{(drif_ucb_addr[12:0] == 13'h118)}} & {1'b1, 49'h0, ext_mode_reg1[14:0]} | | |
6108 | {65{(drif_ucb_addr[12:0] == 13'h120)}} & {1'b1, 49'h0, ext_mode_reg3[14:0]} | | |
6109 | {65{(drif_ucb_addr[12:0] == 13'h128)}} & {1'b1, 63'h0, drif_eight_bank_mode_mod} | | |
6110 | {65{(drif_ucb_addr[12:0] == 13'h138)}} & {1'b1, 63'h0, drif_branch_disabled} | | |
6111 | {65{(drif_ucb_addr[12:0] == 13'h140)}} & {1'b1, 63'h0, drif_addr_bank_low_sel} | | |
6112 | {65{(drif_ucb_addr[12:0] == 13'h148)}} & {1'b1, 63'h0, drif_single_channel_mode} | | |
6113 | {65{(drif_ucb_addr[12:0] == 13'h1a0)}} & {1'b1, 62'h0, drif_cke_reg, drif_init} | | |
6114 | {65{(drif_ucb_addr[12:0] == 13'h208)}} & {1'b1, 63'h0, drif_wr_mode_reg_done} | | |
6115 | {65{(drif_ucb_addr[12:0] == 13'h210)}} & {1'b1, 63'h0, drif_init_status_reg} | | |
6116 | {65{(drif_ucb_addr[12:0] == 13'h218)}} & {1'b1, 60'h0, drif_dimms_present} | | |
6117 | {65{(drif_ucb_addr[12:0] == 13'h220)}} & {1'b1, 63'h0, drif_fail_over_mode} | | |
6118 | {65{(drif_ucb_addr[12:0] == 13'h228)}} & {1'b1, 29'h0, drif_fail_over_mask[34:0]} | | |
6119 | {65{(drif_ucb_addr[12:0] == 13'h230)}} & {1'b1, 58'h0, rdpctl_dtm_atspeed, rdpctl_dtm_mask_chnl[1:0], | |
6120 | rdpctl_dbg_trig_enable, rdpctl_mask_err, | |
6121 | rdpctl_kp_lnk_up} | | |
6122 | {65{(drif_ucb_addr[12:0] == 13'h238)}} & {1'b1, 63'h0, drif_pd_mode_enable} | | |
6123 | {65{(drif_ucb_addr[12:0] == 13'h280)}} & {1'b1, rdpctl_err_sts_reg[25:16],38'h0,rdpctl_err_sts_reg[15:0]} | | |
6124 | {65{(drif_ucb_addr[12:0] == 13'h288)}} & {1'b1, 24'h0, rdpctl_err_addr_reg[35:0], 4'h0} | | |
6125 | {65{(drif_ucb_addr[12:0] == 13'h290)}} & {1'b1, 32'h0, drif_err_inj_reg, drif_sshot_err_reg, 14'h0, | |
6126 | drif_err_mask_reg[15:0]} | | |
6127 | {65{(drif_ucb_addr[12:0] == 13'h298)}} & {1'b1, 48'h0, rdpctl_err_cnt[15:0]} | | |
6128 | {65{(drif_ucb_addr[12:0] == 13'h2a0)}} & {1'b1, 28'h0, rdpctl_err_loc[35:0]} | | |
6129 | {65{(drif_ucb_addr[12:0] == 13'h2a8)}} & {1'b1, 27'h0, rdpctl_err_retry_reg[36:0]} | | |
6130 | {65{(drif_ucb_addr[12:0] == 13'h400)}} & {1'b1, 56'h0, drif_perf_cntl_reg[7:0]} | | |
6131 | {65{(drif_ucb_addr[12:0] == 13'h408)}} & {1'b1, drif_perf_cnt0_reg[31:0],drif_perf_cnt1_reg[31:0]}}; | |
6132 | ||
6133 | /////////////////////////////////////////////////// | |
6134 | // Error FIFO: when ecc error occurs, transaction is placed in this FIFO for further processing | |
6135 | /////////////////////////////////////////////////// | |
6136 | ||
6137 | mcu_drif_ctl_msff_ctl_macro__width_3 ff_scrub_wren ( | |
6138 | .scan_in(ff_scrub_wren_scanin), | |
6139 | .scan_out(ff_scrub_wren_scanout), | |
6140 | .din({rdpctl_scrub_wren,drif_scrub_wren,drif_scrub_wren_d1}), | |
6141 | .dout({drif_scrub_wren,drif_scrub_wren_d1,drif_scrub_wren_d2}), | |
6142 | .l1clk(l1clk), | |
6143 | .siclk(siclk), | |
6144 | .soclk(soclk)); | |
6145 | ||
6146 | assign drif_err_fifo_deq = drif_err_state[`DRIF_ERR_READ0] & drif_err_fifo_crc & rdpctl_no_crc_err | | |
6147 | drif_err_state[`DRIF_ERR_READ1] & drif_err_rd_picked | | |
6148 | drif_err_state[`DRIF_ERR_WRITE] & (|readdp_ecc_multi_err[1:0]) & drif_scrub_wren | | |
6149 | drif_err_state[`DRIF_ERR_CRC_FR] & drif_err_fifo_crc & (rdpctl_no_crc_err | rdpctl_crc_err); | |
6150 | ||
6151 | // if the entry dequeued from the error fifo is from a scrub, | |
6152 | // need to increment the scrub address | |
6153 | assign drif_scrub_addr_incr = drif_err_fifo_scrub & ~drif_err_fifo_crc & drif_err_fifo_deq; | |
6154 | ||
6155 | // 14 - crc/ecc error | |
6156 | // 13 - rank | |
6157 | // 12:10 - dimm | |
6158 | // 9:7 - bank | |
6159 | // 6 - parity | |
6160 | // 5 - scrub | |
6161 | // 4:2 - req queue entry | |
6162 | // 1 - qword id (PA[5]) | |
6163 | // 0 - l2 bank (for which queue) | |
6164 | ||
6165 | mcu_errq_ctl errq ( | |
6166 | .scan_in(errq_scanin), | |
6167 | .scan_out(errq_scanout), | |
6168 | .l1clk(l1clk), | |
6169 | .errq_enq(rdpctl_err_fifo_enq), | |
6170 | .errq_din(rdpctl_err_fifo_data[14:0]), | |
6171 | .errq_deq(drif_err_fifo_deq), | |
6172 | .errq_dout(drif_err_fifo_ent0[14:0]), | |
6173 | .errq_full(drif_err_fifo_full), | |
6174 | .errq_empty(drif_err_fifo_empty), | |
6175 | .tcu_aclk(tcu_aclk), | |
6176 | .tcu_bclk(tcu_bclk), | |
6177 | .tcu_scan_en(tcu_scan_en) | |
6178 | ); | |
6179 | ||
6180 | mcu_drif_ctl_msff_ctl_macro ff_err_fifo_empty_d1 ( | |
6181 | .scan_in(ff_err_fifo_empty_d1_scanin), | |
6182 | .scan_out(ff_err_fifo_empty_d1_scanout), | |
6183 | .din(drif_err_fifo_empty), | |
6184 | .dout(drif_err_fifo_empty_d1), | |
6185 | .l1clk(l1clk), | |
6186 | .siclk(siclk), | |
6187 | .soclk(soclk)); | |
6188 | ||
6189 | assign drif_drq0_clear_ent[0] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6190 | (drif_err_fifo_rdq_entry[2:0] == 3'h0); | |
6191 | assign drif_drq0_clear_ent[1] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6192 | (drif_err_fifo_rdq_entry[2:0] == 3'h1); | |
6193 | assign drif_drq0_clear_ent[2] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6194 | (drif_err_fifo_rdq_entry[2:0] == 3'h2); | |
6195 | assign drif_drq0_clear_ent[3] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6196 | (drif_err_fifo_rdq_entry[2:0] == 3'h3); | |
6197 | assign drif_drq0_clear_ent[4] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6198 | (drif_err_fifo_rdq_entry[2:0] == 3'h4); | |
6199 | assign drif_drq0_clear_ent[5] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6200 | (drif_err_fifo_rdq_entry[2:0] == 3'h5); | |
6201 | assign drif_drq0_clear_ent[6] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6202 | (drif_err_fifo_rdq_entry[2:0] == 3'h6); | |
6203 | assign drif_drq0_clear_ent[7] = drif_err_fifo_deq & ~drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6204 | (drif_err_fifo_rdq_entry[2:0] == 3'h7); | |
6205 | ||
6206 | assign drif_drq1_clear_ent[0] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6207 | (drif_err_fifo_rdq_entry[2:0] == 3'h0); | |
6208 | assign drif_drq1_clear_ent[1] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6209 | (drif_err_fifo_rdq_entry[2:0] == 3'h1); | |
6210 | assign drif_drq1_clear_ent[2] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6211 | (drif_err_fifo_rdq_entry[2:0] == 3'h2); | |
6212 | assign drif_drq1_clear_ent[3] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6213 | (drif_err_fifo_rdq_entry[2:0] == 3'h3); | |
6214 | assign drif_drq1_clear_ent[4] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6215 | (drif_err_fifo_rdq_entry[2:0] == 3'h4); | |
6216 | assign drif_drq1_clear_ent[5] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6217 | (drif_err_fifo_rdq_entry[2:0] == 3'h5); | |
6218 | assign drif_drq1_clear_ent[6] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6219 | (drif_err_fifo_rdq_entry[2:0] == 3'h6); | |
6220 | assign drif_drq1_clear_ent[7] = drif_err_fifo_deq & drif_err_fifo_l2bank & ~drif_err_fifo_scrub & ~drif_err_fifo_crc & | |
6221 | (drif_err_fifo_rdq_entry[2:0] == 3'h7); | |
6222 | ||
6223 | // Error handling code | |
6224 | ||
6225 | // override values for address queue selects when processing errors | |
6226 | assign drif0_req_rdwr_addr_sel[0] = drq0_req_rdwr_addr_sel & drif_err_state[`DRIF_ERR_IDLE]; | |
6227 | assign drif0_req_rdwr_addr_sel[1] = ~drif0_req_rdwr_addr_sel[0]; | |
6228 | assign drif0_rd_adr_queue_sel[7:0] = drif_err_state[`DRIF_ERR_IDLE] ? drq0_rd_adr_queue_sel[7:0] : | |
6229 | drif_err_rd_adr_queue_sel[7:0]; | |
6230 | assign drif1_req_rdwr_addr_sel[0] = drq1_req_rdwr_addr_sel & drif_err_state[`DRIF_ERR_IDLE]; | |
6231 | assign drif1_req_rdwr_addr_sel[1] = ~drif1_req_rdwr_addr_sel[0]; | |
6232 | assign drif1_rd_adr_queue_sel[7:0] = drif_err_state[`DRIF_ERR_IDLE] ? drq1_rd_adr_queue_sel[7:0] : | |
6233 | drif_err_rd_adr_queue_sel[7:0]; | |
6234 | ||
6235 | assign drif_err_rd_adr_queue_sel[7:0] = {drif_err_fifo_rdq_entry[2:0] == 3'h7, drif_err_fifo_rdq_entry[2:0] == 3'h6, | |
6236 | drif_err_fifo_rdq_entry[2:0] == 3'h5, drif_err_fifo_rdq_entry[2:0] == 3'h4, | |
6237 | drif_err_fifo_rdq_entry[2:0] == 3'h3, drif_err_fifo_rdq_entry[2:0] == 3'h2, | |
6238 | drif_err_fifo_rdq_entry[2:0] == 3'h1, drif_err_fifo_rdq_entry[2:0] == 3'h0}; | |
6239 | ||
6240 | // error fifo entry components | |
6241 | assign drif_err_fifo_crc = drif_err_fifo_ent0[14]; | |
6242 | assign drif_err_fifo_rank_adr = drif_err_fifo_ent0[13]; | |
6243 | assign drif_err_fifo_dimm_adr[2:0] = drif_err_fifo_ent0[12:10]; | |
6244 | assign drif_err_fifo_bank_adr[3] = drif_eight_bank_mode_mod ? (drif_stacked_dimm ? drif_err_fifo_rank_adr : | |
6245 | drif_err_fifo_dimm_adr[0]) : | |
6246 | (drif_stacked_dimm ? drif_err_fifo_dimm_adr[0] : | |
6247 | drif_err_fifo_dimm_adr[1]); | |
6248 | assign drif_err_fifo_bank_adr[2:0] = drif_err_fifo_ent0[9:7]; | |
6249 | assign drif_err_fifo_parity = drif_err_fifo_ent0[6]; | |
6250 | assign drif_err_fifo_scrub = drif_err_fifo_ent0[5]; | |
6251 | assign drif_err_fifo_rdq_entry[2:0] = drif_err_fifo_ent0[4:2]; | |
6252 | assign drif_err_fifo_err_type = drif_err_fifo_ent0[1]; | |
6253 | assign drif_err_fifo_l2bank = drif_err_fifo_ent0[0]; | |
6254 | ||
6255 | // generate signals to arbitration logic to send out error requests | |
6256 | assign drif_err_ready = |(drif_bank_available[15:0] & drif_err_entry_val[15:0]) & ~drif_blk_new_openbank & | |
6257 | ~(|dmmdly_4_activate_stall[7:0]) & fbdic_sync_frame_req_l & ~fbdic_l0s_lfsr_stall & | |
6258 | ~drif_crc_retry_wait & ~fbdic_error_mode & woq_empty & woq_owr_empty & ~woq_wr_error_mode & | |
6259 | (|drif_err_rank_avail[15:0]) & ~drif_cas_picked & ~woq_wdata_send; | |
6260 | assign drif_err_rd_ready = drif_err_ready & (drif_err_state[`DRIF_ERR_READ0] | drif_err_state[`DRIF_ERR_READ1] | | |
6261 | drif_err_state[`DRIF_ERR_CRC_FR] & (fbdic_l0_state | fbdic_chnl_reset_error_mode)) & | |
6262 | (|drif_dimm_err_rd_avail[7:0]); | |
6263 | assign drif_err_wr_ready = drif_err_ready & drif_err_wrdata_ready & (drif_err_state[`DRIF_ERR_WRITE]) & | |
6264 | ~fbdic_sync_frame_req_early3 & ~fbdic_sync_frame_req_early2 & | |
6265 | ~fbdic_sync_frame_req_early1 & ~fbdic_sync_frame_req; | |
6266 | ||
6267 | assign drif_dimm_err_rd_avail[7:0] = {drif_err_fifo_dimm_adr[2:0] == 3'h7, drif_err_fifo_dimm_adr[2:0] == 3'h6, | |
6268 | drif_err_fifo_dimm_adr[2:0] == 3'h5, drif_err_fifo_dimm_adr[2:0] == 3'h4, | |
6269 | drif_err_fifo_dimm_adr[2:0] == 3'h3, drif_err_fifo_dimm_adr[2:0] == 3'h2, | |
6270 | drif_err_fifo_dimm_adr[2:0] == 3'h1, drif_err_fifo_dimm_adr[2:0] == 3'h0} & | |
6271 | drif_dimm_rd_available[7:0]; | |
6272 | ||
6273 | assign rtr_cnt_is_zero_err = drif_err_fifo_dimm_adr[2:0] == 3'h0 & rtr_cnt_is_zero[0] | | |
6274 | drif_err_fifo_dimm_adr[2:0] == 3'h1 & rtr_cnt_is_zero[1] | | |
6275 | drif_err_fifo_dimm_adr[2:0] == 3'h2 & rtr_cnt_is_zero[2] | | |
6276 | drif_err_fifo_dimm_adr[2:0] == 3'h3 & rtr_cnt_is_zero[3] | | |
6277 | drif_err_fifo_dimm_adr[2:0] == 3'h4 & rtr_cnt_is_zero[4] | | |
6278 | drif_err_fifo_dimm_adr[2:0] == 3'h5 & rtr_cnt_is_zero[5] | | |
6279 | drif_err_fifo_dimm_adr[2:0] == 3'h6 & rtr_cnt_is_zero[6] | | |
6280 | drif_err_fifo_dimm_adr[2:0] == 3'h7 & rtr_cnt_is_zero[7]; | |
6281 | ||
6282 | assign wtr_cnt_is_zero_err = drif_err_fifo_dimm_adr[2:0] == 3'h0 & wtr_cnt_is_zero[0] | | |
6283 | drif_err_fifo_dimm_adr[2:0] == 3'h1 & wtr_cnt_is_zero[1] | | |
6284 | drif_err_fifo_dimm_adr[2:0] == 3'h2 & wtr_cnt_is_zero[2] | | |
6285 | drif_err_fifo_dimm_adr[2:0] == 3'h3 & wtr_cnt_is_zero[3] | | |
6286 | drif_err_fifo_dimm_adr[2:0] == 3'h4 & wtr_cnt_is_zero[4] | | |
6287 | drif_err_fifo_dimm_adr[2:0] == 3'h5 & wtr_cnt_is_zero[5] | | |
6288 | drif_err_fifo_dimm_adr[2:0] == 3'h6 & wtr_cnt_is_zero[6] | | |
6289 | drif_err_fifo_dimm_adr[2:0] == 3'h7 & wtr_cnt_is_zero[7]; | |
6290 | ||
6291 | assign wtw_cnt_is_zero_err = drif_err_fifo_dimm_adr[2:0] == 3'h0 & wtw_cnt_is_zero[0] | | |
6292 | drif_err_fifo_dimm_adr[2:0] == 3'h1 & wtw_cnt_is_zero[1] | | |
6293 | drif_err_fifo_dimm_adr[2:0] == 3'h2 & wtw_cnt_is_zero[2] | | |
6294 | drif_err_fifo_dimm_adr[2:0] == 3'h3 & wtw_cnt_is_zero[3] | | |
6295 | drif_err_fifo_dimm_adr[2:0] == 3'h4 & wtw_cnt_is_zero[4] | | |
6296 | drif_err_fifo_dimm_adr[2:0] == 3'h5 & wtw_cnt_is_zero[5] | | |
6297 | drif_err_fifo_dimm_adr[2:0] == 3'h6 & wtw_cnt_is_zero[6] | | |
6298 | drif_err_fifo_dimm_adr[2:0] == 3'h7 & wtw_cnt_is_zero[7]; | |
6299 | ||
6300 | assign rtw_cnt_is_zero_err = drif_err_fifo_dimm_adr[2:0] == 3'h0 & rtw_cnt_is_zero[0] | | |
6301 | drif_err_fifo_dimm_adr[2:0] == 3'h1 & rtw_cnt_is_zero[1] | | |
6302 | drif_err_fifo_dimm_adr[2:0] == 3'h2 & rtw_cnt_is_zero[2] | | |
6303 | drif_err_fifo_dimm_adr[2:0] == 3'h3 & rtw_cnt_is_zero[3] | | |
6304 | drif_err_fifo_dimm_adr[2:0] == 3'h4 & rtw_cnt_is_zero[4] | | |
6305 | drif_err_fifo_dimm_adr[2:0] == 3'h5 & rtw_cnt_is_zero[5] | | |
6306 | drif_err_fifo_dimm_adr[2:0] == 3'h6 & rtw_cnt_is_zero[6] | | |
6307 | drif_err_fifo_dimm_adr[2:0] == 3'h7 & rtw_cnt_is_zero[7]; | |
6308 | ||
6309 | assign drif_err_rd_picked = drif_err_rd_ready & rtr_cnt_is_zero_err & wtr_cnt_is_zero_err & rd_rrd_cnt_is_zero & | |
6310 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drif_err_fifo_dimm_adr[2:0] | | |
6311 | drif_last_rank_picked[3:0] == {drif_err_fifo_rank_adr,drif_err_fifo_dimm_adr[2:0]}); | |
6312 | assign drif_err_wr_picked = drif_err_wr_ready & wtw_cnt_is_zero_err & rtw_cnt_is_zero_err & | |
6313 | (~drif_rank_wait | drif_last_rank_picked[2:0] != drif_err_fifo_dimm_adr[2:0] | | |
6314 | drif_last_rank_picked[3:0] == {drif_err_fifo_rank_adr,drif_err_fifo_dimm_adr[2:0]}); | |
6315 | assign drif_crc_rd_picked = drif_err_rd_picked & drif_err_fifo_crc; | |
6316 | ||
6317 | assign drif_err_bank_valid[15:0] = {16{~drif_err_fifo_empty}} & | |
6318 | {drif_err_fifo_bank_adr[3:0] == 4'hf, drif_err_fifo_bank_adr[3:0] == 4'he, | |
6319 | drif_err_fifo_bank_adr[3:0] == 4'hd, drif_err_fifo_bank_adr[3:0] == 4'hc, | |
6320 | drif_err_fifo_bank_adr[3:0] == 4'hb, drif_err_fifo_bank_adr[3:0] == 4'ha, | |
6321 | drif_err_fifo_bank_adr[3:0] == 4'h9, drif_err_fifo_bank_adr[3:0] == 4'h8, | |
6322 | drif_err_fifo_bank_adr[3:0] == 4'h7, drif_err_fifo_bank_adr[3:0] == 4'h6, | |
6323 | drif_err_fifo_bank_adr[3:0] == 4'h5, drif_err_fifo_bank_adr[3:0] == 4'h4, | |
6324 | drif_err_fifo_bank_adr[3:0] == 4'h3, drif_err_fifo_bank_adr[3:0] == 4'h2, | |
6325 | drif_err_fifo_bank_adr[3:0] == 4'h1, drif_err_fifo_bank_adr[3:0] == 4'h0}; | |
6326 | ||
6327 | assign drif_err_entry_val[15:0] = drif_err_bank_valid[15:0] & {16{(((drif_refresh_rank[3:0] != | |
6328 | {drif_err_fifo_rank_adr,drif_err_fifo_dimm_adr[2:0]}) & | |
6329 | (drif_mcu_state[2] | drif_mcu_state[4]) & ~drif_init) | drif_mcu_state[1])}}; | |
6330 | ||
6331 | assign drif0_err_rd_picked = drif_err_rd_picked & ~drif_err_fifo_l2bank; | |
6332 | assign drif0_err_wr_picked = drif_err_wr_picked & ~drif_err_fifo_l2bank; | |
6333 | assign drif1_err_rd_picked = drif_err_rd_picked & drif_err_fifo_l2bank; | |
6334 | assign drif1_err_wr_picked = drif_err_wr_picked & drif_err_fifo_l2bank; | |
6335 | ||
6336 | mcu_drif_ctl_msff_ctl_macro ff_err_rd_picked_d1 ( | |
6337 | .scan_in(ff_err_rd_picked_d1_scanin), | |
6338 | .scan_out(ff_err_rd_picked_d1_scanout), | |
6339 | .din(drif_err_rd_picked), | |
6340 | .dout(drif_err_rd_picked_d1), | |
6341 | .l1clk(l1clk), | |
6342 | .siclk(siclk), | |
6343 | .soclk(soclk)); | |
6344 | ||
6345 | mcu_drif_ctl_msff_ctl_macro__width_4 ff_err_fifo_d1 ( | |
6346 | .scan_in(ff_err_fifo_d1_scanin), | |
6347 | .scan_out(ff_err_fifo_d1_scanout), | |
6348 | .din({drif_err_fifo_crc,drif_err_fifo_rdq_entry[2:0]}), | |
6349 | .dout({drif_err_fifo_crc_d1,drif_err_fifo_rdq_entry_d1[2:0]}), | |
6350 | .l1clk(l1clk), | |
6351 | .siclk(siclk), | |
6352 | .soclk(soclk)); | |
6353 | ||
6354 | assign drif_crc_retry_wait_in = drif_crc_rd_picked ? 1'b1 : | |
6355 | rdpctl_no_crc_err | (rdpctl_crc_err & drif_err_state[`DRIF_ERR_CRC_FR]) | | |
6356 | fbdic_scr_frame_req_d4 | fbdic_err_fast_reset_done ? 1'b0 : drif_crc_retry_wait; | |
6357 | mcu_drif_ctl_msff_ctl_macro ff_crc_retry_wait ( | |
6358 | .scan_in(ff_crc_retry_wait_scanin), | |
6359 | .scan_out(ff_crc_retry_wait_scanout), | |
6360 | .din(drif_crc_retry_wait_in), | |
6361 | .dout(drif_crc_retry_wait), | |
6362 | .l1clk(l1clk), | |
6363 | .siclk(siclk), | |
6364 | .soclk(soclk)); | |
6365 | ||
6366 | // Error handling state machine | |
6367 | // 0in one_hot -var drif_err_state[4:0] | |
6368 | assign inv_drif_err_state_next[0] = ~drif_err_state_next[0]; | |
6369 | assign drif_err_state[0] = ~inv_drif_err_state[0]; | |
6370 | mcu_drif_ctl_msff_ctl_macro__width_5 ff_err_state ( | |
6371 | .scan_in(ff_err_state_scanin), | |
6372 | .scan_out(ff_err_state_scanout), | |
6373 | .din({drif_err_state_next[4:1], inv_drif_err_state_next[0]}), | |
6374 | .dout({drif_err_state[4:1], inv_drif_err_state[0]}), | |
6375 | .l1clk(l1clk), | |
6376 | .siclk(siclk), | |
6377 | .soclk(soclk)); | |
6378 | ||
6379 | //`ifdef MCU_BUG_118947 | |
6380 | //assign drif_scrub_wr_drop = drif_err_wrdata_ready & (fbdic_scr_frame_req_d4 | ~fbdic_l0_state); | |
6381 | //`endif | |
6382 | ||
6383 | assign drif_err_state_next[`DRIF_ERR_IDLE] = drif_err_state[`DRIF_ERR_IDLE] & ~drif_err_ready | | |
6384 | //`ifdef MCU_BUG_118947 | |
6385 | // drif_err_state[`DRIF_ERR_WRITE] & | |
6386 | // ((|readdp_ecc_multi_err[1:0]) & drif_scrub_wren | drif_scrub_wr_drop) | | |
6387 | //`else | |
6388 | drif_err_state[`DRIF_ERR_WRITE] & ((|readdp_ecc_multi_err[1:0]) & drif_scrub_wren) | | |
6389 | //`endif | |
6390 | drif_err_state[`DRIF_ERR_READ0] & drif_err_fifo_crc & rdpctl_no_crc_err | | |
6391 | drif_err_state[`DRIF_ERR_READ1] & drif_err_rd_picked | | |
6392 | drif_err_state[`DRIF_ERR_CRC_FR] & drif_err_fifo_crc & (rdpctl_no_crc_err | | |
6393 | rdpctl_crc_err); | |
6394 | assign drif_err_state_next[`DRIF_ERR_READ0] = drif_err_state[`DRIF_ERR_IDLE] & drif_err_ready | | |
6395 | drif_err_state[`DRIF_ERR_READ0] & ~drif_err_rd_picked & ~drif_err_fifo_crc | | |
6396 | drif_err_state[`DRIF_ERR_READ0] & drif_err_fifo_crc & ~rdpctl_no_crc_err & | |
6397 | ~rdpctl_crc_err; | |
6398 | assign drif_err_state_next[`DRIF_ERR_WRITE] = drif_err_state[`DRIF_ERR_READ0] & drif_err_rd_picked & ~drif_err_fifo_crc | | |
6399 | drif_err_state[`DRIF_ERR_WRITE] & ~(drif_err_wr_picked | | |
6400 | //`ifdef MCU_BUG_118947 | |
6401 | // (|readdp_ecc_multi_err[1:0]) & drif_scrub_wren | drif_scrub_wr_drop); | |
6402 | //`else | |
6403 | (|readdp_ecc_multi_err[1:0]) & drif_scrub_wren); | |
6404 | //`endif | |
6405 | assign drif_err_state_next[`DRIF_ERR_READ1] = drif_err_state[`DRIF_ERR_WRITE] & drif_err_wr_picked | | |
6406 | drif_err_state[`DRIF_ERR_READ1] & ~drif_err_rd_picked; | |
6407 | assign drif_err_state_next[`DRIF_ERR_CRC_FR] = drif_err_state[`DRIF_ERR_READ0] & drif_err_fifo_crc & rdpctl_crc_err | | |
6408 | drif_err_state[`DRIF_ERR_CRC_FR] & drif_err_fifo_crc & ~rdpctl_no_crc_err & | |
6409 | ~rdpctl_crc_err; | |
6410 | ||
6411 | // error signals for other modules | |
6412 | assign drif_err_state_crc_fr = drif_err_state[`DRIF_ERR_CRC_FR]; | |
6413 | assign drif_mcu_error_mode_in = ~drif_err_fifo_empty | ~drif_err_state[`DRIF_ERR_IDLE] | fbdic_error_mode; | |
6414 | ||
6415 | mcu_drif_ctl_msff_ctl_macro ff_mcu_error_mode ( | |
6416 | .scan_in(ff_mcu_error_mode_scanin), | |
6417 | .scan_out(ff_mcu_error_mode_scanout), | |
6418 | .din(drif_mcu_error_mode_in), | |
6419 | .dout(drif_mcu_error_mode), | |
6420 | .l1clk(l1clk), | |
6421 | .siclk(siclk), | |
6422 | .soclk(soclk)); | |
6423 | ||
6424 | // Load enables for registers in rdpctl block | |
6425 | ||
6426 | assign drif_err_sts_reg_ld = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h280); | |
6427 | assign drif_err_addr_reg_ld = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h288); | |
6428 | assign drif_err_cnt_reg_ld = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h298); | |
6429 | assign drif_err_loc_reg_ld = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h2a0); | |
6430 | assign drif_err_retry_reg_ld = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h2a8); | |
6431 | assign drif_dbg_trig_reg_ld = drif_ucb_wr_req_vld & (drif_ucb_addr[12:0] == 13'h230); | |
6432 | ||
6433 | mcu_reqq_ctl reqq ( | |
6434 | .scan_in(reqq_scanin), | |
6435 | .scan_out(reqq_scanout), | |
6436 | .l1clk(l1clk), | |
6437 | .drif_eight_bank_mode(drif_eight_bank_mode_mod), | |
6438 | .drif_mcu_state_1(drif_mcu_state[1]), | |
6439 | .drif_mcu_state_2(drif_mcu_state[2]), | |
6440 | .drif_mcu_state_3(drif_mcu_state[3]), | |
6441 | .drif_mcu_state_4(drif_mcu_state[4]), | |
6442 | .drif_mcu_state_5(drif_mcu_state[5]), | |
6443 | .drif_mcu_state_6(drif_mcu_state[6]), | |
6444 | .woq_entry0(woq_entry0[15:0]), | |
6445 | .woq_entry1(woq_entry1[15:0]), | |
6446 | .woq_entry_valid(woq_entry_valid[2:0]), | |
6447 | .woq_entry0_val(woq_entry0_val[15:0]), | |
6448 | .woq_entry1_val(woq_entry1_val[15:0]), | |
6449 | .woq_wr_bank_val(woq_wr_bank_val[15:0]), | |
6450 | .woq_wdq_radr(woq_wdq_radr[4:0]), | |
6451 | .woq_io_wdata_sel(woq_io_wdata_sel[1:0]), | |
6452 | .woq1_wr_picked(woq1_wr_picked[2:0]), | |
6453 | .woq_wr_addr_picked(woq_wr_addr_picked[9:0]), | |
6454 | .woq_wr1_addr_picked(woq_wr1_addr_picked[9:0]), | |
6455 | .woq_wr2_addr_picked(woq_wr2_addr_picked[9:0]), | |
6456 | .woq_wr_index_picked(woq_wr_index_picked[2:0]), | |
6457 | .woq_wr1_index_picked(woq_wr1_index_picked[2:0]), | |
6458 | .woq_wr2_index_picked(woq_wr2_index_picked[2:0]), | |
6459 | .woq_wr_wdq_index_picked(woq_wr_wdq_index_picked[2:0]), | |
6460 | .woq_wr1_wdq_index_picked(woq_wr1_wdq_index_picked[2:0]), | |
6461 | .woq_wr2_wdq_index_picked(woq_wr2_wdq_index_picked[2:0]), | |
6462 | .woq_wr_adr_queue_sel(woq_wr_adr_queue_sel[7:0]), | |
6463 | .woq_wr1_adr_queue_sel(woq_wr1_adr_queue_sel[7:0]), | |
6464 | .woq_wr2_adr_queue_sel(woq_wr2_adr_queue_sel[7:0]), | |
6465 | .woq_wadr_parity(woq_wadr_parity), | |
6466 | .woq_wdata_wsn(woq_wdata_wsn), | |
6467 | .woq_err_st_wait_free(woq_err_st_wait_free), | |
6468 | .woq_err_fifo_empty(woq_err_fifo_empty), | |
6469 | .woq_wr_req_out(woq_wr_req_out[1:0]), | |
6470 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[15:0]), | |
6471 | .woq_owr_empty(woq_owr_empty), | |
6472 | .woq_empty(woq_empty), | |
6473 | .woq_wr_error_mode(woq_wr_error_mode), | |
6474 | .woq_wdata_send(woq_wdata_send), | |
6475 | .drq0_rd_adr_queue7_en(drq0_rd_adr_queue7_en), | |
6476 | .drq0_rd_adr_queue6_en(drq0_rd_adr_queue6_en), | |
6477 | .drq0_rd_adr_queue5_en(drq0_rd_adr_queue5_en), | |
6478 | .drq0_rd_adr_queue4_en(drq0_rd_adr_queue4_en), | |
6479 | .drq0_rd_adr_queue3_en(drq0_rd_adr_queue3_en), | |
6480 | .drq0_rd_adr_queue2_en(drq0_rd_adr_queue2_en), | |
6481 | .drq0_rd_adr_queue1_en(drq0_rd_adr_queue1_en), | |
6482 | .drq0_rd_adr_queue0_en(drq0_rd_adr_queue0_en), | |
6483 | .drq0_rd_adr_queue_sel(drq0_rd_adr_queue_sel[7:0]), | |
6484 | .drq0_wr_adr_queue7_en(drq0_wr_adr_queue7_en), | |
6485 | .drq0_wr_adr_queue6_en(drq0_wr_adr_queue6_en), | |
6486 | .drq0_wr_adr_queue5_en(drq0_wr_adr_queue5_en), | |
6487 | .drq0_wr_adr_queue4_en(drq0_wr_adr_queue4_en), | |
6488 | .drq0_wr_adr_queue3_en(drq0_wr_adr_queue3_en), | |
6489 | .drq0_wr_adr_queue2_en(drq0_wr_adr_queue2_en), | |
6490 | .drq0_wr_adr_queue1_en(drq0_wr_adr_queue1_en), | |
6491 | .drq0_wr_adr_queue0_en(drq0_wr_adr_queue0_en), | |
6492 | .drq0_req_rdwr_addr_sel(drq0_req_rdwr_addr_sel), | |
6493 | .drq0_rdbuf_valids(drq0_rdbuf_valids[7:0]), | |
6494 | .drq0_wrbuf_valids(drq0_wrbuf_valids[7:0]), | |
6495 | .drq0_pending_wr_req(drq0_pending_wr_req[7:0]), | |
6496 | .drq0_read_queue_cnt(drq0_read_queue_cnt[3:0]), | |
6497 | .drq0_write_queue_cnt(drq0_write_queue_cnt[3:0]), | |
6498 | .drq0_rd_entry0_val(drq0_rd_entry0_val[15:0]), | |
6499 | .drq0_rd_entry1_val(drq0_rd_entry1_val[15:0]), | |
6500 | .drq0_rd_entry2_val(drq0_rd_entry2_val[15:0]), | |
6501 | .drq0_rd_entry3_val(drq0_rd_entry3_val[15:0]), | |
6502 | .drq0_rd_entry4_val(drq0_rd_entry4_val[15:0]), | |
6503 | .drq0_rd_entry5_val(drq0_rd_entry5_val[15:0]), | |
6504 | .drq0_rd_entry6_val(drq0_rd_entry6_val[15:0]), | |
6505 | .drq0_rd_entry7_val(drq0_rd_entry7_val[15:0]), | |
6506 | .drq0_rd_bank_val(drq0_rd_bank_val[15:0]), | |
6507 | .drq0_rd_entry0_rank(drq0_rd_entry0_rank), | |
6508 | .drq0_rd_entry1_rank(drq0_rd_entry1_rank), | |
6509 | .drq0_rd_entry2_rank(drq0_rd_entry2_rank), | |
6510 | .drq0_rd_entry3_rank(drq0_rd_entry3_rank), | |
6511 | .drq0_rd_entry4_rank(drq0_rd_entry4_rank), | |
6512 | .drq0_rd_entry5_rank(drq0_rd_entry5_rank), | |
6513 | .drq0_rd_entry6_rank(drq0_rd_entry6_rank), | |
6514 | .drq0_rd_entry7_rank(drq0_rd_entry7_rank), | |
6515 | .drq0_wr_entry0_rank(drq0_wr_entry0_rank), | |
6516 | .drq0_wr_entry1_rank(drq0_wr_entry1_rank), | |
6517 | .drq0_wr_entry2_rank(drq0_wr_entry2_rank), | |
6518 | .drq0_wr_entry3_rank(drq0_wr_entry3_rank), | |
6519 | .drq0_wr_entry4_rank(drq0_wr_entry4_rank), | |
6520 | .drq0_wr_entry5_rank(drq0_wr_entry5_rank), | |
6521 | .drq0_wr_entry6_rank(drq0_wr_entry6_rank), | |
6522 | .drq0_wr_entry7_rank(drq0_wr_entry7_rank), | |
6523 | .drq0_rd_entry0_dimm(drq0_rd_entry0_dimm[2:0]), | |
6524 | .drq0_rd_entry1_dimm(drq0_rd_entry1_dimm[2:0]), | |
6525 | .drq0_rd_entry2_dimm(drq0_rd_entry2_dimm[2:0]), | |
6526 | .drq0_rd_entry3_dimm(drq0_rd_entry3_dimm[2:0]), | |
6527 | .drq0_rd_entry4_dimm(drq0_rd_entry4_dimm[2:0]), | |
6528 | .drq0_rd_entry5_dimm(drq0_rd_entry5_dimm[2:0]), | |
6529 | .drq0_rd_entry6_dimm(drq0_rd_entry6_dimm[2:0]), | |
6530 | .drq0_rd_entry7_dimm(drq0_rd_entry7_dimm[2:0]), | |
6531 | .drq0_wr_entry0_dimm(drq0_wr_entry0_dimm[2:0]), | |
6532 | .drq0_wr_entry1_dimm(drq0_wr_entry1_dimm[2:0]), | |
6533 | .drq0_wr_entry2_dimm(drq0_wr_entry2_dimm[2:0]), | |
6534 | .drq0_wr_entry3_dimm(drq0_wr_entry3_dimm[2:0]), | |
6535 | .drq0_wr_entry4_dimm(drq0_wr_entry4_dimm[2:0]), | |
6536 | .drq0_wr_entry5_dimm(drq0_wr_entry5_dimm[2:0]), | |
6537 | .drq0_wr_entry6_dimm(drq0_wr_entry6_dimm[2:0]), | |
6538 | .drq0_wr_entry7_dimm(drq0_wr_entry7_dimm[2:0]), | |
6539 | .drq0_rd_addr_picked(drq0_rd_addr_picked[9:0]), | |
6540 | .drq0_rdq_free(drq0_rdq_free), | |
6541 | .drq0_rdq_full(drq0_rdq_full), | |
6542 | .drq0_empty(drq0_empty), | |
6543 | .drq0_rd_index_picked(drq0_rd_index_picked[2:0]), | |
6544 | .drq0_wr_index_picked(drq0_wr_index_picked[2:0]), | |
6545 | .drq0_wr_id_picked(drq0_wr_id_picked[2:0]), | |
6546 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[15:0]), | |
6547 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[15:0]), | |
6548 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[15:0]), | |
6549 | .woq0_wdq_rd(woq0_wdq_rd), | |
6550 | .woq0_wdq_entry_free(woq0_wdq_entry_free[7:0]), | |
6551 | .drq0_rd_req(drq0_rd_req), | |
6552 | .drq0_wr_req(drq0_wr_req), | |
6553 | .drif0_raw_hazard(drif0_raw_hazard), | |
6554 | .l2if0_rd_req(l2if0_rd_req), | |
6555 | .l2if0_wr_req(l2if0_wr_req), | |
6556 | .drif0_cpu_wr_addr(drif0_cpu_wr_addr[2:0]), | |
6557 | .l2if0_wdq_in_cntr(l2if0_wdq_in_cntr[3:0]), | |
6558 | .l2b0_rd_rank_adr(l2b0_rd_rank_adr), | |
6559 | .l2b0_rd_dimm_adr(l2b0_rd_dimm_adr[2:0]), | |
6560 | .l2b0_rd_bank_adr(l2b0_rd_bank_adr[2:0]), | |
6561 | .l2b0_rd_addr_err(l2b0_rd_addr_err), | |
6562 | .l2b0_rd_addr_par(l2b0_rd_addr_par), | |
6563 | .l2b0_wr_rank_adr(l2b0_wr_rank_adr), | |
6564 | .l2b0_wr_dimm_adr(l2b0_wr_dimm_adr[2:0]), | |
6565 | .l2b0_wr_bank_adr(l2b0_wr_bank_adr[2:0]), | |
6566 | .l2b0_wr_addr_err(l2b0_wr_addr_err), | |
6567 | .l2b0_wr_addr_par(l2b0_wr_addr_par), | |
6568 | .rdpctl_drq0_clear_ent(rdpctl_drq0_clear_ent[7:0]), | |
6569 | .drif_drq0_clear_ent(drif_drq0_clear_ent[7:0]), | |
6570 | .drif0_rd_entry_picked(drif0_rd_entry_picked[7:0]), | |
6571 | .drq1_rd_adr_queue7_en(drq1_rd_adr_queue7_en), | |
6572 | .drq1_rd_adr_queue6_en(drq1_rd_adr_queue6_en), | |
6573 | .drq1_rd_adr_queue5_en(drq1_rd_adr_queue5_en), | |
6574 | .drq1_rd_adr_queue4_en(drq1_rd_adr_queue4_en), | |
6575 | .drq1_rd_adr_queue3_en(drq1_rd_adr_queue3_en), | |
6576 | .drq1_rd_adr_queue2_en(drq1_rd_adr_queue2_en), | |
6577 | .drq1_rd_adr_queue1_en(drq1_rd_adr_queue1_en), | |
6578 | .drq1_rd_adr_queue0_en(drq1_rd_adr_queue0_en), | |
6579 | .drq1_rd_adr_queue_sel(drq1_rd_adr_queue_sel[7:0]), | |
6580 | .drq1_wr_adr_queue7_en(drq1_wr_adr_queue7_en), | |
6581 | .drq1_wr_adr_queue6_en(drq1_wr_adr_queue6_en), | |
6582 | .drq1_wr_adr_queue5_en(drq1_wr_adr_queue5_en), | |
6583 | .drq1_wr_adr_queue4_en(drq1_wr_adr_queue4_en), | |
6584 | .drq1_wr_adr_queue3_en(drq1_wr_adr_queue3_en), | |
6585 | .drq1_wr_adr_queue2_en(drq1_wr_adr_queue2_en), | |
6586 | .drq1_wr_adr_queue1_en(drq1_wr_adr_queue1_en), | |
6587 | .drq1_wr_adr_queue0_en(drq1_wr_adr_queue0_en), | |
6588 | .drq1_req_rdwr_addr_sel(drq1_req_rdwr_addr_sel), | |
6589 | .drq1_rdbuf_valids(drq1_rdbuf_valids[7:0]), | |
6590 | .drq1_wrbuf_valids(drq1_wrbuf_valids[7:0]), | |
6591 | .drq1_pending_wr_req(drq1_pending_wr_req[7:0]), | |
6592 | .drq1_read_queue_cnt(drq1_read_queue_cnt[3:0]), | |
6593 | .drq1_write_queue_cnt(drq1_write_queue_cnt[3:0]), | |
6594 | .drq1_rd_entry0_val(drq1_rd_entry0_val[15:0]), | |
6595 | .drq1_rd_entry1_val(drq1_rd_entry1_val[15:0]), | |
6596 | .drq1_rd_entry2_val(drq1_rd_entry2_val[15:0]), | |
6597 | .drq1_rd_entry3_val(drq1_rd_entry3_val[15:0]), | |
6598 | .drq1_rd_entry4_val(drq1_rd_entry4_val[15:0]), | |
6599 | .drq1_rd_entry5_val(drq1_rd_entry5_val[15:0]), | |
6600 | .drq1_rd_entry6_val(drq1_rd_entry6_val[15:0]), | |
6601 | .drq1_rd_entry7_val(drq1_rd_entry7_val[15:0]), | |
6602 | .drq1_rd_bank_val(drq1_rd_bank_val[15:0]), | |
6603 | .drq1_rd_entry0_rank(drq1_rd_entry0_rank), | |
6604 | .drq1_rd_entry1_rank(drq1_rd_entry1_rank), | |
6605 | .drq1_rd_entry2_rank(drq1_rd_entry2_rank), | |
6606 | .drq1_rd_entry3_rank(drq1_rd_entry3_rank), | |
6607 | .drq1_rd_entry4_rank(drq1_rd_entry4_rank), | |
6608 | .drq1_rd_entry5_rank(drq1_rd_entry5_rank), | |
6609 | .drq1_rd_entry6_rank(drq1_rd_entry6_rank), | |
6610 | .drq1_rd_entry7_rank(drq1_rd_entry7_rank), | |
6611 | .drq1_wr_entry0_rank(drq1_wr_entry0_rank), | |
6612 | .drq1_wr_entry1_rank(drq1_wr_entry1_rank), | |
6613 | .drq1_wr_entry2_rank(drq1_wr_entry2_rank), | |
6614 | .drq1_wr_entry3_rank(drq1_wr_entry3_rank), | |
6615 | .drq1_wr_entry4_rank(drq1_wr_entry4_rank), | |
6616 | .drq1_wr_entry5_rank(drq1_wr_entry5_rank), | |
6617 | .drq1_wr_entry6_rank(drq1_wr_entry6_rank), | |
6618 | .drq1_wr_entry7_rank(drq1_wr_entry7_rank), | |
6619 | .drq1_rd_entry0_dimm(drq1_rd_entry0_dimm[2:0]), | |
6620 | .drq1_rd_entry1_dimm(drq1_rd_entry1_dimm[2:0]), | |
6621 | .drq1_rd_entry2_dimm(drq1_rd_entry2_dimm[2:0]), | |
6622 | .drq1_rd_entry3_dimm(drq1_rd_entry3_dimm[2:0]), | |
6623 | .drq1_rd_entry4_dimm(drq1_rd_entry4_dimm[2:0]), | |
6624 | .drq1_rd_entry5_dimm(drq1_rd_entry5_dimm[2:0]), | |
6625 | .drq1_rd_entry6_dimm(drq1_rd_entry6_dimm[2:0]), | |
6626 | .drq1_rd_entry7_dimm(drq1_rd_entry7_dimm[2:0]), | |
6627 | .drq1_wr_entry0_dimm(drq1_wr_entry0_dimm[2:0]), | |
6628 | .drq1_wr_entry1_dimm(drq1_wr_entry1_dimm[2:0]), | |
6629 | .drq1_wr_entry2_dimm(drq1_wr_entry2_dimm[2:0]), | |
6630 | .drq1_wr_entry3_dimm(drq1_wr_entry3_dimm[2:0]), | |
6631 | .drq1_wr_entry4_dimm(drq1_wr_entry4_dimm[2:0]), | |
6632 | .drq1_wr_entry5_dimm(drq1_wr_entry5_dimm[2:0]), | |
6633 | .drq1_wr_entry6_dimm(drq1_wr_entry6_dimm[2:0]), | |
6634 | .drq1_wr_entry7_dimm(drq1_wr_entry7_dimm[2:0]), | |
6635 | .drq1_rd_addr_picked(drq1_rd_addr_picked[9:0]), | |
6636 | .drq1_rdq_free(drq1_rdq_free), | |
6637 | .woq1_wdq_entry_free(woq1_wdq_entry_free[7:0]), | |
6638 | .drq1_rdq_full(drq1_rdq_full), | |
6639 | .drq1_empty(drq1_empty), | |
6640 | .drq1_rd_index_picked(drq1_rd_index_picked[2:0]), | |
6641 | .drq1_wr_index_picked(drq1_wr_index_picked[2:0]), | |
6642 | .drq1_wr_id_picked(drq1_wr_id_picked[2:0]), | |
6643 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[15:0]), | |
6644 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[15:0]), | |
6645 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[15:0]), | |
6646 | .woq1_wdq_rd(woq1_wdq_rd), | |
6647 | .drq1_rd_req(drq1_rd_req), | |
6648 | .drq1_wr_req(drq1_wr_req), | |
6649 | .woq_err_pdm_wr_incr(woq_err_pdm_wr_incr[15:0]), | |
6650 | .woq_err_pdm_wr_decr(woq_err_pdm_wr_decr[15:0]), | |
6651 | .drif1_raw_hazard(drif1_raw_hazard), | |
6652 | .l2if1_rd_req(l2if1_rd_req), | |
6653 | .l2if1_wr_req(l2if1_wr_req), | |
6654 | .drif1_cpu_wr_addr(drif1_cpu_wr_addr[2:0]), | |
6655 | .l2if1_wdq_in_cntr(l2if1_wdq_in_cntr[3:0]), | |
6656 | .l2b1_rd_rank_adr(l2b1_rd_rank_adr), | |
6657 | .l2b1_rd_dimm_adr(l2b1_rd_dimm_adr[2:0]), | |
6658 | .l2b1_rd_bank_adr(l2b1_rd_bank_adr[2:0]), | |
6659 | .l2b1_rd_addr_err(l2b1_rd_addr_err), | |
6660 | .l2b1_rd_addr_par(l2b1_rd_addr_par), | |
6661 | .l2b1_wr_rank_adr(l2b1_wr_rank_adr), | |
6662 | .l2b1_wr_dimm_adr(l2b1_wr_dimm_adr[2:0]), | |
6663 | .l2b1_wr_bank_adr(l2b1_wr_bank_adr[2:0]), | |
6664 | .l2b1_wr_addr_err(l2b1_wr_addr_err), | |
6665 | .l2b1_wr_addr_par(l2b1_wr_addr_par), | |
6666 | .rdpctl_drq1_clear_ent(rdpctl_drq1_clear_ent[7:0]), | |
6667 | .drif_drq1_clear_ent(drif_drq1_clear_ent[7:0]), | |
6668 | .drif1_rd_entry_picked(drif1_rd_entry_picked[7:0]), | |
6669 | .drif_wr_entry_picked(drif_wr_entry_picked[2:0]), | |
6670 | .drif_init(drif_init), | |
6671 | .drif_init_mcu_done(drif_init_mcu_done), | |
6672 | .drif_cmd_picked(drif_cmd_picked), | |
6673 | .drif_blk_new_openbank(drif_blk_new_openbank), | |
6674 | .drif_refresh_rank(drif_refresh_rank[3:0]), | |
6675 | .drif_rd_picked(drif_rd_picked), | |
6676 | .drif_wr_picked(drif_wr_picked), | |
6677 | .drif_stacked_dimm(drif_stacked_dimm), | |
6678 | .drif_sync_frame_req_l(drif_sync_frame_req_l), | |
6679 | .drif_sync_frame_req_early3_l(drif_sync_frame_req_early3_l), | |
6680 | .drif_single_channel_mode(drif_single_channel_mode), | |
6681 | .drif_pd_mode_pending(drif_pd_mode_pending), | |
6682 | .drif_err_fifo_empty(drif_err_fifo_empty), | |
6683 | .pdmc_rank_avail(pdmc_rank_avail[15:0]), | |
6684 | .drif_dimm_rd_available(drif_dimm_rd_available[7:0]), | |
6685 | .drif_dimm_wr_available(drif_dimm_wr_available[7:0]), | |
6686 | .drif_wr_bc_stall(drif_wr_bc_stall), | |
6687 | .drif_hw_selfrsh(drif_hw_selfrsh), | |
6688 | .fbdic_l0_state(fbdic_l0_state), | |
6689 | .fbdic_chnl_reset_error_mode(fbdic_chnl_reset_error_mode), | |
6690 | .drif_woq_free(drif_woq_free[1:0]), | |
6691 | .fbdic_clear_wrq_ent(fbdic_clear_wrq_ent), | |
6692 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
6693 | .fbdic_error_mode(fbdic_error_mode), | |
6694 | .tcu_aclk(tcu_aclk), | |
6695 | .tcu_bclk(tcu_bclk), | |
6696 | .tcu_scan_en(tcu_scan_en) | |
6697 | ); | |
6698 | ||
6699 | // Scrub address | |
6700 | assign drif_scrub_addr_in[31:0] = drif_scrub_addr[31:0] + 32'h1; | |
6701 | assign drif_scrub_addr_en = rdpctl_scrub_addrinc_en | drif_scrub_addr_incr; | |
6702 | assign drif_scrub_addr_clr = drif_scrub_addr_err; | |
6703 | ||
6704 | mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_32 ff_scrub_addr ( | |
6705 | .scan_in(ff_scrub_addr_scanin), | |
6706 | .scan_out(ff_scrub_addr_scanout), | |
6707 | .din(drif_scrub_addr_in[31:0]), | |
6708 | .dout(drif_scrub_addr[31:0]), | |
6709 | .en(drif_scrub_addr_en), | |
6710 | .clr(drif_scrub_addr_clr), | |
6711 | .l1clk(l1clk), | |
6712 | .siclk(siclk), | |
6713 | .soclk(soclk)); | |
6714 | ||
6715 | mcu_adrgen_ctl adrgen ( | |
6716 | .scan_in(adrgen_scanin), | |
6717 | .scan_out(adrgen_scanout), | |
6718 | .l1clk(l1clk), | |
6719 | .adrgen_rank(drif_scrub_rank_adr), | |
6720 | .adrgen_dimm(drif_scrub_dimm_adr[2:0]), | |
6721 | .adrgen_bank(drif_scrub_bank_adr[2:0]), | |
6722 | .adrgen_row_addr(drif_scrub_ras_adr[14:0]), | |
6723 | .adrgen_col_addr(drif_scrub_cas_adr[10:0]), | |
6724 | .adrgen_addr_err(drif_scrub_addr_err_out), | |
6725 | .adrgen_addr_parity(drif_scrub_addr_parity), | |
6726 | .addr_39to9(drif_scrub_addr[31:1]), | |
6727 | .addr_6to5({drif_scrub_addr[0],1'b0}), | |
6728 | .stacked_dimm(drif_stacked_dimm), | |
6729 | .addr_bank_low_sel(drif_addr_bank_low_sel), | |
6730 | .mem_type(drif_mem_type[1:0]), | |
6731 | .sngl_chnl_mode(drif_single_channel_mode), | |
6732 | .num_dimms(drif_num_dimms[2:0]), | |
6733 | .tcu_aclk(tcu_aclk), | |
6734 | .tcu_bclk(tcu_bclk), | |
6735 | .tcu_scan_en(tcu_scan_en) | |
6736 | ); | |
6737 | ||
6738 | assign drif_scrub_addr_err = drif_scrub_addr_err_out | drif_scrub_addr[31] & drif_single_channel_mode; | |
6739 | ||
6740 | assign drif_pd_mode_scrub_rank[15:0] = {{drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'hf, | |
6741 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'he, | |
6742 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'hd, | |
6743 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'hc, | |
6744 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'hb, | |
6745 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'ha, | |
6746 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h9, | |
6747 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h8, | |
6748 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h7, | |
6749 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h6, | |
6750 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h5, | |
6751 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h4, | |
6752 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h3, | |
6753 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h2, | |
6754 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h1, | |
6755 | {drif_scrub_rank_adr, drif_scrub_dimm_adr[2:0]} == 4'h0}; | |
6756 | assign drif_pd_mode_scrub_incr[15:0] = {16{drif_scrub_time}} & drif_pd_mode_scrub_rank[15:0]; | |
6757 | assign drif_pd_mode_scrub_decr[15:0] = {16{drif_scrub_picked}} & drif_pd_mode_scrub_rank[15:0]; | |
6758 | assign drif_scrub_rank_avail[15:0] = drif_pd_mode_scrub_rank[15:0] & pdmc_rank_avail[15:0] & | |
6759 | {drif_dimm_rd_available[7:0],drif_dimm_rd_available[7:0]}; | |
6760 | ||
6761 | // Power down mode counter: increment when xactions placed in error FIFO | |
6762 | assign drif_pd_mode_err_incr[15:0] = {16{rdpctl_err_fifo_enq}} & | |
6763 | {rdpctl_err_fifo_data[13:10] == 4'hf, | |
6764 | rdpctl_err_fifo_data[13:10] == 4'he, | |
6765 | rdpctl_err_fifo_data[13:10] == 4'hd, | |
6766 | rdpctl_err_fifo_data[13:10] == 4'hc, | |
6767 | rdpctl_err_fifo_data[13:10] == 4'hb, | |
6768 | rdpctl_err_fifo_data[13:10] == 4'ha, | |
6769 | rdpctl_err_fifo_data[13:10] == 4'h9, | |
6770 | rdpctl_err_fifo_data[13:10] == 4'h8, | |
6771 | rdpctl_err_fifo_data[13:10] == 4'h7, | |
6772 | rdpctl_err_fifo_data[13:10] == 4'h6, | |
6773 | rdpctl_err_fifo_data[13:10] == 4'h5, | |
6774 | rdpctl_err_fifo_data[13:10] == 4'h4, | |
6775 | rdpctl_err_fifo_data[13:10] == 4'h3, | |
6776 | rdpctl_err_fifo_data[13:10] == 4'h2, | |
6777 | rdpctl_err_fifo_data[13:10] == 4'h1, | |
6778 | rdpctl_err_fifo_data[13:10] == 4'h0}; | |
6779 | ||
6780 | // Power down mode counter: decrement on FIFO dequeue | |
6781 | assign drif_pd_mode_err_decr[15:0] = {16{drif_err_fifo_deq}} & drif_pd_mode_err_rank[15:0]; | |
6782 | ||
6783 | assign drif_pd_mode_err_rank[15:0] = {{drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'hf, | |
6784 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'he, | |
6785 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'hd, | |
6786 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'hc, | |
6787 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'hb, | |
6788 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'ha, | |
6789 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h9, | |
6790 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h8, | |
6791 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h7, | |
6792 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h6, | |
6793 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h5, | |
6794 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h4, | |
6795 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h3, | |
6796 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h2, | |
6797 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h1, | |
6798 | {drif_err_fifo_rank_adr, drif_err_fifo_dimm_adr[2:0]} == 4'h0}; | |
6799 | ||
6800 | assign drif_err_rank_avail[15:0] = drif_pd_mode_err_rank[15:0] & pdmc_rank_avail[15:0]; | |
6801 | ||
6802 | // | |
6803 | assign drif_pd_mode_pending = drif_pd_mode_exit_pending | drif_pd_mode_enter_pending; | |
6804 | assign drif_pd_mode_exit_pending = (|pdmc_pdx_pending[15:0]) & ~fbdic_error_mode & | |
6805 | (~drif_cmd_a_val & ~drif_cmd_a_val_d1 | drif_dram_dimm_a[2:0] != drif_pd_mode_exit_dimm[2:0]) & | |
6806 | (~drif_cmd_b_val & ~drif_cmd_b_val_d1 | drif_dram_dimm_b[2:0] != drif_pd_mode_exit_dimm[2:0]) & | |
6807 | (~drif_refresh_req_picked | drif_refresh_rank[2:0] != drif_pd_mode_exit_dimm[2:0]); | |
6808 | assign drif_pd_mode_enter_pending = (|pdmc_pde_pending[15:0]) & ~fbdic_error_mode & | |
6809 | (~drif_cmd_a_val & ~drif_cmd_a_val_d1 | drif_dram_dimm_a[2:0] != drif_pd_mode_enter_dimm[2:0]) & | |
6810 | (~drif_cmd_b_val & ~drif_cmd_b_val_d1 | drif_dram_dimm_b[2:0] != drif_pd_mode_enter_dimm[2:0]) & | |
6811 | (~drif_refresh_req_picked | drif_refresh_rank[2:0] != drif_pd_mode_enter_dimm[2:0]); | |
6812 | ||
6813 | assign drif_pdx_issued[15:0] = {16{~(drif_wdq_sel_d1 | drif_scrub_data_rden_en_d1) & | |
6814 | ~drif_cmd_c_val & ~drif_cmd_c_val_d1 & | |
6815 | drif_pd_mode_exit_pending & fbdic_sync_frame_req_l}} & | |
6816 | pdmc_pdx_pending_priority[15:0]; | |
6817 | assign drif_pde_issued[15:0] = {16{~(drif_wdq_sel_d1 | drif_scrub_data_rden_en_d1) & | |
6818 | ~drif_cmd_c_val & ~drif_cmd_c_val_d1 & | |
6819 | ~drif_pd_mode_exit_pending & drif_pd_mode_enter_pending & | |
6820 | fbdic_sync_frame_req_l}} & pdmc_pde_pending_priority[15:0]; | |
6821 | ||
6822 | assign {drif_pd_mode_exit_rank, drif_pd_mode_exit_dimm[2:0]} = pdmc_pdx_pending[0] ? 4'h0 : | |
6823 | pdmc_pdx_pending[1] ? 4'h1 : | |
6824 | pdmc_pdx_pending[2] ? 4'h2 : | |
6825 | pdmc_pdx_pending[3] ? 4'h3 : | |
6826 | pdmc_pdx_pending[4] ? 4'h4 : | |
6827 | pdmc_pdx_pending[5] ? 4'h5 : | |
6828 | pdmc_pdx_pending[6] ? 4'h6 : | |
6829 | pdmc_pdx_pending[7] ? 4'h7 : | |
6830 | pdmc_pdx_pending[8] ? 4'h8 : | |
6831 | pdmc_pdx_pending[9] ? 4'h9 : | |
6832 | pdmc_pdx_pending[10] ? 4'ha : | |
6833 | pdmc_pdx_pending[11] ? 4'hb : | |
6834 | pdmc_pdx_pending[12] ? 4'hc : | |
6835 | pdmc_pdx_pending[13] ? 4'hd : | |
6836 | pdmc_pdx_pending[14] ? 4'he : 4'hf; | |
6837 | ||
6838 | assign pdmc_pdx_pending_priority[15:0] = pdmc_pdx_pending[0] ? 16'h0001 : | |
6839 | pdmc_pdx_pending[1] ? 16'h0002 : | |
6840 | pdmc_pdx_pending[2] ? 16'h0004 : | |
6841 | pdmc_pdx_pending[3] ? 16'h0008 : | |
6842 | pdmc_pdx_pending[4] ? 16'h0010 : | |
6843 | pdmc_pdx_pending[5] ? 16'h0020 : | |
6844 | pdmc_pdx_pending[6] ? 16'h0040 : | |
6845 | pdmc_pdx_pending[7] ? 16'h0080 : | |
6846 | pdmc_pdx_pending[8] ? 16'h0100 : | |
6847 | pdmc_pdx_pending[9] ? 16'h0200 : | |
6848 | pdmc_pdx_pending[10] ? 16'h0400 : | |
6849 | pdmc_pdx_pending[11] ? 16'h0800 : | |
6850 | pdmc_pdx_pending[12] ? 16'h1000 : | |
6851 | pdmc_pdx_pending[13] ? 16'h2000 : | |
6852 | pdmc_pdx_pending[14] ? 16'h4000 : | |
6853 | pdmc_pdx_pending[15] ? 16'h8000 : 16'h0000; | |
6854 | ||
6855 | assign {drif_pd_mode_enter_rank, drif_pd_mode_enter_dimm[2:0]} = pdmc_pde_pending[0] ? 4'h0 : | |
6856 | pdmc_pde_pending[1] ? 4'h1 : | |
6857 | pdmc_pde_pending[2] ? 4'h2 : | |
6858 | pdmc_pde_pending[3] ? 4'h3 : | |
6859 | pdmc_pde_pending[4] ? 4'h4 : | |
6860 | pdmc_pde_pending[5] ? 4'h5 : | |
6861 | pdmc_pde_pending[6] ? 4'h6 : | |
6862 | pdmc_pde_pending[7] ? 4'h7 : | |
6863 | pdmc_pde_pending[8] ? 4'h8 : | |
6864 | pdmc_pde_pending[9] ? 4'h9 : | |
6865 | pdmc_pde_pending[10] ? 4'ha : | |
6866 | pdmc_pde_pending[11] ? 4'hb : | |
6867 | pdmc_pde_pending[12] ? 4'hc : | |
6868 | pdmc_pde_pending[13] ? 4'hd : | |
6869 | pdmc_pde_pending[14] ? 4'he : 4'hf; | |
6870 | ||
6871 | assign pdmc_pde_pending_priority[15:0] = pdmc_pde_pending[0] ? 16'h0001 : | |
6872 | pdmc_pde_pending[1] ? 16'h0002 : | |
6873 | pdmc_pde_pending[2] ? 16'h0004 : | |
6874 | pdmc_pde_pending[3] ? 16'h0008 : | |
6875 | pdmc_pde_pending[4] ? 16'h0010 : | |
6876 | pdmc_pde_pending[5] ? 16'h0020 : | |
6877 | pdmc_pde_pending[6] ? 16'h0040 : | |
6878 | pdmc_pde_pending[7] ? 16'h0080 : | |
6879 | pdmc_pde_pending[8] ? 16'h0100 : | |
6880 | pdmc_pde_pending[9] ? 16'h0200 : | |
6881 | pdmc_pde_pending[10] ? 16'h0400 : | |
6882 | pdmc_pde_pending[11] ? 16'h0800 : | |
6883 | pdmc_pde_pending[12] ? 16'h1000 : | |
6884 | pdmc_pde_pending[13] ? 16'h2000 : | |
6885 | pdmc_pde_pending[14] ? 16'h4000 : | |
6886 | pdmc_pde_pending[15] ? 16'h8000 : 16'h0000; | |
6887 | ||
6888 | assign drif_num_dimm_dec[7:0] = {8{drif_pd_mode_enable}} & | |
6889 | {{7'h0, drif_num_dimms[2:0] == 3'h1 } | | |
6890 | {6'h0, {2{drif_num_dimms[2:0] == 3'h2}}} | | |
6891 | {5'h0, {3{drif_num_dimms[2:0] == 3'h3}}} | | |
6892 | {4'h0, {4{drif_num_dimms[2:0] == 3'h4}}} | | |
6893 | {3'h0, {5{drif_num_dimms[2:0] == 3'h5}}} | | |
6894 | {2'h0, {6{drif_num_dimms[2:0] == 3'h6}}} | | |
6895 | {1'h0, {7{drif_num_dimms[2:0] == 3'h7}}} | | |
6896 | {8{drif_num_dimms[2:0] == 3'h0}}}; | |
6897 | ||
6898 | assign drif_pdmc_enable[15:8] = drif_stacked_dimm ? drif_num_dimm_dec[7:0] : 8'h0; | |
6899 | assign drif_pdmc_enable[7:0] = drif_num_dimm_dec[7:0]; | |
6900 | ||
6901 | assign drif_refresh_rank_dec[15:0] = {drif_refresh_rank[3:0] == 4'hf, | |
6902 | drif_refresh_rank[3:0] == 4'he, | |
6903 | drif_refresh_rank[3:0] == 4'hd, | |
6904 | drif_refresh_rank[3:0] == 4'hc, | |
6905 | drif_refresh_rank[3:0] == 4'hb, | |
6906 | drif_refresh_rank[3:0] == 4'ha, | |
6907 | drif_refresh_rank[3:0] == 4'h9, | |
6908 | drif_refresh_rank[3:0] == 4'h8, | |
6909 | drif_refresh_rank[3:0] == 4'h7, | |
6910 | drif_refresh_rank[3:0] == 4'h6, | |
6911 | drif_refresh_rank[3:0] == 4'h5, | |
6912 | drif_refresh_rank[3:0] == 4'h4, | |
6913 | drif_refresh_rank[3:0] == 4'h3, | |
6914 | drif_refresh_rank[3:0] == 4'h2, | |
6915 | drif_refresh_rank[3:0] == 4'h1, | |
6916 | drif_refresh_rank[3:0] == 4'h0}; | |
6917 | ||
6918 | assign drif_refresh_mode[15:0] = {16{(|drif_mcu_state[4:2])}} & drif_refresh_rank_dec[15:0] | {16{(|drif_mcu_state[6:5]) | drif_hw_selfrsh}}; | |
6919 | ||
6920 | // block transactions to opposite rank of DIMM with pending Power Down mode transaction | |
6921 | assign pdmc_rank_avail[15:0] = pdmc_rank_avail_out[15:0] & | |
6922 | {~pdmc_pde_pending[7:0],~pdmc_pde_pending[15:8]} & | |
6923 | {~pdmc_pdx_pending[7:0],~pdmc_pdx_pending[15:8]}; | |
6924 | ||
6925 | // Power down mode counters | |
6926 | mcu_pdmc_ctl pdmc0 ( | |
6927 | .scan_in(pdmc0_scanin), | |
6928 | .scan_out(pdmc0_scanout), | |
6929 | .l1clk(l1clk), | |
6930 | .pdmc_pde_pending(pdmc_pde_pending[0]), | |
6931 | .pdmc_pdx_pending(pdmc_pdx_pending[0]), | |
6932 | .pdmc_rank_avail(pdmc_rank_avail_out[0]), | |
6933 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[0]), | |
6934 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[0]), | |
6935 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[0]), | |
6936 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[0]), | |
6937 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[0]), | |
6938 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[0]), | |
6939 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[0]), | |
6940 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[0]), | |
6941 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[0]), | |
6942 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[0]), | |
6943 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[0]), | |
6944 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[0]), | |
6945 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[0]), | |
6946 | .drif_pdx_issued(drif_pdx_issued[0]), | |
6947 | .drif_pde_issued(drif_pde_issued[0]), | |
6948 | .drif_pdmc_enable(drif_pdmc_enable[0]), | |
6949 | .drif_refresh_mode(drif_refresh_mode[0]), | |
6950 | .fbdic_l0_state(fbdic_l0_state), | |
6951 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
6952 | .drif_pdmc_idle(drif_pdmc_idle), | |
6953 | .dal_reg(dal_reg[4:0]), | |
6954 | .ral_reg(ral_reg[4:0]), | |
6955 | .tcu_aclk(tcu_aclk), | |
6956 | .tcu_bclk(tcu_bclk), | |
6957 | .tcu_scan_en(tcu_scan_en) | |
6958 | ); | |
6959 | ||
6960 | mcu_pdmc_ctl pdmc1 ( | |
6961 | .scan_in(pdmc1_scanin), | |
6962 | .scan_out(pdmc1_scanout), | |
6963 | .l1clk(l1clk), | |
6964 | .pdmc_pde_pending(pdmc_pde_pending[1]), | |
6965 | .pdmc_pdx_pending(pdmc_pdx_pending[1]), | |
6966 | .pdmc_rank_avail(pdmc_rank_avail_out[1]), | |
6967 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[1]), | |
6968 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[1]), | |
6969 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[1]), | |
6970 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[1]), | |
6971 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[1]), | |
6972 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[1]), | |
6973 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[1]), | |
6974 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[1]), | |
6975 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[1]), | |
6976 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[1]), | |
6977 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[1]), | |
6978 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[1]), | |
6979 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[1]), | |
6980 | .drif_pdx_issued(drif_pdx_issued[1]), | |
6981 | .drif_pde_issued(drif_pde_issued[1]), | |
6982 | .drif_pdmc_enable(drif_pdmc_enable[1]), | |
6983 | .drif_refresh_mode(drif_refresh_mode[1]), | |
6984 | .fbdic_l0_state(fbdic_l0_state), | |
6985 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
6986 | .drif_pdmc_idle(drif_pdmc_idle), | |
6987 | .dal_reg(dal_reg[4:0]), | |
6988 | .ral_reg(ral_reg[4:0]), | |
6989 | .tcu_aclk(tcu_aclk), | |
6990 | .tcu_bclk(tcu_bclk), | |
6991 | .tcu_scan_en(tcu_scan_en) | |
6992 | ); | |
6993 | ||
6994 | mcu_pdmc_ctl pdmc2 ( | |
6995 | .scan_in(pdmc2_scanin), | |
6996 | .scan_out(pdmc2_scanout), | |
6997 | .l1clk(l1clk), | |
6998 | .pdmc_pde_pending(pdmc_pde_pending[2]), | |
6999 | .pdmc_pdx_pending(pdmc_pdx_pending[2]), | |
7000 | .pdmc_rank_avail(pdmc_rank_avail_out[2]), | |
7001 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[2]), | |
7002 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[2]), | |
7003 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[2]), | |
7004 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[2]), | |
7005 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[2]), | |
7006 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[2]), | |
7007 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[2]), | |
7008 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[2]), | |
7009 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[2]), | |
7010 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[2]), | |
7011 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[2]), | |
7012 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[2]), | |
7013 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[2]), | |
7014 | .drif_pdx_issued(drif_pdx_issued[2]), | |
7015 | .drif_pde_issued(drif_pde_issued[2]), | |
7016 | .drif_pdmc_enable(drif_pdmc_enable[2]), | |
7017 | .drif_refresh_mode(drif_refresh_mode[2]), | |
7018 | .fbdic_l0_state(fbdic_l0_state), | |
7019 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7020 | .drif_pdmc_idle(drif_pdmc_idle), | |
7021 | .dal_reg(dal_reg[4:0]), | |
7022 | .ral_reg(ral_reg[4:0]), | |
7023 | .tcu_aclk(tcu_aclk), | |
7024 | .tcu_bclk(tcu_bclk), | |
7025 | .tcu_scan_en(tcu_scan_en) | |
7026 | ); | |
7027 | ||
7028 | mcu_pdmc_ctl pdmc3 ( | |
7029 | .scan_in(pdmc3_scanin), | |
7030 | .scan_out(pdmc3_scanout), | |
7031 | .l1clk(l1clk), | |
7032 | .pdmc_pde_pending(pdmc_pde_pending[3]), | |
7033 | .pdmc_pdx_pending(pdmc_pdx_pending[3]), | |
7034 | .pdmc_rank_avail(pdmc_rank_avail_out[3]), | |
7035 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[3]), | |
7036 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[3]), | |
7037 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[3]), | |
7038 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[3]), | |
7039 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[3]), | |
7040 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[3]), | |
7041 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[3]), | |
7042 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[3]), | |
7043 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[3]), | |
7044 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[3]), | |
7045 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[3]), | |
7046 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[3]), | |
7047 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[3]), | |
7048 | .drif_pdx_issued(drif_pdx_issued[3]), | |
7049 | .drif_pde_issued(drif_pde_issued[3]), | |
7050 | .drif_pdmc_enable(drif_pdmc_enable[3]), | |
7051 | .drif_refresh_mode(drif_refresh_mode[3]), | |
7052 | .fbdic_l0_state(fbdic_l0_state), | |
7053 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7054 | .drif_pdmc_idle(drif_pdmc_idle), | |
7055 | .dal_reg(dal_reg[4:0]), | |
7056 | .ral_reg(ral_reg[4:0]), | |
7057 | .tcu_aclk(tcu_aclk), | |
7058 | .tcu_bclk(tcu_bclk), | |
7059 | .tcu_scan_en(tcu_scan_en) | |
7060 | ); | |
7061 | ||
7062 | mcu_pdmchi_ctl pdmc4 ( | |
7063 | .scan_in(pdmc4_scanin), | |
7064 | .scan_out(pdmc4_scanout), | |
7065 | .l1clk(l1clk), | |
7066 | .pdmc_pde_pending(pdmc_pde_pending[4]), | |
7067 | .pdmc_pdx_pending(pdmc_pdx_pending[4]), | |
7068 | .pdmc_rank_avail(pdmc_rank_avail_out[4]), | |
7069 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[4]), | |
7070 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[4]), | |
7071 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[4]), | |
7072 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[4]), | |
7073 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[4]), | |
7074 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[4]), | |
7075 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[4]), | |
7076 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[4]), | |
7077 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[4]), | |
7078 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[4]), | |
7079 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[4]), | |
7080 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[4]), | |
7081 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[4]), | |
7082 | .drif_pdx_issued(drif_pdx_issued[4]), | |
7083 | .drif_pde_issued(drif_pde_issued[4]), | |
7084 | .drif_pdmc_enable(drif_pdmc_enable[4]), | |
7085 | .drif_refresh_mode(drif_refresh_mode[4]), | |
7086 | .fbdic_l0_state(fbdic_l0_state), | |
7087 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7088 | .dal_reg(dal_reg[4:0]), | |
7089 | .ral_reg(ral_reg[4:0]), | |
7090 | .tcu_aclk(tcu_aclk), | |
7091 | .tcu_bclk(tcu_bclk), | |
7092 | .tcu_scan_en(tcu_scan_en) | |
7093 | ); | |
7094 | ||
7095 | mcu_pdmchi_ctl pdmc5 ( | |
7096 | .scan_in(pdmc5_scanin), | |
7097 | .scan_out(pdmc5_scanout), | |
7098 | .l1clk(l1clk), | |
7099 | .pdmc_pde_pending(pdmc_pde_pending[5]), | |
7100 | .pdmc_pdx_pending(pdmc_pdx_pending[5]), | |
7101 | .pdmc_rank_avail(pdmc_rank_avail_out[5]), | |
7102 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[5]), | |
7103 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[5]), | |
7104 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[5]), | |
7105 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[5]), | |
7106 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[5]), | |
7107 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[5]), | |
7108 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[5]), | |
7109 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[5]), | |
7110 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[5]), | |
7111 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[5]), | |
7112 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[5]), | |
7113 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[5]), | |
7114 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[5]), | |
7115 | .drif_pdx_issued(drif_pdx_issued[5]), | |
7116 | .drif_pde_issued(drif_pde_issued[5]), | |
7117 | .drif_pdmc_enable(drif_pdmc_enable[5]), | |
7118 | .drif_refresh_mode(drif_refresh_mode[5]), | |
7119 | .fbdic_l0_state(fbdic_l0_state), | |
7120 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7121 | .dal_reg(dal_reg[4:0]), | |
7122 | .ral_reg(ral_reg[4:0]), | |
7123 | .tcu_aclk(tcu_aclk), | |
7124 | .tcu_bclk(tcu_bclk), | |
7125 | .tcu_scan_en(tcu_scan_en) | |
7126 | ); | |
7127 | ||
7128 | mcu_pdmchi_ctl pdmc6 ( | |
7129 | .scan_in(pdmc6_scanin), | |
7130 | .scan_out(pdmc6_scanout), | |
7131 | .l1clk(l1clk), | |
7132 | .pdmc_pde_pending(pdmc_pde_pending[6]), | |
7133 | .pdmc_pdx_pending(pdmc_pdx_pending[6]), | |
7134 | .pdmc_rank_avail(pdmc_rank_avail_out[6]), | |
7135 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[6]), | |
7136 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[6]), | |
7137 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[6]), | |
7138 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[6]), | |
7139 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[6]), | |
7140 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[6]), | |
7141 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[6]), | |
7142 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[6]), | |
7143 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[6]), | |
7144 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[6]), | |
7145 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[6]), | |
7146 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[6]), | |
7147 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[6]), | |
7148 | .drif_pdx_issued(drif_pdx_issued[6]), | |
7149 | .drif_pde_issued(drif_pde_issued[6]), | |
7150 | .drif_pdmc_enable(drif_pdmc_enable[6]), | |
7151 | .drif_refresh_mode(drif_refresh_mode[6]), | |
7152 | .fbdic_l0_state(fbdic_l0_state), | |
7153 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7154 | .dal_reg(dal_reg[4:0]), | |
7155 | .ral_reg(ral_reg[4:0]), | |
7156 | .tcu_aclk(tcu_aclk), | |
7157 | .tcu_bclk(tcu_bclk), | |
7158 | .tcu_scan_en(tcu_scan_en) | |
7159 | ); | |
7160 | ||
7161 | mcu_pdmchi_ctl pdmc7 ( | |
7162 | .scan_in(pdmc7_scanin), | |
7163 | .scan_out(pdmc7_scanout), | |
7164 | .l1clk(l1clk), | |
7165 | .pdmc_pde_pending(pdmc_pde_pending[7]), | |
7166 | .pdmc_pdx_pending(pdmc_pdx_pending[7]), | |
7167 | .pdmc_rank_avail(pdmc_rank_avail_out[7]), | |
7168 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[7]), | |
7169 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[7]), | |
7170 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[7]), | |
7171 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[7]), | |
7172 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[7]), | |
7173 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[7]), | |
7174 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[7]), | |
7175 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[7]), | |
7176 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[7]), | |
7177 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[7]), | |
7178 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[7]), | |
7179 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[7]), | |
7180 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[7]), | |
7181 | .drif_pdx_issued(drif_pdx_issued[7]), | |
7182 | .drif_pde_issued(drif_pde_issued[7]), | |
7183 | .drif_pdmc_enable(drif_pdmc_enable[7]), | |
7184 | .drif_refresh_mode(drif_refresh_mode[7]), | |
7185 | .fbdic_l0_state(fbdic_l0_state), | |
7186 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7187 | .dal_reg(dal_reg[4:0]), | |
7188 | .ral_reg(ral_reg[4:0]), | |
7189 | .tcu_aclk(tcu_aclk), | |
7190 | .tcu_bclk(tcu_bclk), | |
7191 | .tcu_scan_en(tcu_scan_en) | |
7192 | ); | |
7193 | ||
7194 | mcu_pdmchi_ctl pdmc8 ( | |
7195 | .scan_in(pdmc8_scanin), | |
7196 | .scan_out(pdmc8_scanout), | |
7197 | .l1clk(l1clk), | |
7198 | .pdmc_pde_pending(pdmc_pde_pending[8]), | |
7199 | .pdmc_pdx_pending(pdmc_pdx_pending[8]), | |
7200 | .pdmc_rank_avail(pdmc_rank_avail_out[8]), | |
7201 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[8]), | |
7202 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[8]), | |
7203 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[8]), | |
7204 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[8]), | |
7205 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[8]), | |
7206 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[8]), | |
7207 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[8]), | |
7208 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[8]), | |
7209 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[8]), | |
7210 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[8]), | |
7211 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[8]), | |
7212 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[8]), | |
7213 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[8]), | |
7214 | .drif_pdx_issued(drif_pdx_issued[8]), | |
7215 | .drif_pde_issued(drif_pde_issued[8]), | |
7216 | .drif_pdmc_enable(drif_pdmc_enable[8]), | |
7217 | .drif_refresh_mode(drif_refresh_mode[8]), | |
7218 | .fbdic_l0_state(fbdic_l0_state), | |
7219 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7220 | .dal_reg(dal_reg[4:0]), | |
7221 | .ral_reg(ral_reg[4:0]), | |
7222 | .tcu_aclk(tcu_aclk), | |
7223 | .tcu_bclk(tcu_bclk), | |
7224 | .tcu_scan_en(tcu_scan_en) | |
7225 | ); | |
7226 | ||
7227 | mcu_pdmchi_ctl pdmc9 ( | |
7228 | .scan_in(pdmc9_scanin), | |
7229 | .scan_out(pdmc9_scanout), | |
7230 | .l1clk(l1clk), | |
7231 | .pdmc_pde_pending(pdmc_pde_pending[9]), | |
7232 | .pdmc_pdx_pending(pdmc_pdx_pending[9]), | |
7233 | .pdmc_rank_avail(pdmc_rank_avail_out[9]), | |
7234 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[9]), | |
7235 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[9]), | |
7236 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[9]), | |
7237 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[9]), | |
7238 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[9]), | |
7239 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[9]), | |
7240 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[9]), | |
7241 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[9]), | |
7242 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[9]), | |
7243 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[9]), | |
7244 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[9]), | |
7245 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[9]), | |
7246 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[9]), | |
7247 | .drif_pdx_issued(drif_pdx_issued[9]), | |
7248 | .drif_pde_issued(drif_pde_issued[9]), | |
7249 | .drif_pdmc_enable(drif_pdmc_enable[9]), | |
7250 | .drif_refresh_mode(drif_refresh_mode[9]), | |
7251 | .fbdic_l0_state(fbdic_l0_state), | |
7252 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7253 | .dal_reg(dal_reg[4:0]), | |
7254 | .ral_reg(ral_reg[4:0]), | |
7255 | .tcu_aclk(tcu_aclk), | |
7256 | .tcu_bclk(tcu_bclk), | |
7257 | .tcu_scan_en(tcu_scan_en) | |
7258 | ); | |
7259 | ||
7260 | mcu_pdmchi_ctl pdmc10 ( | |
7261 | .scan_in(pdmc10_scanin), | |
7262 | .scan_out(pdmc10_scanout), | |
7263 | .l1clk(l1clk), | |
7264 | .pdmc_pde_pending(pdmc_pde_pending[10]), | |
7265 | .pdmc_pdx_pending(pdmc_pdx_pending[10]), | |
7266 | .pdmc_rank_avail(pdmc_rank_avail_out[10]), | |
7267 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[10]), | |
7268 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[10]), | |
7269 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[10]), | |
7270 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[10]), | |
7271 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[10]), | |
7272 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[10]), | |
7273 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[10]), | |
7274 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[10]), | |
7275 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[10]), | |
7276 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[10]), | |
7277 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[10]), | |
7278 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[10]), | |
7279 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[10]), | |
7280 | .drif_pdx_issued(drif_pdx_issued[10]), | |
7281 | .drif_pde_issued(drif_pde_issued[10]), | |
7282 | .drif_pdmc_enable(drif_pdmc_enable[10]), | |
7283 | .drif_refresh_mode(drif_refresh_mode[10]), | |
7284 | .fbdic_l0_state(fbdic_l0_state), | |
7285 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7286 | .dal_reg(dal_reg[4:0]), | |
7287 | .ral_reg(ral_reg[4:0]), | |
7288 | .tcu_aclk(tcu_aclk), | |
7289 | .tcu_bclk(tcu_bclk), | |
7290 | .tcu_scan_en(tcu_scan_en) | |
7291 | ); | |
7292 | ||
7293 | mcu_pdmchi_ctl pdmc11 ( | |
7294 | .scan_in(pdmc11_scanin), | |
7295 | .scan_out(pdmc11_scanout), | |
7296 | .l1clk(l1clk), | |
7297 | .pdmc_pde_pending(pdmc_pde_pending[11]), | |
7298 | .pdmc_pdx_pending(pdmc_pdx_pending[11]), | |
7299 | .pdmc_rank_avail(pdmc_rank_avail_out[11]), | |
7300 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[11]), | |
7301 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[11]), | |
7302 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[11]), | |
7303 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[11]), | |
7304 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[11]), | |
7305 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[11]), | |
7306 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[11]), | |
7307 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[11]), | |
7308 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[11]), | |
7309 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[11]), | |
7310 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[11]), | |
7311 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[11]), | |
7312 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[11]), | |
7313 | .drif_pdx_issued(drif_pdx_issued[11]), | |
7314 | .drif_pde_issued(drif_pde_issued[11]), | |
7315 | .drif_pdmc_enable(drif_pdmc_enable[11]), | |
7316 | .drif_refresh_mode(drif_refresh_mode[11]), | |
7317 | .fbdic_l0_state(fbdic_l0_state), | |
7318 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7319 | .dal_reg(dal_reg[4:0]), | |
7320 | .ral_reg(ral_reg[4:0]), | |
7321 | .tcu_aclk(tcu_aclk), | |
7322 | .tcu_bclk(tcu_bclk), | |
7323 | .tcu_scan_en(tcu_scan_en) | |
7324 | ); | |
7325 | ||
7326 | mcu_pdmchi_ctl pdmc12 ( | |
7327 | .scan_in(pdmc12_scanin), | |
7328 | .scan_out(pdmc12_scanout), | |
7329 | .l1clk(l1clk), | |
7330 | .pdmc_pde_pending(pdmc_pde_pending[12]), | |
7331 | .pdmc_pdx_pending(pdmc_pdx_pending[12]), | |
7332 | .pdmc_rank_avail(pdmc_rank_avail_out[12]), | |
7333 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[12]), | |
7334 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[12]), | |
7335 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[12]), | |
7336 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[12]), | |
7337 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[12]), | |
7338 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[12]), | |
7339 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[12]), | |
7340 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[12]), | |
7341 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[12]), | |
7342 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[12]), | |
7343 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[12]), | |
7344 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[12]), | |
7345 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[12]), | |
7346 | .drif_pdx_issued(drif_pdx_issued[12]), | |
7347 | .drif_pde_issued(drif_pde_issued[12]), | |
7348 | .drif_pdmc_enable(drif_pdmc_enable[12]), | |
7349 | .drif_refresh_mode(drif_refresh_mode[12]), | |
7350 | .fbdic_l0_state(fbdic_l0_state), | |
7351 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7352 | .dal_reg(dal_reg[4:0]), | |
7353 | .ral_reg(ral_reg[4:0]), | |
7354 | .tcu_aclk(tcu_aclk), | |
7355 | .tcu_bclk(tcu_bclk), | |
7356 | .tcu_scan_en(tcu_scan_en) | |
7357 | ); | |
7358 | ||
7359 | mcu_pdmchi_ctl pdmc13 ( | |
7360 | .scan_in(pdmc13_scanin), | |
7361 | .scan_out(pdmc13_scanout), | |
7362 | .l1clk(l1clk), | |
7363 | .pdmc_pde_pending(pdmc_pde_pending[13]), | |
7364 | .pdmc_pdx_pending(pdmc_pdx_pending[13]), | |
7365 | .pdmc_rank_avail(pdmc_rank_avail_out[13]), | |
7366 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[13]), | |
7367 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[13]), | |
7368 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[13]), | |
7369 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[13]), | |
7370 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[13]), | |
7371 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[13]), | |
7372 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[13]), | |
7373 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[13]), | |
7374 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[13]), | |
7375 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[13]), | |
7376 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[13]), | |
7377 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[13]), | |
7378 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[13]), | |
7379 | .drif_pdx_issued(drif_pdx_issued[13]), | |
7380 | .drif_pde_issued(drif_pde_issued[13]), | |
7381 | .drif_pdmc_enable(drif_pdmc_enable[13]), | |
7382 | .drif_refresh_mode(drif_refresh_mode[13]), | |
7383 | .fbdic_l0_state(fbdic_l0_state), | |
7384 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7385 | .dal_reg(dal_reg[4:0]), | |
7386 | .ral_reg(ral_reg[4:0]), | |
7387 | .tcu_aclk(tcu_aclk), | |
7388 | .tcu_bclk(tcu_bclk), | |
7389 | .tcu_scan_en(tcu_scan_en) | |
7390 | ); | |
7391 | ||
7392 | mcu_pdmchi_ctl pdmc14 ( | |
7393 | .scan_in(pdmc14_scanin), | |
7394 | .scan_out(pdmc14_scanout), | |
7395 | .l1clk(l1clk), | |
7396 | .pdmc_pde_pending(pdmc_pde_pending[14]), | |
7397 | .pdmc_pdx_pending(pdmc_pdx_pending[14]), | |
7398 | .pdmc_rank_avail(pdmc_rank_avail_out[14]), | |
7399 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[14]), | |
7400 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[14]), | |
7401 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[14]), | |
7402 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[14]), | |
7403 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[14]), | |
7404 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[14]), | |
7405 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[14]), | |
7406 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[14]), | |
7407 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[14]), | |
7408 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[14]), | |
7409 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[14]), | |
7410 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[14]), | |
7411 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[14]), | |
7412 | .drif_pdx_issued(drif_pdx_issued[14]), | |
7413 | .drif_pde_issued(drif_pde_issued[14]), | |
7414 | .drif_pdmc_enable(drif_pdmc_enable[14]), | |
7415 | .drif_refresh_mode(drif_refresh_mode[14]), | |
7416 | .fbdic_l0_state(fbdic_l0_state), | |
7417 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7418 | .dal_reg(dal_reg[4:0]), | |
7419 | .ral_reg(ral_reg[4:0]), | |
7420 | .tcu_aclk(tcu_aclk), | |
7421 | .tcu_bclk(tcu_bclk), | |
7422 | .tcu_scan_en(tcu_scan_en) | |
7423 | ); | |
7424 | ||
7425 | mcu_pdmchi_ctl pdmc15 ( | |
7426 | .scan_in(pdmc15_scanin), | |
7427 | .scan_out(pdmc15_scanout), | |
7428 | .l1clk(l1clk), | |
7429 | .pdmc_pde_pending(pdmc_pde_pending[15]), | |
7430 | .pdmc_pdx_pending(pdmc_pdx_pending[15]), | |
7431 | .pdmc_rank_avail(pdmc_rank_avail_out[15]), | |
7432 | .drq0_pd_mode_rd_incr(drq0_pd_mode_rd_incr[15]), | |
7433 | .drq1_pd_mode_rd_incr(drq1_pd_mode_rd_incr[15]), | |
7434 | .drq0_pd_mode_wr_incr(drq0_pd_mode_wr_incr[15]), | |
7435 | .drq1_pd_mode_wr_incr(drq1_pd_mode_wr_incr[15]), | |
7436 | .drif_pd_mode_scrub_incr(drif_pd_mode_scrub_incr[15]), | |
7437 | .drif_pd_mode_err_incr(drif_pd_mode_err_incr[15]), | |
7438 | .drq0_pd_mode_rd_decr(drq0_pd_mode_rd_decr[15]), | |
7439 | .drq1_pd_mode_rd_decr(drq1_pd_mode_rd_decr[15]), | |
7440 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[15]), | |
7441 | .woq_pd_mode_wr_err_decr(woq_err_pdm_wr_decr[15]), | |
7442 | .woq_pd_mode_wr_err_incr(woq_err_pdm_wr_incr[15]), | |
7443 | .drif_pd_mode_scrub_decr(drif_pd_mode_scrub_decr[15]), | |
7444 | .drif_pd_mode_err_decr(drif_pd_mode_err_decr[15]), | |
7445 | .drif_pdx_issued(drif_pdx_issued[15]), | |
7446 | .drif_pde_issued(drif_pde_issued[15]), | |
7447 | .drif_pdmc_enable(drif_pdmc_enable[15]), | |
7448 | .drif_refresh_mode(drif_refresh_mode[15]), | |
7449 | .fbdic_l0_state(fbdic_l0_state), | |
7450 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
7451 | .dal_reg(dal_reg[4:0]), | |
7452 | .ral_reg(ral_reg[4:0]), | |
7453 | .tcu_aclk(tcu_aclk), | |
7454 | .tcu_bclk(tcu_bclk), | |
7455 | .tcu_scan_en(tcu_scan_en) | |
7456 | ); | |
7457 | ||
7458 | ||
7459 | assign drif_pdmc_idle = drif_pdmc_idle_d0 & ~drif_pdmc_idle_d1; | |
7460 | assign drif_pdmc_idle_d0 = drif_mcu_idle & ~drq0_rd_req & ~drq0_wr_req & | |
7461 | ~drq1_rd_req & ~drq1_wr_req & ~drif_scrub_time & | |
7462 | ~rdpctl_err_fifo_enq; | |
7463 | assign drif_mcu_idle = drq0_empty & drq1_empty & woq_empty & drif_err_fifo_empty & | |
7464 | ~(drif_scrub_read_pending | drif_scrub_read_outstanding); | |
7465 | ||
7466 | // spare gates | |
7467 | //spare_ctl_macro spares (num=49) ( | |
7468 | // .scan_in(spares_scanin), | |
7469 | // .scan_out(spares_scanout), | |
7470 | // .l1clk(l1clk) | |
7471 | //); | |
7472 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
7473 | .siclk(siclk), | |
7474 | .soclk(soclk), | |
7475 | .si(si_0), | |
7476 | .so(so_0), | |
7477 | .d(drif_pdmc_idle_d0), | |
7478 | .q(drif_pdmc_idle_d1)); | |
7479 | assign si_0 = spares_scanin; | |
7480 | ||
7481 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
7482 | .out(spare0_buf_32x_unused)); | |
7483 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
7484 | .in1(1'b1), | |
7485 | .in2(1'b1), | |
7486 | .out(spare0_nand3_8x_unused)); | |
7487 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
7488 | .out(spare0_inv_8x_unused)); | |
7489 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
7490 | .in01(1'b1), | |
7491 | .in10(1'b1), | |
7492 | .in11(1'b1), | |
7493 | .out(spare0_aoi22_4x_unused)); | |
7494 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
7495 | .out(spare0_buf_8x_unused)); | |
7496 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
7497 | .in01(1'b1), | |
7498 | .in10(1'b1), | |
7499 | .in11(1'b1), | |
7500 | .out(spare0_oai22_4x_unused)); | |
7501 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
7502 | .out(spare0_inv_16x_unused)); | |
7503 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
7504 | .in1(1'b1), | |
7505 | .out(spare0_nand2_16x_unused)); | |
7506 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
7507 | .in1(1'b0), | |
7508 | .in2(1'b0), | |
7509 | .out(spare0_nor3_4x_unused)); | |
7510 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
7511 | .in1(1'b1), | |
7512 | .out(spare0_nand2_8x_unused)); | |
7513 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
7514 | .out(spare0_buf_16x_unused)); | |
7515 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
7516 | .in1(1'b0), | |
7517 | .out(spare0_nor2_16x_unused)); | |
7518 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
7519 | .out(spare0_inv_32x_unused)); | |
7520 | ||
7521 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
7522 | .siclk(siclk), | |
7523 | .soclk(soclk), | |
7524 | .si(si_1), | |
7525 | .so(so_1), | |
7526 | .d(1'b0), | |
7527 | .q(spare1_flop_unused)); | |
7528 | assign si_1 = so_0; | |
7529 | ||
7530 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
7531 | .out(spare1_buf_32x_unused)); | |
7532 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
7533 | .in1(1'b1), | |
7534 | .in2(1'b1), | |
7535 | .out(spare1_nand3_8x_unused)); | |
7536 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
7537 | .out(spare1_inv_8x_unused)); | |
7538 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
7539 | .in01(1'b1), | |
7540 | .in10(1'b1), | |
7541 | .in11(1'b1), | |
7542 | .out(spare1_aoi22_4x_unused)); | |
7543 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
7544 | .out(spare1_buf_8x_unused)); | |
7545 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
7546 | .in01(1'b1), | |
7547 | .in10(1'b1), | |
7548 | .in11(1'b1), | |
7549 | .out(spare1_oai22_4x_unused)); | |
7550 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
7551 | .out(spare1_inv_16x_unused)); | |
7552 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
7553 | .in1(1'b1), | |
7554 | .out(spare1_nand2_16x_unused)); | |
7555 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
7556 | .in1(1'b0), | |
7557 | .in2(1'b0), | |
7558 | .out(spare1_nor3_4x_unused)); | |
7559 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
7560 | .in1(1'b1), | |
7561 | .out(spare1_nand2_8x_unused)); | |
7562 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
7563 | .out(spare1_buf_16x_unused)); | |
7564 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
7565 | .in1(1'b0), | |
7566 | .out(spare1_nor2_16x_unused)); | |
7567 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
7568 | .out(spare1_inv_32x_unused)); | |
7569 | ||
7570 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
7571 | .siclk(siclk), | |
7572 | .soclk(soclk), | |
7573 | .si(si_2), | |
7574 | .so(so_2), | |
7575 | .d(1'b0), | |
7576 | .q(spare2_flop_unused)); | |
7577 | assign si_2 = so_1; | |
7578 | ||
7579 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
7580 | .out(spare2_buf_32x_unused)); | |
7581 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
7582 | .in1(1'b1), | |
7583 | .in2(1'b1), | |
7584 | .out(spare2_nand3_8x_unused)); | |
7585 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
7586 | .out(spare2_inv_8x_unused)); | |
7587 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
7588 | .in01(1'b1), | |
7589 | .in10(1'b1), | |
7590 | .in11(1'b1), | |
7591 | .out(spare2_aoi22_4x_unused)); | |
7592 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
7593 | .out(spare2_buf_8x_unused)); | |
7594 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
7595 | .in01(1'b1), | |
7596 | .in10(1'b1), | |
7597 | .in11(1'b1), | |
7598 | .out(spare2_oai22_4x_unused)); | |
7599 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
7600 | .out(spare2_inv_16x_unused)); | |
7601 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
7602 | .in1(1'b1), | |
7603 | .out(spare2_nand2_16x_unused)); | |
7604 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
7605 | .in1(1'b0), | |
7606 | .in2(1'b0), | |
7607 | .out(spare2_nor3_4x_unused)); | |
7608 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
7609 | .in1(1'b1), | |
7610 | .out(spare2_nand2_8x_unused)); | |
7611 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
7612 | .out(spare2_buf_16x_unused)); | |
7613 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
7614 | .in1(1'b0), | |
7615 | .out(spare2_nor2_16x_unused)); | |
7616 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
7617 | .out(spare2_inv_32x_unused)); | |
7618 | ||
7619 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
7620 | .siclk(siclk), | |
7621 | .soclk(soclk), | |
7622 | .si(si_3), | |
7623 | .so(so_3), | |
7624 | .d(1'b0), | |
7625 | .q(spare3_flop_unused)); | |
7626 | assign si_3 = so_2; | |
7627 | ||
7628 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
7629 | .out(spare3_buf_32x_unused)); | |
7630 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
7631 | .in1(1'b1), | |
7632 | .in2(1'b1), | |
7633 | .out(spare3_nand3_8x_unused)); | |
7634 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
7635 | .out(spare3_inv_8x_unused)); | |
7636 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
7637 | .in01(1'b1), | |
7638 | .in10(1'b1), | |
7639 | .in11(1'b1), | |
7640 | .out(spare3_aoi22_4x_unused)); | |
7641 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
7642 | .out(spare3_buf_8x_unused)); | |
7643 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
7644 | .in01(1'b1), | |
7645 | .in10(1'b1), | |
7646 | .in11(1'b1), | |
7647 | .out(spare3_oai22_4x_unused)); | |
7648 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
7649 | .out(spare3_inv_16x_unused)); | |
7650 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
7651 | .in1(1'b1), | |
7652 | .out(spare3_nand2_16x_unused)); | |
7653 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
7654 | .in1(1'b0), | |
7655 | .in2(1'b0), | |
7656 | .out(spare3_nor3_4x_unused)); | |
7657 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
7658 | .in1(1'b1), | |
7659 | .out(spare3_nand2_8x_unused)); | |
7660 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
7661 | .out(spare3_buf_16x_unused)); | |
7662 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
7663 | .in1(1'b0), | |
7664 | .out(spare3_nor2_16x_unused)); | |
7665 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
7666 | .out(spare3_inv_32x_unused)); | |
7667 | ||
7668 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), | |
7669 | .siclk(siclk), | |
7670 | .soclk(soclk), | |
7671 | .si(si_4), | |
7672 | .so(so_4), | |
7673 | .d(1'b0), | |
7674 | .q(spare4_flop_unused)); | |
7675 | assign si_4 = so_3; | |
7676 | ||
7677 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
7678 | .out(spare4_buf_32x_unused)); | |
7679 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
7680 | .in1(1'b1), | |
7681 | .in2(1'b1), | |
7682 | .out(spare4_nand3_8x_unused)); | |
7683 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
7684 | .out(spare4_inv_8x_unused)); | |
7685 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
7686 | .in01(1'b1), | |
7687 | .in10(1'b1), | |
7688 | .in11(1'b1), | |
7689 | .out(spare4_aoi22_4x_unused)); | |
7690 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
7691 | .out(spare4_buf_8x_unused)); | |
7692 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
7693 | .in01(1'b1), | |
7694 | .in10(1'b1), | |
7695 | .in11(1'b1), | |
7696 | .out(spare4_oai22_4x_unused)); | |
7697 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
7698 | .out(spare4_inv_16x_unused)); | |
7699 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
7700 | .in1(1'b1), | |
7701 | .out(spare4_nand2_16x_unused)); | |
7702 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
7703 | .in1(1'b0), | |
7704 | .in2(1'b0), | |
7705 | .out(spare4_nor3_4x_unused)); | |
7706 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
7707 | .in1(1'b1), | |
7708 | .out(spare4_nand2_8x_unused)); | |
7709 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
7710 | .out(spare4_buf_16x_unused)); | |
7711 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
7712 | .in1(1'b0), | |
7713 | .out(spare4_nor2_16x_unused)); | |
7714 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
7715 | .out(spare4_inv_32x_unused)); | |
7716 | ||
7717 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), | |
7718 | .siclk(siclk), | |
7719 | .soclk(soclk), | |
7720 | .si(si_5), | |
7721 | .so(so_5), | |
7722 | .d(1'b0), | |
7723 | .q(spare5_flop_unused)); | |
7724 | assign si_5 = so_4; | |
7725 | ||
7726 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
7727 | .out(spare5_buf_32x_unused)); | |
7728 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
7729 | .in1(1'b1), | |
7730 | .in2(1'b1), | |
7731 | .out(spare5_nand3_8x_unused)); | |
7732 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
7733 | .out(spare5_inv_8x_unused)); | |
7734 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
7735 | .in01(1'b1), | |
7736 | .in10(1'b1), | |
7737 | .in11(1'b1), | |
7738 | .out(spare5_aoi22_4x_unused)); | |
7739 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
7740 | .out(spare5_buf_8x_unused)); | |
7741 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
7742 | .in01(1'b1), | |
7743 | .in10(1'b1), | |
7744 | .in11(1'b1), | |
7745 | .out(spare5_oai22_4x_unused)); | |
7746 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
7747 | .out(spare5_inv_16x_unused)); | |
7748 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
7749 | .in1(1'b1), | |
7750 | .out(spare5_nand2_16x_unused)); | |
7751 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
7752 | .in1(1'b0), | |
7753 | .in2(1'b0), | |
7754 | .out(spare5_nor3_4x_unused)); | |
7755 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
7756 | .in1(1'b1), | |
7757 | .out(spare5_nand2_8x_unused)); | |
7758 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
7759 | .out(spare5_buf_16x_unused)); | |
7760 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
7761 | .in1(1'b0), | |
7762 | .out(spare5_nor2_16x_unused)); | |
7763 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
7764 | .out(spare5_inv_32x_unused)); | |
7765 | ||
7766 | cl_sc1_msff_8x spare6_flop (.l1clk(l1clk), | |
7767 | .siclk(siclk), | |
7768 | .soclk(soclk), | |
7769 | .si(si_6), | |
7770 | .so(so_6), | |
7771 | .d(1'b0), | |
7772 | .q(spare6_flop_unused)); | |
7773 | assign si_6 = so_5; | |
7774 | ||
7775 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), | |
7776 | .out(spare6_buf_32x_unused)); | |
7777 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), | |
7778 | .in1(1'b1), | |
7779 | .in2(1'b1), | |
7780 | .out(spare6_nand3_8x_unused)); | |
7781 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), | |
7782 | .out(spare6_inv_8x_unused)); | |
7783 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), | |
7784 | .in01(1'b1), | |
7785 | .in10(1'b1), | |
7786 | .in11(1'b1), | |
7787 | .out(spare6_aoi22_4x_unused)); | |
7788 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), | |
7789 | .out(spare6_buf_8x_unused)); | |
7790 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), | |
7791 | .in01(1'b1), | |
7792 | .in10(1'b1), | |
7793 | .in11(1'b1), | |
7794 | .out(spare6_oai22_4x_unused)); | |
7795 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), | |
7796 | .out(spare6_inv_16x_unused)); | |
7797 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), | |
7798 | .in1(1'b1), | |
7799 | .out(spare6_nand2_16x_unused)); | |
7800 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), | |
7801 | .in1(1'b0), | |
7802 | .in2(1'b0), | |
7803 | .out(spare6_nor3_4x_unused)); | |
7804 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), | |
7805 | .in1(1'b1), | |
7806 | .out(spare6_nand2_8x_unused)); | |
7807 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), | |
7808 | .out(spare6_buf_16x_unused)); | |
7809 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), | |
7810 | .in1(1'b0), | |
7811 | .out(spare6_nor2_16x_unused)); | |
7812 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), | |
7813 | .out(spare6_inv_32x_unused)); | |
7814 | ||
7815 | cl_sc1_msff_8x spare7_flop (.l1clk(l1clk), | |
7816 | .siclk(siclk), | |
7817 | .soclk(soclk), | |
7818 | .si(si_7), | |
7819 | .so(so_7), | |
7820 | .d(1'b0), | |
7821 | .q(spare7_flop_unused)); | |
7822 | assign si_7 = so_6; | |
7823 | ||
7824 | cl_u1_buf_32x spare7_buf_32x (.in(1'b1), | |
7825 | .out(spare7_buf_32x_unused)); | |
7826 | cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1), | |
7827 | .in1(1'b1), | |
7828 | .in2(1'b1), | |
7829 | .out(spare7_nand3_8x_unused)); | |
7830 | cl_u1_inv_8x spare7_inv_8x (.in(1'b1), | |
7831 | .out(spare7_inv_8x_unused)); | |
7832 | cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1), | |
7833 | .in01(1'b1), | |
7834 | .in10(1'b1), | |
7835 | .in11(1'b1), | |
7836 | .out(spare7_aoi22_4x_unused)); | |
7837 | cl_u1_buf_8x spare7_buf_8x (.in(1'b1), | |
7838 | .out(spare7_buf_8x_unused)); | |
7839 | cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1), | |
7840 | .in01(1'b1), | |
7841 | .in10(1'b1), | |
7842 | .in11(1'b1), | |
7843 | .out(spare7_oai22_4x_unused)); | |
7844 | cl_u1_inv_16x spare7_inv_16x (.in(1'b1), | |
7845 | .out(spare7_inv_16x_unused)); | |
7846 | cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1), | |
7847 | .in1(1'b1), | |
7848 | .out(spare7_nand2_16x_unused)); | |
7849 | cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0), | |
7850 | .in1(1'b0), | |
7851 | .in2(1'b0), | |
7852 | .out(spare7_nor3_4x_unused)); | |
7853 | cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1), | |
7854 | .in1(1'b1), | |
7855 | .out(spare7_nand2_8x_unused)); | |
7856 | cl_u1_buf_16x spare7_buf_16x (.in(1'b1), | |
7857 | .out(spare7_buf_16x_unused)); | |
7858 | cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0), | |
7859 | .in1(1'b0), | |
7860 | .out(spare7_nor2_16x_unused)); | |
7861 | cl_u1_inv_32x spare7_inv_32x (.in(1'b1), | |
7862 | .out(spare7_inv_32x_unused)); | |
7863 | ||
7864 | cl_sc1_msff_8x spare8_flop (.l1clk(l1clk), | |
7865 | .siclk(siclk), | |
7866 | .soclk(soclk), | |
7867 | .si(si_8), | |
7868 | .so(so_8), | |
7869 | .d(1'b0), | |
7870 | .q(spare8_flop_unused)); | |
7871 | assign si_8 = so_7; | |
7872 | ||
7873 | cl_u1_buf_32x spare8_buf_32x (.in(1'b1), | |
7874 | .out(spare8_buf_32x_unused)); | |
7875 | cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1), | |
7876 | .in1(1'b1), | |
7877 | .in2(1'b1), | |
7878 | .out(spare8_nand3_8x_unused)); | |
7879 | cl_u1_inv_8x spare8_inv_8x (.in(1'b1), | |
7880 | .out(spare8_inv_8x_unused)); | |
7881 | cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1), | |
7882 | .in01(1'b1), | |
7883 | .in10(1'b1), | |
7884 | .in11(1'b1), | |
7885 | .out(spare8_aoi22_4x_unused)); | |
7886 | cl_u1_buf_8x spare8_buf_8x (.in(1'b1), | |
7887 | .out(spare8_buf_8x_unused)); | |
7888 | cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1), | |
7889 | .in01(1'b1), | |
7890 | .in10(1'b1), | |
7891 | .in11(1'b1), | |
7892 | .out(spare8_oai22_4x_unused)); | |
7893 | cl_u1_inv_16x spare8_inv_16x (.in(1'b1), | |
7894 | .out(spare8_inv_16x_unused)); | |
7895 | cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1), | |
7896 | .in1(1'b1), | |
7897 | .out(spare8_nand2_16x_unused)); | |
7898 | cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0), | |
7899 | .in1(1'b0), | |
7900 | .in2(1'b0), | |
7901 | .out(spare8_nor3_4x_unused)); | |
7902 | cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1), | |
7903 | .in1(1'b1), | |
7904 | .out(spare8_nand2_8x_unused)); | |
7905 | cl_u1_buf_16x spare8_buf_16x (.in(1'b1), | |
7906 | .out(spare8_buf_16x_unused)); | |
7907 | cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0), | |
7908 | .in1(1'b0), | |
7909 | .out(spare8_nor2_16x_unused)); | |
7910 | cl_u1_inv_32x spare8_inv_32x (.in(1'b1), | |
7911 | .out(spare8_inv_32x_unused)); | |
7912 | ||
7913 | cl_sc1_msff_8x spare9_flop (.l1clk(l1clk), | |
7914 | .siclk(siclk), | |
7915 | .soclk(soclk), | |
7916 | .si(si_9), | |
7917 | .so(so_9), | |
7918 | .d(1'b0), | |
7919 | .q(spare9_flop_unused)); | |
7920 | assign si_9 = so_8; | |
7921 | ||
7922 | cl_u1_buf_32x spare9_buf_32x (.in(1'b1), | |
7923 | .out(spare9_buf_32x_unused)); | |
7924 | cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1), | |
7925 | .in1(1'b1), | |
7926 | .in2(1'b1), | |
7927 | .out(spare9_nand3_8x_unused)); | |
7928 | cl_u1_inv_8x spare9_inv_8x (.in(1'b1), | |
7929 | .out(spare9_inv_8x_unused)); | |
7930 | cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1), | |
7931 | .in01(1'b1), | |
7932 | .in10(1'b1), | |
7933 | .in11(1'b1), | |
7934 | .out(spare9_aoi22_4x_unused)); | |
7935 | cl_u1_buf_8x spare9_buf_8x (.in(1'b1), | |
7936 | .out(spare9_buf_8x_unused)); | |
7937 | cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1), | |
7938 | .in01(1'b1), | |
7939 | .in10(1'b1), | |
7940 | .in11(1'b1), | |
7941 | .out(spare9_oai22_4x_unused)); | |
7942 | cl_u1_inv_16x spare9_inv_16x (.in(1'b1), | |
7943 | .out(spare9_inv_16x_unused)); | |
7944 | cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1), | |
7945 | .in1(1'b1), | |
7946 | .out(spare9_nand2_16x_unused)); | |
7947 | cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0), | |
7948 | .in1(1'b0), | |
7949 | .in2(1'b0), | |
7950 | .out(spare9_nor3_4x_unused)); | |
7951 | cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1), | |
7952 | .in1(1'b1), | |
7953 | .out(spare9_nand2_8x_unused)); | |
7954 | cl_u1_buf_16x spare9_buf_16x (.in(1'b1), | |
7955 | .out(spare9_buf_16x_unused)); | |
7956 | cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0), | |
7957 | .in1(1'b0), | |
7958 | .out(spare9_nor2_16x_unused)); | |
7959 | cl_u1_inv_32x spare9_inv_32x (.in(1'b1), | |
7960 | .out(spare9_inv_32x_unused)); | |
7961 | ||
7962 | cl_sc1_msff_8x spare10_flop (.l1clk(l1clk), | |
7963 | .siclk(siclk), | |
7964 | .soclk(soclk), | |
7965 | .si(si_10), | |
7966 | .so(so_10), | |
7967 | .d(1'b0), | |
7968 | .q(spare10_flop_unused)); | |
7969 | assign si_10 = so_9; | |
7970 | ||
7971 | cl_u1_buf_32x spare10_buf_32x (.in(1'b1), | |
7972 | .out(spare10_buf_32x_unused)); | |
7973 | cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1), | |
7974 | .in1(1'b1), | |
7975 | .in2(1'b1), | |
7976 | .out(spare10_nand3_8x_unused)); | |
7977 | cl_u1_inv_8x spare10_inv_8x (.in(1'b1), | |
7978 | .out(spare10_inv_8x_unused)); | |
7979 | cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1), | |
7980 | .in01(1'b1), | |
7981 | .in10(1'b1), | |
7982 | .in11(1'b1), | |
7983 | .out(spare10_aoi22_4x_unused)); | |
7984 | cl_u1_buf_8x spare10_buf_8x (.in(1'b1), | |
7985 | .out(spare10_buf_8x_unused)); | |
7986 | cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1), | |
7987 | .in01(1'b1), | |
7988 | .in10(1'b1), | |
7989 | .in11(1'b1), | |
7990 | .out(spare10_oai22_4x_unused)); | |
7991 | cl_u1_inv_16x spare10_inv_16x (.in(1'b1), | |
7992 | .out(spare10_inv_16x_unused)); | |
7993 | cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1), | |
7994 | .in1(1'b1), | |
7995 | .out(spare10_nand2_16x_unused)); | |
7996 | cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0), | |
7997 | .in1(1'b0), | |
7998 | .in2(1'b0), | |
7999 | .out(spare10_nor3_4x_unused)); | |
8000 | cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1), | |
8001 | .in1(1'b1), | |
8002 | .out(spare10_nand2_8x_unused)); | |
8003 | cl_u1_buf_16x spare10_buf_16x (.in(1'b1), | |
8004 | .out(spare10_buf_16x_unused)); | |
8005 | cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0), | |
8006 | .in1(1'b0), | |
8007 | .out(spare10_nor2_16x_unused)); | |
8008 | cl_u1_inv_32x spare10_inv_32x (.in(1'b1), | |
8009 | .out(spare10_inv_32x_unused)); | |
8010 | ||
8011 | cl_sc1_msff_8x spare11_flop (.l1clk(l1clk), | |
8012 | .siclk(siclk), | |
8013 | .soclk(soclk), | |
8014 | .si(si_11), | |
8015 | .so(so_11), | |
8016 | .d(1'b0), | |
8017 | .q(spare11_flop_unused)); | |
8018 | assign si_11 = so_10; | |
8019 | ||
8020 | cl_u1_buf_32x spare11_buf_32x (.in(1'b1), | |
8021 | .out(spare11_buf_32x_unused)); | |
8022 | cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1), | |
8023 | .in1(1'b1), | |
8024 | .in2(1'b1), | |
8025 | .out(spare11_nand3_8x_unused)); | |
8026 | cl_u1_inv_8x spare11_inv_8x (.in(1'b1), | |
8027 | .out(spare11_inv_8x_unused)); | |
8028 | cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1), | |
8029 | .in01(1'b1), | |
8030 | .in10(1'b1), | |
8031 | .in11(1'b1), | |
8032 | .out(spare11_aoi22_4x_unused)); | |
8033 | cl_u1_buf_8x spare11_buf_8x (.in(1'b1), | |
8034 | .out(spare11_buf_8x_unused)); | |
8035 | cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1), | |
8036 | .in01(1'b1), | |
8037 | .in10(1'b1), | |
8038 | .in11(1'b1), | |
8039 | .out(spare11_oai22_4x_unused)); | |
8040 | cl_u1_inv_16x spare11_inv_16x (.in(1'b1), | |
8041 | .out(spare11_inv_16x_unused)); | |
8042 | cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1), | |
8043 | .in1(1'b1), | |
8044 | .out(spare11_nand2_16x_unused)); | |
8045 | cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0), | |
8046 | .in1(1'b0), | |
8047 | .in2(1'b0), | |
8048 | .out(spare11_nor3_4x_unused)); | |
8049 | cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1), | |
8050 | .in1(1'b1), | |
8051 | .out(spare11_nand2_8x_unused)); | |
8052 | cl_u1_buf_16x spare11_buf_16x (.in(1'b1), | |
8053 | .out(spare11_buf_16x_unused)); | |
8054 | cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0), | |
8055 | .in1(1'b0), | |
8056 | .out(spare11_nor2_16x_unused)); | |
8057 | cl_u1_inv_32x spare11_inv_32x (.in(1'b1), | |
8058 | .out(spare11_inv_32x_unused)); | |
8059 | ||
8060 | cl_sc1_msff_8x spare12_flop (.l1clk(l1clk), | |
8061 | .siclk(siclk), | |
8062 | .soclk(soclk), | |
8063 | .si(si_12), | |
8064 | .so(so_12), | |
8065 | .d(1'b0), | |
8066 | .q(spare12_flop_unused)); | |
8067 | assign si_12 = so_11; | |
8068 | ||
8069 | cl_u1_buf_32x spare12_buf_32x (.in(1'b1), | |
8070 | .out(spare12_buf_32x_unused)); | |
8071 | cl_u1_nand3_8x spare12_nand3_8x (.in0(1'b1), | |
8072 | .in1(1'b1), | |
8073 | .in2(1'b1), | |
8074 | .out(spare12_nand3_8x_unused)); | |
8075 | cl_u1_inv_8x spare12_inv_8x (.in(1'b1), | |
8076 | .out(spare12_inv_8x_unused)); | |
8077 | cl_u1_aoi22_4x spare12_aoi22_4x (.in00(1'b1), | |
8078 | .in01(1'b1), | |
8079 | .in10(1'b1), | |
8080 | .in11(1'b1), | |
8081 | .out(spare12_aoi22_4x_unused)); | |
8082 | cl_u1_buf_8x spare12_buf_8x (.in(1'b1), | |
8083 | .out(spare12_buf_8x_unused)); | |
8084 | cl_u1_oai22_4x spare12_oai22_4x (.in00(1'b1), | |
8085 | .in01(1'b1), | |
8086 | .in10(1'b1), | |
8087 | .in11(1'b1), | |
8088 | .out(spare12_oai22_4x_unused)); | |
8089 | cl_u1_inv_16x spare12_inv_16x (.in(1'b1), | |
8090 | .out(spare12_inv_16x_unused)); | |
8091 | cl_u1_nand2_16x spare12_nand2_16x (.in0(1'b1), | |
8092 | .in1(1'b1), | |
8093 | .out(spare12_nand2_16x_unused)); | |
8094 | cl_u1_nor3_4x spare12_nor3_4x (.in0(1'b0), | |
8095 | .in1(1'b0), | |
8096 | .in2(1'b0), | |
8097 | .out(spare12_nor3_4x_unused)); | |
8098 | cl_u1_nand2_8x spare12_nand2_8x (.in0(1'b1), | |
8099 | .in1(1'b1), | |
8100 | .out(spare12_nand2_8x_unused)); | |
8101 | cl_u1_buf_16x spare12_buf_16x (.in(1'b1), | |
8102 | .out(spare12_buf_16x_unused)); | |
8103 | cl_u1_nor2_16x spare12_nor2_16x (.in0(1'b0), | |
8104 | .in1(1'b0), | |
8105 | .out(spare12_nor2_16x_unused)); | |
8106 | cl_u1_inv_32x spare12_inv_32x (.in(1'b1), | |
8107 | .out(spare12_inv_32x_unused)); | |
8108 | ||
8109 | cl_sc1_msff_8x spare13_flop (.l1clk(l1clk), | |
8110 | .siclk(siclk), | |
8111 | .soclk(soclk), | |
8112 | .si(si_13), | |
8113 | .so(so_13), | |
8114 | .d(1'b0), | |
8115 | .q(spare13_flop_unused)); | |
8116 | assign si_13 = so_12; | |
8117 | ||
8118 | cl_u1_buf_32x spare13_buf_32x (.in(1'b1), | |
8119 | .out(spare13_buf_32x_unused)); | |
8120 | cl_u1_nand3_8x spare13_nand3_8x (.in0(1'b1), | |
8121 | .in1(1'b1), | |
8122 | .in2(1'b1), | |
8123 | .out(spare13_nand3_8x_unused)); | |
8124 | cl_u1_inv_8x spare13_inv_8x (.in(1'b1), | |
8125 | .out(spare13_inv_8x_unused)); | |
8126 | cl_u1_aoi22_4x spare13_aoi22_4x (.in00(1'b1), | |
8127 | .in01(1'b1), | |
8128 | .in10(1'b1), | |
8129 | .in11(1'b1), | |
8130 | .out(spare13_aoi22_4x_unused)); | |
8131 | cl_u1_buf_8x spare13_buf_8x (.in(1'b1), | |
8132 | .out(spare13_buf_8x_unused)); | |
8133 | cl_u1_oai22_4x spare13_oai22_4x (.in00(1'b1), | |
8134 | .in01(1'b1), | |
8135 | .in10(1'b1), | |
8136 | .in11(1'b1), | |
8137 | .out(spare13_oai22_4x_unused)); | |
8138 | cl_u1_inv_16x spare13_inv_16x (.in(1'b1), | |
8139 | .out(spare13_inv_16x_unused)); | |
8140 | cl_u1_nand2_16x spare13_nand2_16x (.in0(1'b1), | |
8141 | .in1(1'b1), | |
8142 | .out(spare13_nand2_16x_unused)); | |
8143 | cl_u1_nor3_4x spare13_nor3_4x (.in0(1'b0), | |
8144 | .in1(1'b0), | |
8145 | .in2(1'b0), | |
8146 | .out(spare13_nor3_4x_unused)); | |
8147 | cl_u1_nand2_8x spare13_nand2_8x (.in0(1'b1), | |
8148 | .in1(1'b1), | |
8149 | .out(spare13_nand2_8x_unused)); | |
8150 | cl_u1_buf_16x spare13_buf_16x (.in(1'b1), | |
8151 | .out(spare13_buf_16x_unused)); | |
8152 | cl_u1_nor2_16x spare13_nor2_16x (.in0(1'b0), | |
8153 | .in1(1'b0), | |
8154 | .out(spare13_nor2_16x_unused)); | |
8155 | cl_u1_inv_32x spare13_inv_32x (.in(1'b1), | |
8156 | .out(spare13_inv_32x_unused)); | |
8157 | ||
8158 | cl_sc1_msff_8x spare14_flop (.l1clk(l1clk), | |
8159 | .siclk(siclk), | |
8160 | .soclk(soclk), | |
8161 | .si(si_14), | |
8162 | .so(so_14), | |
8163 | .d(1'b0), | |
8164 | .q(spare14_flop_unused)); | |
8165 | assign si_14 = so_13; | |
8166 | ||
8167 | cl_u1_buf_32x spare14_buf_32x (.in(1'b1), | |
8168 | .out(spare14_buf_32x_unused)); | |
8169 | cl_u1_nand3_8x spare14_nand3_8x (.in0(1'b1), | |
8170 | .in1(1'b1), | |
8171 | .in2(1'b1), | |
8172 | .out(spare14_nand3_8x_unused)); | |
8173 | cl_u1_inv_8x spare14_inv_8x (.in(1'b1), | |
8174 | .out(spare14_inv_8x_unused)); | |
8175 | cl_u1_aoi22_4x spare14_aoi22_4x (.in00(1'b1), | |
8176 | .in01(1'b1), | |
8177 | .in10(1'b1), | |
8178 | .in11(1'b1), | |
8179 | .out(spare14_aoi22_4x_unused)); | |
8180 | cl_u1_buf_8x spare14_buf_8x (.in(1'b1), | |
8181 | .out(spare14_buf_8x_unused)); | |
8182 | cl_u1_oai22_4x spare14_oai22_4x (.in00(1'b1), | |
8183 | .in01(1'b1), | |
8184 | .in10(1'b1), | |
8185 | .in11(1'b1), | |
8186 | .out(spare14_oai22_4x_unused)); | |
8187 | cl_u1_inv_16x spare14_inv_16x (.in(1'b1), | |
8188 | .out(spare14_inv_16x_unused)); | |
8189 | cl_u1_nand2_16x spare14_nand2_16x (.in0(1'b1), | |
8190 | .in1(1'b1), | |
8191 | .out(spare14_nand2_16x_unused)); | |
8192 | cl_u1_nor3_4x spare14_nor3_4x (.in0(1'b0), | |
8193 | .in1(1'b0), | |
8194 | .in2(1'b0), | |
8195 | .out(spare14_nor3_4x_unused)); | |
8196 | cl_u1_nand2_8x spare14_nand2_8x (.in0(1'b1), | |
8197 | .in1(1'b1), | |
8198 | .out(spare14_nand2_8x_unused)); | |
8199 | cl_u1_buf_16x spare14_buf_16x (.in(1'b1), | |
8200 | .out(spare14_buf_16x_unused)); | |
8201 | cl_u1_nor2_16x spare14_nor2_16x (.in0(1'b0), | |
8202 | .in1(1'b0), | |
8203 | .out(spare14_nor2_16x_unused)); | |
8204 | cl_u1_inv_32x spare14_inv_32x (.in(1'b1), | |
8205 | .out(spare14_inv_32x_unused)); | |
8206 | ||
8207 | cl_sc1_msff_8x spare15_flop (.l1clk(l1clk), | |
8208 | .siclk(siclk), | |
8209 | .soclk(soclk), | |
8210 | .si(si_15), | |
8211 | .so(so_15), | |
8212 | .d(1'b0), | |
8213 | .q(spare15_flop_unused)); | |
8214 | assign si_15 = so_14; | |
8215 | ||
8216 | cl_u1_buf_32x spare15_buf_32x (.in(1'b1), | |
8217 | .out(spare15_buf_32x_unused)); | |
8218 | cl_u1_nand3_8x spare15_nand3_8x (.in0(1'b1), | |
8219 | .in1(1'b1), | |
8220 | .in2(1'b1), | |
8221 | .out(spare15_nand3_8x_unused)); | |
8222 | cl_u1_inv_8x spare15_inv_8x (.in(1'b1), | |
8223 | .out(spare15_inv_8x_unused)); | |
8224 | cl_u1_aoi22_4x spare15_aoi22_4x (.in00(1'b1), | |
8225 | .in01(1'b1), | |
8226 | .in10(1'b1), | |
8227 | .in11(1'b1), | |
8228 | .out(spare15_aoi22_4x_unused)); | |
8229 | cl_u1_buf_8x spare15_buf_8x (.in(1'b1), | |
8230 | .out(spare15_buf_8x_unused)); | |
8231 | cl_u1_oai22_4x spare15_oai22_4x (.in00(1'b1), | |
8232 | .in01(1'b1), | |
8233 | .in10(1'b1), | |
8234 | .in11(1'b1), | |
8235 | .out(spare15_oai22_4x_unused)); | |
8236 | cl_u1_inv_16x spare15_inv_16x (.in(1'b1), | |
8237 | .out(spare15_inv_16x_unused)); | |
8238 | cl_u1_nand2_16x spare15_nand2_16x (.in0(1'b1), | |
8239 | .in1(1'b1), | |
8240 | .out(spare15_nand2_16x_unused)); | |
8241 | cl_u1_nor3_4x spare15_nor3_4x (.in0(1'b0), | |
8242 | .in1(1'b0), | |
8243 | .in2(1'b0), | |
8244 | .out(spare15_nor3_4x_unused)); | |
8245 | cl_u1_nand2_8x spare15_nand2_8x (.in0(1'b1), | |
8246 | .in1(1'b1), | |
8247 | .out(spare15_nand2_8x_unused)); | |
8248 | cl_u1_buf_16x spare15_buf_16x (.in(1'b1), | |
8249 | .out(spare15_buf_16x_unused)); | |
8250 | cl_u1_nor2_16x spare15_nor2_16x (.in0(1'b0), | |
8251 | .in1(1'b0), | |
8252 | .out(spare15_nor2_16x_unused)); | |
8253 | cl_u1_inv_32x spare15_inv_32x (.in(1'b1), | |
8254 | .out(spare15_inv_32x_unused)); | |
8255 | ||
8256 | cl_sc1_msff_8x spare16_flop (.l1clk(l1clk), | |
8257 | .siclk(siclk), | |
8258 | .soclk(soclk), | |
8259 | .si(si_16), | |
8260 | .so(so_16), | |
8261 | .d(1'b0), | |
8262 | .q(spare16_flop_unused)); | |
8263 | assign si_16 = so_15; | |
8264 | ||
8265 | cl_u1_buf_32x spare16_buf_32x (.in(1'b1), | |
8266 | .out(spare16_buf_32x_unused)); | |
8267 | cl_u1_nand3_8x spare16_nand3_8x (.in0(1'b1), | |
8268 | .in1(1'b1), | |
8269 | .in2(1'b1), | |
8270 | .out(spare16_nand3_8x_unused)); | |
8271 | cl_u1_inv_8x spare16_inv_8x (.in(1'b1), | |
8272 | .out(spare16_inv_8x_unused)); | |
8273 | cl_u1_aoi22_4x spare16_aoi22_4x (.in00(1'b1), | |
8274 | .in01(1'b1), | |
8275 | .in10(1'b1), | |
8276 | .in11(1'b1), | |
8277 | .out(spare16_aoi22_4x_unused)); | |
8278 | cl_u1_buf_8x spare16_buf_8x (.in(1'b1), | |
8279 | .out(spare16_buf_8x_unused)); | |
8280 | cl_u1_oai22_4x spare16_oai22_4x (.in00(1'b1), | |
8281 | .in01(1'b1), | |
8282 | .in10(1'b1), | |
8283 | .in11(1'b1), | |
8284 | .out(spare16_oai22_4x_unused)); | |
8285 | cl_u1_inv_16x spare16_inv_16x (.in(1'b1), | |
8286 | .out(spare16_inv_16x_unused)); | |
8287 | cl_u1_nand2_16x spare16_nand2_16x (.in0(1'b1), | |
8288 | .in1(1'b1), | |
8289 | .out(spare16_nand2_16x_unused)); | |
8290 | cl_u1_nor3_4x spare16_nor3_4x (.in0(1'b0), | |
8291 | .in1(1'b0), | |
8292 | .in2(1'b0), | |
8293 | .out(spare16_nor3_4x_unused)); | |
8294 | cl_u1_nand2_8x spare16_nand2_8x (.in0(1'b1), | |
8295 | .in1(1'b1), | |
8296 | .out(spare16_nand2_8x_unused)); | |
8297 | cl_u1_buf_16x spare16_buf_16x (.in(1'b1), | |
8298 | .out(spare16_buf_16x_unused)); | |
8299 | cl_u1_nor2_16x spare16_nor2_16x (.in0(1'b0), | |
8300 | .in1(1'b0), | |
8301 | .out(spare16_nor2_16x_unused)); | |
8302 | cl_u1_inv_32x spare16_inv_32x (.in(1'b1), | |
8303 | .out(spare16_inv_32x_unused)); | |
8304 | ||
8305 | cl_sc1_msff_8x spare17_flop (.l1clk(l1clk), | |
8306 | .siclk(siclk), | |
8307 | .soclk(soclk), | |
8308 | .si(si_17), | |
8309 | .so(so_17), | |
8310 | .d(1'b0), | |
8311 | .q(spare17_flop_unused)); | |
8312 | assign si_17 = so_16; | |
8313 | ||
8314 | cl_u1_buf_32x spare17_buf_32x (.in(1'b1), | |
8315 | .out(spare17_buf_32x_unused)); | |
8316 | cl_u1_nand3_8x spare17_nand3_8x (.in0(1'b1), | |
8317 | .in1(1'b1), | |
8318 | .in2(1'b1), | |
8319 | .out(spare17_nand3_8x_unused)); | |
8320 | cl_u1_inv_8x spare17_inv_8x (.in(1'b1), | |
8321 | .out(spare17_inv_8x_unused)); | |
8322 | cl_u1_aoi22_4x spare17_aoi22_4x (.in00(1'b1), | |
8323 | .in01(1'b1), | |
8324 | .in10(1'b1), | |
8325 | .in11(1'b1), | |
8326 | .out(spare17_aoi22_4x_unused)); | |
8327 | cl_u1_buf_8x spare17_buf_8x (.in(1'b1), | |
8328 | .out(spare17_buf_8x_unused)); | |
8329 | cl_u1_oai22_4x spare17_oai22_4x (.in00(1'b1), | |
8330 | .in01(1'b1), | |
8331 | .in10(1'b1), | |
8332 | .in11(1'b1), | |
8333 | .out(spare17_oai22_4x_unused)); | |
8334 | cl_u1_inv_16x spare17_inv_16x (.in(1'b1), | |
8335 | .out(spare17_inv_16x_unused)); | |
8336 | cl_u1_nand2_16x spare17_nand2_16x (.in0(1'b1), | |
8337 | .in1(1'b1), | |
8338 | .out(spare17_nand2_16x_unused)); | |
8339 | cl_u1_nor3_4x spare17_nor3_4x (.in0(1'b0), | |
8340 | .in1(1'b0), | |
8341 | .in2(1'b0), | |
8342 | .out(spare17_nor3_4x_unused)); | |
8343 | cl_u1_nand2_8x spare17_nand2_8x (.in0(1'b1), | |
8344 | .in1(1'b1), | |
8345 | .out(spare17_nand2_8x_unused)); | |
8346 | cl_u1_buf_16x spare17_buf_16x (.in(1'b1), | |
8347 | .out(spare17_buf_16x_unused)); | |
8348 | cl_u1_nor2_16x spare17_nor2_16x (.in0(1'b0), | |
8349 | .in1(1'b0), | |
8350 | .out(spare17_nor2_16x_unused)); | |
8351 | cl_u1_inv_32x spare17_inv_32x (.in(1'b1), | |
8352 | .out(spare17_inv_32x_unused)); | |
8353 | ||
8354 | cl_sc1_msff_8x spare18_flop (.l1clk(l1clk), | |
8355 | .siclk(siclk), | |
8356 | .soclk(soclk), | |
8357 | .si(si_18), | |
8358 | .so(so_18), | |
8359 | .d(1'b0), | |
8360 | .q(spare18_flop_unused)); | |
8361 | assign si_18 = so_17; | |
8362 | ||
8363 | cl_u1_buf_32x spare18_buf_32x (.in(1'b1), | |
8364 | .out(spare18_buf_32x_unused)); | |
8365 | cl_u1_nand3_8x spare18_nand3_8x (.in0(1'b1), | |
8366 | .in1(1'b1), | |
8367 | .in2(1'b1), | |
8368 | .out(spare18_nand3_8x_unused)); | |
8369 | cl_u1_inv_8x spare18_inv_8x (.in(1'b1), | |
8370 | .out(spare18_inv_8x_unused)); | |
8371 | cl_u1_aoi22_4x spare18_aoi22_4x (.in00(1'b1), | |
8372 | .in01(1'b1), | |
8373 | .in10(1'b1), | |
8374 | .in11(1'b1), | |
8375 | .out(spare18_aoi22_4x_unused)); | |
8376 | cl_u1_buf_8x spare18_buf_8x (.in(1'b1), | |
8377 | .out(spare18_buf_8x_unused)); | |
8378 | cl_u1_oai22_4x spare18_oai22_4x (.in00(1'b1), | |
8379 | .in01(1'b1), | |
8380 | .in10(1'b1), | |
8381 | .in11(1'b1), | |
8382 | .out(spare18_oai22_4x_unused)); | |
8383 | cl_u1_inv_16x spare18_inv_16x (.in(1'b1), | |
8384 | .out(spare18_inv_16x_unused)); | |
8385 | cl_u1_nand2_16x spare18_nand2_16x (.in0(1'b1), | |
8386 | .in1(1'b1), | |
8387 | .out(spare18_nand2_16x_unused)); | |
8388 | cl_u1_nor3_4x spare18_nor3_4x (.in0(1'b0), | |
8389 | .in1(1'b0), | |
8390 | .in2(1'b0), | |
8391 | .out(spare18_nor3_4x_unused)); | |
8392 | cl_u1_nand2_8x spare18_nand2_8x (.in0(1'b1), | |
8393 | .in1(1'b1), | |
8394 | .out(spare18_nand2_8x_unused)); | |
8395 | cl_u1_buf_16x spare18_buf_16x (.in(1'b1), | |
8396 | .out(spare18_buf_16x_unused)); | |
8397 | cl_u1_nor2_16x spare18_nor2_16x (.in0(1'b0), | |
8398 | .in1(1'b0), | |
8399 | .out(spare18_nor2_16x_unused)); | |
8400 | cl_u1_inv_32x spare18_inv_32x (.in(1'b1), | |
8401 | .out(spare18_inv_32x_unused)); | |
8402 | ||
8403 | cl_sc1_msff_8x spare19_flop (.l1clk(l1clk), | |
8404 | .siclk(siclk), | |
8405 | .soclk(soclk), | |
8406 | .si(si_19), | |
8407 | .so(so_19), | |
8408 | .d(1'b0), | |
8409 | .q(spare19_flop_unused)); | |
8410 | assign si_19 = so_18; | |
8411 | ||
8412 | cl_u1_buf_32x spare19_buf_32x (.in(1'b1), | |
8413 | .out(spare19_buf_32x_unused)); | |
8414 | cl_u1_nand3_8x spare19_nand3_8x (.in0(1'b1), | |
8415 | .in1(1'b1), | |
8416 | .in2(1'b1), | |
8417 | .out(spare19_nand3_8x_unused)); | |
8418 | cl_u1_inv_8x spare19_inv_8x (.in(1'b1), | |
8419 | .out(spare19_inv_8x_unused)); | |
8420 | cl_u1_aoi22_4x spare19_aoi22_4x (.in00(1'b1), | |
8421 | .in01(1'b1), | |
8422 | .in10(1'b1), | |
8423 | .in11(1'b1), | |
8424 | .out(spare19_aoi22_4x_unused)); | |
8425 | cl_u1_buf_8x spare19_buf_8x (.in(1'b1), | |
8426 | .out(spare19_buf_8x_unused)); | |
8427 | cl_u1_oai22_4x spare19_oai22_4x (.in00(1'b1), | |
8428 | .in01(1'b1), | |
8429 | .in10(1'b1), | |
8430 | .in11(1'b1), | |
8431 | .out(spare19_oai22_4x_unused)); | |
8432 | cl_u1_inv_16x spare19_inv_16x (.in(1'b1), | |
8433 | .out(spare19_inv_16x_unused)); | |
8434 | cl_u1_nand2_16x spare19_nand2_16x (.in0(1'b1), | |
8435 | .in1(1'b1), | |
8436 | .out(spare19_nand2_16x_unused)); | |
8437 | cl_u1_nor3_4x spare19_nor3_4x (.in0(1'b0), | |
8438 | .in1(1'b0), | |
8439 | .in2(1'b0), | |
8440 | .out(spare19_nor3_4x_unused)); | |
8441 | cl_u1_nand2_8x spare19_nand2_8x (.in0(1'b1), | |
8442 | .in1(1'b1), | |
8443 | .out(spare19_nand2_8x_unused)); | |
8444 | cl_u1_buf_16x spare19_buf_16x (.in(1'b1), | |
8445 | .out(spare19_buf_16x_unused)); | |
8446 | cl_u1_nor2_16x spare19_nor2_16x (.in0(1'b0), | |
8447 | .in1(1'b0), | |
8448 | .out(spare19_nor2_16x_unused)); | |
8449 | cl_u1_inv_32x spare19_inv_32x (.in(1'b1), | |
8450 | .out(spare19_inv_32x_unused)); | |
8451 | ||
8452 | cl_sc1_msff_8x spare20_flop (.l1clk(l1clk), | |
8453 | .siclk(siclk), | |
8454 | .soclk(soclk), | |
8455 | .si(si_20), | |
8456 | .so(so_20), | |
8457 | .d(1'b0), | |
8458 | .q(spare20_flop_unused)); | |
8459 | assign si_20 = so_19; | |
8460 | ||
8461 | cl_u1_buf_32x spare20_buf_32x (.in(1'b1), | |
8462 | .out(spare20_buf_32x_unused)); | |
8463 | cl_u1_nand3_8x spare20_nand3_8x (.in0(1'b1), | |
8464 | .in1(1'b1), | |
8465 | .in2(1'b1), | |
8466 | .out(spare20_nand3_8x_unused)); | |
8467 | cl_u1_inv_8x spare20_inv_8x (.in(1'b1), | |
8468 | .out(spare20_inv_8x_unused)); | |
8469 | cl_u1_aoi22_4x spare20_aoi22_4x (.in00(1'b1), | |
8470 | .in01(1'b1), | |
8471 | .in10(1'b1), | |
8472 | .in11(1'b1), | |
8473 | .out(spare20_aoi22_4x_unused)); | |
8474 | cl_u1_buf_8x spare20_buf_8x (.in(1'b1), | |
8475 | .out(spare20_buf_8x_unused)); | |
8476 | cl_u1_oai22_4x spare20_oai22_4x (.in00(1'b1), | |
8477 | .in01(1'b1), | |
8478 | .in10(1'b1), | |
8479 | .in11(1'b1), | |
8480 | .out(spare20_oai22_4x_unused)); | |
8481 | cl_u1_inv_16x spare20_inv_16x (.in(1'b1), | |
8482 | .out(spare20_inv_16x_unused)); | |
8483 | cl_u1_nand2_16x spare20_nand2_16x (.in0(1'b1), | |
8484 | .in1(1'b1), | |
8485 | .out(spare20_nand2_16x_unused)); | |
8486 | cl_u1_nor3_4x spare20_nor3_4x (.in0(1'b0), | |
8487 | .in1(1'b0), | |
8488 | .in2(1'b0), | |
8489 | .out(spare20_nor3_4x_unused)); | |
8490 | cl_u1_nand2_8x spare20_nand2_8x (.in0(1'b1), | |
8491 | .in1(1'b1), | |
8492 | .out(spare20_nand2_8x_unused)); | |
8493 | cl_u1_buf_16x spare20_buf_16x (.in(1'b1), | |
8494 | .out(spare20_buf_16x_unused)); | |
8495 | cl_u1_nor2_16x spare20_nor2_16x (.in0(1'b0), | |
8496 | .in1(1'b0), | |
8497 | .out(spare20_nor2_16x_unused)); | |
8498 | cl_u1_inv_32x spare20_inv_32x (.in(1'b1), | |
8499 | .out(spare20_inv_32x_unused)); | |
8500 | ||
8501 | cl_sc1_msff_8x spare21_flop (.l1clk(l1clk), | |
8502 | .siclk(siclk), | |
8503 | .soclk(soclk), | |
8504 | .si(si_21), | |
8505 | .so(so_21), | |
8506 | .d(1'b0), | |
8507 | .q(spare21_flop_unused)); | |
8508 | assign si_21 = so_20; | |
8509 | ||
8510 | cl_u1_buf_32x spare21_buf_32x (.in(1'b1), | |
8511 | .out(spare21_buf_32x_unused)); | |
8512 | cl_u1_nand3_8x spare21_nand3_8x (.in0(1'b1), | |
8513 | .in1(1'b1), | |
8514 | .in2(1'b1), | |
8515 | .out(spare21_nand3_8x_unused)); | |
8516 | cl_u1_inv_8x spare21_inv_8x (.in(1'b1), | |
8517 | .out(spare21_inv_8x_unused)); | |
8518 | cl_u1_aoi22_4x spare21_aoi22_4x (.in00(1'b1), | |
8519 | .in01(1'b1), | |
8520 | .in10(1'b1), | |
8521 | .in11(1'b1), | |
8522 | .out(spare21_aoi22_4x_unused)); | |
8523 | cl_u1_buf_8x spare21_buf_8x (.in(1'b1), | |
8524 | .out(spare21_buf_8x_unused)); | |
8525 | cl_u1_oai22_4x spare21_oai22_4x (.in00(1'b1), | |
8526 | .in01(1'b1), | |
8527 | .in10(1'b1), | |
8528 | .in11(1'b1), | |
8529 | .out(spare21_oai22_4x_unused)); | |
8530 | cl_u1_inv_16x spare21_inv_16x (.in(1'b1), | |
8531 | .out(spare21_inv_16x_unused)); | |
8532 | cl_u1_nand2_16x spare21_nand2_16x (.in0(1'b1), | |
8533 | .in1(1'b1), | |
8534 | .out(spare21_nand2_16x_unused)); | |
8535 | cl_u1_nor3_4x spare21_nor3_4x (.in0(1'b0), | |
8536 | .in1(1'b0), | |
8537 | .in2(1'b0), | |
8538 | .out(spare21_nor3_4x_unused)); | |
8539 | cl_u1_nand2_8x spare21_nand2_8x (.in0(1'b1), | |
8540 | .in1(1'b1), | |
8541 | .out(spare21_nand2_8x_unused)); | |
8542 | cl_u1_buf_16x spare21_buf_16x (.in(1'b1), | |
8543 | .out(spare21_buf_16x_unused)); | |
8544 | cl_u1_nor2_16x spare21_nor2_16x (.in0(1'b0), | |
8545 | .in1(1'b0), | |
8546 | .out(spare21_nor2_16x_unused)); | |
8547 | cl_u1_inv_32x spare21_inv_32x (.in(1'b1), | |
8548 | .out(spare21_inv_32x_unused)); | |
8549 | ||
8550 | cl_sc1_msff_8x spare22_flop (.l1clk(l1clk), | |
8551 | .siclk(siclk), | |
8552 | .soclk(soclk), | |
8553 | .si(si_22), | |
8554 | .so(so_22), | |
8555 | .d(1'b0), | |
8556 | .q(spare22_flop_unused)); | |
8557 | assign si_22 = so_21; | |
8558 | ||
8559 | cl_u1_buf_32x spare22_buf_32x (.in(1'b1), | |
8560 | .out(spare22_buf_32x_unused)); | |
8561 | cl_u1_nand3_8x spare22_nand3_8x (.in0(1'b1), | |
8562 | .in1(1'b1), | |
8563 | .in2(1'b1), | |
8564 | .out(spare22_nand3_8x_unused)); | |
8565 | cl_u1_inv_8x spare22_inv_8x (.in(1'b1), | |
8566 | .out(spare22_inv_8x_unused)); | |
8567 | cl_u1_aoi22_4x spare22_aoi22_4x (.in00(1'b1), | |
8568 | .in01(1'b1), | |
8569 | .in10(1'b1), | |
8570 | .in11(1'b1), | |
8571 | .out(spare22_aoi22_4x_unused)); | |
8572 | cl_u1_buf_8x spare22_buf_8x (.in(1'b1), | |
8573 | .out(spare22_buf_8x_unused)); | |
8574 | cl_u1_oai22_4x spare22_oai22_4x (.in00(1'b1), | |
8575 | .in01(1'b1), | |
8576 | .in10(1'b1), | |
8577 | .in11(1'b1), | |
8578 | .out(spare22_oai22_4x_unused)); | |
8579 | cl_u1_inv_16x spare22_inv_16x (.in(1'b1), | |
8580 | .out(spare22_inv_16x_unused)); | |
8581 | cl_u1_nand2_16x spare22_nand2_16x (.in0(1'b1), | |
8582 | .in1(1'b1), | |
8583 | .out(spare22_nand2_16x_unused)); | |
8584 | cl_u1_nor3_4x spare22_nor3_4x (.in0(1'b0), | |
8585 | .in1(1'b0), | |
8586 | .in2(1'b0), | |
8587 | .out(spare22_nor3_4x_unused)); | |
8588 | cl_u1_nand2_8x spare22_nand2_8x (.in0(1'b1), | |
8589 | .in1(1'b1), | |
8590 | .out(spare22_nand2_8x_unused)); | |
8591 | cl_u1_buf_16x spare22_buf_16x (.in(1'b1), | |
8592 | .out(spare22_buf_16x_unused)); | |
8593 | cl_u1_nor2_16x spare22_nor2_16x (.in0(1'b0), | |
8594 | .in1(1'b0), | |
8595 | .out(spare22_nor2_16x_unused)); | |
8596 | cl_u1_inv_32x spare22_inv_32x (.in(1'b1), | |
8597 | .out(spare22_inv_32x_unused)); | |
8598 | ||
8599 | cl_sc1_msff_8x spare23_flop (.l1clk(l1clk), | |
8600 | .siclk(siclk), | |
8601 | .soclk(soclk), | |
8602 | .si(si_23), | |
8603 | .so(so_23), | |
8604 | .d(1'b0), | |
8605 | .q(spare23_flop_unused)); | |
8606 | assign si_23 = so_22; | |
8607 | ||
8608 | cl_u1_buf_32x spare23_buf_32x (.in(1'b1), | |
8609 | .out(spare23_buf_32x_unused)); | |
8610 | cl_u1_nand3_8x spare23_nand3_8x (.in0(1'b1), | |
8611 | .in1(1'b1), | |
8612 | .in2(1'b1), | |
8613 | .out(spare23_nand3_8x_unused)); | |
8614 | cl_u1_inv_8x spare23_inv_8x (.in(1'b1), | |
8615 | .out(spare23_inv_8x_unused)); | |
8616 | cl_u1_aoi22_4x spare23_aoi22_4x (.in00(1'b1), | |
8617 | .in01(1'b1), | |
8618 | .in10(1'b1), | |
8619 | .in11(1'b1), | |
8620 | .out(spare23_aoi22_4x_unused)); | |
8621 | cl_u1_buf_8x spare23_buf_8x (.in(1'b1), | |
8622 | .out(spare23_buf_8x_unused)); | |
8623 | cl_u1_oai22_4x spare23_oai22_4x (.in00(1'b1), | |
8624 | .in01(1'b1), | |
8625 | .in10(1'b1), | |
8626 | .in11(1'b1), | |
8627 | .out(spare23_oai22_4x_unused)); | |
8628 | cl_u1_inv_16x spare23_inv_16x (.in(1'b1), | |
8629 | .out(spare23_inv_16x_unused)); | |
8630 | cl_u1_nand2_16x spare23_nand2_16x (.in0(1'b1), | |
8631 | .in1(1'b1), | |
8632 | .out(spare23_nand2_16x_unused)); | |
8633 | cl_u1_nor3_4x spare23_nor3_4x (.in0(1'b0), | |
8634 | .in1(1'b0), | |
8635 | .in2(1'b0), | |
8636 | .out(spare23_nor3_4x_unused)); | |
8637 | cl_u1_nand2_8x spare23_nand2_8x (.in0(1'b1), | |
8638 | .in1(1'b1), | |
8639 | .out(spare23_nand2_8x_unused)); | |
8640 | cl_u1_buf_16x spare23_buf_16x (.in(1'b1), | |
8641 | .out(spare23_buf_16x_unused)); | |
8642 | cl_u1_nor2_16x spare23_nor2_16x (.in0(1'b0), | |
8643 | .in1(1'b0), | |
8644 | .out(spare23_nor2_16x_unused)); | |
8645 | cl_u1_inv_32x spare23_inv_32x (.in(1'b1), | |
8646 | .out(spare23_inv_32x_unused)); | |
8647 | ||
8648 | cl_sc1_msff_8x spare24_flop (.l1clk(l1clk), | |
8649 | .siclk(siclk), | |
8650 | .soclk(soclk), | |
8651 | .si(si_24), | |
8652 | .so(so_24), | |
8653 | .d(1'b0), | |
8654 | .q(spare24_flop_unused)); | |
8655 | assign si_24 = so_23; | |
8656 | ||
8657 | cl_u1_buf_32x spare24_buf_32x (.in(1'b1), | |
8658 | .out(spare24_buf_32x_unused)); | |
8659 | cl_u1_nand3_8x spare24_nand3_8x (.in0(1'b1), | |
8660 | .in1(1'b1), | |
8661 | .in2(1'b1), | |
8662 | .out(spare24_nand3_8x_unused)); | |
8663 | cl_u1_inv_8x spare24_inv_8x (.in(1'b1), | |
8664 | .out(spare24_inv_8x_unused)); | |
8665 | cl_u1_aoi22_4x spare24_aoi22_4x (.in00(1'b1), | |
8666 | .in01(1'b1), | |
8667 | .in10(1'b1), | |
8668 | .in11(1'b1), | |
8669 | .out(spare24_aoi22_4x_unused)); | |
8670 | cl_u1_buf_8x spare24_buf_8x (.in(1'b1), | |
8671 | .out(spare24_buf_8x_unused)); | |
8672 | cl_u1_oai22_4x spare24_oai22_4x (.in00(1'b1), | |
8673 | .in01(1'b1), | |
8674 | .in10(1'b1), | |
8675 | .in11(1'b1), | |
8676 | .out(spare24_oai22_4x_unused)); | |
8677 | cl_u1_inv_16x spare24_inv_16x (.in(1'b1), | |
8678 | .out(spare24_inv_16x_unused)); | |
8679 | cl_u1_nand2_16x spare24_nand2_16x (.in0(1'b1), | |
8680 | .in1(1'b1), | |
8681 | .out(spare24_nand2_16x_unused)); | |
8682 | cl_u1_nor3_4x spare24_nor3_4x (.in0(1'b0), | |
8683 | .in1(1'b0), | |
8684 | .in2(1'b0), | |
8685 | .out(spare24_nor3_4x_unused)); | |
8686 | cl_u1_nand2_8x spare24_nand2_8x (.in0(1'b1), | |
8687 | .in1(1'b1), | |
8688 | .out(spare24_nand2_8x_unused)); | |
8689 | cl_u1_buf_16x spare24_buf_16x (.in(1'b1), | |
8690 | .out(spare24_buf_16x_unused)); | |
8691 | cl_u1_nor2_16x spare24_nor2_16x (.in0(1'b0), | |
8692 | .in1(1'b0), | |
8693 | .out(spare24_nor2_16x_unused)); | |
8694 | cl_u1_inv_32x spare24_inv_32x (.in(1'b1), | |
8695 | .out(spare24_inv_32x_unused)); | |
8696 | ||
8697 | cl_sc1_msff_8x spare25_flop (.l1clk(l1clk), | |
8698 | .siclk(siclk), | |
8699 | .soclk(soclk), | |
8700 | .si(si_25), | |
8701 | .so(so_25), | |
8702 | .d(1'b0), | |
8703 | .q(spare25_flop_unused)); | |
8704 | assign si_25 = so_24; | |
8705 | ||
8706 | cl_u1_buf_32x spare25_buf_32x (.in(1'b1), | |
8707 | .out(spare25_buf_32x_unused)); | |
8708 | cl_u1_nand3_8x spare25_nand3_8x (.in0(1'b1), | |
8709 | .in1(1'b1), | |
8710 | .in2(1'b1), | |
8711 | .out(spare25_nand3_8x_unused)); | |
8712 | cl_u1_inv_8x spare25_inv_8x (.in(1'b1), | |
8713 | .out(spare25_inv_8x_unused)); | |
8714 | cl_u1_aoi22_4x spare25_aoi22_4x (.in00(1'b1), | |
8715 | .in01(1'b1), | |
8716 | .in10(1'b1), | |
8717 | .in11(1'b1), | |
8718 | .out(spare25_aoi22_4x_unused)); | |
8719 | cl_u1_buf_8x spare25_buf_8x (.in(1'b1), | |
8720 | .out(spare25_buf_8x_unused)); | |
8721 | cl_u1_oai22_4x spare25_oai22_4x (.in00(1'b1), | |
8722 | .in01(1'b1), | |
8723 | .in10(1'b1), | |
8724 | .in11(1'b1), | |
8725 | .out(spare25_oai22_4x_unused)); | |
8726 | cl_u1_inv_16x spare25_inv_16x (.in(1'b1), | |
8727 | .out(spare25_inv_16x_unused)); | |
8728 | cl_u1_nand2_16x spare25_nand2_16x (.in0(1'b1), | |
8729 | .in1(1'b1), | |
8730 | .out(spare25_nand2_16x_unused)); | |
8731 | cl_u1_nor3_4x spare25_nor3_4x (.in0(1'b0), | |
8732 | .in1(1'b0), | |
8733 | .in2(1'b0), | |
8734 | .out(spare25_nor3_4x_unused)); | |
8735 | cl_u1_nand2_8x spare25_nand2_8x (.in0(1'b1), | |
8736 | .in1(1'b1), | |
8737 | .out(spare25_nand2_8x_unused)); | |
8738 | cl_u1_buf_16x spare25_buf_16x (.in(1'b1), | |
8739 | .out(spare25_buf_16x_unused)); | |
8740 | cl_u1_nor2_16x spare25_nor2_16x (.in0(1'b0), | |
8741 | .in1(1'b0), | |
8742 | .out(spare25_nor2_16x_unused)); | |
8743 | cl_u1_inv_32x spare25_inv_32x (.in(1'b1), | |
8744 | .out(spare25_inv_32x_unused)); | |
8745 | ||
8746 | cl_sc1_msff_8x spare26_flop (.l1clk(l1clk), | |
8747 | .siclk(siclk), | |
8748 | .soclk(soclk), | |
8749 | .si(si_26), | |
8750 | .so(so_26), | |
8751 | .d(1'b0), | |
8752 | .q(spare26_flop_unused)); | |
8753 | assign si_26 = so_25; | |
8754 | ||
8755 | cl_u1_buf_32x spare26_buf_32x (.in(1'b1), | |
8756 | .out(spare26_buf_32x_unused)); | |
8757 | cl_u1_nand3_8x spare26_nand3_8x (.in0(1'b1), | |
8758 | .in1(1'b1), | |
8759 | .in2(1'b1), | |
8760 | .out(spare26_nand3_8x_unused)); | |
8761 | cl_u1_inv_8x spare26_inv_8x (.in(1'b1), | |
8762 | .out(spare26_inv_8x_unused)); | |
8763 | cl_u1_aoi22_4x spare26_aoi22_4x (.in00(1'b1), | |
8764 | .in01(1'b1), | |
8765 | .in10(1'b1), | |
8766 | .in11(1'b1), | |
8767 | .out(spare26_aoi22_4x_unused)); | |
8768 | cl_u1_buf_8x spare26_buf_8x (.in(1'b1), | |
8769 | .out(spare26_buf_8x_unused)); | |
8770 | cl_u1_oai22_4x spare26_oai22_4x (.in00(1'b1), | |
8771 | .in01(1'b1), | |
8772 | .in10(1'b1), | |
8773 | .in11(1'b1), | |
8774 | .out(spare26_oai22_4x_unused)); | |
8775 | cl_u1_inv_16x spare26_inv_16x (.in(1'b1), | |
8776 | .out(spare26_inv_16x_unused)); | |
8777 | cl_u1_nand2_16x spare26_nand2_16x (.in0(1'b1), | |
8778 | .in1(1'b1), | |
8779 | .out(spare26_nand2_16x_unused)); | |
8780 | cl_u1_nor3_4x spare26_nor3_4x (.in0(1'b0), | |
8781 | .in1(1'b0), | |
8782 | .in2(1'b0), | |
8783 | .out(spare26_nor3_4x_unused)); | |
8784 | cl_u1_nand2_8x spare26_nand2_8x (.in0(1'b1), | |
8785 | .in1(1'b1), | |
8786 | .out(spare26_nand2_8x_unused)); | |
8787 | cl_u1_buf_16x spare26_buf_16x (.in(1'b1), | |
8788 | .out(spare26_buf_16x_unused)); | |
8789 | cl_u1_nor2_16x spare26_nor2_16x (.in0(1'b0), | |
8790 | .in1(1'b0), | |
8791 | .out(spare26_nor2_16x_unused)); | |
8792 | cl_u1_inv_32x spare26_inv_32x (.in(1'b1), | |
8793 | .out(spare26_inv_32x_unused)); | |
8794 | ||
8795 | cl_sc1_msff_8x spare27_flop (.l1clk(l1clk), | |
8796 | .siclk(siclk), | |
8797 | .soclk(soclk), | |
8798 | .si(si_27), | |
8799 | .so(so_27), | |
8800 | .d(1'b0), | |
8801 | .q(spare27_flop_unused)); | |
8802 | assign si_27 = so_26; | |
8803 | ||
8804 | cl_u1_buf_32x spare27_buf_32x (.in(1'b1), | |
8805 | .out(spare27_buf_32x_unused)); | |
8806 | cl_u1_nand3_8x spare27_nand3_8x (.in0(1'b1), | |
8807 | .in1(1'b1), | |
8808 | .in2(1'b1), | |
8809 | .out(spare27_nand3_8x_unused)); | |
8810 | cl_u1_inv_8x spare27_inv_8x (.in(1'b1), | |
8811 | .out(spare27_inv_8x_unused)); | |
8812 | cl_u1_aoi22_4x spare27_aoi22_4x (.in00(1'b1), | |
8813 | .in01(1'b1), | |
8814 | .in10(1'b1), | |
8815 | .in11(1'b1), | |
8816 | .out(spare27_aoi22_4x_unused)); | |
8817 | cl_u1_buf_8x spare27_buf_8x (.in(1'b1), | |
8818 | .out(spare27_buf_8x_unused)); | |
8819 | cl_u1_oai22_4x spare27_oai22_4x (.in00(1'b1), | |
8820 | .in01(1'b1), | |
8821 | .in10(1'b1), | |
8822 | .in11(1'b1), | |
8823 | .out(spare27_oai22_4x_unused)); | |
8824 | cl_u1_inv_16x spare27_inv_16x (.in(1'b1), | |
8825 | .out(spare27_inv_16x_unused)); | |
8826 | cl_u1_nand2_16x spare27_nand2_16x (.in0(1'b1), | |
8827 | .in1(1'b1), | |
8828 | .out(spare27_nand2_16x_unused)); | |
8829 | cl_u1_nor3_4x spare27_nor3_4x (.in0(1'b0), | |
8830 | .in1(1'b0), | |
8831 | .in2(1'b0), | |
8832 | .out(spare27_nor3_4x_unused)); | |
8833 | cl_u1_nand2_8x spare27_nand2_8x (.in0(1'b1), | |
8834 | .in1(1'b1), | |
8835 | .out(spare27_nand2_8x_unused)); | |
8836 | cl_u1_buf_16x spare27_buf_16x (.in(1'b1), | |
8837 | .out(spare27_buf_16x_unused)); | |
8838 | cl_u1_nor2_16x spare27_nor2_16x (.in0(1'b0), | |
8839 | .in1(1'b0), | |
8840 | .out(spare27_nor2_16x_unused)); | |
8841 | cl_u1_inv_32x spare27_inv_32x (.in(1'b1), | |
8842 | .out(spare27_inv_32x_unused)); | |
8843 | ||
8844 | cl_sc1_msff_8x spare28_flop (.l1clk(l1clk), | |
8845 | .siclk(siclk), | |
8846 | .soclk(soclk), | |
8847 | .si(si_28), | |
8848 | .so(so_28), | |
8849 | .d(1'b0), | |
8850 | .q(spare28_flop_unused)); | |
8851 | assign si_28 = so_27; | |
8852 | ||
8853 | cl_u1_buf_32x spare28_buf_32x (.in(1'b1), | |
8854 | .out(spare28_buf_32x_unused)); | |
8855 | cl_u1_nand3_8x spare28_nand3_8x (.in0(1'b1), | |
8856 | .in1(1'b1), | |
8857 | .in2(1'b1), | |
8858 | .out(spare28_nand3_8x_unused)); | |
8859 | cl_u1_inv_8x spare28_inv_8x (.in(1'b1), | |
8860 | .out(spare28_inv_8x_unused)); | |
8861 | cl_u1_aoi22_4x spare28_aoi22_4x (.in00(1'b1), | |
8862 | .in01(1'b1), | |
8863 | .in10(1'b1), | |
8864 | .in11(1'b1), | |
8865 | .out(spare28_aoi22_4x_unused)); | |
8866 | cl_u1_buf_8x spare28_buf_8x (.in(1'b1), | |
8867 | .out(spare28_buf_8x_unused)); | |
8868 | cl_u1_oai22_4x spare28_oai22_4x (.in00(1'b1), | |
8869 | .in01(1'b1), | |
8870 | .in10(1'b1), | |
8871 | .in11(1'b1), | |
8872 | .out(spare28_oai22_4x_unused)); | |
8873 | cl_u1_inv_16x spare28_inv_16x (.in(1'b1), | |
8874 | .out(spare28_inv_16x_unused)); | |
8875 | cl_u1_nand2_16x spare28_nand2_16x (.in0(1'b1), | |
8876 | .in1(1'b1), | |
8877 | .out(spare28_nand2_16x_unused)); | |
8878 | cl_u1_nor3_4x spare28_nor3_4x (.in0(1'b0), | |
8879 | .in1(1'b0), | |
8880 | .in2(1'b0), | |
8881 | .out(spare28_nor3_4x_unused)); | |
8882 | cl_u1_nand2_8x spare28_nand2_8x (.in0(1'b1), | |
8883 | .in1(1'b1), | |
8884 | .out(spare28_nand2_8x_unused)); | |
8885 | cl_u1_buf_16x spare28_buf_16x (.in(1'b1), | |
8886 | .out(spare28_buf_16x_unused)); | |
8887 | cl_u1_nor2_16x spare28_nor2_16x (.in0(1'b0), | |
8888 | .in1(1'b0), | |
8889 | .out(spare28_nor2_16x_unused)); | |
8890 | cl_u1_inv_32x spare28_inv_32x (.in(1'b1), | |
8891 | .out(spare28_inv_32x_unused)); | |
8892 | ||
8893 | cl_sc1_msff_8x spare29_flop (.l1clk(l1clk), | |
8894 | .siclk(siclk), | |
8895 | .soclk(soclk), | |
8896 | .si(si_29), | |
8897 | .so(so_29), | |
8898 | .d(1'b0), | |
8899 | .q(spare29_flop_unused)); | |
8900 | assign si_29 = so_28; | |
8901 | ||
8902 | cl_u1_buf_32x spare29_buf_32x (.in(1'b1), | |
8903 | .out(spare29_buf_32x_unused)); | |
8904 | cl_u1_nand3_8x spare29_nand3_8x (.in0(1'b1), | |
8905 | .in1(1'b1), | |
8906 | .in2(1'b1), | |
8907 | .out(spare29_nand3_8x_unused)); | |
8908 | cl_u1_inv_8x spare29_inv_8x (.in(1'b1), | |
8909 | .out(spare29_inv_8x_unused)); | |
8910 | cl_u1_aoi22_4x spare29_aoi22_4x (.in00(1'b1), | |
8911 | .in01(1'b1), | |
8912 | .in10(1'b1), | |
8913 | .in11(1'b1), | |
8914 | .out(spare29_aoi22_4x_unused)); | |
8915 | cl_u1_buf_8x spare29_buf_8x (.in(1'b1), | |
8916 | .out(spare29_buf_8x_unused)); | |
8917 | cl_u1_oai22_4x spare29_oai22_4x (.in00(1'b1), | |
8918 | .in01(1'b1), | |
8919 | .in10(1'b1), | |
8920 | .in11(1'b1), | |
8921 | .out(spare29_oai22_4x_unused)); | |
8922 | cl_u1_inv_16x spare29_inv_16x (.in(1'b1), | |
8923 | .out(spare29_inv_16x_unused)); | |
8924 | cl_u1_nand2_16x spare29_nand2_16x (.in0(1'b1), | |
8925 | .in1(1'b1), | |
8926 | .out(spare29_nand2_16x_unused)); | |
8927 | cl_u1_nor3_4x spare29_nor3_4x (.in0(1'b0), | |
8928 | .in1(1'b0), | |
8929 | .in2(1'b0), | |
8930 | .out(spare29_nor3_4x_unused)); | |
8931 | cl_u1_nand2_8x spare29_nand2_8x (.in0(1'b1), | |
8932 | .in1(1'b1), | |
8933 | .out(spare29_nand2_8x_unused)); | |
8934 | cl_u1_buf_16x spare29_buf_16x (.in(1'b1), | |
8935 | .out(spare29_buf_16x_unused)); | |
8936 | cl_u1_nor2_16x spare29_nor2_16x (.in0(1'b0), | |
8937 | .in1(1'b0), | |
8938 | .out(spare29_nor2_16x_unused)); | |
8939 | cl_u1_inv_32x spare29_inv_32x (.in(1'b1), | |
8940 | .out(spare29_inv_32x_unused)); | |
8941 | ||
8942 | cl_sc1_msff_8x spare30_flop (.l1clk(l1clk), | |
8943 | .siclk(siclk), | |
8944 | .soclk(soclk), | |
8945 | .si(si_30), | |
8946 | .so(so_30), | |
8947 | .d(1'b0), | |
8948 | .q(spare30_flop_unused)); | |
8949 | assign si_30 = so_29; | |
8950 | ||
8951 | cl_u1_buf_32x spare30_buf_32x (.in(1'b1), | |
8952 | .out(spare30_buf_32x_unused)); | |
8953 | cl_u1_nand3_8x spare30_nand3_8x (.in0(1'b1), | |
8954 | .in1(1'b1), | |
8955 | .in2(1'b1), | |
8956 | .out(spare30_nand3_8x_unused)); | |
8957 | cl_u1_inv_8x spare30_inv_8x (.in(1'b1), | |
8958 | .out(spare30_inv_8x_unused)); | |
8959 | cl_u1_aoi22_4x spare30_aoi22_4x (.in00(1'b1), | |
8960 | .in01(1'b1), | |
8961 | .in10(1'b1), | |
8962 | .in11(1'b1), | |
8963 | .out(spare30_aoi22_4x_unused)); | |
8964 | cl_u1_buf_8x spare30_buf_8x (.in(1'b1), | |
8965 | .out(spare30_buf_8x_unused)); | |
8966 | cl_u1_oai22_4x spare30_oai22_4x (.in00(1'b1), | |
8967 | .in01(1'b1), | |
8968 | .in10(1'b1), | |
8969 | .in11(1'b1), | |
8970 | .out(spare30_oai22_4x_unused)); | |
8971 | cl_u1_inv_16x spare30_inv_16x (.in(1'b1), | |
8972 | .out(spare30_inv_16x_unused)); | |
8973 | cl_u1_nand2_16x spare30_nand2_16x (.in0(1'b1), | |
8974 | .in1(1'b1), | |
8975 | .out(spare30_nand2_16x_unused)); | |
8976 | cl_u1_nor3_4x spare30_nor3_4x (.in0(1'b0), | |
8977 | .in1(1'b0), | |
8978 | .in2(1'b0), | |
8979 | .out(spare30_nor3_4x_unused)); | |
8980 | cl_u1_nand2_8x spare30_nand2_8x (.in0(1'b1), | |
8981 | .in1(1'b1), | |
8982 | .out(spare30_nand2_8x_unused)); | |
8983 | cl_u1_buf_16x spare30_buf_16x (.in(1'b1), | |
8984 | .out(spare30_buf_16x_unused)); | |
8985 | cl_u1_nor2_16x spare30_nor2_16x (.in0(1'b0), | |
8986 | .in1(1'b0), | |
8987 | .out(spare30_nor2_16x_unused)); | |
8988 | cl_u1_inv_32x spare30_inv_32x (.in(1'b1), | |
8989 | .out(spare30_inv_32x_unused)); | |
8990 | ||
8991 | cl_sc1_msff_8x spare31_flop (.l1clk(l1clk), | |
8992 | .siclk(siclk), | |
8993 | .soclk(soclk), | |
8994 | .si(si_31), | |
8995 | .so(so_31), | |
8996 | .d(1'b0), | |
8997 | .q(spare31_flop_unused)); | |
8998 | assign si_31 = so_30; | |
8999 | ||
9000 | cl_u1_buf_32x spare31_buf_32x (.in(1'b1), | |
9001 | .out(spare31_buf_32x_unused)); | |
9002 | cl_u1_nand3_8x spare31_nand3_8x (.in0(1'b1), | |
9003 | .in1(1'b1), | |
9004 | .in2(1'b1), | |
9005 | .out(spare31_nand3_8x_unused)); | |
9006 | cl_u1_inv_8x spare31_inv_8x (.in(1'b1), | |
9007 | .out(spare31_inv_8x_unused)); | |
9008 | cl_u1_aoi22_4x spare31_aoi22_4x (.in00(1'b1), | |
9009 | .in01(1'b1), | |
9010 | .in10(1'b1), | |
9011 | .in11(1'b1), | |
9012 | .out(spare31_aoi22_4x_unused)); | |
9013 | cl_u1_buf_8x spare31_buf_8x (.in(1'b1), | |
9014 | .out(spare31_buf_8x_unused)); | |
9015 | cl_u1_oai22_4x spare31_oai22_4x (.in00(1'b1), | |
9016 | .in01(1'b1), | |
9017 | .in10(1'b1), | |
9018 | .in11(1'b1), | |
9019 | .out(spare31_oai22_4x_unused)); | |
9020 | cl_u1_inv_16x spare31_inv_16x (.in(1'b1), | |
9021 | .out(spare31_inv_16x_unused)); | |
9022 | cl_u1_nand2_16x spare31_nand2_16x (.in0(1'b1), | |
9023 | .in1(1'b1), | |
9024 | .out(spare31_nand2_16x_unused)); | |
9025 | cl_u1_nor3_4x spare31_nor3_4x (.in0(1'b0), | |
9026 | .in1(1'b0), | |
9027 | .in2(1'b0), | |
9028 | .out(spare31_nor3_4x_unused)); | |
9029 | cl_u1_nand2_8x spare31_nand2_8x (.in0(1'b1), | |
9030 | .in1(1'b1), | |
9031 | .out(spare31_nand2_8x_unused)); | |
9032 | cl_u1_buf_16x spare31_buf_16x (.in(1'b1), | |
9033 | .out(spare31_buf_16x_unused)); | |
9034 | cl_u1_nor2_16x spare31_nor2_16x (.in0(1'b0), | |
9035 | .in1(1'b0), | |
9036 | .out(spare31_nor2_16x_unused)); | |
9037 | cl_u1_inv_32x spare31_inv_32x (.in(1'b1), | |
9038 | .out(spare31_inv_32x_unused)); | |
9039 | ||
9040 | cl_sc1_msff_8x spare32_flop (.l1clk(l1clk), | |
9041 | .siclk(siclk), | |
9042 | .soclk(soclk), | |
9043 | .si(si_32), | |
9044 | .so(so_32), | |
9045 | .d(1'b0), | |
9046 | .q(spare32_flop_unused)); | |
9047 | assign si_32 = so_31; | |
9048 | ||
9049 | cl_u1_buf_32x spare32_buf_32x (.in(1'b1), | |
9050 | .out(spare32_buf_32x_unused)); | |
9051 | cl_u1_nand3_8x spare32_nand3_8x (.in0(1'b1), | |
9052 | .in1(1'b1), | |
9053 | .in2(1'b1), | |
9054 | .out(spare32_nand3_8x_unused)); | |
9055 | cl_u1_inv_8x spare32_inv_8x (.in(1'b1), | |
9056 | .out(spare32_inv_8x_unused)); | |
9057 | cl_u1_aoi22_4x spare32_aoi22_4x (.in00(1'b1), | |
9058 | .in01(1'b1), | |
9059 | .in10(1'b1), | |
9060 | .in11(1'b1), | |
9061 | .out(spare32_aoi22_4x_unused)); | |
9062 | cl_u1_buf_8x spare32_buf_8x (.in(1'b1), | |
9063 | .out(spare32_buf_8x_unused)); | |
9064 | cl_u1_oai22_4x spare32_oai22_4x (.in00(1'b1), | |
9065 | .in01(1'b1), | |
9066 | .in10(1'b1), | |
9067 | .in11(1'b1), | |
9068 | .out(spare32_oai22_4x_unused)); | |
9069 | cl_u1_inv_16x spare32_inv_16x (.in(1'b1), | |
9070 | .out(spare32_inv_16x_unused)); | |
9071 | cl_u1_nand2_16x spare32_nand2_16x (.in0(1'b1), | |
9072 | .in1(1'b1), | |
9073 | .out(spare32_nand2_16x_unused)); | |
9074 | cl_u1_nor3_4x spare32_nor3_4x (.in0(1'b0), | |
9075 | .in1(1'b0), | |
9076 | .in2(1'b0), | |
9077 | .out(spare32_nor3_4x_unused)); | |
9078 | cl_u1_nand2_8x spare32_nand2_8x (.in0(1'b1), | |
9079 | .in1(1'b1), | |
9080 | .out(spare32_nand2_8x_unused)); | |
9081 | cl_u1_buf_16x spare32_buf_16x (.in(1'b1), | |
9082 | .out(spare32_buf_16x_unused)); | |
9083 | cl_u1_nor2_16x spare32_nor2_16x (.in0(1'b0), | |
9084 | .in1(1'b0), | |
9085 | .out(spare32_nor2_16x_unused)); | |
9086 | cl_u1_inv_32x spare32_inv_32x (.in(1'b1), | |
9087 | .out(spare32_inv_32x_unused)); | |
9088 | ||
9089 | cl_sc1_msff_8x spare33_flop (.l1clk(l1clk), | |
9090 | .siclk(siclk), | |
9091 | .soclk(soclk), | |
9092 | .si(si_33), | |
9093 | .so(so_33), | |
9094 | .d(1'b0), | |
9095 | .q(spare33_flop_unused)); | |
9096 | assign si_33 = so_32; | |
9097 | ||
9098 | cl_u1_buf_32x spare33_buf_32x (.in(1'b1), | |
9099 | .out(spare33_buf_32x_unused)); | |
9100 | cl_u1_nand3_8x spare33_nand3_8x (.in0(1'b1), | |
9101 | .in1(1'b1), | |
9102 | .in2(1'b1), | |
9103 | .out(spare33_nand3_8x_unused)); | |
9104 | cl_u1_inv_8x spare33_inv_8x (.in(1'b1), | |
9105 | .out(spare33_inv_8x_unused)); | |
9106 | cl_u1_aoi22_4x spare33_aoi22_4x (.in00(1'b1), | |
9107 | .in01(1'b1), | |
9108 | .in10(1'b1), | |
9109 | .in11(1'b1), | |
9110 | .out(spare33_aoi22_4x_unused)); | |
9111 | cl_u1_buf_8x spare33_buf_8x (.in(1'b1), | |
9112 | .out(spare33_buf_8x_unused)); | |
9113 | cl_u1_oai22_4x spare33_oai22_4x (.in00(1'b1), | |
9114 | .in01(1'b1), | |
9115 | .in10(1'b1), | |
9116 | .in11(1'b1), | |
9117 | .out(spare33_oai22_4x_unused)); | |
9118 | cl_u1_inv_16x spare33_inv_16x (.in(1'b1), | |
9119 | .out(spare33_inv_16x_unused)); | |
9120 | cl_u1_nand2_16x spare33_nand2_16x (.in0(1'b1), | |
9121 | .in1(1'b1), | |
9122 | .out(spare33_nand2_16x_unused)); | |
9123 | cl_u1_nor3_4x spare33_nor3_4x (.in0(1'b0), | |
9124 | .in1(1'b0), | |
9125 | .in2(1'b0), | |
9126 | .out(spare33_nor3_4x_unused)); | |
9127 | cl_u1_nand2_8x spare33_nand2_8x (.in0(1'b1), | |
9128 | .in1(1'b1), | |
9129 | .out(spare33_nand2_8x_unused)); | |
9130 | cl_u1_buf_16x spare33_buf_16x (.in(1'b1), | |
9131 | .out(spare33_buf_16x_unused)); | |
9132 | cl_u1_nor2_16x spare33_nor2_16x (.in0(1'b0), | |
9133 | .in1(1'b0), | |
9134 | .out(spare33_nor2_16x_unused)); | |
9135 | cl_u1_inv_32x spare33_inv_32x (.in(1'b1), | |
9136 | .out(spare33_inv_32x_unused)); | |
9137 | ||
9138 | cl_sc1_msff_8x spare34_flop (.l1clk(l1clk), | |
9139 | .siclk(siclk), | |
9140 | .soclk(soclk), | |
9141 | .si(si_34), | |
9142 | .so(so_34), | |
9143 | .d(1'b0), | |
9144 | .q(spare34_flop_unused)); | |
9145 | assign si_34 = so_33; | |
9146 | ||
9147 | cl_u1_buf_32x spare34_buf_32x (.in(1'b1), | |
9148 | .out(spare34_buf_32x_unused)); | |
9149 | cl_u1_nand3_8x spare34_nand3_8x (.in0(1'b1), | |
9150 | .in1(1'b1), | |
9151 | .in2(1'b1), | |
9152 | .out(spare34_nand3_8x_unused)); | |
9153 | cl_u1_inv_8x spare34_inv_8x (.in(1'b1), | |
9154 | .out(spare34_inv_8x_unused)); | |
9155 | cl_u1_aoi22_4x spare34_aoi22_4x (.in00(1'b1), | |
9156 | .in01(1'b1), | |
9157 | .in10(1'b1), | |
9158 | .in11(1'b1), | |
9159 | .out(spare34_aoi22_4x_unused)); | |
9160 | cl_u1_buf_8x spare34_buf_8x (.in(1'b1), | |
9161 | .out(spare34_buf_8x_unused)); | |
9162 | cl_u1_oai22_4x spare34_oai22_4x (.in00(1'b1), | |
9163 | .in01(1'b1), | |
9164 | .in10(1'b1), | |
9165 | .in11(1'b1), | |
9166 | .out(spare34_oai22_4x_unused)); | |
9167 | cl_u1_inv_16x spare34_inv_16x (.in(1'b1), | |
9168 | .out(spare34_inv_16x_unused)); | |
9169 | cl_u1_nand2_16x spare34_nand2_16x (.in0(1'b1), | |
9170 | .in1(1'b1), | |
9171 | .out(spare34_nand2_16x_unused)); | |
9172 | cl_u1_nor3_4x spare34_nor3_4x (.in0(1'b0), | |
9173 | .in1(1'b0), | |
9174 | .in2(1'b0), | |
9175 | .out(spare34_nor3_4x_unused)); | |
9176 | cl_u1_nand2_8x spare34_nand2_8x (.in0(1'b1), | |
9177 | .in1(1'b1), | |
9178 | .out(spare34_nand2_8x_unused)); | |
9179 | cl_u1_buf_16x spare34_buf_16x (.in(1'b1), | |
9180 | .out(spare34_buf_16x_unused)); | |
9181 | cl_u1_nor2_16x spare34_nor2_16x (.in0(1'b0), | |
9182 | .in1(1'b0), | |
9183 | .out(spare34_nor2_16x_unused)); | |
9184 | cl_u1_inv_32x spare34_inv_32x (.in(1'b1), | |
9185 | .out(spare34_inv_32x_unused)); | |
9186 | ||
9187 | cl_sc1_msff_8x spare35_flop (.l1clk(l1clk), | |
9188 | .siclk(siclk), | |
9189 | .soclk(soclk), | |
9190 | .si(si_35), | |
9191 | .so(so_35), | |
9192 | .d(1'b0), | |
9193 | .q(spare35_flop_unused)); | |
9194 | assign si_35 = so_34; | |
9195 | ||
9196 | cl_u1_buf_32x spare35_buf_32x (.in(1'b1), | |
9197 | .out(spare35_buf_32x_unused)); | |
9198 | cl_u1_nand3_8x spare35_nand3_8x (.in0(1'b1), | |
9199 | .in1(1'b1), | |
9200 | .in2(1'b1), | |
9201 | .out(spare35_nand3_8x_unused)); | |
9202 | cl_u1_inv_8x spare35_inv_8x (.in(1'b1), | |
9203 | .out(spare35_inv_8x_unused)); | |
9204 | cl_u1_aoi22_4x spare35_aoi22_4x (.in00(1'b1), | |
9205 | .in01(1'b1), | |
9206 | .in10(1'b1), | |
9207 | .in11(1'b1), | |
9208 | .out(spare35_aoi22_4x_unused)); | |
9209 | cl_u1_buf_8x spare35_buf_8x (.in(1'b1), | |
9210 | .out(spare35_buf_8x_unused)); | |
9211 | cl_u1_oai22_4x spare35_oai22_4x (.in00(1'b1), | |
9212 | .in01(1'b1), | |
9213 | .in10(1'b1), | |
9214 | .in11(1'b1), | |
9215 | .out(spare35_oai22_4x_unused)); | |
9216 | cl_u1_inv_16x spare35_inv_16x (.in(1'b1), | |
9217 | .out(spare35_inv_16x_unused)); | |
9218 | cl_u1_nand2_16x spare35_nand2_16x (.in0(1'b1), | |
9219 | .in1(1'b1), | |
9220 | .out(spare35_nand2_16x_unused)); | |
9221 | cl_u1_nor3_4x spare35_nor3_4x (.in0(1'b0), | |
9222 | .in1(1'b0), | |
9223 | .in2(1'b0), | |
9224 | .out(spare35_nor3_4x_unused)); | |
9225 | cl_u1_nand2_8x spare35_nand2_8x (.in0(1'b1), | |
9226 | .in1(1'b1), | |
9227 | .out(spare35_nand2_8x_unused)); | |
9228 | cl_u1_buf_16x spare35_buf_16x (.in(1'b1), | |
9229 | .out(spare35_buf_16x_unused)); | |
9230 | cl_u1_nor2_16x spare35_nor2_16x (.in0(1'b0), | |
9231 | .in1(1'b0), | |
9232 | .out(spare35_nor2_16x_unused)); | |
9233 | cl_u1_inv_32x spare35_inv_32x (.in(1'b1), | |
9234 | .out(spare35_inv_32x_unused)); | |
9235 | ||
9236 | cl_sc1_msff_8x spare36_flop (.l1clk(l1clk), | |
9237 | .siclk(siclk), | |
9238 | .soclk(soclk), | |
9239 | .si(si_36), | |
9240 | .so(so_36), | |
9241 | .d(1'b0), | |
9242 | .q(spare36_flop_unused)); | |
9243 | assign si_36 = so_35; | |
9244 | ||
9245 | cl_u1_buf_32x spare36_buf_32x (.in(1'b1), | |
9246 | .out(spare36_buf_32x_unused)); | |
9247 | cl_u1_nand3_8x spare36_nand3_8x (.in0(1'b1), | |
9248 | .in1(1'b1), | |
9249 | .in2(1'b1), | |
9250 | .out(spare36_nand3_8x_unused)); | |
9251 | cl_u1_inv_8x spare36_inv_8x (.in(1'b1), | |
9252 | .out(spare36_inv_8x_unused)); | |
9253 | cl_u1_aoi22_4x spare36_aoi22_4x (.in00(1'b1), | |
9254 | .in01(1'b1), | |
9255 | .in10(1'b1), | |
9256 | .in11(1'b1), | |
9257 | .out(spare36_aoi22_4x_unused)); | |
9258 | cl_u1_buf_8x spare36_buf_8x (.in(1'b1), | |
9259 | .out(spare36_buf_8x_unused)); | |
9260 | cl_u1_oai22_4x spare36_oai22_4x (.in00(1'b1), | |
9261 | .in01(1'b1), | |
9262 | .in10(1'b1), | |
9263 | .in11(1'b1), | |
9264 | .out(spare36_oai22_4x_unused)); | |
9265 | cl_u1_inv_16x spare36_inv_16x (.in(1'b1), | |
9266 | .out(spare36_inv_16x_unused)); | |
9267 | cl_u1_nand2_16x spare36_nand2_16x (.in0(1'b1), | |
9268 | .in1(1'b1), | |
9269 | .out(spare36_nand2_16x_unused)); | |
9270 | cl_u1_nor3_4x spare36_nor3_4x (.in0(1'b0), | |
9271 | .in1(1'b0), | |
9272 | .in2(1'b0), | |
9273 | .out(spare36_nor3_4x_unused)); | |
9274 | cl_u1_nand2_8x spare36_nand2_8x (.in0(1'b1), | |
9275 | .in1(1'b1), | |
9276 | .out(spare36_nand2_8x_unused)); | |
9277 | cl_u1_buf_16x spare36_buf_16x (.in(1'b1), | |
9278 | .out(spare36_buf_16x_unused)); | |
9279 | cl_u1_nor2_16x spare36_nor2_16x (.in0(1'b0), | |
9280 | .in1(1'b0), | |
9281 | .out(spare36_nor2_16x_unused)); | |
9282 | cl_u1_inv_32x spare36_inv_32x (.in(1'b1), | |
9283 | .out(spare36_inv_32x_unused)); | |
9284 | ||
9285 | cl_sc1_msff_8x spare37_flop (.l1clk(l1clk), | |
9286 | .siclk(siclk), | |
9287 | .soclk(soclk), | |
9288 | .si(si_37), | |
9289 | .so(so_37), | |
9290 | .d(1'b0), | |
9291 | .q(spare37_flop_unused)); | |
9292 | assign si_37 = so_36; | |
9293 | ||
9294 | cl_u1_buf_32x spare37_buf_32x (.in(1'b1), | |
9295 | .out(spare37_buf_32x_unused)); | |
9296 | cl_u1_nand3_8x spare37_nand3_8x (.in0(1'b1), | |
9297 | .in1(1'b1), | |
9298 | .in2(1'b1), | |
9299 | .out(spare37_nand3_8x_unused)); | |
9300 | cl_u1_inv_8x spare37_inv_8x (.in(1'b1), | |
9301 | .out(spare37_inv_8x_unused)); | |
9302 | cl_u1_aoi22_4x spare37_aoi22_4x (.in00(1'b1), | |
9303 | .in01(1'b1), | |
9304 | .in10(1'b1), | |
9305 | .in11(1'b1), | |
9306 | .out(spare37_aoi22_4x_unused)); | |
9307 | cl_u1_buf_8x spare37_buf_8x (.in(1'b1), | |
9308 | .out(spare37_buf_8x_unused)); | |
9309 | cl_u1_oai22_4x spare37_oai22_4x (.in00(1'b1), | |
9310 | .in01(1'b1), | |
9311 | .in10(1'b1), | |
9312 | .in11(1'b1), | |
9313 | .out(spare37_oai22_4x_unused)); | |
9314 | cl_u1_inv_16x spare37_inv_16x (.in(1'b1), | |
9315 | .out(spare37_inv_16x_unused)); | |
9316 | cl_u1_nand2_16x spare37_nand2_16x (.in0(1'b1), | |
9317 | .in1(1'b1), | |
9318 | .out(spare37_nand2_16x_unused)); | |
9319 | cl_u1_nor3_4x spare37_nor3_4x (.in0(1'b0), | |
9320 | .in1(1'b0), | |
9321 | .in2(1'b0), | |
9322 | .out(spare37_nor3_4x_unused)); | |
9323 | cl_u1_nand2_8x spare37_nand2_8x (.in0(1'b1), | |
9324 | .in1(1'b1), | |
9325 | .out(spare37_nand2_8x_unused)); | |
9326 | cl_u1_buf_16x spare37_buf_16x (.in(1'b1), | |
9327 | .out(spare37_buf_16x_unused)); | |
9328 | cl_u1_nor2_16x spare37_nor2_16x (.in0(1'b0), | |
9329 | .in1(1'b0), | |
9330 | .out(spare37_nor2_16x_unused)); | |
9331 | cl_u1_inv_32x spare37_inv_32x (.in(1'b1), | |
9332 | .out(spare37_inv_32x_unused)); | |
9333 | ||
9334 | cl_sc1_msff_8x spare38_flop (.l1clk(l1clk), | |
9335 | .siclk(siclk), | |
9336 | .soclk(soclk), | |
9337 | .si(si_38), | |
9338 | .so(so_38), | |
9339 | .d(1'b0), | |
9340 | .q(spare38_flop_unused)); | |
9341 | assign si_38 = so_37; | |
9342 | ||
9343 | cl_u1_buf_32x spare38_buf_32x (.in(1'b1), | |
9344 | .out(spare38_buf_32x_unused)); | |
9345 | cl_u1_nand3_8x spare38_nand3_8x (.in0(1'b1), | |
9346 | .in1(1'b1), | |
9347 | .in2(1'b1), | |
9348 | .out(spare38_nand3_8x_unused)); | |
9349 | cl_u1_inv_8x spare38_inv_8x (.in(1'b1), | |
9350 | .out(spare38_inv_8x_unused)); | |
9351 | cl_u1_aoi22_4x spare38_aoi22_4x (.in00(1'b1), | |
9352 | .in01(1'b1), | |
9353 | .in10(1'b1), | |
9354 | .in11(1'b1), | |
9355 | .out(spare38_aoi22_4x_unused)); | |
9356 | cl_u1_buf_8x spare38_buf_8x (.in(1'b1), | |
9357 | .out(spare38_buf_8x_unused)); | |
9358 | cl_u1_oai22_4x spare38_oai22_4x (.in00(1'b1), | |
9359 | .in01(1'b1), | |
9360 | .in10(1'b1), | |
9361 | .in11(1'b1), | |
9362 | .out(spare38_oai22_4x_unused)); | |
9363 | cl_u1_inv_16x spare38_inv_16x (.in(1'b1), | |
9364 | .out(spare38_inv_16x_unused)); | |
9365 | cl_u1_nand2_16x spare38_nand2_16x (.in0(1'b1), | |
9366 | .in1(1'b1), | |
9367 | .out(spare38_nand2_16x_unused)); | |
9368 | cl_u1_nor3_4x spare38_nor3_4x (.in0(1'b0), | |
9369 | .in1(1'b0), | |
9370 | .in2(1'b0), | |
9371 | .out(spare38_nor3_4x_unused)); | |
9372 | cl_u1_nand2_8x spare38_nand2_8x (.in0(1'b1), | |
9373 | .in1(1'b1), | |
9374 | .out(spare38_nand2_8x_unused)); | |
9375 | cl_u1_buf_16x spare38_buf_16x (.in(1'b1), | |
9376 | .out(spare38_buf_16x_unused)); | |
9377 | cl_u1_nor2_16x spare38_nor2_16x (.in0(1'b0), | |
9378 | .in1(1'b0), | |
9379 | .out(spare38_nor2_16x_unused)); | |
9380 | cl_u1_inv_32x spare38_inv_32x (.in(1'b1), | |
9381 | .out(spare38_inv_32x_unused)); | |
9382 | ||
9383 | cl_sc1_msff_8x spare39_flop (.l1clk(l1clk), | |
9384 | .siclk(siclk), | |
9385 | .soclk(soclk), | |
9386 | .si(si_39), | |
9387 | .so(so_39), | |
9388 | .d(1'b0), | |
9389 | .q(spare39_flop_unused)); | |
9390 | assign si_39 = so_38; | |
9391 | ||
9392 | cl_u1_buf_32x spare39_buf_32x (.in(1'b1), | |
9393 | .out(spare39_buf_32x_unused)); | |
9394 | cl_u1_nand3_8x spare39_nand3_8x (.in0(1'b1), | |
9395 | .in1(1'b1), | |
9396 | .in2(1'b1), | |
9397 | .out(spare39_nand3_8x_unused)); | |
9398 | cl_u1_inv_8x spare39_inv_8x (.in(1'b1), | |
9399 | .out(spare39_inv_8x_unused)); | |
9400 | cl_u1_aoi22_4x spare39_aoi22_4x (.in00(1'b1), | |
9401 | .in01(1'b1), | |
9402 | .in10(1'b1), | |
9403 | .in11(1'b1), | |
9404 | .out(spare39_aoi22_4x_unused)); | |
9405 | cl_u1_buf_8x spare39_buf_8x (.in(1'b1), | |
9406 | .out(spare39_buf_8x_unused)); | |
9407 | cl_u1_oai22_4x spare39_oai22_4x (.in00(1'b1), | |
9408 | .in01(1'b1), | |
9409 | .in10(1'b1), | |
9410 | .in11(1'b1), | |
9411 | .out(spare39_oai22_4x_unused)); | |
9412 | cl_u1_inv_16x spare39_inv_16x (.in(1'b1), | |
9413 | .out(spare39_inv_16x_unused)); | |
9414 | cl_u1_nand2_16x spare39_nand2_16x (.in0(1'b1), | |
9415 | .in1(1'b1), | |
9416 | .out(spare39_nand2_16x_unused)); | |
9417 | cl_u1_nor3_4x spare39_nor3_4x (.in0(1'b0), | |
9418 | .in1(1'b0), | |
9419 | .in2(1'b0), | |
9420 | .out(spare39_nor3_4x_unused)); | |
9421 | cl_u1_nand2_8x spare39_nand2_8x (.in0(1'b1), | |
9422 | .in1(1'b1), | |
9423 | .out(spare39_nand2_8x_unused)); | |
9424 | cl_u1_buf_16x spare39_buf_16x (.in(1'b1), | |
9425 | .out(spare39_buf_16x_unused)); | |
9426 | cl_u1_nor2_16x spare39_nor2_16x (.in0(1'b0), | |
9427 | .in1(1'b0), | |
9428 | .out(spare39_nor2_16x_unused)); | |
9429 | cl_u1_inv_32x spare39_inv_32x (.in(1'b1), | |
9430 | .out(spare39_inv_32x_unused)); | |
9431 | ||
9432 | cl_sc1_msff_8x spare40_flop (.l1clk(l1clk), | |
9433 | .siclk(siclk), | |
9434 | .soclk(soclk), | |
9435 | .si(si_40), | |
9436 | .so(so_40), | |
9437 | .d(1'b0), | |
9438 | .q(spare40_flop_unused)); | |
9439 | assign si_40 = so_39; | |
9440 | ||
9441 | cl_u1_buf_32x spare40_buf_32x (.in(1'b1), | |
9442 | .out(spare40_buf_32x_unused)); | |
9443 | cl_u1_nand3_8x spare40_nand3_8x (.in0(1'b1), | |
9444 | .in1(1'b1), | |
9445 | .in2(1'b1), | |
9446 | .out(spare40_nand3_8x_unused)); | |
9447 | cl_u1_inv_8x spare40_inv_8x (.in(1'b1), | |
9448 | .out(spare40_inv_8x_unused)); | |
9449 | cl_u1_aoi22_4x spare40_aoi22_4x (.in00(1'b1), | |
9450 | .in01(1'b1), | |
9451 | .in10(1'b1), | |
9452 | .in11(1'b1), | |
9453 | .out(spare40_aoi22_4x_unused)); | |
9454 | cl_u1_buf_8x spare40_buf_8x (.in(1'b1), | |
9455 | .out(spare40_buf_8x_unused)); | |
9456 | cl_u1_oai22_4x spare40_oai22_4x (.in00(1'b1), | |
9457 | .in01(1'b1), | |
9458 | .in10(1'b1), | |
9459 | .in11(1'b1), | |
9460 | .out(spare40_oai22_4x_unused)); | |
9461 | cl_u1_inv_16x spare40_inv_16x (.in(1'b1), | |
9462 | .out(spare40_inv_16x_unused)); | |
9463 | cl_u1_nand2_16x spare40_nand2_16x (.in0(1'b1), | |
9464 | .in1(1'b1), | |
9465 | .out(spare40_nand2_16x_unused)); | |
9466 | cl_u1_nor3_4x spare40_nor3_4x (.in0(1'b0), | |
9467 | .in1(1'b0), | |
9468 | .in2(1'b0), | |
9469 | .out(spare40_nor3_4x_unused)); | |
9470 | cl_u1_nand2_8x spare40_nand2_8x (.in0(1'b1), | |
9471 | .in1(1'b1), | |
9472 | .out(spare40_nand2_8x_unused)); | |
9473 | cl_u1_buf_16x spare40_buf_16x (.in(1'b1), | |
9474 | .out(spare40_buf_16x_unused)); | |
9475 | cl_u1_nor2_16x spare40_nor2_16x (.in0(1'b0), | |
9476 | .in1(1'b0), | |
9477 | .out(spare40_nor2_16x_unused)); | |
9478 | cl_u1_inv_32x spare40_inv_32x (.in(1'b1), | |
9479 | .out(spare40_inv_32x_unused)); | |
9480 | ||
9481 | cl_sc1_msff_8x spare41_flop (.l1clk(l1clk), | |
9482 | .siclk(siclk), | |
9483 | .soclk(soclk), | |
9484 | .si(si_41), | |
9485 | .so(so_41), | |
9486 | .d(1'b0), | |
9487 | .q(spare41_flop_unused)); | |
9488 | assign si_41 = so_40; | |
9489 | ||
9490 | cl_u1_buf_32x spare41_buf_32x (.in(1'b1), | |
9491 | .out(spare41_buf_32x_unused)); | |
9492 | cl_u1_nand3_8x spare41_nand3_8x (.in0(1'b1), | |
9493 | .in1(1'b1), | |
9494 | .in2(1'b1), | |
9495 | .out(spare41_nand3_8x_unused)); | |
9496 | cl_u1_inv_8x spare41_inv_8x (.in(1'b1), | |
9497 | .out(spare41_inv_8x_unused)); | |
9498 | cl_u1_aoi22_4x spare41_aoi22_4x (.in00(1'b1), | |
9499 | .in01(1'b1), | |
9500 | .in10(1'b1), | |
9501 | .in11(1'b1), | |
9502 | .out(spare41_aoi22_4x_unused)); | |
9503 | cl_u1_buf_8x spare41_buf_8x (.in(1'b1), | |
9504 | .out(spare41_buf_8x_unused)); | |
9505 | cl_u1_oai22_4x spare41_oai22_4x (.in00(1'b1), | |
9506 | .in01(1'b1), | |
9507 | .in10(1'b1), | |
9508 | .in11(1'b1), | |
9509 | .out(spare41_oai22_4x_unused)); | |
9510 | cl_u1_inv_16x spare41_inv_16x (.in(1'b1), | |
9511 | .out(spare41_inv_16x_unused)); | |
9512 | cl_u1_nand2_16x spare41_nand2_16x (.in0(1'b1), | |
9513 | .in1(1'b1), | |
9514 | .out(spare41_nand2_16x_unused)); | |
9515 | cl_u1_nor3_4x spare41_nor3_4x (.in0(1'b0), | |
9516 | .in1(1'b0), | |
9517 | .in2(1'b0), | |
9518 | .out(spare41_nor3_4x_unused)); | |
9519 | cl_u1_nand2_8x spare41_nand2_8x (.in0(1'b1), | |
9520 | .in1(1'b1), | |
9521 | .out(spare41_nand2_8x_unused)); | |
9522 | cl_u1_buf_16x spare41_buf_16x (.in(1'b1), | |
9523 | .out(spare41_buf_16x_unused)); | |
9524 | cl_u1_nor2_16x spare41_nor2_16x (.in0(1'b0), | |
9525 | .in1(1'b0), | |
9526 | .out(spare41_nor2_16x_unused)); | |
9527 | cl_u1_inv_32x spare41_inv_32x (.in(1'b1), | |
9528 | .out(spare41_inv_32x_unused)); | |
9529 | ||
9530 | cl_sc1_msff_8x spare42_flop (.l1clk(l1clk), | |
9531 | .siclk(siclk), | |
9532 | .soclk(soclk), | |
9533 | .si(si_42), | |
9534 | .so(so_42), | |
9535 | .d(1'b0), | |
9536 | .q(spare42_flop_unused)); | |
9537 | assign si_42 = so_41; | |
9538 | ||
9539 | cl_u1_buf_32x spare42_buf_32x (.in(1'b1), | |
9540 | .out(spare42_buf_32x_unused)); | |
9541 | cl_u1_nand3_8x spare42_nand3_8x (.in0(1'b1), | |
9542 | .in1(1'b1), | |
9543 | .in2(1'b1), | |
9544 | .out(spare42_nand3_8x_unused)); | |
9545 | cl_u1_inv_8x spare42_inv_8x (.in(1'b1), | |
9546 | .out(spare42_inv_8x_unused)); | |
9547 | cl_u1_aoi22_4x spare42_aoi22_4x (.in00(1'b1), | |
9548 | .in01(1'b1), | |
9549 | .in10(1'b1), | |
9550 | .in11(1'b1), | |
9551 | .out(spare42_aoi22_4x_unused)); | |
9552 | cl_u1_buf_8x spare42_buf_8x (.in(1'b1), | |
9553 | .out(spare42_buf_8x_unused)); | |
9554 | cl_u1_oai22_4x spare42_oai22_4x (.in00(1'b1), | |
9555 | .in01(1'b1), | |
9556 | .in10(1'b1), | |
9557 | .in11(1'b1), | |
9558 | .out(spare42_oai22_4x_unused)); | |
9559 | cl_u1_inv_16x spare42_inv_16x (.in(1'b1), | |
9560 | .out(spare42_inv_16x_unused)); | |
9561 | cl_u1_nand2_16x spare42_nand2_16x (.in0(1'b1), | |
9562 | .in1(1'b1), | |
9563 | .out(spare42_nand2_16x_unused)); | |
9564 | cl_u1_nor3_4x spare42_nor3_4x (.in0(1'b0), | |
9565 | .in1(1'b0), | |
9566 | .in2(1'b0), | |
9567 | .out(spare42_nor3_4x_unused)); | |
9568 | cl_u1_nand2_8x spare42_nand2_8x (.in0(1'b1), | |
9569 | .in1(1'b1), | |
9570 | .out(spare42_nand2_8x_unused)); | |
9571 | cl_u1_buf_16x spare42_buf_16x (.in(1'b1), | |
9572 | .out(spare42_buf_16x_unused)); | |
9573 | cl_u1_nor2_16x spare42_nor2_16x (.in0(1'b0), | |
9574 | .in1(1'b0), | |
9575 | .out(spare42_nor2_16x_unused)); | |
9576 | cl_u1_inv_32x spare42_inv_32x (.in(1'b1), | |
9577 | .out(spare42_inv_32x_unused)); | |
9578 | ||
9579 | cl_sc1_msff_8x spare43_flop (.l1clk(l1clk), | |
9580 | .siclk(siclk), | |
9581 | .soclk(soclk), | |
9582 | .si(si_43), | |
9583 | .so(so_43), | |
9584 | .d(1'b0), | |
9585 | .q(spare43_flop_unused)); | |
9586 | assign si_43 = so_42; | |
9587 | ||
9588 | cl_u1_buf_32x spare43_buf_32x (.in(1'b1), | |
9589 | .out(spare43_buf_32x_unused)); | |
9590 | cl_u1_nand3_8x spare43_nand3_8x (.in0(1'b1), | |
9591 | .in1(1'b1), | |
9592 | .in2(1'b1), | |
9593 | .out(spare43_nand3_8x_unused)); | |
9594 | cl_u1_inv_8x spare43_inv_8x (.in(1'b1), | |
9595 | .out(spare43_inv_8x_unused)); | |
9596 | cl_u1_aoi22_4x spare43_aoi22_4x (.in00(1'b1), | |
9597 | .in01(1'b1), | |
9598 | .in10(1'b1), | |
9599 | .in11(1'b1), | |
9600 | .out(spare43_aoi22_4x_unused)); | |
9601 | cl_u1_buf_8x spare43_buf_8x (.in(1'b1), | |
9602 | .out(spare43_buf_8x_unused)); | |
9603 | cl_u1_oai22_4x spare43_oai22_4x (.in00(1'b1), | |
9604 | .in01(1'b1), | |
9605 | .in10(1'b1), | |
9606 | .in11(1'b1), | |
9607 | .out(spare43_oai22_4x_unused)); | |
9608 | cl_u1_inv_16x spare43_inv_16x (.in(1'b1), | |
9609 | .out(spare43_inv_16x_unused)); | |
9610 | cl_u1_nand2_16x spare43_nand2_16x (.in0(1'b1), | |
9611 | .in1(1'b1), | |
9612 | .out(spare43_nand2_16x_unused)); | |
9613 | cl_u1_nor3_4x spare43_nor3_4x (.in0(1'b0), | |
9614 | .in1(1'b0), | |
9615 | .in2(1'b0), | |
9616 | .out(spare43_nor3_4x_unused)); | |
9617 | cl_u1_nand2_8x spare43_nand2_8x (.in0(1'b1), | |
9618 | .in1(1'b1), | |
9619 | .out(spare43_nand2_8x_unused)); | |
9620 | cl_u1_buf_16x spare43_buf_16x (.in(1'b1), | |
9621 | .out(spare43_buf_16x_unused)); | |
9622 | cl_u1_nor2_16x spare43_nor2_16x (.in0(1'b0), | |
9623 | .in1(1'b0), | |
9624 | .out(spare43_nor2_16x_unused)); | |
9625 | cl_u1_inv_32x spare43_inv_32x (.in(1'b1), | |
9626 | .out(spare43_inv_32x_unused)); | |
9627 | ||
9628 | cl_sc1_msff_8x spare44_flop (.l1clk(l1clk), | |
9629 | .siclk(siclk), | |
9630 | .soclk(soclk), | |
9631 | .si(si_44), | |
9632 | .so(so_44), | |
9633 | .d(1'b0), | |
9634 | .q(spare44_flop_unused)); | |
9635 | assign si_44 = so_43; | |
9636 | ||
9637 | cl_u1_buf_32x spare44_buf_32x (.in(1'b1), | |
9638 | .out(spare44_buf_32x_unused)); | |
9639 | cl_u1_nand3_8x spare44_nand3_8x (.in0(1'b1), | |
9640 | .in1(1'b1), | |
9641 | .in2(1'b1), | |
9642 | .out(spare44_nand3_8x_unused)); | |
9643 | cl_u1_inv_8x spare44_inv_8x (.in(1'b1), | |
9644 | .out(spare44_inv_8x_unused)); | |
9645 | cl_u1_aoi22_4x spare44_aoi22_4x (.in00(1'b1), | |
9646 | .in01(1'b1), | |
9647 | .in10(1'b1), | |
9648 | .in11(1'b1), | |
9649 | .out(spare44_aoi22_4x_unused)); | |
9650 | cl_u1_buf_8x spare44_buf_8x (.in(1'b1), | |
9651 | .out(spare44_buf_8x_unused)); | |
9652 | cl_u1_oai22_4x spare44_oai22_4x (.in00(1'b1), | |
9653 | .in01(1'b1), | |
9654 | .in10(1'b1), | |
9655 | .in11(1'b1), | |
9656 | .out(spare44_oai22_4x_unused)); | |
9657 | cl_u1_inv_16x spare44_inv_16x (.in(1'b1), | |
9658 | .out(spare44_inv_16x_unused)); | |
9659 | cl_u1_nand2_16x spare44_nand2_16x (.in0(1'b1), | |
9660 | .in1(1'b1), | |
9661 | .out(spare44_nand2_16x_unused)); | |
9662 | cl_u1_nor3_4x spare44_nor3_4x (.in0(1'b0), | |
9663 | .in1(1'b0), | |
9664 | .in2(1'b0), | |
9665 | .out(spare44_nor3_4x_unused)); | |
9666 | cl_u1_nand2_8x spare44_nand2_8x (.in0(1'b1), | |
9667 | .in1(1'b1), | |
9668 | .out(spare44_nand2_8x_unused)); | |
9669 | cl_u1_buf_16x spare44_buf_16x (.in(1'b1), | |
9670 | .out(spare44_buf_16x_unused)); | |
9671 | cl_u1_nor2_16x spare44_nor2_16x (.in0(1'b0), | |
9672 | .in1(1'b0), | |
9673 | .out(spare44_nor2_16x_unused)); | |
9674 | cl_u1_inv_32x spare44_inv_32x (.in(1'b1), | |
9675 | .out(spare44_inv_32x_unused)); | |
9676 | ||
9677 | cl_sc1_msff_8x spare45_flop (.l1clk(l1clk), | |
9678 | .siclk(siclk), | |
9679 | .soclk(soclk), | |
9680 | .si(si_45), | |
9681 | .so(so_45), | |
9682 | .d(1'b0), | |
9683 | .q(spare45_flop_unused)); | |
9684 | assign si_45 = so_44; | |
9685 | ||
9686 | cl_u1_buf_32x spare45_buf_32x (.in(1'b1), | |
9687 | .out(spare45_buf_32x_unused)); | |
9688 | cl_u1_nand3_8x spare45_nand3_8x (.in0(1'b1), | |
9689 | .in1(1'b1), | |
9690 | .in2(1'b1), | |
9691 | .out(spare45_nand3_8x_unused)); | |
9692 | cl_u1_inv_8x spare45_inv_8x (.in(1'b1), | |
9693 | .out(spare45_inv_8x_unused)); | |
9694 | cl_u1_aoi22_4x spare45_aoi22_4x (.in00(1'b1), | |
9695 | .in01(1'b1), | |
9696 | .in10(1'b1), | |
9697 | .in11(1'b1), | |
9698 | .out(spare45_aoi22_4x_unused)); | |
9699 | cl_u1_buf_8x spare45_buf_8x (.in(1'b1), | |
9700 | .out(spare45_buf_8x_unused)); | |
9701 | cl_u1_oai22_4x spare45_oai22_4x (.in00(1'b1), | |
9702 | .in01(1'b1), | |
9703 | .in10(1'b1), | |
9704 | .in11(1'b1), | |
9705 | .out(spare45_oai22_4x_unused)); | |
9706 | cl_u1_inv_16x spare45_inv_16x (.in(1'b1), | |
9707 | .out(spare45_inv_16x_unused)); | |
9708 | cl_u1_nand2_16x spare45_nand2_16x (.in0(1'b1), | |
9709 | .in1(1'b1), | |
9710 | .out(spare45_nand2_16x_unused)); | |
9711 | cl_u1_nor3_4x spare45_nor3_4x (.in0(1'b0), | |
9712 | .in1(1'b0), | |
9713 | .in2(1'b0), | |
9714 | .out(spare45_nor3_4x_unused)); | |
9715 | cl_u1_nand2_8x spare45_nand2_8x (.in0(1'b1), | |
9716 | .in1(1'b1), | |
9717 | .out(spare45_nand2_8x_unused)); | |
9718 | cl_u1_buf_16x spare45_buf_16x (.in(1'b1), | |
9719 | .out(spare45_buf_16x_unused)); | |
9720 | cl_u1_nor2_16x spare45_nor2_16x (.in0(1'b0), | |
9721 | .in1(1'b0), | |
9722 | .out(spare45_nor2_16x_unused)); | |
9723 | cl_u1_inv_32x spare45_inv_32x (.in(1'b1), | |
9724 | .out(spare45_inv_32x_unused)); | |
9725 | ||
9726 | cl_sc1_msff_8x spare46_flop (.l1clk(l1clk), | |
9727 | .siclk(siclk), | |
9728 | .soclk(soclk), | |
9729 | .si(si_46), | |
9730 | .so(so_46), | |
9731 | .d(1'b0), | |
9732 | .q(spare46_flop_unused)); | |
9733 | assign si_46 = so_45; | |
9734 | ||
9735 | cl_u1_buf_32x spare46_buf_32x (.in(1'b1), | |
9736 | .out(spare46_buf_32x_unused)); | |
9737 | cl_u1_nand3_8x spare46_nand3_8x (.in0(1'b1), | |
9738 | .in1(1'b1), | |
9739 | .in2(1'b1), | |
9740 | .out(spare46_nand3_8x_unused)); | |
9741 | cl_u1_inv_8x spare46_inv_8x (.in(1'b1), | |
9742 | .out(spare46_inv_8x_unused)); | |
9743 | cl_u1_aoi22_4x spare46_aoi22_4x (.in00(1'b1), | |
9744 | .in01(1'b1), | |
9745 | .in10(1'b1), | |
9746 | .in11(1'b1), | |
9747 | .out(spare46_aoi22_4x_unused)); | |
9748 | cl_u1_buf_8x spare46_buf_8x (.in(1'b1), | |
9749 | .out(spare46_buf_8x_unused)); | |
9750 | cl_u1_oai22_4x spare46_oai22_4x (.in00(1'b1), | |
9751 | .in01(1'b1), | |
9752 | .in10(1'b1), | |
9753 | .in11(1'b1), | |
9754 | .out(spare46_oai22_4x_unused)); | |
9755 | cl_u1_inv_16x spare46_inv_16x (.in(1'b1), | |
9756 | .out(spare46_inv_16x_unused)); | |
9757 | cl_u1_nand2_16x spare46_nand2_16x (.in0(1'b1), | |
9758 | .in1(1'b1), | |
9759 | .out(spare46_nand2_16x_unused)); | |
9760 | cl_u1_nor3_4x spare46_nor3_4x (.in0(1'b0), | |
9761 | .in1(1'b0), | |
9762 | .in2(1'b0), | |
9763 | .out(spare46_nor3_4x_unused)); | |
9764 | cl_u1_nand2_8x spare46_nand2_8x (.in0(1'b1), | |
9765 | .in1(1'b1), | |
9766 | .out(spare46_nand2_8x_unused)); | |
9767 | cl_u1_buf_16x spare46_buf_16x (.in(1'b1), | |
9768 | .out(spare46_buf_16x_unused)); | |
9769 | cl_u1_nor2_16x spare46_nor2_16x (.in0(1'b0), | |
9770 | .in1(1'b0), | |
9771 | .out(spare46_nor2_16x_unused)); | |
9772 | cl_u1_inv_32x spare46_inv_32x (.in(1'b1), | |
9773 | .out(spare46_inv_32x_unused)); | |
9774 | ||
9775 | cl_sc1_msff_8x spare47_flop (.l1clk(l1clk), | |
9776 | .siclk(siclk), | |
9777 | .soclk(soclk), | |
9778 | .si(si_47), | |
9779 | .so(so_47), | |
9780 | .d(1'b0), | |
9781 | .q(spare47_flop_unused)); | |
9782 | assign si_47 = so_46; | |
9783 | ||
9784 | cl_u1_buf_32x spare47_buf_32x (.in(1'b1), | |
9785 | .out(spare47_buf_32x_unused)); | |
9786 | cl_u1_nand3_8x spare47_nand3_8x (.in0(1'b1), | |
9787 | .in1(1'b1), | |
9788 | .in2(1'b1), | |
9789 | .out(spare47_nand3_8x_unused)); | |
9790 | cl_u1_inv_8x spare47_inv_8x (.in(1'b1), | |
9791 | .out(spare47_inv_8x_unused)); | |
9792 | cl_u1_aoi22_4x spare47_aoi22_4x (.in00(1'b1), | |
9793 | .in01(1'b1), | |
9794 | .in10(1'b1), | |
9795 | .in11(1'b1), | |
9796 | .out(spare47_aoi22_4x_unused)); | |
9797 | cl_u1_buf_8x spare47_buf_8x (.in(1'b1), | |
9798 | .out(spare47_buf_8x_unused)); | |
9799 | cl_u1_oai22_4x spare47_oai22_4x (.in00(1'b1), | |
9800 | .in01(1'b1), | |
9801 | .in10(1'b1), | |
9802 | .in11(1'b1), | |
9803 | .out(spare47_oai22_4x_unused)); | |
9804 | cl_u1_inv_16x spare47_inv_16x (.in(1'b1), | |
9805 | .out(spare47_inv_16x_unused)); | |
9806 | cl_u1_nand2_16x spare47_nand2_16x (.in0(1'b1), | |
9807 | .in1(1'b1), | |
9808 | .out(spare47_nand2_16x_unused)); | |
9809 | cl_u1_nor3_4x spare47_nor3_4x (.in0(1'b0), | |
9810 | .in1(1'b0), | |
9811 | .in2(1'b0), | |
9812 | .out(spare47_nor3_4x_unused)); | |
9813 | cl_u1_nand2_8x spare47_nand2_8x (.in0(1'b1), | |
9814 | .in1(1'b1), | |
9815 | .out(spare47_nand2_8x_unused)); | |
9816 | cl_u1_buf_16x spare47_buf_16x (.in(1'b1), | |
9817 | .out(spare47_buf_16x_unused)); | |
9818 | cl_u1_nor2_16x spare47_nor2_16x (.in0(1'b0), | |
9819 | .in1(1'b0), | |
9820 | .out(spare47_nor2_16x_unused)); | |
9821 | cl_u1_inv_32x spare47_inv_32x (.in(1'b1), | |
9822 | .out(spare47_inv_32x_unused)); | |
9823 | ||
9824 | cl_sc1_msff_8x spare48_flop (.l1clk(l1clk), | |
9825 | .siclk(siclk), | |
9826 | .soclk(soclk), | |
9827 | .si(si_48), | |
9828 | .so(so_48), | |
9829 | .d(1'b0), | |
9830 | .q(spare48_flop_unused)); | |
9831 | assign si_48 = so_47; | |
9832 | ||
9833 | cl_u1_buf_32x spare48_buf_32x (.in(1'b1), | |
9834 | .out(spare48_buf_32x_unused)); | |
9835 | cl_u1_nand3_8x spare48_nand3_8x (.in0(1'b1), | |
9836 | .in1(1'b1), | |
9837 | .in2(1'b1), | |
9838 | .out(spare48_nand3_8x_unused)); | |
9839 | cl_u1_inv_8x spare48_inv_8x (.in(1'b1), | |
9840 | .out(spare48_inv_8x_unused)); | |
9841 | cl_u1_aoi22_4x spare48_aoi22_4x (.in00(1'b1), | |
9842 | .in01(1'b1), | |
9843 | .in10(1'b1), | |
9844 | .in11(1'b1), | |
9845 | .out(spare48_aoi22_4x_unused)); | |
9846 | cl_u1_buf_8x spare48_buf_8x (.in(1'b1), | |
9847 | .out(spare48_buf_8x_unused)); | |
9848 | cl_u1_oai22_4x spare48_oai22_4x (.in00(1'b1), | |
9849 | .in01(1'b1), | |
9850 | .in10(1'b1), | |
9851 | .in11(1'b1), | |
9852 | .out(spare48_oai22_4x_unused)); | |
9853 | cl_u1_inv_16x spare48_inv_16x (.in(1'b1), | |
9854 | .out(spare48_inv_16x_unused)); | |
9855 | cl_u1_nand2_16x spare48_nand2_16x (.in0(1'b1), | |
9856 | .in1(1'b1), | |
9857 | .out(spare48_nand2_16x_unused)); | |
9858 | cl_u1_nor3_4x spare48_nor3_4x (.in0(1'b0), | |
9859 | .in1(1'b0), | |
9860 | .in2(1'b0), | |
9861 | .out(spare48_nor3_4x_unused)); | |
9862 | cl_u1_nand2_8x spare48_nand2_8x (.in0(1'b1), | |
9863 | .in1(1'b1), | |
9864 | .out(spare48_nand2_8x_unused)); | |
9865 | cl_u1_buf_16x spare48_buf_16x (.in(1'b1), | |
9866 | .out(spare48_buf_16x_unused)); | |
9867 | cl_u1_nor2_16x spare48_nor2_16x (.in0(1'b0), | |
9868 | .in1(1'b0), | |
9869 | .out(spare48_nor2_16x_unused)); | |
9870 | cl_u1_inv_32x spare48_inv_32x (.in(1'b1), | |
9871 | .out(spare48_inv_32x_unused)); | |
9872 | assign spares_scanout = so_48; | |
9873 | ||
9874 | ||
9875 | ||
9876 | ||
9877 | // CLEANUP | |
9878 | assign drif_scrub_write_req = drif_err_wr_picked; // for mcusat | |
9879 | assign drif_tot_ranks[2:0] = 3'h0; | |
9880 | assign drif_power_down_mode = 1'b0; | |
9881 | assign mcu_ddp_clk_enable = 1'b0; | |
9882 | ||
9883 | // fixscan start: | |
9884 | assign ff_ucb_req_scanin = scan_in ; | |
9885 | assign ff_hw_selfref_scanin = ff_ucb_req_scanout ; | |
9886 | assign ff_sync_frame_req_l_scanin = ff_hw_selfref_scanout ; | |
9887 | assign dmmdly0_scanin = ff_sync_frame_req_l_scanout; | |
9888 | assign dmmdly1_scanin = dmmdly0_scanout ; | |
9889 | assign dmmdly2_scanin = dmmdly1_scanout ; | |
9890 | assign dmmdly3_scanin = dmmdly2_scanout ; | |
9891 | assign dmmdly4_scanin = dmmdly3_scanout ; | |
9892 | assign dmmdly5_scanin = dmmdly4_scanout ; | |
9893 | assign dmmdly6_scanin = dmmdly5_scanout ; | |
9894 | assign dmmdly7_scanin = dmmdly6_scanout ; | |
9895 | assign ff_rfc_cnt_scanin = dmmdly7_scanout ; | |
9896 | assign ff_rd_rrd_cnt_scanin = ff_rfc_cnt_scanout ; | |
9897 | assign bnksm0_scanin = ff_rd_rrd_cnt_scanout ; | |
9898 | assign bnksm1_scanin = bnksm0_scanout ; | |
9899 | assign bnksm2_scanin = bnksm1_scanout ; | |
9900 | assign bnksm3_scanin = bnksm2_scanout ; | |
9901 | assign bnksm4_scanin = bnksm3_scanout ; | |
9902 | assign bnksm5_scanin = bnksm4_scanout ; | |
9903 | assign bnksm6_scanin = bnksm5_scanout ; | |
9904 | assign bnksm7_scanin = bnksm6_scanout ; | |
9905 | assign bnksm8_scanin = bnksm7_scanout ; | |
9906 | assign bnksm9_scanin = bnksm8_scanout ; | |
9907 | assign bnksm10_scanin = bnksm9_scanout ; | |
9908 | assign bnksm11_scanin = bnksm10_scanout ; | |
9909 | assign bnksm12_scanin = bnksm11_scanout ; | |
9910 | assign bnksm13_scanin = bnksm12_scanout ; | |
9911 | assign bnksm14_scanin = bnksm13_scanout ; | |
9912 | assign bnksm15_scanin = bnksm14_scanout ; | |
9913 | assign ff_entry_priority_scanin = bnksm15_scanout ; | |
9914 | assign ff_cas_abnk_picked_scanin = ff_entry_priority_scanout; | |
9915 | assign ff_cas_bcbnk_picked_scanin = ff_cas_abnk_picked_scanout; | |
9916 | assign ff_rank_dimm_picked_scanin = ff_cas_bcbnk_picked_scanout; | |
9917 | assign ff_ras_picked_d2_scanin = ff_rank_dimm_picked_scanout; | |
9918 | assign ff_wr_entry_pend_scanin = ff_ras_picked_d2_scanout ; | |
9919 | assign ff_raw_match_scanin = ff_wr_entry_pend_scanout ; | |
9920 | assign ff_cmd_picked_d1_scanin = ff_raw_match_scanout ; | |
9921 | assign ff_scrub_picked_d1_scanin = ff_cmd_picked_d1_scanout ; | |
9922 | assign ff_addr_parity_d1_scanin = ff_scrub_picked_d1_scanout; | |
9923 | assign ff_addr_err_d1_scanin = ff_addr_parity_d1_scanout; | |
9924 | assign ff_wr_starve_cnt0_scanin = ff_addr_err_d1_scanout ; | |
9925 | assign ff_pick_wr_first0_scanin = ff_wr_starve_cnt0_scanout; | |
9926 | assign ff_wr_starve_cnt1_scanin = ff_pick_wr_first0_scanout; | |
9927 | assign ff_pick_wr_first1_scanin = ff_wr_starve_cnt1_scanout; | |
9928 | assign ff_cas_picked_scanin = ff_pick_wr_first1_scanout; | |
9929 | assign ff_ras_adr_d1_scanin = ff_cas_picked_scanout ; | |
9930 | assign ff_cas_adr_d1_scanin = ff_ras_adr_d1_scanout ; | |
9931 | assign ff_req_id_d1_scanin = ff_cas_adr_d1_scanout ; | |
9932 | assign ff_cas_adr_d2_scanin = ff_req_id_d1_scanout ; | |
9933 | assign ff_bank_adr_scanin = ff_cas_adr_d2_scanout ; | |
9934 | assign ff_dimm_adr_scanin = ff_bank_adr_scanout ; | |
9935 | assign ff_rank_adr_scanin = ff_dimm_adr_scanout ; | |
9936 | assign ff_mux_wr_en_scanin = ff_rank_adr_scanout ; | |
9937 | assign ff_cmd_val_scanin = ff_mux_wr_en_scanout ; | |
9938 | assign ff_cmd_val_d1_scanin = ff_cmd_val_scanout ; | |
9939 | assign ff_wr1_adr_d1_scanin = ff_cmd_val_d1_scanout ; | |
9940 | assign ff_write1_data_scanin = ff_wr1_adr_d1_scanout ; | |
9941 | assign ff_wr1_adr_d2_scanin = ff_write1_data_scanout ; | |
9942 | assign ff_write2_data_scanin = ff_wr1_adr_d2_scanout ; | |
9943 | assign ff_wr2_adr_d1_scanin = ff_write2_data_scanout ; | |
9944 | assign ff_wr2_adr_d2_scanin = ff_wr2_adr_d1_scanout ; | |
9945 | assign ff_wdata_wsn_scanin = ff_wr2_adr_d2_scanout ; | |
9946 | assign ff_rd_wr_picked_d1_scanin = ff_wdata_wsn_scanout ; | |
9947 | assign ff0_wr_entry0_scanin = ff_rd_wr_picked_d1_scanout; | |
9948 | assign ff1_wr_entry0_scanin = ff0_wr_entry0_scanout ; | |
9949 | assign ff_wdq_sel_scanin = ff1_wr_entry0_scanout ; | |
9950 | assign ff_scrub_data_rden_scanin = ff_wdq_sel_scanout ; | |
9951 | assign ff_scrub_buffer_cnt_scanin = ff_scrub_data_rden_scanout; | |
9952 | assign ff_multi_err_scanin = ff_scrub_buffer_cnt_scanout; | |
9953 | assign ff_error_write_flag_scanin = ff_multi_err_scanout ; | |
9954 | assign ff_scrub_data_rden_en_d1_scanin = ff_error_write_flag_scanout; | |
9955 | assign ff_err_wrdata_ready_scanin = ff_scrub_data_rden_en_d1_scanout; | |
9956 | assign ff_wadr_parity_scanin = ff_err_wrdata_ready_scanout; | |
9957 | assign ff_rd_index_d1_scanin = ff_wadr_parity_scanout ; | |
9958 | assign ff_err_fifo_err_type_d1_scanin = ff_rd_index_d1_scanout ; | |
9959 | assign ff_mcu_state_enc_scanin = ff_err_fifo_err_type_d1_scanout; | |
9960 | assign ff_cyc_cnt_scanin = ff_mcu_state_enc_scanout ; | |
9961 | assign ff_mrd_cnt_scanin = ff_cyc_cnt_scanout ; | |
9962 | assign ff_rp_cnt_scanin = ff_mrd_cnt_scanout ; | |
9963 | assign ff_bank_idle_cnt_scanin = ff_rp_cnt_scanout ; | |
9964 | assign ff_refresh_rank_scanin = ff_bank_idle_cnt_scanout ; | |
9965 | assign ff_enter_self_refresh_scanin = ff_refresh_rank_scanout ; | |
9966 | assign ff_exit_self_refresh_scanin = ff_enter_self_refresh_scanout; | |
9967 | assign ff_l2_poison_qw_scanin = ff_exit_self_refresh_scanout; | |
9968 | assign ff_mem_type_scanin = ff_l2_poison_qw_scanout ; | |
9969 | assign ff_init_scanin = ff_mem_type_scanout ; | |
9970 | assign ff_single_channel_mode_pend_scanin = ff_init_scanout ; | |
9971 | assign ff_cke_enable_scanin = ff_single_channel_mode_pend_scanout; | |
9972 | assign ff_dal_reg_scanin = ff_cke_enable_scanout ; | |
9973 | assign ff_ral_reg_scanin = ff_dal_reg_scanout ; | |
9974 | assign ff_precharge_wait_scanin = ff_ral_reg_scanout ; | |
9975 | assign ff_wdq_sel_d1_scanin = ff_precharge_wait_scanout; | |
9976 | assign ff_ref_cnt_scanin = ff_wdq_sel_d1_scanout ; | |
9977 | assign ff_l0_state_d1_scanin = ff_ref_cnt_scanout ; | |
9978 | assign ff_scrub_cnt_scanin = ff_l0_state_d1_scanout ; | |
9979 | assign ff_scrub_read_pending_scanin = ff_scrub_cnt_scanout ; | |
9980 | assign ff_scrub_read_out_scanin = ff_scrub_read_pending_scanout; | |
9981 | assign ff_scrub_read_pending_en_d1_scanin = ff_scrub_read_out_scanout; | |
9982 | assign ff_pt_sync_out_d1_scanin = ff_scrub_read_pending_en_d1_scanout; | |
9983 | assign ff_pt_sync_out_scanin = ff_pt_sync_out_d1_scanout; | |
9984 | assign ff_pt_sync_scanin = ff_pt_sync_out_scanout ; | |
9985 | assign ff_banks_open_scanin = ff_pt_sync_scanout ; | |
9986 | assign ff_time_cntr_scanin = ff_banks_open_scanout ; | |
9987 | assign ff_blk_openbank_scanin = ff_time_cntr_scanout ; | |
9988 | assign ff_wr_mode_reg_scanin = ff_blk_openbank_scanout ; | |
9989 | assign ff_init_done_scanin = ff_wr_mode_reg_scanout ; | |
9990 | assign ff_init_status_reg_scanin = ff_init_done_scanout ; | |
9991 | assign ff_ucb_data_scanin = ff_init_status_reg_scanout; | |
9992 | assign ff_pd_mode_enable_scanin = ff_ucb_data_scanout ; | |
9993 | assign ff_perf_cntl_reg_scanin = ff_pd_mode_enable_scanout; | |
9994 | assign ff_crit_sig_scanin = ff_perf_cntl_reg_scanout ; | |
9995 | assign ff_perf_cnt0_reg_scanin = ff_crit_sig_scanout ; | |
9996 | assign ff_perf_cnt1_reg_scanin = ff_perf_cnt0_reg_scanout ; | |
9997 | assign ff_raw_hazard_d1_scanin = ff_perf_cnt1_reg_scanout ; | |
9998 | assign ff_scrub_wren_scanin = ff_raw_hazard_d1_scanout ; | |
9999 | assign errq_scanin = ff_scrub_wren_scanout ; | |
10000 | assign ff_err_fifo_empty_d1_scanin = errq_scanout ; | |
10001 | assign ff_err_rd_picked_d1_scanin = ff_err_fifo_empty_d1_scanout; | |
10002 | assign ff_err_fifo_d1_scanin = ff_err_rd_picked_d1_scanout; | |
10003 | assign ff_crc_retry_wait_scanin = ff_err_fifo_d1_scanout ; | |
10004 | assign ff_err_state_scanin = ff_crc_retry_wait_scanout; | |
10005 | assign ff_mcu_error_mode_scanin = ff_err_state_scanout ; | |
10006 | assign reqq_scanin = ff_mcu_error_mode_scanout; | |
10007 | assign ff_scrub_addr_scanin = reqq_scanout ; | |
10008 | assign adrgen_scanin = ff_scrub_addr_scanout ; | |
10009 | assign pdmc0_scanin = adrgen_scanout ; | |
10010 | assign pdmc1_scanin = pdmc0_scanout ; | |
10011 | assign pdmc2_scanin = pdmc1_scanout ; | |
10012 | assign pdmc3_scanin = pdmc2_scanout ; | |
10013 | assign pdmc4_scanin = pdmc3_scanout ; | |
10014 | assign pdmc5_scanin = pdmc4_scanout ; | |
10015 | assign pdmc6_scanin = pdmc5_scanout ; | |
10016 | assign pdmc7_scanin = pdmc6_scanout ; | |
10017 | assign pdmc8_scanin = pdmc7_scanout ; | |
10018 | assign pdmc9_scanin = pdmc8_scanout ; | |
10019 | assign pdmc10_scanin = pdmc9_scanout ; | |
10020 | assign pdmc11_scanin = pdmc10_scanout ; | |
10021 | assign pdmc12_scanin = pdmc11_scanout ; | |
10022 | assign pdmc13_scanin = pdmc12_scanout ; | |
10023 | assign pdmc14_scanin = pdmc13_scanout ; | |
10024 | assign pdmc15_scanin = pdmc14_scanout ; | |
10025 | assign spares_scanin = pdmc15_scanout ; | |
10026 | assign scan_out = spares_scanout ; | |
10027 | ||
10028 | assign pff_mode_reg_wmr_scanin = wmr_scan_in ; | |
10029 | assign pff_ext_mode_reg1_wmr_scanin = pff_mode_reg_wmr_scanout ; | |
10030 | assign pff_ext_mode_reg2_wmr_scanin = pff_ext_mode_reg1_wmr_scanout; | |
10031 | assign pff_ext_mode_reg3_wmr_scanin = pff_ext_mode_reg2_wmr_scanout; | |
10032 | assign pff_stacked_dimm_wmr_scanin = pff_ext_mode_reg3_wmr_scanout; | |
10033 | assign pff_cas_addr_bits_wmr_scanin = pff_stacked_dimm_wmr_scanout; | |
10034 | assign pff_ras_addr_bits_wmr_scanin = pff_cas_addr_bits_wmr_scanout; | |
10035 | assign pff_freq_scrub_wmr_scanin = pff_ras_addr_bits_wmr_scanout; | |
10036 | assign pff_dimms_present_wmr_scanin = pff_freq_scrub_wmr_scanout; | |
10037 | assign pff_branch_disabled_wmr_scanin = pff_dimms_present_wmr_scanout; | |
10038 | assign pff_bank_low_sel_wmr_scanin = pff_branch_disabled_wmr_scanout; | |
10039 | assign pff_eight_bank_present_wmr_scanin = pff_bank_low_sel_wmr_scanout; | |
10040 | assign pff_single_channel_mode_wmr_scanin = pff_eight_bank_present_wmr_scanout; | |
10041 | assign pff_fail_over_mode_wmr_scanin = pff_single_channel_mode_wmr_scanout; | |
10042 | assign pff_fail_over_mask_wmr_scanin = pff_fail_over_mode_wmr_scanout; | |
10043 | assign pff_rrd_reg_wmr_scanin = pff_fail_over_mask_wmr_scanout; | |
10044 | assign pff_rcd_reg_wmr_scanin = pff_rrd_reg_wmr_scanout ; | |
10045 | assign pff_iwtr_reg_wmr_scanin = pff_rcd_reg_wmr_scanout ; | |
10046 | assign pff_wtr_reg_wmr_scanin = pff_iwtr_reg_wmr_scanout ; | |
10047 | assign pff_rtw_reg_wmr_scanin = pff_wtr_reg_wmr_scanout ; | |
10048 | assign pff_rtp_reg_wmr_scanin = pff_rtw_reg_wmr_scanout ; | |
10049 | assign pff_ras_reg_wmr_scanin = pff_rtp_reg_wmr_scanout ; | |
10050 | assign pff_rp_reg_wmr_scanin = pff_ras_reg_wmr_scanout ; | |
10051 | assign pff_rc_reg_wmr_scanin = pff_rp_reg_wmr_scanout ; | |
10052 | assign pff_wr_reg_wmr_scanin = pff_rc_reg_wmr_scanout ; | |
10053 | assign pff_rfc_reg_wmr_scanin = pff_wr_reg_wmr_scanout ; | |
10054 | assign pff_mrd_reg_wmr_scanin = pff_rfc_reg_wmr_scanout ; | |
10055 | assign pff_faw_reg_wmr_scanin = pff_mrd_reg_wmr_scanout ; | |
10056 | assign pff_err_inj_wmr_scanin = pff_faw_reg_wmr_scanout ; | |
10057 | assign pff_sshot_wmr_scanin = pff_err_inj_wmr_scanout ; | |
10058 | assign pff_err_mask_wmr_scanin = pff_sshot_wmr_scanout ; | |
10059 | assign pff_ref_freq_wmr_scanin = pff_err_mask_wmr_scanout ; | |
10060 | assign pff_data_scrub_wmr_scanin = pff_ref_freq_wmr_scanout ; | |
10061 | assign pff_max_banks_open_wmr_scanin = pff_data_scrub_wmr_scanout; | |
10062 | assign pff_max_time_wmr_scanin = pff_max_banks_open_wmr_scanout; | |
10063 | assign wmr_scan_out = pff_max_time_wmr_scanout ; | |
10064 | // fixscan end: | |
10065 | endmodule | |
10066 | ||
10067 | ||
10068 | ||
10069 | ||
10070 | ||
10071 | ||
10072 | // any PARAMS parms go into naming of macro | |
10073 | ||
10074 | module mcu_drif_ctl_l1clkhdr_ctl_macro ( | |
10075 | l2clk, | |
10076 | l1en, | |
10077 | pce_ov, | |
10078 | stop, | |
10079 | se, | |
10080 | l1clk); | |
10081 | ||
10082 | ||
10083 | input l2clk; | |
10084 | input l1en; | |
10085 | input pce_ov; | |
10086 | input stop; | |
10087 | input se; | |
10088 | output l1clk; | |
10089 | ||
10090 | ||
10091 | ||
10092 | ||
10093 | ||
10094 | cl_sc1_l1hdr_8x c_0 ( | |
10095 | ||
10096 | ||
10097 | .l2clk(l2clk), | |
10098 | .pce(l1en), | |
10099 | .l1clk(l1clk), | |
10100 | .se(se), | |
10101 | .pce_ov(pce_ov), | |
10102 | .stop(stop) | |
10103 | ); | |
10104 | ||
10105 | ||
10106 | ||
10107 | endmodule | |
10108 | ||
10109 | ||
10110 | ||
10111 | ||
10112 | ||
10113 | ||
10114 | ||
10115 | ||
10116 | ||
10117 | ||
10118 | ||
10119 | ||
10120 | ||
10121 | // any PARAMS parms go into naming of macro | |
10122 | ||
10123 | module mcu_drif_ctl_msff_ctl_macro__width_79 ( | |
10124 | din, | |
10125 | l1clk, | |
10126 | scan_in, | |
10127 | siclk, | |
10128 | soclk, | |
10129 | dout, | |
10130 | scan_out); | |
10131 | wire [78:0] fdin; | |
10132 | wire [77:0] so; | |
10133 | ||
10134 | input [78:0] din; | |
10135 | input l1clk; | |
10136 | input scan_in; | |
10137 | ||
10138 | ||
10139 | input siclk; | |
10140 | input soclk; | |
10141 | ||
10142 | output [78:0] dout; | |
10143 | output scan_out; | |
10144 | assign fdin[78:0] = din[78:0]; | |
10145 | ||
10146 | ||
10147 | ||
10148 | ||
10149 | ||
10150 | ||
10151 | dff #(79) d0_0 ( | |
10152 | .l1clk(l1clk), | |
10153 | .siclk(siclk), | |
10154 | .soclk(soclk), | |
10155 | .d(fdin[78:0]), | |
10156 | .si({scan_in,so[77:0]}), | |
10157 | .so({so[77:0],scan_out}), | |
10158 | .q(dout[78:0]) | |
10159 | ); | |
10160 | ||
10161 | ||
10162 | ||
10163 | ||
10164 | ||
10165 | ||
10166 | ||
10167 | ||
10168 | ||
10169 | ||
10170 | ||
10171 | ||
10172 | endmodule | |
10173 | ||
10174 | ||
10175 | ||
10176 | ||
10177 | ||
10178 | ||
10179 | ||
10180 | ||
10181 | ||
10182 | ||
10183 | ||
10184 | ||
10185 | ||
10186 | // any PARAMS parms go into naming of macro | |
10187 | ||
10188 | module mcu_drif_ctl_msff_ctl_macro__width_1 ( | |
10189 | din, | |
10190 | l1clk, | |
10191 | scan_in, | |
10192 | siclk, | |
10193 | soclk, | |
10194 | dout, | |
10195 | scan_out); | |
10196 | wire [0:0] fdin; | |
10197 | ||
10198 | input [0:0] din; | |
10199 | input l1clk; | |
10200 | input scan_in; | |
10201 | ||
10202 | ||
10203 | input siclk; | |
10204 | input soclk; | |
10205 | ||
10206 | output [0:0] dout; | |
10207 | output scan_out; | |
10208 | assign fdin[0:0] = din[0:0]; | |
10209 | ||
10210 | ||
10211 | ||
10212 | ||
10213 | ||
10214 | ||
10215 | dff #(1) d0_0 ( | |
10216 | .l1clk(l1clk), | |
10217 | .siclk(siclk), | |
10218 | .soclk(soclk), | |
10219 | .d(fdin[0:0]), | |
10220 | .si(scan_in), | |
10221 | .so(scan_out), | |
10222 | .q(dout[0:0]) | |
10223 | ); | |
10224 | ||
10225 | ||
10226 | ||
10227 | ||
10228 | ||
10229 | ||
10230 | ||
10231 | ||
10232 | ||
10233 | ||
10234 | ||
10235 | ||
10236 | endmodule | |
10237 | ||
10238 | ||
10239 | ||
10240 | ||
10241 | ||
10242 | ||
10243 | ||
10244 | ||
10245 | ||
10246 | ||
10247 | ||
10248 | ||
10249 | ||
10250 | // any PARAMS parms go into naming of macro | |
10251 | ||
10252 | module mcu_drif_ctl_msff_ctl_macro__width_3 ( | |
10253 | din, | |
10254 | l1clk, | |
10255 | scan_in, | |
10256 | siclk, | |
10257 | soclk, | |
10258 | dout, | |
10259 | scan_out); | |
10260 | wire [2:0] fdin; | |
10261 | wire [1:0] so; | |
10262 | ||
10263 | input [2:0] din; | |
10264 | input l1clk; | |
10265 | input scan_in; | |
10266 | ||
10267 | ||
10268 | input siclk; | |
10269 | input soclk; | |
10270 | ||
10271 | output [2:0] dout; | |
10272 | output scan_out; | |
10273 | assign fdin[2:0] = din[2:0]; | |
10274 | ||
10275 | ||
10276 | ||
10277 | ||
10278 | ||
10279 | ||
10280 | dff #(3) d0_0 ( | |
10281 | .l1clk(l1clk), | |
10282 | .siclk(siclk), | |
10283 | .soclk(soclk), | |
10284 | .d(fdin[2:0]), | |
10285 | .si({scan_in,so[1:0]}), | |
10286 | .so({so[1:0],scan_out}), | |
10287 | .q(dout[2:0]) | |
10288 | ); | |
10289 | ||
10290 | ||
10291 | endmodule | |
10292 | ||
10293 | ||
10294 | ||
10295 | ||
10296 | ||
10297 | // any PARAMS parms go into naming of macro | |
10298 | ||
10299 | module mcu_drif_ctl_msff_ctl_macro__width_4 ( | |
10300 | din, | |
10301 | l1clk, | |
10302 | scan_in, | |
10303 | siclk, | |
10304 | soclk, | |
10305 | dout, | |
10306 | scan_out); | |
10307 | wire [3:0] fdin; | |
10308 | wire [2:0] so; | |
10309 | ||
10310 | input [3:0] din; | |
10311 | input l1clk; | |
10312 | input scan_in; | |
10313 | ||
10314 | ||
10315 | input siclk; | |
10316 | input soclk; | |
10317 | ||
10318 | output [3:0] dout; | |
10319 | output scan_out; | |
10320 | assign fdin[3:0] = din[3:0]; | |
10321 | ||
10322 | ||
10323 | ||
10324 | ||
10325 | ||
10326 | ||
10327 | dff #(4) d0_0 ( | |
10328 | .l1clk(l1clk), | |
10329 | .siclk(siclk), | |
10330 | .soclk(soclk), | |
10331 | .d(fdin[3:0]), | |
10332 | .si({scan_in,so[2:0]}), | |
10333 | .so({so[2:0],scan_out}), | |
10334 | .q(dout[3:0]) | |
10335 | ); | |
10336 | ||
10337 | ||
10338 | ||
10339 | ||
10340 | ||
10341 | ||
10342 | ||
10343 | ||
10344 | ||
10345 | ||
10346 | ||
10347 | ||
10348 | endmodule | |
10349 | ||
10350 | ||
10351 | ||
10352 | ||
10353 | ||
10354 | ||
10355 | ||
10356 | ||
10357 | ||
10358 | ||
10359 | ||
10360 | ||
10361 | ||
10362 | // any PARAMS parms go into naming of macro | |
10363 | ||
10364 | module mcu_drif_ctl_msff_ctl_macro__width_2 ( | |
10365 | din, | |
10366 | l1clk, | |
10367 | scan_in, | |
10368 | siclk, | |
10369 | soclk, | |
10370 | dout, | |
10371 | scan_out); | |
10372 | wire [1:0] fdin; | |
10373 | wire [0:0] so; | |
10374 | ||
10375 | input [1:0] din; | |
10376 | input l1clk; | |
10377 | input scan_in; | |
10378 | ||
10379 | ||
10380 | input siclk; | |
10381 | input soclk; | |
10382 | ||
10383 | output [1:0] dout; | |
10384 | output scan_out; | |
10385 | assign fdin[1:0] = din[1:0]; | |
10386 | ||
10387 | ||
10388 | ||
10389 | ||
10390 | ||
10391 | ||
10392 | dff #(2) d0_0 ( | |
10393 | .l1clk(l1clk), | |
10394 | .siclk(siclk), | |
10395 | .soclk(soclk), | |
10396 | .d(fdin[1:0]), | |
10397 | .si({scan_in,so[0:0]}), | |
10398 | .so({so[0:0],scan_out}), | |
10399 | .q(dout[1:0]) | |
10400 | ); | |
10401 | ||
10402 | ||
10403 | ||
10404 | ||
10405 | ||
10406 | ||
10407 | ||
10408 | ||
10409 | ||
10410 | ||
10411 | ||
10412 | ||
10413 | endmodule | |
10414 | ||
10415 | ||
10416 | ||
10417 | ||
10418 | ||
10419 | ||
10420 | ||
10421 | ||
10422 | ||
10423 | ||
10424 | ||
10425 | ||
10426 | ||
10427 | // any PARAMS parms go into naming of macro | |
10428 | ||
10429 | module mcu_drif_ctl_msff_ctl_macro__en_0__width_5 ( | |
10430 | din, | |
10431 | l1clk, | |
10432 | scan_in, | |
10433 | siclk, | |
10434 | soclk, | |
10435 | dout, | |
10436 | scan_out); | |
10437 | wire [4:0] fdin; | |
10438 | wire [3:0] so; | |
10439 | ||
10440 | input [4:0] din; | |
10441 | input l1clk; | |
10442 | input scan_in; | |
10443 | ||
10444 | ||
10445 | input siclk; | |
10446 | input soclk; | |
10447 | ||
10448 | output [4:0] dout; | |
10449 | output scan_out; | |
10450 | assign fdin[4:0] = din[4:0]; | |
10451 | ||
10452 | ||
10453 | ||
10454 | ||
10455 | ||
10456 | ||
10457 | dff #(5) d0_0 ( | |
10458 | .l1clk(l1clk), | |
10459 | .siclk(siclk), | |
10460 | .soclk(soclk), | |
10461 | .d(fdin[4:0]), | |
10462 | .si({scan_in,so[3:0]}), | |
10463 | .so({so[3:0],scan_out}), | |
10464 | .q(dout[4:0]) | |
10465 | ); | |
10466 | ||
10467 | ||
10468 | ||
10469 | ||
10470 | ||
10471 | ||
10472 | ||
10473 | ||
10474 | ||
10475 | ||
10476 | ||
10477 | ||
10478 | endmodule | |
10479 | ||
10480 | ||
10481 | ||
10482 | ||
10483 | ||
10484 | ||
10485 | ||
10486 | ||
10487 | ||
10488 | ||
10489 | ||
10490 | ||
10491 | ||
10492 | // any PARAMS parms go into naming of macro | |
10493 | ||
10494 | module mcu_drif_ctl_msff_ctl_macro__width_7 ( | |
10495 | din, | |
10496 | l1clk, | |
10497 | scan_in, | |
10498 | siclk, | |
10499 | soclk, | |
10500 | dout, | |
10501 | scan_out); | |
10502 | wire [6:0] fdin; | |
10503 | wire [5:0] so; | |
10504 | ||
10505 | input [6:0] din; | |
10506 | input l1clk; | |
10507 | input scan_in; | |
10508 | ||
10509 | ||
10510 | input siclk; | |
10511 | input soclk; | |
10512 | ||
10513 | output [6:0] dout; | |
10514 | output scan_out; | |
10515 | assign fdin[6:0] = din[6:0]; | |
10516 | ||
10517 | ||
10518 | ||
10519 | ||
10520 | ||
10521 | ||
10522 | dff #(7) d0_0 ( | |
10523 | .l1clk(l1clk), | |
10524 | .siclk(siclk), | |
10525 | .soclk(soclk), | |
10526 | .d(fdin[6:0]), | |
10527 | .si({scan_in,so[5:0]}), | |
10528 | .so({so[5:0],scan_out}), | |
10529 | .q(dout[6:0]) | |
10530 | ); | |
10531 | ||
10532 | ||
10533 | endmodule | |
10534 | ||
10535 | ||
10536 | ||
10537 | // any PARAMS parms go into naming of macro | |
10538 | ||
10539 | module mcu_drif_ctl_msff_ctl_macro__width_5 ( | |
10540 | din, | |
10541 | l1clk, | |
10542 | scan_in, | |
10543 | siclk, | |
10544 | soclk, | |
10545 | dout, | |
10546 | scan_out); | |
10547 | wire [4:0] fdin; | |
10548 | wire [3:0] so; | |
10549 | ||
10550 | input [4:0] din; | |
10551 | input l1clk; | |
10552 | input scan_in; | |
10553 | ||
10554 | ||
10555 | input siclk; | |
10556 | input soclk; | |
10557 | ||
10558 | output [4:0] dout; | |
10559 | output scan_out; | |
10560 | assign fdin[4:0] = din[4:0]; | |
10561 | ||
10562 | ||
10563 | ||
10564 | ||
10565 | ||
10566 | ||
10567 | dff #(5) d0_0 ( | |
10568 | .l1clk(l1clk), | |
10569 | .siclk(siclk), | |
10570 | .soclk(soclk), | |
10571 | .d(fdin[4:0]), | |
10572 | .si({scan_in,so[3:0]}), | |
10573 | .so({so[3:0],scan_out}), | |
10574 | .q(dout[4:0]) | |
10575 | ); | |
10576 | ||
10577 | ||
10578 | ||
10579 | ||
10580 | ||
10581 | ||
10582 | ||
10583 | ||
10584 | ||
10585 | ||
10586 | ||
10587 | ||
10588 | endmodule | |
10589 | ||
10590 | ||
10591 | ||
10592 | ||
10593 | ||
10594 | ||
10595 | ||
10596 | ||
10597 | ||
10598 | ||
10599 | ||
10600 | ||
10601 | ||
10602 | // any PARAMS parms go into naming of macro | |
10603 | ||
10604 | module mcu_drif_ctl_msff_ctl_macro ( | |
10605 | din, | |
10606 | l1clk, | |
10607 | scan_in, | |
10608 | siclk, | |
10609 | soclk, | |
10610 | dout, | |
10611 | scan_out); | |
10612 | wire [0:0] fdin; | |
10613 | ||
10614 | input [0:0] din; | |
10615 | input l1clk; | |
10616 | input scan_in; | |
10617 | ||
10618 | ||
10619 | input siclk; | |
10620 | input soclk; | |
10621 | ||
10622 | output [0:0] dout; | |
10623 | output scan_out; | |
10624 | assign fdin[0:0] = din[0:0]; | |
10625 | ||
10626 | ||
10627 | ||
10628 | ||
10629 | ||
10630 | ||
10631 | dff #(1) d0_0 ( | |
10632 | .l1clk(l1clk), | |
10633 | .siclk(siclk), | |
10634 | .soclk(soclk), | |
10635 | .d(fdin[0:0]), | |
10636 | .si(scan_in), | |
10637 | .so(scan_out), | |
10638 | .q(dout[0:0]) | |
10639 | ); | |
10640 | ||
10641 | ||
10642 | ||
10643 | ||
10644 | ||
10645 | ||
10646 | ||
10647 | ||
10648 | ||
10649 | ||
10650 | ||
10651 | ||
10652 | endmodule | |
10653 | ||
10654 | ||
10655 | ||
10656 | ||
10657 | ||
10658 | ||
10659 | ||
10660 | ||
10661 | ||
10662 | ||
10663 | ||
10664 | ||
10665 | ||
10666 | // any PARAMS parms go into naming of macro | |
10667 | ||
10668 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_16 ( | |
10669 | din, | |
10670 | en, | |
10671 | l1clk, | |
10672 | scan_in, | |
10673 | siclk, | |
10674 | soclk, | |
10675 | dout, | |
10676 | scan_out); | |
10677 | wire [15:0] fdin; | |
10678 | wire [14:0] so; | |
10679 | ||
10680 | input [15:0] din; | |
10681 | input en; | |
10682 | input l1clk; | |
10683 | input scan_in; | |
10684 | ||
10685 | ||
10686 | input siclk; | |
10687 | input soclk; | |
10688 | ||
10689 | output [15:0] dout; | |
10690 | output scan_out; | |
10691 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); | |
10692 | ||
10693 | ||
10694 | ||
10695 | ||
10696 | ||
10697 | ||
10698 | dff #(16) d0_0 ( | |
10699 | .l1clk(l1clk), | |
10700 | .siclk(siclk), | |
10701 | .soclk(soclk), | |
10702 | .d(fdin[15:0]), | |
10703 | .si({scan_in,so[14:0]}), | |
10704 | .so({so[14:0],scan_out}), | |
10705 | .q(dout[15:0]) | |
10706 | ); | |
10707 | ||
10708 | ||
10709 | ||
10710 | ||
10711 | ||
10712 | ||
10713 | ||
10714 | ||
10715 | ||
10716 | ||
10717 | ||
10718 | ||
10719 | endmodule | |
10720 | ||
10721 | ||
10722 | ||
10723 | ||
10724 | ||
10725 | ||
10726 | ||
10727 | ||
10728 | ||
10729 | ||
10730 | ||
10731 | ||
10732 | ||
10733 | // any PARAMS parms go into naming of macro | |
10734 | ||
10735 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_4 ( | |
10736 | din, | |
10737 | en, | |
10738 | l1clk, | |
10739 | scan_in, | |
10740 | siclk, | |
10741 | soclk, | |
10742 | dout, | |
10743 | scan_out); | |
10744 | wire [3:0] fdin; | |
10745 | wire [2:0] so; | |
10746 | ||
10747 | input [3:0] din; | |
10748 | input en; | |
10749 | input l1clk; | |
10750 | input scan_in; | |
10751 | ||
10752 | ||
10753 | input siclk; | |
10754 | input soclk; | |
10755 | ||
10756 | output [3:0] dout; | |
10757 | output scan_out; | |
10758 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
10759 | ||
10760 | ||
10761 | ||
10762 | ||
10763 | ||
10764 | ||
10765 | dff #(4) d0_0 ( | |
10766 | .l1clk(l1clk), | |
10767 | .siclk(siclk), | |
10768 | .soclk(soclk), | |
10769 | .d(fdin[3:0]), | |
10770 | .si({scan_in,so[2:0]}), | |
10771 | .so({so[2:0],scan_out}), | |
10772 | .q(dout[3:0]) | |
10773 | ); | |
10774 | ||
10775 | ||
10776 | ||
10777 | ||
10778 | ||
10779 | ||
10780 | ||
10781 | ||
10782 | ||
10783 | ||
10784 | ||
10785 | ||
10786 | endmodule | |
10787 | ||
10788 | ||
10789 | ||
10790 | ||
10791 | ||
10792 | ||
10793 | ||
10794 | ||
10795 | ||
10796 | ||
10797 | ||
10798 | ||
10799 | ||
10800 | // any PARAMS parms go into naming of macro | |
10801 | ||
10802 | module mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_1 ( | |
10803 | din, | |
10804 | en, | |
10805 | clr, | |
10806 | l1clk, | |
10807 | scan_in, | |
10808 | siclk, | |
10809 | soclk, | |
10810 | dout, | |
10811 | scan_out); | |
10812 | wire [0:0] fdin; | |
10813 | ||
10814 | input [0:0] din; | |
10815 | input en; | |
10816 | input clr; | |
10817 | input l1clk; | |
10818 | input scan_in; | |
10819 | ||
10820 | ||
10821 | input siclk; | |
10822 | input soclk; | |
10823 | ||
10824 | output [0:0] dout; | |
10825 | output scan_out; | |
10826 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}}); | |
10827 | ||
10828 | ||
10829 | ||
10830 | ||
10831 | ||
10832 | ||
10833 | dff #(1) d0_0 ( | |
10834 | .l1clk(l1clk), | |
10835 | .siclk(siclk), | |
10836 | .soclk(soclk), | |
10837 | .d(fdin[0:0]), | |
10838 | .si(scan_in), | |
10839 | .so(scan_out), | |
10840 | .q(dout[0:0]) | |
10841 | ); | |
10842 | ||
10843 | ||
10844 | ||
10845 | ||
10846 | ||
10847 | ||
10848 | ||
10849 | ||
10850 | ||
10851 | ||
10852 | ||
10853 | ||
10854 | endmodule | |
10855 | ||
10856 | ||
10857 | ||
10858 | ||
10859 | ||
10860 | ||
10861 | ||
10862 | ||
10863 | ||
10864 | ||
10865 | ||
10866 | ||
10867 | ||
10868 | // any PARAMS parms go into naming of macro | |
10869 | ||
10870 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_9 ( | |
10871 | din, | |
10872 | en, | |
10873 | l1clk, | |
10874 | scan_in, | |
10875 | siclk, | |
10876 | soclk, | |
10877 | dout, | |
10878 | scan_out); | |
10879 | wire [8:0] fdin; | |
10880 | wire [7:0] so; | |
10881 | ||
10882 | input [8:0] din; | |
10883 | input en; | |
10884 | input l1clk; | |
10885 | input scan_in; | |
10886 | ||
10887 | ||
10888 | input siclk; | |
10889 | input soclk; | |
10890 | ||
10891 | output [8:0] dout; | |
10892 | output scan_out; | |
10893 | assign fdin[8:0] = (din[8:0] & {9{en}}) | (dout[8:0] & ~{9{en}}); | |
10894 | ||
10895 | ||
10896 | ||
10897 | ||
10898 | ||
10899 | ||
10900 | dff #(9) d0_0 ( | |
10901 | .l1clk(l1clk), | |
10902 | .siclk(siclk), | |
10903 | .soclk(soclk), | |
10904 | .d(fdin[8:0]), | |
10905 | .si({scan_in,so[7:0]}), | |
10906 | .so({so[7:0],scan_out}), | |
10907 | .q(dout[8:0]) | |
10908 | ); | |
10909 | ||
10910 | ||
10911 | ||
10912 | ||
10913 | ||
10914 | ||
10915 | ||
10916 | ||
10917 | ||
10918 | ||
10919 | ||
10920 | ||
10921 | endmodule | |
10922 | ||
10923 | ||
10924 | ||
10925 | ||
10926 | ||
10927 | ||
10928 | ||
10929 | ||
10930 | ||
10931 | ||
10932 | ||
10933 | ||
10934 | ||
10935 | // any PARAMS parms go into naming of macro | |
10936 | ||
10937 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_1 ( | |
10938 | din, | |
10939 | en, | |
10940 | l1clk, | |
10941 | scan_in, | |
10942 | siclk, | |
10943 | soclk, | |
10944 | dout, | |
10945 | scan_out); | |
10946 | wire [0:0] fdin; | |
10947 | ||
10948 | input [0:0] din; | |
10949 | input en; | |
10950 | input l1clk; | |
10951 | input scan_in; | |
10952 | ||
10953 | ||
10954 | input siclk; | |
10955 | input soclk; | |
10956 | ||
10957 | output [0:0] dout; | |
10958 | output scan_out; | |
10959 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
10960 | ||
10961 | ||
10962 | ||
10963 | ||
10964 | ||
10965 | ||
10966 | dff #(1) d0_0 ( | |
10967 | .l1clk(l1clk), | |
10968 | .siclk(siclk), | |
10969 | .soclk(soclk), | |
10970 | .d(fdin[0:0]), | |
10971 | .si(scan_in), | |
10972 | .so(scan_out), | |
10973 | .q(dout[0:0]) | |
10974 | ); | |
10975 | ||
10976 | ||
10977 | ||
10978 | ||
10979 | ||
10980 | ||
10981 | ||
10982 | ||
10983 | ||
10984 | ||
10985 | ||
10986 | ||
10987 | endmodule | |
10988 | ||
10989 | ||
10990 | ||
10991 | ||
10992 | ||
10993 | ||
10994 | ||
10995 | ||
10996 | ||
10997 | ||
10998 | ||
10999 | ||
11000 | ||
11001 | // any PARAMS parms go into naming of macro | |
11002 | ||
11003 | module mcu_drif_ctl_msff_ctl_macro__clr_1__width_6 ( | |
11004 | din, | |
11005 | clr, | |
11006 | l1clk, | |
11007 | scan_in, | |
11008 | siclk, | |
11009 | soclk, | |
11010 | dout, | |
11011 | scan_out); | |
11012 | wire [5:0] fdin; | |
11013 | wire [4:0] so; | |
11014 | ||
11015 | input [5:0] din; | |
11016 | input clr; | |
11017 | input l1clk; | |
11018 | input scan_in; | |
11019 | ||
11020 | ||
11021 | input siclk; | |
11022 | input soclk; | |
11023 | ||
11024 | output [5:0] dout; | |
11025 | output scan_out; | |
11026 | assign fdin[5:0] = din[5:0] & ~{6{clr}}; | |
11027 | ||
11028 | ||
11029 | ||
11030 | ||
11031 | ||
11032 | ||
11033 | dff #(6) d0_0 ( | |
11034 | .l1clk(l1clk), | |
11035 | .siclk(siclk), | |
11036 | .soclk(soclk), | |
11037 | .d(fdin[5:0]), | |
11038 | .si({scan_in,so[4:0]}), | |
11039 | .so({so[4:0],scan_out}), | |
11040 | .q(dout[5:0]) | |
11041 | ); | |
11042 | ||
11043 | ||
11044 | ||
11045 | ||
11046 | ||
11047 | ||
11048 | ||
11049 | ||
11050 | ||
11051 | ||
11052 | ||
11053 | ||
11054 | endmodule | |
11055 | ||
11056 | ||
11057 | ||
11058 | ||
11059 | ||
11060 | ||
11061 | ||
11062 | ||
11063 | ||
11064 | ||
11065 | ||
11066 | ||
11067 | ||
11068 | // any PARAMS parms go into naming of macro | |
11069 | ||
11070 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_15 ( | |
11071 | din, | |
11072 | en, | |
11073 | l1clk, | |
11074 | scan_in, | |
11075 | siclk, | |
11076 | soclk, | |
11077 | dout, | |
11078 | scan_out); | |
11079 | wire [14:0] fdin; | |
11080 | wire [13:0] so; | |
11081 | ||
11082 | input [14:0] din; | |
11083 | input en; | |
11084 | input l1clk; | |
11085 | input scan_in; | |
11086 | ||
11087 | ||
11088 | input siclk; | |
11089 | input soclk; | |
11090 | ||
11091 | output [14:0] dout; | |
11092 | output scan_out; | |
11093 | assign fdin[14:0] = (din[14:0] & {15{en}}) | (dout[14:0] & ~{15{en}}); | |
11094 | ||
11095 | ||
11096 | ||
11097 | ||
11098 | ||
11099 | ||
11100 | dff #(15) d0_0 ( | |
11101 | .l1clk(l1clk), | |
11102 | .siclk(siclk), | |
11103 | .soclk(soclk), | |
11104 | .d(fdin[14:0]), | |
11105 | .si({scan_in,so[13:0]}), | |
11106 | .so({so[13:0],scan_out}), | |
11107 | .q(dout[14:0]) | |
11108 | ); | |
11109 | ||
11110 | ||
11111 | ||
11112 | ||
11113 | ||
11114 | ||
11115 | ||
11116 | ||
11117 | ||
11118 | ||
11119 | ||
11120 | ||
11121 | endmodule | |
11122 | ||
11123 | ||
11124 | ||
11125 | ||
11126 | ||
11127 | ||
11128 | ||
11129 | ||
11130 | ||
11131 | ||
11132 | ||
11133 | ||
11134 | ||
11135 | // any PARAMS parms go into naming of macro | |
11136 | ||
11137 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_11 ( | |
11138 | din, | |
11139 | en, | |
11140 | l1clk, | |
11141 | scan_in, | |
11142 | siclk, | |
11143 | soclk, | |
11144 | dout, | |
11145 | scan_out); | |
11146 | wire [10:0] fdin; | |
11147 | wire [9:0] so; | |
11148 | ||
11149 | input [10:0] din; | |
11150 | input en; | |
11151 | input l1clk; | |
11152 | input scan_in; | |
11153 | ||
11154 | ||
11155 | input siclk; | |
11156 | input soclk; | |
11157 | ||
11158 | output [10:0] dout; | |
11159 | output scan_out; | |
11160 | assign fdin[10:0] = (din[10:0] & {11{en}}) | (dout[10:0] & ~{11{en}}); | |
11161 | ||
11162 | ||
11163 | ||
11164 | ||
11165 | ||
11166 | ||
11167 | dff #(11) d0_0 ( | |
11168 | .l1clk(l1clk), | |
11169 | .siclk(siclk), | |
11170 | .soclk(soclk), | |
11171 | .d(fdin[10:0]), | |
11172 | .si({scan_in,so[9:0]}), | |
11173 | .so({so[9:0],scan_out}), | |
11174 | .q(dout[10:0]) | |
11175 | ); | |
11176 | ||
11177 | ||
11178 | ||
11179 | ||
11180 | ||
11181 | ||
11182 | ||
11183 | ||
11184 | ||
11185 | ||
11186 | ||
11187 | ||
11188 | endmodule | |
11189 | ||
11190 | ||
11191 | ||
11192 | ||
11193 | ||
11194 | ||
11195 | ||
11196 | ||
11197 | ||
11198 | ||
11199 | ||
11200 | ||
11201 | ||
11202 | // any PARAMS parms go into naming of macro | |
11203 | ||
11204 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_3 ( | |
11205 | din, | |
11206 | en, | |
11207 | l1clk, | |
11208 | scan_in, | |
11209 | siclk, | |
11210 | soclk, | |
11211 | dout, | |
11212 | scan_out); | |
11213 | wire [2:0] fdin; | |
11214 | wire [1:0] so; | |
11215 | ||
11216 | input [2:0] din; | |
11217 | input en; | |
11218 | input l1clk; | |
11219 | input scan_in; | |
11220 | ||
11221 | ||
11222 | input siclk; | |
11223 | input soclk; | |
11224 | ||
11225 | output [2:0] dout; | |
11226 | output scan_out; | |
11227 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
11228 | ||
11229 | ||
11230 | ||
11231 | ||
11232 | ||
11233 | ||
11234 | dff #(3) d0_0 ( | |
11235 | .l1clk(l1clk), | |
11236 | .siclk(siclk), | |
11237 | .soclk(soclk), | |
11238 | .d(fdin[2:0]), | |
11239 | .si({scan_in,so[1:0]}), | |
11240 | .so({so[1:0],scan_out}), | |
11241 | .q(dout[2:0]) | |
11242 | ); | |
11243 | ||
11244 | ||
11245 | ||
11246 | ||
11247 | ||
11248 | ||
11249 | ||
11250 | ||
11251 | ||
11252 | ||
11253 | ||
11254 | ||
11255 | endmodule | |
11256 | ||
11257 | ||
11258 | ||
11259 | ||
11260 | ||
11261 | ||
11262 | ||
11263 | ||
11264 | ||
11265 | ||
11266 | ||
11267 | ||
11268 | ||
11269 | // any PARAMS parms go into naming of macro | |
11270 | ||
11271 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_6 ( | |
11272 | din, | |
11273 | en, | |
11274 | l1clk, | |
11275 | scan_in, | |
11276 | siclk, | |
11277 | soclk, | |
11278 | dout, | |
11279 | scan_out); | |
11280 | wire [5:0] fdin; | |
11281 | wire [4:0] so; | |
11282 | ||
11283 | input [5:0] din; | |
11284 | input en; | |
11285 | input l1clk; | |
11286 | input scan_in; | |
11287 | ||
11288 | ||
11289 | input siclk; | |
11290 | input soclk; | |
11291 | ||
11292 | output [5:0] dout; | |
11293 | output scan_out; | |
11294 | assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}}); | |
11295 | ||
11296 | ||
11297 | ||
11298 | ||
11299 | ||
11300 | ||
11301 | dff #(6) d0_0 ( | |
11302 | .l1clk(l1clk), | |
11303 | .siclk(siclk), | |
11304 | .soclk(soclk), | |
11305 | .d(fdin[5:0]), | |
11306 | .si({scan_in,so[4:0]}), | |
11307 | .so({so[4:0],scan_out}), | |
11308 | .q(dout[5:0]) | |
11309 | ); | |
11310 | ||
11311 | ||
11312 | ||
11313 | ||
11314 | ||
11315 | ||
11316 | ||
11317 | ||
11318 | ||
11319 | ||
11320 | ||
11321 | ||
11322 | endmodule | |
11323 | ||
11324 | ||
11325 | ||
11326 | ||
11327 | ||
11328 | ||
11329 | ||
11330 | ||
11331 | ||
11332 | ||
11333 | ||
11334 | ||
11335 | ||
11336 | // any PARAMS parms go into naming of macro | |
11337 | ||
11338 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_2 ( | |
11339 | din, | |
11340 | en, | |
11341 | l1clk, | |
11342 | scan_in, | |
11343 | siclk, | |
11344 | soclk, | |
11345 | dout, | |
11346 | scan_out); | |
11347 | wire [1:0] fdin; | |
11348 | wire [0:0] so; | |
11349 | ||
11350 | input [1:0] din; | |
11351 | input en; | |
11352 | input l1clk; | |
11353 | input scan_in; | |
11354 | ||
11355 | ||
11356 | input siclk; | |
11357 | input soclk; | |
11358 | ||
11359 | output [1:0] dout; | |
11360 | output scan_out; | |
11361 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
11362 | ||
11363 | ||
11364 | ||
11365 | ||
11366 | ||
11367 | ||
11368 | dff #(2) d0_0 ( | |
11369 | .l1clk(l1clk), | |
11370 | .siclk(siclk), | |
11371 | .soclk(soclk), | |
11372 | .d(fdin[1:0]), | |
11373 | .si({scan_in,so[0:0]}), | |
11374 | .so({so[0:0],scan_out}), | |
11375 | .q(dout[1:0]) | |
11376 | ); | |
11377 | ||
11378 | ||
11379 | ||
11380 | ||
11381 | ||
11382 | ||
11383 | ||
11384 | ||
11385 | ||
11386 | ||
11387 | ||
11388 | ||
11389 | endmodule | |
11390 | ||
11391 | ||
11392 | ||
11393 | ||
11394 | ||
11395 | ||
11396 | ||
11397 | ||
11398 | ||
11399 | ||
11400 | ||
11401 | ||
11402 | ||
11403 | // any PARAMS parms go into naming of macro | |
11404 | ||
11405 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_26 ( | |
11406 | din, | |
11407 | en, | |
11408 | l1clk, | |
11409 | scan_in, | |
11410 | siclk, | |
11411 | soclk, | |
11412 | dout, | |
11413 | scan_out); | |
11414 | wire [25:0] fdin; | |
11415 | wire [24:0] so; | |
11416 | ||
11417 | input [25:0] din; | |
11418 | input en; | |
11419 | input l1clk; | |
11420 | input scan_in; | |
11421 | ||
11422 | ||
11423 | input siclk; | |
11424 | input soclk; | |
11425 | ||
11426 | output [25:0] dout; | |
11427 | output scan_out; | |
11428 | assign fdin[25:0] = (din[25:0] & {26{en}}) | (dout[25:0] & ~{26{en}}); | |
11429 | ||
11430 | ||
11431 | ||
11432 | ||
11433 | ||
11434 | ||
11435 | dff #(26) d0_0 ( | |
11436 | .l1clk(l1clk), | |
11437 | .siclk(siclk), | |
11438 | .soclk(soclk), | |
11439 | .d(fdin[25:0]), | |
11440 | .si({scan_in,so[24:0]}), | |
11441 | .so({so[24:0],scan_out}), | |
11442 | .q(dout[25:0]) | |
11443 | ); | |
11444 | ||
11445 | ||
11446 | ||
11447 | ||
11448 | ||
11449 | ||
11450 | ||
11451 | ||
11452 | ||
11453 | ||
11454 | ||
11455 | ||
11456 | endmodule | |
11457 | ||
11458 | ||
11459 | ||
11460 | ||
11461 | ||
11462 | ||
11463 | ||
11464 | ||
11465 | ||
11466 | ||
11467 | ||
11468 | ||
11469 | ||
11470 | // any PARAMS parms go into naming of macro | |
11471 | ||
11472 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_7 ( | |
11473 | din, | |
11474 | en, | |
11475 | l1clk, | |
11476 | scan_in, | |
11477 | siclk, | |
11478 | soclk, | |
11479 | dout, | |
11480 | scan_out); | |
11481 | wire [6:0] fdin; | |
11482 | wire [5:0] so; | |
11483 | ||
11484 | input [6:0] din; | |
11485 | input en; | |
11486 | input l1clk; | |
11487 | input scan_in; | |
11488 | ||
11489 | ||
11490 | input siclk; | |
11491 | input soclk; | |
11492 | ||
11493 | output [6:0] dout; | |
11494 | output scan_out; | |
11495 | assign fdin[6:0] = (din[6:0] & {7{en}}) | (dout[6:0] & ~{7{en}}); | |
11496 | ||
11497 | ||
11498 | ||
11499 | ||
11500 | ||
11501 | ||
11502 | dff #(7) d0_0 ( | |
11503 | .l1clk(l1clk), | |
11504 | .siclk(siclk), | |
11505 | .soclk(soclk), | |
11506 | .d(fdin[6:0]), | |
11507 | .si({scan_in,so[5:0]}), | |
11508 | .so({so[5:0],scan_out}), | |
11509 | .q(dout[6:0]) | |
11510 | ); | |
11511 | ||
11512 | ||
11513 | ||
11514 | ||
11515 | ||
11516 | ||
11517 | ||
11518 | ||
11519 | ||
11520 | ||
11521 | ||
11522 | ||
11523 | endmodule | |
11524 | ||
11525 | ||
11526 | ||
11527 | ||
11528 | ||
11529 | ||
11530 | ||
11531 | ||
11532 | ||
11533 | ||
11534 | ||
11535 | ||
11536 | ||
11537 | // any PARAMS parms go into naming of macro | |
11538 | ||
11539 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_18 ( | |
11540 | din, | |
11541 | en, | |
11542 | l1clk, | |
11543 | scan_in, | |
11544 | siclk, | |
11545 | soclk, | |
11546 | dout, | |
11547 | scan_out); | |
11548 | wire [17:0] fdin; | |
11549 | wire [16:0] so; | |
11550 | ||
11551 | input [17:0] din; | |
11552 | input en; | |
11553 | input l1clk; | |
11554 | input scan_in; | |
11555 | ||
11556 | ||
11557 | input siclk; | |
11558 | input soclk; | |
11559 | ||
11560 | output [17:0] dout; | |
11561 | output scan_out; | |
11562 | assign fdin[17:0] = (din[17:0] & {18{en}}) | (dout[17:0] & ~{18{en}}); | |
11563 | ||
11564 | ||
11565 | ||
11566 | ||
11567 | ||
11568 | ||
11569 | dff #(18) d0_0 ( | |
11570 | .l1clk(l1clk), | |
11571 | .siclk(siclk), | |
11572 | .soclk(soclk), | |
11573 | .d(fdin[17:0]), | |
11574 | .si({scan_in,so[16:0]}), | |
11575 | .so({so[16:0],scan_out}), | |
11576 | .q(dout[17:0]) | |
11577 | ); | |
11578 | ||
11579 | ||
11580 | ||
11581 | ||
11582 | ||
11583 | ||
11584 | ||
11585 | ||
11586 | ||
11587 | ||
11588 | ||
11589 | ||
11590 | endmodule | |
11591 | ||
11592 | ||
11593 | ||
11594 | ||
11595 | ||
11596 | ||
11597 | ||
11598 | ||
11599 | ||
11600 | ||
11601 | ||
11602 | ||
11603 | ||
11604 | // any PARAMS parms go into naming of macro | |
11605 | ||
11606 | module mcu_drif_ctl_msff_ctl_macro__width_8 ( | |
11607 | din, | |
11608 | l1clk, | |
11609 | scan_in, | |
11610 | siclk, | |
11611 | soclk, | |
11612 | dout, | |
11613 | scan_out); | |
11614 | wire [7:0] fdin; | |
11615 | wire [6:0] so; | |
11616 | ||
11617 | input [7:0] din; | |
11618 | input l1clk; | |
11619 | input scan_in; | |
11620 | ||
11621 | ||
11622 | input siclk; | |
11623 | input soclk; | |
11624 | ||
11625 | output [7:0] dout; | |
11626 | output scan_out; | |
11627 | assign fdin[7:0] = din[7:0]; | |
11628 | ||
11629 | ||
11630 | ||
11631 | ||
11632 | ||
11633 | ||
11634 | dff #(8) d0_0 ( | |
11635 | .l1clk(l1clk), | |
11636 | .siclk(siclk), | |
11637 | .soclk(soclk), | |
11638 | .d(fdin[7:0]), | |
11639 | .si({scan_in,so[6:0]}), | |
11640 | .so({so[6:0],scan_out}), | |
11641 | .q(dout[7:0]) | |
11642 | ); | |
11643 | ||
11644 | ||
11645 | ||
11646 | ||
11647 | ||
11648 | ||
11649 | ||
11650 | ||
11651 | ||
11652 | ||
11653 | ||
11654 | ||
11655 | endmodule | |
11656 | ||
11657 | ||
11658 | ||
11659 | ||
11660 | ||
11661 | ||
11662 | ||
11663 | ||
11664 | ||
11665 | ||
11666 | ||
11667 | ||
11668 | ||
11669 | // any PARAMS parms go into naming of macro | |
11670 | ||
11671 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_12 ( | |
11672 | din, | |
11673 | en, | |
11674 | l1clk, | |
11675 | scan_in, | |
11676 | siclk, | |
11677 | soclk, | |
11678 | dout, | |
11679 | scan_out); | |
11680 | wire [11:0] fdin; | |
11681 | wire [10:0] so; | |
11682 | ||
11683 | input [11:0] din; | |
11684 | input en; | |
11685 | input l1clk; | |
11686 | input scan_in; | |
11687 | ||
11688 | ||
11689 | input siclk; | |
11690 | input soclk; | |
11691 | ||
11692 | output [11:0] dout; | |
11693 | output scan_out; | |
11694 | assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}}); | |
11695 | ||
11696 | ||
11697 | ||
11698 | ||
11699 | ||
11700 | ||
11701 | dff #(12) d0_0 ( | |
11702 | .l1clk(l1clk), | |
11703 | .siclk(siclk), | |
11704 | .soclk(soclk), | |
11705 | .d(fdin[11:0]), | |
11706 | .si({scan_in,so[10:0]}), | |
11707 | .so({so[10:0],scan_out}), | |
11708 | .q(dout[11:0]) | |
11709 | ); | |
11710 | ||
11711 | ||
11712 | ||
11713 | ||
11714 | ||
11715 | ||
11716 | ||
11717 | ||
11718 | ||
11719 | ||
11720 | ||
11721 | ||
11722 | endmodule | |
11723 | ||
11724 | ||
11725 | ||
11726 | ||
11727 | ||
11728 | ||
11729 | ||
11730 | ||
11731 | ||
11732 | ||
11733 | ||
11734 | ||
11735 | ||
11736 | // any PARAMS parms go into naming of macro | |
11737 | ||
11738 | module mcu_drif_ctl_msff_ctl_macro__en_1 ( | |
11739 | din, | |
11740 | en, | |
11741 | l1clk, | |
11742 | scan_in, | |
11743 | siclk, | |
11744 | soclk, | |
11745 | dout, | |
11746 | scan_out); | |
11747 | wire [0:0] fdin; | |
11748 | ||
11749 | input [0:0] din; | |
11750 | input en; | |
11751 | input l1clk; | |
11752 | input scan_in; | |
11753 | ||
11754 | ||
11755 | input siclk; | |
11756 | input soclk; | |
11757 | ||
11758 | output [0:0] dout; | |
11759 | output scan_out; | |
11760 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
11761 | ||
11762 | ||
11763 | ||
11764 | ||
11765 | ||
11766 | ||
11767 | dff #(1) d0_0 ( | |
11768 | .l1clk(l1clk), | |
11769 | .siclk(siclk), | |
11770 | .soclk(soclk), | |
11771 | .d(fdin[0:0]), | |
11772 | .si(scan_in), | |
11773 | .so(scan_out), | |
11774 | .q(dout[0:0]) | |
11775 | ); | |
11776 | ||
11777 | ||
11778 | ||
11779 | ||
11780 | ||
11781 | ||
11782 | ||
11783 | ||
11784 | ||
11785 | ||
11786 | ||
11787 | ||
11788 | endmodule | |
11789 | ||
11790 | ||
11791 | ||
11792 | ||
11793 | ||
11794 | ||
11795 | ||
11796 | ||
11797 | ||
11798 | ||
11799 | ||
11800 | ||
11801 | ||
11802 | // any PARAMS parms go into naming of macro | |
11803 | ||
11804 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_35 ( | |
11805 | din, | |
11806 | en, | |
11807 | l1clk, | |
11808 | scan_in, | |
11809 | siclk, | |
11810 | soclk, | |
11811 | dout, | |
11812 | scan_out); | |
11813 | wire [34:0] fdin; | |
11814 | wire [33:0] so; | |
11815 | ||
11816 | input [34:0] din; | |
11817 | input en; | |
11818 | input l1clk; | |
11819 | input scan_in; | |
11820 | ||
11821 | ||
11822 | input siclk; | |
11823 | input soclk; | |
11824 | ||
11825 | output [34:0] dout; | |
11826 | output scan_out; | |
11827 | assign fdin[34:0] = (din[34:0] & {35{en}}) | (dout[34:0] & ~{35{en}}); | |
11828 | ||
11829 | ||
11830 | ||
11831 | ||
11832 | ||
11833 | ||
11834 | dff #(35) d0_0 ( | |
11835 | .l1clk(l1clk), | |
11836 | .siclk(siclk), | |
11837 | .soclk(soclk), | |
11838 | .d(fdin[34:0]), | |
11839 | .si({scan_in,so[33:0]}), | |
11840 | .so({so[33:0],scan_out}), | |
11841 | .q(dout[34:0]) | |
11842 | ); | |
11843 | ||
11844 | ||
11845 | ||
11846 | ||
11847 | ||
11848 | ||
11849 | ||
11850 | ||
11851 | ||
11852 | ||
11853 | ||
11854 | ||
11855 | endmodule | |
11856 | ||
11857 | ||
11858 | ||
11859 | ||
11860 | ||
11861 | ||
11862 | ||
11863 | ||
11864 | ||
11865 | ||
11866 | ||
11867 | ||
11868 | ||
11869 | // any PARAMS parms go into naming of macro | |
11870 | ||
11871 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_5 ( | |
11872 | din, | |
11873 | en, | |
11874 | l1clk, | |
11875 | scan_in, | |
11876 | siclk, | |
11877 | soclk, | |
11878 | dout, | |
11879 | scan_out); | |
11880 | wire [4:0] fdin; | |
11881 | wire [3:0] so; | |
11882 | ||
11883 | input [4:0] din; | |
11884 | input en; | |
11885 | input l1clk; | |
11886 | input scan_in; | |
11887 | ||
11888 | ||
11889 | input siclk; | |
11890 | input soclk; | |
11891 | ||
11892 | output [4:0] dout; | |
11893 | output scan_out; | |
11894 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); | |
11895 | ||
11896 | ||
11897 | ||
11898 | ||
11899 | ||
11900 | ||
11901 | dff #(5) d0_0 ( | |
11902 | .l1clk(l1clk), | |
11903 | .siclk(siclk), | |
11904 | .soclk(soclk), | |
11905 | .d(fdin[4:0]), | |
11906 | .si({scan_in,so[3:0]}), | |
11907 | .so({so[3:0],scan_out}), | |
11908 | .q(dout[4:0]) | |
11909 | ); | |
11910 | ||
11911 | ||
11912 | ||
11913 | ||
11914 | ||
11915 | ||
11916 | ||
11917 | ||
11918 | ||
11919 | ||
11920 | ||
11921 | ||
11922 | endmodule | |
11923 | ||
11924 | ||
11925 | ||
11926 | ||
11927 | ||
11928 | ||
11929 | ||
11930 | ||
11931 | ||
11932 | ||
11933 | ||
11934 | ||
11935 | ||
11936 | // any PARAMS parms go into naming of macro | |
11937 | ||
11938 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_8 ( | |
11939 | din, | |
11940 | en, | |
11941 | l1clk, | |
11942 | scan_in, | |
11943 | siclk, | |
11944 | soclk, | |
11945 | dout, | |
11946 | scan_out); | |
11947 | wire [7:0] fdin; | |
11948 | wire [6:0] so; | |
11949 | ||
11950 | input [7:0] din; | |
11951 | input en; | |
11952 | input l1clk; | |
11953 | input scan_in; | |
11954 | ||
11955 | ||
11956 | input siclk; | |
11957 | input soclk; | |
11958 | ||
11959 | output [7:0] dout; | |
11960 | output scan_out; | |
11961 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
11962 | ||
11963 | ||
11964 | ||
11965 | ||
11966 | ||
11967 | ||
11968 | dff #(8) d0_0 ( | |
11969 | .l1clk(l1clk), | |
11970 | .siclk(siclk), | |
11971 | .soclk(soclk), | |
11972 | .d(fdin[7:0]), | |
11973 | .si({scan_in,so[6:0]}), | |
11974 | .so({so[6:0],scan_out}), | |
11975 | .q(dout[7:0]) | |
11976 | ); | |
11977 | ||
11978 | ||
11979 | ||
11980 | ||
11981 | ||
11982 | ||
11983 | ||
11984 | ||
11985 | ||
11986 | ||
11987 | ||
11988 | ||
11989 | endmodule | |
11990 | ||
11991 | ||
11992 | ||
11993 | ||
11994 | ||
11995 | ||
11996 | ||
11997 | ||
11998 | ||
11999 | ||
12000 | ||
12001 | ||
12002 | ||
12003 | // any PARAMS parms go into naming of macro | |
12004 | ||
12005 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_13 ( | |
12006 | din, | |
12007 | en, | |
12008 | l1clk, | |
12009 | scan_in, | |
12010 | siclk, | |
12011 | soclk, | |
12012 | dout, | |
12013 | scan_out); | |
12014 | wire [12:0] fdin; | |
12015 | wire [11:0] so; | |
12016 | ||
12017 | input [12:0] din; | |
12018 | input en; | |
12019 | input l1clk; | |
12020 | input scan_in; | |
12021 | ||
12022 | ||
12023 | input siclk; | |
12024 | input soclk; | |
12025 | ||
12026 | output [12:0] dout; | |
12027 | output scan_out; | |
12028 | assign fdin[12:0] = (din[12:0] & {13{en}}) | (dout[12:0] & ~{13{en}}); | |
12029 | ||
12030 | ||
12031 | ||
12032 | ||
12033 | ||
12034 | ||
12035 | dff #(13) d0_0 ( | |
12036 | .l1clk(l1clk), | |
12037 | .siclk(siclk), | |
12038 | .soclk(soclk), | |
12039 | .d(fdin[12:0]), | |
12040 | .si({scan_in,so[11:0]}), | |
12041 | .so({so[11:0],scan_out}), | |
12042 | .q(dout[12:0]) | |
12043 | ); | |
12044 | ||
12045 | ||
12046 | ||
12047 | ||
12048 | ||
12049 | ||
12050 | ||
12051 | ||
12052 | ||
12053 | ||
12054 | ||
12055 | ||
12056 | endmodule | |
12057 | ||
12058 | ||
12059 | ||
12060 | ||
12061 | ||
12062 | ||
12063 | ||
12064 | ||
12065 | ||
12066 | ||
12067 | ||
12068 | ||
12069 | ||
12070 | // any PARAMS parms go into naming of macro | |
12071 | ||
12072 | module mcu_drif_ctl_msff_ctl_macro__width_13 ( | |
12073 | din, | |
12074 | l1clk, | |
12075 | scan_in, | |
12076 | siclk, | |
12077 | soclk, | |
12078 | dout, | |
12079 | scan_out); | |
12080 | wire [12:0] fdin; | |
12081 | wire [11:0] so; | |
12082 | ||
12083 | input [12:0] din; | |
12084 | input l1clk; | |
12085 | input scan_in; | |
12086 | ||
12087 | ||
12088 | input siclk; | |
12089 | input soclk; | |
12090 | ||
12091 | output [12:0] dout; | |
12092 | output scan_out; | |
12093 | assign fdin[12:0] = din[12:0]; | |
12094 | ||
12095 | ||
12096 | ||
12097 | ||
12098 | ||
12099 | ||
12100 | dff #(13) d0_0 ( | |
12101 | .l1clk(l1clk), | |
12102 | .siclk(siclk), | |
12103 | .soclk(soclk), | |
12104 | .d(fdin[12:0]), | |
12105 | .si({scan_in,so[11:0]}), | |
12106 | .so({so[11:0],scan_out}), | |
12107 | .q(dout[12:0]) | |
12108 | ); | |
12109 | ||
12110 | ||
12111 | ||
12112 | ||
12113 | ||
12114 | ||
12115 | ||
12116 | ||
12117 | ||
12118 | ||
12119 | ||
12120 | ||
12121 | endmodule | |
12122 | ||
12123 | ||
12124 | ||
12125 | ||
12126 | ||
12127 | ||
12128 | ||
12129 | ||
12130 | ||
12131 | ||
12132 | ||
12133 | ||
12134 | ||
12135 | // any PARAMS parms go into naming of macro | |
12136 | ||
12137 | module mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_12 ( | |
12138 | din, | |
12139 | en, | |
12140 | clr, | |
12141 | l1clk, | |
12142 | scan_in, | |
12143 | siclk, | |
12144 | soclk, | |
12145 | dout, | |
12146 | scan_out); | |
12147 | wire [11:0] fdin; | |
12148 | wire [10:0] so; | |
12149 | ||
12150 | input [11:0] din; | |
12151 | input en; | |
12152 | input clr; | |
12153 | input l1clk; | |
12154 | input scan_in; | |
12155 | ||
12156 | ||
12157 | input siclk; | |
12158 | input soclk; | |
12159 | ||
12160 | output [11:0] dout; | |
12161 | output scan_out; | |
12162 | assign fdin[11:0] = (din[11:0] & {12{en}} & ~{12{clr}}) | (dout[11:0] & ~{12{en}} & ~{12{clr}}); | |
12163 | ||
12164 | ||
12165 | ||
12166 | ||
12167 | ||
12168 | ||
12169 | dff #(12) d0_0 ( | |
12170 | .l1clk(l1clk), | |
12171 | .siclk(siclk), | |
12172 | .soclk(soclk), | |
12173 | .d(fdin[11:0]), | |
12174 | .si({scan_in,so[10:0]}), | |
12175 | .so({so[10:0],scan_out}), | |
12176 | .q(dout[11:0]) | |
12177 | ); | |
12178 | ||
12179 | ||
12180 | ||
12181 | ||
12182 | ||
12183 | ||
12184 | ||
12185 | ||
12186 | ||
12187 | ||
12188 | ||
12189 | ||
12190 | endmodule | |
12191 | ||
12192 | ||
12193 | ||
12194 | ||
12195 | ||
12196 | ||
12197 | ||
12198 | ||
12199 | ||
12200 | ||
12201 | ||
12202 | ||
12203 | ||
12204 | // any PARAMS parms go into naming of macro | |
12205 | ||
12206 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_17 ( | |
12207 | din, | |
12208 | en, | |
12209 | l1clk, | |
12210 | scan_in, | |
12211 | siclk, | |
12212 | soclk, | |
12213 | dout, | |
12214 | scan_out); | |
12215 | wire [16:0] fdin; | |
12216 | wire [15:0] so; | |
12217 | ||
12218 | input [16:0] din; | |
12219 | input en; | |
12220 | input l1clk; | |
12221 | input scan_in; | |
12222 | ||
12223 | ||
12224 | input siclk; | |
12225 | input soclk; | |
12226 | ||
12227 | output [16:0] dout; | |
12228 | output scan_out; | |
12229 | assign fdin[16:0] = (din[16:0] & {17{en}}) | (dout[16:0] & ~{17{en}}); | |
12230 | ||
12231 | ||
12232 | ||
12233 | ||
12234 | ||
12235 | ||
12236 | dff #(17) d0_0 ( | |
12237 | .l1clk(l1clk), | |
12238 | .siclk(siclk), | |
12239 | .soclk(soclk), | |
12240 | .d(fdin[16:0]), | |
12241 | .si({scan_in,so[15:0]}), | |
12242 | .so({so[15:0],scan_out}), | |
12243 | .q(dout[16:0]) | |
12244 | ); | |
12245 | ||
12246 | ||
12247 | ||
12248 | ||
12249 | ||
12250 | ||
12251 | ||
12252 | ||
12253 | ||
12254 | ||
12255 | ||
12256 | ||
12257 | endmodule | |
12258 | ||
12259 | ||
12260 | ||
12261 | ||
12262 | ||
12263 | ||
12264 | ||
12265 | ||
12266 | ||
12267 | ||
12268 | ||
12269 | ||
12270 | ||
12271 | // any PARAMS parms go into naming of macro | |
12272 | ||
12273 | module mcu_drif_ctl_msff_ctl_macro__width_16 ( | |
12274 | din, | |
12275 | l1clk, | |
12276 | scan_in, | |
12277 | siclk, | |
12278 | soclk, | |
12279 | dout, | |
12280 | scan_out); | |
12281 | wire [15:0] fdin; | |
12282 | wire [14:0] so; | |
12283 | ||
12284 | input [15:0] din; | |
12285 | input l1clk; | |
12286 | input scan_in; | |
12287 | ||
12288 | ||
12289 | input siclk; | |
12290 | input soclk; | |
12291 | ||
12292 | output [15:0] dout; | |
12293 | output scan_out; | |
12294 | assign fdin[15:0] = din[15:0]; | |
12295 | ||
12296 | ||
12297 | ||
12298 | ||
12299 | ||
12300 | ||
12301 | dff #(16) d0_0 ( | |
12302 | .l1clk(l1clk), | |
12303 | .siclk(siclk), | |
12304 | .soclk(soclk), | |
12305 | .d(fdin[15:0]), | |
12306 | .si({scan_in,so[14:0]}), | |
12307 | .so({so[14:0],scan_out}), | |
12308 | .q(dout[15:0]) | |
12309 | ); | |
12310 | ||
12311 | ||
12312 | ||
12313 | ||
12314 | ||
12315 | ||
12316 | ||
12317 | ||
12318 | ||
12319 | ||
12320 | ||
12321 | ||
12322 | endmodule | |
12323 | ||
12324 | ||
12325 | ||
12326 | ||
12327 | ||
12328 | ||
12329 | ||
12330 | ||
12331 | ||
12332 | ||
12333 | ||
12334 | ||
12335 | ||
12336 | // any PARAMS parms go into naming of macro | |
12337 | ||
12338 | module mcu_drif_ctl_msff_ctl_macro__clr_1__width_1 ( | |
12339 | din, | |
12340 | clr, | |
12341 | l1clk, | |
12342 | scan_in, | |
12343 | siclk, | |
12344 | soclk, | |
12345 | dout, | |
12346 | scan_out); | |
12347 | wire [0:0] fdin; | |
12348 | ||
12349 | input [0:0] din; | |
12350 | input clr; | |
12351 | input l1clk; | |
12352 | input scan_in; | |
12353 | ||
12354 | ||
12355 | input siclk; | |
12356 | input soclk; | |
12357 | ||
12358 | output [0:0] dout; | |
12359 | output scan_out; | |
12360 | assign fdin[0:0] = din[0:0] & ~{1{clr}}; | |
12361 | ||
12362 | ||
12363 | ||
12364 | ||
12365 | ||
12366 | ||
12367 | dff #(1) d0_0 ( | |
12368 | .l1clk(l1clk), | |
12369 | .siclk(siclk), | |
12370 | .soclk(soclk), | |
12371 | .d(fdin[0:0]), | |
12372 | .si(scan_in), | |
12373 | .so(scan_out), | |
12374 | .q(dout[0:0]) | |
12375 | ); | |
12376 | ||
12377 | ||
12378 | ||
12379 | ||
12380 | ||
12381 | ||
12382 | ||
12383 | ||
12384 | ||
12385 | ||
12386 | ||
12387 | ||
12388 | endmodule | |
12389 | ||
12390 | ||
12391 | ||
12392 | ||
12393 | ||
12394 | ||
12395 | ||
12396 | ||
12397 | ||
12398 | ||
12399 | ||
12400 | ||
12401 | ||
12402 | // any PARAMS parms go into naming of macro | |
12403 | ||
12404 | module mcu_drif_ctl_msff_ctl_macro__width_66 ( | |
12405 | din, | |
12406 | l1clk, | |
12407 | scan_in, | |
12408 | siclk, | |
12409 | soclk, | |
12410 | dout, | |
12411 | scan_out); | |
12412 | wire [65:0] fdin; | |
12413 | wire [64:0] so; | |
12414 | ||
12415 | input [65:0] din; | |
12416 | input l1clk; | |
12417 | input scan_in; | |
12418 | ||
12419 | ||
12420 | input siclk; | |
12421 | input soclk; | |
12422 | ||
12423 | output [65:0] dout; | |
12424 | output scan_out; | |
12425 | assign fdin[65:0] = din[65:0]; | |
12426 | ||
12427 | ||
12428 | ||
12429 | ||
12430 | ||
12431 | ||
12432 | dff #(66) d0_0 ( | |
12433 | .l1clk(l1clk), | |
12434 | .siclk(siclk), | |
12435 | .soclk(soclk), | |
12436 | .d(fdin[65:0]), | |
12437 | .si({scan_in,so[64:0]}), | |
12438 | .so({so[64:0],scan_out}), | |
12439 | .q(dout[65:0]) | |
12440 | ); | |
12441 | ||
12442 | ||
12443 | ||
12444 | ||
12445 | ||
12446 | ||
12447 | ||
12448 | ||
12449 | ||
12450 | ||
12451 | ||
12452 | ||
12453 | endmodule | |
12454 | ||
12455 | ||
12456 | ||
12457 | ||
12458 | ||
12459 | ||
12460 | ||
12461 | ||
12462 | ||
12463 | ||
12464 | ||
12465 | ||
12466 | ||
12467 | // any PARAMS parms go into naming of macro | |
12468 | ||
12469 | module mcu_drif_ctl_msff_ctl_macro__en_1__width_32 ( | |
12470 | din, | |
12471 | en, | |
12472 | l1clk, | |
12473 | scan_in, | |
12474 | siclk, | |
12475 | soclk, | |
12476 | dout, | |
12477 | scan_out); | |
12478 | wire [31:0] fdin; | |
12479 | wire [30:0] so; | |
12480 | ||
12481 | input [31:0] din; | |
12482 | input en; | |
12483 | input l1clk; | |
12484 | input scan_in; | |
12485 | ||
12486 | ||
12487 | input siclk; | |
12488 | input soclk; | |
12489 | ||
12490 | output [31:0] dout; | |
12491 | output scan_out; | |
12492 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); | |
12493 | ||
12494 | ||
12495 | ||
12496 | ||
12497 | ||
12498 | ||
12499 | dff #(32) d0_0 ( | |
12500 | .l1clk(l1clk), | |
12501 | .siclk(siclk), | |
12502 | .soclk(soclk), | |
12503 | .d(fdin[31:0]), | |
12504 | .si({scan_in,so[30:0]}), | |
12505 | .so({so[30:0],scan_out}), | |
12506 | .q(dout[31:0]) | |
12507 | ); | |
12508 | ||
12509 | endmodule | |
12510 | ||
12511 | ||
12512 | ||
12513 | // any PARAMS parms go into naming of macro | |
12514 | ||
12515 | module mcu_drif_ctl_msff_ctl_macro__width_6 ( | |
12516 | din, | |
12517 | l1clk, | |
12518 | scan_in, | |
12519 | siclk, | |
12520 | soclk, | |
12521 | dout, | |
12522 | scan_out); | |
12523 | wire [5:0] fdin; | |
12524 | wire [4:0] so; | |
12525 | ||
12526 | input [5:0] din; | |
12527 | input l1clk; | |
12528 | input scan_in; | |
12529 | ||
12530 | ||
12531 | input siclk; | |
12532 | input soclk; | |
12533 | ||
12534 | output [5:0] dout; | |
12535 | output scan_out; | |
12536 | assign fdin[5:0] = din[5:0]; | |
12537 | ||
12538 | ||
12539 | ||
12540 | ||
12541 | ||
12542 | ||
12543 | dff #(6) d0_0 ( | |
12544 | .l1clk(l1clk), | |
12545 | .siclk(siclk), | |
12546 | .soclk(soclk), | |
12547 | .d(fdin[5:0]), | |
12548 | .si({scan_in,so[4:0]}), | |
12549 | .so({so[4:0],scan_out}), | |
12550 | .q(dout[5:0]) | |
12551 | ); | |
12552 | ||
12553 | ||
12554 | ||
12555 | ||
12556 | ||
12557 | ||
12558 | ||
12559 | ||
12560 | ||
12561 | ||
12562 | ||
12563 | ||
12564 | endmodule | |
12565 | ||
12566 | ||
12567 | ||
12568 | ||
12569 | ||
12570 | ||
12571 | ||
12572 | ||
12573 | ||
12574 | ||
12575 | ||
12576 | ||
12577 | ||
12578 | // any PARAMS parms go into naming of macro | |
12579 | ||
12580 | module mcu_drif_ctl_msff_ctl_macro__width_9 ( | |
12581 | din, | |
12582 | l1clk, | |
12583 | scan_in, | |
12584 | siclk, | |
12585 | soclk, | |
12586 | dout, | |
12587 | scan_out); | |
12588 | wire [8:0] fdin; | |
12589 | wire [7:0] so; | |
12590 | ||
12591 | input [8:0] din; | |
12592 | input l1clk; | |
12593 | input scan_in; | |
12594 | ||
12595 | ||
12596 | input siclk; | |
12597 | input soclk; | |
12598 | ||
12599 | output [8:0] dout; | |
12600 | output scan_out; | |
12601 | assign fdin[8:0] = din[8:0]; | |
12602 | ||
12603 | ||
12604 | ||
12605 | ||
12606 | ||
12607 | ||
12608 | dff #(9) d0_0 ( | |
12609 | .l1clk(l1clk), | |
12610 | .siclk(siclk), | |
12611 | .soclk(soclk), | |
12612 | .d(fdin[8:0]), | |
12613 | .si({scan_in,so[7:0]}), | |
12614 | .so({so[7:0],scan_out}), | |
12615 | .q(dout[8:0]) | |
12616 | ); | |
12617 | ||
12618 | ||
12619 | ||
12620 | ||
12621 | ||
12622 | ||
12623 | ||
12624 | ||
12625 | ||
12626 | ||
12627 | ||
12628 | ||
12629 | endmodule | |
12630 | ||
12631 | ||
12632 | ||
12633 | ||
12634 | // any PARAMS parms go into naming of macro | |
12635 | ||
12636 | module mcu_drif_ctl_msff_ctl_macro__clr_1__width_16 ( | |
12637 | din, | |
12638 | clr, | |
12639 | l1clk, | |
12640 | scan_in, | |
12641 | siclk, | |
12642 | soclk, | |
12643 | dout, | |
12644 | scan_out); | |
12645 | wire [15:0] fdin; | |
12646 | wire [14:0] so; | |
12647 | ||
12648 | input [15:0] din; | |
12649 | input clr; | |
12650 | input l1clk; | |
12651 | input scan_in; | |
12652 | ||
12653 | ||
12654 | input siclk; | |
12655 | input soclk; | |
12656 | ||
12657 | output [15:0] dout; | |
12658 | output scan_out; | |
12659 | assign fdin[15:0] = din[15:0] & ~{16{clr}}; | |
12660 | ||
12661 | ||
12662 | ||
12663 | ||
12664 | ||
12665 | ||
12666 | dff #(16) d0_0 ( | |
12667 | .l1clk(l1clk), | |
12668 | .siclk(siclk), | |
12669 | .soclk(soclk), | |
12670 | .d(fdin[15:0]), | |
12671 | .si({scan_in,so[14:0]}), | |
12672 | .so({so[14:0],scan_out}), | |
12673 | .q(dout[15:0]) | |
12674 | ); | |
12675 | ||
12676 | ||
12677 | ||
12678 | ||
12679 | ||
12680 | ||
12681 | ||
12682 | ||
12683 | ||
12684 | ||
12685 | ||
12686 | ||
12687 | endmodule | |
12688 | ||
12689 | ||
12690 | ||
12691 | ||
12692 | ||
12693 | ||
12694 | ||
12695 | ||
12696 | ||
12697 | ||
12698 | ||
12699 | ||
12700 | ||
12701 | // any PARAMS parms go into naming of macro | |
12702 | ||
12703 | module mcu_drif_ctl_msff_ctl_macro__clr_1__width_3 ( | |
12704 | din, | |
12705 | clr, | |
12706 | l1clk, | |
12707 | scan_in, | |
12708 | siclk, | |
12709 | soclk, | |
12710 | dout, | |
12711 | scan_out); | |
12712 | wire [2:0] fdin; | |
12713 | wire [1:0] so; | |
12714 | ||
12715 | input [2:0] din; | |
12716 | input clr; | |
12717 | input l1clk; | |
12718 | input scan_in; | |
12719 | ||
12720 | ||
12721 | input siclk; | |
12722 | input soclk; | |
12723 | ||
12724 | output [2:0] dout; | |
12725 | output scan_out; | |
12726 | assign fdin[2:0] = din[2:0] & ~{3{clr}}; | |
12727 | ||
12728 | ||
12729 | ||
12730 | ||
12731 | ||
12732 | ||
12733 | dff #(3) d0_0 ( | |
12734 | .l1clk(l1clk), | |
12735 | .siclk(siclk), | |
12736 | .soclk(soclk), | |
12737 | .d(fdin[2:0]), | |
12738 | .si({scan_in,so[1:0]}), | |
12739 | .so({so[1:0],scan_out}), | |
12740 | .q(dout[2:0]) | |
12741 | ); | |
12742 | ||
12743 | ||
12744 | ||
12745 | ||
12746 | ||
12747 | ||
12748 | ||
12749 | ||
12750 | ||
12751 | ||
12752 | ||
12753 | ||
12754 | endmodule | |
12755 | ||
12756 | ||
12757 | ||
12758 | ||
12759 | ||
12760 | ||
12761 | ||
12762 | ||
12763 | ||
12764 | ||
12765 | ||
12766 | ||
12767 | ||
12768 | // any PARAMS parms go into naming of macro | |
12769 | ||
12770 | module mcu_drif_ctl_msff_ctl_macro__clr_1__en_1__width_32 ( | |
12771 | din, | |
12772 | en, | |
12773 | clr, | |
12774 | l1clk, | |
12775 | scan_in, | |
12776 | siclk, | |
12777 | soclk, | |
12778 | dout, | |
12779 | scan_out); | |
12780 | wire [31:0] fdin; | |
12781 | wire [30:0] so; | |
12782 | ||
12783 | input [31:0] din; | |
12784 | input en; | |
12785 | input clr; | |
12786 | input l1clk; | |
12787 | input scan_in; | |
12788 | ||
12789 | ||
12790 | input siclk; | |
12791 | input soclk; | |
12792 | ||
12793 | output [31:0] dout; | |
12794 | output scan_out; | |
12795 | assign fdin[31:0] = (din[31:0] & {32{en}} & ~{32{clr}}) | (dout[31:0] & ~{32{en}} & ~{32{clr}}); | |
12796 | ||
12797 | ||
12798 | ||
12799 | ||
12800 | ||
12801 | ||
12802 | dff #(32) d0_0 ( | |
12803 | .l1clk(l1clk), | |
12804 | .siclk(siclk), | |
12805 | .soclk(soclk), | |
12806 | .d(fdin[31:0]), | |
12807 | .si({scan_in,so[30:0]}), | |
12808 | .so({so[30:0],scan_out}), | |
12809 | .q(dout[31:0]) | |
12810 | ); | |
12811 | ||
12812 | ||
12813 | endmodule | |
12814 |