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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_fbdic_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define DRIF_MCU_STATE_00 5'd0 | |
36 | `define DRIF_MCU_STATE_01 5'd1 | |
37 | `define DRIF_MCU_STATE_02 5'd2 | |
38 | `define DRIF_MCU_STATE_03 5'd3 | |
39 | `define DRIF_MCU_STATE_04 5'd4 | |
40 | `define DRIF_MCU_STATE_05 5'd5 | |
41 | `define DRIF_MCU_STATE_06 5'd6 | |
42 | `define DRIF_MCU_STATE_07 5'd7 | |
43 | `define DRIF_MCU_STATE_08 5'd8 | |
44 | `define DRIF_MCU_STATE_09 5'd9 | |
45 | `define DRIF_MCU_STATE_10 5'd10 | |
46 | `define DRIF_MCU_STATE_11 5'd11 | |
47 | `define DRIF_MCU_STATE_12 5'd12 | |
48 | `define DRIF_MCU_STATE_13 5'd13 | |
49 | `define DRIF_MCU_STATE_14 5'd14 | |
50 | `define DRIF_MCU_STATE_15 5'd15 | |
51 | `define DRIF_MCU_STATE_16 5'd16 | |
52 | `define DRIF_MCU_STATE_17 5'd17 | |
53 | `define DRIF_MCU_STATE_18 5'd18 | |
54 | `define DRIF_MCU_STATE_19 5'd19 | |
55 | `define DRIF_MCU_STATE_20 5'd20 | |
56 | `define DRIF_MCU_STATE_21 5'd21 | |
57 | `define DRIF_MCU_STATE_22 5'd22 | |
58 | `define DRIF_MCU_STATE_23 5'd23 | |
59 | `define DRIF_MCU_STATE_24 5'd24 | |
60 | `define DRIF_MCU_STATE_25 5'd25 | |
61 | `define DRIF_MCU_STATE_26 5'd26 | |
62 | ||
63 | `define DRIF_MCU_STATE_MAX 4 | |
64 | `define DRIF_MCU_STATE_WIDTH 5 | |
65 | ||
66 | // | |
67 | // UCB Packet Type | |
68 | // =============== | |
69 | // | |
70 | `define UCB_READ_NACK 4'b0000 // ack/nack types | |
71 | `define UCB_READ_ACK 4'b0001 | |
72 | `define UCB_WRITE_ACK 4'b0010 | |
73 | `define UCB_IFILL_ACK 4'b0011 | |
74 | `define UCB_IFILL_NACK 4'b0111 | |
75 | ||
76 | `define UCB_READ_REQ 4'b0100 // req types | |
77 | `define UCB_WRITE_REQ 4'b0101 | |
78 | `define UCB_IFILL_REQ 4'b0110 | |
79 | ||
80 | `define UCB_INT 4'b1000 // plain interrupt | |
81 | `define UCB_INT_VEC 4'b1100 // interrupt with vector | |
82 | `define UCB_RESET_VEC 4'b1101 // reset with vector | |
83 | `define UCB_IDLE_VEC 4'b1110 // idle with vector | |
84 | `define UCB_RESUME_VEC 4'b1111 // resume with vector | |
85 | ||
86 | ||
87 | // | |
88 | // UCB Data Packet Format | |
89 | // ====================== | |
90 | // | |
91 | `define UCB_NOPAY_PKT_WIDTH 64 // packet without payload | |
92 | `define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload | |
93 | `define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload | |
94 | ||
95 | `define UCB_DATA_EXT_HI 191 // (64) extended data | |
96 | `define UCB_DATA_EXT_LO 128 | |
97 | `define UCB_DATA_HI 127 // (64) data | |
98 | `define UCB_DATA_LO 64 | |
99 | `define UCB_RSV_HI 63 // (9) reserved bits | |
100 | `define UCB_RSV_LO 55 | |
101 | `define UCB_ADDR_HI 54 // (40) bit address | |
102 | `define UCB_ADDR_LO 15 | |
103 | `define UCB_SIZE_HI 14 // (3) request size | |
104 | `define UCB_SIZE_LO 12 | |
105 | `define UCB_BUF_HI 11 // (2) buffer ID | |
106 | `define UCB_BUF_LO 10 | |
107 | `define UCB_THR_HI 9 // (6) cpu/thread ID | |
108 | `define UCB_THR_LO 4 | |
109 | `define UCB_PKT_HI 3 // (4) packet type | |
110 | `define UCB_PKT_LO 0 | |
111 | ||
112 | `define UCB_DATA_EXT_WIDTH 64 | |
113 | `define UCB_DATA_WIDTH 64 | |
114 | `define UCB_RSV_WIDTH 9 | |
115 | `define UCB_ADDR_WIDTH 40 | |
116 | `define UCB_SIZE_WIDTH 3 | |
117 | `define UCB_BUF_WIDTH 2 | |
118 | `define UCB_THR_WIDTH 6 | |
119 | `define UCB_PKT_WIDTH 4 | |
120 | ||
121 | // Size encoding for the UCB_SIZE_HI/LO field | |
122 | // 000 - byte | |
123 | // 001 - half-word | |
124 | // 010 - word | |
125 | // 011 - double-word | |
126 | `define UCB_SIZE_1B 3'b000 | |
127 | `define UCB_SIZE_2B 3'b001 | |
128 | `define UCB_SIZE_4B 3'b010 | |
129 | `define UCB_SIZE_8B 3'b011 | |
130 | `define UCB_SIZE_16B 3'b100 | |
131 | ||
132 | ||
133 | // | |
134 | // UCB Interrupt Packet Format | |
135 | // =========================== | |
136 | // | |
137 | `define UCB_INT_PKT_WIDTH 64 | |
138 | ||
139 | `define UCB_INT_RSV_HI 63 // (7) reserved bits | |
140 | `define UCB_INT_RSV_LO 57 | |
141 | `define UCB_INT_VEC_HI 56 // (6) interrupt vector | |
142 | `define UCB_INT_VEC_LO 51 | |
143 | `define UCB_INT_STAT_HI 50 // (32) interrupt status | |
144 | `define UCB_INT_STAT_LO 19 | |
145 | `define UCB_INT_DEV_HI 18 // (9) device ID | |
146 | `define UCB_INT_DEV_LO 10 | |
147 | //`define UCB_THR_HI 9 // (6) cpu/thread ID shared with | |
148 | //`define UCB_THR_LO 4 data packet format | |
149 | //`define UCB_PKT_HI 3 // (4) packet type shared with | |
150 | //`define UCB_PKT_LO 0 // data packet format | |
151 | ||
152 | `define UCB_INT_RSV_WIDTH 7 | |
153 | `define UCB_INT_VEC_WIDTH 6 | |
154 | `define UCB_INT_STAT_WIDTH 32 | |
155 | `define UCB_INT_DEV_WIDTH 9 | |
156 | ||
157 | ||
158 | `define MCU_CAS_BIT2_SEL_PA10 4'h1 | |
159 | `define MCU_CAS_BIT2_SEL_PA32 4'h2 | |
160 | `define MCU_CAS_BIT2_SEL_PA33 4'h4 | |
161 | `define MCU_CAS_BIT2_SEL_PA34 4'h8 | |
162 | ||
163 | `define MCU_CAS_BIT3_SEL_PA11 4'h1 | |
164 | `define MCU_CAS_BIT3_SEL_PA33 4'h2 | |
165 | `define MCU_CAS_BIT3_SEL_PA34 4'h4 | |
166 | `define MCU_CAS_BIT3_SEL_PA35 4'h8 | |
167 | ||
168 | `define MCU_CAS_BIT4_SEL_PA12 3'h1 | |
169 | `define MCU_CAS_BIT4_SEL_PA35 3'h2 | |
170 | `define MCU_CAS_BIT4_SEL_PA36 3'h4 | |
171 | ||
172 | `define MCU_DIMMHI_SEL_ZERO 6'h01 | |
173 | `define MCU_DIMMHI_SEL_PA32 6'h02 | |
174 | `define MCU_DIMMHI_SEL_PA33 6'h04 | |
175 | `define MCU_DIMMHI_SEL_PA34 6'h08 | |
176 | `define MCU_DIMMHI_SEL_PA35 6'h10 | |
177 | `define MCU_DIMMHI_SEL_PA36 6'h20 | |
178 | ||
179 | `define MCU_DIMMLO_SEL_ZERO 4'h1 | |
180 | `define MCU_DIMMLO_SEL_PA10 4'h2 | |
181 | `define MCU_DIMMLO_SEL_PA11 4'h4 | |
182 | `define MCU_DIMMLO_SEL_PA12 4'h8 | |
183 | ||
184 | `define MCU_RANK_SEL_ZERO 7'h01 | |
185 | `define MCU_RANK_SEL_PA32 7'h02 | |
186 | `define MCU_RANK_SEL_PA33 7'h04 | |
187 | `define MCU_RANK_SEL_PA34 7'h08 | |
188 | `define MCU_RANK_SEL_PA35 7'h10 | |
189 | `define MCU_RANK_SEL_PA10 7'h20 | |
190 | `define MCU_RANK_SEL_PA11 7'h40 | |
191 | ||
192 | `define MCU_ADDR_ERR_SEL_39_32 6'h01 | |
193 | `define MCU_ADDR_ERR_SEL_39_33 6'h02 | |
194 | `define MCU_ADDR_ERR_SEL_39_34 6'h04 | |
195 | `define MCU_ADDR_ERR_SEL_39_35 6'h08 | |
196 | `define MCU_ADDR_ERR_SEL_39_36 6'h10 | |
197 | `define MCU_ADDR_ERR_SEL_39_37 6'h20 | |
198 | ||
199 | `define DRIF_ERR_IDLE 0 | |
200 | `define DRIF_ERR_IDLE_ST 5'h1 | |
201 | `define DRIF_ERR_READ0 1 | |
202 | `define DRIF_ERR_READ0_ST 5'h2 | |
203 | `define DRIF_ERR_WRITE 2 | |
204 | `define DRIF_ERR_WRITE_ST 5'h4 | |
205 | `define DRIF_ERR_READ1 3 | |
206 | `define DRIF_ERR_READ1_ST 5'h8 | |
207 | `define DRIF_ERR_CRC_FR 4 | |
208 | `define DRIF_ERR_CRC_FR_ST 5'h10 | |
209 | ||
210 | `define MCU_WDQ_RF_DATA_WIDTH 72 | |
211 | `define MCU_WDQ_RF_ADDR_WIDTH 5 | |
212 | `define MCU_WDQ_RF_DEPTH 32 | |
213 | ||
214 | // FBDIMM header defines | |
215 | `define FBD_TS0_HDR 12'hbfe | |
216 | `define FBD_TS1_HDR 12'hffe | |
217 | `define FBD_TS2_HDR 12'h7fe | |
218 | `define FBD_TS3_HDR 12'h3fe | |
219 | ||
220 | // MCU FBDIMM Channel commands | |
221 | `define FBD_DRAM_CMD_NOP 3'h0 | |
222 | `define FBD_DRAM_CMD_OTHER 3'h1 | |
223 | `define FBD_DRAM_CMD_RD 3'h2 | |
224 | `define FBD_DRAM_CMD_WR 3'h3 | |
225 | `define FBD_DRAM_CMD_ACT 3'h4 | |
226 | `define FBD_DRAM_CMD_WDATA 3'h5 | |
227 | ||
228 | `define FBD_DRAM_CMD_OTHER_REF 3'h5 | |
229 | `define FBD_DRAM_CMD_OTHER_SRE 3'h4 | |
230 | `define FBD_DRAM_CMD_OTHER_PDE 3'h2 | |
231 | `define FBD_DRAM_CMD_OTHER_SRPDX 3'h3 | |
232 | ||
233 | `define FBD_CHNL_CMD_NOP 2'h0 | |
234 | `define FBD_CHNL_CMD_SYNC 2'h1 | |
235 | `define FBD_CHNL_CMD_SCRST 2'h2 | |
236 | ||
237 | `define FBDIC_ERR_IDLE_ST 7'h01 | |
238 | `define FBDIC_ERR_IDLE 0 | |
239 | ||
240 | `define FBDIC_ERR_STS_ST 7'h02 | |
241 | `define FBDIC_ERR_STS 1 | |
242 | ||
243 | `define FBDIC_ERR_SCRST_ST 7'h04 | |
244 | `define FBDIC_ERR_SCRST 2 | |
245 | ||
246 | `define FBDIC_ERR_SCRST_STS_ST 7'h08 | |
247 | `define FBDIC_ERR_SCRST_STS 3 | |
248 | ||
249 | `define FBDIC_ERR_STS2_ST 7'h10 | |
250 | `define FBDIC_ERR_STS2 4 | |
251 | ||
252 | `define FBDIC_ERR_FASTRST_ST 7'h20 | |
253 | `define FBDIC_ERR_FASTRST 5 | |
254 | ||
255 | `define FBDIC_ERR_FASTRST_STS_ST 7'h40 | |
256 | `define FBDIC_ERR_FASTRST_STS 6 | |
257 | ||
258 | ||
259 | // IBIST DEFINITION | |
260 | ||
261 | `define L_2_0 12'h555 | |
262 | `define L_2_1 12'h555 | |
263 | `define L_4_0 12'h333 | |
264 | `define L_4_1 12'h333 | |
265 | `define L_6_0 12'h1c7 | |
266 | `define L_6_1 12'h1c7 | |
267 | `define L_8_0 12'h0f0 | |
268 | `define L_8_1 12'hf0f | |
269 | `define L_24_0 12'h000 | |
270 | `define L_24_1 12'hfff | |
271 | ||
272 | `define idle 4'h0 | |
273 | ||
274 | `define error_0 4'h1 | |
275 | `define error_1 4'h2 | |
276 | ||
277 | `define start1_0 4'h3 | |
278 | `define start1_1 4'h4 | |
279 | `define start2_0 4'h5 | |
280 | `define start2_1 4'h6 | |
281 | ||
282 | `define pat1_0 4'h7 | |
283 | `define pat1_1 4'h8 | |
284 | ||
285 | `define clkpat_0 4'h9 | |
286 | `define clkpat_1 4'ha | |
287 | ||
288 | `define const_0 4'hb | |
289 | `define const_1 4'hc | |
290 | ||
291 | `define stop1_0 4'h1 | |
292 | `define stop1_1 4'h2 | |
293 | ||
294 | `define stop2_0 4'hd | |
295 | `define stop2_1 4'he | |
296 | `define error 4'hf | |
297 | ||
298 | `define IBTX_STATE_IDLE 0 | |
299 | `define IBTX_STATE_PATT 1 | |
300 | `define IBTX_STATE_MODN 2 | |
301 | `define IBTX_STATE_CONST 3 | |
302 | ||
303 | `define IBRX_STATE_IDLE 0 | |
304 | `define IBRX_STATE_PATT 1 | |
305 | `define IBRX_STATE_MODN 2 | |
306 | `define IBRX_STATE_CONST 3 | |
307 | ||
308 | ||
309 | ||
310 | module mcu_fbdic_ctl ( | |
311 | fbdic_data_sel, | |
312 | fbdic0_ts_data, | |
313 | fbdic1_ts_data, | |
314 | fbdic_ibist_data, | |
315 | fbdic_f, | |
316 | fbdic_f_1_l, | |
317 | fbdic0_chnl_disable, | |
318 | fbdic1_chnl_disable, | |
319 | fbdic_a_cmd, | |
320 | fbdic_bc_cmd, | |
321 | fbdic0_cmd_crc_sel, | |
322 | fbdic0_data_crc_sel, | |
323 | fbdic0_sb_failover, | |
324 | fbdic0_sb_failover_l, | |
325 | fbdic0_sb_failover_mask, | |
326 | fbdic0_sb_failover_mask_l, | |
327 | fbdic0_nb_failover, | |
328 | fbdic0_nb_failover_l, | |
329 | fbdic0_nb_failover_mask, | |
330 | fbdic0_nb_failover_mask_l, | |
331 | fbdic1_cmd_crc_sel, | |
332 | fbdic1_data_crc_sel, | |
333 | fbdic1_sb_failover, | |
334 | fbdic1_sb_failover_l, | |
335 | fbdic1_sb_failover_mask, | |
336 | fbdic1_sb_failover_mask_l, | |
337 | fbdic1_nb_failover, | |
338 | fbdic1_nb_failover_l, | |
339 | fbdic1_nb_failover_mask, | |
340 | fbdic1_nb_failover_mask_l, | |
341 | fbdic_ucb_rd_data, | |
342 | fbdic_train_state, | |
343 | fbdic_disable_state, | |
344 | fbdic_enable_sync_count, | |
345 | fbdic_sync_frame_req_early3, | |
346 | fbdic_sync_frame_req_early2, | |
347 | fbdic_sync_frame_req_early1, | |
348 | fbdic_sync_frame_req, | |
349 | fbdic_sync_frame_req_d1, | |
350 | fbdic_scr_frame_req_d4, | |
351 | fbdic_l0_state, | |
352 | fbdic_l0s_lfsr_stall, | |
353 | fbdic_err_fast_reset_done, | |
354 | fbdic_chnl_reset_error, | |
355 | fbdic_chnl_reset_error_mode, | |
356 | fbdic_special_cmd, | |
357 | fbdic_special_cmd_l, | |
358 | fbdic_ibrx_data_sel, | |
359 | fbdic_ibrx_data_sel_l, | |
360 | fbdic_rddata_vld, | |
361 | fbdic_rddata_vld_l, | |
362 | fbdic_woq_free, | |
363 | fbdic_clear_wrq_ent, | |
364 | fbdic_error_mode, | |
365 | fbdic_fbd_error, | |
366 | fbdic_crc_error, | |
367 | fbdic_err_unrecov, | |
368 | fbdic_err_recov, | |
369 | fbdic_err_fbr, | |
370 | fbdic0_inc_wptr, | |
371 | fbdic0_inc_rptr, | |
372 | fbdic0_clr_ptrs, | |
373 | fbdic1_inc_wptr, | |
374 | fbdic1_inc_rptr, | |
375 | fbdic1_clr_ptrs, | |
376 | fbdic_idle_lfsr_reset, | |
377 | mcu_fsr0_cfgpll_enpll, | |
378 | mcu_fsr1_cfgpll_enpll, | |
379 | mcu_fsr01_cfgpll_lb, | |
380 | mcu_fsr01_cfgpll_mpy, | |
381 | mcu_fsr0_cfgrx_enrx, | |
382 | mcu_fsr1_cfgrx_enrx, | |
383 | mcu_fsr0_cfgrx_entest, | |
384 | mcu_fsr1_cfgrx_entest, | |
385 | mcu_fsr0_cfgrx_align, | |
386 | mcu_fsr1_cfgrx_align, | |
387 | mcu_fsr0_cfgrx_invpair, | |
388 | mcu_fsr1_cfgrx_invpair, | |
389 | mcu_fsr01_cfgrx_eq, | |
390 | mcu_fsr01_cfgrx_cdr, | |
391 | mcu_fsr01_cfgrx_term, | |
392 | mcu_fsr0_cfgtx_entx, | |
393 | mcu_fsr1_cfgtx_entx, | |
394 | mcu_fsr0_cfgtx_entest, | |
395 | mcu_fsr1_cfgtx_entest, | |
396 | mcu_fsr0_cfgtx_enidl, | |
397 | mcu_fsr1_cfgtx_enidl, | |
398 | mcu_fsr0_cfgtx_invpair, | |
399 | mcu_fsr1_cfgtx_invpair, | |
400 | mcu_fsr01_cfgtx_enftp, | |
401 | mcu_fsr01_cfgtx_de, | |
402 | mcu_fsr01_cfgtx_swing, | |
403 | mcu_fsr01_cfgtx_cm, | |
404 | mcu_fsr01_cfgrtx_rate, | |
405 | mcu_fsr0_testcfg, | |
406 | mcu_fsr1_testcfg, | |
407 | fbdic_link_cnt_en, | |
408 | fbdic_link_cnt_reset, | |
409 | rdpctl_kp_lnk_up, | |
410 | rdpctl_kp_lnk_up_clr, | |
411 | fbdic_serdes_dtm, | |
412 | fbdic_srds_dtm_muxsel, | |
413 | fbdic_cfgrd_crc_error, | |
414 | fbdic_mcu_idle, | |
415 | fbd0_elect_idle, | |
416 | fbd1_elect_idle, | |
417 | fbd0_frame_lock, | |
418 | fbd1_frame_lock, | |
419 | fbd0_testfail, | |
420 | fbd1_testfail, | |
421 | drif_ucb_wr_req_vld, | |
422 | drif_ucb_rd_req_vld, | |
423 | drif_ucb_addr, | |
424 | drif_ucb_data, | |
425 | lndskw0_data, | |
426 | lndskw1_data, | |
427 | fbdird_ibrx_data, | |
428 | drif_dram_cmd_a, | |
429 | drif_dram_addr_a, | |
430 | drif_dram_bank_a, | |
431 | drif_dram_dimm_a, | |
432 | drif_dram_rank_a, | |
433 | drif_dram_cmd_b, | |
434 | drif_dram_addr_b, | |
435 | drif_dram_bank_b, | |
436 | drif_dram_dimm_b, | |
437 | drif_dram_rank_b, | |
438 | drif_wdata_wsn, | |
439 | woq_err_st_wait_free, | |
440 | drif_dram_cmd_c, | |
441 | drif_dram_addr_c, | |
442 | drif_dram_bank_c, | |
443 | drif_dram_dimm_c, | |
444 | drif_dram_rank_c, | |
445 | drif_single_channel_mode, | |
446 | drif_branch_disabled, | |
447 | drif_mcu_idle, | |
448 | drif_cke_reg, | |
449 | drif_stacked_dimm, | |
450 | drif_num_dimms, | |
451 | rdpctl_fifo_empty, | |
452 | rdpctl_crc_recov_err, | |
453 | rdpctl_crc_unrecov_err, | |
454 | rdpctl_mask_err, | |
455 | drif_dbg_trig_reg_ld, | |
456 | fdout_link_cnt, | |
457 | drif_err_state_crc_fr, | |
458 | rdata_err_fbui, | |
459 | rdata_err_fbri, | |
460 | fbdird_crc_cmp0_0, | |
461 | fbdird_crc_cmp0_1, | |
462 | fbdird_crc_cmp1_0, | |
463 | fbdird_crc_cmp1_1, | |
464 | lndskw0_ts0_hdr_match, | |
465 | lndskw1_ts0_hdr_match, | |
466 | lndskw0_status_parity, | |
467 | lndskw1_status_parity, | |
468 | lndskw0_idle_match, | |
469 | lndskw1_idle_match, | |
470 | lndskw0_alert_match, | |
471 | lndskw1_alert_match, | |
472 | lndskw0_alert_asserted, | |
473 | lndskw1_alert_asserted, | |
474 | lndskw0_nbde, | |
475 | lndskw1_nbde, | |
476 | lndskw0_thermal_trip, | |
477 | lndskw1_thermal_trip, | |
478 | fbdird0_cnfgreg_data, | |
479 | fbdird1_cnfgreg_data, | |
480 | fsr0_mcu_stspll_lock, | |
481 | fsr1_mcu_stspll_lock, | |
482 | fsr0_mcu_ststx_testfail, | |
483 | fsr1_mcu_ststx_testfail, | |
484 | rdpctl_dtm_atspeed, | |
485 | ccu_serdes_dtm, | |
486 | mcu_gnd, | |
487 | drl2clk, | |
488 | scan_in, | |
489 | scan_out, | |
490 | wmr_scan_in, | |
491 | fbdic_wmr_scanout, | |
492 | tcu_pce_ov, | |
493 | tcu_aclk, | |
494 | tcu_bclk, | |
495 | aclk_wmr, | |
496 | tcu_scan_en, | |
497 | wmr_protect, | |
498 | tcu_mcu_testmode, | |
499 | fbdtm_si, | |
500 | fbdtm_so, | |
501 | fbdtm_wmr_si, | |
502 | fbdtm_wmr_so); | |
503 | wire pce_ov; | |
504 | wire siclk; | |
505 | wire soclk; | |
506 | wire se; | |
507 | wire l1clk; | |
508 | wire fbdic_fbd_state_ld; | |
509 | wire fbdic_fbd_state_en; | |
510 | wire fbdic_fbd_chnl_init_seq; | |
511 | wire [7:0] fbdic_fbd_state; | |
512 | wire fbdic_tdisable_done; | |
513 | wire fbdic_tcalibrate_done; | |
514 | wire [1:0] fbdic_tclktrain_done; | |
515 | wire fbdic_tclktrain_to_done; | |
516 | wire [1:0] fbdic_testing_done; | |
517 | wire fbdic_testing_to_done; | |
518 | wire [1:0] fbdic_polling_done; | |
519 | wire fbdic_polling_to_done; | |
520 | wire [1:0] fbdic_config_done; | |
521 | wire fbdic_config_to_done; | |
522 | wire fbdic_sync_frame_req_d4; | |
523 | wire fbdic_chnl_reset_ld; | |
524 | wire fbdic_ibtx_start_ld; | |
525 | wire fbdic_dtm_fbd_state0_en; | |
526 | wire fbdic_dtm_fbd_state2_en; | |
527 | wire fbdic_dtm_fbd_state6_en; | |
528 | wire [1:0] fbdic_chnl_reset; | |
529 | wire fbdic_ibtx_start; | |
530 | wire fbdic_ibist_done; | |
531 | wire [7:0] fbdic_fbd_state_in; | |
532 | wire fbdic_fast_reset; | |
533 | wire fbdic_sbcaliben; | |
534 | wire pff_fbd_state_wmr_scanin; | |
535 | wire pff_fbd_state_wmr_scanout; | |
536 | wire ff_fbd_state_scanin; | |
537 | wire ff_fbd_state_scanout; | |
538 | wire fbdic_calibrate_state; | |
539 | wire fbdic_testing_state; | |
540 | wire fbdic_polling_state; | |
541 | wire fbdic_config_state; | |
542 | wire fbdic_fast_reset_en; | |
543 | wire [3:0] fbdic_fast_reset_in; | |
544 | wire fbdic_fast_reset_3_en; | |
545 | wire fbdic_sync_ier_enable; | |
546 | wire pff_fast_reset_wmr_scanin; | |
547 | wire pff_fast_reset_3_wmr_scanout; | |
548 | wire pff_fast_reset_wmr_scanout; | |
549 | wire [1:0] fbdic_sync_r; | |
550 | wire fbdic_sync_ier_in; | |
551 | wire ff_sync_ier_scanin; | |
552 | wire ff_sync_ier_scanout; | |
553 | wire fbdic_sync_ier; | |
554 | wire fbdic_fr_issued_in; | |
555 | wire fbdic_err_fast_chnl_reset; | |
556 | wire fast_reset_err; | |
557 | wire [6:0] fbdic_err_state; | |
558 | wire fbdic_fr_issued; | |
559 | wire ff_fr_issued_scanin; | |
560 | wire ff_fr_issued_scanout; | |
561 | wire fbdic_sync_erc; | |
562 | wire fast_reset_err_on_first_sync; | |
563 | wire fbdic_idle_lfsr_reset_d1; | |
564 | wire fbdic_idle_frame; | |
565 | wire fbdic_chnl_reset_en; | |
566 | wire fbdic_chnl_reset_clr; | |
567 | wire [1:0] fbdic_chnl_reset_in; | |
568 | wire pff_chnl_reset1_wmr_scanin; | |
569 | wire pff_chnl_reset1_wmr_scanout; | |
570 | wire pff_chnl_reset0_scanin; | |
571 | wire pff_chnl_reset0_scanout; | |
572 | wire fbdic_chnl_reset_error_mode_in; | |
573 | wire ff_chnl_reset_error_mode_scanin; | |
574 | wire ff_chnl_reset_error_mode_scanout; | |
575 | wire fbdic_sb2nb_map_en; | |
576 | wire [3:0] fbdic_sb2nb_map_in; | |
577 | wire pff_sb2nb_map_wmr_scanin; | |
578 | wire pff_sb2nb_map_wmr_scanout; | |
579 | wire [3:0] fbdic_sb2nb_map; | |
580 | wire fbdic_amb_test_param_en; | |
581 | wire [23:0] fbdic_amb_test_param_in; | |
582 | wire pff_amb_test_param_wmr_scanin; | |
583 | wire pff_amb_test_param_wmr_scanout; | |
584 | wire [23:0] fbdic_amb_test_param; | |
585 | wire fbdic_failover_config_en; | |
586 | wire [15:0] fbdic_failover_config_in; | |
587 | wire [15:0] inv_fbdic_failover_config_in; | |
588 | wire [15:0] fbdic_failover_config; | |
589 | wire [15:0] inv_fbdic_failover_config; | |
590 | wire pff_failover_config_wmr_scanin; | |
591 | wire pff_failover_config_wmr_scanout; | |
592 | wire [27:0] inv_fbdic_elect_idle_detect_in; | |
593 | wire [27:0] fbdic_elect_idle_detect; | |
594 | wire [27:0] inv_fbdic_elect_idle_detect; | |
595 | wire ff_elect_idle_detect_scanin; | |
596 | wire ff_elect_idle_detect_scanout; | |
597 | wire fbdic_tdisable_period_en; | |
598 | wire [9:0] fbdic_tdisable_period_in; | |
599 | wire [7:0] inv_fbdic_tdisable_period_in; | |
600 | wire [9:0] fbdic_tdisable_period; | |
601 | wire [7:0] inv_fbdic_tdisable_period; | |
602 | wire pff_tdisable_period_wmr_scanin; | |
603 | wire pff_tdisable_period_wmr_scanout; | |
604 | wire fbdic_enter_disable_state; | |
605 | wire fbdic_tdisable_done_en; | |
606 | wire [9:0] fbdic_tdisable_cnt; | |
607 | wire fbdic_tdisable_done_in; | |
608 | wire ff_tdisable_done_scanin; | |
609 | wire ff_tdisable_done_scanout; | |
610 | wire [9:0] fbdic_tdisable_cnt_in; | |
611 | wire fbdic_tdisable_start; | |
612 | wire [9:0] fbdic_sbdiscnt; | |
613 | wire [9:0] inv_fbdic_tdisable_cnt_in; | |
614 | wire [9:0] inv_fbdic_tdisable_cnt; | |
615 | wire ff_tdisable_cnt_scanin; | |
616 | wire ff_tdisable_cnt_scanout; | |
617 | wire fbdic_tdisable_start_in; | |
618 | wire ff_tdisable_start_scanin; | |
619 | wire ff_tdisable_start_scanout; | |
620 | wire fbdic_tcalibrate_period_en; | |
621 | wire [19:0] fbdic_tcalibrate_period_in; | |
622 | wire pff_tcalibrate_period_wmr_scanin; | |
623 | wire pff_tcalibrate_period_wmr_scanout; | |
624 | wire [19:0] fbdic_tcalibrate_period; | |
625 | wire fbdic_tcalibrate_done_en; | |
626 | wire [19:0] fbdic_tcalibrate_cnt; | |
627 | wire fbdic_tcalibrate_done_in; | |
628 | wire ff_tcalibrate_done_scanin; | |
629 | wire ff_tcalibrate_done_scanout; | |
630 | wire [19:0] fbdic_tcalibrate_cnt_in; | |
631 | wire [19:0] fbdic_sbibistcalperiod; | |
632 | wire ff_tcalibrate_cnt_scanin; | |
633 | wire ff_tcalibrate_cnt_scanout; | |
634 | wire fbdic_tclktrain_min_en; | |
635 | wire [15:0] fbdic_tclktrain_min_in; | |
636 | wire [7:0] inv_fbdic_tclktrain_min_in; | |
637 | wire [15:0] fbdic_tclktrain_min; | |
638 | wire [7:0] inv_fbdic_tclktrain_min; | |
639 | wire pff_tclktrain_min_wmr_scanin; | |
640 | wire pff_tclktrain_min_wmr_scanout; | |
641 | wire [15:0] fbdic_tclktrain_min_cnt_in; | |
642 | wire [15:0] fbdic_tclktrain_min_cnt; | |
643 | wire ff_tclktrain_min_cnt_scanin; | |
644 | wire ff_tclktrain_min_cnt_scanout; | |
645 | wire fbdic_enable_sync_count_in; | |
646 | wire [1:0] fbdic_loopback; | |
647 | wire ff_enable_sync_count_scanin; | |
648 | wire ff_enable_sync_count_scanout; | |
649 | wire fbdic_tclktrain_rst_done; | |
650 | wire [3:0] fbdic0_ts_match_cnt; | |
651 | wire [15:0] fbdic_tclktrain_timeout_cnt; | |
652 | wire fbdic_tclktrain_ibst_done; | |
653 | wire [9:0] fbdic_sbts_cnt; | |
654 | wire fbdic_tclktrain_done_en; | |
655 | wire [1:0] fbdic_tclktrain_done_in; | |
656 | wire ff_tclktrain_done_scanin; | |
657 | wire ff_tclktrain_done_scanout; | |
658 | wire fbdic_tclktrain_timeout_en; | |
659 | wire [15:0] fbdic_tclktrain_timeout_in; | |
660 | wire [15:0] inv_fbdic_tclktrain_timeout_in; | |
661 | wire [15:0] fbdic_tclktrain_timeout; | |
662 | wire [15:0] inv_fbdic_tclktrain_timeout; | |
663 | wire pff_tclktrain_timeout_wmr_scanin; | |
664 | wire pff_tclktrain_timeout_wmr_scanout; | |
665 | wire [15:0] fbdic_tclktrain_timeout_cnt_in; | |
666 | wire fbdic_ibist_data_mode; | |
667 | wire ff_tclktrain_timeout_cnt_scanin; | |
668 | wire ff_tclktrain_timeout_cnt_scanout; | |
669 | wire fbdic_testing_rst_done; | |
670 | wire [7:0] fbdic_testing_timeout_cnt; | |
671 | wire fbdic_testing_ibst_done; | |
672 | wire ibtx_done; | |
673 | wire fbdic_testing_done_en; | |
674 | wire [1:0] fbdic_testing_done_in; | |
675 | wire ff_testing_done_scanin; | |
676 | wire ff_testing_done_scanout; | |
677 | wire fbdic_testing_timeout_en; | |
678 | wire [7:0] fbdic_testing_timeout_in; | |
679 | wire [7:0] inv_fbdic_testing_timeout_in; | |
680 | wire [7:0] fbdic_testing_timeout; | |
681 | wire [7:0] inv_fbdic_testing_timeout; | |
682 | wire pff_testing_timeout_wmr_scanin; | |
683 | wire pff_testing_timeout_wmr_scanout; | |
684 | wire [7:0] fbdic_testing_timeout_cnt_in; | |
685 | wire ff_testing_timeout_cnt_scanin; | |
686 | wire ff_testing_timeout_cnt_scanout; | |
687 | wire fbdic_polling_rst_done; | |
688 | wire [7:0] fbdic_polling_timeout_cnt; | |
689 | wire fbdic_polling_ibst_done; | |
690 | wire fbdic_polling_done_en; | |
691 | wire [1:0] fbdic_polling_done_in; | |
692 | wire ff_polling_done_scanin; | |
693 | wire ff_polling_done_scanout; | |
694 | wire fbdic_polling_timeout_en; | |
695 | wire [7:0] fbdic_polling_timeout_in; | |
696 | wire [7:0] inv_fbdic_polling_timeout_in; | |
697 | wire [7:0] fbdic_polling_timeout; | |
698 | wire [7:0] inv_fbdic_polling_timeout; | |
699 | wire pff_polling_timeout_wmr_scanin; | |
700 | wire pff_polling_timeout_wmr_scanout; | |
701 | wire [7:0] fbdic_polling_timeout_cnt_in; | |
702 | wire ff_polling_timeout_cnt_scanin; | |
703 | wire ff_polling_timeout_cnt_scanout; | |
704 | wire fbdic_config_rst_done; | |
705 | wire [7:0] fbdic_config_timeout_cnt; | |
706 | wire fbdic_config_ibst_done; | |
707 | wire fbdic_config_done_en; | |
708 | wire [1:0] fbdic_config_done_in; | |
709 | wire ff_config_done_scanin; | |
710 | wire ff_config_done_scanout; | |
711 | wire fbdic_config_timeout_en; | |
712 | wire [7:0] fbdic_config_timeout_in; | |
713 | wire [7:0] inv_fbdic_config_timeout_in; | |
714 | wire [7:0] fbdic_config_timeout; | |
715 | wire [7:0] inv_fbdic_config_timeout; | |
716 | wire pff_config_timeout_wmr_scanin; | |
717 | wire pff_config_timeout_wmr_scanout; | |
718 | wire [7:0] fbdic_config_timeout_cnt_in; | |
719 | wire ff_config_timeout_cnt_scanin; | |
720 | wire ff_config_timeout_cnt_scanout; | |
721 | wire fbdic_per_rank_cke_en; | |
722 | wire [15:0] fbdic_per_rank_cke_in; | |
723 | wire [15:0] inv_fbdic_per_rank_cke_in; | |
724 | wire [15:0] fbdic_per_rank_cke; | |
725 | wire [15:0] inv_fbdic_per_rank_cke; | |
726 | wire pff_per_rank_cke_wmr_scanin; | |
727 | wire pff_per_rank_cke_wmr_scanout; | |
728 | wire fbdic_cke_cmd_pend_in; | |
729 | wire fbdic_cke_reg_d1; | |
730 | wire fbdic_scr_frame_req_d5; | |
731 | wire fbdic_issue_cke_cmd; | |
732 | wire fbdic_cke_cmd_pend; | |
733 | wire fbdic_config_reg_access_rdy; | |
734 | wire ff_cke_reg_d1_scanin; | |
735 | wire ff_cke_reg_d1_scanout; | |
736 | wire [23:0] fbdic_lower_cke_cmd; | |
737 | wire [23:0] fbdic_upper_cke_cmd; | |
738 | wire fbdic_l0s_time_en; | |
739 | wire [6:0] fbdic_l0s_time_in; | |
740 | wire [6:0] fbdic_l0s_time; | |
741 | wire [6:0] fbdic_l0s_time_out; | |
742 | wire pff_l0s_time_wmr_scanin; | |
743 | wire pff_l0s_time_wmr_scanout; | |
744 | wire fbdic_l0s_enable; | |
745 | wire fbdic_sync_el0s; | |
746 | wire fbdic_l0s_stall_in; | |
747 | wire fbdic_l0s_stall; | |
748 | wire fbdic_mcu_idle_in; | |
749 | wire ff_l0s_stall_scanin; | |
750 | wire ff_l0s_stall_scanout; | |
751 | wire fbdic_loopback_en; | |
752 | wire [1:0] fbdic_loopback_in; | |
753 | wire ff_loopback_scanin; | |
754 | wire ff_loopback_scanout; | |
755 | wire [5:0] fbdic_sds_pll_status; | |
756 | wire sync_stspll5_scanin; | |
757 | wire sync_stspll5_scanout; | |
758 | wire sync_stspll4_scanin; | |
759 | wire sync_stspll4_scanout; | |
760 | wire sync_stspll3_scanin; | |
761 | wire sync_stspll3_scanout; | |
762 | wire sync_stspll2_scanin; | |
763 | wire sync_stspll2_scanout; | |
764 | wire sync_stspll1_scanin; | |
765 | wire sync_stspll1_scanout; | |
766 | wire sync_stspll0_scanin; | |
767 | wire sync_stspll0_scanout; | |
768 | wire [29:0] fbdic_sds_config; | |
769 | wire [47:0] fbdic_sds_invert; | |
770 | wire [31:0] fbdic_sds_testcfg; | |
771 | wire ff_sds_test_status_scanin; | |
772 | wire ff_sds_test_status_scanout; | |
773 | wire [47:0] fbdic_sds_test_status; | |
774 | wire fbdic_config_reg_addr_en; | |
775 | wire [15:2] fbdic_config_reg_addr_in; | |
776 | wire ff_config_reg_addr_scanin; | |
777 | wire ff_config_reg_addr_scanout; | |
778 | wire [15:2] fbdic_config_reg_addr; | |
779 | wire fbdic_cnfgreg_wr_pend_in; | |
780 | wire fbdic_config_reg_write; | |
781 | wire fbdic_cnfgreg_wr_pend; | |
782 | wire fbdic_cnfgreg_rd_pend_in; | |
783 | wire fbdic_config_reg_read; | |
784 | wire fbdic_cnfgreg_rd_pend; | |
785 | wire fbdic_inj_crc_err; | |
786 | wire fbdic_cnfgreg_rddata_vld; | |
787 | wire ff_cnfg_access_pending_scanin; | |
788 | wire ff_cnfg_access_pending_scanout; | |
789 | wire [31:0] fbdic_cnfgreg_wr_data_in; | |
790 | wire fbdic_cnfgreg_wr_data_en; | |
791 | wire ff_cnfgreg_wr_data_scanin; | |
792 | wire ff_cnfgreg_wr_data_scanout; | |
793 | wire [31:0] fbdic_cnfgreg_wr_data; | |
794 | wire [1:0] fbdic_sync_sd; | |
795 | wire ff_config_reg_write_d1_scanin; | |
796 | wire ff_config_reg_write_d1_scanout; | |
797 | wire fbdic_config_reg_write_d1; | |
798 | wire [47:0] fbdic_thermal_trip_in; | |
799 | wire fbdic_thermal_trip_en; | |
800 | wire fbdic_status_frame; | |
801 | wire fbdic_status_parity_error_en; | |
802 | wire ff_thermal_trip_scanin; | |
803 | wire ff_thermal_trip_scanout; | |
804 | wire [47:0] fbdic_thermal_trip; | |
805 | wire fbdic_mcu_syndrome_en; | |
806 | wire [30:0] fbdic_mcu_syndrome; | |
807 | wire fbdic_fbu_error; | |
808 | wire fbdic_aa; | |
809 | wire fbdic_mcu_synd_aa; | |
810 | wire [30:0] fbdic_mcu_syndrome_in; | |
811 | wire [11:0] fbdic1_chnl_alert; | |
812 | wire [11:0] fbdic0_chnl_alert; | |
813 | wire fbdic_scr; | |
814 | wire fbdic_fr; | |
815 | wire fbdic_spe; | |
816 | wire fbdic_af; | |
817 | wire pff_mcu_syndrome_wmr_scanin; | |
818 | wire pff_mcu_syndrome_wmr_scanout; | |
819 | wire fbdic_mcu_synd_valid; | |
820 | wire fbdic_mcu_synd_fr; | |
821 | wire fbdic_fbu_error_in; | |
822 | wire ff_fbu_error_scanin; | |
823 | wire ff_fbu_error_scanout; | |
824 | wire fbdic_inj_err_src_en; | |
825 | wire [1:0] fbdic_inj_err_src_in; | |
826 | wire pff_inj_err_src_wmr_scanin; | |
827 | wire pff_inj_err_src_wmr_scanout; | |
828 | wire [1:0] fbdic_inj_err_src; | |
829 | wire fbdic_fbr_count_en; | |
830 | wire [16:0] fbdic_fbr_count; | |
831 | wire [16:0] fbdic_fbr_count_in; | |
832 | wire pff_fbr_count_wmr_scanin; | |
833 | wire pff_fbr_count_wmr_scanout; | |
834 | wire fbdic_err_fbr_in; | |
835 | wire ff_err_fbr_scanin; | |
836 | wire ff_err_fbr_scanout; | |
837 | wire ff_ts_data_scanin; | |
838 | wire ff_ts_data_scanout; | |
839 | wire [11:0] fbdic0_ts_data_in; | |
840 | wire [11:0] fbdic1_ts_data_in; | |
841 | wire [119:0] ibist_txdata; | |
842 | wire [7:0] init_state; | |
843 | wire [3:0] amb_id; | |
844 | wire [11:0] fbdic_amb_mask; | |
845 | wire fbdic_l0_state_in; | |
846 | wire ts3_cnt_en; | |
847 | wire [2:0] fbdic_l0_state_dly; | |
848 | wire ff_l0_state_scanin; | |
849 | wire ff_l0_state_scanout; | |
850 | wire [2:0] fbdic_l0_state_dly_in; | |
851 | wire ff_l0_state_dly_scanin; | |
852 | wire ff_l0_state_dly_scanout; | |
853 | wire [11:0] fbdic_ts_data_in; | |
854 | wire ts0_cnt_en; | |
855 | wire [11:0] ts0_data; | |
856 | wire ts1_cnt_en; | |
857 | wire [11:0] ts1_data; | |
858 | wire ts2_cnt_en; | |
859 | wire [11:0] ts2_data; | |
860 | wire [11:0] ts3_data0; | |
861 | wire [11:0] ts3_data1; | |
862 | wire [3:0] ts0_cnt_in; | |
863 | wire [3:0] ts0_cnt; | |
864 | wire ff_ts0_cnt_scanin; | |
865 | wire ff_ts0_cnt_scanout; | |
866 | wire [5:0] ts1_cnt_in; | |
867 | wire [5:0] ts1_cnt; | |
868 | wire ff_ts1_cnt_scanin; | |
869 | wire ff_ts1_cnt_scanout; | |
870 | wire [2:0] ts2_cnt_in; | |
871 | wire [2:0] ts2_cnt; | |
872 | wire ff_ts2_cnt_scanin; | |
873 | wire ff_ts2_cnt_scanout; | |
874 | wire [3:0] ts2_seq_id; | |
875 | wire [3:0] ts2_seq_id_in; | |
876 | wire ts2_seq_id_en; | |
877 | wire ts2_seq_id_clr; | |
878 | wire ff_ts2_seq_id_scanin; | |
879 | wire ff_ts2_seq_id_scanout; | |
880 | wire [2:0] ts3_cnt_in; | |
881 | wire [2:0] ts3_cnt; | |
882 | wire ff_ts3_cnt_scanin; | |
883 | wire ff_ts3_cnt_scanout; | |
884 | wire [11:0] fbdic0_nb_data; | |
885 | wire [11:0] fbdic1_nb_data; | |
886 | wire [3:0] fbdic_sequence_en; | |
887 | wire [1:0] fbdic_sequence_in; | |
888 | wire [1:0] fbdic_sequence; | |
889 | wire ff_sequence_scanin; | |
890 | wire ff_sequence_scanout; | |
891 | wire [11:0] fbdic0_ts_exp_data_in; | |
892 | wire [11:0] fbdic0_ts0_exp_in; | |
893 | wire [11:0] fbdic0_ts1_exp_in; | |
894 | wire [11:0] fbdic0_ts2_exp_in; | |
895 | wire [11:0] fbdic0_ts3_exp_in; | |
896 | wire [11:0] fbdic1_ts_exp_data_in; | |
897 | wire [11:0] fbdic1_ts0_exp_in; | |
898 | wire [11:0] fbdic1_ts1_exp_in; | |
899 | wire [11:0] fbdic1_ts2_exp_in; | |
900 | wire [11:0] fbdic1_ts3_exp_in; | |
901 | wire ff_ts_exp_data_scanin; | |
902 | wire ff_ts_exp_data_scanout; | |
903 | wire [11:0] fbdic0_ts_exp_data; | |
904 | wire [11:0] fbdic1_ts_exp_data; | |
905 | wire [5:0] fbdic0_nb_ts_cnt; | |
906 | wire [4:0] fbdic_ch0_cap_reg; | |
907 | wire [3:0] fbdic0_nb_ts2_seq_id; | |
908 | wire [3:0] fbdic0_nb_ts2_seq_id_in; | |
909 | wire fbdic0_nb_ts2_seq_id_en; | |
910 | wire fbdic0_nb_ts2_seq_id_clr; | |
911 | wire ff_nb_ts2_seq_id0_scanin; | |
912 | wire ff_nb_ts2_seq_id0_scanout; | |
913 | wire fbdic0_hdr_match; | |
914 | wire [5:0] fbdic0_nb_ts_cnt_in; | |
915 | wire fbdic0_nb_ts_cnt_en; | |
916 | wire ff_nb_ts_cnt0_scanin; | |
917 | wire ff_nb_ts_cnt0_scanout; | |
918 | wire fbdic0_lane0_match; | |
919 | wire fbdic0_lane1_match; | |
920 | wire fbdic0_lane2_match; | |
921 | wire fbdic0_ts_match_in; | |
922 | wire fbdic0_ts_match; | |
923 | wire ff_ts_match0_scanin; | |
924 | wire ff_ts_match0_scanout; | |
925 | wire [3:0] fbdic0_ts_match_cnt_in; | |
926 | wire ff_ts_match0_cnt_scanin; | |
927 | wire ff_ts_match0_cnt_scanout; | |
928 | wire [5:0] fbdic1_nb_ts_cnt; | |
929 | wire [4:0] fbdic_ch1_cap_reg; | |
930 | wire [3:0] fbdic1_nb_ts2_seq_id; | |
931 | wire [3:0] fbdic1_nb_ts2_seq_id_in; | |
932 | wire fbdic1_nb_ts2_seq_id_en; | |
933 | wire fbdic1_nb_ts2_seq_id_clr; | |
934 | wire ff_nb_ts2_seq_id1_scanin; | |
935 | wire ff_nb_ts2_seq_id1_scanout; | |
936 | wire fbdic1_hdr_match; | |
937 | wire [5:0] fbdic1_nb_ts_cnt_in; | |
938 | wire fbdic1_nb_ts_cnt_en; | |
939 | wire ff_nb_ts_cnt1_scanin; | |
940 | wire ff_nb_ts_cnt1_scanout; | |
941 | wire fbdic1_lane0_match; | |
942 | wire fbdic1_lane1_match; | |
943 | wire fbdic1_lane2_match; | |
944 | wire fbdic1_ts_match_in; | |
945 | wire [0:0] fbdic1_ts_match; | |
946 | wire ff_ts_match1_scanin; | |
947 | wire ff_ts_match1_scanout; | |
948 | wire [3:0] fbdic1_ts_match_cnt_in; | |
949 | wire [3:0] fbdic1_ts_match_cnt; | |
950 | wire ff_ts_match1_cnt_scanin; | |
951 | wire ff_ts_match1_cnt_scanout; | |
952 | wire [15:0] fbdic_chnl_read_lat; | |
953 | wire [7:0] fbdic_rt_lat1; | |
954 | wire [7:0] fbdic_rt_lat0; | |
955 | wire [7:0] fbdic_rt_lat_cntr0_in; | |
956 | wire [7:0] fbdic_rt_lat_cntr0; | |
957 | wire fbdic_rt_lat_cntr0_en; | |
958 | wire fbdic_rt_lat_cntr0_clr; | |
959 | wire ff_rt_lat_cntr0_scanin; | |
960 | wire ff_rt_lat_cntr0_scanout; | |
961 | wire fbdic_rt_lat0_en; | |
962 | wire [7:0] fbdic_rt_lat0_in; | |
963 | wire [7:0] inv_fbdic_rt_lat0_in; | |
964 | wire [7:0] inv_fbdic_rt_lat0; | |
965 | wire ff_rt_lat0_wmr_scanin; | |
966 | wire ff_rt_lat0_wmr_scanout; | |
967 | wire fbdic_rt_lat_cntr1_en; | |
968 | wire [7:0] fbdic_rt_lat_cntr1_in; | |
969 | wire [7:0] fbdic_rt_lat_cntr1; | |
970 | wire fbdic_rt_lat_cntr1_clr; | |
971 | wire ff_rt_lat_cntr1_scanin; | |
972 | wire ff_rt_lat_cntr1_scanout; | |
973 | wire fbdic_rt_lat1_en; | |
974 | wire [7:0] fbdic_rt_lat1_in; | |
975 | wire [7:0] inv_fbdic_rt_lat1_in; | |
976 | wire [7:0] inv_fbdic_rt_lat1; | |
977 | wire ff_rt_lat1_wmr_scanin; | |
978 | wire ff_rt_lat1_wmr_scanout; | |
979 | wire [4:0] fbdic_ch0_cap_reg_in; | |
980 | wire fbdic_ch0_cap_reg_en; | |
981 | wire ff_ch0_cap_reg_scanin; | |
982 | wire ff_ch0_cap_reg_scanout; | |
983 | wire [4:0] fbdic_ch1_cap_reg_in; | |
984 | wire fbdic_ch1_cap_reg_en; | |
985 | wire ff_ch1_cap_reg_scanin; | |
986 | wire ff_ch1_cap_reg_scanout; | |
987 | wire [9:0] fbdic_chnl_cap; | |
988 | wire ff_kp_lnk_up_d1_scanin; | |
989 | wire ff_kp_lnk_up_d1_scanout; | |
990 | wire rdpctl_kp_lnk_up_d1; | |
991 | wire fbdic_link_cnt_eq_3; | |
992 | wire fbdic_link_cnt_eq_4_in; | |
993 | wire ff_sync_frame_req_early_scanin; | |
994 | wire ff_sync_frame_req_early_scanout; | |
995 | wire fbdic_link_cnt_eq_4; | |
996 | wire fbdic_link_cnt_eq_0_in; | |
997 | wire fbdic_link_cnt_eq_0; | |
998 | wire [2:0] fbdic_sync_frame_req_delay_in; | |
999 | wire [2:0] fbdic_sync_frame_req_delay; | |
1000 | wire ff_sync_frame_req_delay_scanin; | |
1001 | wire ff_sync_frame_req_delay_scanout; | |
1002 | wire fbdic_sync_frame_req_d2; | |
1003 | wire fbdic_rd_cmd_a_d1; | |
1004 | wire fbdic_rd_cmd_a_d2; | |
1005 | wire fbdic_rd_cmd_a_d3; | |
1006 | wire ff_rd_cmd_a_d1_scanin; | |
1007 | wire ff_rd_cmd_a_d1_scanout; | |
1008 | wire fbdic_rd_cmd_a; | |
1009 | wire [5:0] fbdic_sync_frm_period; | |
1010 | wire [3:0] fbdic_scr_frame_req_dly_in; | |
1011 | wire [3:0] fbdic_scr_frame_req_dly; | |
1012 | wire fbdic_scr_frame_req_dly_en; | |
1013 | wire fbdic_scr_frame_req; | |
1014 | wire ff_scr_dly_scanin; | |
1015 | wire ff_scr_dly_scanout; | |
1016 | wire fbdic_scr_frame_req_d10; | |
1017 | wire fbdic_issue_pre_all_cmd_in; | |
1018 | wire [3:0] fbdic_pre_all_rank; | |
1019 | wire [3:0] fbdic_last_rank; | |
1020 | wire fbdic_issue_pre_all_cmd; | |
1021 | wire ff_issue_pre_all_cmd_scanin; | |
1022 | wire ff_issue_pre_all_cmd_scanout; | |
1023 | wire [3:0] fbdic_pre_all_rank_in; | |
1024 | wire ff_pre_all_rank_scanin; | |
1025 | wire ff_pre_all_rank_scanout; | |
1026 | wire [23:0] fbdic_act_cmd_a; | |
1027 | wire fbdic_wr_cmd_a; | |
1028 | wire [23:0] fbdic_rd_wr_cmd_a; | |
1029 | wire [23:0] fbdic_sync_cmd_a; | |
1030 | wire [23:0] fbdic_soft_chnl_reset_cmd; | |
1031 | wire [23:0] fbdic_a_cmd_in; | |
1032 | wire [1:0] fbdic_f_in; | |
1033 | wire ff_f_scanin; | |
1034 | wire ff_f_scanout; | |
1035 | wire ff_a_cmd_scanin; | |
1036 | wire ff_a_cmd_scanout; | |
1037 | wire fbdic_special_cmd_in; | |
1038 | wire ff_special_cmd_scanin; | |
1039 | wire ff_special_cmd_scanout; | |
1040 | wire fbdic_trans_id; | |
1041 | wire fbdic1_last_trans_id; | |
1042 | wire fbdic0_last_trans_id; | |
1043 | wire fbdic0_last_trans_id_in; | |
1044 | wire fbdic0_last_trans_id_en; | |
1045 | wire ff_last_trans_id0_scanin; | |
1046 | wire ff_last_trans_id0_scanout; | |
1047 | wire fbdic1_last_trans_id_in; | |
1048 | wire fbdic1_last_trans_id_en; | |
1049 | wire ff_last_trans_id1_scanin; | |
1050 | wire ff_last_trans_id1_scanout; | |
1051 | wire [23:0] fbdic_pre_all_cmd; | |
1052 | wire [23:0] fbdic_ref_cmd_b; | |
1053 | wire [35:0] fbdic_b_cmd; | |
1054 | wire [23:0] fbdic_sre_cmd_c; | |
1055 | wire [23:0] fbdic_pde_cmd_c; | |
1056 | wire [23:0] fbdic_srpdx_cmd_c; | |
1057 | wire [35:0] fbdic_c_cmd; | |
1058 | wire [71:0] fbdic_bc_cmd_in; | |
1059 | wire ff_bc_cmd_scanin; | |
1060 | wire ff_bc_cmd_scanout; | |
1061 | wire fbdic0_lane_align; | |
1062 | wire fbdic1_lane_align; | |
1063 | wire fbdic0_lane_align_in; | |
1064 | wire fbdic0_13_lanes_aligned; | |
1065 | wire fbdic0_lane_align_out; | |
1066 | wire fbdic1_lane_align_in; | |
1067 | wire fbdic1_13_lanes_aligned; | |
1068 | wire fbdic1_lane_align_out; | |
1069 | wire ff_lane_align_wmr_scanin; | |
1070 | wire ff_lane_align_wmr_scanout; | |
1071 | wire [7:0] fbdic_chnl_latency_cntr_in; | |
1072 | wire [7:0] fbdic_chnl_latency_cntr; | |
1073 | wire ff_chnl_latency_cntr_scanin; | |
1074 | wire ff_chnl_latency_cntr_scanout; | |
1075 | wire fbdic_latq_enq; | |
1076 | wire fbdic_latq_deq; | |
1077 | wire [11:0] fbdic_latq_dout; | |
1078 | wire fbdic_latq_empty; | |
1079 | wire fbdic_rddata_vld_d0; | |
1080 | wire ff_rddata_vld_d1_scanin; | |
1081 | wire ff_rddata_vld_d1_scanout; | |
1082 | wire fbdic_rddata_vld_d1; | |
1083 | wire fbdic_rddata_vld_d2; | |
1084 | wire fbdic_rddata_vld_d3; | |
1085 | wire fbdic_latq_deq_d1; | |
1086 | wire [11:8] fbdic_latq_dout_reg; | |
1087 | wire fbdic_latq_deq_d2; | |
1088 | wire fbdic_latq_deq_d3; | |
1089 | wire fbdic_latq_deq_d0; | |
1090 | wire ff_latq_deq_dly_scanin; | |
1091 | wire ff_latq_deq_dly_scanout; | |
1092 | wire fbdic_latq_dout_reg_en; | |
1093 | wire ff_latq_dout_reg_scanin; | |
1094 | wire ff_latq_dout_reg_scanout; | |
1095 | wire fbdic_scr_response_frame; | |
1096 | wire ff_status_frame_d1_scanin; | |
1097 | wire ff_status_frame_d1_scanout; | |
1098 | wire fbdic_status_frame_d1; | |
1099 | wire fbdic_scr_response_frame_d1; | |
1100 | wire fbdic_cnfgreg_rddata_vld_in; | |
1101 | wire [31:0] fbdic_cnfgreg_data_in; | |
1102 | wire fbdic_cnfgreg_data_32_in; | |
1103 | wire ff_cnfgreg_data_scanin; | |
1104 | wire ff_cnfgreg_data_scanout; | |
1105 | wire [32:0] fbdic_cnfgreg_data; | |
1106 | wire [3:0] fbdic_latq_xaction; | |
1107 | wire [7:0] fbd_delay; | |
1108 | wire inv_fbd_delay_0; | |
1109 | wire ff_fbd_delay_scanin; | |
1110 | wire ff_fbd_delay_scanout; | |
1111 | wire [11:0] fbdic_latq_din; | |
1112 | wire latq_scanin; | |
1113 | wire latq_scanout; | |
1114 | wire fbdic_latq_full; | |
1115 | wire [11:0] fbdic0_status_parity; | |
1116 | wire [11:0] fbdic1_status_parity; | |
1117 | wire [11:0] fbdic0_alert_asserted; | |
1118 | wire [11:0] fbdic1_alert_asserted; | |
1119 | wire fbdic_inj_sfp_err; | |
1120 | wire fbdic_alert_asserted_en; | |
1121 | wire fbdic_inj_aa_err; | |
1122 | wire fbdic_alert_frame_en; | |
1123 | wire fbdic_inj_af_err; | |
1124 | wire fbdic_status_parity_error_in; | |
1125 | wire fbdic_status_parity_error; | |
1126 | wire fbdic_status_parity_error_clr; | |
1127 | wire fbdic_alert_asserted_in; | |
1128 | wire fbdic_alert_asserted; | |
1129 | wire fbdic_alert_asserted_clr; | |
1130 | wire fbdic_alert_frame_in; | |
1131 | wire fbdic_alert_frame; | |
1132 | wire fbdic_alert_frame_clr; | |
1133 | wire fbdic_err_unrecov_in; | |
1134 | wire fbdic_err_recov_in; | |
1135 | wire ff_fbd_error_scanin; | |
1136 | wire ff_fbd_error_scanout; | |
1137 | wire fbdic_fbd_error_in; | |
1138 | wire ff_fbd_error_dly_scanin; | |
1139 | wire ff_fbd_error_dly_scanout; | |
1140 | wire fbdic_status_parity_error_en_d1; | |
1141 | wire fbdic_alert_asserted_en_d1; | |
1142 | wire fbdic_fbd_error_save_clr; | |
1143 | wire fbdic_spe_in; | |
1144 | wire fbdic_aa_in; | |
1145 | wire fbdic_af_in; | |
1146 | wire fbdic_scr_in; | |
1147 | wire fbdic_fr_in; | |
1148 | wire ff_fbd_error_save_scanin; | |
1149 | wire ff_fbd_error_save_scanout; | |
1150 | wire fbdic_chnl_alert_clr; | |
1151 | wire ff_chnl_alert_scanin; | |
1152 | wire ff_chnl_alert_scanout; | |
1153 | wire fbdic_train_seq; | |
1154 | wire fbdic_train_seq_l; | |
1155 | wire fbdic_txstart; | |
1156 | wire [1:0] fbdic0_cmd_crc_sel_in; | |
1157 | wire [2:0] fbdic0_data_crc_sel_in; | |
1158 | wire [1:0] fbdic1_cmd_crc_sel_in; | |
1159 | wire [2:0] fbdic1_data_crc_sel_in; | |
1160 | wire ff_crc_sel0_scanin; | |
1161 | wire ff_crc_sel0_scanout; | |
1162 | wire ff_crc_sel1_scanin; | |
1163 | wire ff_crc_sel1_scanout; | |
1164 | wire [23:0] fbdic_sbfibportctl; | |
1165 | wire [31:0] fbdic_sbfibpgctl; | |
1166 | wire [23:0] fbdic_sbfibpattbuf1; | |
1167 | wire [9:0] fbdic_sbfibtxmsk; | |
1168 | wire [9:0] fbdic_sbfibtxshft; | |
1169 | wire [23:0] fbdic_sbfibpattbuf2; | |
1170 | wire [9:0] fbdic_sbfibpatt2en; | |
1171 | wire [30:0] fbdic_sbfibinit; | |
1172 | wire [23:0] fbdic_sbibistmisc; | |
1173 | wire [23:0] fbdic_nbfibportctl; | |
1174 | wire [31:0] fbdic_nbfibpgctl; | |
1175 | wire [23:0] fbdic_nbfibpattbuf1; | |
1176 | wire [13:0] fbdic_nbfibrxmsk; | |
1177 | wire [13:0] fbdic_nbfibrxshft; | |
1178 | wire [13:0] fbdic_nbfibrxlnerr; | |
1179 | wire [23:0] fbdic_nbfibpattbuf2; | |
1180 | wire [13:0] fbdic_nbfibpatt2en; | |
1181 | wire fbdic_scr_qual; | |
1182 | wire fbdic_scr_qual_in; | |
1183 | wire scr_qual_scanin; | |
1184 | wire scr_qual_scanout; | |
1185 | wire fbdic_err_fast_chnl_reset_p2; | |
1186 | wire ff_err_fast_chnl_reset_scanin; | |
1187 | wire ff_err_fast_chnl_reset_scanout; | |
1188 | wire fbdic_err_fast_chnl_reset_p1; | |
1189 | wire ff_err_recov_scanin; | |
1190 | wire ff_err_recov_scanout; | |
1191 | wire ff_err_unrecov_scanin; | |
1192 | wire ff_err_unrecov_scanout; | |
1193 | wire [0:0] inv_fbdic_err_state_in; | |
1194 | wire [0:0] inv_fbdic_err_state; | |
1195 | wire ff_err_state_scanin; | |
1196 | wire ff_err_state_scanout; | |
1197 | wire fbdic_sbfibportctl_en; | |
1198 | wire [5:0] fbdic_sbfibportctl_in; | |
1199 | wire pff_sbfibportctl_wmr_scanin; | |
1200 | wire pff_sbfibportctl_wmr_scanout; | |
1201 | wire fbdic_ibtx_done_flag_in; | |
1202 | wire fbdic_ibtx_done_flag; | |
1203 | wire pff_ibtx_done_flag_wmr_scanin; | |
1204 | wire pff_ibtx_done_flag_wmr_scanout; | |
1205 | wire fbdic_ibtx_start_en; | |
1206 | wire pff_ibtx_start_wmr_scanin; | |
1207 | wire pff_ibtx_start_wmr_scanout; | |
1208 | wire [31:0] fbdic_sbfibpgctl_reset_val; | |
1209 | wire fbdic_sbfibpgctl_en; | |
1210 | wire [31:0] fbdic_sbfibpgctl_in; | |
1211 | wire [31:0] fbdic_sbfibpgctl_out; | |
1212 | wire pff_sbfibpgctl_wmr_scanin; | |
1213 | wire pff_sbfibpgctl_wmr_scanout; | |
1214 | wire [23:0] fbdic_sbfibpattbuf1_reset_val; | |
1215 | wire fbdic_sbfibpattbuf1_en; | |
1216 | wire [23:0] fbdic_sbfibpattbuf1_in; | |
1217 | wire [23:0] fbdic_sbfibpattbuf1_out; | |
1218 | wire pff_sbfibpattbuf1_wmr_scanin; | |
1219 | wire pff_sbfibpattbuf1_wmr_scanout; | |
1220 | wire [9:0] fbdic_sbfibtxmsk_reset_val; | |
1221 | wire fbdic_sbfibtxmsk_en; | |
1222 | wire [9:0] fbdic_sbfibtxmsk_in; | |
1223 | wire [9:0] fbdic_sbfibtxmsk_out; | |
1224 | wire pff_sbfibtxmsk_wmr_scanin; | |
1225 | wire pff_sbfibtxmsk_wmr_scanout; | |
1226 | wire [9:0] fbdic_sbfibtxshft_reset_val; | |
1227 | wire fbdic_sbfibtxshft_en; | |
1228 | wire [9:0] fbdic_sbfibtxshft_in; | |
1229 | wire [9:0] fbdic_sbfibtxshft_out; | |
1230 | wire pff_sbfibtxshft_wmr_scanin; | |
1231 | wire pff_sbfibtxshft_wmr_scanout; | |
1232 | wire [23:0] fbdic_sbfibpattbuf2_reset_val; | |
1233 | wire fbdic_sbfibpattbuf2_en; | |
1234 | wire [23:0] fbdic_sbfibpattbuf2_in; | |
1235 | wire [23:0] fbdic_sbfibpattbuf2_out; | |
1236 | wire pff_sbfibpattbuf2_wmr_scanin; | |
1237 | wire pff_sbfibpattbuf2_wmr_scanout; | |
1238 | wire fbdic_sbfibpatt2en_en; | |
1239 | wire [9:0] fbdic_sbfibpatt2en_in; | |
1240 | wire pff_sbfibpatt2en_wmr_scanin; | |
1241 | wire pff_sbfibpatt2en_wmr_scanout; | |
1242 | wire [30:0] fbdic_sbfibinit_reset_val; | |
1243 | wire fbdic_sbfibinit_en; | |
1244 | wire [30:0] fbdic_sbfibinit_in; | |
1245 | wire [30:0] fbdic_sbfibinit_out; | |
1246 | wire pff_sbfibinit_wmr_scanin; | |
1247 | wire pff_sbfibinit_wmr_scanout; | |
1248 | wire [9:0] fbdic_sbts0cnt; | |
1249 | wire [9:0] fbdic_sbts1cnt; | |
1250 | wire fbdic_sbibistiniten; | |
1251 | wire fbdic_sbts_cnt_decr; | |
1252 | wire [9:0] fbdic_sbts_cnt_in; | |
1253 | wire ff_sbts_cnt_scanin; | |
1254 | wire ff_sbts_cnt_scanout; | |
1255 | wire [23:0] fbdic_sbibistmisc_reset_val; | |
1256 | wire fbdic_sbibistmisc_en; | |
1257 | wire [23:0] fbdic_sbibistmisc_in; | |
1258 | wire [23:0] fbdic_sbibistmisc_out; | |
1259 | wire pff_sbibistmisc_wmr_scanin; | |
1260 | wire pff_sbibistmisc_wmr_scanout; | |
1261 | wire [3:0] fbdic_ibist_ambid; | |
1262 | wire fbdic_nbfibportctl_en; | |
1263 | wire [5:0] fbdic_nbfibportctl_in; | |
1264 | wire pff_nbfibportctl_wmr_scanin; | |
1265 | wire pff_nbfibportctl_wmr_scanout; | |
1266 | wire [9:0] ibrx_errcnt; | |
1267 | wire [3:0] ibrx_errlnnum; | |
1268 | wire [1:0] ibrx_errstat; | |
1269 | wire fbdic_ibrx_done_flag_in; | |
1270 | wire ibrx_done; | |
1271 | wire fbdic_ibrx_start_ld; | |
1272 | wire fbdic_ibrx_done_flag; | |
1273 | wire pff_ibrx_done_flag_scanin; | |
1274 | wire pff_ibrx_done_flag_scanout; | |
1275 | wire fbdic_ibrx_start_en; | |
1276 | wire pff_ibrx_start_wmr_scanin; | |
1277 | wire pff_ibrx_start_wmr_scanout; | |
1278 | wire fbdic_ibrx_start; | |
1279 | wire [31:0] fbdic_nbfibpgctl_reset_val; | |
1280 | wire fbdic_nbfibpgctl_en; | |
1281 | wire [31:0] fbdic_nbfibpgctl_in; | |
1282 | wire [31:0] fbdic_nbfibpgctl_out; | |
1283 | wire pff_nbfibpgctl_wmr_scanin; | |
1284 | wire pff_nbfibpgctl_wmr_scanout; | |
1285 | wire [23:0] fbdic_nbfibpattbuf1_reset_val; | |
1286 | wire fbdic_nbfibpattbuf1_en; | |
1287 | wire [23:0] fbdic_nbfibpattbuf1_in; | |
1288 | wire [23:0] fbdic_nbfibpattbuf1_out; | |
1289 | wire pff_nbfibpattbuf1_wmr_scanin; | |
1290 | wire pff_nbfibpattbuf1_wmr_scanout; | |
1291 | wire [13:0] fbdic_nbfibrxmsk_reset_val; | |
1292 | wire fbdic_nbfibrxmsk_en; | |
1293 | wire [13:0] fbdic_nbfibrxmsk_in; | |
1294 | wire [13:0] fbdic_nbfibrxmsk_out; | |
1295 | wire pff_nbfibrxmsk_wmr_scanin; | |
1296 | wire pff_nbfibrxmsk_wmr_scanout; | |
1297 | wire [13:0] fbdic_nbfibrxshft_reset_val; | |
1298 | wire fbdic_nbfibrxshft_en; | |
1299 | wire [13:0] fbdic_nbfibrxshft_in; | |
1300 | wire [13:0] fbdic_nbfibrxshft_out; | |
1301 | wire pff_nbfibrxshft_wmr_scanin; | |
1302 | wire pff_nbfibrxshft_wmr_scanout; | |
1303 | wire [13:0] ibrx_rxerrstat; | |
1304 | wire [23:0] fbdic_nbfibpattbuf2_reset_val; | |
1305 | wire fbdic_nbfibpattbuf2_en; | |
1306 | wire [23:0] fbdic_nbfibpattbuf2_in; | |
1307 | wire [23:0] fbdic_nbfibpattbuf2_out; | |
1308 | wire pff_nbfibpattbuf2_wmr_scanin; | |
1309 | wire pff_nbfibpattbuf2_wmr_scanout; | |
1310 | wire fbdic_nbfibpatt2en_en; | |
1311 | wire [13:0] fbdic_nbfibpatt2en_in; | |
1312 | wire pff_nbfibpatt2en_wmr_scanin; | |
1313 | wire pff_nbfibpatt2en_wmr_scanout; | |
1314 | wire fbdic_ibist_data_mode_in; | |
1315 | wire ff_ibist_data_scanin; | |
1316 | wire ff_ibist_data_scanout; | |
1317 | wire fbdic_ibist_done_in; | |
1318 | wire ff_ibist_done_scanin; | |
1319 | wire ff_ibist_done_scanout; | |
1320 | wire [39:0] fbdic_ibrx_data; | |
1321 | wire fbdic_ibrx_lane0_s0_match; | |
1322 | wire fbdic_ibrx_lane1_s0_match; | |
1323 | wire fbdic_ibrx_lane2_s0_match; | |
1324 | wire fbdic_ibrx_lane0_s1_match; | |
1325 | wire fbdic_ibrx_lane1_s1_match; | |
1326 | wire fbdic_ibrx_lane2_s1_match; | |
1327 | wire fbdic_ibrx_s0_match; | |
1328 | wire fbdic_ibrx_s1_match; | |
1329 | wire fbdic_s0_s1_s0_s1; | |
1330 | wire fbdic_s0_s1_s0_d1; | |
1331 | wire fbdic_s0_s1_s0; | |
1332 | wire fbdic_s0_s1_d1; | |
1333 | wire fbdic_s0_s1; | |
1334 | wire fbdic_s0_d1; | |
1335 | wire ff_rx_s0s1_match_dly_scanin; | |
1336 | wire ff_rx_s0s1_match_dly_scanout; | |
1337 | wire fbdic_rxstart; | |
1338 | wire ibist_scanin; | |
1339 | wire ibist_scanout; | |
1340 | wire ff_err_fbxi_scanin; | |
1341 | wire ff_err_fbxi_scanout; | |
1342 | wire fbdic_err_fbri; | |
1343 | wire fbdic_err_fbui; | |
1344 | wire fbdic_fbr_injected_in; | |
1345 | wire fbdic_fbr_injected; | |
1346 | wire ff_fbr_injected_scanin; | |
1347 | wire ff_fbr_injected_scanout; | |
1348 | wire ff_serdes_dtm_scanin; | |
1349 | wire ff_serdes_dtm_scanout; | |
1350 | wire fbdic_serdes_dtm_out; | |
1351 | wire [2:0] fbdic_dtm_zero_cnt_in; | |
1352 | wire fbdic_dtm_state; | |
1353 | wire [2:0] fbdic_dtm_zero_cnt; | |
1354 | wire ff_dtm_zero_cnt_scanin; | |
1355 | wire ff_dtm_zero_cnt_scanout; | |
1356 | wire fbdic_dtm_state_in; | |
1357 | wire ff_dtm_state_scanin; | |
1358 | wire ff_dtm_state_scanout; | |
1359 | wire fbdic_srds_dtm_muxsel_in; | |
1360 | wire ff_srds_dtm_muxsel_scanin; | |
1361 | wire ff_srds_dtm_muxsel_scanout; | |
1362 | wire si_0; | |
1363 | wire so_0; | |
1364 | wire spare0_flop_unused; | |
1365 | wire spares_scanin; | |
1366 | wire spare0_buf_32x_unused; | |
1367 | wire spare0_nand3_8x_unused; | |
1368 | wire spare0_inv_8x_unused; | |
1369 | wire spare0_aoi22_4x_unused; | |
1370 | wire spare0_buf_8x_unused; | |
1371 | wire spare0_oai22_4x_unused; | |
1372 | wire spare0_inv_16x_unused; | |
1373 | wire spare0_nand2_16x_unused; | |
1374 | wire spare0_nor3_4x_unused; | |
1375 | wire spare0_nand2_8x_unused; | |
1376 | wire spare0_buf_16x_unused; | |
1377 | wire spare0_nor2_16x_unused; | |
1378 | wire spare0_inv_32x_unused; | |
1379 | wire si_1; | |
1380 | wire so_1; | |
1381 | wire spare1_flop_unused; | |
1382 | wire spare1_buf_32x_unused; | |
1383 | wire spare1_nand3_8x_unused; | |
1384 | wire spare1_inv_8x_unused; | |
1385 | wire spare1_aoi22_4x_unused; | |
1386 | wire spare1_buf_8x_unused; | |
1387 | wire spare1_oai22_4x_unused; | |
1388 | wire spare1_inv_16x_unused; | |
1389 | wire spare1_nand2_16x_unused; | |
1390 | wire spare1_nor3_4x_unused; | |
1391 | wire spare1_nand2_8x_unused; | |
1392 | wire spare1_buf_16x_unused; | |
1393 | wire spare1_nor2_16x_unused; | |
1394 | wire spare1_inv_32x_unused; | |
1395 | wire si_2; | |
1396 | wire so_2; | |
1397 | wire spare2_flop_unused; | |
1398 | wire spare2_buf_32x_unused; | |
1399 | wire spare2_nand3_8x_unused; | |
1400 | wire spare2_inv_8x_unused; | |
1401 | wire spare2_aoi22_4x_unused; | |
1402 | wire spare2_buf_8x_unused; | |
1403 | wire spare2_oai22_4x_unused; | |
1404 | wire spare2_inv_16x_unused; | |
1405 | wire spare2_nand2_16x_unused; | |
1406 | wire spare2_nor3_4x_unused; | |
1407 | wire spare2_nand2_8x_unused; | |
1408 | wire spare2_buf_16x_unused; | |
1409 | wire spare2_nor2_16x_unused; | |
1410 | wire spare2_inv_32x_unused; | |
1411 | wire si_3; | |
1412 | wire so_3; | |
1413 | wire spare3_flop_unused; | |
1414 | wire spare3_buf_32x_unused; | |
1415 | wire spare3_nand3_8x_unused; | |
1416 | wire spare3_inv_8x_unused; | |
1417 | wire spare3_aoi22_4x_unused; | |
1418 | wire spare3_buf_8x_unused; | |
1419 | wire spare3_oai22_4x_unused; | |
1420 | wire spare3_inv_16x_unused; | |
1421 | wire spare3_nand2_16x_unused; | |
1422 | wire spare3_nor3_4x_unused; | |
1423 | wire spare3_nand2_8x_unused; | |
1424 | wire spare3_buf_16x_unused; | |
1425 | wire spare3_nor2_16x_unused; | |
1426 | wire spare3_inv_32x_unused; | |
1427 | wire si_4; | |
1428 | wire so_4; | |
1429 | wire spare4_flop_unused; | |
1430 | wire spare4_buf_32x_unused; | |
1431 | wire spare4_nand3_8x_unused; | |
1432 | wire spare4_inv_8x_unused; | |
1433 | wire spare4_aoi22_4x_unused; | |
1434 | wire spare4_buf_8x_unused; | |
1435 | wire spare4_oai22_4x_unused; | |
1436 | wire spare4_inv_16x_unused; | |
1437 | wire spare4_nand2_16x_unused; | |
1438 | wire spare4_nor3_4x_unused; | |
1439 | wire spare4_nand2_8x_unused; | |
1440 | wire spare4_buf_16x_unused; | |
1441 | wire spare4_nor2_16x_unused; | |
1442 | wire spare4_inv_32x_unused; | |
1443 | wire si_5; | |
1444 | wire so_5; | |
1445 | wire spare5_flop_unused; | |
1446 | wire spare5_buf_32x_unused; | |
1447 | wire spare5_nand3_8x_unused; | |
1448 | wire spare5_inv_8x_unused; | |
1449 | wire spare5_aoi22_4x_unused; | |
1450 | wire spare5_buf_8x_unused; | |
1451 | wire spare5_oai22_4x_unused; | |
1452 | wire spare5_inv_16x_unused; | |
1453 | wire spare5_nand2_16x_unused; | |
1454 | wire spare5_nor3_4x_unused; | |
1455 | wire spare5_nand2_8x_unused; | |
1456 | wire spare5_buf_16x_unused; | |
1457 | wire spare5_nor2_16x_unused; | |
1458 | wire spare5_inv_32x_unused; | |
1459 | wire si_6; | |
1460 | wire so_6; | |
1461 | wire spare6_flop_unused; | |
1462 | wire spare6_buf_32x_unused; | |
1463 | wire spare6_nand3_8x_unused; | |
1464 | wire spare6_inv_8x_unused; | |
1465 | wire spare6_aoi22_4x_unused; | |
1466 | wire spare6_buf_8x_unused; | |
1467 | wire spare6_oai22_4x_unused; | |
1468 | wire spare6_inv_16x_unused; | |
1469 | wire spare6_nand2_16x_unused; | |
1470 | wire spare6_nor3_4x_unused; | |
1471 | wire spare6_nand2_8x_unused; | |
1472 | wire spare6_buf_16x_unused; | |
1473 | wire spare6_nor2_16x_unused; | |
1474 | wire spare6_inv_32x_unused; | |
1475 | wire si_7; | |
1476 | wire so_7; | |
1477 | wire spare7_flop_unused; | |
1478 | wire spare7_buf_32x_unused; | |
1479 | wire spare7_nand3_8x_unused; | |
1480 | wire spare7_inv_8x_unused; | |
1481 | wire spare7_aoi22_4x_unused; | |
1482 | wire spare7_buf_8x_unused; | |
1483 | wire spare7_oai22_4x_unused; | |
1484 | wire spare7_inv_16x_unused; | |
1485 | wire spare7_nand2_16x_unused; | |
1486 | wire spare7_nor3_4x_unused; | |
1487 | wire spare7_nand2_8x_unused; | |
1488 | wire spare7_buf_16x_unused; | |
1489 | wire spare7_nor2_16x_unused; | |
1490 | wire spare7_inv_32x_unused; | |
1491 | wire si_8; | |
1492 | wire so_8; | |
1493 | wire spare8_buf_32x_unused; | |
1494 | wire spare8_nand3_8x_unused; | |
1495 | wire spare8_inv_8x_unused; | |
1496 | wire spare8_aoi22_4x_unused; | |
1497 | wire spare8_buf_8x_unused; | |
1498 | wire spare8_oai22_4x_unused; | |
1499 | wire spare8_inv_16x_unused; | |
1500 | wire spare8_nand2_16x_unused; | |
1501 | wire spare8_nor3_4x_unused; | |
1502 | wire spare8_nand2_8x_unused; | |
1503 | wire spare8_buf_16x_unused; | |
1504 | wire spare8_nor2_16x_unused; | |
1505 | wire spare8_inv_32x_unused; | |
1506 | wire si_9; | |
1507 | wire so_9; | |
1508 | wire spare9_flop_unused; | |
1509 | wire spare9_buf_32x_unused; | |
1510 | wire spare9_nand3_8x_unused; | |
1511 | wire spare9_inv_8x_unused; | |
1512 | wire spare9_aoi22_4x_unused; | |
1513 | wire spare9_buf_8x_unused; | |
1514 | wire spare9_oai22_4x_unused; | |
1515 | wire spare9_inv_16x_unused; | |
1516 | wire spare9_nand2_16x_unused; | |
1517 | wire spare9_nor3_4x_unused; | |
1518 | wire spare9_nand2_8x_unused; | |
1519 | wire spare9_buf_16x_unused; | |
1520 | wire spare9_nor2_16x_unused; | |
1521 | wire spare9_inv_32x_unused; | |
1522 | wire si_10; | |
1523 | wire so_10; | |
1524 | wire spare10_buf_32x_unused; | |
1525 | wire spare10_nand3_8x_unused; | |
1526 | wire spare10_inv_8x_unused; | |
1527 | wire spare10_aoi22_4x_unused; | |
1528 | wire spare10_buf_8x_unused; | |
1529 | wire spare10_oai22_4x_unused; | |
1530 | wire spare10_inv_16x_unused; | |
1531 | wire spare10_nand2_16x_unused; | |
1532 | wire spare10_nor3_4x_unused; | |
1533 | wire spare10_nand2_8x_unused; | |
1534 | wire spare10_buf_16x_unused; | |
1535 | wire spare10_nor2_16x_unused; | |
1536 | wire spare10_inv_32x_unused; | |
1537 | wire si_11; | |
1538 | wire so_11; | |
1539 | wire spare11_flop_unused; | |
1540 | wire spare11_buf_32x_unused; | |
1541 | wire spare11_nand3_8x_unused; | |
1542 | wire spare11_inv_8x_unused; | |
1543 | wire spare11_aoi22_4x_unused; | |
1544 | wire spare11_buf_8x_unused; | |
1545 | wire spare11_oai22_4x_unused; | |
1546 | wire spare11_inv_16x_unused; | |
1547 | wire spare11_nand2_16x_unused; | |
1548 | wire spare11_nor3_4x_unused; | |
1549 | wire spare11_nand2_8x_unused; | |
1550 | wire spare11_buf_16x_unused; | |
1551 | wire spare11_nor2_16x_unused; | |
1552 | wire spare11_inv_32x_unused; | |
1553 | wire si_12; | |
1554 | wire so_12; | |
1555 | wire spare12_flop_unused; | |
1556 | wire spare12_buf_32x_unused; | |
1557 | wire spare12_nand3_8x_unused; | |
1558 | wire spare12_inv_8x_unused; | |
1559 | wire spare12_aoi22_4x_unused; | |
1560 | wire spare12_buf_8x_unused; | |
1561 | wire spare12_oai22_4x_unused; | |
1562 | wire spare12_inv_16x_unused; | |
1563 | wire spare12_nand2_16x_unused; | |
1564 | wire spare12_nor3_4x_unused; | |
1565 | wire spare12_nand2_8x_unused; | |
1566 | wire spare12_buf_16x_unused; | |
1567 | wire spare12_nor2_16x_unused; | |
1568 | wire spare12_inv_32x_unused; | |
1569 | wire si_13; | |
1570 | wire so_13; | |
1571 | wire spare13_flop_unused; | |
1572 | wire spare13_buf_32x_unused; | |
1573 | wire spare13_nand3_8x_unused; | |
1574 | wire spare13_inv_8x_unused; | |
1575 | wire spare13_aoi22_4x_unused; | |
1576 | wire spare13_buf_8x_unused; | |
1577 | wire spare13_oai22_4x_unused; | |
1578 | wire spare13_inv_16x_unused; | |
1579 | wire spare13_nand2_16x_unused; | |
1580 | wire spare13_nor3_4x_unused; | |
1581 | wire spare13_nand2_8x_unused; | |
1582 | wire spare13_buf_16x_unused; | |
1583 | wire spare13_nor2_16x_unused; | |
1584 | wire spare13_inv_32x_unused; | |
1585 | wire si_14; | |
1586 | wire so_14; | |
1587 | wire spare14_flop_unused; | |
1588 | wire spare14_buf_32x_unused; | |
1589 | wire spare14_nand3_8x_unused; | |
1590 | wire spare14_inv_8x_unused; | |
1591 | wire spare14_aoi22_4x_unused; | |
1592 | wire spare14_buf_8x_unused; | |
1593 | wire spare14_oai22_4x_unused; | |
1594 | wire spare14_inv_16x_unused; | |
1595 | wire spare14_nand2_16x_unused; | |
1596 | wire spare14_nor3_4x_unused; | |
1597 | wire spare14_nand2_8x_unused; | |
1598 | wire spare14_buf_16x_unused; | |
1599 | wire spare14_nor2_16x_unused; | |
1600 | wire spare14_inv_32x_unused; | |
1601 | wire si_15; | |
1602 | wire so_15; | |
1603 | wire spare15_flop_unused; | |
1604 | wire spare15_buf_32x_unused; | |
1605 | wire spare15_nand3_8x_unused; | |
1606 | wire spare15_inv_8x_unused; | |
1607 | wire spare15_aoi22_4x_unused; | |
1608 | wire spare15_buf_8x_unused; | |
1609 | wire spare15_oai22_4x_unused; | |
1610 | wire spare15_inv_16x_unused; | |
1611 | wire spare15_nand2_16x_unused; | |
1612 | wire spare15_nor3_4x_unused; | |
1613 | wire spare15_nand2_8x_unused; | |
1614 | wire spare15_buf_16x_unused; | |
1615 | wire spare15_nor2_16x_unused; | |
1616 | wire spare15_inv_32x_unused; | |
1617 | wire si_16; | |
1618 | wire so_16; | |
1619 | wire spare16_flop_unused; | |
1620 | wire spare16_buf_32x_unused; | |
1621 | wire spare16_nand3_8x_unused; | |
1622 | wire spare16_inv_8x_unused; | |
1623 | wire spare16_aoi22_4x_unused; | |
1624 | wire spare16_buf_8x_unused; | |
1625 | wire spare16_oai22_4x_unused; | |
1626 | wire spare16_inv_16x_unused; | |
1627 | wire spare16_nand2_16x_unused; | |
1628 | wire spare16_nor3_4x_unused; | |
1629 | wire spare16_nand2_8x_unused; | |
1630 | wire spare16_buf_16x_unused; | |
1631 | wire spare16_nor2_16x_unused; | |
1632 | wire spare16_inv_32x_unused; | |
1633 | wire si_17; | |
1634 | wire so_17; | |
1635 | wire spare17_flop_unused; | |
1636 | wire spare17_buf_32x_unused; | |
1637 | wire spare17_nand3_8x_unused; | |
1638 | wire spare17_inv_8x_unused; | |
1639 | wire spare17_aoi22_4x_unused; | |
1640 | wire spare17_buf_8x_unused; | |
1641 | wire spare17_oai22_4x_unused; | |
1642 | wire spare17_inv_16x_unused; | |
1643 | wire spare17_nand2_16x_unused; | |
1644 | wire spare17_nor3_4x_unused; | |
1645 | wire spare17_nand2_8x_unused; | |
1646 | wire spare17_buf_16x_unused; | |
1647 | wire spare17_nor2_16x_unused; | |
1648 | wire spare17_inv_32x_unused; | |
1649 | wire si_18; | |
1650 | wire so_18; | |
1651 | wire spare18_buf_32x_unused; | |
1652 | wire spare18_nand3_8x_unused; | |
1653 | wire spare18_inv_8x_unused; | |
1654 | wire spare18_aoi22_4x_unused; | |
1655 | wire spare18_buf_8x_unused; | |
1656 | wire spare18_oai22_4x_unused; | |
1657 | wire spare18_inv_16x_unused; | |
1658 | wire spare18_nand2_16x_unused; | |
1659 | wire spare18_nor3_4x_unused; | |
1660 | wire spare18_nand2_8x_unused; | |
1661 | wire spare18_buf_16x_unused; | |
1662 | wire spare18_nor2_16x_unused; | |
1663 | wire spare18_inv_32x_unused; | |
1664 | wire si_19; | |
1665 | wire so_19; | |
1666 | wire spare19_flop_unused; | |
1667 | wire spare19_buf_32x_unused; | |
1668 | wire spare19_nand3_8x_unused; | |
1669 | wire spare19_inv_8x_unused; | |
1670 | wire spare19_aoi22_4x_unused; | |
1671 | wire spare19_buf_8x_unused; | |
1672 | wire spare19_oai22_4x_unused; | |
1673 | wire spare19_inv_16x_unused; | |
1674 | wire spare19_nand2_16x_unused; | |
1675 | wire spare19_nor3_4x_unused; | |
1676 | wire spare19_nand2_8x_unused; | |
1677 | wire spare19_buf_16x_unused; | |
1678 | wire spare19_nor2_16x_unused; | |
1679 | wire spare19_inv_32x_unused; | |
1680 | wire si_20; | |
1681 | wire so_20; | |
1682 | wire spare20_buf_32x_unused; | |
1683 | wire spare20_nand3_8x_unused; | |
1684 | wire spare20_inv_8x_unused; | |
1685 | wire spare20_aoi22_4x_unused; | |
1686 | wire spare20_buf_8x_unused; | |
1687 | wire spare20_oai22_4x_unused; | |
1688 | wire spare20_inv_16x_unused; | |
1689 | wire spare20_nand2_16x_unused; | |
1690 | wire spare20_nor3_4x_unused; | |
1691 | wire spare20_nand2_8x_unused; | |
1692 | wire spare20_buf_16x_unused; | |
1693 | wire spare20_nor2_16x_unused; | |
1694 | wire spare20_inv_32x_unused; | |
1695 | wire si_21; | |
1696 | wire so_21; | |
1697 | wire spare21_flop_unused; | |
1698 | wire spare21_buf_32x_unused; | |
1699 | wire spare21_nand3_8x_unused; | |
1700 | wire spare21_inv_8x_unused; | |
1701 | wire spare21_aoi22_4x_unused; | |
1702 | wire spare21_buf_8x_unused; | |
1703 | wire spare21_oai22_4x_unused; | |
1704 | wire spare21_inv_16x_unused; | |
1705 | wire spare21_nand2_16x_unused; | |
1706 | wire spare21_nor3_4x_unused; | |
1707 | wire spare21_nand2_8x_unused; | |
1708 | wire spare21_buf_16x_unused; | |
1709 | wire spare21_nor2_16x_unused; | |
1710 | wire spare21_inv_32x_unused; | |
1711 | wire spares_scanout; | |
1712 | wire fbdtm_wmr_scanin; | |
1713 | wire fbdtm_wmr_scanout; | |
1714 | wire fbdtm_scanin; | |
1715 | wire fbdtm_scanout; | |
1716 | wire wmr_scan_out; | |
1717 | ||
1718 | ||
1719 | output [4:0] fbdic_data_sel; | |
1720 | output [11:0] fbdic0_ts_data; | |
1721 | output [11:0] fbdic1_ts_data; | |
1722 | output [119:0] fbdic_ibist_data; | |
1723 | output [1:0] fbdic_f; | |
1724 | output fbdic_f_1_l; | |
1725 | output fbdic0_chnl_disable; | |
1726 | output fbdic1_chnl_disable; | |
1727 | output [23:0] fbdic_a_cmd; | |
1728 | output [71:0] fbdic_bc_cmd; | |
1729 | output [1:0] fbdic0_cmd_crc_sel; | |
1730 | output [2:0] fbdic0_data_crc_sel; | |
1731 | output fbdic0_sb_failover; | |
1732 | output fbdic0_sb_failover_l; | |
1733 | output [8:0] fbdic0_sb_failover_mask; | |
1734 | output [8:0] fbdic0_sb_failover_mask_l; | |
1735 | output fbdic0_nb_failover; | |
1736 | output fbdic0_nb_failover_l; | |
1737 | output [12:0] fbdic0_nb_failover_mask; | |
1738 | output [12:0] fbdic0_nb_failover_mask_l; | |
1739 | output [1:0] fbdic1_cmd_crc_sel; | |
1740 | output [2:0] fbdic1_data_crc_sel; | |
1741 | output fbdic1_sb_failover; | |
1742 | output fbdic1_sb_failover_l; | |
1743 | output [8:0] fbdic1_sb_failover_mask; | |
1744 | output [8:0] fbdic1_sb_failover_mask_l; | |
1745 | output fbdic1_nb_failover; | |
1746 | output fbdic1_nb_failover_l; | |
1747 | output [12:0] fbdic1_nb_failover_mask; | |
1748 | output [12:0] fbdic1_nb_failover_mask_l; | |
1749 | ||
1750 | output [65:0] fbdic_ucb_rd_data; | |
1751 | output fbdic_train_state; | |
1752 | output fbdic_disable_state; | |
1753 | output fbdic_enable_sync_count; | |
1754 | ||
1755 | output fbdic_sync_frame_req_early3; | |
1756 | output fbdic_sync_frame_req_early2; | |
1757 | output fbdic_sync_frame_req_early1; | |
1758 | output fbdic_sync_frame_req; | |
1759 | output fbdic_sync_frame_req_d1; | |
1760 | output fbdic_scr_frame_req_d4; | |
1761 | output fbdic_l0_state; | |
1762 | output fbdic_l0s_lfsr_stall; | |
1763 | output fbdic_err_fast_reset_done; | |
1764 | output fbdic_chnl_reset_error; | |
1765 | output fbdic_chnl_reset_error_mode; | |
1766 | ||
1767 | output fbdic_special_cmd; | |
1768 | output fbdic_special_cmd_l; | |
1769 | output fbdic_ibrx_data_sel; | |
1770 | output fbdic_ibrx_data_sel_l; | |
1771 | ||
1772 | output fbdic_rddata_vld; | |
1773 | output fbdic_rddata_vld_l; | |
1774 | output [1:0] fbdic_woq_free; | |
1775 | output fbdic_clear_wrq_ent; | |
1776 | output fbdic_error_mode; // error mode signal to drif to stall transaction issue | |
1777 | output fbdic_fbd_error; // Error mode signal for Debug bus | |
1778 | output fbdic_crc_error; // CRC error to rdpctl/drif to retry transaction | |
1779 | output fbdic_err_unrecov; // Unrecoverable error signal for MCU error status reg | |
1780 | output fbdic_err_recov; // Recoverable error signal for MCU error status reg | |
1781 | ||
1782 | output fbdic_err_fbr; // FBR count interrupt | |
1783 | ||
1784 | output fbdic0_inc_wptr; | |
1785 | output [13:0] fbdic0_inc_rptr; | |
1786 | output fbdic0_clr_ptrs; | |
1787 | output fbdic1_inc_wptr; | |
1788 | output [13:0] fbdic1_inc_rptr; | |
1789 | output fbdic1_clr_ptrs; | |
1790 | ||
1791 | output fbdic_idle_lfsr_reset; | |
1792 | ||
1793 | output mcu_fsr0_cfgpll_enpll; | |
1794 | output mcu_fsr1_cfgpll_enpll; | |
1795 | output [1:0] mcu_fsr01_cfgpll_lb; | |
1796 | output [3:0] mcu_fsr01_cfgpll_mpy; | |
1797 | output mcu_fsr0_cfgrx_enrx; | |
1798 | output mcu_fsr1_cfgrx_enrx; | |
1799 | output mcu_fsr0_cfgrx_entest; | |
1800 | output mcu_fsr1_cfgrx_entest; | |
1801 | output mcu_fsr0_cfgrx_align; | |
1802 | output mcu_fsr1_cfgrx_align; | |
1803 | output [13:0] mcu_fsr0_cfgrx_invpair; | |
1804 | output [13:0] mcu_fsr1_cfgrx_invpair; | |
1805 | output [3:0] mcu_fsr01_cfgrx_eq; | |
1806 | output [2:0] mcu_fsr01_cfgrx_cdr; | |
1807 | output [2:0] mcu_fsr01_cfgrx_term; | |
1808 | output mcu_fsr0_cfgtx_entx; | |
1809 | output mcu_fsr1_cfgtx_entx; | |
1810 | output mcu_fsr0_cfgtx_entest; | |
1811 | output mcu_fsr1_cfgtx_entest; | |
1812 | output mcu_fsr0_cfgtx_enidl; | |
1813 | output mcu_fsr1_cfgtx_enidl; | |
1814 | output [9:0] mcu_fsr0_cfgtx_invpair; | |
1815 | output [9:0] mcu_fsr1_cfgtx_invpair; | |
1816 | output mcu_fsr01_cfgtx_enftp; | |
1817 | output [3:0] mcu_fsr01_cfgtx_de; | |
1818 | output [2:0] mcu_fsr01_cfgtx_swing; | |
1819 | output mcu_fsr01_cfgtx_cm; | |
1820 | output [1:0] mcu_fsr01_cfgrtx_rate; | |
1821 | output [11:0] mcu_fsr0_testcfg; | |
1822 | output [11:0] mcu_fsr1_testcfg; | |
1823 | ||
1824 | output fbdic_link_cnt_en; | |
1825 | output [5:0] fbdic_link_cnt_reset; | |
1826 | output rdpctl_kp_lnk_up; | |
1827 | output rdpctl_kp_lnk_up_clr; | |
1828 | ||
1829 | output fbdic_serdes_dtm; | |
1830 | output fbdic_srds_dtm_muxsel; | |
1831 | ||
1832 | output fbdic_cfgrd_crc_error; | |
1833 | ||
1834 | output fbdic_mcu_idle; | |
1835 | ||
1836 | input [13:0] fbd0_elect_idle; | |
1837 | input [13:0] fbd1_elect_idle; | |
1838 | input [13:0] fbd0_frame_lock; | |
1839 | input [13:0] fbd1_frame_lock; | |
1840 | input [13:0] fbd0_testfail; | |
1841 | input [13:0] fbd1_testfail; | |
1842 | ||
1843 | input drif_ucb_wr_req_vld; | |
1844 | input drif_ucb_rd_req_vld; | |
1845 | input [12:0] drif_ucb_addr; | |
1846 | input [63:0] drif_ucb_data; | |
1847 | ||
1848 | input [39:0] lndskw0_data; | |
1849 | input [39:0] lndskw1_data; | |
1850 | ||
1851 | input [167:40] fbdird_ibrx_data; | |
1852 | ||
1853 | input [2:0] drif_dram_cmd_a; | |
1854 | input [15:0] drif_dram_addr_a; | |
1855 | input [2:0] drif_dram_bank_a; | |
1856 | input [2:0] drif_dram_dimm_a; | |
1857 | input drif_dram_rank_a; | |
1858 | ||
1859 | input [2:0] drif_dram_cmd_b; | |
1860 | input [15:0] drif_dram_addr_b; | |
1861 | input [2:0] drif_dram_bank_b; | |
1862 | input [2:0] drif_dram_dimm_b; | |
1863 | input drif_dram_rank_b; | |
1864 | ||
1865 | input drif_wdata_wsn; | |
1866 | input woq_err_st_wait_free; | |
1867 | ||
1868 | input [2:0] drif_dram_cmd_c; | |
1869 | input [15:0] drif_dram_addr_c; | |
1870 | input [2:0] drif_dram_bank_c; | |
1871 | input [2:0] drif_dram_dimm_c; | |
1872 | input drif_dram_rank_c; | |
1873 | ||
1874 | input drif_single_channel_mode; | |
1875 | input drif_branch_disabled; | |
1876 | input drif_mcu_idle; | |
1877 | input drif_cke_reg; | |
1878 | input drif_stacked_dimm; | |
1879 | input [2:0] drif_num_dimms; | |
1880 | input rdpctl_fifo_empty; | |
1881 | input rdpctl_crc_recov_err; | |
1882 | input rdpctl_crc_unrecov_err; | |
1883 | input rdpctl_mask_err; | |
1884 | input drif_dbg_trig_reg_ld; | |
1885 | input [5:0] fdout_link_cnt; | |
1886 | ||
1887 | input drif_err_state_crc_fr; | |
1888 | ||
1889 | input rdata_err_fbui; | |
1890 | input rdata_err_fbri; | |
1891 | ||
1892 | input fbdird_crc_cmp0_0; | |
1893 | input fbdird_crc_cmp0_1; | |
1894 | input fbdird_crc_cmp1_0; | |
1895 | input fbdird_crc_cmp1_1; | |
1896 | ||
1897 | input [13:0] lndskw0_ts0_hdr_match; | |
1898 | input [13:0] lndskw1_ts0_hdr_match; | |
1899 | input [11:0] lndskw0_status_parity; | |
1900 | input [11:0] lndskw1_status_parity; | |
1901 | input [13:0] lndskw0_idle_match; | |
1902 | input [13:0] lndskw1_idle_match; | |
1903 | input [13:0] lndskw0_alert_match; | |
1904 | input [13:0] lndskw1_alert_match; | |
1905 | input [11:0] lndskw0_alert_asserted; | |
1906 | input [11:0] lndskw1_alert_asserted; | |
1907 | input [11:0] lndskw0_nbde; | |
1908 | input [11:0] lndskw1_nbde; | |
1909 | input [23:0] lndskw0_thermal_trip; | |
1910 | input [23:0] lndskw1_thermal_trip; | |
1911 | ||
1912 | input [31:0] fbdird0_cnfgreg_data; | |
1913 | input [31:0] fbdird1_cnfgreg_data; | |
1914 | ||
1915 | input [2:0] fsr0_mcu_stspll_lock; | |
1916 | input [2:0] fsr1_mcu_stspll_lock; | |
1917 | input [9:0] fsr0_mcu_ststx_testfail; | |
1918 | input [9:0] fsr1_mcu_ststx_testfail; | |
1919 | ||
1920 | input rdpctl_dtm_atspeed; | |
1921 | input ccu_serdes_dtm; | |
1922 | input mcu_gnd; | |
1923 | ||
1924 | input drl2clk; | |
1925 | input scan_in; | |
1926 | output scan_out; | |
1927 | input wmr_scan_in; | |
1928 | output fbdic_wmr_scanout; | |
1929 | input tcu_pce_ov; | |
1930 | input tcu_aclk; | |
1931 | input tcu_bclk; | |
1932 | input aclk_wmr; | |
1933 | input tcu_scan_en; | |
1934 | input wmr_protect; | |
1935 | input tcu_mcu_testmode; | |
1936 | ||
1937 | input fbdtm_si; | |
1938 | output fbdtm_so; | |
1939 | input fbdtm_wmr_si; | |
1940 | output fbdtm_wmr_so; | |
1941 | ||
1942 | // Code | |
1943 | assign pce_ov = tcu_pce_ov; | |
1944 | assign siclk = tcu_aclk; | |
1945 | assign soclk = tcu_bclk; | |
1946 | assign se = tcu_scan_en; | |
1947 | ||
1948 | // 0in set_clock drl2clk -default | |
1949 | // 0in default_reset tcu_scan_en | |
1950 | mcu_fbdic_ctl_l1clkhdr_ctl_macro clkgen ( | |
1951 | .l2clk(drl2clk), | |
1952 | .l1en (1'b1), | |
1953 | .stop(1'b0), | |
1954 | .l1clk(l1clk), | |
1955 | .pce_ov(pce_ov), | |
1956 | .se(se)); | |
1957 | ||
1958 | // | |
1959 | reg [6:0] fbdic_err_state_in; | |
1960 | ||
1961 | ///////////////////////////////// | |
1962 | // REGISTERS | |
1963 | ///////////////////////////////// | |
1964 | ||
1965 | ///////////////////////////////// | |
1966 | // FBD Initialization State Register | |
1967 | ///////////////////////////////// | |
1968 | assign fbdic_fbd_state_ld = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h800; | |
1969 | assign fbdic_fbd_state_en = fbdic_fbd_state_ld | | |
1970 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h0 & fbdic_tdisable_done | | |
1971 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h1 & fbdic_tcalibrate_done | | |
1972 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h2 & (fbdic_tclktrain_done[0] | fbdic_tclktrain_to_done) | | |
1973 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h3 & (fbdic_testing_done[0] | fbdic_testing_to_done) | | |
1974 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h4 & (fbdic_polling_done[0] | fbdic_polling_to_done) | | |
1975 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h5 & (fbdic_config_done[0] | fbdic_config_to_done) | | |
1976 | fbdic_fbd_state[2:0] == 3'h7 & fbdic_sync_frame_req_d4 | | |
1977 | fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | fbdic_dtm_fbd_state0_en | fbdic_dtm_fbd_state2_en | | |
1978 | fbdic_dtm_fbd_state6_en | rdpctl_kp_lnk_up_clr; | |
1979 | ||
1980 | assign fbdic_fbd_chnl_init_seq = fbdic_chnl_reset[0] | fbdic_ibtx_start | fbdic_ibist_done; | |
1981 | ||
1982 | assign fbdic_fbd_state_in[2:0] = fbdic_fbd_state_ld ? drif_ucb_data[2:0] : | |
1983 | fbdic_fbd_state[2:0] == 3'h0 & fbdic_tdisable_done & (fbdic_chnl_reset[0] & fbdic_fast_reset | | |
1984 | fbdic_ibtx_start & ~fbdic_sbcaliben | | |
1985 | fbdic_chnl_reset[0] & ~fbdic_fast_reset & fbdic_tcalibrate_done | | |
1986 | fbdic_ibtx_start & fbdic_sbcaliben & fbdic_tcalibrate_done) | fbdic_dtm_fbd_state2_en ? 3'h2 : | |
1987 | fbdic_fbd_state[2:0] == 3'h0 & fbdic_tdisable_done & (fbdic_chnl_reset[0] & ~fbdic_fast_reset | | |
1988 | fbdic_ibtx_start & fbdic_sbcaliben) ? 3'h1 : | |
1989 | fbdic_fbd_chnl_init_seq & (fbdic_fbd_state[2:0] == 3'h1 & fbdic_tcalibrate_done | | |
1990 | fbdic_fbd_state[2:0] == 3'h2 & fbdic_tclktrain_to_done | | |
1991 | fbdic_fbd_state[2:0] == 3'h3 & fbdic_testing_to_done | | |
1992 | fbdic_fbd_state[2:0] == 3'h4 & fbdic_polling_to_done | | |
1993 | fbdic_fbd_state[2:0] == 3'h5 & fbdic_config_to_done) | fbdic_dtm_fbd_state0_en ? 3'h0 : | |
1994 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h2 & fbdic_tclktrain_done[0] ? 3'h3 : | |
1995 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h3 & fbdic_testing_done[0] ? 3'h4 : | |
1996 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h4 & fbdic_polling_done[0] ? 3'h5 : | |
1997 | fbdic_fbd_chnl_init_seq & fbdic_fbd_state[2:0] == 3'h5 & fbdic_config_done[0] | | |
1998 | fbdic_dtm_fbd_state6_en | rdpctl_kp_lnk_up_clr ? 3'h6 : | |
1999 | fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | fbdic_fbd_state[2:0] == 3'h7 & fbdic_sync_frame_req_d4 ? 3'h0 : | |
2000 | fbdic_fbd_state[2:1] == 2'h3 & fbdic_fbd_state_ld & drif_ucb_data[2:0] == 3'h0 ? 3'h7 : 3'h0; | |
2001 | ||
2002 | assign fbdic_fbd_state_in[7:3] = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h800 ? | |
2003 | drif_ucb_data[7:3] : fbdic_fbd_state[7:3]; | |
2004 | ||
2005 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_4 pff_fbd_state ( // FS:wmr_protect | |
2006 | .scan_in(pff_fbd_state_wmr_scanin), | |
2007 | .scan_out(pff_fbd_state_wmr_scanout), | |
2008 | .siclk(aclk_wmr), | |
2009 | .din(fbdic_fbd_state_in[6:3]), | |
2010 | .dout(fbdic_fbd_state[6:3]), | |
2011 | .en(fbdic_fbd_state_en), | |
2012 | .l1clk(l1clk), | |
2013 | .soclk(soclk)); | |
2014 | ||
2015 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_4 ff_fbd_state ( | |
2016 | .scan_in(ff_fbd_state_scanin), | |
2017 | .scan_out(ff_fbd_state_scanout), | |
2018 | .din({fbdic_fbd_state_in[7],fbdic_fbd_state_in[2:0]}), | |
2019 | .dout({fbdic_fbd_state[7],fbdic_fbd_state[2:0]}), | |
2020 | .en(fbdic_fbd_state_en), | |
2021 | .l1clk(l1clk), | |
2022 | .siclk(siclk), | |
2023 | .soclk(soclk)); | |
2024 | ||
2025 | assign fbdic_disable_state = fbdic_fbd_state[2:0] == 3'h0; | |
2026 | assign fbdic_calibrate_state = fbdic_fbd_state[2:0] == 3'h1; | |
2027 | assign fbdic_testing_state = fbdic_fbd_state[2:0] == 3'h3; | |
2028 | assign fbdic_polling_state = fbdic_fbd_state[2:0] == 3'h4; | |
2029 | assign fbdic_config_state = fbdic_fbd_state[2:0] == 3'h5; | |
2030 | ||
2031 | ///////////////////////////////// | |
2032 | // FBD Fast Reset Flag | |
2033 | ///////////////////////////////// | |
2034 | assign fbdic_fast_reset_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h808; | |
2035 | assign fbdic_fast_reset_in[2:0] = drif_ucb_data[2:0]; | |
2036 | ||
2037 | assign fbdic_fast_reset_3_en = fbdic_fast_reset_en | fbdic_sync_ier_enable & ~fbdic_l0_state; | |
2038 | assign fbdic_fast_reset_in[3] = drif_ucb_data[3] & fbdic_l0_state; | |
2039 | ||
2040 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_1 pff_fast_reset_3 ( // FS:wmr_protect | |
2041 | .scan_in(pff_fast_reset_wmr_scanin), | |
2042 | .scan_out(pff_fast_reset_3_wmr_scanout), | |
2043 | .siclk(aclk_wmr), | |
2044 | .din(fbdic_fast_reset_in[3]), | |
2045 | .dout(fbdic_sync_ier_enable), | |
2046 | .en(fbdic_fast_reset_3_en), | |
2047 | .l1clk(l1clk), | |
2048 | .soclk(soclk)); | |
2049 | ||
2050 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_3 pff_fast_reset ( // FS:wmr_protect | |
2051 | .scan_in(pff_fast_reset_3_wmr_scanout), | |
2052 | .scan_out(pff_fast_reset_wmr_scanout), | |
2053 | .siclk(aclk_wmr), | |
2054 | .din(fbdic_fast_reset_in[2:0]), | |
2055 | .dout({fbdic_sync_r[1:0], fbdic_fast_reset}), | |
2056 | .en(fbdic_fast_reset_en), | |
2057 | .l1clk(l1clk), | |
2058 | .soclk(soclk)); | |
2059 | ||
2060 | assign fbdic_sync_ier_in = fbdic_sync_ier_enable; | |
2061 | ||
2062 | mcu_fbdic_ctl_msff_ctl_macro ff_sync_ier ( | |
2063 | .scan_in(ff_sync_ier_scanin), | |
2064 | .scan_out(ff_sync_ier_scanout), | |
2065 | .din(fbdic_sync_ier_in), | |
2066 | .dout(fbdic_sync_ier), | |
2067 | .l1clk(l1clk), | |
2068 | .siclk(siclk), | |
2069 | .soclk(soclk)); | |
2070 | ||
2071 | //`ifdef MCU_BUG_118987 | |
2072 | //assign fbdic_fr_issued_in = fbdic_err_fast_chnl_reset | fast_reset_err ? 1'b1 : | |
2073 | // ~(drif_err_state_crc_fr | fbdic_err_state[`FBDIC_ERR_FASTRST]) | | |
2074 | // drif_err_state_crc_fr & fbdic_err_state[`FBDIC_ERR_FASTRST] ? 1'b0 : fbdic_fr_issued; | |
2075 | //`else | |
2076 | assign fbdic_fr_issued_in = fbdic_err_fast_chnl_reset | fast_reset_err ? 1'b1 : | |
2077 | ~(drif_err_state_crc_fr | fbdic_err_state[`FBDIC_ERR_FASTRST]) ? 1'b0 : fbdic_fr_issued; | |
2078 | //`endif | |
2079 | ||
2080 | mcu_fbdic_ctl_msff_ctl_macro ff_fr_issued ( | |
2081 | .scan_in(ff_fr_issued_scanin), | |
2082 | .scan_out(ff_fr_issued_scanout), | |
2083 | .din(fbdic_fr_issued_in), | |
2084 | .dout(fbdic_fr_issued), | |
2085 | .l1clk(l1clk), | |
2086 | .siclk(siclk), | |
2087 | .soclk(soclk)); | |
2088 | ||
2089 | // Recalibrate not supported | |
2090 | assign fbdic_sync_erc = 1'b0; | |
2091 | ||
2092 | ///////////////////////////////// | |
2093 | // FBD Channel Reset (Initialization) Flag | |
2094 | ///////////////////////////////// | |
2095 | ||
2096 | assign fast_reset_err_on_first_sync = fbdic_idle_lfsr_reset_d1 & ~fbdic_idle_lfsr_reset & ~fbdic_idle_frame ; | |
2097 | ||
2098 | assign fast_reset_err = fast_reset_err_on_first_sync | woq_err_st_wait_free & fbdic_error_mode; | |
2099 | ||
2100 | assign fbdic_chnl_reset_ld = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h810 & drif_ucb_data[0] | | |
2101 | fbdic_err_fast_chnl_reset | fast_reset_err; | |
2102 | assign fbdic_chnl_reset_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h810 | fbdic_chnl_reset_clr | | |
2103 | fbdic_err_fast_chnl_reset | fast_reset_err; | |
2104 | assign fbdic_chnl_reset_in[1:0] = fbdic_chnl_reset_clr ? {fbdic_chnl_reset_error, 1'b0} : | |
2105 | fbdic_err_fast_chnl_reset | fast_reset_err ? 2'h1 : drif_ucb_data[1:0]; | |
2106 | assign fbdic_chnl_reset_clr = fbdic_chnl_reset[0] & fbdic_fbd_state[2:0] == 3'h5 & fbdic_config_done[0] | | |
2107 | fbdic_chnl_reset_error; | |
2108 | assign fbdic_chnl_reset_error = fbdic_tclktrain_to_done | fbdic_testing_to_done | | |
2109 | fbdic_polling_to_done | fbdic_config_to_done; | |
2110 | ||
2111 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_1 pff_chnl_reset1 ( // FS:wmr_protect | |
2112 | .scan_in(pff_chnl_reset1_wmr_scanin), | |
2113 | .scan_out(pff_chnl_reset1_wmr_scanout), | |
2114 | .siclk(aclk_wmr), | |
2115 | .din(fbdic_chnl_reset_in[1]), | |
2116 | .dout(fbdic_chnl_reset[1]), | |
2117 | .en(fbdic_chnl_reset_en), | |
2118 | .l1clk(l1clk), | |
2119 | .soclk(soclk)); | |
2120 | ||
2121 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_1 pff_chnl_reset0 ( | |
2122 | .scan_in(pff_chnl_reset0_scanin), | |
2123 | .scan_out(pff_chnl_reset0_scanout), | |
2124 | .din(fbdic_chnl_reset_in[0]), | |
2125 | .dout(fbdic_chnl_reset[0]), | |
2126 | .en(fbdic_chnl_reset_en), | |
2127 | .l1clk(l1clk), | |
2128 | .siclk(siclk), | |
2129 | .soclk(soclk)); | |
2130 | ||
2131 | assign fbdic_chnl_reset_error_mode_in = fbdic_chnl_reset_error ? 1'b1 : | |
2132 | (|fbdic_fbd_state[2:0]) ? 1'b0 : fbdic_chnl_reset_error_mode; | |
2133 | mcu_fbdic_ctl_msff_ctl_macro ff_chnl_reset_error_mode ( | |
2134 | .scan_in(ff_chnl_reset_error_mode_scanin), | |
2135 | .scan_out(ff_chnl_reset_error_mode_scanout), | |
2136 | .din(fbdic_chnl_reset_error_mode_in), | |
2137 | .dout(fbdic_chnl_reset_error_mode), | |
2138 | .l1clk(l1clk), | |
2139 | .siclk(siclk), | |
2140 | .soclk(soclk)); | |
2141 | ||
2142 | ///////////////////////////////// | |
2143 | // FBD TS1 SB to NB Mapping Register | |
2144 | ///////////////////////////////// | |
2145 | assign fbdic_sb2nb_map_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h818; | |
2146 | assign fbdic_sb2nb_map_in[3:0] = drif_ucb_data[3:0]; | |
2147 | ||
2148 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_4 pff_sb2nb_map ( // FS:wmr_protect | |
2149 | .scan_in(pff_sb2nb_map_wmr_scanin), | |
2150 | .scan_out(pff_sb2nb_map_wmr_scanout), | |
2151 | .siclk(aclk_wmr), | |
2152 | .din(fbdic_sb2nb_map_in[3:0]), | |
2153 | .dout(fbdic_sb2nb_map[3:0]), | |
2154 | .en(fbdic_sb2nb_map_en), | |
2155 | .l1clk(l1clk), | |
2156 | .soclk(soclk)); | |
2157 | ||
2158 | assign fbdic_ibrx_data_sel = fbdic_sb2nb_map[3]; | |
2159 | assign fbdic_ibrx_data_sel_l = ~fbdic_sb2nb_map[3]; | |
2160 | ||
2161 | ///////////////////////////////// | |
2162 | // FBD TS1 Test Parameter Register | |
2163 | ///////////////////////////////// | |
2164 | assign fbdic_amb_test_param_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h820; | |
2165 | assign fbdic_amb_test_param_in[23:0] = drif_ucb_data[23:0]; | |
2166 | ||
2167 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_24 pff_amb_test_param ( // FS:wmr_protect | |
2168 | .scan_in(pff_amb_test_param_wmr_scanin), | |
2169 | .scan_out(pff_amb_test_param_wmr_scanout), | |
2170 | .siclk(aclk_wmr), | |
2171 | .din(fbdic_amb_test_param_in[23:0]), | |
2172 | .dout(fbdic_amb_test_param[23:0]), | |
2173 | .en(fbdic_amb_test_param_en), | |
2174 | .l1clk(l1clk), | |
2175 | .soclk(soclk)); | |
2176 | ||
2177 | ///////////////////////////////// | |
2178 | // FBD TS3 Failover Configuration Register - reset to 16'hffff | |
2179 | ///////////////////////////////// | |
2180 | ||
2181 | assign fbdic_failover_config_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h828; | |
2182 | assign fbdic_failover_config_in[15:0] = drif_ucb_data[15:0]; | |
2183 | ||
2184 | assign inv_fbdic_failover_config_in[15:0] = ~fbdic_failover_config_in[15:0]; | |
2185 | assign fbdic_failover_config[15:0] = ~inv_fbdic_failover_config[15:0]; | |
2186 | ||
2187 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_16 pff_failover_config ( // FS:wmr_protect | |
2188 | .scan_in(pff_failover_config_wmr_scanin), | |
2189 | .scan_out(pff_failover_config_wmr_scanout), | |
2190 | .siclk(aclk_wmr), | |
2191 | .din(inv_fbdic_failover_config_in[15:0]), | |
2192 | .dout(inv_fbdic_failover_config[15:0]), | |
2193 | .en(fbdic_failover_config_en), | |
2194 | .l1clk(l1clk), | |
2195 | .soclk(soclk)); | |
2196 | ||
2197 | assign fbdic1_sb_failover = fbdic_failover_config[15:12] <= 4'd9; | |
2198 | assign fbdic1_sb_failover_l = ~fbdic1_sb_failover; | |
2199 | assign fbdic1_sb_failover_mask[8:0] = {fbdic_failover_config[15:12] <= 4'h8, | |
2200 | fbdic_failover_config[15:12] <= 4'h7, | |
2201 | fbdic_failover_config[15:12] <= 4'h6, | |
2202 | fbdic_failover_config[15:12] <= 4'h5, | |
2203 | fbdic_failover_config[15:12] <= 4'h4, | |
2204 | fbdic_failover_config[15:12] <= 4'h3, | |
2205 | fbdic_failover_config[15:12] <= 4'h2, | |
2206 | fbdic_failover_config[15:12] <= 4'h1, | |
2207 | fbdic_failover_config[15:12] == 4'h0}; | |
2208 | assign fbdic1_sb_failover_mask_l[8:0] = ~fbdic1_sb_failover_mask[8:0]; | |
2209 | ||
2210 | ||
2211 | assign fbdic1_nb_failover = fbdic_failover_config[11:8] <= 4'd13; | |
2212 | assign fbdic1_nb_failover_l = ~fbdic1_nb_failover; | |
2213 | assign fbdic1_nb_failover_mask[12:0] = {fbdic_failover_config[11:8] <= 4'hc, | |
2214 | fbdic_failover_config[11:8] <= 4'hb, | |
2215 | fbdic_failover_config[11:8] <= 4'ha, | |
2216 | fbdic_failover_config[11:8] <= 4'h9, | |
2217 | fbdic_failover_config[11:8] <= 4'h8, | |
2218 | fbdic_failover_config[11:8] <= 4'h7, | |
2219 | fbdic_failover_config[11:8] <= 4'h6, | |
2220 | fbdic_failover_config[11:8] <= 4'h5, | |
2221 | fbdic_failover_config[11:8] <= 4'h4, | |
2222 | fbdic_failover_config[11:8] <= 4'h3, | |
2223 | fbdic_failover_config[11:8] <= 4'h2, | |
2224 | fbdic_failover_config[11:8] <= 4'h1, | |
2225 | fbdic_failover_config[11:8] == 4'h0}; | |
2226 | assign fbdic1_nb_failover_mask_l[12:0] = ~fbdic1_nb_failover_mask[12:0]; | |
2227 | ||
2228 | assign fbdic0_sb_failover = fbdic_failover_config[7:4] <= 4'd9; | |
2229 | assign fbdic0_sb_failover_l = ~fbdic0_sb_failover; | |
2230 | assign fbdic0_sb_failover_mask[8:0] = {fbdic_failover_config[7:4] <= 4'h8, | |
2231 | fbdic_failover_config[7:4] <= 4'h7, | |
2232 | fbdic_failover_config[7:4] <= 4'h6, | |
2233 | fbdic_failover_config[7:4] <= 4'h5, | |
2234 | fbdic_failover_config[7:4] <= 4'h4, | |
2235 | fbdic_failover_config[7:4] <= 4'h3, | |
2236 | fbdic_failover_config[7:4] <= 4'h2, | |
2237 | fbdic_failover_config[7:4] <= 4'h1, | |
2238 | fbdic_failover_config[7:4] == 4'h0}; | |
2239 | assign fbdic0_sb_failover_mask_l[8:0] = ~fbdic0_sb_failover_mask[8:0]; | |
2240 | ||
2241 | assign fbdic0_nb_failover = fbdic_failover_config[3:0] <= 4'd13; | |
2242 | assign fbdic0_nb_failover_l = ~fbdic0_nb_failover; | |
2243 | assign fbdic0_nb_failover_mask[12:0] = {fbdic_failover_config[3:0] <= 4'hc, | |
2244 | fbdic_failover_config[3:0] <= 4'hb, | |
2245 | fbdic_failover_config[3:0] <= 4'ha, | |
2246 | fbdic_failover_config[3:0] <= 4'h9, | |
2247 | fbdic_failover_config[3:0] <= 4'h8, | |
2248 | fbdic_failover_config[3:0] <= 4'h7, | |
2249 | fbdic_failover_config[3:0] <= 4'h6, | |
2250 | fbdic_failover_config[3:0] <= 4'h5, | |
2251 | fbdic_failover_config[3:0] <= 4'h4, | |
2252 | fbdic_failover_config[3:0] <= 4'h3, | |
2253 | fbdic_failover_config[3:0] <= 4'h2, | |
2254 | fbdic_failover_config[3:0] <= 4'h1, | |
2255 | fbdic_failover_config[3:0] == 4'h0}; | |
2256 | assign fbdic0_nb_failover_mask_l[12:0] = ~fbdic0_nb_failover_mask[12:0]; | |
2257 | ||
2258 | ///////////////////////////////// | |
2259 | // FBD Electical Idle Detected Register - read-only | |
2260 | ///////////////////////////////// | |
2261 | ||
2262 | assign inv_fbdic_elect_idle_detect_in[27:0] = {~fbd1_elect_idle[13:0],~fbd0_elect_idle[13:0]}; | |
2263 | assign fbdic_elect_idle_detect[27:0] = ~inv_fbdic_elect_idle_detect[27:0]; | |
2264 | ||
2265 | mcu_fbdic_ctl_msff_ctl_macro__width_28 ff_elect_idle_detect ( | |
2266 | .scan_in(ff_elect_idle_detect_scanin), | |
2267 | .scan_out(ff_elect_idle_detect_scanout), | |
2268 | .din(inv_fbdic_elect_idle_detect_in[27:0]), | |
2269 | .dout(inv_fbdic_elect_idle_detect[27:0]), | |
2270 | .l1clk(l1clk), | |
2271 | .siclk(siclk), | |
2272 | .soclk(soclk)); | |
2273 | ||
2274 | ///////////////////////////////// | |
2275 | // FBD Disable State Period Register | |
2276 | ///////////////////////////////// | |
2277 | ||
2278 | assign fbdic_tdisable_period_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h838; | |
2279 | assign fbdic_tdisable_period_in[9:0] = drif_ucb_data[9:0]; | |
2280 | ||
2281 | assign inv_fbdic_tdisable_period_in[7:0] = ~fbdic_tdisable_period_in[7:0]; | |
2282 | assign fbdic_tdisable_period[7:0] = ~inv_fbdic_tdisable_period[7:0]; | |
2283 | ||
2284 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_10 pff_tdisable_period ( // FS:wmr_protect | |
2285 | .scan_in(pff_tdisable_period_wmr_scanin), | |
2286 | .scan_out(pff_tdisable_period_wmr_scanout), | |
2287 | .siclk(aclk_wmr), | |
2288 | .din({fbdic_tdisable_period_in[9:8],inv_fbdic_tdisable_period_in[7:0]}), | |
2289 | .dout({fbdic_tdisable_period[9:8],inv_fbdic_tdisable_period[7:0]}), | |
2290 | .en(fbdic_tdisable_period_en), | |
2291 | .l1clk(l1clk), | |
2292 | .soclk(soclk)); | |
2293 | ||
2294 | ///////////////////////////////// | |
2295 | // FBD Disable State Period Done Register | |
2296 | ///////////////////////////////// | |
2297 | assign fbdic_enter_disable_state = fbdic_fbd_state_en & (fbdic_fbd_state_in[2:0] == 3'h0); | |
2298 | ||
2299 | assign fbdic_tdisable_done_en = fbdic_disable_state & ~fbdic_tdisable_done & fbdic_tdisable_cnt[9:0] == 10'h0 | | |
2300 | fbdic_calibrate_state | fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | | |
2301 | fbdic_enter_disable_state | | |
2302 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h840; | |
2303 | assign fbdic_tdisable_done_in = fbdic_disable_state & ~fbdic_tdisable_done & fbdic_tdisable_cnt[9:0] == 10'h0 ? 1'b1 : | |
2304 | fbdic_calibrate_state | fbdic_ibtx_start_ld | fbdic_chnl_reset_ld | | |
2305 | fbdic_enter_disable_state ? 1'b0 : drif_ucb_data[0]; | |
2306 | ||
2307 | mcu_fbdic_ctl_msff_ctl_macro__en_1 ff_tdisable_done ( | |
2308 | .scan_in(ff_tdisable_done_scanin), | |
2309 | .scan_out(ff_tdisable_done_scanout), | |
2310 | .din(fbdic_tdisable_done_in), | |
2311 | .dout(fbdic_tdisable_done), | |
2312 | .en(fbdic_tdisable_done_en), | |
2313 | .l1clk(l1clk), | |
2314 | .siclk(siclk), | |
2315 | .soclk(soclk)); | |
2316 | ||
2317 | assign fbdic_tdisable_cnt_in[9:0] = fbdic_disable_state & (fbdic_chnl_reset[0] | fbdic_ibtx_start | fbdic_tdisable_start) ? | |
2318 | (fbdic_tdisable_cnt[9:0] == 10'h0 ? 10'h0 : fbdic_tdisable_cnt[9:0] - 10'h1) : | |
2319 | fbdic_ibtx_start_ld ? fbdic_sbdiscnt[9:0] : fbdic_tdisable_period[9:0]; | |
2320 | ||
2321 | assign inv_fbdic_tdisable_cnt_in[9:0] = ~fbdic_tdisable_cnt_in[9:0]; | |
2322 | assign fbdic_tdisable_cnt[9:0] = ~inv_fbdic_tdisable_cnt[9:0]; | |
2323 | ||
2324 | mcu_fbdic_ctl_msff_ctl_macro__width_10 ff_tdisable_cnt ( | |
2325 | .scan_in(ff_tdisable_cnt_scanin), | |
2326 | .scan_out(ff_tdisable_cnt_scanout), | |
2327 | .din(inv_fbdic_tdisable_cnt_in[9:0]), | |
2328 | .dout(inv_fbdic_tdisable_cnt[9:0]), | |
2329 | .l1clk(l1clk), | |
2330 | .siclk(siclk), | |
2331 | .soclk(soclk)); | |
2332 | ||
2333 | assign fbdic_tdisable_start_in = fbdic_fbd_state_en & (fbdic_fbd_state_in[2:0] == 3'h0) ? 1'b1 : | |
2334 | (|fbdic_fbd_state[2:0]) ? 1'b0 : fbdic_tdisable_start; | |
2335 | ||
2336 | mcu_fbdic_ctl_msff_ctl_macro ff_tdisable_start ( | |
2337 | .scan_in(ff_tdisable_start_scanin), | |
2338 | .scan_out(ff_tdisable_start_scanout), | |
2339 | .din(fbdic_tdisable_start_in), | |
2340 | .dout(fbdic_tdisable_start), | |
2341 | .l1clk(l1clk), | |
2342 | .siclk(siclk), | |
2343 | .soclk(soclk)); | |
2344 | ||
2345 | ///////////////////////////////// | |
2346 | // FBD Calibrate State Period Register | |
2347 | ///////////////////////////////// | |
2348 | ||
2349 | assign fbdic_tcalibrate_period_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h848; | |
2350 | assign fbdic_tcalibrate_period_in[19:0] = drif_ucb_data[19:0]; | |
2351 | ||
2352 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_20 pff_tcalibrate_period ( // FS:wmr_protect | |
2353 | .scan_in(pff_tcalibrate_period_wmr_scanin), | |
2354 | .scan_out(pff_tcalibrate_period_wmr_scanout), | |
2355 | .siclk(aclk_wmr), | |
2356 | .din(fbdic_tcalibrate_period_in[19:0]), | |
2357 | .dout(fbdic_tcalibrate_period[19:0]), | |
2358 | .en(fbdic_tcalibrate_period_en), | |
2359 | .l1clk(l1clk), | |
2360 | .soclk(soclk)); | |
2361 | ||
2362 | ///////////////////////////////// | |
2363 | // FBD Calibrate State Period Done Register | |
2364 | ///////////////////////////////// | |
2365 | assign fbdic_tcalibrate_done_en = fbdic_calibrate_state & ~fbdic_tcalibrate_done & fbdic_tcalibrate_cnt[19:0] == 20'h0 | | |
2366 | fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | | |
2367 | fbdic_fbd_state_en & fbdic_fbd_state_in[2:0] == 3'h0 & fbdic_fbd_state[2:0] != 3'h1 | | |
2368 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h850; | |
2369 | assign fbdic_tcalibrate_done_in = | |
2370 | fbdic_calibrate_state & ~fbdic_tcalibrate_done & fbdic_tcalibrate_cnt[19:0] == 20'h0 ? 1'b1 : | |
2371 | fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | | |
2372 | fbdic_fbd_state_en & fbdic_fbd_state_in[2:0] == 3'h0 & fbdic_fbd_state[2:0] != 3'h1 ? 1'b0 : | |
2373 | drif_ucb_data[0]; | |
2374 | ||
2375 | mcu_fbdic_ctl_msff_ctl_macro__en_1 ff_tcalibrate_done ( | |
2376 | .scan_in(ff_tcalibrate_done_scanin), | |
2377 | .scan_out(ff_tcalibrate_done_scanout), | |
2378 | .din(fbdic_tcalibrate_done_in), | |
2379 | .dout(fbdic_tcalibrate_done), | |
2380 | .en(fbdic_tcalibrate_done_en), | |
2381 | .l1clk(l1clk), | |
2382 | .siclk(siclk), | |
2383 | .soclk(soclk)); | |
2384 | ||
2385 | assign fbdic_tcalibrate_cnt_in[19:0] = fbdic_calibrate_state ? (fbdic_tcalibrate_cnt[19:0] == 20'h0 ? 20'h0 : | |
2386 | fbdic_tcalibrate_cnt[19:0] - 20'h1) : | |
2387 | fbdic_ibtx_start ? fbdic_sbibistcalperiod[19:0] : fbdic_tcalibrate_period[19:0]; | |
2388 | ||
2389 | mcu_fbdic_ctl_msff_ctl_macro__width_20 ff_tcalibrate_cnt ( | |
2390 | .scan_in(ff_tcalibrate_cnt_scanin), | |
2391 | .scan_out(ff_tcalibrate_cnt_scanout), | |
2392 | .din(fbdic_tcalibrate_cnt_in[19:0]), | |
2393 | .dout(fbdic_tcalibrate_cnt[19:0]), | |
2394 | .l1clk(l1clk), | |
2395 | .siclk(siclk), | |
2396 | .soclk(soclk)); | |
2397 | ||
2398 | ///////////////////////////////// | |
2399 | // FBD Training State Minimum Time Register | |
2400 | ///////////////////////////////// | |
2401 | assign fbdic_tclktrain_min_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h858; | |
2402 | assign fbdic_tclktrain_min_in[15:0] = drif_ucb_data[15:0]; | |
2403 | ||
2404 | assign inv_fbdic_tclktrain_min_in[7:0] = ~fbdic_tclktrain_min_in[7:0]; | |
2405 | assign fbdic_tclktrain_min[7:0] = ~inv_fbdic_tclktrain_min[7:0]; | |
2406 | ||
2407 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_16 pff_tclktrain_min ( // FS:wmr_protect | |
2408 | .scan_in(pff_tclktrain_min_wmr_scanin), | |
2409 | .scan_out(pff_tclktrain_min_wmr_scanout), | |
2410 | .siclk(aclk_wmr), | |
2411 | .din({fbdic_tclktrain_min_in[15:8],inv_fbdic_tclktrain_min_in[7:0]}), | |
2412 | .dout({fbdic_tclktrain_min[15:8],inv_fbdic_tclktrain_min[7:0]}), | |
2413 | .en(fbdic_tclktrain_min_en), | |
2414 | .l1clk(l1clk), | |
2415 | .soclk(soclk)); | |
2416 | ||
2417 | assign fbdic_tclktrain_min_cnt_in[15:0] = fbdic_train_state ? (fbdic_tclktrain_min_cnt[15:0] == 16'h0 ? 16'h0 : | |
2418 | fbdic_tclktrain_min_cnt[15:0] - 16'h1) : | |
2419 | fbdic_tclktrain_min[15:0]; | |
2420 | ||
2421 | mcu_fbdic_ctl_msff_ctl_macro__width_16 ff_tclktrain_min_cnt ( | |
2422 | .scan_in(ff_tclktrain_min_cnt_scanin), | |
2423 | .scan_out(ff_tclktrain_min_cnt_scanout), | |
2424 | .din(fbdic_tclktrain_min_cnt_in[15:0]), | |
2425 | .dout(fbdic_tclktrain_min_cnt[15:0]), | |
2426 | .l1clk(l1clk), | |
2427 | .siclk(siclk), | |
2428 | .soclk(soclk)); | |
2429 | ||
2430 | assign fbdic_enable_sync_count_in = (fbdic_tclktrain_min_cnt[15:0] == 16'h0) & fbdic_train_state | | |
2431 | fbdic_disable_state & (fbdic_serdes_dtm | fbdic_loopback[1]); | |
2432 | mcu_fbdic_ctl_msff_ctl_macro__width_1 ff_enable_sync_count ( | |
2433 | .scan_in(ff_enable_sync_count_scanin), | |
2434 | .scan_out(ff_enable_sync_count_scanout), | |
2435 | .din(fbdic_enable_sync_count_in), | |
2436 | .dout(fbdic_enable_sync_count), | |
2437 | .l1clk(l1clk), | |
2438 | .siclk(siclk), | |
2439 | .soclk(soclk)); | |
2440 | ||
2441 | ///////////////////////////////// | |
2442 | // FBD Training State Done Register | |
2443 | ///////////////////////////////// | |
2444 | assign fbdic_tclktrain_rst_done = fbdic_train_state & ~(|fbdic_tclktrain_done[1:0]) & | |
2445 | fbdic_tclktrain_min_cnt[15:0] == 16'h0 & fbdic0_ts_match_cnt[3:0] == 4'hf; | |
2446 | assign fbdic_tclktrain_to_done = fbdic_train_state & ~(|fbdic_tclktrain_done[1:0]) & | |
2447 | fbdic_tclktrain_min_cnt[15:0] == 16'h0 & fbdic_tclktrain_timeout_cnt[15:0] == 16'h0; | |
2448 | assign fbdic_tclktrain_ibst_done = fbdic_ibtx_start & fbdic_train_state & fbdic_sbts_cnt[9:0] == 10'h0; | |
2449 | ||
2450 | assign fbdic_tclktrain_done_en = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | fbdic_tclktrain_rst_done | | |
2451 | fbdic_tclktrain_to_done | fbdic_tclktrain_ibst_done | fbdic_enter_disable_state | | |
2452 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h860; | |
2453 | ||
2454 | assign fbdic_tclktrain_done_in[1:0] = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld ? 2'h0 : | |
2455 | fbdic_tclktrain_to_done ? 2'h2 : | |
2456 | fbdic_enter_disable_state ? {fbdic_tclktrain_done[1], 1'b0} : | |
2457 | fbdic_tclktrain_rst_done | fbdic_tclktrain_ibst_done ? 2'h1 : drif_ucb_data[1:0]; | |
2458 | ||
2459 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_2 ff_tclktrain_done ( | |
2460 | .scan_in(ff_tclktrain_done_scanin), | |
2461 | .scan_out(ff_tclktrain_done_scanout), | |
2462 | .din(fbdic_tclktrain_done_in[1:0]), | |
2463 | .dout(fbdic_tclktrain_done[1:0]), | |
2464 | .en(fbdic_tclktrain_done_en), | |
2465 | .l1clk(l1clk), | |
2466 | .siclk(siclk), | |
2467 | .soclk(soclk)); | |
2468 | ||
2469 | ///////////////////////////////// | |
2470 | // FBD Training State Timeout Register | |
2471 | ///////////////////////////////// | |
2472 | assign fbdic_tclktrain_timeout_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h868; | |
2473 | assign fbdic_tclktrain_timeout_in[15:0] = drif_ucb_data[15:0]; | |
2474 | ||
2475 | assign inv_fbdic_tclktrain_timeout_in[15:0] = ~fbdic_tclktrain_timeout_in[15:0]; | |
2476 | assign fbdic_tclktrain_timeout[15:0] = ~inv_fbdic_tclktrain_timeout[15:0]; | |
2477 | ||
2478 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_16 pff_tclktrain_timeout ( // FS:wmr_protect | |
2479 | .scan_in(pff_tclktrain_timeout_wmr_scanin), | |
2480 | .scan_out(pff_tclktrain_timeout_wmr_scanout), | |
2481 | .siclk(aclk_wmr), | |
2482 | .din(inv_fbdic_tclktrain_timeout_in[15:0]), | |
2483 | .dout(inv_fbdic_tclktrain_timeout[15:0]), | |
2484 | .en(fbdic_tclktrain_timeout_en), | |
2485 | .l1clk(l1clk), | |
2486 | .soclk(soclk)); | |
2487 | ||
2488 | assign fbdic_tclktrain_timeout_cnt_in[15:0] = (fbdic_train_state & fbdic_tclktrain_min_cnt[15:0] == 16'h0 ? | |
2489 | (fbdic_tclktrain_timeout_cnt[15:0] == 16'h0 ? 16'h0 : | |
2490 | fbdic_tclktrain_timeout_cnt[15:0] - 16'h1) : | |
2491 | fbdic_tclktrain_timeout[15:0]) | | |
2492 | {8'h0, fbdic_ibist_data_mode | ~fbdic_chnl_reset[0], 7'h0}; | |
2493 | ||
2494 | mcu_fbdic_ctl_msff_ctl_macro__width_16 ff_tclktrain_timeout_cnt ( | |
2495 | .scan_in(ff_tclktrain_timeout_cnt_scanin), | |
2496 | .scan_out(ff_tclktrain_timeout_cnt_scanout), | |
2497 | .din(fbdic_tclktrain_timeout_cnt_in[15:0]), | |
2498 | .dout(fbdic_tclktrain_timeout_cnt[15:0]), | |
2499 | .l1clk(l1clk), | |
2500 | .siclk(siclk), | |
2501 | .soclk(soclk)); | |
2502 | ||
2503 | ///////////////////////////////// | |
2504 | // FBD Testing State Done Register | |
2505 | ///////////////////////////////// | |
2506 | assign fbdic_testing_rst_done = fbdic_testing_state & ~(|fbdic_testing_done[1:0]) & | |
2507 | fbdic0_ts_match_cnt[3:0] == 4'h4; | |
2508 | assign fbdic_testing_to_done = fbdic_testing_state & ~(|fbdic_testing_done[1:0]) & | |
2509 | fbdic_testing_timeout_cnt[7:0] == 8'h0; | |
2510 | assign fbdic_testing_ibst_done = ibtx_done & fbdic_testing_state & fbdic_sbts_cnt[9:0] == 10'h0; | |
2511 | ||
2512 | assign fbdic_testing_done_en = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | fbdic_testing_rst_done | | |
2513 | fbdic_testing_to_done | fbdic_testing_ibst_done | fbdic_enter_disable_state | | |
2514 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h870; | |
2515 | assign fbdic_testing_done_in[1:0] = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld ? 2'h0 : | |
2516 | fbdic_testing_to_done ? 2'h2 : | |
2517 | fbdic_enter_disable_state ? {fbdic_testing_done[1], 1'b0} : | |
2518 | fbdic_testing_rst_done | fbdic_testing_ibst_done ? 2'h1 : drif_ucb_data[1:0]; | |
2519 | ||
2520 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_2 ff_testing_done ( | |
2521 | .scan_in(ff_testing_done_scanin), | |
2522 | .scan_out(ff_testing_done_scanout), | |
2523 | .din(fbdic_testing_done_in[1:0]), | |
2524 | .dout(fbdic_testing_done[1:0]), | |
2525 | .en(fbdic_testing_done_en), | |
2526 | .l1clk(l1clk), | |
2527 | .siclk(siclk), | |
2528 | .soclk(soclk)); | |
2529 | ||
2530 | ///////////////////////////////// | |
2531 | // FBD Testing State Timeout Register | |
2532 | ///////////////////////////////// | |
2533 | ||
2534 | assign fbdic_testing_timeout_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h878; | |
2535 | assign fbdic_testing_timeout_in[7:0] = drif_ucb_data[7:0]; | |
2536 | ||
2537 | assign inv_fbdic_testing_timeout_in[7:0] = ~fbdic_testing_timeout_in[7:0]; | |
2538 | assign fbdic_testing_timeout[7:0] = ~inv_fbdic_testing_timeout[7:0]; | |
2539 | ||
2540 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_8 pff_testing_timeout ( // FS:wmr_protect | |
2541 | .scan_in(pff_testing_timeout_wmr_scanin), | |
2542 | .scan_out(pff_testing_timeout_wmr_scanout), | |
2543 | .siclk(aclk_wmr), | |
2544 | .din(inv_fbdic_testing_timeout_in[7:0]), | |
2545 | .dout(inv_fbdic_testing_timeout[7:0]), | |
2546 | .en(fbdic_testing_timeout_en), | |
2547 | .l1clk(l1clk), | |
2548 | .soclk(soclk)); | |
2549 | ||
2550 | assign fbdic_testing_timeout_cnt_in[7:0] = (fbdic_testing_state ? (fbdic_testing_timeout_cnt[7:0] == 8'h0 ? 8'h0 : | |
2551 | fbdic_testing_timeout_cnt[7:0] - 8'h1) : | |
2552 | fbdic_testing_timeout[7:0]) | | |
2553 | {fbdic_ibist_data_mode | ~fbdic_chnl_reset[0], 7'h0}; | |
2554 | mcu_fbdic_ctl_msff_ctl_macro__width_8 ff_testing_timeout_cnt ( | |
2555 | .scan_in(ff_testing_timeout_cnt_scanin), | |
2556 | .scan_out(ff_testing_timeout_cnt_scanout), | |
2557 | .din(fbdic_testing_timeout_cnt_in[7:0]), | |
2558 | .dout(fbdic_testing_timeout_cnt[7:0]), | |
2559 | .l1clk(l1clk), | |
2560 | .siclk(siclk), | |
2561 | .soclk(soclk)); | |
2562 | ||
2563 | ///////////////////////////////// | |
2564 | // FBD Polling State Done Register | |
2565 | ///////////////////////////////// | |
2566 | assign fbdic_polling_rst_done = fbdic_polling_state & ~(|fbdic_polling_done[1:0]) & | |
2567 | fbdic0_ts_match_cnt[3:0] == 4'hf; | |
2568 | assign fbdic_polling_to_done = fbdic_polling_state & ~(|fbdic_polling_done[1:0]) & | |
2569 | fbdic_polling_timeout_cnt[7:0] == 8'h0; | |
2570 | assign fbdic_polling_ibst_done = fbdic_ibist_done & fbdic_polling_state & fbdic_sbts_cnt[9:0] == 10'h0; | |
2571 | ||
2572 | assign fbdic_polling_done_en = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | fbdic_polling_to_done | | |
2573 | fbdic_polling_rst_done | fbdic_polling_ibst_done | fbdic_enter_disable_state | | |
2574 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h870; | |
2575 | assign fbdic_polling_done_in[1:0] = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld ? 2'h0 : | |
2576 | fbdic_polling_to_done ? 2'h2 : | |
2577 | fbdic_enter_disable_state ? {fbdic_polling_done[1], 1'b0} : | |
2578 | fbdic_polling_rst_done | fbdic_polling_ibst_done ? 2'h1 : drif_ucb_data[1:0]; | |
2579 | ||
2580 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_2 ff_polling_done ( | |
2581 | .scan_in(ff_polling_done_scanin), | |
2582 | .scan_out(ff_polling_done_scanout), | |
2583 | .din(fbdic_polling_done_in[1:0]), | |
2584 | .dout(fbdic_polling_done[1:0]), | |
2585 | .en(fbdic_polling_done_en), | |
2586 | .l1clk(l1clk), | |
2587 | .siclk(siclk), | |
2588 | .soclk(soclk)); | |
2589 | ||
2590 | ///////////////////////////////// | |
2591 | // FBD Polling State Timeout Register | |
2592 | ///////////////////////////////// | |
2593 | ||
2594 | assign fbdic_polling_timeout_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h888; | |
2595 | assign fbdic_polling_timeout_in[7:0] = drif_ucb_data[7:0]; | |
2596 | ||
2597 | assign inv_fbdic_polling_timeout_in[7:0] = ~fbdic_polling_timeout_in[7:0]; | |
2598 | assign fbdic_polling_timeout[7:0] = ~inv_fbdic_polling_timeout[7:0]; | |
2599 | ||
2600 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_8 pff_polling_timeout ( // FS:wmr_protect | |
2601 | .scan_in(pff_polling_timeout_wmr_scanin), | |
2602 | .scan_out(pff_polling_timeout_wmr_scanout), | |
2603 | .siclk(aclk_wmr), | |
2604 | .din(inv_fbdic_polling_timeout_in[7:0]), | |
2605 | .dout(inv_fbdic_polling_timeout[7:0]), | |
2606 | .en(fbdic_polling_timeout_en), | |
2607 | .l1clk(l1clk), | |
2608 | .soclk(soclk)); | |
2609 | ||
2610 | assign fbdic_polling_timeout_cnt_in[7:0] = (fbdic_polling_state ? (fbdic_polling_timeout_cnt[7:0] == 8'h0 ? 8'h0 : | |
2611 | fbdic_polling_timeout_cnt[7:0] - 8'h1) : | |
2612 | fbdic_polling_timeout[7:0]) | {~fbdic_chnl_reset[0], 7'h0}; | |
2613 | mcu_fbdic_ctl_msff_ctl_macro__width_8 ff_polling_timeout_cnt ( | |
2614 | .scan_in(ff_polling_timeout_cnt_scanin), | |
2615 | .scan_out(ff_polling_timeout_cnt_scanout), | |
2616 | .din(fbdic_polling_timeout_cnt_in[7:0]), | |
2617 | .dout(fbdic_polling_timeout_cnt[7:0]), | |
2618 | .l1clk(l1clk), | |
2619 | .siclk(siclk), | |
2620 | .soclk(soclk)); | |
2621 | ||
2622 | ///////////////////////////////// | |
2623 | // FBD Config State Done Register | |
2624 | ///////////////////////////////// | |
2625 | assign fbdic_config_rst_done = fbdic_config_state & ~(|fbdic_config_done[1:0]) & | |
2626 | fbdic0_ts_match_cnt[3:0] == 4'h4; | |
2627 | assign fbdic_config_to_done = fbdic_config_state & ~(|fbdic_config_done[1:0]) & | |
2628 | fbdic_config_timeout_cnt[7:0] == 8'h0; | |
2629 | assign fbdic_config_ibst_done = fbdic_ibist_done & fbdic_config_state & fbdic_sbts_cnt[9:0] == 10'h0; | |
2630 | ||
2631 | assign fbdic_config_done_en = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld | fbdic_config_rst_done | | |
2632 | fbdic_config_to_done | fbdic_config_ibst_done | fbdic_enter_disable_state | | |
2633 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h870; | |
2634 | assign fbdic_config_done_in[1:0] = fbdic_chnl_reset_ld | fbdic_ibtx_start_ld ? 2'h0 : | |
2635 | fbdic_config_to_done ? 2'h2 : | |
2636 | fbdic_enter_disable_state ? {fbdic_config_done[1], 1'b0} : | |
2637 | fbdic_config_ibst_done | fbdic_config_rst_done ? 2'h1 : drif_ucb_data[1:0]; | |
2638 | ||
2639 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_2 ff_config_done ( | |
2640 | .scan_in(ff_config_done_scanin), | |
2641 | .scan_out(ff_config_done_scanout), | |
2642 | .din(fbdic_config_done_in[1:0]), | |
2643 | .dout(fbdic_config_done[1:0]), | |
2644 | .en(fbdic_config_done_en), | |
2645 | .l1clk(l1clk), | |
2646 | .siclk(siclk), | |
2647 | .soclk(soclk)); | |
2648 | ||
2649 | ///////////////////////////////// | |
2650 | // FBD Config State Timeout Register | |
2651 | ///////////////////////////////// | |
2652 | ||
2653 | assign fbdic_config_timeout_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h898; | |
2654 | assign fbdic_config_timeout_in[7:0] = drif_ucb_data[7:0]; | |
2655 | ||
2656 | assign inv_fbdic_config_timeout_in[7:0] = ~fbdic_config_timeout_in[7:0]; | |
2657 | assign fbdic_config_timeout[7:0] = ~inv_fbdic_config_timeout[7:0]; | |
2658 | ||
2659 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_8 pff_config_timeout ( // FS:wmr_protect | |
2660 | .scan_in(pff_config_timeout_wmr_scanin), | |
2661 | .scan_out(pff_config_timeout_wmr_scanout), | |
2662 | .siclk(aclk_wmr), | |
2663 | .din(inv_fbdic_config_timeout_in[7:0]), | |
2664 | .dout(inv_fbdic_config_timeout[7:0]), | |
2665 | .en(fbdic_config_timeout_en), | |
2666 | .l1clk(l1clk), | |
2667 | .soclk(soclk)); | |
2668 | ||
2669 | assign fbdic_config_timeout_cnt_in[7:0] = (fbdic_config_state ? (fbdic_config_timeout_cnt[7:0] == 8'h0 ? 8'h0 : | |
2670 | fbdic_config_timeout_cnt[7:0] - 8'h1) : | |
2671 | fbdic_config_timeout[7:0]) | {~fbdic_chnl_reset[0], 7'h0}; | |
2672 | mcu_fbdic_ctl_msff_ctl_macro__width_8 ff_config_timeout_cnt ( | |
2673 | .scan_in(ff_config_timeout_cnt_scanin), | |
2674 | .scan_out(ff_config_timeout_cnt_scanout), | |
2675 | .din(fbdic_config_timeout_cnt_in[7:0]), | |
2676 | .dout(fbdic_config_timeout_cnt[7:0]), | |
2677 | .l1clk(l1clk), | |
2678 | .siclk(siclk), | |
2679 | .soclk(soclk)); | |
2680 | ||
2681 | ///////////////////////////////// | |
2682 | // FBD Per Rank CKE Register - reset to 16'hffff | |
2683 | ///////////////////////////////// | |
2684 | assign fbdic_per_rank_cke_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8A0; | |
2685 | assign fbdic_per_rank_cke_in[15:0] = drif_ucb_data[15:0]; | |
2686 | ||
2687 | assign inv_fbdic_per_rank_cke_in[15:0] = ~fbdic_per_rank_cke_in[15:0]; | |
2688 | assign fbdic_per_rank_cke[15:0] = ~inv_fbdic_per_rank_cke[15:0]; | |
2689 | ||
2690 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_16 pff_per_rank_cke ( // FS:wmr_protect | |
2691 | .scan_in(pff_per_rank_cke_wmr_scanin), | |
2692 | .scan_out(pff_per_rank_cke_wmr_scanout), | |
2693 | .siclk(aclk_wmr), | |
2694 | .din(inv_fbdic_per_rank_cke_in[15:0]), | |
2695 | .dout(inv_fbdic_per_rank_cke[15:0]), | |
2696 | .en(fbdic_per_rank_cke_en), | |
2697 | .l1clk(l1clk), | |
2698 | .soclk(soclk)); | |
2699 | ||
2700 | ||
2701 | assign fbdic_cke_cmd_pend_in = (fbdic_per_rank_cke_en & drif_cke_reg | drif_cke_reg ^ fbdic_cke_reg_d1 | | |
2702 | fbdic_scr_frame_req_d5) & fbdic_l0_state ? 1'b1 : | |
2703 | fbdic_issue_cke_cmd | ~fbdic_l0_state | fbdic_error_mode ? 1'b0 : fbdic_cke_cmd_pend; | |
2704 | ||
2705 | assign fbdic_issue_cke_cmd = fbdic_cke_cmd_pend & fbdic_config_reg_access_rdy | fbdic_scr_frame_req_d5; | |
2706 | ||
2707 | // Using spare10_flop below | |
2708 | ||
2709 | //msff_ctl_macro ff_cke_cmd_pend ( | |
2710 | // .scan_in(1'b0), | |
2711 | // .scan_out(ff_cke_cmd_pend_scanout), | |
2712 | // .din(fbdic_cke_cmd_pend_in), | |
2713 | // .dout(fbdic_cke_cmd_pend), | |
2714 | // .l1clk(l1clk)); | |
2715 | ||
2716 | mcu_fbdic_ctl_msff_ctl_macro__width_1 ff_cke_reg_d1 ( | |
2717 | .scan_in(ff_cke_reg_d1_scanin), | |
2718 | .scan_out(ff_cke_reg_d1_scanout), | |
2719 | .din(drif_cke_reg), | |
2720 | .dout(fbdic_cke_reg_d1), | |
2721 | .l1clk(l1clk), | |
2722 | .siclk(siclk), | |
2723 | .soclk(soclk)); | |
2724 | ||
2725 | assign fbdic_lower_cke_cmd[23:0] = drif_stacked_dimm ? {16'h01a0, fbdic_per_rank_cke[7:0] & {8{drif_cke_reg}}} : | |
2726 | {16'h01e0, {fbdic_per_rank_cke[14],fbdic_per_rank_cke[12], | |
2727 | fbdic_per_rank_cke[10],fbdic_per_rank_cke[8], | |
2728 | fbdic_per_rank_cke[6], fbdic_per_rank_cke[4], | |
2729 | fbdic_per_rank_cke[2], fbdic_per_rank_cke[0]} & {8{drif_cke_reg}}}; | |
2730 | ||
2731 | assign fbdic_upper_cke_cmd[23:0] = drif_stacked_dimm ? {16'h81a0, fbdic_per_rank_cke[15:8] & {8{drif_cke_reg}}} : 24'h0; | |
2732 | ||
2733 | ///////////////////////////////// | |
2734 | // FBD L0s Duration Register | |
2735 | ///////////////////////////////// | |
2736 | assign fbdic_l0s_time_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8A8; | |
2737 | assign fbdic_l0s_time_in[6:0] = drif_ucb_data[6:0] ^ 7'h2a; | |
2738 | assign fbdic_l0s_time[6:0] = fbdic_l0s_time_out[6:0] ^ 7'h2a; | |
2739 | ||
2740 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_7 pff_l0s_time ( // FS:wmr_protect | |
2741 | .scan_in(pff_l0s_time_wmr_scanin), | |
2742 | .scan_out(pff_l0s_time_wmr_scanout), | |
2743 | .siclk(aclk_wmr), | |
2744 | .din(fbdic_l0s_time_in[6:0]), | |
2745 | .dout(fbdic_l0s_time_out[6:0]), | |
2746 | .en(fbdic_l0s_time_en), | |
2747 | .l1clk(l1clk), | |
2748 | .soclk(soclk)); | |
2749 | ||
2750 | assign fbdic_l0s_enable = fbdic_l0s_time[6]; | |
2751 | assign fbdic_sync_el0s = fbdic_l0s_enable & fbdic_mcu_idle; | |
2752 | ||
2753 | assign fbdic_l0s_stall_in = fbdic_sync_frame_req ? fbdic_sync_el0s : fbdic_l0s_stall; | |
2754 | ||
2755 | assign fbdic_mcu_idle_in = drif_mcu_idle & rdpctl_fifo_empty; | |
2756 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_l0s_stall ( | |
2757 | .scan_in(ff_l0s_stall_scanin), | |
2758 | .scan_out(ff_l0s_stall_scanout), | |
2759 | .din({fbdic_mcu_idle_in,fbdic_l0s_stall_in}), | |
2760 | .dout({fbdic_mcu_idle,fbdic_l0s_stall}), | |
2761 | .l1clk(l1clk), | |
2762 | .siclk(siclk), | |
2763 | .soclk(soclk)); | |
2764 | ||
2765 | assign fbdic_l0s_lfsr_stall = fbdic_l0s_stall | fbdic_idle_lfsr_reset_d1; | |
2766 | ||
2767 | ///////////////////////////////// | |
2768 | // Loopback Mode Control Register | |
2769 | ///////////////////////////////// | |
2770 | assign fbdic_loopback_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8C8; | |
2771 | assign fbdic_loopback_in[1:0] = drif_ucb_data[1:0]; | |
2772 | ||
2773 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_2 ff_loopback ( | |
2774 | .scan_in(ff_loopback_scanin), | |
2775 | .scan_out(ff_loopback_scanout), | |
2776 | .din(fbdic_loopback_in[1:0]), | |
2777 | .dout(fbdic_loopback[1:0]), | |
2778 | .en(fbdic_loopback_en), | |
2779 | .l1clk(l1clk), | |
2780 | .siclk(siclk), | |
2781 | .soclk(soclk)); | |
2782 | ||
2783 | ///////////////////////////////// | |
2784 | // SERDES PLL Status Register - address 8e8 - read only | |
2785 | ///////////////////////////////// | |
2786 | cl_sc1_clksyncff_4x sync_stspll5 ( | |
2787 | .d(fsr1_mcu_stspll_lock[2]), | |
2788 | .q(fbdic_sds_pll_status[5]), | |
2789 | .si(sync_stspll5_scanin), | |
2790 | .so(sync_stspll5_scanout), | |
2791 | .l1clk(l1clk), | |
2792 | .siclk(siclk), | |
2793 | .soclk(soclk)); | |
2794 | ||
2795 | cl_sc1_clksyncff_4x sync_stspll4 ( | |
2796 | .d(fsr1_mcu_stspll_lock[1]), | |
2797 | .q(fbdic_sds_pll_status[4]), | |
2798 | .si(sync_stspll4_scanin), | |
2799 | .so(sync_stspll4_scanout), | |
2800 | .l1clk(l1clk), | |
2801 | .siclk(siclk), | |
2802 | .soclk(soclk)); | |
2803 | ||
2804 | cl_sc1_clksyncff_4x sync_stspll3 ( | |
2805 | .d(fsr1_mcu_stspll_lock[0]), | |
2806 | .q(fbdic_sds_pll_status[3]), | |
2807 | .si(sync_stspll3_scanin), | |
2808 | .so(sync_stspll3_scanout), | |
2809 | .l1clk(l1clk), | |
2810 | .siclk(siclk), | |
2811 | .soclk(soclk)); | |
2812 | ||
2813 | cl_sc1_clksyncff_4x sync_stspll2 ( | |
2814 | .d(fsr0_mcu_stspll_lock[2]), | |
2815 | .q(fbdic_sds_pll_status[2]), | |
2816 | .si(sync_stspll2_scanin), | |
2817 | .so(sync_stspll2_scanout), | |
2818 | .l1clk(l1clk), | |
2819 | .siclk(siclk), | |
2820 | .soclk(soclk)); | |
2821 | ||
2822 | cl_sc1_clksyncff_4x sync_stspll1 ( | |
2823 | .d(fsr0_mcu_stspll_lock[1]), | |
2824 | .q(fbdic_sds_pll_status[1]), | |
2825 | .si(sync_stspll1_scanin), | |
2826 | .so(sync_stspll1_scanout), | |
2827 | .l1clk(l1clk), | |
2828 | .siclk(siclk), | |
2829 | .soclk(soclk)); | |
2830 | ||
2831 | cl_sc1_clksyncff_4x sync_stspll0 ( | |
2832 | .d(fsr0_mcu_stspll_lock[0]), | |
2833 | .q(fbdic_sds_pll_status[0]), | |
2834 | .si(sync_stspll0_scanin), | |
2835 | .so(sync_stspll0_scanout), | |
2836 | .l1clk(l1clk), | |
2837 | .siclk(siclk), | |
2838 | .soclk(soclk)); | |
2839 | ||
2840 | // SERDES Configuration Bus assignments | |
2841 | ||
2842 | assign mcu_fsr01_cfgpll_lb[1:0] = fbdic_sds_config[1:0]; | |
2843 | assign mcu_fsr01_cfgpll_mpy[3:0] = fbdic_sds_config[5:2]; | |
2844 | assign mcu_fsr01_cfgrx_eq[3:0] = fbdic_sds_config[11:8]; | |
2845 | assign mcu_fsr01_cfgrx_cdr[2:0] = fbdic_sds_config[14:12]; | |
2846 | assign mcu_fsr01_cfgrx_term[2:0] = {3{mcu_gnd}}; | |
2847 | assign mcu_fsr01_cfgtx_enftp = fbdic_sds_config[19]; | |
2848 | assign mcu_fsr01_cfgtx_de[3:0] = fbdic_sds_config[23:20]; | |
2849 | assign mcu_fsr01_cfgtx_swing[2:0] = fbdic_sds_config[26:24]; | |
2850 | assign mcu_fsr01_cfgtx_cm = fbdic_sds_config[27]; | |
2851 | assign mcu_fsr01_cfgrtx_rate[1:0] = fbdic_sds_config[29:28]; | |
2852 | ||
2853 | assign mcu_fsr0_cfgpll_enpll = ~drif_branch_disabled; | |
2854 | assign mcu_fsr1_cfgpll_enpll = ~drif_branch_disabled & ~drif_single_channel_mode; | |
2855 | assign mcu_fsr0_cfgrx_enrx = ~drif_branch_disabled; | |
2856 | assign mcu_fsr1_cfgrx_enrx = ~drif_branch_disabled & ~drif_single_channel_mode; | |
2857 | assign mcu_fsr0_cfgtx_entx = ~drif_branch_disabled; | |
2858 | assign mcu_fsr1_cfgtx_entx = ~drif_branch_disabled & ~drif_single_channel_mode; | |
2859 | ||
2860 | // SERDES TX and RX Differential Pair Inversion assignments | |
2861 | assign mcu_fsr0_cfgrx_invpair[13:0] = fbdic_sds_invert[13:0]; | |
2862 | assign mcu_fsr1_cfgrx_invpair[13:0] = fbdic_sds_invert[27:14]; | |
2863 | assign mcu_fsr0_cfgtx_invpair[9:0] = fbdic_sds_invert[37:28]; | |
2864 | assign mcu_fsr1_cfgtx_invpair[9:0] = fbdic_sds_invert[47:38]; | |
2865 | ||
2866 | // Test config bus assignments | |
2867 | assign mcu_fsr0_testcfg[11:0] = {fbdic_sds_testcfg[13:11], mcu_gnd, fbdic_sds_testcfg[7:0]}; | |
2868 | assign mcu_fsr1_testcfg[11:0] = {fbdic_sds_testcfg[27:25], mcu_gnd, fbdic_sds_testcfg[21:14]}; | |
2869 | assign mcu_fsr0_cfgrx_entest = fbdic_sds_testcfg[28]; | |
2870 | assign mcu_fsr1_cfgrx_entest = fbdic_sds_testcfg[29]; | |
2871 | assign mcu_fsr0_cfgtx_entest = fbdic_sds_testcfg[30]; | |
2872 | assign mcu_fsr1_cfgtx_entest = fbdic_sds_testcfg[31]; | |
2873 | ||
2874 | ///////////////////////////////// | |
2875 | // SERDES Test Status Register | |
2876 | ///////////////////////////////// | |
2877 | mcu_fbdic_ctl_msff_ctl_macro__width_20 ff_sds_test_status ( | |
2878 | .scan_in(ff_sds_test_status_scanin), | |
2879 | .scan_out(ff_sds_test_status_scanout), | |
2880 | .din({fsr1_mcu_ststx_testfail[9:0],fsr0_mcu_ststx_testfail[9:0]}), | |
2881 | .dout(fbdic_sds_test_status[47:28]), | |
2882 | .l1clk(l1clk), | |
2883 | .siclk(siclk), | |
2884 | .soclk(soclk)); | |
2885 | ||
2886 | assign fbdic_sds_test_status[27:0] = {fbd1_testfail[13:0],fbd0_testfail[13:0]}; | |
2887 | ||
2888 | ///////////////////////////////// | |
2889 | // Config Register Access Address Register | |
2890 | ///////////////////////////////// | |
2891 | assign fbdic_config_reg_addr_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h900; | |
2892 | assign fbdic_config_reg_addr_in[15:2] = drif_ucb_data[15:2]; | |
2893 | ||
2894 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_14 ff_config_reg_addr ( | |
2895 | .scan_in(ff_config_reg_addr_scanin), | |
2896 | .scan_out(ff_config_reg_addr_scanout), | |
2897 | .din(fbdic_config_reg_addr_in[15:2]), | |
2898 | .dout(fbdic_config_reg_addr[15:2]), | |
2899 | .en(fbdic_config_reg_addr_en), | |
2900 | .l1clk(l1clk), | |
2901 | .siclk(siclk), | |
2902 | .soclk(soclk)); | |
2903 | ||
2904 | ///////////////////////////////// | |
2905 | // Config Register Access Data Register | |
2906 | ///////////////////////////////// | |
2907 | assign fbdic_cnfgreg_wr_pend_in = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h908 ? 1'b1 : | |
2908 | fbdic_config_reg_write | ~fbdic_l0_state | fbdic_error_mode ? 1'b0 : | |
2909 | fbdic_cnfgreg_wr_pend; | |
2910 | ||
2911 | assign fbdic_cnfgreg_rd_pend_in = drif_ucb_rd_req_vld & drif_ucb_addr[12:0] == 13'h908 | | |
2912 | fbdic_cfgrd_crc_error & fbdic_l0_state ? 1'b1 : | |
2913 | fbdic_config_reg_read | ~fbdic_l0_state ? 1'b0 : fbdic_cnfgreg_rd_pend; | |
2914 | ||
2915 | assign fbdic_cfgrd_crc_error = (~(fbdird_crc_cmp0_0 & fbdird_crc_cmp0_1 & fbdird_crc_cmp1_0 & fbdird_crc_cmp1_1) | | |
2916 | fbdic_inj_crc_err) & fbdic_cnfgreg_rddata_vld & ~fbdic_chnl_reset_error_mode; | |
2917 | ||
2918 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_cnfg_access_pending ( | |
2919 | .scan_in(ff_cnfg_access_pending_scanin), | |
2920 | .scan_out(ff_cnfg_access_pending_scanout), | |
2921 | .din({fbdic_cnfgreg_wr_pend_in,fbdic_cnfgreg_rd_pend_in}), | |
2922 | .dout({fbdic_cnfgreg_wr_pend,fbdic_cnfgreg_rd_pend}), | |
2923 | .l1clk(l1clk), | |
2924 | .siclk(siclk), | |
2925 | .soclk(soclk)); | |
2926 | ||
2927 | assign fbdic_cnfgreg_wr_data_in[31:0] = drif_ucb_data[31:0]; | |
2928 | assign fbdic_cnfgreg_wr_data_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h908; | |
2929 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_32 ff_cnfgreg_wr_data ( | |
2930 | .scan_in(ff_cnfgreg_wr_data_scanin), | |
2931 | .scan_out(ff_cnfgreg_wr_data_scanout), | |
2932 | .din(fbdic_cnfgreg_wr_data_in[31:0]), | |
2933 | .dout(fbdic_cnfgreg_wr_data[31:0]), | |
2934 | .en(fbdic_cnfgreg_wr_data_en), | |
2935 | .l1clk(l1clk), | |
2936 | .siclk(siclk), | |
2937 | .soclk(soclk)); | |
2938 | ||
2939 | assign fbdic_config_reg_access_rdy = ~fbdic_sync_frame_req & ~fbdic_sync_frame_req_early1 & ~fbdic_error_mode & | |
2940 | (drif_dram_cmd_a[2:0] == 3'h0) & | |
2941 | (drif_dram_cmd_b[2:0] == 3'h0) & (drif_dram_cmd_c[2:0] == 3'h0) & | |
2942 | (fbdic_sync_sd[1:0] == 2'h0); | |
2943 | assign fbdic_config_reg_read = fbdic_cnfgreg_rd_pend & (fbdic_config_reg_access_rdy | ~fbdic_l0_state); | |
2944 | assign fbdic_config_reg_write = fbdic_cnfgreg_wr_pend & fbdic_config_reg_access_rdy; | |
2945 | ||
2946 | mcu_fbdic_ctl_msff_ctl_macro ff_config_reg_write_d1 ( | |
2947 | .scan_in(ff_config_reg_write_d1_scanin), | |
2948 | .scan_out(ff_config_reg_write_d1_scanout), | |
2949 | .din(fbdic_config_reg_write), | |
2950 | .dout(fbdic_config_reg_write_d1), | |
2951 | .l1clk(l1clk), | |
2952 | .siclk(siclk), | |
2953 | .soclk(soclk)); | |
2954 | ||
2955 | // Only send write data to one channel | |
2956 | assign fbdic0_chnl_disable = fbdic_config_reg_write_d1 & fbdic_config_reg_addr[15]; | |
2957 | assign fbdic1_chnl_disable = fbdic_config_reg_write_d1 & ~fbdic_config_reg_addr[15]; | |
2958 | ||
2959 | ///////////////////////////////// | |
2960 | // AMB Thermal Trip Register - address 0xa00 - read only | |
2961 | ///////////////////////////////// | |
2962 | assign fbdic_thermal_trip_in[47:0] = {lndskw1_thermal_trip[23:0],lndskw0_thermal_trip[23:0]}; | |
2963 | assign fbdic_thermal_trip_en = fbdic_status_frame & ~fbdic_status_parity_error_en; | |
2964 | ||
2965 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_48 ff_thermal_trip ( | |
2966 | .scan_in(ff_thermal_trip_scanin), | |
2967 | .scan_out(ff_thermal_trip_scanout), | |
2968 | .din(fbdic_thermal_trip_in[47:0]), | |
2969 | .dout(fbdic_thermal_trip[47:0]), | |
2970 | .en(fbdic_thermal_trip_en), | |
2971 | .l1clk(l1clk), | |
2972 | .siclk(siclk), | |
2973 | .soclk(soclk)); | |
2974 | ||
2975 | ///////////////////////////////// | |
2976 | // MCU Syndrome Register (FBD error status register) | |
2977 | ///////////////////////////////// | |
2978 | assign fbdic_mcu_syndrome_en = (fbdic_err_recov | rdpctl_crc_recov_err) & ~fbdic_mcu_syndrome[30] | | |
2979 | (fbdic_err_unrecov | rdpctl_crc_unrecov_err) & ~fbdic_fbu_error | | |
2980 | fbdic_err_recov & fbdic_aa & ~fbdic_mcu_synd_aa | | |
2981 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hC00; | |
2982 | assign fbdic_mcu_syndrome_in[30:0] = (fbdic_err_recov | rdpctl_crc_recov_err) & ~fbdic_mcu_syndrome[30] | | |
2983 | (fbdic_err_unrecov | rdpctl_crc_unrecov_err) & ~fbdic_fbu_error ? | |
2984 | {1'b1, // valid | |
2985 | fbdic1_chnl_alert[11:0], | |
2986 | fbdic0_chnl_alert[11:0], | |
2987 | fbdic_scr, | |
2988 | fbdic_fr, | |
2989 | fbdic_spe, | |
2990 | fbdic_aa, | |
2991 | fbdic_af, | |
2992 | rdpctl_crc_recov_err | rdpctl_crc_unrecov_err} : | |
2993 | fbdic_err_recov & fbdic_aa & ~fbdic_mcu_synd_aa ? | |
2994 | {fbdic_mcu_syndrome[30], | |
2995 | fbdic1_chnl_alert[11:0], | |
2996 | fbdic0_chnl_alert[11:0], | |
2997 | fbdic_mcu_syndrome[5:3], 1'b1, // AA | |
2998 | fbdic_mcu_syndrome[1:0]} : | |
2999 | {drif_ucb_data[63],drif_ucb_data[29:0]}; | |
3000 | ||
3001 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_31 pff_mcu_syndrome ( // FS:wmr_protect | |
3002 | .scan_in(pff_mcu_syndrome_wmr_scanin), | |
3003 | .scan_out(pff_mcu_syndrome_wmr_scanout), | |
3004 | .siclk(aclk_wmr), | |
3005 | .din(fbdic_mcu_syndrome_in[30:0]), | |
3006 | .dout(fbdic_mcu_syndrome[30:0]), | |
3007 | .en(fbdic_mcu_syndrome_en), | |
3008 | .l1clk(l1clk), | |
3009 | .soclk(soclk)); | |
3010 | ||
3011 | assign fbdic_mcu_synd_valid = fbdic_mcu_syndrome[30]; | |
3012 | assign fbdic_mcu_synd_fr = fbdic_mcu_syndrome[4]; | |
3013 | assign fbdic_mcu_synd_aa = fbdic_mcu_syndrome[2]; | |
3014 | ||
3015 | assign fbdic_fbu_error_in = fbdic_err_unrecov | rdpctl_crc_unrecov_err ? 1'b1 : | |
3016 | ~fbdic_mcu_syndrome[30] ? 1'b0 : fbdic_fbu_error; | |
3017 | mcu_fbdic_ctl_msff_ctl_macro ff_fbu_error ( | |
3018 | .scan_in(ff_fbu_error_scanin), | |
3019 | .scan_out(ff_fbu_error_scanout), | |
3020 | .din(fbdic_fbu_error_in), | |
3021 | .dout(fbdic_fbu_error), | |
3022 | .l1clk(l1clk), | |
3023 | .siclk(siclk), | |
3024 | .soclk(soclk)); | |
3025 | ||
3026 | ///////////////////////////////// | |
3027 | // Injected Error Source Register | |
3028 | ///////////////////////////////// | |
3029 | // 00: CRC, 01: alert frame, 10: alert asserted, 11: status frame parity | |
3030 | ||
3031 | assign fbdic_inj_err_src_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hC08; | |
3032 | assign fbdic_inj_err_src_in[1:0] = drif_ucb_data[1:0]; | |
3033 | ||
3034 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_2 pff_inj_err_src ( // FS:wmr_protect | |
3035 | .scan_in(pff_inj_err_src_wmr_scanin), | |
3036 | .scan_out(pff_inj_err_src_wmr_scanout), | |
3037 | .siclk(aclk_wmr), | |
3038 | .din(fbdic_inj_err_src_in[1:0]), | |
3039 | .dout(fbdic_inj_err_src[1:0]), | |
3040 | .en(fbdic_inj_err_src_en), | |
3041 | .l1clk(l1clk), | |
3042 | .soclk(soclk)); | |
3043 | ||
3044 | ///////////////////////////////// | |
3045 | // MCU FBR Count Register | |
3046 | ///////////////////////////////// | |
3047 | assign fbdic_fbr_count_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hC10 | | |
3048 | (rdpctl_crc_recov_err | fbdic_err_recov) & ~fbdic_fbr_count[16]; | |
3049 | assign fbdic_fbr_count_in[16] = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hC10 ? drif_ucb_data[16] : | |
3050 | fbdic_fbr_count[16]; | |
3051 | assign fbdic_fbr_count_in[15:0] = (rdpctl_crc_recov_err | fbdic_err_recov) & ~fbdic_fbr_count[16] ? | |
3052 | ((fbdic_fbr_count[15:0] == 16'h0) ? 16'h0 : fbdic_fbr_count[15:0] - 16'h1) : | |
3053 | drif_ucb_data[15:0]; | |
3054 | ||
3055 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_17 pff_fbr_count ( // FS:wmr_protect | |
3056 | .scan_in(pff_fbr_count_wmr_scanin), | |
3057 | .scan_out(pff_fbr_count_wmr_scanout), | |
3058 | .siclk(aclk_wmr), | |
3059 | .din(fbdic_fbr_count_in[16:0]), | |
3060 | .dout(fbdic_fbr_count[16:0]), | |
3061 | .en(fbdic_fbr_count_en), | |
3062 | .l1clk(l1clk), | |
3063 | .soclk(soclk)); | |
3064 | ||
3065 | assign fbdic_err_fbr_in = (rdpctl_crc_recov_err | fbdic_err_recov) & | |
3066 | (fbdic_fbr_count[16] | fbdic_fbr_count[15:0] == 16'h1); | |
3067 | mcu_fbdic_ctl_msff_ctl_macro ff_err_fbr ( | |
3068 | .scan_in(ff_err_fbr_scanin), | |
3069 | .scan_out(ff_err_fbr_scanout), | |
3070 | .din(fbdic_err_fbr_in), | |
3071 | .dout(fbdic_err_fbr), | |
3072 | .l1clk(l1clk), | |
3073 | .siclk(siclk), | |
3074 | .soclk(soclk)); | |
3075 | ||
3076 | ////////////////////////////////////////////////////////////////// | |
3077 | ||
3078 | mcu_fbdic_ctl_msff_ctl_macro__width_24 ff_ts_data ( | |
3079 | .scan_in(ff_ts_data_scanin), | |
3080 | .scan_out(ff_ts_data_scanout), | |
3081 | .din({fbdic0_ts_data_in[11:0],fbdic1_ts_data_in[11:0]}), | |
3082 | .dout({fbdic0_ts_data[11:0],fbdic1_ts_data[11:0]}), | |
3083 | .l1clk(l1clk), | |
3084 | .siclk(siclk), | |
3085 | .soclk(soclk)); | |
3086 | ||
3087 | //assign fbdic_ts_data[119:0] = fbdic_ibist_data_mode | fbdic_txstart ? ibist_txdata[119:0] : {10{fbdic_ts_data_1bit[11:0]}}; | |
3088 | assign fbdic_ibist_data[119:0] = ibist_txdata[119:0]; | |
3089 | ||
3090 | assign init_state[7:0] = {fbdic_fbd_state[2:0] == 3'h7, | |
3091 | fbdic_fbd_state[2:0] == 3'h6, | |
3092 | fbdic_fbd_state[2:0] == 3'h5, | |
3093 | fbdic_fbd_state[2:0] == 3'h4, | |
3094 | fbdic_fbd_state[2:0] == 3'h3, | |
3095 | fbdic_fbd_state[2:0] == 3'h2, | |
3096 | fbdic_fbd_state[2:0] == 3'h1, | |
3097 | fbdic_fbd_state[2:0] == 3'h0}; | |
3098 | ||
3099 | assign amb_id[3:0] = fbdic_fbd_state[6:3]; | |
3100 | ||
3101 | // mask for checking errors from status frames | |
3102 | assign fbdic_amb_mask[11:0] = amb_id[3:0] == 4'h1 ? 12'h003 : | |
3103 | amb_id[3:0] == 4'h2 ? 12'h007 : | |
3104 | amb_id[3:0] == 4'h3 ? 12'h00f : | |
3105 | amb_id[3:0] == 4'h4 ? 12'h01f : | |
3106 | amb_id[3:0] == 4'h5 ? 12'h03f : | |
3107 | amb_id[3:0] == 4'h6 ? 12'h07f : | |
3108 | amb_id[3:0] == 4'h7 ? 12'h0ff : | |
3109 | amb_id[3:0] == 4'h8 ? 12'h1ff : | |
3110 | amb_id[3:0] == 4'h9 ? 12'h3ff : | |
3111 | amb_id[3:0] == 4'ha ? 12'h7ff : | |
3112 | amb_id[3:0] == 4'hb ? 12'hfff : 12'h001; | |
3113 | ||
3114 | ||
3115 | assign fbdic_l0_state_in = (fbdic_fbd_state[2:1] == 2'h3) & ~ts3_cnt_en & fbdic_l0_state_dly[2:0] == 3'h0; | |
3116 | ||
3117 | mcu_fbdic_ctl_msff_ctl_macro ff_l0_state ( | |
3118 | .scan_in(ff_l0_state_scanin), | |
3119 | .scan_out(ff_l0_state_scanout), | |
3120 | .din(fbdic_l0_state_in), | |
3121 | .dout(fbdic_l0_state), | |
3122 | .l1clk(l1clk), | |
3123 | .siclk(siclk), | |
3124 | .soclk(soclk)); | |
3125 | ||
3126 | assign fbdic_l0_state_dly_in[2:0] = (fbdic_fbd_state[2:0] == 3'h5) ? 3'h7 : | |
3127 | (fbdic_fbd_state[2:1] == 2'h3) & ~ts3_cnt_en & (fbdic_l0_state_dly[2:0] != 3'h0) ? | |
3128 | fbdic_l0_state_dly[2:0] - 3'h1 : fbdic_l0_state_dly[2:0]; | |
3129 | ||
3130 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_l0_state_dly ( | |
3131 | .scan_in(ff_l0_state_dly_scanin), | |
3132 | .scan_out(ff_l0_state_dly_scanout), | |
3133 | .din(fbdic_l0_state_dly_in[2:0]), | |
3134 | .dout(fbdic_l0_state_dly[2:0]), | |
3135 | .l1clk(l1clk), | |
3136 | .siclk(siclk), | |
3137 | .soclk(soclk)); | |
3138 | ||
3139 | assign fbdic_ts_data_in[11:0] = {12{init_state[1]}} | | |
3140 | {12{ts0_cnt_en}} & ts0_data[11:0] | {12{ts1_cnt_en}} & ts1_data[11:0] | | |
3141 | {12{ts2_cnt_en}} & ts2_data[11:0]; | |
3142 | ||
3143 | assign fbdic0_ts_data_in[11:0] = fbdic_ts_data_in[11:0] | {12{ts3_cnt_en}} & ts3_data0[11:0]; | |
3144 | assign fbdic1_ts_data_in[11:0] = {12{~drif_single_channel_mode}} & | |
3145 | (fbdic_ts_data_in[11:0] | {12{ts3_cnt_en}} & ts3_data1[11:0]); | |
3146 | ||
3147 | // TS0 patterns | |
3148 | assign ts0_cnt_in[3:0] = ts0_cnt[3:0] == 4'hb ? 4'h0 : ts0_cnt[3:0] + 4'h1; | |
3149 | assign ts0_cnt_en = init_state[2] | (|ts0_cnt[3:0]); | |
3150 | ||
3151 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_4 ff_ts0_cnt ( | |
3152 | .scan_in(ff_ts0_cnt_scanin), | |
3153 | .scan_out(ff_ts0_cnt_scanout), | |
3154 | .din(ts0_cnt_in[3:0]), | |
3155 | .dout(ts0_cnt[3:0]), | |
3156 | .en(ts0_cnt_en), | |
3157 | .l1clk(l1clk), | |
3158 | .siclk(siclk), | |
3159 | .soclk(soclk)); | |
3160 | ||
3161 | assign ts0_data[11:0] = (ts0_cnt[3:0] == 4'h0) ? `FBD_TS0_HDR : | |
3162 | (ts0_cnt[3:0] == 4'h1) ? {amb_id[3],1'b0,amb_id[2],1'b0,amb_id[1],1'b0,amb_id[0],5'h0a} : 12'haaa; | |
3163 | ||
3164 | assign fbdic_train_state = ts0_cnt_en; | |
3165 | ||
3166 | // TS1 patterns | |
3167 | assign ts1_cnt_in[5:0] = ts1_cnt[5:0] == 6'h7 ? 6'h0 : ts1_cnt[5:0] + 6'h1; | |
3168 | assign ts1_cnt_en = init_state[3] & ~ts0_cnt_en | (|ts1_cnt[5:0]); | |
3169 | ||
3170 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_6 ff_ts1_cnt ( | |
3171 | .scan_in(ff_ts1_cnt_scanin), | |
3172 | .scan_out(ff_ts1_cnt_scanout), | |
3173 | .din(ts1_cnt_in[5:0]), | |
3174 | .dout(ts1_cnt[5:0]), | |
3175 | .en(ts1_cnt_en), | |
3176 | .l1clk(l1clk), | |
3177 | .siclk(siclk), | |
3178 | .soclk(soclk)); | |
3179 | ||
3180 | assign ts1_data[11:0] = (ts1_cnt[5:0] == 6'h0) ? `FBD_TS1_HDR : | |
3181 | (ts1_cnt[5:0] == 6'h1) ? {5'h0, fbdic_sb2nb_map[2:0], 4'hf} : | |
3182 | (ts1_cnt[5:0] == 6'h2) ? fbdic_amb_test_param[23:12] : | |
3183 | (ts1_cnt[5:0] == 6'h3) ? fbdic_amb_test_param[11:0] : | |
3184 | (ts1_cnt[5:0] == 6'h4) ? 12'h678 : | |
3185 | (ts1_cnt[5:0] == 6'h5) ? 12'h345 : | |
3186 | (ts1_cnt[5:0] == 6'h6) ? 12'h678 : | |
3187 | (ts1_cnt[5:0] == 6'h7) ? 12'h345 : 12'h0; | |
3188 | ||
3189 | // TS2 patterns | |
3190 | assign ts2_cnt_in[2:0] = ts2_cnt[2:0] == 3'h5 ? 3'h0 : ts2_cnt[2:0] + 3'h1; | |
3191 | assign ts2_cnt_en = init_state[4] & ~ts1_cnt_en | (|ts2_cnt[2:0]); | |
3192 | ||
3193 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_3 ff_ts2_cnt ( | |
3194 | .scan_in(ff_ts2_cnt_scanin), | |
3195 | .scan_out(ff_ts2_cnt_scanout), | |
3196 | .din(ts2_cnt_in[2:0]), | |
3197 | .dout(ts2_cnt[2:0]), | |
3198 | .en(ts2_cnt_en), | |
3199 | .l1clk(l1clk), | |
3200 | .siclk(siclk), | |
3201 | .soclk(soclk)); | |
3202 | ||
3203 | assign ts2_data[11:0] = (ts2_cnt[2:0] == 3'h0) ? `FBD_TS2_HDR : | |
3204 | (ts2_cnt[2:0] == 3'h1) ? {6'h00, fbdic_fbd_state[7], 1'b0, amb_id[3:0]} : | |
3205 | (ts2_cnt[2:0] == 3'h2) ? {8'h00, ts2_seq_id[3:0]} : 12'haaa; | |
3206 | ||
3207 | assign ts2_seq_id_in[3:0] = ts2_seq_id[3:0] + 4'h1; | |
3208 | assign ts2_seq_id_en = (ts2_cnt[2:0] == 3'h2); | |
3209 | assign ts2_seq_id_clr = ~ts2_cnt_en; | |
3210 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_4 ff_ts2_seq_id ( | |
3211 | .scan_in(ff_ts2_seq_id_scanin), | |
3212 | .scan_out(ff_ts2_seq_id_scanout), | |
3213 | .din(ts2_seq_id_in[3:0]), | |
3214 | .dout(ts2_seq_id[3:0]), | |
3215 | .en(ts2_seq_id_en), | |
3216 | .clr(ts2_seq_id_clr), | |
3217 | .l1clk(l1clk), | |
3218 | .siclk(siclk), | |
3219 | .soclk(soclk)); | |
3220 | ||
3221 | // TS3 patterns | |
3222 | assign ts3_cnt_in[2:0] = ts3_cnt[2:0] == 3'h5 ? 3'h0 : ts3_cnt[2:0] + 3'h1; | |
3223 | assign ts3_cnt_en = init_state[5] & ~ts2_cnt_en | (|ts3_cnt[2:0]); | |
3224 | ||
3225 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_3 ff_ts3_cnt ( | |
3226 | .scan_in(ff_ts3_cnt_scanin), | |
3227 | .scan_out(ff_ts3_cnt_scanout), | |
3228 | .din(ts3_cnt_in[2:0]), | |
3229 | .dout(ts3_cnt[2:0]), | |
3230 | .en(ts3_cnt_en), | |
3231 | .l1clk(l1clk), | |
3232 | .siclk(siclk), | |
3233 | .soclk(soclk)); | |
3234 | ||
3235 | assign ts3_data0[11:0] = (ts3_cnt[2:0] == 3'h0) ? `FBD_TS3_HDR : | |
3236 | (ts3_cnt[2:0] == 3'h1) ? {3'h0, 4'h3, 1'b0, 4'hf} : | |
3237 | (ts3_cnt[2:0] == 3'h2) ? {2'h1,fbdic_failover_config[3:0], | |
3238 | 2'h0,fbdic_failover_config[7:4]} : 12'haaa; | |
3239 | assign ts3_data1[11:0] = (ts3_cnt[2:0] == 3'h0) ? `FBD_TS3_HDR : | |
3240 | (ts3_cnt[2:0] == 3'h1) ? {3'h0, 4'h3, 1'b0, 4'hf} : | |
3241 | (ts3_cnt[2:0] == 3'h2) ? {2'h1,fbdic_failover_config[11:8], | |
3242 | 2'h0,fbdic_failover_config[15:12]} : 12'haaa; | |
3243 | ///////////////////// | |
3244 | // Northbound data | |
3245 | ///////////////////// | |
3246 | ||
3247 | assign fbdic0_nb_data[11:0] = lndskw0_data[11:0]; | |
3248 | assign fbdic1_nb_data[11:0] = lndskw1_data[11:0]; | |
3249 | ||
3250 | assign fbdic_sequence_en[3:0] = {fbdic0_nb_data[11:0] == `FBD_TS3_HDR, | |
3251 | fbdic0_nb_data[11:0] == `FBD_TS2_HDR, | |
3252 | fbdic0_nb_data[11:0] == `FBD_TS1_HDR, | |
3253 | fbdic0_nb_data[11:0] == `FBD_TS0_HDR}; | |
3254 | ||
3255 | assign fbdic_sequence_in[1:0] = fbdic_sequence_en[0] ? 2'h0 : | |
3256 | fbdic_sequence_en[1] ? 2'h1 : | |
3257 | fbdic_sequence_en[2] ? 2'h2 : | |
3258 | fbdic_sequence_en[3] ? 2'h3 : fbdic_sequence[1:0]; | |
3259 | ||
3260 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_sequence ( | |
3261 | .scan_in(ff_sequence_scanin), | |
3262 | .scan_out(ff_sequence_scanout), | |
3263 | .din(fbdic_sequence_in[1:0]), | |
3264 | .dout(fbdic_sequence[1:0]), | |
3265 | .l1clk(l1clk), | |
3266 | .siclk(siclk), | |
3267 | .soclk(soclk)); | |
3268 | ||
3269 | assign fbdic0_ts_exp_data_in[11:0] = (fbdic_fbd_state[2:0] == 3'h2) ? fbdic0_ts0_exp_in[11:0] : | |
3270 | (fbdic_fbd_state[2:0] == 3'h3) ? fbdic0_ts1_exp_in[11:0] : | |
3271 | (fbdic_fbd_state[2:0] == 3'h4) ? fbdic0_ts2_exp_in[11:0] : | |
3272 | (fbdic_fbd_state[2:0] == 3'h5) ? fbdic0_ts3_exp_in[11:0] : 12'h0; | |
3273 | assign fbdic1_ts_exp_data_in[11:0] = (fbdic_fbd_state[2:0] == 3'h2) ? fbdic1_ts0_exp_in[11:0] : | |
3274 | (fbdic_fbd_state[2:0] == 3'h3) ? fbdic1_ts1_exp_in[11:0] : | |
3275 | (fbdic_fbd_state[2:0] == 3'h4) ? fbdic1_ts2_exp_in[11:0] : | |
3276 | (fbdic_fbd_state[2:0] == 3'h5) ? fbdic1_ts3_exp_in[11:0] : 12'h0; | |
3277 | ||
3278 | mcu_fbdic_ctl_msff_ctl_macro__width_24 ff_ts_exp_data ( | |
3279 | .scan_in(ff_ts_exp_data_scanin), | |
3280 | .scan_out(ff_ts_exp_data_scanout), | |
3281 | .din({fbdic0_ts_exp_data_in[11:0],fbdic1_ts_exp_data_in[11:0]}), | |
3282 | .dout({fbdic0_ts_exp_data[11:0],fbdic1_ts_exp_data[11:0]}), | |
3283 | .l1clk(l1clk), | |
3284 | .siclk(siclk), | |
3285 | .soclk(soclk)); | |
3286 | ||
3287 | // Channel 0 expected TS data | |
3288 | assign fbdic0_ts0_exp_in[11:0] = fbdic0_nb_ts_cnt[5:0] == 6'h0 ? {amb_id[3],1'b0,amb_id[2],1'b0, | |
3289 | amb_id[1],1'b0,amb_id[0],5'h0a} : | |
3290 | fbdic0_nb_ts_cnt[5:0] == 6'hb ? `FBD_TS0_HDR : 12'haaa; | |
3291 | ||
3292 | assign fbdic0_ts1_exp_in[11:0] = (fbdic0_nb_ts_cnt[5:0] == 6'h7) ? `FBD_TS1_HDR : | |
3293 | (fbdic0_nb_ts_cnt[5:0] == 6'h0) ? {5'h0, fbdic_sb2nb_map[2:0], amb_id[3:0]} : | |
3294 | (fbdic0_nb_ts_cnt[5:0] == 6'h1) ? fbdic_amb_test_param[23:12] : | |
3295 | (fbdic0_nb_ts_cnt[5:0] == 6'h2) ? fbdic_amb_test_param[11:0] : | |
3296 | (fbdic0_nb_ts_cnt[5:0] == 6'h3) ? 12'h678 : | |
3297 | (fbdic0_nb_ts_cnt[5:0] == 6'h4) ? 12'h345 : | |
3298 | (fbdic0_nb_ts_cnt[5:0] == 6'h5) ? 12'h678 : | |
3299 | (fbdic0_nb_ts_cnt[5:0] == 6'h6) ? 12'h345 : 12'h0; | |
3300 | ||
3301 | assign fbdic0_ts2_exp_in[11:0] = (fbdic0_nb_ts_cnt[5:0] == 6'h5) ? `FBD_TS2_HDR : | |
3302 | (fbdic0_nb_ts_cnt[5:0] == 6'h0) ? {6'h00, fbdic_fbd_state[7], 1'b0, amb_id[3:0]} : | |
3303 | (fbdic0_nb_ts_cnt[5:0] == 6'h1) ? {2'h0,fbdic_ch0_cap_reg[4:0], | |
3304 | 1'b0,fbdic0_nb_ts2_seq_id[3:0]} : 12'haaa; | |
3305 | ||
3306 | assign fbdic0_ts3_exp_in[11:0] = (fbdic0_nb_ts_cnt[5:0] == 6'h5) ? `FBD_TS3_HDR : | |
3307 | (fbdic0_nb_ts_cnt[5:0] == 6'h0) ? {3'h0, 4'h0, 1'b0, amb_id[3:0]} : | |
3308 | (fbdic0_nb_ts_cnt[5:0] == 6'h1) ? {2'h1,fbdic_failover_config[3:0], | |
3309 | 2'h0,fbdic_failover_config[7:4]} : 12'haaa; | |
3310 | ||
3311 | assign fbdic0_nb_ts2_seq_id_in[3:0] = fbdic0_nb_ts2_seq_id[3:0] + 4'h1; | |
3312 | assign fbdic0_nb_ts2_seq_id_en = (fbdic_sequence[1:0] == 2'h2) & (fbdic0_nb_ts_cnt[5:0] == 6'h2); | |
3313 | assign fbdic0_nb_ts2_seq_id_clr = (fbdic_sequence[1:0] != 2'h2); | |
3314 | ||
3315 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_4 ff_nb_ts2_seq_id0 ( | |
3316 | .scan_in(ff_nb_ts2_seq_id0_scanin), | |
3317 | .scan_out(ff_nb_ts2_seq_id0_scanout), | |
3318 | .din(fbdic0_nb_ts2_seq_id_in[3:0]), | |
3319 | .dout(fbdic0_nb_ts2_seq_id[3:0]), | |
3320 | .en(fbdic0_nb_ts2_seq_id_en), | |
3321 | .clr(fbdic0_nb_ts2_seq_id_clr), | |
3322 | .l1clk(l1clk), | |
3323 | .siclk(siclk), | |
3324 | .soclk(soclk)); | |
3325 | ||
3326 | assign fbdic0_hdr_match = (fbdic0_nb_data[11:0] == `FBD_TS0_HDR) & (fbdic_fbd_state[2:0] == 3'h2) | | |
3327 | (fbdic0_nb_data[11:0] == `FBD_TS1_HDR) & (fbdic_fbd_state[2:0] == 3'h3) | | |
3328 | (fbdic0_nb_data[11:0] == `FBD_TS2_HDR) & (fbdic_fbd_state[2:0] == 3'h4) | | |
3329 | (fbdic0_nb_data[11:0] == `FBD_TS3_HDR) & (fbdic_fbd_state[2:0] == 3'h5); | |
3330 | ||
3331 | assign fbdic0_nb_ts_cnt_in[5:0] = fbdic0_hdr_match ? 6'h1 : | |
3332 | fbdic_fbd_state[2:0] == 3'h2 & fbdic0_nb_ts_cnt[5:0] == 6'hb | | |
3333 | fbdic_fbd_state[2:0] == 3'h3 & fbdic0_nb_ts_cnt[5:0] == 6'h7 | | |
3334 | fbdic_fbd_state[2:0] == 3'h4 & fbdic0_nb_ts_cnt[5:0] == 6'h5 | | |
3335 | fbdic_fbd_state[2:0] == 3'h5 & fbdic0_nb_ts_cnt[5:0] == 6'h5 ? 6'h0 : | |
3336 | fbdic0_nb_ts_cnt[5:0] + 6'h1; | |
3337 | ||
3338 | assign fbdic0_nb_ts_cnt_en = fbdic_fbd_state[2:1] == 2'h1 | fbdic_fbd_state[2:1] == 2'h2; | |
3339 | ||
3340 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_6 ff_nb_ts_cnt0 ( | |
3341 | .scan_in(ff_nb_ts_cnt0_scanin), | |
3342 | .scan_out(ff_nb_ts_cnt0_scanout), | |
3343 | .din(fbdic0_nb_ts_cnt_in[5:0]), | |
3344 | .dout(fbdic0_nb_ts_cnt[5:0]), | |
3345 | .en(fbdic0_nb_ts_cnt_en), | |
3346 | .l1clk(l1clk), | |
3347 | .siclk(siclk), | |
3348 | .soclk(soclk)); | |
3349 | ||
3350 | // Counting sequence matches for channel 0 | |
3351 | ||
3352 | // check that at least two lanes match expected data | |
3353 | assign fbdic0_lane0_match = fbdic0_ts_exp_data[11:0] == lndskw0_data[35:24]; | |
3354 | assign fbdic0_lane1_match = fbdic0_ts_exp_data[11:0] == lndskw0_data[23:12]; | |
3355 | assign fbdic0_lane2_match = fbdic0_ts_exp_data[11:0] == lndskw0_data[11:0]; | |
3356 | ||
3357 | assign fbdic0_ts_match_in = (fbdic0_nb_ts_cnt[5:0] == 6'h0) | (fbdic0_lane0_match & fbdic0_lane1_match | | |
3358 | fbdic0_lane0_match & fbdic0_lane2_match | fbdic0_lane1_match & fbdic0_lane2_match) & | |
3359 | fbdic0_ts_match; | |
3360 | ||
3361 | mcu_fbdic_ctl_msff_ctl_macro ff_ts_match0 ( | |
3362 | .scan_in(ff_ts_match0_scanin), | |
3363 | .scan_out(ff_ts_match0_scanout), | |
3364 | .din(fbdic0_ts_match_in), | |
3365 | .dout(fbdic0_ts_match), | |
3366 | .l1clk(l1clk), | |
3367 | .siclk(siclk), | |
3368 | .soclk(soclk)); | |
3369 | ||
3370 | assign fbdic0_ts_match_cnt_in[3:0] = | |
3371 | (fbdic0_nb_ts_cnt[5:0] == 6'h0 & ~fbdic0_ts_match) ? 4'h0 : | |
3372 | (fbdic0_nb_ts_cnt[5:0] == 6'h0 & fbdic0_ts_match & fbdic0_ts_match_cnt[3:0] != 4'hf) ? | |
3373 | fbdic0_ts_match_cnt[3:0] + 4'h1 : fbdic0_ts_match_cnt[3:0]; | |
3374 | ||
3375 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__width_4 ff_ts_match0_cnt ( | |
3376 | .scan_in(ff_ts_match0_cnt_scanin), | |
3377 | .scan_out(ff_ts_match0_cnt_scanout), | |
3378 | .din(fbdic0_ts_match_cnt_in[3:0]), | |
3379 | .dout(fbdic0_ts_match_cnt[3:0]), | |
3380 | .clr(fbdic_fbd_state_en), | |
3381 | .l1clk(l1clk), | |
3382 | .siclk(siclk), | |
3383 | .soclk(soclk)); | |
3384 | ||
3385 | // Channel 1 expected TS data | |
3386 | assign fbdic1_ts0_exp_in[11:0] = fbdic1_nb_ts_cnt[5:0] == 6'h0 ? {amb_id[3],1'b0,amb_id[2],1'b0, | |
3387 | amb_id[1],1'b0,amb_id[0],5'h0a} : | |
3388 | fbdic1_nb_ts_cnt[5:0] == 6'hb ? `FBD_TS0_HDR : 12'haaa; | |
3389 | ||
3390 | assign fbdic1_ts1_exp_in[11:0] = (fbdic1_nb_ts_cnt[5:0] == 6'h7) ? `FBD_TS1_HDR : | |
3391 | (fbdic1_nb_ts_cnt[5:0] == 6'h0) ? {5'h0, fbdic_sb2nb_map[2:0], amb_id[3:0]} : | |
3392 | (fbdic1_nb_ts_cnt[5:0] == 6'h1) ? fbdic_amb_test_param[23:12] : | |
3393 | (fbdic1_nb_ts_cnt[5:0] == 6'h2) ? fbdic_amb_test_param[11:0] : | |
3394 | (fbdic1_nb_ts_cnt[5:0] == 6'h3) ? 12'h678 : | |
3395 | (fbdic1_nb_ts_cnt[5:0] == 6'h4) ? 12'h345 : | |
3396 | (fbdic1_nb_ts_cnt[5:0] == 6'h5) ? 12'h678 : | |
3397 | (fbdic1_nb_ts_cnt[5:0] == 6'h6) ? 12'h345 : 12'h0; | |
3398 | ||
3399 | assign fbdic1_ts2_exp_in[11:0] = (fbdic1_nb_ts_cnt[5:0] == 6'h5) ? `FBD_TS2_HDR : | |
3400 | (fbdic1_nb_ts_cnt[5:0] == 6'h0) ? {6'h00, fbdic_fbd_state[7], 1'b0, amb_id[3:0]} : | |
3401 | (fbdic1_nb_ts_cnt[5:0] == 6'h1) ? {2'h0,fbdic_ch1_cap_reg[4:0], | |
3402 | 1'b0,fbdic1_nb_ts2_seq_id[3:0]} : 12'haaa; | |
3403 | ||
3404 | assign fbdic1_ts3_exp_in[11:0] = (fbdic1_nb_ts_cnt[5:0] == 6'h5) ? `FBD_TS3_HDR : | |
3405 | (fbdic1_nb_ts_cnt[5:0] == 6'h0) ? {3'h0, 4'h0, 1'b0, amb_id[3:0]} : | |
3406 | (fbdic1_nb_ts_cnt[5:0] == 6'h1) ? {2'h1,fbdic_failover_config[11:8], | |
3407 | 2'h0,fbdic_failover_config[15:12]} : 12'haaa; | |
3408 | ||
3409 | assign fbdic1_nb_ts2_seq_id_in[3:0] = fbdic1_nb_ts2_seq_id[3:0] + 4'h1; | |
3410 | assign fbdic1_nb_ts2_seq_id_en = (fbdic_sequence[1:0] == 2'h2) & (fbdic1_nb_ts_cnt[5:0] == 6'h2); | |
3411 | assign fbdic1_nb_ts2_seq_id_clr = (fbdic_sequence[1:0] != 2'h2); | |
3412 | ||
3413 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_4 ff_nb_ts2_seq_id1 ( | |
3414 | .scan_in(ff_nb_ts2_seq_id1_scanin), | |
3415 | .scan_out(ff_nb_ts2_seq_id1_scanout), | |
3416 | .din(fbdic1_nb_ts2_seq_id_in[3:0]), | |
3417 | .dout(fbdic1_nb_ts2_seq_id[3:0]), | |
3418 | .en(fbdic1_nb_ts2_seq_id_en), | |
3419 | .clr(fbdic1_nb_ts2_seq_id_clr), | |
3420 | .l1clk(l1clk), | |
3421 | .siclk(siclk), | |
3422 | .soclk(soclk)); | |
3423 | ||
3424 | assign fbdic1_hdr_match = (fbdic1_nb_data[11:0] == `FBD_TS0_HDR) & (fbdic_fbd_state[2:0] == 3'h2) | | |
3425 | (fbdic1_nb_data[11:0] == `FBD_TS1_HDR) & (fbdic_fbd_state[2:0] == 3'h3) | | |
3426 | (fbdic1_nb_data[11:0] == `FBD_TS2_HDR) & (fbdic_fbd_state[2:0] == 3'h4) | | |
3427 | (fbdic1_nb_data[11:0] == `FBD_TS3_HDR) & (fbdic_fbd_state[2:0] == 3'h5); | |
3428 | ||
3429 | assign fbdic1_nb_ts_cnt_in[5:0] = fbdic_fbd_state[2:0] == 3'h2 & fbdic1_nb_ts_cnt[5:0] == 6'hb | | |
3430 | fbdic_fbd_state[2:0] == 3'h3 & fbdic1_nb_ts_cnt[5:0] == 6'h7 | | |
3431 | fbdic_fbd_state[2:0] == 3'h4 & fbdic1_nb_ts_cnt[5:0] == 6'h5 | | |
3432 | fbdic_fbd_state[2:0] == 3'h5 & fbdic1_nb_ts_cnt[5:0] == 6'h5 ? 6'h0 : | |
3433 | fbdic1_hdr_match ? 6'h1 : fbdic1_nb_ts_cnt[5:0] + 6'h1; | |
3434 | ||
3435 | assign fbdic1_nb_ts_cnt_en = fbdic_fbd_state[2:1] == 2'h1 | fbdic_fbd_state[2:1] == 2'h2; | |
3436 | ||
3437 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_6 ff_nb_ts_cnt1 ( | |
3438 | .scan_in(ff_nb_ts_cnt1_scanin), | |
3439 | .scan_out(ff_nb_ts_cnt1_scanout), | |
3440 | .din(fbdic1_nb_ts_cnt_in[5:0]), | |
3441 | .dout(fbdic1_nb_ts_cnt[5:0]), | |
3442 | .en(fbdic1_nb_ts_cnt_en), | |
3443 | .l1clk(l1clk), | |
3444 | .siclk(siclk), | |
3445 | .soclk(soclk)); | |
3446 | ||
3447 | // Counting sequence matches for channel 1 | |
3448 | ||
3449 | assign fbdic1_lane0_match = fbdic1_ts_exp_data[11:0] == lndskw1_data[35:24]; | |
3450 | assign fbdic1_lane1_match = fbdic1_ts_exp_data[11:0] == lndskw1_data[23:12]; | |
3451 | assign fbdic1_lane2_match = fbdic1_ts_exp_data[11:0] == lndskw1_data[11:0]; | |
3452 | ||
3453 | assign fbdic1_ts_match_in = (fbdic1_nb_ts_cnt[5:0] == 6'h0) | (fbdic1_lane0_match & fbdic1_lane1_match | | |
3454 | fbdic1_lane0_match & fbdic1_lane2_match | fbdic1_lane1_match & fbdic1_lane2_match) & | |
3455 | fbdic1_ts_match; | |
3456 | ||
3457 | mcu_fbdic_ctl_msff_ctl_macro ff_ts_match1 ( | |
3458 | .scan_in(ff_ts_match1_scanin), | |
3459 | .scan_out(ff_ts_match1_scanout), | |
3460 | .din(fbdic1_ts_match_in), | |
3461 | .dout(fbdic1_ts_match), | |
3462 | .l1clk(l1clk), | |
3463 | .siclk(siclk), | |
3464 | .soclk(soclk)); | |
3465 | ||
3466 | assign fbdic1_ts_match_cnt_in[3:0] = | |
3467 | (fbdic1_nb_ts_cnt[5:0] == 6'h0 & ~fbdic1_ts_match[0]) ? 4'h0 : | |
3468 | (fbdic1_nb_ts_cnt[5:0] == 6'h0 & fbdic1_ts_match[0] & fbdic1_ts_match_cnt[3:0] != 4'hf) ? | |
3469 | fbdic1_ts_match_cnt[3:0] + 4'h1 : fbdic1_ts_match_cnt[3:0]; | |
3470 | ||
3471 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__width_4 ff_ts_match1_cnt ( | |
3472 | .scan_in(ff_ts_match1_cnt_scanin), | |
3473 | .scan_out(ff_ts_match1_cnt_scanout), | |
3474 | .din(fbdic1_ts_match_cnt_in[3:0]), | |
3475 | .dout(fbdic1_ts_match_cnt[3:0]), | |
3476 | .clr(fbdic_fbd_state_en), | |
3477 | .l1clk(l1clk), | |
3478 | .siclk(siclk), | |
3479 | .soclk(soclk)); | |
3480 | ||
3481 | ///////////////////////////////// | |
3482 | // Channel Read Latency Register | |
3483 | ///////////////////////////////// | |
3484 | assign fbdic_chnl_read_lat[15:0] = {fbdic_rt_lat1[7:0],fbdic_rt_lat0[7:0]}; | |
3485 | ||
3486 | // Channel round-trip latency counters | |
3487 | ||
3488 | // Channel 0 | |
3489 | assign fbdic_rt_lat_cntr0_in[7:0] = fbdic_rt_lat_cntr0[7:0] + 8'h1; | |
3490 | assign fbdic_rt_lat_cntr0_en = fbdic_sequence[1:0] == 2'h2 | fbdic_sequence_en[2]; | |
3491 | assign fbdic_rt_lat_cntr0_clr = ts2_cnt[2:0] == 3'h5 & ts2_seq_id[3:0] == 4'h0; | |
3492 | ||
3493 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_8 ff_rt_lat_cntr0 ( | |
3494 | .scan_in(ff_rt_lat_cntr0_scanin), | |
3495 | .scan_out(ff_rt_lat_cntr0_scanout), | |
3496 | .din(fbdic_rt_lat_cntr0_in[7:0]), | |
3497 | .dout(fbdic_rt_lat_cntr0[7:0]), | |
3498 | .en(fbdic_rt_lat_cntr0_en), | |
3499 | .clr(fbdic_rt_lat_cntr0_clr), | |
3500 | .l1clk(l1clk), | |
3501 | .siclk(siclk), | |
3502 | .soclk(soclk)); | |
3503 | ||
3504 | assign fbdic_rt_lat0_en = fbdic_sequence[1:0] == 2'h2 & fbdic0_nb_ts_cnt[5:0] == 6'h5 & fbdic0_nb_ts2_seq_id[3:0] == 4'h0 | | |
3505 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8b8; | |
3506 | assign fbdic_rt_lat0_in[7:0] = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8b8 ? | |
3507 | drif_ucb_data[7:0] : fbdic_rt_lat_cntr0[7:0]; | |
3508 | ||
3509 | assign inv_fbdic_rt_lat0_in[7:0] = ~fbdic_rt_lat0_in[7:0]; | |
3510 | assign fbdic_rt_lat0[7:0] = ~inv_fbdic_rt_lat0[7:0]; | |
3511 | ||
3512 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_8 ff_rt_lat0 ( // FS:wmr_protect | |
3513 | .scan_in(ff_rt_lat0_wmr_scanin), | |
3514 | .scan_out(ff_rt_lat0_wmr_scanout), | |
3515 | .siclk(aclk_wmr), | |
3516 | .din(inv_fbdic_rt_lat0_in[7:0]), | |
3517 | .dout(inv_fbdic_rt_lat0[7:0]), | |
3518 | .en(fbdic_rt_lat0_en), | |
3519 | .l1clk(l1clk), | |
3520 | .soclk(soclk)); | |
3521 | ||
3522 | // Channel 1 | |
3523 | ||
3524 | assign fbdic_rt_lat_cntr1_en = fbdic_sequence[1:0] == 2'h2 | fbdic_sequence_en[2]; | |
3525 | assign fbdic_rt_lat_cntr1_in[7:0] = fbdic_rt_lat_cntr1[7:0] + 8'h1; | |
3526 | assign fbdic_rt_lat_cntr1_clr = ts2_cnt[2:0] == 3'h5 & ts2_seq_id[3:0] == 4'h0; | |
3527 | ||
3528 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_8 ff_rt_lat_cntr1 ( | |
3529 | .scan_in(ff_rt_lat_cntr1_scanin), | |
3530 | .scan_out(ff_rt_lat_cntr1_scanout), | |
3531 | .din(fbdic_rt_lat_cntr1_in[7:0]), | |
3532 | .dout(fbdic_rt_lat_cntr1[7:0]), | |
3533 | .en(fbdic_rt_lat_cntr1_en), | |
3534 | .clr(fbdic_rt_lat_cntr1_clr), | |
3535 | .l1clk(l1clk), | |
3536 | .siclk(siclk), | |
3537 | .soclk(soclk)); | |
3538 | ||
3539 | assign fbdic_rt_lat1_en = fbdic_sequence[1:0] == 2'h2 & fbdic0_nb_ts_cnt[5:0] == 6'h5 & fbdic0_nb_ts2_seq_id[3:0] == 4'h0 | | |
3540 | drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8b8; | |
3541 | assign fbdic_rt_lat1_in[7:0] = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8b8 ? | |
3542 | drif_ucb_data[23:16] : fbdic_rt_lat_cntr1[7:0]; | |
3543 | ||
3544 | assign inv_fbdic_rt_lat1_in[7:0] = ~fbdic_rt_lat1_in[7:0]; | |
3545 | assign fbdic_rt_lat1[7:0] = ~inv_fbdic_rt_lat1[7:0]; | |
3546 | ||
3547 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_8 ff_rt_lat1 ( // FS:wmr_protect | |
3548 | .scan_in(ff_rt_lat1_wmr_scanin), | |
3549 | .scan_out(ff_rt_lat1_wmr_scanout), | |
3550 | .siclk(aclk_wmr), | |
3551 | .din(inv_fbdic_rt_lat1_in[7:0]), | |
3552 | .dout(inv_fbdic_rt_lat1[7:0]), | |
3553 | .en(fbdic_rt_lat1_en), | |
3554 | .l1clk(l1clk), | |
3555 | .soclk(soclk)); | |
3556 | ||
3557 | //////////////////////////////////////// | |
3558 | // Channel capability registers | |
3559 | //////////////////////////////////////// | |
3560 | ||
3561 | assign fbdic_ch0_cap_reg_in[4:0] = fbdic0_nb_data[9:5]; | |
3562 | assign fbdic_ch0_cap_reg_en = fbdic_sequence[1:0] == 2'h2 & fbdic0_nb_ts_cnt[5:0] == 6'h2; | |
3563 | ||
3564 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_5 ff_ch0_cap_reg ( | |
3565 | .scan_in(ff_ch0_cap_reg_scanin), | |
3566 | .scan_out(ff_ch0_cap_reg_scanout), | |
3567 | .din(fbdic_ch0_cap_reg_in[4:0]), | |
3568 | .dout(fbdic_ch0_cap_reg[4:0]), | |
3569 | .en(fbdic_ch0_cap_reg_en), | |
3570 | .l1clk(l1clk), | |
3571 | .siclk(siclk), | |
3572 | .soclk(soclk)); | |
3573 | ||
3574 | // CLEANUP - add chnl 1 expected values | |
3575 | assign fbdic_ch1_cap_reg_in[4:0] = fbdic1_nb_data[9:5]; | |
3576 | assign fbdic_ch1_cap_reg_en = fbdic_sequence[1:0] == 2'h2 & fbdic0_nb_ts_cnt[5:0] == 6'h2; | |
3577 | ||
3578 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_5 ff_ch1_cap_reg ( | |
3579 | .scan_in(ff_ch1_cap_reg_scanin), | |
3580 | .scan_out(ff_ch1_cap_reg_scanout), | |
3581 | .din(fbdic_ch1_cap_reg_in[4:0]), | |
3582 | .dout(fbdic_ch1_cap_reg[4:0]), | |
3583 | .en(fbdic_ch1_cap_reg_en), | |
3584 | .l1clk(l1clk), | |
3585 | .siclk(siclk), | |
3586 | .soclk(soclk)); | |
3587 | ||
3588 | assign fbdic_chnl_cap[9:0] = {fbdic_ch1_cap_reg[4:0],fbdic_ch0_cap_reg[4:0]}; | |
3589 | ||
3590 | //////////////////////////////////////// | |
3591 | // Sync Frame Generation | |
3592 | //////////////////////////////////////// | |
3593 | // The counter is in mcu_fdout_ctl so that it won't be reset when kp_lnk_up is set | |
3594 | ||
3595 | //assign fbdic_link_cnt_en = (fbdic_l0_state | rdpctl_kp_lnk_up | rdpctl_kp_lnk_up_d1) & ~rdpctl_kp_lnk_up_clr; | |
3596 | assign fbdic_link_cnt_en = fbdic_l0_state | rdpctl_kp_lnk_up; | |
3597 | mcu_fbdic_ctl_msff_ctl_macro ff_kp_lnk_up_d1 ( | |
3598 | .scan_in(ff_kp_lnk_up_d1_scanin), | |
3599 | .scan_out(ff_kp_lnk_up_d1_scanout), | |
3600 | .din(rdpctl_kp_lnk_up), | |
3601 | .dout(rdpctl_kp_lnk_up_d1), | |
3602 | .l1clk(l1clk), | |
3603 | .siclk(siclk), | |
3604 | .soclk(soclk)); | |
3605 | ||
3606 | assign fbdic_sync_frame_req_early3 = fbdic_link_cnt_eq_3 & fbdic_l0_state & ~rdpctl_kp_lnk_up; | |
3607 | ||
3608 | assign fbdic_link_cnt_eq_4_in = fdout_link_cnt[5:0] == 6'h4; | |
3609 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_sync_frame_req_early ( | |
3610 | .scan_in(ff_sync_frame_req_early_scanin), | |
3611 | .scan_out(ff_sync_frame_req_early_scanout), | |
3612 | .din({fbdic_link_cnt_eq_4, fbdic_sync_frame_req_early3, fbdic_sync_frame_req_early2}), | |
3613 | .dout({fbdic_link_cnt_eq_3, fbdic_sync_frame_req_early2, fbdic_sync_frame_req_early1}), | |
3614 | .l1clk(l1clk), | |
3615 | .siclk(siclk), | |
3616 | .soclk(soclk)); | |
3617 | ||
3618 | assign fbdic_link_cnt_eq_0_in = fdout_link_cnt[5:0] == 6'h0; | |
3619 | assign fbdic_sync_frame_req = fbdic_link_cnt_eq_0 & ~rdpctl_kp_lnk_up & fbdic_l0_state; | |
3620 | ||
3621 | assign fbdic_sync_frame_req_delay_in[2:0] = fbdic_sync_frame_req | (|fbdic_sync_frame_req_delay[2:0]) ? | |
3622 | fbdic_sync_frame_req_delay[2:0] + 3'h1 : fbdic_sync_frame_req_delay[2:0]; | |
3623 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_sync_frame_req_delay ( | |
3624 | .scan_in(ff_sync_frame_req_delay_scanin), | |
3625 | .scan_out(ff_sync_frame_req_delay_scanout), | |
3626 | .din(fbdic_sync_frame_req_delay_in[2:0]), | |
3627 | .dout(fbdic_sync_frame_req_delay[2:0]), | |
3628 | .l1clk(l1clk), | |
3629 | .siclk(siclk), | |
3630 | .soclk(soclk)); | |
3631 | ||
3632 | assign fbdic_sync_frame_req_d1 = fbdic_sync_frame_req_delay[2:0] == 3'h1; | |
3633 | assign fbdic_sync_frame_req_d2 = fbdic_sync_frame_req_delay[2:0] == 3'h2; | |
3634 | assign fbdic_sync_frame_req_d4 = fbdic_sync_frame_req_delay[2:0] == 3'h4; | |
3635 | ||
3636 | assign fbdic_sync_sd[1:0] = drif_single_channel_mode ? (fbdic_rd_cmd_a_d1 ? 2'h3 : | |
3637 | fbdic_rd_cmd_a_d2 ? 2'h2 : | |
3638 | fbdic_rd_cmd_a_d3 ? 2'h1 : 2'h0) : {1'b0, fbdic_rd_cmd_a_d1}; | |
3639 | ||
3640 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_rd_cmd_a_d1 ( | |
3641 | .scan_in(ff_rd_cmd_a_d1_scanin), | |
3642 | .scan_out(ff_rd_cmd_a_d1_scanout), | |
3643 | .din({fbdic_rd_cmd_a,fbdic_rd_cmd_a_d1,fbdic_rd_cmd_a_d2}), | |
3644 | .dout({fbdic_rd_cmd_a_d1,fbdic_rd_cmd_a_d2,fbdic_rd_cmd_a_d3}), | |
3645 | .l1clk(l1clk), | |
3646 | .siclk(siclk), | |
3647 | .soclk(soclk)); | |
3648 | ||
3649 | assign fbdic_link_cnt_reset[5:0] = fbdic_sync_el0s & ~rdpctl_kp_lnk_up ? fbdic_l0s_time[5:0] : fbdic_sync_frm_period[5:0]; | |
3650 | ||
3651 | // Soft channel reset request delay for issuing next command | |
3652 | assign fbdic_scr_frame_req_dly_in[3:0] = fbdic_scr_frame_req_dly[3:0] + 4'h1; | |
3653 | assign fbdic_scr_frame_req_dly_en = fbdic_scr_frame_req | (|fbdic_scr_frame_req_dly[3:0]); | |
3654 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_4 ff_scr_dly ( | |
3655 | .scan_in(ff_scr_dly_scanin), | |
3656 | .scan_out(ff_scr_dly_scanout), | |
3657 | .din(fbdic_scr_frame_req_dly_in[3:0]), | |
3658 | .dout(fbdic_scr_frame_req_dly[3:0]), | |
3659 | .en(fbdic_scr_frame_req_dly_en), | |
3660 | .l1clk(l1clk), | |
3661 | .siclk(siclk), | |
3662 | .soclk(soclk)); | |
3663 | assign fbdic_scr_frame_req_d4 = fbdic_scr_frame_req_dly[3:0] == 4'h4; | |
3664 | assign fbdic_scr_frame_req_d5 = fbdic_scr_frame_req_dly[3:0] == 4'h5; | |
3665 | assign fbdic_scr_frame_req_d10 = fbdic_scr_frame_req_dly[3:0] == 4'ha; | |
3666 | ||
3667 | ||
3668 | // Issue Pre-charge All command after SCR | |
3669 | assign fbdic_issue_pre_all_cmd_in = fbdic_scr_frame_req_d10 ? 1'b1 : | |
3670 | fbdic_pre_all_rank[3:0] == fbdic_last_rank[3:0] ? 1'b0 : fbdic_issue_pre_all_cmd; | |
3671 | mcu_fbdic_ctl_msff_ctl_macro ff_issue_pre_all_cmd ( | |
3672 | .scan_in(ff_issue_pre_all_cmd_scanin), | |
3673 | .scan_out(ff_issue_pre_all_cmd_scanout), | |
3674 | .din(fbdic_issue_pre_all_cmd_in), | |
3675 | .dout(fbdic_issue_pre_all_cmd), | |
3676 | .l1clk(l1clk), | |
3677 | .siclk(siclk), | |
3678 | .soclk(soclk)); | |
3679 | ||
3680 | assign fbdic_pre_all_rank_in[3] = fbdic_issue_pre_all_cmd & (fbdic_pre_all_rank[3] ^ drif_stacked_dimm); | |
3681 | assign fbdic_pre_all_rank_in[2:0] = {3{fbdic_issue_pre_all_cmd}} & (fbdic_pre_all_rank[2:0] + | |
3682 | {2'h0, fbdic_pre_all_rank[3] & drif_stacked_dimm | ~drif_stacked_dimm}); | |
3683 | ||
3684 | mcu_fbdic_ctl_msff_ctl_macro__width_4 ff_pre_all_rank ( | |
3685 | .scan_in(ff_pre_all_rank_scanin), | |
3686 | .scan_out(ff_pre_all_rank_scanout), | |
3687 | .din(fbdic_pre_all_rank_in[3:0]), | |
3688 | .dout(fbdic_pre_all_rank[3:0]), | |
3689 | .l1clk(l1clk), | |
3690 | .siclk(siclk), | |
3691 | .soclk(soclk)); | |
3692 | ||
3693 | assign fbdic_last_rank[3:0] = {drif_stacked_dimm, drif_num_dimms[2:0] - 3'h1}; | |
3694 | ||
3695 | // DRAM and Channel Commands | |
3696 | ||
3697 | assign fbdic_act_cmd_a[23:0] = {drif_dram_dimm_a[2:0], 1'b1, drif_dram_addr_a[15:14], drif_dram_rank_a, | |
3698 | drif_dram_addr_a[13], drif_dram_bank_a[2:0], drif_dram_addr_a[12:0]}; | |
3699 | ||
3700 | assign fbdic_rd_cmd_a = (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_RD); | |
3701 | assign fbdic_wr_cmd_a = (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_WR); | |
3702 | assign fbdic_rd_wr_cmd_a[23:0] = {drif_dram_dimm_a[2:0], 2'h1, fbdic_wr_cmd_a, drif_dram_rank_a, 1'b0, | |
3703 | drif_dram_bank_a[2:0], drif_dram_addr_a[12:0]}; | |
3704 | ||
3705 | assign fbdic_sync_cmd_a[23:0] = {11'h2, fbdic_sync_sd[1:0], 4'h0, fbdic_sync_ier, | |
3706 | fbdic_sync_erc, fbdic_sync_el0s, 2'h0, fbdic_sync_r[1:0]}; | |
3707 | ||
3708 | assign fbdic_soft_chnl_reset_cmd[23:0] = 24'h008000; | |
3709 | ||
3710 | assign fbdic_a_cmd_in[23:0] = fbdic_sync_frame_req ? fbdic_sync_cmd_a[23:0] : | |
3711 | fbdic_scr_frame_req ? fbdic_soft_chnl_reset_cmd[23:0] : | |
3712 | (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_ACT) ? fbdic_act_cmd_a[23:0] : | |
3713 | (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_RD) | | |
3714 | (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_WR) ? fbdic_rd_wr_cmd_a[23:0] : 24'h0; | |
3715 | ||
3716 | assign fbdic_f_in[1] = (drif_dram_cmd_b[2:0] == `FBD_DRAM_CMD_WDATA); | |
3717 | assign fbdic_f_in[0] = fbdic_f_in[1] ? drif_wdata_wsn : 1'b0; | |
3718 | ||
3719 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_f ( | |
3720 | .scan_in(ff_f_scanin), | |
3721 | .scan_out(ff_f_scanout), | |
3722 | .din(fbdic_f_in[1:0]), | |
3723 | .dout(fbdic_f[1:0]), | |
3724 | .l1clk(l1clk), | |
3725 | .siclk(siclk), | |
3726 | .soclk(soclk)); | |
3727 | ||
3728 | assign fbdic_f_1_l = ~fbdic_f[1]; | |
3729 | ||
3730 | mcu_fbdic_ctl_msff_ctl_macro__width_24 ff_a_cmd ( | |
3731 | .scan_in(ff_a_cmd_scanin), | |
3732 | .scan_out(ff_a_cmd_scanout), | |
3733 | .din(fbdic_a_cmd_in[23:0]), | |
3734 | .dout(fbdic_a_cmd[23:0]), | |
3735 | .l1clk(l1clk), | |
3736 | .siclk(siclk), | |
3737 | .soclk(soclk)); | |
3738 | ||
3739 | assign fbdic_special_cmd_in = fbdic_sync_frame_req | fbdic_scr_frame_req; | |
3740 | ||
3741 | mcu_fbdic_ctl_msff_ctl_macro__width_1 ff_special_cmd ( | |
3742 | .scan_in(ff_special_cmd_scanin), | |
3743 | .scan_out(ff_special_cmd_scanout), | |
3744 | .din(fbdic_special_cmd_in), | |
3745 | .dout(fbdic_special_cmd), | |
3746 | .l1clk(l1clk), | |
3747 | .siclk(siclk), | |
3748 | .soclk(soclk)); | |
3749 | ||
3750 | assign fbdic_trans_id = fbdic_config_reg_addr[15] ? ~fbdic1_last_trans_id : ~fbdic0_last_trans_id; | |
3751 | ||
3752 | assign fbdic0_last_trans_id_in = ~fbdic0_last_trans_id; | |
3753 | assign fbdic0_last_trans_id_en = fbdic_config_reg_write & ~fbdic_config_reg_addr[15]; | |
3754 | mcu_fbdic_ctl_msff_ctl_macro__en_1 ff_last_trans_id0 ( | |
3755 | .scan_in(ff_last_trans_id0_scanin), | |
3756 | .scan_out(ff_last_trans_id0_scanout), | |
3757 | .din(fbdic0_last_trans_id_in), | |
3758 | .dout(fbdic0_last_trans_id), | |
3759 | .en(fbdic0_last_trans_id_en), | |
3760 | .l1clk(l1clk), | |
3761 | .siclk(siclk), | |
3762 | .soclk(soclk)); | |
3763 | ||
3764 | assign fbdic1_last_trans_id_in = ~fbdic1_last_trans_id; | |
3765 | assign fbdic1_last_trans_id_en = fbdic_config_reg_write & fbdic_config_reg_addr[15]; | |
3766 | mcu_fbdic_ctl_msff_ctl_macro__en_1 ff_last_trans_id1 ( | |
3767 | .scan_in(ff_last_trans_id1_scanin), | |
3768 | .scan_out(ff_last_trans_id1_scanout), | |
3769 | .din(fbdic1_last_trans_id_in), | |
3770 | .dout(fbdic1_last_trans_id), | |
3771 | .en(fbdic1_last_trans_id_en), | |
3772 | .l1clk(l1clk), | |
3773 | .siclk(siclk), | |
3774 | .soclk(soclk)); | |
3775 | ||
3776 | assign fbdic_pre_all_cmd[23:0] = {fbdic_pre_all_rank[2:0], 3'h1, fbdic_pre_all_rank[3], 17'h01c00}; | |
3777 | assign fbdic_ref_cmd_b[23:0] = {drif_dram_dimm_b[2:0], 3'h1, drif_dram_rank_b,4'h0,`FBD_DRAM_CMD_OTHER_REF,10'h0}; | |
3778 | assign fbdic_b_cmd[35:0] = fbdic_config_reg_write | fbdic_config_reg_read ? | |
3779 | {12'h0,fbdic_config_reg_addr[13:11],6'h02,fbdic_config_reg_write,fbdic_config_reg_addr[14], | |
3780 | fbdic_trans_id & fbdic_config_reg_write,1'b0,fbdic_config_reg_addr[10:2],2'h0} : | |
3781 | fbdic_issue_cke_cmd ? {12'h0, fbdic_lower_cke_cmd[23:0]} : | |
3782 | fbdic_issue_pre_all_cmd ? {12'h0, fbdic_pre_all_cmd[23:0]} : | |
3783 | (drif_dram_cmd_b[2:0] == `FBD_DRAM_CMD_ACT) ? {12'h0, drif_dram_dimm_b[2:0], 1'b1, | |
3784 | drif_dram_addr_b[15:14], drif_dram_rank_b, drif_dram_addr_b[13], | |
3785 | drif_dram_bank_b[2:0], drif_dram_addr_b[12:0]} : | |
3786 | (drif_dram_cmd_b[2:0] == `FBD_DRAM_CMD_WR) ? {12'h0, drif_dram_dimm_b[2:0], 3'h3, | |
3787 | drif_dram_rank_b, 1'b0, drif_dram_bank_b[2:0], drif_dram_addr_b[12:0]} : | |
3788 | (drif_dram_cmd_b[2:0] == `FBD_DRAM_CMD_OTHER) & | |
3789 | (drif_dram_addr_b[2:0] == `FBD_DRAM_CMD_OTHER_REF) ? | |
3790 | {12'h0, fbdic_ref_cmd_b[23:0]} : 36'h0; | |
3791 | ||
3792 | assign fbdic_sre_cmd_c[23:0] = {drif_dram_dimm_c[2:0], 3'h1, drif_dram_rank_c,4'h0,`FBD_DRAM_CMD_OTHER_SRE,10'h0}; | |
3793 | assign fbdic_pde_cmd_c[23:0] = {drif_dram_dimm_c[2:0], 3'h1, drif_dram_rank_c,4'h0,`FBD_DRAM_CMD_OTHER_PDE,10'h0}; | |
3794 | assign fbdic_srpdx_cmd_c[23:0] = {drif_dram_dimm_c[2:0], 3'h1, drif_dram_rank_c,4'h0,`FBD_DRAM_CMD_OTHER_SRPDX,10'h0}; | |
3795 | ||
3796 | assign fbdic_c_cmd[35:0] = fbdic_config_reg_write ? {4'hf,fbdic_cnfgreg_wr_data[31:0]} : | |
3797 | fbdic_issue_cke_cmd ? {12'h0, fbdic_upper_cke_cmd[23:0]} : | |
3798 | (drif_dram_cmd_c[2:0] == `FBD_DRAM_CMD_ACT) ? {12'h0, drif_dram_dimm_c[2:0], 1'b1, | |
3799 | drif_dram_addr_c[15:14], drif_dram_rank_c, drif_dram_addr_c[13], | |
3800 | drif_dram_bank_c[2:0], drif_dram_addr_c[12:0]} : | |
3801 | (drif_dram_cmd_c[2:0] == `FBD_DRAM_CMD_WR) ? {12'h0, drif_dram_dimm_c[2:0], 3'h3, | |
3802 | drif_dram_rank_c, 1'b0, drif_dram_bank_c[2:0], drif_dram_addr_c[12:0]} : | |
3803 | (drif_dram_cmd_c[2:0] != `FBD_DRAM_CMD_OTHER) ? 36'h0 : | |
3804 | (drif_dram_addr_c[2:0] == `FBD_DRAM_CMD_OTHER_SRE) ? {12'h0, fbdic_sre_cmd_c[23:0]} : | |
3805 | (drif_dram_addr_c[2:0] == `FBD_DRAM_CMD_OTHER_PDE) ? {12'h0, fbdic_pde_cmd_c[23:0]} : | |
3806 | (drif_dram_addr_c[2:0] == `FBD_DRAM_CMD_OTHER_SRPDX) ? {12'h0, fbdic_srpdx_cmd_c[23:0]} : | |
3807 | 36'h0; | |
3808 | ||
3809 | assign fbdic_bc_cmd_in[71:0] = fbdic_special_cmd_in ? 72'haa_55aa55aa_55aa55aa : | |
3810 | {fbdic_c_cmd[35:32],fbdic_b_cmd[35:32], | |
3811 | fbdic_c_cmd[31:28],fbdic_b_cmd[31:28], | |
3812 | fbdic_c_cmd[27:24],fbdic_b_cmd[27:24], | |
3813 | fbdic_c_cmd[23:20],fbdic_b_cmd[23:20], | |
3814 | fbdic_c_cmd[19:16],fbdic_b_cmd[19:16], | |
3815 | fbdic_c_cmd[15:12],fbdic_b_cmd[15:12], | |
3816 | fbdic_c_cmd[11:8], fbdic_b_cmd[11:8], | |
3817 | fbdic_c_cmd[7:4], fbdic_b_cmd[7:4], | |
3818 | fbdic_c_cmd[3:0], fbdic_b_cmd[3:0]}; | |
3819 | ||
3820 | mcu_fbdic_ctl_msff_ctl_macro__width_72 ff_bc_cmd ( | |
3821 | .scan_in(ff_bc_cmd_scanin), | |
3822 | .scan_out(ff_bc_cmd_scanout), | |
3823 | .din(fbdic_bc_cmd_in[71:0]), | |
3824 | .dout(fbdic_bc_cmd[71:0]), | |
3825 | .l1clk(l1clk), | |
3826 | .siclk(siclk), | |
3827 | .soclk(soclk)); | |
3828 | ||
3829 | // Lane deskew buffer control logic | |
3830 | // The logic waits for the TS0 header to appear at the head of all 28 buffers before proceeding. | |
3831 | // If only 13 lanes of either channel 0 or channel 1 have TS0 headers present, then the logic waits | |
3832 | // until the tclktrain miniumum time has expired and then allows the buffers to proceed. | |
3833 | ||
3834 | assign fbdic0_inc_wptr = fbdic_fbd_state[2] | fbdic_fbd_state[1] | rdpctl_kp_lnk_up | fbdic_serdes_dtm | fbdic_loopback[1]; | |
3835 | assign fbdic0_inc_rptr[13:0] = ~lndskw0_ts0_hdr_match[13:0] | {14{fbdic0_lane_align & | |
3836 | (fbdic1_lane_align | drif_single_channel_mode)}}; | |
3837 | assign fbdic0_clr_ptrs = fbdic_fbd_state[2:0] == 3'h0 & ~rdpctl_kp_lnk_up & ~fbdic_serdes_dtm & ~fbdic_loopback[1]; | |
3838 | assign fbdic0_lane_align_in = ((|fbdic_fbd_state[2:0]) | rdpctl_kp_lnk_up | fbdic_serdes_dtm | fbdic_loopback[1]) & | |
3839 | (&lndskw0_ts0_hdr_match[13:0] | | |
3840 | fbdic0_13_lanes_aligned & ~(|fbdic_tclktrain_timeout_cnt[15:10]) | | |
3841 | fbdic0_lane_align_out); | |
3842 | ||
3843 | assign fbdic0_13_lanes_aligned = lndskw0_ts0_hdr_match[13:0] == 14'h3ffe | | |
3844 | lndskw0_ts0_hdr_match[13:0] == 14'h3ffd | | |
3845 | lndskw0_ts0_hdr_match[13:0] == 14'h3ffb | | |
3846 | lndskw0_ts0_hdr_match[13:0] == 14'h3ff7 | | |
3847 | lndskw0_ts0_hdr_match[13:0] == 14'h3fef | | |
3848 | lndskw0_ts0_hdr_match[13:0] == 14'h3fdf | | |
3849 | lndskw0_ts0_hdr_match[13:0] == 14'h3fbf | | |
3850 | lndskw0_ts0_hdr_match[13:0] == 14'h3f7f | | |
3851 | lndskw0_ts0_hdr_match[13:0] == 14'h3eff | | |
3852 | lndskw0_ts0_hdr_match[13:0] == 14'h3dff | | |
3853 | lndskw0_ts0_hdr_match[13:0] == 14'h3bff | | |
3854 | lndskw0_ts0_hdr_match[13:0] == 14'h37ff | | |
3855 | lndskw0_ts0_hdr_match[13:0] == 14'h2fff | | |
3856 | lndskw0_ts0_hdr_match[13:0] == 14'h1fff; | |
3857 | ||
3858 | assign fbdic1_inc_wptr = (fbdic_fbd_state[2] | fbdic_fbd_state[1] | rdpctl_kp_lnk_up | fbdic_serdes_dtm | | |
3859 | fbdic_loopback[1]) & ~drif_single_channel_mode; | |
3860 | assign fbdic1_inc_rptr[13:0] = drif_single_channel_mode ? 14'h0 : | |
3861 | ~lndskw1_ts0_hdr_match[13:0] | {14{fbdic0_lane_align & fbdic1_lane_align}}; | |
3862 | assign fbdic1_clr_ptrs = fbdic_fbd_state[2:0] == 3'h0 & ~rdpctl_kp_lnk_up & ~fbdic_serdes_dtm & ~fbdic_loopback[1]; | |
3863 | assign fbdic1_lane_align_in = ((|fbdic_fbd_state[2:0]) | rdpctl_kp_lnk_up | fbdic_serdes_dtm | fbdic_loopback[1]) & | |
3864 | (&lndskw1_ts0_hdr_match[13:0] | | |
3865 | fbdic1_13_lanes_aligned & ~(|fbdic_tclktrain_timeout_cnt[15:10]) | | |
3866 | fbdic1_lane_align_out); | |
3867 | ||
3868 | assign fbdic1_13_lanes_aligned = lndskw1_ts0_hdr_match[13:0] == 14'h3ffe | | |
3869 | lndskw1_ts0_hdr_match[13:0] == 14'h3ffd | | |
3870 | lndskw1_ts0_hdr_match[13:0] == 14'h3ffb | | |
3871 | lndskw1_ts0_hdr_match[13:0] == 14'h3ff7 | | |
3872 | lndskw1_ts0_hdr_match[13:0] == 14'h3fef | | |
3873 | lndskw1_ts0_hdr_match[13:0] == 14'h3fdf | | |
3874 | lndskw1_ts0_hdr_match[13:0] == 14'h3fbf | | |
3875 | lndskw1_ts0_hdr_match[13:0] == 14'h3f7f | | |
3876 | lndskw1_ts0_hdr_match[13:0] == 14'h3eff | | |
3877 | lndskw1_ts0_hdr_match[13:0] == 14'h3dff | | |
3878 | lndskw1_ts0_hdr_match[13:0] == 14'h3bff | | |
3879 | lndskw1_ts0_hdr_match[13:0] == 14'h37ff | | |
3880 | lndskw1_ts0_hdr_match[13:0] == 14'h2fff | | |
3881 | lndskw1_ts0_hdr_match[13:0] == 14'h1fff; | |
3882 | ||
3883 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_lane_align ( // FS:wmr_protect | |
3884 | .scan_in(ff_lane_align_wmr_scanin), | |
3885 | .scan_out(ff_lane_align_wmr_scanout), | |
3886 | .siclk(aclk_wmr), | |
3887 | .din({fbdic0_lane_align_in,fbdic1_lane_align_in}), | |
3888 | .dout({fbdic0_lane_align_out,fbdic1_lane_align_out}), | |
3889 | .l1clk(l1clk), | |
3890 | .soclk(soclk)); | |
3891 | ||
3892 | assign fbdic0_lane_align = fbdic0_lane_align_out | fbdic0_lane_align_in; | |
3893 | assign fbdic1_lane_align = fbdic1_lane_align_out | fbdic1_lane_align_in; | |
3894 | ||
3895 | ////////////////////////////////////////////////////////////////////////////////// | |
3896 | // Free running counter: when a request is issued, the counter value plus the | |
3897 | // channel latency is stored in a fifo. When the counter reaches the value at | |
3898 | // the head of the fifo, rddata_vld is asserted for reads, status is detected for | |
3899 | // sync/soft channel reset frames, and idle/alert frame detects are generated for | |
3900 | // write requests. | |
3901 | ////////////////////////////////////////////////////////////////////////////////// | |
3902 | ||
3903 | assign fbdic_chnl_latency_cntr_in[7:0] = fbdic_chnl_latency_cntr[7:0] + 8'h1; | |
3904 | mcu_fbdic_ctl_msff_ctl_macro__width_8 ff_chnl_latency_cntr ( | |
3905 | .scan_in(ff_chnl_latency_cntr_scanin), | |
3906 | .scan_out(ff_chnl_latency_cntr_scanout), | |
3907 | .din(fbdic_chnl_latency_cntr_in[7:0]), | |
3908 | .dout(fbdic_chnl_latency_cntr[7:0]), | |
3909 | .l1clk(l1clk), | |
3910 | .siclk(siclk), | |
3911 | .soclk(soclk)); | |
3912 | ||
3913 | assign fbdic_latq_enq = (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_RD | drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_WR | | |
3914 | drif_dram_cmd_b[2:0] == `FBD_DRAM_CMD_WR | drif_dram_cmd_c[2:0] == `FBD_DRAM_CMD_WR) | | |
3915 | fbdic_config_reg_read | fbdic_sync_frame_req | fbdic_scr_frame_req; | |
3916 | assign fbdic_latq_deq = (fbdic_chnl_latency_cntr[7:0] == fbdic_latq_dout[7:0]) & ~fbdic_latq_empty; | |
3917 | ||
3918 | assign fbdic_rddata_vld_d0 = fbdic_latq_deq & fbdic_latq_dout[11:8] == 4'h0; | |
3919 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_rddata_vld_d1 ( | |
3920 | .scan_in(ff_rddata_vld_d1_scanin), | |
3921 | .scan_out(ff_rddata_vld_d1_scanout), | |
3922 | .din({fbdic_rddata_vld_d0,fbdic_rddata_vld_d1,fbdic_rddata_vld_d2}), | |
3923 | .dout({fbdic_rddata_vld_d1,fbdic_rddata_vld_d2,fbdic_rddata_vld_d3}), | |
3924 | .l1clk(l1clk), | |
3925 | .siclk(siclk), | |
3926 | .soclk(soclk)); | |
3927 | ||
3928 | assign fbdic_rddata_vld = fbdic_rddata_vld_d0 | fbdic_rddata_vld_d1 | | |
3929 | drif_single_channel_mode & (fbdic_rddata_vld_d2 | fbdic_rddata_vld_d3); | |
3930 | assign fbdic_rddata_vld_l = ~(fbdic_rddata_vld | fbdic_cnfgreg_rddata_vld); | |
3931 | ||
3932 | assign fbdic_woq_free[1:0] = fbdic_latq_deq & fbdic_latq_dout[11:8] == 4'h1 ? 2'h1 : | |
3933 | fbdic_latq_deq & fbdic_latq_dout[11:8] == 4'h2 ? 2'h2 : 2'h0; | |
3934 | ||
3935 | assign fbdic_status_frame = fbdic_latq_deq & fbdic_latq_dout[11:8] == 4'h4 | | |
3936 | fbdic_latq_deq_d1 & fbdic_latq_dout_reg[11:8] == 4'h5 | | |
3937 | fbdic_latq_deq_d2 & fbdic_latq_dout_reg[11:8] == 4'h6 | | |
3938 | fbdic_latq_deq_d3 & fbdic_latq_dout_reg[11:8] == 4'h7; | |
3939 | ||
3940 | assign fbdic_latq_deq_d0 = fbdic_latq_deq & fbdic_latq_dout[11:10] == 2'h1; | |
3941 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_latq_deq_dly ( | |
3942 | .scan_in(ff_latq_deq_dly_scanin), | |
3943 | .scan_out(ff_latq_deq_dly_scanout), | |
3944 | .din( {fbdic_latq_deq_d0, fbdic_latq_deq_d1, fbdic_latq_deq_d2}), | |
3945 | .dout({fbdic_latq_deq_d1, fbdic_latq_deq_d2, fbdic_latq_deq_d3}), | |
3946 | .l1clk(l1clk), | |
3947 | .siclk(siclk), | |
3948 | .soclk(soclk)); | |
3949 | ||
3950 | assign fbdic_latq_dout_reg_en = fbdic_latq_deq & fbdic_latq_dout[11:10] == 2'h1; | |
3951 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_4 ff_latq_dout_reg ( | |
3952 | .scan_in(ff_latq_dout_reg_scanin), | |
3953 | .scan_out(ff_latq_dout_reg_scanout), | |
3954 | .din(fbdic_latq_dout[11:8]), | |
3955 | .dout(fbdic_latq_dout_reg[11:8]), | |
3956 | .en(fbdic_latq_dout_reg_en), | |
3957 | .l1clk(l1clk), | |
3958 | .siclk(siclk), | |
3959 | .soclk(soclk)); | |
3960 | ||
3961 | assign fbdic_scr_response_frame = fbdic_latq_deq & fbdic_latq_dout[11:8] == 4'h3; | |
3962 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_status_frame_d1 ( | |
3963 | .scan_in(ff_status_frame_d1_scanin), | |
3964 | .scan_out(ff_status_frame_d1_scanout), | |
3965 | .din({fbdic_status_frame, fbdic_scr_response_frame}), | |
3966 | .dout({fbdic_status_frame_d1, fbdic_scr_response_frame_d1}), | |
3967 | .l1clk(l1clk), | |
3968 | .siclk(siclk), | |
3969 | .soclk(soclk)); | |
3970 | ||
3971 | assign fbdic_cnfgreg_rddata_vld_in = fbdic_latq_deq & fbdic_latq_dout[11:8] == 4'h8; | |
3972 | assign fbdic_cnfgreg_data_in[31:0] = fbdic_config_reg_addr[15] ? fbdird1_cnfgreg_data[31:0] : fbdird0_cnfgreg_data[31:0]; | |
3973 | ||
3974 | assign fbdic_cnfgreg_data_32_in = fbdic_cnfgreg_rddata_vld & ~fbdic_cfgrd_crc_error & fbdic_l0_state; | |
3975 | ||
3976 | mcu_fbdic_ctl_msff_ctl_macro__width_34 ff_cnfgreg_data ( | |
3977 | .scan_in(ff_cnfgreg_data_scanin), | |
3978 | .scan_out(ff_cnfgreg_data_scanout), | |
3979 | .din({fbdic_cnfgreg_rddata_vld_in,fbdic_cnfgreg_data_32_in,fbdic_cnfgreg_data_in[31:0]}), | |
3980 | .dout({fbdic_cnfgreg_rddata_vld,fbdic_cnfgreg_data[32:0]}), | |
3981 | .l1clk(l1clk), | |
3982 | .siclk(siclk), | |
3983 | .soclk(soclk)); | |
3984 | ||
3985 | ||
3986 | // FIFO entries | |
3987 | //-------------------------------------- | |
3988 | // bits [11:8] | |
3989 | // 0 - read | |
3990 | // 1 - 1 write | |
3991 | // 2 - 2 writes | |
3992 | // 3 - SCR | |
3993 | // 4-7 - Sync + delay | |
3994 | // 8 Cfg Read | |
3995 | // bits [7:0] - latency value | |
3996 | ||
3997 | assign fbdic_latq_xaction[3:0] = fbdic_sync_frame_req ? {2'h1, fbdic_sync_sd[1:0]} : | |
3998 | fbdic_scr_frame_req ? 4'h3 : | |
3999 | (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_RD) ? 4'h0 : | |
4000 | (drif_dram_cmd_a[2:0] == `FBD_DRAM_CMD_WR) ? 4'h1 : | |
4001 | (drif_dram_cmd_b[2:0] == `FBD_DRAM_CMD_WR & drif_dram_cmd_c[2:0] == `FBD_DRAM_CMD_WR) ? 4'h2 : | |
4002 | (drif_dram_cmd_b[2:0] == `FBD_DRAM_CMD_WR | drif_dram_cmd_c[2:0] == `FBD_DRAM_CMD_WR) ? 4'h1 : | |
4003 | fbdic_config_reg_read ? 4'h8 : 4'h0; | |
4004 | ||
4005 | assign fbd_delay[7:0] = {7'h0,~inv_fbd_delay_0}; | |
4006 | mcu_fbdic_ctl_msff_ctl_macro ff_fbd_delay ( | |
4007 | .scan_in(ff_fbd_delay_scanin), | |
4008 | .scan_out(ff_fbd_delay_scanout), | |
4009 | .din(1'b0), | |
4010 | .dout(inv_fbd_delay_0), | |
4011 | .l1clk(l1clk), | |
4012 | .siclk(siclk), | |
4013 | .soclk(soclk)); | |
4014 | ||
4015 | assign fbdic_latq_din[11:0] = {fbdic_latq_xaction[3:0], fbdic_chnl_latency_cntr[7:0] + fbdic_rt_lat0[7:0] + fbd_delay[7:0]}; | |
4016 | ||
4017 | mcu_latq_ctl latq ( | |
4018 | .scan_in(latq_scanin), | |
4019 | .scan_out(latq_scanout), | |
4020 | .l1clk(l1clk), | |
4021 | .latq_enq(fbdic_latq_enq), | |
4022 | .latq_din(fbdic_latq_din[11:0]), | |
4023 | .latq_deq(fbdic_latq_deq), | |
4024 | .latq_dout(fbdic_latq_dout[11:0]), | |
4025 | .latq_full(fbdic_latq_full), | |
4026 | .latq_empty(fbdic_latq_empty), | |
4027 | .tcu_aclk(tcu_aclk), | |
4028 | .tcu_bclk(tcu_bclk), | |
4029 | .tcu_scan_en(tcu_scan_en) | |
4030 | ); | |
4031 | ||
4032 | // Qualify status frames with amb_mask | |
4033 | assign fbdic0_status_parity[11:0] = ~lndskw0_status_parity[11:0] & fbdic_amb_mask[11:0]; | |
4034 | assign fbdic1_status_parity[11:0] = ~lndskw1_status_parity[11:0] & fbdic_amb_mask[11:0] & {12{~drif_single_channel_mode}}; | |
4035 | assign fbdic0_alert_asserted[11:0] = lndskw0_alert_asserted[11:0] & fbdic_amb_mask[11:0]; | |
4036 | assign fbdic1_alert_asserted[11:0] = lndskw1_alert_asserted[11:0] & fbdic_amb_mask[11:0] & {12{~drif_single_channel_mode}}; | |
4037 | ||
4038 | // FBD channel error types | |
4039 | assign fbdic_crc_error = (~(fbdird_crc_cmp0_0 & fbdird_crc_cmp0_1 & fbdird_crc_cmp1_0 & fbdird_crc_cmp1_1) | | |
4040 | fbdic_inj_crc_err) & fbdic_rddata_vld & ~fbdic_chnl_reset_error_mode; | |
4041 | ||
4042 | assign fbdic_status_parity_error_en = ((|fbdic0_status_parity[11:0]) | (|fbdic1_status_parity[11:0]) | fbdic_inj_sfp_err) & | |
4043 | fbdic_status_frame & ~fbdic_chnl_reset_error_mode & fbdic_l0_state; | |
4044 | assign fbdic_alert_asserted_en = ((|fbdic0_alert_asserted[11:0]) | (|fbdic1_alert_asserted[11:0]) | fbdic_inj_aa_err) & | |
4045 | fbdic_status_frame & ~fbdic_chnl_reset_error_mode & ~fbdic_status_parity_error_en & | |
4046 | fbdic_l0_state; | |
4047 | assign fbdic_alert_frame_en = (((&lndskw0_alert_match[12:0]) | ((&lndskw1_alert_match[12:0]) & ~drif_single_channel_mode)) | | |
4048 | fbdic_inj_af_err) & ~fbdic_chnl_reset_error_mode & fbdic_l0_state & ~rdpctl_mask_err; | |
4049 | ||
4050 | assign fbdic_status_parity_error_in = fbdic_status_parity_error_en | fbdic_status_parity_error & ~fbdic_status_parity_error_clr; | |
4051 | assign fbdic_alert_asserted_in = fbdic_alert_asserted_en | fbdic_alert_asserted & ~fbdic_alert_asserted_clr; | |
4052 | assign fbdic_alert_frame_in = fbdic_alert_frame_en | fbdic_alert_frame & ~fbdic_alert_frame_clr; | |
4053 | ||
4054 | assign fbdic_status_parity_error_clr = fbdic_err_unrecov_in | fbdic_err_recov_in; | |
4055 | assign fbdic_alert_asserted_clr = fbdic_err_unrecov_in | fbdic_err_recov_in; | |
4056 | assign fbdic_alert_frame_clr = fbdic_err_unrecov_in | fbdic_err_recov_in; | |
4057 | ||
4058 | mcu_fbdic_ctl_msff_ctl_macro__width_4 ff_fbd_error ( | |
4059 | .scan_in(ff_fbd_error_scanin), | |
4060 | .scan_out(ff_fbd_error_scanout), | |
4061 | .din({fbdic_status_parity_error_in,fbdic_alert_asserted_in,fbdic_alert_frame_in,fbdic_fbd_error_in}), | |
4062 | .dout({fbdic_status_parity_error,fbdic_alert_asserted,fbdic_alert_frame,fbdic_fbd_error}), | |
4063 | .l1clk(l1clk), | |
4064 | .siclk(siclk), | |
4065 | .soclk(soclk)); | |
4066 | ||
4067 | assign fbdic_fbd_error_in = fbdic_err_unrecov | fbdic_err_recov | rdpctl_crc_recov_err | rdpctl_crc_unrecov_err; | |
4068 | ||
4069 | // delay alert asserted and status parity error enables for one cycle for error state machine | |
4070 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_fbd_error_dly ( | |
4071 | .scan_in(ff_fbd_error_dly_scanin), | |
4072 | .scan_out(ff_fbd_error_dly_scanout), | |
4073 | .din({fbdic_status_parity_error_en,fbdic_alert_asserted_en}), | |
4074 | .dout({fbdic_status_parity_error_en_d1,fbdic_alert_asserted_en_d1}), | |
4075 | .l1clk(l1clk), | |
4076 | .siclk(siclk), | |
4077 | .soclk(soclk)); | |
4078 | ||
4079 | assign fbdic_fbd_error_save_clr = fbdic_err_unrecov | fbdic_err_recov | rdpctl_crc_recov_err | rdpctl_crc_unrecov_err; | |
4080 | assign fbdic_spe_in = fbdic_status_parity_error | fbdic_spe; | |
4081 | assign fbdic_aa_in = fbdic_alert_asserted | fbdic_aa; | |
4082 | assign fbdic_af_in = fbdic_alert_frame | fbdic_af; | |
4083 | assign fbdic_scr_in = fbdic_err_state[`FBDIC_ERR_SCRST] | fbdic_scr; | |
4084 | assign fbdic_fr_in = fbdic_err_state[`FBDIC_ERR_FASTRST] | drif_err_state_crc_fr | fbdic_fr; | |
4085 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__width_5 ff_fbd_error_save ( | |
4086 | .scan_in(ff_fbd_error_save_scanin), | |
4087 | .scan_out(ff_fbd_error_save_scanout), | |
4088 | .din({fbdic_spe_in, fbdic_aa_in, fbdic_af_in,fbdic_scr_in,fbdic_fr_in}), | |
4089 | .dout({fbdic_spe, fbdic_aa, fbdic_af,fbdic_scr,fbdic_fr}), | |
4090 | .clr(fbdic_fbd_error_save_clr), | |
4091 | .l1clk(l1clk), | |
4092 | .siclk(siclk), | |
4093 | .soclk(soclk)); | |
4094 | ||
4095 | // Idle frame detect, used for retiring writes | |
4096 | assign fbdic_idle_frame = (&lndskw0_idle_match[12:0]) & ((&lndskw1_idle_match[12:0]) | drif_single_channel_mode) & | |
4097 | ~fbdic_latq_deq & ~fbdic_rddata_vld; | |
4098 | ||
4099 | assign fbdic_clear_wrq_ent = (fbdic_idle_frame & ~fbdic_status_frame | | |
4100 | fbdic_status_frame & ~fbdic_status_parity_error_in & ~fbdic_alert_asserted_in) & | |
4101 | fbdic_err_state[`FBDIC_ERR_IDLE]; | |
4102 | ||
4103 | assign fbdic_chnl_alert_clr = fbdic_err_unrecov | fbdic_err_recov; | |
4104 | mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_24 ff_chnl_alert ( | |
4105 | .scan_in(ff_chnl_alert_scanin), | |
4106 | .scan_out(ff_chnl_alert_scanout), | |
4107 | .din({fbdic0_alert_asserted[11:0],fbdic1_alert_asserted[11:0]}), | |
4108 | .dout({fbdic0_chnl_alert[11:0],fbdic1_chnl_alert[11:0]}), | |
4109 | .en(fbdic_alert_asserted_en), | |
4110 | .clr(fbdic_chnl_alert_clr), | |
4111 | .l1clk(l1clk), | |
4112 | .siclk(siclk), | |
4113 | .soclk(soclk)); | |
4114 | ||
4115 | // Control signals from fbdiwr data path block | |
4116 | assign fbdic_train_seq = ~fbdic_l0_state; | |
4117 | assign fbdic_train_seq_l = fbdic_l0_state; | |
4118 | assign fbdic_data_sel[4:0] = fbdic_loopback[1] ? {fbdic_loopback[0],~fbdic_loopback[0],3'h0} : | |
4119 | fbdic_ibist_data_mode | fbdic_txstart ? 5'h4 : | |
4120 | {3'h0,~fbdic_l0_state,fbdic_l0_state}; | |
4121 | ||
4122 | assign fbdic_special_cmd_l = ~fbdic_special_cmd; | |
4123 | ||
4124 | assign fbdic0_cmd_crc_sel_in[1:0] = {~fbdic0_sb_failover, fbdic0_sb_failover}; | |
4125 | assign fbdic0_data_crc_sel_in[2:0] = {~fbdic0_sb_failover & ~fbdic_special_cmd_in, | |
4126 | fbdic0_sb_failover & ~fbdic_special_cmd_in, | |
4127 | fbdic_special_cmd_in}; | |
4128 | assign fbdic1_cmd_crc_sel_in[1:0] = {~fbdic1_sb_failover, fbdic1_sb_failover}; | |
4129 | assign fbdic1_data_crc_sel_in[2:0] = {~fbdic1_sb_failover & ~fbdic_special_cmd_in, | |
4130 | fbdic1_sb_failover & ~fbdic_special_cmd_in, | |
4131 | fbdic_special_cmd_in}; | |
4132 | ||
4133 | mcu_fbdic_ctl_msff_ctl_macro__width_5 ff_crc_sel0 ( | |
4134 | .scan_in(ff_crc_sel0_scanin), | |
4135 | .scan_out(ff_crc_sel0_scanout), | |
4136 | .din({fbdic0_cmd_crc_sel_in[1:0],fbdic0_data_crc_sel_in[2:0]}), | |
4137 | .dout({fbdic0_cmd_crc_sel[1:0],fbdic0_data_crc_sel[2:0]}), | |
4138 | .l1clk(l1clk), | |
4139 | .siclk(siclk), | |
4140 | .soclk(soclk)); | |
4141 | ||
4142 | mcu_fbdic_ctl_msff_ctl_macro__width_5 ff_crc_sel1 ( | |
4143 | .scan_in(ff_crc_sel1_scanin), | |
4144 | .scan_out(ff_crc_sel1_scanout), | |
4145 | .din({fbdic1_cmd_crc_sel_in[1:0],fbdic1_data_crc_sel_in[2:0]}), | |
4146 | .dout({fbdic1_cmd_crc_sel[1:0],fbdic1_data_crc_sel[2:0]}), | |
4147 | .l1clk(l1clk), | |
4148 | .siclk(siclk), | |
4149 | .soclk(soclk)); | |
4150 | ||
4151 | assign fbdic_ucb_rd_data[65] = drif_ucb_rd_req_vld & drif_ucb_addr[11] & ~fbdic_ucb_rd_data[64] & | |
4152 | drif_ucb_addr[12:0] != 13'h908 | (fbdic_cnfgreg_rddata_vld & ~fbdic_l0_state); | |
4153 | ||
4154 | assign fbdic_ucb_rd_data[64:0] = {65{drif_ucb_rd_req_vld}} & | |
4155 | {{65{drif_ucb_addr[12:0] == 13'h800}} & {1'b1, 56'h0, fbdic_fbd_state[7:0]} | | |
4156 | {65{drif_ucb_addr[12:0] == 13'h808}} & {1'b1, 60'h0, fbdic_sync_ier_enable, fbdic_sync_r[1:0], fbdic_fast_reset} | | |
4157 | {65{drif_ucb_addr[12:0] == 13'h810}} & {1'b1, 62'h0, fbdic_chnl_reset[1:0]} | | |
4158 | {65{drif_ucb_addr[12:0] == 13'h818}} & {1'b1, 60'h0, fbdic_sb2nb_map[3:0]} | | |
4159 | {65{drif_ucb_addr[12:0] == 13'h820}} & {1'b1, 40'h0, fbdic_amb_test_param[23:0]} | | |
4160 | {65{drif_ucb_addr[12:0] == 13'h828}} & {1'b1, 48'h0, fbdic_failover_config[15:0]} | | |
4161 | {65{drif_ucb_addr[12:0] == 13'h830}} & {1'b1, 36'h0, fbdic_elect_idle_detect[27:0]} | | |
4162 | {65{drif_ucb_addr[12:0] == 13'h838}} & {1'b1, 56'h0, fbdic_tdisable_period[7:0]} | | |
4163 | {65{drif_ucb_addr[12:0] == 13'h840}} & {1'b1, 63'h0, fbdic_tdisable_done} | | |
4164 | {65{drif_ucb_addr[12:0] == 13'h848}} & {1'b1, 44'h0, fbdic_tcalibrate_period[19:0]} | | |
4165 | {65{drif_ucb_addr[12:0] == 13'h850}} & {1'b1, 63'h0, fbdic_tcalibrate_done} | | |
4166 | {65{drif_ucb_addr[12:0] == 13'h858}} & {1'b1, 56'h0, fbdic_tclktrain_min[7:0]} | | |
4167 | {65{drif_ucb_addr[12:0] == 13'h860}} & {1'b1, 62'h0, fbdic_tclktrain_done[1:0]} | | |
4168 | {65{drif_ucb_addr[12:0] == 13'h868}} & {1'b1, 56'h0, fbdic_tclktrain_timeout[7:0]} | | |
4169 | {65{drif_ucb_addr[12:0] == 13'h870}} & {1'b1, 62'h0, fbdic_testing_done[1:0]} | | |
4170 | {65{drif_ucb_addr[12:0] == 13'h878}} & {1'b1, 56'h0, fbdic_testing_timeout[7:0]} | | |
4171 | {65{drif_ucb_addr[12:0] == 13'h880}} & {1'b1, 62'h0, fbdic_polling_done[1:0]} | | |
4172 | {65{drif_ucb_addr[12:0] == 13'h888}} & {1'b1, 56'h0, fbdic_polling_timeout[7:0]} | | |
4173 | {65{drif_ucb_addr[12:0] == 13'h890}} & {1'b1, 62'h0, fbdic_config_done[1:0]} | | |
4174 | {65{drif_ucb_addr[12:0] == 13'h898}} & {1'b1, 56'h0, fbdic_config_timeout[7:0]} | | |
4175 | {65{drif_ucb_addr[12:0] == 13'h8a0}} & {1'b1, 48'h0, fbdic_per_rank_cke[15:0]} | | |
4176 | {65{drif_ucb_addr[12:0] == 13'h8a8}} & {1'b1, 57'h0, fbdic_l0s_time[6:0]} | | |
4177 | {65{drif_ucb_addr[12:0] == 13'h8b0}} & {1'b1, 58'h0, fbdic_sync_frm_period[5:0]} | | |
4178 | {65{drif_ucb_addr[12:0] == 13'h8b8}} & {1'b1, 48'h0, fbdic_chnl_read_lat[15:0]} | | |
4179 | {65{drif_ucb_addr[12:0] == 13'h8c0}} & {1'b1, 58'h0, fbdic_chnl_cap[5:0]} | | |
4180 | {65{drif_ucb_addr[12:0] == 13'h8c8}} & {1'b1, 62'h0, fbdic_loopback[1:0]} | | |
4181 | {65{drif_ucb_addr[12:0] == 13'h8d0}} & {1'b1, 34'h0, fbdic_sds_config[29:0]} | | |
4182 | {65{drif_ucb_addr[12:0] == 13'h8d8}} & {1'b1, 16'h0, fbdic_sds_invert[47:0]} | | |
4183 | {65{drif_ucb_addr[12:0] == 13'h8e0}} & {1'b1, 32'h0, fbdic_sds_testcfg[31:0]} | | |
4184 | {65{drif_ucb_addr[12:0] == 13'h8e8}} & {1'b1, 58'h0, fbdic_sds_pll_status[5:0]} | | |
4185 | {65{drif_ucb_addr[12:0] == 13'h8f0}} & {1'b1, 16'h0, fbdic_sds_test_status[47:0]} | | |
4186 | {65{drif_ucb_addr[12:0] == 13'h900}} & {1'b1, 48'h0, fbdic_config_reg_addr[15:2], 2'h0} | | |
4187 | {65{drif_ucb_addr[12:0] == 13'h908}} & {1'b0, 64'h0} | | |
4188 | {65{drif_ucb_addr[12:0] == 13'ha00}} & {1'b1, 16'h0, fbdic_thermal_trip[47:0]} | | |
4189 | {65{drif_ucb_addr[12:0] == 13'hc00}} & {1'b1, fbdic_mcu_syndrome[30], 33'h0, fbdic_mcu_syndrome[29:0]} | | |
4190 | {65{drif_ucb_addr[12:0] == 13'hc08}} & {1'b1, 62'h0, fbdic_inj_err_src[1:0]} | | |
4191 | {65{drif_ucb_addr[12:0] == 13'hc10}} & {1'b1, 47'h0, fbdic_fbr_count[16:0]} | | |
4192 | {65{drif_ucb_addr[12:0] == 13'he80}} & {1'b1, 8'h0, fbdic_sbfibportctl[23:0], fbdic_sbfibpgctl[31:0]} | | |
4193 | {65{drif_ucb_addr[12:0] == 13'he88}} & {1'b1, 8'h0, fbdic_sbfibpattbuf1[23:0], 22'h0, fbdic_sbfibtxmsk[9:0]} | | |
4194 | {65{drif_ucb_addr[12:0] == 13'he90}} & {1'b1, 54'h0, fbdic_sbfibtxshft[9:0]} | | |
4195 | {65{drif_ucb_addr[12:0] == 13'hea0}} & {1'b1, 8'h0, fbdic_sbfibpattbuf2[23:0], 22'h0, fbdic_sbfibpatt2en[9:0]} | | |
4196 | {65{drif_ucb_addr[12:0] == 13'heb0}} & {1'b1, 1'b0, fbdic_sbfibinit[30:0], 8'h0, fbdic_sbibistmisc[23:0]} | | |
4197 | {65{drif_ucb_addr[12:0] == 13'hec0}} & {1'b1, 8'h0, fbdic_nbfibportctl[23:0], fbdic_nbfibpgctl[31:0]} | | |
4198 | {65{drif_ucb_addr[12:0] == 13'hec8}} & {1'b1, 8'h0, fbdic_nbfibpattbuf1[23:0], 32'h0} | | |
4199 | {65{drif_ucb_addr[12:0] == 13'hed0}} & {1'b1, 18'h0, fbdic_nbfibrxmsk[13:0], 32'h0} | | |
4200 | {65{drif_ucb_addr[12:0] == 13'hed8}} & {1'b1, 18'h0, fbdic_nbfibrxshft[13:0], 18'h0, fbdic_nbfibrxlnerr[13:0]} | | |
4201 | {65{drif_ucb_addr[12:0] == 13'hee0}} & {1'b1, 8'h0, fbdic_nbfibpattbuf2[23:0], 18'h0, fbdic_nbfibpatt2en[13:0]}} | | |
4202 | {65{fbdic_cnfgreg_data[32]}} & {1'b1, 32'h0, fbdic_cnfgreg_data[31:0]}; | |
4203 | ||
4204 | // | |
4205 | assign fbdic_error_mode = ~fbdic_err_state[`FBDIC_ERR_IDLE]; | |
4206 | ||
4207 | assign fbdic_scr_frame_req = fbdic_sync_frame_req_d2 & fbdic_err_state[`FBDIC_ERR_SCRST] & fbdic_scr_qual; | |
4208 | ||
4209 | assign fbdic_scr_qual_in = fbdic_sync_frame_req_d2 & fbdic_err_state[`FBDIC_ERR_SCRST] & ~fbdic_scr_qual ? 1'b1 : | |
4210 | fbdic_scr_frame_req ? 1'b0 : fbdic_scr_qual; | |
4211 | ||
4212 | mcu_fbdic_ctl_msff_ctl_macro scr_qual ( | |
4213 | .scan_in(scr_qual_scanin), | |
4214 | .scan_out(scr_qual_scanout), | |
4215 | .din(fbdic_scr_qual_in), | |
4216 | .dout(fbdic_scr_qual), | |
4217 | .l1clk(l1clk), | |
4218 | .siclk(siclk), | |
4219 | .soclk(soclk)); | |
4220 | ||
4221 | // wait 4 cycles after sync frame request to send fast reset (of IER bit in sync frame) | |
4222 | assign fbdic_err_fast_chnl_reset_p2 = (drif_err_state_crc_fr | fbdic_err_state[`FBDIC_ERR_FASTRST]) & | |
4223 | fbdic_sync_frame_req_d2 & ~fbdic_fr_issued; | |
4224 | ||
4225 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_err_fast_chnl_reset ( | |
4226 | .scan_in(ff_err_fast_chnl_reset_scanin), | |
4227 | .scan_out(ff_err_fast_chnl_reset_scanout), | |
4228 | .din({fbdic_err_fast_chnl_reset_p2,fbdic_err_fast_chnl_reset_p1}), | |
4229 | .dout({fbdic_err_fast_chnl_reset_p1,fbdic_err_fast_chnl_reset}), | |
4230 | .l1clk(l1clk), | |
4231 | .siclk(siclk), | |
4232 | .soclk(soclk)); | |
4233 | ||
4234 | assign fbdic_err_fast_reset_done = (drif_err_state_crc_fr | fbdic_err_state[`FBDIC_ERR_FASTRST]) & fbdic_chnl_reset_clr; | |
4235 | ||
4236 | // Check for recoverable and unrecoverable errors | |
4237 | assign fbdic_err_recov_in = (fbdic_err_state[`FBDIC_ERR_STS] & fbdic_status_frame & ~fbdic_status_parity_error_en | | |
4238 | fbdic_err_state[`FBDIC_ERR_STS2] & fbdic_status_frame & ~fbdic_status_parity_error_en | | |
4239 | fbdic_err_state[`FBDIC_ERR_FASTRST_STS] & fbdic_status_frame_d1 & ~fbdic_alert_frame_en & | |
4240 | ~fbdic_status_parity_error_en_d1 | fbdic_cfgrd_crc_error) & fbdic_l0_state; | |
4241 | ||
4242 | mcu_fbdic_ctl_msff_ctl_macro ff_err_recov ( | |
4243 | .scan_in(ff_err_recov_scanin), | |
4244 | .scan_out(ff_err_recov_scanout), | |
4245 | .din(fbdic_err_recov_in), | |
4246 | .dout(fbdic_err_recov), | |
4247 | .l1clk(l1clk), | |
4248 | .siclk(siclk), | |
4249 | .soclk(soclk)); | |
4250 | ||
4251 | // ASW - 04/18/06 | |
4252 | // REMOVED fbdic_alert_asserted_en_d1 because AA should never cause an FBU. | |
4253 | assign fbdic_err_unrecov_in = fbdic_err_state[`FBDIC_ERR_FASTRST_STS] & fbdic_l0_state & fbdic_status_frame_d1 & | |
4254 | (fbdic_alert_frame_en | fbdic_status_parity_error_en_d1); | |
4255 | ||
4256 | mcu_fbdic_ctl_msff_ctl_macro ff_err_unrecov ( | |
4257 | .scan_in(ff_err_unrecov_scanin), | |
4258 | .scan_out(ff_err_unrecov_scanout), | |
4259 | .din(fbdic_err_unrecov_in), | |
4260 | .dout(fbdic_err_unrecov), | |
4261 | .l1clk(l1clk), | |
4262 | .siclk(siclk), | |
4263 | .soclk(soclk)); | |
4264 | ||
4265 | // Error handling state machine | |
4266 | assign inv_fbdic_err_state_in[0] = ~fbdic_err_state_in[0]; | |
4267 | assign fbdic_err_state[0] = ~inv_fbdic_err_state[0]; | |
4268 | ||
4269 | // 0in one_hot -var fbdic_err_state[6:0] | |
4270 | mcu_fbdic_ctl_msff_ctl_macro__width_7 ff_err_state ( | |
4271 | .scan_in(ff_err_state_scanin), | |
4272 | .scan_out(ff_err_state_scanout), | |
4273 | .din({fbdic_err_state_in[6:1],inv_fbdic_err_state_in[0]}), | |
4274 | .dout({fbdic_err_state[6:1],inv_fbdic_err_state[0]}), | |
4275 | .l1clk(l1clk), | |
4276 | .siclk(siclk), | |
4277 | .soclk(soclk)); | |
4278 | ||
4279 | always @(fbdic_alert_asserted or fbdic_alert_frame or fbdic_err_state or fbdic_status_frame or | |
4280 | fbdic_sync_frame_req_d2 or fbdic_mcu_synd_valid or fbdic_chnl_reset_error or | |
4281 | fbdic_scr_response_frame or fbdic_mcu_synd_aa or fbdic_status_parity_error_en or | |
4282 | fbdic_status_parity_error or fbdic_disable_state or fbdic_err_unrecov or fbdic_err_recov or | |
4283 | fbdic_alert_frame_en or fbdic_mcu_synd_fr or fbdic_fbu_error or fbdic_scr_qual) | |
4284 | begin | |
4285 | ||
4286 | fbdic_err_state_in[6:0] = fbdic_err_state[6:0]; | |
4287 | case (1'b1) | |
4288 | ||
4289 | // State 7'h1 | |
4290 | fbdic_err_state[`FBDIC_ERR_IDLE]: begin | |
4291 | ||
4292 | // For status parity error or alert asserted, wait for next status frame | |
4293 | // ignore alert_asserted until software clears valid bit (should be after clearing Alert bits in AMBs) | |
4294 | if (fbdic_status_parity_error & ~(fbdic_fbu_error & fbdic_mcu_synd_valid & fbdic_mcu_synd_fr) | | |
4295 | fbdic_alert_asserted & ~(fbdic_mcu_synd_valid & fbdic_mcu_synd_aa) & ~fbdic_err_recov) | |
4296 | fbdic_err_state_in[6:0] = `FBDIC_ERR_STS_ST; | |
4297 | ||
4298 | // For alert frame, issue SCR immediately | |
4299 | else if (fbdic_alert_frame & ~(fbdic_fbu_error & fbdic_mcu_synd_valid & fbdic_mcu_synd_fr)) | |
4300 | fbdic_err_state_in[6:0] = `FBDIC_ERR_SCRST_ST; | |
4301 | else | |
4302 | fbdic_err_state_in[6:0] = `FBDIC_ERR_IDLE_ST; | |
4303 | end | |
4304 | ||
4305 | // State 7'h2 | |
4306 | fbdic_err_state[`FBDIC_ERR_STS]: begin | |
4307 | ||
4308 | // If status parity error persists, or alert frame is detected, issue SCR | |
4309 | if (fbdic_status_frame & fbdic_status_parity_error_en | fbdic_alert_frame) | |
4310 | fbdic_err_state_in[6:0] = `FBDIC_ERR_SCRST_ST; | |
4311 | ||
4312 | // If status parity error is gone, return to Idle -> FBR | |
4313 | // If alert_asserted is the only error detected, it is logged as FBR | |
4314 | else if (fbdic_status_frame & ~fbdic_status_parity_error_en) | |
4315 | fbdic_err_state_in[6:0] = `FBDIC_ERR_IDLE_ST; | |
4316 | else | |
4317 | fbdic_err_state_in[6:0] = `FBDIC_ERR_STS_ST; | |
4318 | end | |
4319 | ||
4320 | // State 7'h4 | |
4321 | fbdic_err_state[`FBDIC_ERR_SCRST]: begin | |
4322 | ||
4323 | // Issue SCR two cycles after next sync frame request | |
4324 | if (fbdic_sync_frame_req_d2 & fbdic_scr_qual) | |
4325 | fbdic_err_state_in[6:0] = `FBDIC_ERR_SCRST_STS_ST; | |
4326 | else | |
4327 | fbdic_err_state_in[6:0] = `FBDIC_ERR_SCRST_ST; | |
4328 | end | |
4329 | ||
4330 | // State 7'h8 | |
4331 | fbdic_err_state[`FBDIC_ERR_SCRST_STS]: begin | |
4332 | ||
4333 | // When SCR completes, check that Alert frames have stopped | |
4334 | // If they have, wait for next status frame | |
4335 | if (fbdic_scr_response_frame & ~fbdic_alert_frame_en) | |
4336 | fbdic_err_state_in[6:0] = `FBDIC_ERR_STS2_ST; | |
4337 | ||
4338 | // if Alert frames haven't stopped, issue fast reset | |
4339 | else if (fbdic_scr_response_frame & fbdic_alert_frame_en) | |
4340 | fbdic_err_state_in[6:0] = `FBDIC_ERR_FASTRST_ST; | |
4341 | else | |
4342 | fbdic_err_state_in[6:0] = `FBDIC_ERR_SCRST_STS_ST; | |
4343 | end | |
4344 | ||
4345 | // State 7'h10 | |
4346 | fbdic_err_state[`FBDIC_ERR_STS2]: begin | |
4347 | ||
4348 | // Check next status frame for status parity error | |
4349 | // If none, return to Idle (alert may be asserted from Alert frames) | |
4350 | if (fbdic_status_frame & ~fbdic_status_parity_error_en) | |
4351 | fbdic_err_state_in[6:0] = `FBDIC_ERR_IDLE_ST; | |
4352 | ||
4353 | // If status parity error or Alert frames, issue fast reset | |
4354 | else if (fbdic_status_frame & fbdic_status_parity_error_en | | |
4355 | fbdic_alert_frame_en) | |
4356 | fbdic_err_state_in[6:0] = `FBDIC_ERR_FASTRST_ST; | |
4357 | else | |
4358 | fbdic_err_state_in[6:0] = `FBDIC_ERR_STS2_ST; | |
4359 | end | |
4360 | ||
4361 | // State 7'h20 | |
4362 | fbdic_err_state[`FBDIC_ERR_FASTRST]: begin | |
4363 | ||
4364 | // Wait until Fast reset starts | |
4365 | if (fbdic_disable_state) | |
4366 | fbdic_err_state_in[6:0] = `FBDIC_ERR_FASTRST_STS_ST; | |
4367 | else | |
4368 | fbdic_err_state_in[6:0] = `FBDIC_ERR_FASTRST_ST; | |
4369 | end | |
4370 | ||
4371 | // State 7'h40 | |
4372 | fbdic_err_state[`FBDIC_ERR_FASTRST_STS]: begin | |
4373 | ||
4374 | // Wait until Fast reset is completed | |
4375 | if (fbdic_err_unrecov | fbdic_err_recov | fbdic_chnl_reset_error) | |
4376 | fbdic_err_state_in[6:0] = `FBDIC_ERR_IDLE_ST; | |
4377 | else | |
4378 | fbdic_err_state_in[6:0] = `FBDIC_ERR_FASTRST_STS_ST; | |
4379 | end | |
4380 | ||
4381 | default: ; | |
4382 | endcase | |
4383 | end | |
4384 | ||
4385 | /////////////////////////////// | |
4386 | // IBIST Registers | |
4387 | /////////////////////////////// | |
4388 | // SBFIBPORTCTL: 0x680 | |
4389 | assign fbdic_sbfibportctl_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hE80; | |
4390 | assign fbdic_sbfibportctl_in[5:3] = drif_ucb_data[37:35]; | |
4391 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_3 pff_sbfibportctl ( // FS:wmr_protect | |
4392 | .scan_in(pff_sbfibportctl_wmr_scanin), | |
4393 | .scan_out(pff_sbfibportctl_wmr_scanout), | |
4394 | .siclk(aclk_wmr), | |
4395 | .din(fbdic_sbfibportctl_in[5:3]), | |
4396 | .dout(fbdic_sbfibportctl[5:3]), | |
4397 | .en(fbdic_sbfibportctl_en), | |
4398 | .l1clk(l1clk), | |
4399 | .soclk(soclk)); | |
4400 | ||
4401 | // These bits are not used by the transmitter and are read only | |
4402 | assign fbdic_sbfibportctl[23:6] = 18'h0; | |
4403 | assign fbdic_sbfibportctl[1] = 1'b1; | |
4404 | ||
4405 | // Set ibist done flag, write-1 to clear | |
4406 | assign fbdic_ibtx_done_flag_in = ibtx_done ? 1'b1 : | |
4407 | fbdic_sbfibportctl_en & drif_ucb_data[34] | fbdic_ibtx_start_ld ? 1'b0 : | |
4408 | fbdic_ibtx_done_flag; | |
4409 | mcu_fbdic_ctl_msff_ctl_macro pff_ibtx_done_flag ( // FS:wmr_protect | |
4410 | .scan_in(pff_ibtx_done_flag_wmr_scanin), | |
4411 | .scan_out(pff_ibtx_done_flag_wmr_scanout), | |
4412 | .siclk(aclk_wmr), | |
4413 | .din(fbdic_ibtx_done_flag_in), | |
4414 | .dout(fbdic_ibtx_done_flag), | |
4415 | .l1clk(l1clk), | |
4416 | .soclk(soclk)); | |
4417 | ||
4418 | assign fbdic_sbfibportctl[2] = fbdic_ibtx_done_flag; | |
4419 | ||
4420 | // Start ibist transmitter | |
4421 | assign fbdic_ibtx_start_ld = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hE80 & drif_ucb_data[32]; | |
4422 | assign fbdic_ibtx_start_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hE80 | ibtx_done; | |
4423 | assign fbdic_sbfibportctl_in[0] = ibtx_done ? 1'b0 : drif_ucb_data[32]; | |
4424 | mcu_fbdic_ctl_msff_ctl_macro__en_1 pff_ibtx_start ( // FS:wmr_protect | |
4425 | .scan_in(pff_ibtx_start_wmr_scanin), | |
4426 | .scan_out(pff_ibtx_start_wmr_scanout), | |
4427 | .siclk(aclk_wmr), | |
4428 | .din(fbdic_sbfibportctl_in[0]), | |
4429 | .dout(fbdic_sbfibportctl[0]), | |
4430 | .en(fbdic_ibtx_start_en), | |
4431 | .l1clk(l1clk), | |
4432 | .soclk(soclk)); | |
4433 | assign fbdic_ibtx_start = fbdic_sbfibportctl[0]; | |
4434 | ||
4435 | // SBFIBPGCTL: 0x684 | |
4436 | assign fbdic_sbfibpgctl_reset_val[31:0] = {6'hf, 5'h0, 1'b0, 7'hf, 3'h1, 7'hf, 3'h0}; | |
4437 | assign fbdic_sbfibpgctl_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hE80; | |
4438 | assign fbdic_sbfibpgctl_in[31:0] = drif_ucb_data[31:0] ^ fbdic_sbfibpgctl_reset_val[31:0]; | |
4439 | assign fbdic_sbfibpgctl[31:0] = fbdic_sbfibpgctl_out[31:0] ^ fbdic_sbfibpgctl_reset_val[31:0]; | |
4440 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_32 pff_sbfibpgctl ( // FS:wmr_protect | |
4441 | .scan_in(pff_sbfibpgctl_wmr_scanin), | |
4442 | .scan_out(pff_sbfibpgctl_wmr_scanout), | |
4443 | .siclk(aclk_wmr), | |
4444 | .din(fbdic_sbfibpgctl_in[31:0]), | |
4445 | .dout(fbdic_sbfibpgctl_out[31:0]), | |
4446 | .en(fbdic_sbfibpgctl_en), | |
4447 | .l1clk(l1clk), | |
4448 | .soclk(soclk)); | |
4449 | ||
4450 | // SBFIBPATTBUF1: 0x688 | |
4451 | assign fbdic_sbfibpattbuf1_reset_val[23:0] = 24'h02ccfd; | |
4452 | assign fbdic_sbfibpattbuf1_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hE88; | |
4453 | assign fbdic_sbfibpattbuf1_in[23:0] = drif_ucb_data[55:32] ^ fbdic_sbfibpattbuf1_reset_val[23:0]; | |
4454 | assign fbdic_sbfibpattbuf1[23:0] = fbdic_sbfibpattbuf1_out[23:0] ^ fbdic_sbfibpattbuf1_reset_val[23:0]; | |
4455 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_24 pff_sbfibpattbuf1 ( // FS:wmr_protect | |
4456 | .scan_in(pff_sbfibpattbuf1_wmr_scanin), | |
4457 | .scan_out(pff_sbfibpattbuf1_wmr_scanout), | |
4458 | .siclk(aclk_wmr), | |
4459 | .din(fbdic_sbfibpattbuf1_in[23:0]), | |
4460 | .dout(fbdic_sbfibpattbuf1_out[23:0]), | |
4461 | .en(fbdic_sbfibpattbuf1_en), | |
4462 | .l1clk(l1clk), | |
4463 | .soclk(soclk)); | |
4464 | ||
4465 | // SBFIBTXMSK: 0x68C | |
4466 | assign fbdic_sbfibtxmsk_reset_val[9:0] = 10'h3ff; | |
4467 | assign fbdic_sbfibtxmsk_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hE88; | |
4468 | assign fbdic_sbfibtxmsk_in[9:0] = drif_ucb_data[9:0] ^ fbdic_sbfibtxmsk_reset_val[9:0]; | |
4469 | assign fbdic_sbfibtxmsk[9:0] = fbdic_sbfibtxmsk_out[9:0] ^ fbdic_sbfibtxmsk_reset_val[9:0]; | |
4470 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_10 pff_sbfibtxmsk ( // FS:wmr_protect | |
4471 | .scan_in(pff_sbfibtxmsk_wmr_scanin), | |
4472 | .scan_out(pff_sbfibtxmsk_wmr_scanout), | |
4473 | .siclk(aclk_wmr), | |
4474 | .din(fbdic_sbfibtxmsk_in[9:0]), | |
4475 | .dout(fbdic_sbfibtxmsk_out[9:0]), | |
4476 | .en(fbdic_sbfibtxmsk_en), | |
4477 | .l1clk(l1clk), | |
4478 | .soclk(soclk)); | |
4479 | ||
4480 | // SBFIBRXMSK: 0x690 - NOT NEEDED | |
4481 | ||
4482 | // SBFIBTXSHFT: 0x694 | |
4483 | assign fbdic_sbfibtxshft_reset_val[9:0] = 10'h3ff; | |
4484 | assign fbdic_sbfibtxshft_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hE90; | |
4485 | assign fbdic_sbfibtxshft_in[9:0] = drif_ucb_data[9:0] ^ fbdic_sbfibtxshft_reset_val[9:0]; | |
4486 | assign fbdic_sbfibtxshft[9:0] = fbdic_sbfibtxshft_out[9:0] ^ fbdic_sbfibtxshft_reset_val[9:0]; | |
4487 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_10 pff_sbfibtxshft ( // FS:wmr_protect | |
4488 | .scan_in(pff_sbfibtxshft_wmr_scanin), | |
4489 | .scan_out(pff_sbfibtxshft_wmr_scanout), | |
4490 | .siclk(aclk_wmr), | |
4491 | .din(fbdic_sbfibtxshft_in[9:0]), | |
4492 | .dout(fbdic_sbfibtxshft_out[9:0]), | |
4493 | .en(fbdic_sbfibtxshft_en), | |
4494 | .l1clk(l1clk), | |
4495 | .soclk(soclk)); | |
4496 | ||
4497 | // SBFIBRXSHFT: 0x698 - NOT NEEDED | |
4498 | ||
4499 | // SBFIBRXLNERR: 0x69C - NOT NEEDED | |
4500 | ||
4501 | // SBFIBPATTBUF2: 0x6A0 | |
4502 | assign fbdic_sbfibpattbuf2_reset_val[23:0] = 24'hfd3302; | |
4503 | assign fbdic_sbfibpattbuf2_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEA0; | |
4504 | assign fbdic_sbfibpattbuf2_in[23:0] = drif_ucb_data[55:32] ^ fbdic_sbfibpattbuf2_reset_val[23:0]; | |
4505 | assign fbdic_sbfibpattbuf2[23:0] = fbdic_sbfibpattbuf2_out[23:0] ^ fbdic_sbfibpattbuf2_reset_val[23:0]; | |
4506 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_24 pff_sbfibpattbuf2 ( // FS:wmr_protect | |
4507 | .scan_in(pff_sbfibpattbuf2_wmr_scanin), | |
4508 | .scan_out(pff_sbfibpattbuf2_wmr_scanout), | |
4509 | .siclk(aclk_wmr), | |
4510 | .din(fbdic_sbfibpattbuf2_in[23:0]), | |
4511 | .dout(fbdic_sbfibpattbuf2_out[23:0]), | |
4512 | .en(fbdic_sbfibpattbuf2_en), | |
4513 | .l1clk(l1clk), | |
4514 | .soclk(soclk)); | |
4515 | ||
4516 | // SBFIBPATT2EN: 0x6A4 | |
4517 | assign fbdic_sbfibpatt2en_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEA0; | |
4518 | assign fbdic_sbfibpatt2en_in[9:0] = drif_ucb_data[9:0]; | |
4519 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_10 pff_sbfibpatt2en ( // FS:wmr_protect | |
4520 | .scan_in(pff_sbfibpatt2en_wmr_scanin), | |
4521 | .scan_out(pff_sbfibpatt2en_wmr_scanout), | |
4522 | .siclk(aclk_wmr), | |
4523 | .din(fbdic_sbfibpatt2en_in[9:0]), | |
4524 | .dout(fbdic_sbfibpatt2en[9:0]), | |
4525 | .en(fbdic_sbfibpatt2en_en), | |
4526 | .l1clk(l1clk), | |
4527 | .soclk(soclk)); | |
4528 | ||
4529 | // SBFIBINIT: 0x6B0 | |
4530 | assign fbdic_sbfibinit_reset_val[30:0] = {10'hc8,8'h1,10'h100,1'b1,1'b0,1'b0}; | |
4531 | assign fbdic_sbfibinit_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEB0; | |
4532 | assign fbdic_sbfibinit_in[30:0] = drif_ucb_data[62:32] ^ fbdic_sbfibinit_reset_val[30:0]; | |
4533 | assign fbdic_sbfibinit[30:0] = fbdic_sbfibinit_out[30:0] ^ fbdic_sbfibinit_reset_val[30:0]; | |
4534 | ||
4535 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_30 pff_sbfibinit ( // FS:wmr_protect | |
4536 | .scan_in(pff_sbfibinit_wmr_scanin), | |
4537 | .scan_out(pff_sbfibinit_wmr_scanout), | |
4538 | .siclk(aclk_wmr), | |
4539 | .din({fbdic_sbfibinit_in[30:2],fbdic_sbfibinit_in[0]}), | |
4540 | .dout({fbdic_sbfibinit_out[30:2],fbdic_sbfibinit_out[0]}), | |
4541 | .en(fbdic_sbfibinit_en), | |
4542 | .l1clk(l1clk), | |
4543 | .soclk(soclk)); | |
4544 | ||
4545 | assign fbdic_sbts0cnt[9:0] = fbdic_sbfibinit[30:21] - 10'h1; | |
4546 | assign fbdic_sbts1cnt[9:0] = {2'h0, fbdic_sbfibinit[20:13] - 8'h1}; | |
4547 | assign fbdic_sbdiscnt[9:0] = fbdic_sbfibinit[12:3]; | |
4548 | assign fbdic_sbcaliben = fbdic_sbfibinit[2]; | |
4549 | assign fbdic_sbfibinit_out[1] = 1'b0; | |
4550 | assign fbdic_sbibistiniten = fbdic_sbfibinit[0]; | |
4551 | ||
4552 | assign fbdic_sbts_cnt_decr = ts0_cnt[3:0] == 4'hb | ibtx_done | ts2_cnt[2:0] == 3'h5 | ts3_cnt[2:0] == 3'h5; | |
4553 | assign fbdic_sbts_cnt_in[9:0] = fbdic_ibtx_start | fbdic_ibist_done ? | |
4554 | (fbdic_fbd_state_in[2:0] == 3'h2 & fbdic_fbd_state_en ? fbdic_sbts0cnt[9:0] : | |
4555 | fbdic_fbd_state_in[2:0] == 3'h3 & fbdic_fbd_state_en ? fbdic_sbts1cnt[9:0] : | |
4556 | fbdic_fbd_state_in[2:1] == 2'h2 & fbdic_fbd_state_en ? 10'hf : | |
4557 | fbdic_sbts_cnt[9:0] == 10'h0 ? 10'h0 : | |
4558 | fbdic_sbts_cnt_decr ? fbdic_sbts_cnt[9:0] - 10'h1 : fbdic_sbts_cnt[9:0]) : 10'h0; | |
4559 | ||
4560 | mcu_fbdic_ctl_msff_ctl_macro__width_10 ff_sbts_cnt ( | |
4561 | .scan_in(ff_sbts_cnt_scanin), | |
4562 | .scan_out(ff_sbts_cnt_scanout), | |
4563 | .din(fbdic_sbts_cnt_in[9:0]), | |
4564 | .dout(fbdic_sbts_cnt[9:0]), | |
4565 | .l1clk(l1clk), | |
4566 | .siclk(siclk), | |
4567 | .soclk(soclk)); | |
4568 | ||
4569 | // SBIBISTMISC: 0x6B4 | |
4570 | assign fbdic_sbibistmisc_reset_val[23:0] = 24'h061a80; | |
4571 | assign fbdic_sbibistmisc_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEB0; | |
4572 | assign fbdic_sbibistmisc_in[23:0] = drif_ucb_data[23:0] ^ fbdic_sbibistmisc_reset_val[23:0]; | |
4573 | assign fbdic_sbibistmisc[23:0] = fbdic_sbibistmisc_out[23:0] ^ fbdic_sbibistmisc_reset_val[23:0]; | |
4574 | ||
4575 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_24 pff_sbibistmisc ( // FS:wmr_protect | |
4576 | .scan_in(pff_sbibistmisc_wmr_scanin), | |
4577 | .scan_out(pff_sbibistmisc_wmr_scanout), | |
4578 | .siclk(aclk_wmr), | |
4579 | .din(fbdic_sbibistmisc_in[23:0]), | |
4580 | .dout(fbdic_sbibistmisc_out[23:0]), | |
4581 | .en(fbdic_sbibistmisc_en), | |
4582 | .l1clk(l1clk), | |
4583 | .soclk(soclk)); | |
4584 | ||
4585 | assign fbdic_ibist_ambid[3:0] = fbdic_sbibistmisc[23:20]; | |
4586 | assign fbdic_sbibistcalperiod[19:0] = fbdic_sbibistmisc[19:0]; | |
4587 | ||
4588 | //////////////////////////////////////////////////////////// | |
4589 | ||
4590 | // NBFIBPORTCTL: 0x6C0 | |
4591 | assign fbdic_nbfibportctl_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEC0; | |
4592 | assign fbdic_nbfibportctl_in[5:3] = drif_ucb_data[37:35]; | |
4593 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_3 pff_nbfibportctl ( // FS:wmr_protect | |
4594 | .scan_in(pff_nbfibportctl_wmr_scanin), | |
4595 | .scan_out(pff_nbfibportctl_wmr_scanout), | |
4596 | .siclk(aclk_wmr), | |
4597 | .din(fbdic_nbfibportctl_in[5:3]), | |
4598 | .dout(fbdic_nbfibportctl[5:3]), | |
4599 | .en(fbdic_nbfibportctl_en), | |
4600 | .l1clk(l1clk), | |
4601 | .soclk(soclk)); | |
4602 | ||
4603 | // Read only and Write-1 to clear bits bits | |
4604 | assign fbdic_nbfibportctl[23:22] = 2'h0; | |
4605 | assign fbdic_nbfibportctl[21:12] = ibrx_errcnt[9:0]; | |
4606 | assign fbdic_nbfibportctl[11:8] = ibrx_errlnnum[3:0]; | |
4607 | assign fbdic_nbfibportctl[7:6] = ibrx_errstat[1:0]; | |
4608 | assign fbdic_nbfibportctl[1] = 1'b0; | |
4609 | ||
4610 | assign fbdic_ibrx_done_flag_in = ibrx_done ? 1'b1 : | |
4611 | fbdic_nbfibportctl_en & drif_ucb_data[34] | fbdic_ibrx_start_ld ? 1'b0 : | |
4612 | fbdic_ibrx_done_flag; | |
4613 | mcu_fbdic_ctl_msff_ctl_macro pff_ibrx_done_flag ( | |
4614 | .scan_in(pff_ibrx_done_flag_scanin), | |
4615 | .scan_out(pff_ibrx_done_flag_scanout), | |
4616 | .din(fbdic_ibrx_done_flag_in), | |
4617 | .dout(fbdic_ibrx_done_flag), | |
4618 | .l1clk(l1clk), | |
4619 | .siclk(siclk), | |
4620 | .soclk(soclk)); | |
4621 | assign fbdic_nbfibportctl[2] = fbdic_ibrx_done_flag; | |
4622 | ||
4623 | // start IBIST receive engine: wait for start delimiter | |
4624 | assign fbdic_ibrx_start_ld = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEC0 & drif_ucb_data[32]; | |
4625 | assign fbdic_ibrx_start_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEC0 | ibrx_done; | |
4626 | assign fbdic_nbfibportctl_in[0] = ibrx_done ? 1'b0 : drif_ucb_data[32]; | |
4627 | mcu_fbdic_ctl_msff_ctl_macro__en_1 pff_ibrx_start ( // FS:wmr_protect | |
4628 | .scan_in(pff_ibrx_start_wmr_scanin), | |
4629 | .scan_out(pff_ibrx_start_wmr_scanout), | |
4630 | .siclk(aclk_wmr), | |
4631 | .din(fbdic_nbfibportctl_in[0]), | |
4632 | .dout(fbdic_nbfibportctl[0]), | |
4633 | .en(fbdic_ibrx_start_en), | |
4634 | .l1clk(l1clk), | |
4635 | .soclk(soclk)); | |
4636 | assign fbdic_ibrx_start = fbdic_nbfibportctl[0]; | |
4637 | ||
4638 | // NBFIBPGCTL: 0x6C4 | |
4639 | assign fbdic_nbfibpgctl_reset_val[31:0] = {6'hf, 5'h0, 1'b0, 7'hf, 3'h1, 7'hf, 3'h0}; | |
4640 | assign fbdic_nbfibpgctl_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEC0; | |
4641 | assign fbdic_nbfibpgctl_in[31:0] = drif_ucb_data[31:0] ^ fbdic_nbfibpgctl_reset_val[31:0]; | |
4642 | assign fbdic_nbfibpgctl[31:0] = fbdic_nbfibpgctl_out[31:0] ^ fbdic_nbfibpgctl_reset_val[31:0]; | |
4643 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_32 pff_nbfibpgctl ( // FS:wmr_protect | |
4644 | .scan_in(pff_nbfibpgctl_wmr_scanin), | |
4645 | .scan_out(pff_nbfibpgctl_wmr_scanout), | |
4646 | .siclk(aclk_wmr), | |
4647 | .din(fbdic_nbfibpgctl_in[31:0]), | |
4648 | .dout(fbdic_nbfibpgctl_out[31:0]), | |
4649 | .en(fbdic_nbfibpgctl_en), | |
4650 | .l1clk(l1clk), | |
4651 | .soclk(soclk)); | |
4652 | ||
4653 | // NBFIBPATTBUF1: 0x6C8 | |
4654 | assign fbdic_nbfibpattbuf1_reset_val[23:0] = 24'h02ccfd; | |
4655 | assign fbdic_nbfibpattbuf1_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEC8; | |
4656 | assign fbdic_nbfibpattbuf1_in[23:0] = drif_ucb_data[55:32] ^ fbdic_nbfibpattbuf1_reset_val[23:0]; | |
4657 | assign fbdic_nbfibpattbuf1[23:0] = fbdic_nbfibpattbuf1_out[23:0] ^ fbdic_nbfibpattbuf1_reset_val[23:0]; | |
4658 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_24 pff_nbfibpattbuf1 ( // FS:wmr_protect | |
4659 | .scan_in(pff_nbfibpattbuf1_wmr_scanin), | |
4660 | .scan_out(pff_nbfibpattbuf1_wmr_scanout), | |
4661 | .siclk(aclk_wmr), | |
4662 | .din(fbdic_nbfibpattbuf1_in[23:0]), | |
4663 | .dout(fbdic_nbfibpattbuf1_out[23:0]), | |
4664 | .en(fbdic_nbfibpattbuf1_en), | |
4665 | .l1clk(l1clk), | |
4666 | .soclk(soclk)); | |
4667 | ||
4668 | // NBFIBTXMSK: 0x6CC - NOT NEEDED | |
4669 | ||
4670 | // NBFIBRXMSK: 0x6D0 | |
4671 | assign fbdic_nbfibrxmsk_reset_val[13:0] = 14'h3fff; | |
4672 | assign fbdic_nbfibrxmsk_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hED0; | |
4673 | assign fbdic_nbfibrxmsk_in[13:0] = drif_ucb_data[45:32] ^ fbdic_nbfibrxmsk_reset_val[13:0]; | |
4674 | assign fbdic_nbfibrxmsk[13:0] = fbdic_nbfibrxmsk_out[13:0] ^ fbdic_nbfibrxmsk_reset_val[13:0]; | |
4675 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_14 pff_nbfibrxmsk ( // FS:wmr_protect | |
4676 | .scan_in(pff_nbfibrxmsk_wmr_scanin), | |
4677 | .scan_out(pff_nbfibrxmsk_wmr_scanout), | |
4678 | .siclk(aclk_wmr), | |
4679 | .din(fbdic_nbfibrxmsk_in[13:0]), | |
4680 | .dout(fbdic_nbfibrxmsk_out[13:0]), | |
4681 | .en(fbdic_nbfibrxmsk_en), | |
4682 | .l1clk(l1clk), | |
4683 | .soclk(soclk)); | |
4684 | ||
4685 | // NBFIBTXSHFT: 0x6D4 - NOT NEEDED | |
4686 | ||
4687 | // NBFIBRXSHFT: 0x6D8 | |
4688 | assign fbdic_nbfibrxshft_reset_val[13:0] = 14'h3fff; | |
4689 | assign fbdic_nbfibrxshft_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hED8; | |
4690 | assign fbdic_nbfibrxshft_in[13:0] = drif_ucb_data[45:32] ^ fbdic_nbfibrxshft_reset_val[13:0]; | |
4691 | assign fbdic_nbfibrxshft[13:0] = fbdic_nbfibrxshft_out[13:0] ^ fbdic_nbfibrxshft_reset_val[13:0]; | |
4692 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_14 pff_nbfibrxshft ( // FS:wmr_protect | |
4693 | .scan_in(pff_nbfibrxshft_wmr_scanin), | |
4694 | .scan_out(pff_nbfibrxshft_wmr_scanout), | |
4695 | .siclk(aclk_wmr), | |
4696 | .din(fbdic_nbfibrxshft_in[13:0]), | |
4697 | .dout(fbdic_nbfibrxshft_out[13:0]), | |
4698 | .en(fbdic_nbfibrxshft_en), | |
4699 | .l1clk(l1clk), | |
4700 | .soclk(soclk)); | |
4701 | ||
4702 | // NBFIBRXLNERR: 0x6DC | |
4703 | assign fbdic_nbfibrxlnerr[13:0] = ibrx_rxerrstat[13:0]; | |
4704 | ||
4705 | // NBFIBPATTBUF2: 0x6E0 | |
4706 | assign fbdic_nbfibpattbuf2_reset_val[23:0] = 24'hfd3302; | |
4707 | assign fbdic_nbfibpattbuf2_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEE0; | |
4708 | assign fbdic_nbfibpattbuf2_in[23:0] = drif_ucb_data[55:32] ^ fbdic_nbfibpattbuf2_reset_val[23:0]; | |
4709 | assign fbdic_nbfibpattbuf2[23:0] = fbdic_nbfibpattbuf2_out[23:0] ^ fbdic_nbfibpattbuf2_reset_val[23:0]; | |
4710 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_24 pff_nbfibpattbuf2 ( // FS:wmr_protect | |
4711 | .scan_in(pff_nbfibpattbuf2_wmr_scanin), | |
4712 | .scan_out(pff_nbfibpattbuf2_wmr_scanout), | |
4713 | .siclk(aclk_wmr), | |
4714 | .din(fbdic_nbfibpattbuf2_in[23:0]), | |
4715 | .dout(fbdic_nbfibpattbuf2_out[23:0]), | |
4716 | .en(fbdic_nbfibpattbuf2_en), | |
4717 | .l1clk(l1clk), | |
4718 | .soclk(soclk)); | |
4719 | ||
4720 | // NBFIBPATT2EN: 0x6E4 | |
4721 | assign fbdic_nbfibpatt2en_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'hEE0; | |
4722 | assign fbdic_nbfibpatt2en_in[13:0] = drif_ucb_data[13:0]; | |
4723 | mcu_fbdic_ctl_msff_ctl_macro__en_1__width_14 pff_nbfibpatt2en ( // FS:wmr_protect | |
4724 | .scan_in(pff_nbfibpatt2en_wmr_scanin), | |
4725 | .scan_out(pff_nbfibpatt2en_wmr_scanout), | |
4726 | .siclk(aclk_wmr), | |
4727 | .din(fbdic_nbfibpatt2en_in[13:0]), | |
4728 | .dout(fbdic_nbfibpatt2en[13:0]), | |
4729 | .en(fbdic_nbfibpatt2en_en), | |
4730 | .l1clk(l1clk), | |
4731 | .soclk(soclk)); | |
4732 | ||
4733 | // NBFIBINIT: 0x6F0 - NOT NEEDED | |
4734 | ||
4735 | // NBIBISTMISC: 0x6F4 - NOT NEEDED | |
4736 | ||
4737 | // IBIST Transmit Engine | |
4738 | assign fbdic_ibist_data_mode_in = fbdic_txstart ? 1'b1 : ibtx_done ? 1'b0 : fbdic_ibist_data_mode; | |
4739 | mcu_fbdic_ctl_msff_ctl_macro ff_ibist_data ( | |
4740 | .scan_in(ff_ibist_data_scanin), | |
4741 | .scan_out(ff_ibist_data_scanout), | |
4742 | .din(fbdic_ibist_data_mode_in), | |
4743 | .dout(fbdic_ibist_data_mode), | |
4744 | .l1clk(l1clk), | |
4745 | .siclk(siclk), | |
4746 | .soclk(soclk)); | |
4747 | ||
4748 | assign fbdic_ibist_done_in = ibtx_done ? 1'b1 : | |
4749 | fbdic_ibtx_start_ld | fbdic_fbd_state[2:1] == 2'h3 ? 1'b0 : fbdic_ibist_done; | |
4750 | mcu_fbdic_ctl_msff_ctl_macro ff_ibist_done ( | |
4751 | .scan_in(ff_ibist_done_scanin), | |
4752 | .scan_out(ff_ibist_done_scanout), | |
4753 | .din(fbdic_ibist_done_in), | |
4754 | .dout(fbdic_ibist_done), | |
4755 | .l1clk(l1clk), | |
4756 | .siclk(siclk), | |
4757 | .soclk(soclk)); | |
4758 | ||
4759 | assign fbdic_txstart = fbdic_sbfibportctl[0] & (ts1_cnt[5:0] == 6'h3) & ~fbdic_ibist_data_mode; | |
4760 | ||
4761 | // IBIST Receive Engine | |
4762 | assign fbdic_ibrx_data[39:0] = fbdic_ibrx_data_sel ? lndskw1_data[39:0] : lndskw0_data[39:0]; | |
4763 | ||
4764 | assign fbdic_ibrx_lane0_s0_match = fbdic_ibrx_data[11:0] == 12'h543; | |
4765 | assign fbdic_ibrx_lane1_s0_match = fbdic_ibrx_data[23:12] == 12'h543; | |
4766 | assign fbdic_ibrx_lane2_s0_match = fbdic_ibrx_data[35:24] == 12'h543; | |
4767 | assign fbdic_ibrx_lane0_s1_match = fbdic_ibrx_data[11:0] == 12'h876; | |
4768 | assign fbdic_ibrx_lane1_s1_match = fbdic_ibrx_data[23:12] == 12'h876; | |
4769 | assign fbdic_ibrx_lane2_s1_match = fbdic_ibrx_data[35:24] == 12'h876; | |
4770 | ||
4771 | assign fbdic_ibrx_s0_match = fbdic_ibrx_lane0_s0_match & fbdic_ibrx_lane1_s0_match | | |
4772 | fbdic_ibrx_lane1_s0_match & fbdic_ibrx_lane2_s0_match | | |
4773 | fbdic_ibrx_lane0_s0_match & fbdic_ibrx_lane2_s0_match; | |
4774 | assign fbdic_ibrx_s1_match = fbdic_ibrx_lane0_s1_match & fbdic_ibrx_lane1_s1_match | | |
4775 | fbdic_ibrx_lane1_s1_match & fbdic_ibrx_lane2_s1_match | | |
4776 | fbdic_ibrx_lane0_s1_match & fbdic_ibrx_lane2_s1_match; | |
4777 | ||
4778 | assign fbdic_s0_s1_s0_s1 = fbdic_s0_s1_s0_d1 & fbdic_ibrx_s1_match; | |
4779 | assign fbdic_s0_s1_s0 = fbdic_s0_s1_d1 & fbdic_ibrx_s0_match; | |
4780 | assign fbdic_s0_s1 = fbdic_s0_d1 & fbdic_ibrx_s1_match; | |
4781 | ||
4782 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_rx_s0s1_match_dly ( | |
4783 | .scan_in(ff_rx_s0s1_match_dly_scanin), | |
4784 | .scan_out(ff_rx_s0s1_match_dly_scanout), | |
4785 | .din({fbdic_ibrx_s0_match,fbdic_s0_s1,fbdic_s0_s1_s0}), | |
4786 | .dout({fbdic_s0_d1,fbdic_s0_s1_d1,fbdic_s0_s1_s0_d1}), | |
4787 | .l1clk(l1clk), | |
4788 | .siclk(siclk), | |
4789 | .soclk(soclk)); | |
4790 | ||
4791 | assign fbdic_rxstart = fbdic_s0_s1_s0_s1 & (ibrx_errstat[1:0] == 2'h1); | |
4792 | ||
4793 | mcu_ibist_ctl ibist ( | |
4794 | .scan_in(ibist_scanin), | |
4795 | .scan_out(ibist_scanout), | |
4796 | .l1clk(l1clk), | |
4797 | .fbdic_errcnt_clr(drif_ucb_data[53:44]), | |
4798 | .fbdic_errstat_clr(drif_ucb_data[39:38]), | |
4799 | .ibist_rxdata({fbdird_ibrx_data[167:40],fbdic_ibrx_data[39:0]}), | |
4800 | .ibist_txdata(ibist_txdata[119:0]), | |
4801 | .ibtx_done(ibtx_done), | |
4802 | .ibrx_done(ibrx_done), | |
4803 | .ibrx_rxerrstat(ibrx_rxerrstat[13:0]), | |
4804 | .ibrx_errcnt(ibrx_errcnt[9:0]), | |
4805 | .ibrx_errlnnum(ibrx_errlnnum[3:0]), | |
4806 | .ibrx_errstat(ibrx_errstat[1:0]), | |
4807 | .fbdic_sbfibportctl(fbdic_sbfibportctl[23:0]), | |
4808 | .fbdic_sbfibpgctl(fbdic_sbfibpgctl[31:0]), | |
4809 | .fbdic_sbfibpattbuf1(fbdic_sbfibpattbuf1[23:0]), | |
4810 | .fbdic_sbfibtxmsk(fbdic_sbfibtxmsk[9:0]), | |
4811 | .fbdic_sbfibtxshft(fbdic_sbfibtxshft[9:0]), | |
4812 | .fbdic_sbfibpattbuf2(fbdic_sbfibpattbuf2[23:0]), | |
4813 | .fbdic_sbfibpatt2en(fbdic_sbfibpatt2en[9:0]), | |
4814 | .fbdic_txstart(fbdic_txstart), | |
4815 | .fbdic_nbfibportctl(fbdic_nbfibportctl[23:0]), | |
4816 | .fbdic_nbfibpgctl(fbdic_nbfibpgctl[31:0]), | |
4817 | .fbdic_nbfibpattbuf1(fbdic_nbfibpattbuf1[23:0]), | |
4818 | .fbdic_nbfibrxmsk(fbdic_nbfibrxmsk[13:0]), | |
4819 | .fbdic_nbfibrxshft(fbdic_nbfibrxshft[13:0]), | |
4820 | .fbdic_nbfibrxlnerr(fbdic_nbfibrxlnerr[13:0]), | |
4821 | .fbdic_nbfibpattbuf2(fbdic_nbfibpattbuf2[23:0]), | |
4822 | .fbdic_nbfibpatt2en(fbdic_nbfibpatt2en[13:0]), | |
4823 | .fbdic_rxstart(fbdic_rxstart), | |
4824 | .fbdic_ibrx_start_ld(fbdic_ibrx_start_ld), | |
4825 | .fbdic_nbfibportctl_en(fbdic_nbfibportctl_en), | |
4826 | .tcu_aclk(tcu_aclk), | |
4827 | .tcu_bclk(tcu_bclk), | |
4828 | .tcu_scan_en(tcu_scan_en) | |
4829 | ); | |
4830 | ||
4831 | // Error Injection | |
4832 | mcu_fbdic_ctl_msff_ctl_macro__width_2 ff_err_fbxi ( | |
4833 | .scan_in(ff_err_fbxi_scanin), | |
4834 | .scan_out(ff_err_fbxi_scanout), | |
4835 | .din({rdata_err_fbri,rdata_err_fbui}), | |
4836 | .dout({fbdic_err_fbri,fbdic_err_fbui}), | |
4837 | .l1clk(l1clk), | |
4838 | .siclk(siclk), | |
4839 | .soclk(soclk)); | |
4840 | ||
4841 | assign fbdic_fbr_injected_in = fbdic_err_fbri & (fbdic_crc_error & fbdic_inj_crc_err | | |
4842 | fbdic_status_parity_error & fbdic_inj_sfp_err | | |
4843 | fbdic_alert_asserted & fbdic_inj_aa_err | | |
4844 | fbdic_alert_frame & fbdic_inj_af_err) ? 1'b1 : | |
4845 | rdpctl_crc_recov_err | fbdic_err_recov ? 1'b0 : fbdic_fbr_injected; | |
4846 | mcu_fbdic_ctl_msff_ctl_macro ff_fbr_injected ( | |
4847 | .scan_in(ff_fbr_injected_scanin), | |
4848 | .scan_out(ff_fbr_injected_scanout), | |
4849 | .din(fbdic_fbr_injected_in), | |
4850 | .dout(fbdic_fbr_injected), | |
4851 | .l1clk(l1clk), | |
4852 | .siclk(siclk), | |
4853 | .soclk(soclk)); | |
4854 | ||
4855 | assign fbdic_inj_crc_err = fbdic_inj_err_src[1:0] == 2'h0 & (fbdic_err_fbri & ~fbdic_fbr_injected | fbdic_err_fbui); | |
4856 | assign fbdic_inj_af_err = fbdic_inj_err_src[1:0] == 2'h1 & (fbdic_err_fbri & ~fbdic_fbr_injected | fbdic_err_fbui); | |
4857 | assign fbdic_inj_aa_err = fbdic_inj_err_src[1:0] == 2'h2 & (fbdic_err_fbri & ~fbdic_fbr_injected | fbdic_err_fbui); | |
4858 | assign fbdic_inj_sfp_err = fbdic_inj_err_src[1:0] == 2'h3 & (fbdic_err_fbri & ~fbdic_fbr_injected | fbdic_err_fbui); | |
4859 | ||
4860 | // DTM | |
4861 | cl_sc1_clksyncff_4x ff_serdes_dtm ( | |
4862 | .si(ff_serdes_dtm_scanin), | |
4863 | .so(ff_serdes_dtm_scanout), | |
4864 | .d(ccu_serdes_dtm), | |
4865 | .q(fbdic_serdes_dtm_out), | |
4866 | .l1clk(l1clk), | |
4867 | .siclk(siclk), | |
4868 | .soclk(soclk)); | |
4869 | ||
4870 | assign fbdic_serdes_dtm = fbdic_serdes_dtm_out | rdpctl_dtm_atspeed; | |
4871 | ||
4872 | assign fbdic_dtm_zero_cnt_in[2:0] = fbdic_dtm_state & | |
4873 | lndskw0_data[35:0] == 36'h0 & | |
4874 | lndskw1_data[35:0] == 36'h0 ? fbdic_dtm_zero_cnt[2:0] + 3'h1 : 3'h0; | |
4875 | ||
4876 | mcu_fbdic_ctl_msff_ctl_macro__width_3 ff_dtm_zero_cnt ( | |
4877 | .scan_in(ff_dtm_zero_cnt_scanin), | |
4878 | .scan_out(ff_dtm_zero_cnt_scanout), | |
4879 | .din(fbdic_dtm_zero_cnt_in[2:0]), | |
4880 | .dout(fbdic_dtm_zero_cnt[2:0]), | |
4881 | .l1clk(l1clk), | |
4882 | .siclk(siclk), | |
4883 | .soclk(soclk)); | |
4884 | ||
4885 | assign fbdic_dtm_state_in = fbdic_dtm_fbd_state2_en ? 1'b1 : | |
4886 | fbdic_dtm_fbd_state6_en | fbdic_dtm_fbd_state0_en ? 1'b0 : fbdic_dtm_state; | |
4887 | ||
4888 | assign fbdic_dtm_fbd_state0_en = ~fbdic_serdes_dtm & fbdic_dtm_state; | |
4889 | assign fbdic_dtm_fbd_state2_en = fbdic_serdes_dtm & fbdic0_lane_align & (fbdic1_lane_align | drif_single_channel_mode) & | |
4890 | ~fbdic_dtm_state & fbdic_disable_state; | |
4891 | assign fbdic_dtm_fbd_state6_en = fbdic_dtm_zero_cnt[2:0] == 3'h4 & fbdic_dtm_state; | |
4892 | ||
4893 | mcu_fbdic_ctl_msff_ctl_macro__width_1 ff_dtm_state ( | |
4894 | .scan_in(ff_dtm_state_scanin), | |
4895 | .scan_out(ff_dtm_state_scanout), | |
4896 | .din(fbdic_dtm_state_in), | |
4897 | .dout(fbdic_dtm_state), | |
4898 | .l1clk(l1clk), | |
4899 | .siclk(siclk), | |
4900 | .soclk(soclk)); | |
4901 | ||
4902 | // Select line for CRC/DBG mux in ucb | |
4903 | assign fbdic_srds_dtm_muxsel_in = fbdic_serdes_dtm_out & ~rdpctl_dtm_atspeed; | |
4904 | ||
4905 | mcu_fbdic_ctl_msff_ctl_macro ff_srds_dtm_muxsel ( | |
4906 | .scan_in(ff_srds_dtm_muxsel_scanin), | |
4907 | .scan_out(ff_srds_dtm_muxsel_scanout), | |
4908 | .din(fbdic_srds_dtm_muxsel_in), | |
4909 | .dout(fbdic_srds_dtm_muxsel), | |
4910 | .l1clk(l1clk), | |
4911 | .siclk(siclk), | |
4912 | .soclk(soclk)); | |
4913 | ||
4914 | // spare gates | |
4915 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
4916 | .siclk(siclk), | |
4917 | .soclk(soclk), | |
4918 | .si(si_0), | |
4919 | .so(so_0), | |
4920 | .d(1'b0), | |
4921 | .q(spare0_flop_unused)); | |
4922 | assign si_0 = spares_scanin; | |
4923 | ||
4924 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
4925 | .out(spare0_buf_32x_unused)); | |
4926 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
4927 | .in1(1'b1), | |
4928 | .in2(1'b1), | |
4929 | .out(spare0_nand3_8x_unused)); | |
4930 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
4931 | .out(spare0_inv_8x_unused)); | |
4932 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
4933 | .in01(1'b1), | |
4934 | .in10(1'b1), | |
4935 | .in11(1'b1), | |
4936 | .out(spare0_aoi22_4x_unused)); | |
4937 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
4938 | .out(spare0_buf_8x_unused)); | |
4939 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
4940 | .in01(1'b1), | |
4941 | .in10(1'b1), | |
4942 | .in11(1'b1), | |
4943 | .out(spare0_oai22_4x_unused)); | |
4944 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
4945 | .out(spare0_inv_16x_unused)); | |
4946 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
4947 | .in1(1'b1), | |
4948 | .out(spare0_nand2_16x_unused)); | |
4949 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
4950 | .in1(1'b0), | |
4951 | .in2(1'b0), | |
4952 | .out(spare0_nor3_4x_unused)); | |
4953 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
4954 | .in1(1'b1), | |
4955 | .out(spare0_nand2_8x_unused)); | |
4956 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
4957 | .out(spare0_buf_16x_unused)); | |
4958 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
4959 | .in1(1'b0), | |
4960 | .out(spare0_nor2_16x_unused)); | |
4961 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
4962 | .out(spare0_inv_32x_unused)); | |
4963 | ||
4964 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
4965 | .siclk(siclk), | |
4966 | .soclk(soclk), | |
4967 | .si(si_1), | |
4968 | .so(so_1), | |
4969 | .d(1'b0), | |
4970 | .q(spare1_flop_unused)); | |
4971 | assign si_1 = so_0; | |
4972 | ||
4973 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
4974 | .out(spare1_buf_32x_unused)); | |
4975 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
4976 | .in1(1'b1), | |
4977 | .in2(1'b1), | |
4978 | .out(spare1_nand3_8x_unused)); | |
4979 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
4980 | .out(spare1_inv_8x_unused)); | |
4981 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
4982 | .in01(1'b1), | |
4983 | .in10(1'b1), | |
4984 | .in11(1'b1), | |
4985 | .out(spare1_aoi22_4x_unused)); | |
4986 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
4987 | .out(spare1_buf_8x_unused)); | |
4988 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
4989 | .in01(1'b1), | |
4990 | .in10(1'b1), | |
4991 | .in11(1'b1), | |
4992 | .out(spare1_oai22_4x_unused)); | |
4993 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
4994 | .out(spare1_inv_16x_unused)); | |
4995 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
4996 | .in1(1'b1), | |
4997 | .out(spare1_nand2_16x_unused)); | |
4998 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
4999 | .in1(1'b0), | |
5000 | .in2(1'b0), | |
5001 | .out(spare1_nor3_4x_unused)); | |
5002 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
5003 | .in1(1'b1), | |
5004 | .out(spare1_nand2_8x_unused)); | |
5005 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
5006 | .out(spare1_buf_16x_unused)); | |
5007 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
5008 | .in1(1'b0), | |
5009 | .out(spare1_nor2_16x_unused)); | |
5010 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
5011 | .out(spare1_inv_32x_unused)); | |
5012 | ||
5013 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
5014 | .siclk(siclk), | |
5015 | .soclk(soclk), | |
5016 | .si(si_2), | |
5017 | .so(so_2), | |
5018 | .d(1'b0), | |
5019 | .q(spare2_flop_unused)); | |
5020 | assign si_2 = so_1; | |
5021 | ||
5022 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
5023 | .out(spare2_buf_32x_unused)); | |
5024 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
5025 | .in1(1'b1), | |
5026 | .in2(1'b1), | |
5027 | .out(spare2_nand3_8x_unused)); | |
5028 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
5029 | .out(spare2_inv_8x_unused)); | |
5030 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
5031 | .in01(1'b1), | |
5032 | .in10(1'b1), | |
5033 | .in11(1'b1), | |
5034 | .out(spare2_aoi22_4x_unused)); | |
5035 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
5036 | .out(spare2_buf_8x_unused)); | |
5037 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
5038 | .in01(1'b1), | |
5039 | .in10(1'b1), | |
5040 | .in11(1'b1), | |
5041 | .out(spare2_oai22_4x_unused)); | |
5042 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
5043 | .out(spare2_inv_16x_unused)); | |
5044 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
5045 | .in1(1'b1), | |
5046 | .out(spare2_nand2_16x_unused)); | |
5047 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
5048 | .in1(1'b0), | |
5049 | .in2(1'b0), | |
5050 | .out(spare2_nor3_4x_unused)); | |
5051 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
5052 | .in1(1'b1), | |
5053 | .out(spare2_nand2_8x_unused)); | |
5054 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
5055 | .out(spare2_buf_16x_unused)); | |
5056 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
5057 | .in1(1'b0), | |
5058 | .out(spare2_nor2_16x_unused)); | |
5059 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
5060 | .out(spare2_inv_32x_unused)); | |
5061 | ||
5062 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
5063 | .siclk(siclk), | |
5064 | .soclk(soclk), | |
5065 | .si(si_3), | |
5066 | .so(so_3), | |
5067 | .d(1'b0), | |
5068 | .q(spare3_flop_unused)); | |
5069 | assign si_3 = so_2; | |
5070 | ||
5071 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
5072 | .out(spare3_buf_32x_unused)); | |
5073 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
5074 | .in1(1'b1), | |
5075 | .in2(1'b1), | |
5076 | .out(spare3_nand3_8x_unused)); | |
5077 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
5078 | .out(spare3_inv_8x_unused)); | |
5079 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
5080 | .in01(1'b1), | |
5081 | .in10(1'b1), | |
5082 | .in11(1'b1), | |
5083 | .out(spare3_aoi22_4x_unused)); | |
5084 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
5085 | .out(spare3_buf_8x_unused)); | |
5086 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
5087 | .in01(1'b1), | |
5088 | .in10(1'b1), | |
5089 | .in11(1'b1), | |
5090 | .out(spare3_oai22_4x_unused)); | |
5091 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
5092 | .out(spare3_inv_16x_unused)); | |
5093 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
5094 | .in1(1'b1), | |
5095 | .out(spare3_nand2_16x_unused)); | |
5096 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
5097 | .in1(1'b0), | |
5098 | .in2(1'b0), | |
5099 | .out(spare3_nor3_4x_unused)); | |
5100 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
5101 | .in1(1'b1), | |
5102 | .out(spare3_nand2_8x_unused)); | |
5103 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
5104 | .out(spare3_buf_16x_unused)); | |
5105 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
5106 | .in1(1'b0), | |
5107 | .out(spare3_nor2_16x_unused)); | |
5108 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
5109 | .out(spare3_inv_32x_unused)); | |
5110 | ||
5111 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), | |
5112 | .siclk(siclk), | |
5113 | .soclk(soclk), | |
5114 | .si(si_4), | |
5115 | .so(so_4), | |
5116 | .d(1'b0), | |
5117 | .q(spare4_flop_unused)); | |
5118 | assign si_4 = so_3; | |
5119 | ||
5120 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
5121 | .out(spare4_buf_32x_unused)); | |
5122 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
5123 | .in1(1'b1), | |
5124 | .in2(1'b1), | |
5125 | .out(spare4_nand3_8x_unused)); | |
5126 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
5127 | .out(spare4_inv_8x_unused)); | |
5128 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
5129 | .in01(1'b1), | |
5130 | .in10(1'b1), | |
5131 | .in11(1'b1), | |
5132 | .out(spare4_aoi22_4x_unused)); | |
5133 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
5134 | .out(spare4_buf_8x_unused)); | |
5135 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
5136 | .in01(1'b1), | |
5137 | .in10(1'b1), | |
5138 | .in11(1'b1), | |
5139 | .out(spare4_oai22_4x_unused)); | |
5140 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
5141 | .out(spare4_inv_16x_unused)); | |
5142 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
5143 | .in1(1'b1), | |
5144 | .out(spare4_nand2_16x_unused)); | |
5145 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
5146 | .in1(1'b0), | |
5147 | .in2(1'b0), | |
5148 | .out(spare4_nor3_4x_unused)); | |
5149 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
5150 | .in1(1'b1), | |
5151 | .out(spare4_nand2_8x_unused)); | |
5152 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
5153 | .out(spare4_buf_16x_unused)); | |
5154 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
5155 | .in1(1'b0), | |
5156 | .out(spare4_nor2_16x_unused)); | |
5157 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
5158 | .out(spare4_inv_32x_unused)); | |
5159 | ||
5160 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), | |
5161 | .siclk(siclk), | |
5162 | .soclk(soclk), | |
5163 | .si(si_5), | |
5164 | .so(so_5), | |
5165 | .d(1'b0), | |
5166 | .q(spare5_flop_unused)); | |
5167 | assign si_5 = so_4; | |
5168 | ||
5169 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
5170 | .out(spare5_buf_32x_unused)); | |
5171 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
5172 | .in1(1'b1), | |
5173 | .in2(1'b1), | |
5174 | .out(spare5_nand3_8x_unused)); | |
5175 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
5176 | .out(spare5_inv_8x_unused)); | |
5177 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
5178 | .in01(1'b1), | |
5179 | .in10(1'b1), | |
5180 | .in11(1'b1), | |
5181 | .out(spare5_aoi22_4x_unused)); | |
5182 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
5183 | .out(spare5_buf_8x_unused)); | |
5184 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
5185 | .in01(1'b1), | |
5186 | .in10(1'b1), | |
5187 | .in11(1'b1), | |
5188 | .out(spare5_oai22_4x_unused)); | |
5189 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
5190 | .out(spare5_inv_16x_unused)); | |
5191 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
5192 | .in1(1'b1), | |
5193 | .out(spare5_nand2_16x_unused)); | |
5194 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
5195 | .in1(1'b0), | |
5196 | .in2(1'b0), | |
5197 | .out(spare5_nor3_4x_unused)); | |
5198 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
5199 | .in1(1'b1), | |
5200 | .out(spare5_nand2_8x_unused)); | |
5201 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
5202 | .out(spare5_buf_16x_unused)); | |
5203 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
5204 | .in1(1'b0), | |
5205 | .out(spare5_nor2_16x_unused)); | |
5206 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
5207 | .out(spare5_inv_32x_unused)); | |
5208 | ||
5209 | cl_sc1_msff_8x spare6_flop (.l1clk(l1clk), | |
5210 | .siclk(siclk), | |
5211 | .soclk(soclk), | |
5212 | .si(si_6), | |
5213 | .so(so_6), | |
5214 | .d(1'b0), | |
5215 | .q(spare6_flop_unused)); | |
5216 | assign si_6 = so_5; | |
5217 | ||
5218 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), | |
5219 | .out(spare6_buf_32x_unused)); | |
5220 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), | |
5221 | .in1(1'b1), | |
5222 | .in2(1'b1), | |
5223 | .out(spare6_nand3_8x_unused)); | |
5224 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), | |
5225 | .out(spare6_inv_8x_unused)); | |
5226 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), | |
5227 | .in01(1'b1), | |
5228 | .in10(1'b1), | |
5229 | .in11(1'b1), | |
5230 | .out(spare6_aoi22_4x_unused)); | |
5231 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), | |
5232 | .out(spare6_buf_8x_unused)); | |
5233 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), | |
5234 | .in01(1'b1), | |
5235 | .in10(1'b1), | |
5236 | .in11(1'b1), | |
5237 | .out(spare6_oai22_4x_unused)); | |
5238 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), | |
5239 | .out(spare6_inv_16x_unused)); | |
5240 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), | |
5241 | .in1(1'b1), | |
5242 | .out(spare6_nand2_16x_unused)); | |
5243 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), | |
5244 | .in1(1'b0), | |
5245 | .in2(1'b0), | |
5246 | .out(spare6_nor3_4x_unused)); | |
5247 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), | |
5248 | .in1(1'b1), | |
5249 | .out(spare6_nand2_8x_unused)); | |
5250 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), | |
5251 | .out(spare6_buf_16x_unused)); | |
5252 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), | |
5253 | .in1(1'b0), | |
5254 | .out(spare6_nor2_16x_unused)); | |
5255 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), | |
5256 | .out(spare6_inv_32x_unused)); | |
5257 | ||
5258 | cl_sc1_msff_8x spare7_flop (.l1clk(l1clk), | |
5259 | .siclk(siclk), | |
5260 | .soclk(soclk), | |
5261 | .si(si_7), | |
5262 | .so(so_7), | |
5263 | .d(1'b0), | |
5264 | .q(spare7_flop_unused)); | |
5265 | assign si_7 = so_6; | |
5266 | ||
5267 | cl_u1_buf_32x spare7_buf_32x (.in(1'b1), | |
5268 | .out(spare7_buf_32x_unused)); | |
5269 | cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1), | |
5270 | .in1(1'b1), | |
5271 | .in2(1'b1), | |
5272 | .out(spare7_nand3_8x_unused)); | |
5273 | cl_u1_inv_8x spare7_inv_8x (.in(1'b1), | |
5274 | .out(spare7_inv_8x_unused)); | |
5275 | cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1), | |
5276 | .in01(1'b1), | |
5277 | .in10(1'b1), | |
5278 | .in11(1'b1), | |
5279 | .out(spare7_aoi22_4x_unused)); | |
5280 | cl_u1_buf_8x spare7_buf_8x (.in(1'b1), | |
5281 | .out(spare7_buf_8x_unused)); | |
5282 | cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1), | |
5283 | .in01(1'b1), | |
5284 | .in10(1'b1), | |
5285 | .in11(1'b1), | |
5286 | .out(spare7_oai22_4x_unused)); | |
5287 | cl_u1_inv_16x spare7_inv_16x (.in(1'b1), | |
5288 | .out(spare7_inv_16x_unused)); | |
5289 | cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1), | |
5290 | .in1(1'b1), | |
5291 | .out(spare7_nand2_16x_unused)); | |
5292 | cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0), | |
5293 | .in1(1'b0), | |
5294 | .in2(1'b0), | |
5295 | .out(spare7_nor3_4x_unused)); | |
5296 | cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1), | |
5297 | .in1(1'b1), | |
5298 | .out(spare7_nand2_8x_unused)); | |
5299 | cl_u1_buf_16x spare7_buf_16x (.in(1'b1), | |
5300 | .out(spare7_buf_16x_unused)); | |
5301 | cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0), | |
5302 | .in1(1'b0), | |
5303 | .out(spare7_nor2_16x_unused)); | |
5304 | cl_u1_inv_32x spare7_inv_32x (.in(1'b1), | |
5305 | .out(spare7_inv_32x_unused)); | |
5306 | ||
5307 | cl_sc1_msff_8x spare8_flop (.l1clk(l1clk), | |
5308 | .siclk(siclk), | |
5309 | .soclk(soclk), | |
5310 | .si(si_8), | |
5311 | .so(so_8), | |
5312 | .d(fbdic_idle_lfsr_reset), | |
5313 | .q(fbdic_idle_lfsr_reset_d1)); | |
5314 | assign si_8 = so_7; | |
5315 | ||
5316 | cl_u1_buf_32x spare8_buf_32x (.in(1'b1), | |
5317 | .out(spare8_buf_32x_unused)); | |
5318 | cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1), | |
5319 | .in1(1'b1), | |
5320 | .in2(1'b1), | |
5321 | .out(spare8_nand3_8x_unused)); | |
5322 | cl_u1_inv_8x spare8_inv_8x (.in(1'b1), | |
5323 | .out(spare8_inv_8x_unused)); | |
5324 | cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1), | |
5325 | .in01(1'b1), | |
5326 | .in10(1'b1), | |
5327 | .in11(1'b1), | |
5328 | .out(spare8_aoi22_4x_unused)); | |
5329 | cl_u1_buf_8x spare8_buf_8x (.in(1'b1), | |
5330 | .out(spare8_buf_8x_unused)); | |
5331 | cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1), | |
5332 | .in01(1'b1), | |
5333 | .in10(1'b1), | |
5334 | .in11(1'b1), | |
5335 | .out(spare8_oai22_4x_unused)); | |
5336 | cl_u1_inv_16x spare8_inv_16x (.in(1'b1), | |
5337 | .out(spare8_inv_16x_unused)); | |
5338 | cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1), | |
5339 | .in1(1'b1), | |
5340 | .out(spare8_nand2_16x_unused)); | |
5341 | cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0), | |
5342 | .in1(1'b0), | |
5343 | .in2(1'b0), | |
5344 | .out(spare8_nor3_4x_unused)); | |
5345 | cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1), | |
5346 | .in1(1'b1), | |
5347 | .out(spare8_nand2_8x_unused)); | |
5348 | cl_u1_buf_16x spare8_buf_16x (.in(1'b1), | |
5349 | .out(spare8_buf_16x_unused)); | |
5350 | cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0), | |
5351 | .in1(1'b0), | |
5352 | .out(spare8_nor2_16x_unused)); | |
5353 | cl_u1_inv_32x spare8_inv_32x (.in(1'b1), | |
5354 | .out(spare8_inv_32x_unused)); | |
5355 | ||
5356 | cl_sc1_msff_8x spare9_flop (.l1clk(l1clk), | |
5357 | .siclk(siclk), | |
5358 | .soclk(soclk), | |
5359 | .si(si_9), | |
5360 | .so(so_9), | |
5361 | .d(1'b0), | |
5362 | .q(spare9_flop_unused)); | |
5363 | assign si_9 = so_8; | |
5364 | ||
5365 | cl_u1_buf_32x spare9_buf_32x (.in(1'b1), | |
5366 | .out(spare9_buf_32x_unused)); | |
5367 | cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1), | |
5368 | .in1(1'b1), | |
5369 | .in2(1'b1), | |
5370 | .out(spare9_nand3_8x_unused)); | |
5371 | cl_u1_inv_8x spare9_inv_8x (.in(1'b1), | |
5372 | .out(spare9_inv_8x_unused)); | |
5373 | cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1), | |
5374 | .in01(1'b1), | |
5375 | .in10(1'b1), | |
5376 | .in11(1'b1), | |
5377 | .out(spare9_aoi22_4x_unused)); | |
5378 | cl_u1_buf_8x spare9_buf_8x (.in(1'b1), | |
5379 | .out(spare9_buf_8x_unused)); | |
5380 | cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1), | |
5381 | .in01(1'b1), | |
5382 | .in10(1'b1), | |
5383 | .in11(1'b1), | |
5384 | .out(spare9_oai22_4x_unused)); | |
5385 | cl_u1_inv_16x spare9_inv_16x (.in(1'b1), | |
5386 | .out(spare9_inv_16x_unused)); | |
5387 | cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1), | |
5388 | .in1(1'b1), | |
5389 | .out(spare9_nand2_16x_unused)); | |
5390 | cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0), | |
5391 | .in1(1'b0), | |
5392 | .in2(1'b0), | |
5393 | .out(spare9_nor3_4x_unused)); | |
5394 | cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1), | |
5395 | .in1(1'b1), | |
5396 | .out(spare9_nand2_8x_unused)); | |
5397 | cl_u1_buf_16x spare9_buf_16x (.in(1'b1), | |
5398 | .out(spare9_buf_16x_unused)); | |
5399 | cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0), | |
5400 | .in1(1'b0), | |
5401 | .out(spare9_nor2_16x_unused)); | |
5402 | cl_u1_inv_32x spare9_inv_32x (.in(1'b1), | |
5403 | .out(spare9_inv_32x_unused)); | |
5404 | ||
5405 | cl_sc1_msff_8x spare10_flop (.l1clk(l1clk), | |
5406 | .siclk(siclk), | |
5407 | .soclk(soclk), | |
5408 | .si(si_10), | |
5409 | .so(so_10), | |
5410 | .d(fbdic_cke_cmd_pend_in), | |
5411 | .q(fbdic_cke_cmd_pend)); | |
5412 | assign si_10 = so_9; | |
5413 | ||
5414 | cl_u1_buf_32x spare10_buf_32x (.in(1'b1), | |
5415 | .out(spare10_buf_32x_unused)); | |
5416 | cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1), | |
5417 | .in1(1'b1), | |
5418 | .in2(1'b1), | |
5419 | .out(spare10_nand3_8x_unused)); | |
5420 | cl_u1_inv_8x spare10_inv_8x (.in(1'b1), | |
5421 | .out(spare10_inv_8x_unused)); | |
5422 | cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1), | |
5423 | .in01(1'b1), | |
5424 | .in10(1'b1), | |
5425 | .in11(1'b1), | |
5426 | .out(spare10_aoi22_4x_unused)); | |
5427 | cl_u1_buf_8x spare10_buf_8x (.in(1'b1), | |
5428 | .out(spare10_buf_8x_unused)); | |
5429 | cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1), | |
5430 | .in01(1'b1), | |
5431 | .in10(1'b1), | |
5432 | .in11(1'b1), | |
5433 | .out(spare10_oai22_4x_unused)); | |
5434 | cl_u1_inv_16x spare10_inv_16x (.in(1'b1), | |
5435 | .out(spare10_inv_16x_unused)); | |
5436 | cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1), | |
5437 | .in1(1'b1), | |
5438 | .out(spare10_nand2_16x_unused)); | |
5439 | cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0), | |
5440 | .in1(1'b0), | |
5441 | .in2(1'b0), | |
5442 | .out(spare10_nor3_4x_unused)); | |
5443 | cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1), | |
5444 | .in1(1'b1), | |
5445 | .out(spare10_nand2_8x_unused)); | |
5446 | cl_u1_buf_16x spare10_buf_16x (.in(1'b1), | |
5447 | .out(spare10_buf_16x_unused)); | |
5448 | cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0), | |
5449 | .in1(1'b0), | |
5450 | .out(spare10_nor2_16x_unused)); | |
5451 | cl_u1_inv_32x spare10_inv_32x (.in(1'b1), | |
5452 | .out(spare10_inv_32x_unused)); | |
5453 | ||
5454 | cl_sc1_msff_8x spare11_flop (.l1clk(l1clk), | |
5455 | .siclk(siclk), | |
5456 | .soclk(soclk), | |
5457 | .si(si_11), | |
5458 | .so(so_11), | |
5459 | .d(1'b0), | |
5460 | .q(spare11_flop_unused)); | |
5461 | assign si_11 = so_10; | |
5462 | ||
5463 | cl_u1_buf_32x spare11_buf_32x (.in(1'b1), | |
5464 | .out(spare11_buf_32x_unused)); | |
5465 | cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1), | |
5466 | .in1(1'b1), | |
5467 | .in2(1'b1), | |
5468 | .out(spare11_nand3_8x_unused)); | |
5469 | cl_u1_inv_8x spare11_inv_8x (.in(1'b1), | |
5470 | .out(spare11_inv_8x_unused)); | |
5471 | cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1), | |
5472 | .in01(1'b1), | |
5473 | .in10(1'b1), | |
5474 | .in11(1'b1), | |
5475 | .out(spare11_aoi22_4x_unused)); | |
5476 | cl_u1_buf_8x spare11_buf_8x (.in(1'b1), | |
5477 | .out(spare11_buf_8x_unused)); | |
5478 | cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1), | |
5479 | .in01(1'b1), | |
5480 | .in10(1'b1), | |
5481 | .in11(1'b1), | |
5482 | .out(spare11_oai22_4x_unused)); | |
5483 | cl_u1_inv_16x spare11_inv_16x (.in(1'b1), | |
5484 | .out(spare11_inv_16x_unused)); | |
5485 | cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1), | |
5486 | .in1(1'b1), | |
5487 | .out(spare11_nand2_16x_unused)); | |
5488 | cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0), | |
5489 | .in1(1'b0), | |
5490 | .in2(1'b0), | |
5491 | .out(spare11_nor3_4x_unused)); | |
5492 | cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1), | |
5493 | .in1(1'b1), | |
5494 | .out(spare11_nand2_8x_unused)); | |
5495 | cl_u1_buf_16x spare11_buf_16x (.in(1'b1), | |
5496 | .out(spare11_buf_16x_unused)); | |
5497 | cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0), | |
5498 | .in1(1'b0), | |
5499 | .out(spare11_nor2_16x_unused)); | |
5500 | cl_u1_inv_32x spare11_inv_32x (.in(1'b1), | |
5501 | .out(spare11_inv_32x_unused)); | |
5502 | ||
5503 | cl_sc1_msff_8x spare12_flop (.l1clk(l1clk), | |
5504 | .siclk(siclk), | |
5505 | .soclk(soclk), | |
5506 | .si(si_12), | |
5507 | .so(so_12), | |
5508 | .d(1'b0), | |
5509 | .q(spare12_flop_unused)); | |
5510 | assign si_12 = so_11; | |
5511 | ||
5512 | cl_u1_buf_32x spare12_buf_32x (.in(1'b1), | |
5513 | .out(spare12_buf_32x_unused)); | |
5514 | cl_u1_nand3_8x spare12_nand3_8x (.in0(1'b1), | |
5515 | .in1(1'b1), | |
5516 | .in2(1'b1), | |
5517 | .out(spare12_nand3_8x_unused)); | |
5518 | cl_u1_inv_8x spare12_inv_8x (.in(1'b1), | |
5519 | .out(spare12_inv_8x_unused)); | |
5520 | cl_u1_aoi22_4x spare12_aoi22_4x (.in00(1'b1), | |
5521 | .in01(1'b1), | |
5522 | .in10(1'b1), | |
5523 | .in11(1'b1), | |
5524 | .out(spare12_aoi22_4x_unused)); | |
5525 | cl_u1_buf_8x spare12_buf_8x (.in(1'b1), | |
5526 | .out(spare12_buf_8x_unused)); | |
5527 | cl_u1_oai22_4x spare12_oai22_4x (.in00(1'b1), | |
5528 | .in01(1'b1), | |
5529 | .in10(1'b1), | |
5530 | .in11(1'b1), | |
5531 | .out(spare12_oai22_4x_unused)); | |
5532 | cl_u1_inv_16x spare12_inv_16x (.in(1'b1), | |
5533 | .out(spare12_inv_16x_unused)); | |
5534 | cl_u1_nand2_16x spare12_nand2_16x (.in0(1'b1), | |
5535 | .in1(1'b1), | |
5536 | .out(spare12_nand2_16x_unused)); | |
5537 | cl_u1_nor3_4x spare12_nor3_4x (.in0(1'b0), | |
5538 | .in1(1'b0), | |
5539 | .in2(1'b0), | |
5540 | .out(spare12_nor3_4x_unused)); | |
5541 | cl_u1_nand2_8x spare12_nand2_8x (.in0(1'b1), | |
5542 | .in1(1'b1), | |
5543 | .out(spare12_nand2_8x_unused)); | |
5544 | cl_u1_buf_16x spare12_buf_16x (.in(1'b1), | |
5545 | .out(spare12_buf_16x_unused)); | |
5546 | cl_u1_nor2_16x spare12_nor2_16x (.in0(1'b0), | |
5547 | .in1(1'b0), | |
5548 | .out(spare12_nor2_16x_unused)); | |
5549 | cl_u1_inv_32x spare12_inv_32x (.in(1'b1), | |
5550 | .out(spare12_inv_32x_unused)); | |
5551 | ||
5552 | cl_sc1_msff_8x spare13_flop (.l1clk(l1clk), | |
5553 | .siclk(siclk), | |
5554 | .soclk(soclk), | |
5555 | .si(si_13), | |
5556 | .so(so_13), | |
5557 | .d(1'b0), | |
5558 | .q(spare13_flop_unused)); | |
5559 | assign si_13 = so_12; | |
5560 | ||
5561 | cl_u1_buf_32x spare13_buf_32x (.in(1'b1), | |
5562 | .out(spare13_buf_32x_unused)); | |
5563 | cl_u1_nand3_8x spare13_nand3_8x (.in0(1'b1), | |
5564 | .in1(1'b1), | |
5565 | .in2(1'b1), | |
5566 | .out(spare13_nand3_8x_unused)); | |
5567 | cl_u1_inv_8x spare13_inv_8x (.in(1'b1), | |
5568 | .out(spare13_inv_8x_unused)); | |
5569 | cl_u1_aoi22_4x spare13_aoi22_4x (.in00(1'b1), | |
5570 | .in01(1'b1), | |
5571 | .in10(1'b1), | |
5572 | .in11(1'b1), | |
5573 | .out(spare13_aoi22_4x_unused)); | |
5574 | cl_u1_buf_8x spare13_buf_8x (.in(1'b1), | |
5575 | .out(spare13_buf_8x_unused)); | |
5576 | cl_u1_oai22_4x spare13_oai22_4x (.in00(1'b1), | |
5577 | .in01(1'b1), | |
5578 | .in10(1'b1), | |
5579 | .in11(1'b1), | |
5580 | .out(spare13_oai22_4x_unused)); | |
5581 | cl_u1_inv_16x spare13_inv_16x (.in(1'b1), | |
5582 | .out(spare13_inv_16x_unused)); | |
5583 | cl_u1_nand2_16x spare13_nand2_16x (.in0(1'b1), | |
5584 | .in1(1'b1), | |
5585 | .out(spare13_nand2_16x_unused)); | |
5586 | cl_u1_nor3_4x spare13_nor3_4x (.in0(1'b0), | |
5587 | .in1(1'b0), | |
5588 | .in2(1'b0), | |
5589 | .out(spare13_nor3_4x_unused)); | |
5590 | cl_u1_nand2_8x spare13_nand2_8x (.in0(1'b1), | |
5591 | .in1(1'b1), | |
5592 | .out(spare13_nand2_8x_unused)); | |
5593 | cl_u1_buf_16x spare13_buf_16x (.in(1'b1), | |
5594 | .out(spare13_buf_16x_unused)); | |
5595 | cl_u1_nor2_16x spare13_nor2_16x (.in0(1'b0), | |
5596 | .in1(1'b0), | |
5597 | .out(spare13_nor2_16x_unused)); | |
5598 | cl_u1_inv_32x spare13_inv_32x (.in(1'b1), | |
5599 | .out(spare13_inv_32x_unused)); | |
5600 | ||
5601 | cl_sc1_msff_8x spare14_flop (.l1clk(l1clk), | |
5602 | .siclk(siclk), | |
5603 | .soclk(soclk), | |
5604 | .si(si_14), | |
5605 | .so(so_14), | |
5606 | .d(1'b0), | |
5607 | .q(spare14_flop_unused)); | |
5608 | assign si_14 = so_13; | |
5609 | ||
5610 | cl_u1_buf_32x spare14_buf_32x (.in(1'b1), | |
5611 | .out(spare14_buf_32x_unused)); | |
5612 | cl_u1_nand3_8x spare14_nand3_8x (.in0(1'b1), | |
5613 | .in1(1'b1), | |
5614 | .in2(1'b1), | |
5615 | .out(spare14_nand3_8x_unused)); | |
5616 | cl_u1_inv_8x spare14_inv_8x (.in(1'b1), | |
5617 | .out(spare14_inv_8x_unused)); | |
5618 | cl_u1_aoi22_4x spare14_aoi22_4x (.in00(1'b1), | |
5619 | .in01(1'b1), | |
5620 | .in10(1'b1), | |
5621 | .in11(1'b1), | |
5622 | .out(spare14_aoi22_4x_unused)); | |
5623 | cl_u1_buf_8x spare14_buf_8x (.in(1'b1), | |
5624 | .out(spare14_buf_8x_unused)); | |
5625 | cl_u1_oai22_4x spare14_oai22_4x (.in00(1'b1), | |
5626 | .in01(1'b1), | |
5627 | .in10(1'b1), | |
5628 | .in11(1'b1), | |
5629 | .out(spare14_oai22_4x_unused)); | |
5630 | cl_u1_inv_16x spare14_inv_16x (.in(1'b1), | |
5631 | .out(spare14_inv_16x_unused)); | |
5632 | cl_u1_nand2_16x spare14_nand2_16x (.in0(1'b1), | |
5633 | .in1(1'b1), | |
5634 | .out(spare14_nand2_16x_unused)); | |
5635 | cl_u1_nor3_4x spare14_nor3_4x (.in0(1'b0), | |
5636 | .in1(1'b0), | |
5637 | .in2(1'b0), | |
5638 | .out(spare14_nor3_4x_unused)); | |
5639 | cl_u1_nand2_8x spare14_nand2_8x (.in0(1'b1), | |
5640 | .in1(1'b1), | |
5641 | .out(spare14_nand2_8x_unused)); | |
5642 | cl_u1_buf_16x spare14_buf_16x (.in(1'b1), | |
5643 | .out(spare14_buf_16x_unused)); | |
5644 | cl_u1_nor2_16x spare14_nor2_16x (.in0(1'b0), | |
5645 | .in1(1'b0), | |
5646 | .out(spare14_nor2_16x_unused)); | |
5647 | cl_u1_inv_32x spare14_inv_32x (.in(1'b1), | |
5648 | .out(spare14_inv_32x_unused)); | |
5649 | ||
5650 | cl_sc1_msff_8x spare15_flop (.l1clk(l1clk), | |
5651 | .siclk(siclk), | |
5652 | .soclk(soclk), | |
5653 | .si(si_15), | |
5654 | .so(so_15), | |
5655 | .d(1'b0), | |
5656 | .q(spare15_flop_unused)); | |
5657 | assign si_15 = so_14; | |
5658 | ||
5659 | cl_u1_buf_32x spare15_buf_32x (.in(1'b1), | |
5660 | .out(spare15_buf_32x_unused)); | |
5661 | cl_u1_nand3_8x spare15_nand3_8x (.in0(1'b1), | |
5662 | .in1(1'b1), | |
5663 | .in2(1'b1), | |
5664 | .out(spare15_nand3_8x_unused)); | |
5665 | cl_u1_inv_8x spare15_inv_8x (.in(1'b1), | |
5666 | .out(spare15_inv_8x_unused)); | |
5667 | cl_u1_aoi22_4x spare15_aoi22_4x (.in00(1'b1), | |
5668 | .in01(1'b1), | |
5669 | .in10(1'b1), | |
5670 | .in11(1'b1), | |
5671 | .out(spare15_aoi22_4x_unused)); | |
5672 | cl_u1_buf_8x spare15_buf_8x (.in(1'b1), | |
5673 | .out(spare15_buf_8x_unused)); | |
5674 | cl_u1_oai22_4x spare15_oai22_4x (.in00(1'b1), | |
5675 | .in01(1'b1), | |
5676 | .in10(1'b1), | |
5677 | .in11(1'b1), | |
5678 | .out(spare15_oai22_4x_unused)); | |
5679 | cl_u1_inv_16x spare15_inv_16x (.in(1'b1), | |
5680 | .out(spare15_inv_16x_unused)); | |
5681 | cl_u1_nand2_16x spare15_nand2_16x (.in0(1'b1), | |
5682 | .in1(1'b1), | |
5683 | .out(spare15_nand2_16x_unused)); | |
5684 | cl_u1_nor3_4x spare15_nor3_4x (.in0(1'b0), | |
5685 | .in1(1'b0), | |
5686 | .in2(1'b0), | |
5687 | .out(spare15_nor3_4x_unused)); | |
5688 | cl_u1_nand2_8x spare15_nand2_8x (.in0(1'b1), | |
5689 | .in1(1'b1), | |
5690 | .out(spare15_nand2_8x_unused)); | |
5691 | cl_u1_buf_16x spare15_buf_16x (.in(1'b1), | |
5692 | .out(spare15_buf_16x_unused)); | |
5693 | cl_u1_nor2_16x spare15_nor2_16x (.in0(1'b0), | |
5694 | .in1(1'b0), | |
5695 | .out(spare15_nor2_16x_unused)); | |
5696 | cl_u1_inv_32x spare15_inv_32x (.in(1'b1), | |
5697 | .out(spare15_inv_32x_unused)); | |
5698 | ||
5699 | cl_sc1_msff_8x spare16_flop (.l1clk(l1clk), | |
5700 | .siclk(siclk), | |
5701 | .soclk(soclk), | |
5702 | .si(si_16), | |
5703 | .so(so_16), | |
5704 | .d(1'b0), | |
5705 | .q(spare16_flop_unused)); | |
5706 | assign si_16 = so_15; | |
5707 | ||
5708 | cl_u1_buf_32x spare16_buf_32x (.in(1'b1), | |
5709 | .out(spare16_buf_32x_unused)); | |
5710 | cl_u1_nand3_8x spare16_nand3_8x (.in0(1'b1), | |
5711 | .in1(1'b1), | |
5712 | .in2(1'b1), | |
5713 | .out(spare16_nand3_8x_unused)); | |
5714 | cl_u1_inv_8x spare16_inv_8x (.in(1'b1), | |
5715 | .out(spare16_inv_8x_unused)); | |
5716 | cl_u1_aoi22_4x spare16_aoi22_4x (.in00(1'b1), | |
5717 | .in01(1'b1), | |
5718 | .in10(1'b1), | |
5719 | .in11(1'b1), | |
5720 | .out(spare16_aoi22_4x_unused)); | |
5721 | cl_u1_buf_8x spare16_buf_8x (.in(1'b1), | |
5722 | .out(spare16_buf_8x_unused)); | |
5723 | cl_u1_oai22_4x spare16_oai22_4x (.in00(1'b1), | |
5724 | .in01(1'b1), | |
5725 | .in10(1'b1), | |
5726 | .in11(1'b1), | |
5727 | .out(spare16_oai22_4x_unused)); | |
5728 | cl_u1_inv_16x spare16_inv_16x (.in(1'b1), | |
5729 | .out(spare16_inv_16x_unused)); | |
5730 | cl_u1_nand2_16x spare16_nand2_16x (.in0(1'b1), | |
5731 | .in1(1'b1), | |
5732 | .out(spare16_nand2_16x_unused)); | |
5733 | cl_u1_nor3_4x spare16_nor3_4x (.in0(1'b0), | |
5734 | .in1(1'b0), | |
5735 | .in2(1'b0), | |
5736 | .out(spare16_nor3_4x_unused)); | |
5737 | cl_u1_nand2_8x spare16_nand2_8x (.in0(1'b1), | |
5738 | .in1(1'b1), | |
5739 | .out(spare16_nand2_8x_unused)); | |
5740 | cl_u1_buf_16x spare16_buf_16x (.in(1'b1), | |
5741 | .out(spare16_buf_16x_unused)); | |
5742 | cl_u1_nor2_16x spare16_nor2_16x (.in0(1'b0), | |
5743 | .in1(1'b0), | |
5744 | .out(spare16_nor2_16x_unused)); | |
5745 | cl_u1_inv_32x spare16_inv_32x (.in(1'b1), | |
5746 | .out(spare16_inv_32x_unused)); | |
5747 | ||
5748 | cl_sc1_msff_8x spare17_flop (.l1clk(l1clk), | |
5749 | .siclk(siclk), | |
5750 | .soclk(soclk), | |
5751 | .si(si_17), | |
5752 | .so(so_17), | |
5753 | .d(1'b0), | |
5754 | .q(spare17_flop_unused)); | |
5755 | assign si_17 = so_16; | |
5756 | ||
5757 | cl_u1_buf_32x spare17_buf_32x (.in(1'b1), | |
5758 | .out(spare17_buf_32x_unused)); | |
5759 | cl_u1_nand3_8x spare17_nand3_8x (.in0(1'b1), | |
5760 | .in1(1'b1), | |
5761 | .in2(1'b1), | |
5762 | .out(spare17_nand3_8x_unused)); | |
5763 | cl_u1_inv_8x spare17_inv_8x (.in(1'b1), | |
5764 | .out(spare17_inv_8x_unused)); | |
5765 | cl_u1_aoi22_4x spare17_aoi22_4x (.in00(1'b1), | |
5766 | .in01(1'b1), | |
5767 | .in10(1'b1), | |
5768 | .in11(1'b1), | |
5769 | .out(spare17_aoi22_4x_unused)); | |
5770 | cl_u1_buf_8x spare17_buf_8x (.in(1'b1), | |
5771 | .out(spare17_buf_8x_unused)); | |
5772 | cl_u1_oai22_4x spare17_oai22_4x (.in00(1'b1), | |
5773 | .in01(1'b1), | |
5774 | .in10(1'b1), | |
5775 | .in11(1'b1), | |
5776 | .out(spare17_oai22_4x_unused)); | |
5777 | cl_u1_inv_16x spare17_inv_16x (.in(1'b1), | |
5778 | .out(spare17_inv_16x_unused)); | |
5779 | cl_u1_nand2_16x spare17_nand2_16x (.in0(1'b1), | |
5780 | .in1(1'b1), | |
5781 | .out(spare17_nand2_16x_unused)); | |
5782 | cl_u1_nor3_4x spare17_nor3_4x (.in0(1'b0), | |
5783 | .in1(1'b0), | |
5784 | .in2(1'b0), | |
5785 | .out(spare17_nor3_4x_unused)); | |
5786 | cl_u1_nand2_8x spare17_nand2_8x (.in0(1'b1), | |
5787 | .in1(1'b1), | |
5788 | .out(spare17_nand2_8x_unused)); | |
5789 | cl_u1_buf_16x spare17_buf_16x (.in(1'b1), | |
5790 | .out(spare17_buf_16x_unused)); | |
5791 | cl_u1_nor2_16x spare17_nor2_16x (.in0(1'b0), | |
5792 | .in1(1'b0), | |
5793 | .out(spare17_nor2_16x_unused)); | |
5794 | cl_u1_inv_32x spare17_inv_32x (.in(1'b1), | |
5795 | .out(spare17_inv_32x_unused)); | |
5796 | ||
5797 | cl_sc1_msff_8x spare18_flop (.l1clk(l1clk), | |
5798 | .siclk(siclk), | |
5799 | .soclk(soclk), | |
5800 | .si(si_18), | |
5801 | .so(so_18), | |
5802 | .d(fbdic_link_cnt_eq_4_in), | |
5803 | .q(fbdic_link_cnt_eq_4)); | |
5804 | assign si_18 = so_17; | |
5805 | ||
5806 | cl_u1_buf_32x spare18_buf_32x (.in(1'b1), | |
5807 | .out(spare18_buf_32x_unused)); | |
5808 | cl_u1_nand3_8x spare18_nand3_8x (.in0(1'b1), | |
5809 | .in1(1'b1), | |
5810 | .in2(1'b1), | |
5811 | .out(spare18_nand3_8x_unused)); | |
5812 | cl_u1_inv_8x spare18_inv_8x (.in(1'b1), | |
5813 | .out(spare18_inv_8x_unused)); | |
5814 | cl_u1_aoi22_4x spare18_aoi22_4x (.in00(1'b1), | |
5815 | .in01(1'b1), | |
5816 | .in10(1'b1), | |
5817 | .in11(1'b1), | |
5818 | .out(spare18_aoi22_4x_unused)); | |
5819 | cl_u1_buf_8x spare18_buf_8x (.in(1'b1), | |
5820 | .out(spare18_buf_8x_unused)); | |
5821 | cl_u1_oai22_4x spare18_oai22_4x (.in00(1'b1), | |
5822 | .in01(1'b1), | |
5823 | .in10(1'b1), | |
5824 | .in11(1'b1), | |
5825 | .out(spare18_oai22_4x_unused)); | |
5826 | cl_u1_inv_16x spare18_inv_16x (.in(1'b1), | |
5827 | .out(spare18_inv_16x_unused)); | |
5828 | cl_u1_nand2_16x spare18_nand2_16x (.in0(1'b1), | |
5829 | .in1(1'b1), | |
5830 | .out(spare18_nand2_16x_unused)); | |
5831 | cl_u1_nor3_4x spare18_nor3_4x (.in0(1'b0), | |
5832 | .in1(1'b0), | |
5833 | .in2(1'b0), | |
5834 | .out(spare18_nor3_4x_unused)); | |
5835 | cl_u1_nand2_8x spare18_nand2_8x (.in0(1'b1), | |
5836 | .in1(1'b1), | |
5837 | .out(spare18_nand2_8x_unused)); | |
5838 | cl_u1_buf_16x spare18_buf_16x (.in(1'b1), | |
5839 | .out(spare18_buf_16x_unused)); | |
5840 | cl_u1_nor2_16x spare18_nor2_16x (.in0(1'b0), | |
5841 | .in1(1'b0), | |
5842 | .out(spare18_nor2_16x_unused)); | |
5843 | cl_u1_inv_32x spare18_inv_32x (.in(1'b1), | |
5844 | .out(spare18_inv_32x_unused)); | |
5845 | ||
5846 | cl_sc1_msff_8x spare19_flop (.l1clk(l1clk), | |
5847 | .siclk(siclk), | |
5848 | .soclk(soclk), | |
5849 | .si(si_19), | |
5850 | .so(so_19), | |
5851 | .d(1'b0), | |
5852 | .q(spare19_flop_unused)); | |
5853 | assign si_19 = so_18; | |
5854 | ||
5855 | cl_u1_buf_32x spare19_buf_32x (.in(1'b1), | |
5856 | .out(spare19_buf_32x_unused)); | |
5857 | cl_u1_nand3_8x spare19_nand3_8x (.in0(1'b1), | |
5858 | .in1(1'b1), | |
5859 | .in2(1'b1), | |
5860 | .out(spare19_nand3_8x_unused)); | |
5861 | cl_u1_inv_8x spare19_inv_8x (.in(1'b1), | |
5862 | .out(spare19_inv_8x_unused)); | |
5863 | cl_u1_aoi22_4x spare19_aoi22_4x (.in00(1'b1), | |
5864 | .in01(1'b1), | |
5865 | .in10(1'b1), | |
5866 | .in11(1'b1), | |
5867 | .out(spare19_aoi22_4x_unused)); | |
5868 | cl_u1_buf_8x spare19_buf_8x (.in(1'b1), | |
5869 | .out(spare19_buf_8x_unused)); | |
5870 | cl_u1_oai22_4x spare19_oai22_4x (.in00(1'b1), | |
5871 | .in01(1'b1), | |
5872 | .in10(1'b1), | |
5873 | .in11(1'b1), | |
5874 | .out(spare19_oai22_4x_unused)); | |
5875 | cl_u1_inv_16x spare19_inv_16x (.in(1'b1), | |
5876 | .out(spare19_inv_16x_unused)); | |
5877 | cl_u1_nand2_16x spare19_nand2_16x (.in0(1'b1), | |
5878 | .in1(1'b1), | |
5879 | .out(spare19_nand2_16x_unused)); | |
5880 | cl_u1_nor3_4x spare19_nor3_4x (.in0(1'b0), | |
5881 | .in1(1'b0), | |
5882 | .in2(1'b0), | |
5883 | .out(spare19_nor3_4x_unused)); | |
5884 | cl_u1_nand2_8x spare19_nand2_8x (.in0(1'b1), | |
5885 | .in1(1'b1), | |
5886 | .out(spare19_nand2_8x_unused)); | |
5887 | cl_u1_buf_16x spare19_buf_16x (.in(1'b1), | |
5888 | .out(spare19_buf_16x_unused)); | |
5889 | cl_u1_nor2_16x spare19_nor2_16x (.in0(1'b0), | |
5890 | .in1(1'b0), | |
5891 | .out(spare19_nor2_16x_unused)); | |
5892 | cl_u1_inv_32x spare19_inv_32x (.in(1'b1), | |
5893 | .out(spare19_inv_32x_unused)); | |
5894 | ||
5895 | ||
5896 | ||
5897 | cl_sc1_msff_8x spare20_flop (.l1clk(l1clk), | |
5898 | .siclk(siclk), | |
5899 | .soclk(soclk), | |
5900 | .si(si_20), | |
5901 | .so(so_20), | |
5902 | .d(fbdic_link_cnt_eq_0_in), | |
5903 | .q(fbdic_link_cnt_eq_0)); | |
5904 | assign si_20 = so_19; | |
5905 | ||
5906 | cl_u1_buf_32x spare20_buf_32x (.in(1'b1), | |
5907 | .out(spare20_buf_32x_unused)); | |
5908 | cl_u1_nand3_8x spare20_nand3_8x (.in0(1'b1), | |
5909 | .in1(1'b1), | |
5910 | .in2(1'b1), | |
5911 | .out(spare20_nand3_8x_unused)); | |
5912 | cl_u1_inv_8x spare20_inv_8x (.in(1'b1), | |
5913 | .out(spare20_inv_8x_unused)); | |
5914 | cl_u1_aoi22_4x spare20_aoi22_4x (.in00(1'b1), | |
5915 | .in01(1'b1), | |
5916 | .in10(1'b1), | |
5917 | .in11(1'b1), | |
5918 | .out(spare20_aoi22_4x_unused)); | |
5919 | cl_u1_buf_8x spare20_buf_8x (.in(1'b1), | |
5920 | .out(spare20_buf_8x_unused)); | |
5921 | cl_u1_oai22_4x spare20_oai22_4x (.in00(1'b1), | |
5922 | .in01(1'b1), | |
5923 | .in10(1'b1), | |
5924 | .in11(1'b1), | |
5925 | .out(spare20_oai22_4x_unused)); | |
5926 | cl_u1_inv_16x spare20_inv_16x (.in(1'b1), | |
5927 | .out(spare20_inv_16x_unused)); | |
5928 | cl_u1_nand2_16x spare20_nand2_16x (.in0(1'b1), | |
5929 | .in1(1'b1), | |
5930 | .out(spare20_nand2_16x_unused)); | |
5931 | cl_u1_nor3_4x spare20_nor3_4x (.in0(1'b0), | |
5932 | .in1(1'b0), | |
5933 | .in2(1'b0), | |
5934 | .out(spare20_nor3_4x_unused)); | |
5935 | cl_u1_nand2_8x spare20_nand2_8x (.in0(1'b1), | |
5936 | .in1(1'b1), | |
5937 | .out(spare20_nand2_8x_unused)); | |
5938 | cl_u1_buf_16x spare20_buf_16x (.in(1'b1), | |
5939 | .out(spare20_buf_16x_unused)); | |
5940 | cl_u1_nor2_16x spare20_nor2_16x (.in0(1'b0), | |
5941 | .in1(1'b0), | |
5942 | .out(spare20_nor2_16x_unused)); | |
5943 | cl_u1_inv_32x spare20_inv_32x (.in(1'b1), | |
5944 | .out(spare20_inv_32x_unused)); | |
5945 | ||
5946 | cl_sc1_msff_8x spare21_flop (.l1clk(l1clk), | |
5947 | .siclk(siclk), | |
5948 | .soclk(soclk), | |
5949 | .si(si_21), | |
5950 | .so(so_21), | |
5951 | .d(1'b0), | |
5952 | .q(spare21_flop_unused)); | |
5953 | assign si_21 = so_20; | |
5954 | ||
5955 | cl_u1_buf_32x spare21_buf_32x (.in(1'b1), | |
5956 | .out(spare21_buf_32x_unused)); | |
5957 | cl_u1_nand3_8x spare21_nand3_8x (.in0(1'b1), | |
5958 | .in1(1'b1), | |
5959 | .in2(1'b1), | |
5960 | .out(spare21_nand3_8x_unused)); | |
5961 | cl_u1_inv_8x spare21_inv_8x (.in(1'b1), | |
5962 | .out(spare21_inv_8x_unused)); | |
5963 | cl_u1_aoi22_4x spare21_aoi22_4x (.in00(1'b1), | |
5964 | .in01(1'b1), | |
5965 | .in10(1'b1), | |
5966 | .in11(1'b1), | |
5967 | .out(spare21_aoi22_4x_unused)); | |
5968 | cl_u1_buf_8x spare21_buf_8x (.in(1'b1), | |
5969 | .out(spare21_buf_8x_unused)); | |
5970 | cl_u1_oai22_4x spare21_oai22_4x (.in00(1'b1), | |
5971 | .in01(1'b1), | |
5972 | .in10(1'b1), | |
5973 | .in11(1'b1), | |
5974 | .out(spare21_oai22_4x_unused)); | |
5975 | cl_u1_inv_16x spare21_inv_16x (.in(1'b1), | |
5976 | .out(spare21_inv_16x_unused)); | |
5977 | cl_u1_nand2_16x spare21_nand2_16x (.in0(1'b1), | |
5978 | .in1(1'b1), | |
5979 | .out(spare21_nand2_16x_unused)); | |
5980 | cl_u1_nor3_4x spare21_nor3_4x (.in0(1'b0), | |
5981 | .in1(1'b0), | |
5982 | .in2(1'b0), | |
5983 | .out(spare21_nor3_4x_unused)); | |
5984 | cl_u1_nand2_8x spare21_nand2_8x (.in0(1'b1), | |
5985 | .in1(1'b1), | |
5986 | .out(spare21_nand2_8x_unused)); | |
5987 | cl_u1_buf_16x spare21_buf_16x (.in(1'b1), | |
5988 | .out(spare21_buf_16x_unused)); | |
5989 | cl_u1_nor2_16x spare21_nor2_16x (.in0(1'b0), | |
5990 | .in1(1'b0), | |
5991 | .out(spare21_nor2_16x_unused)); | |
5992 | cl_u1_inv_32x spare21_inv_32x (.in(1'b1), | |
5993 | .out(spare21_inv_32x_unused)); | |
5994 | assign spares_scanout = so_21; | |
5995 | ||
5996 | // Test Mode domain - signals that need to be maintained during reset/scan if tcu_mcu_testmode is not asserted. | |
5997 | mcu_fbdtm_ctl fbdtm ( // FS:wmr_protect | |
5998 | .wmr_scan_in(fbdtm_wmr_scanin), | |
5999 | .wmr_scan_out(fbdtm_wmr_scanout), | |
6000 | .scan_in(fbdtm_scanin), | |
6001 | .scan_out(fbdtm_scanout), | |
6002 | .drl2clk(drl2clk), | |
6003 | .fbdic_aclk_wmr(aclk_wmr), | |
6004 | .fbdic_loopback_1(fbdic_loopback[1]), | |
6005 | .drif_ucb_data(drif_ucb_data[47:0]), | |
6006 | .fbdic_sync_frm_period(fbdic_sync_frm_period[5:0]), | |
6007 | .fbdic_sds_config(fbdic_sds_config[29:0]), | |
6008 | .fbdic_sds_invert(fbdic_sds_invert[47:0]), | |
6009 | .fbdic_sds_testcfg(fbdic_sds_testcfg[31:0]), | |
6010 | .rdpctl_kp_lnk_up(rdpctl_kp_lnk_up), | |
6011 | .rdpctl_kp_lnk_up_clr(rdpctl_kp_lnk_up_clr), | |
6012 | .fbdic_idle_lfsr_reset(fbdic_idle_lfsr_reset), | |
6013 | .mcu_fsr0_cfgrx_align(mcu_fsr0_cfgrx_align), | |
6014 | .mcu_fsr1_cfgrx_align(mcu_fsr1_cfgrx_align), | |
6015 | .mcu_fsr0_cfgtx_enidl(mcu_fsr0_cfgtx_enidl), | |
6016 | .mcu_fsr1_cfgtx_enidl(mcu_fsr1_cfgtx_enidl), | |
6017 | .drif_ucb_wr_req_vld(drif_ucb_wr_req_vld), | |
6018 | .drif_ucb_addr(drif_ucb_addr[12:0]), | |
6019 | .drif_dbg_trig_reg_ld(drif_dbg_trig_reg_ld), | |
6020 | .drif_single_channel_mode(drif_single_channel_mode), | |
6021 | .fbdic_fbd_state(fbdic_fbd_state[2:0]), | |
6022 | .fbd0_frame_lock(fbd0_frame_lock[13:0]), | |
6023 | .fbd1_frame_lock(fbd1_frame_lock[13:0]), | |
6024 | .fbdic_disable_state(fbdic_disable_state), | |
6025 | .fbdic_serdes_dtm(fbdic_serdes_dtm), | |
6026 | .fbdic_status_frame(fbdic_status_frame), | |
6027 | .tcu_pce_ov(tcu_pce_ov), | |
6028 | .tcu_aclk(tcu_aclk), | |
6029 | .tcu_bclk(tcu_bclk), | |
6030 | .tcu_scan_en(tcu_scan_en), | |
6031 | .wmr_protect(wmr_protect), | |
6032 | .tcu_mcu_testmode(tcu_mcu_testmode), | |
6033 | .fbdtm_si(fbdtm_si), | |
6034 | .fbdtm_so(fbdtm_so), | |
6035 | .fbdtm_wmr_si(fbdtm_wmr_si), | |
6036 | .fbdtm_wmr_so(fbdtm_wmr_so) | |
6037 | ); | |
6038 | ||
6039 | assign fbdic_wmr_scanout = ~(~wmr_scan_out | wmr_protect); | |
6040 | ||
6041 | // fixscan start: | |
6042 | assign ff_fbd_state_scanin = scan_in ; | |
6043 | assign ff_sync_ier_scanin = ff_fbd_state_scanout ; | |
6044 | assign ff_fr_issued_scanin = ff_sync_ier_scanout ; | |
6045 | assign pff_chnl_reset0_scanin = ff_fr_issued_scanout ; | |
6046 | assign ff_chnl_reset_error_mode_scanin = pff_chnl_reset0_scanout ; | |
6047 | assign ff_elect_idle_detect_scanin = ff_chnl_reset_error_mode_scanout; | |
6048 | assign ff_tdisable_done_scanin = ff_elect_idle_detect_scanout; | |
6049 | assign ff_tdisable_cnt_scanin = ff_tdisable_done_scanout ; | |
6050 | assign ff_tdisable_start_scanin = ff_tdisable_cnt_scanout ; | |
6051 | assign ff_tcalibrate_done_scanin = ff_tdisable_start_scanout; | |
6052 | assign ff_tcalibrate_cnt_scanin = ff_tcalibrate_done_scanout; | |
6053 | assign ff_tclktrain_min_cnt_scanin = ff_tcalibrate_cnt_scanout; | |
6054 | assign ff_enable_sync_count_scanin = ff_tclktrain_min_cnt_scanout; | |
6055 | assign ff_tclktrain_done_scanin = ff_enable_sync_count_scanout; | |
6056 | assign ff_tclktrain_timeout_cnt_scanin = ff_tclktrain_done_scanout; | |
6057 | assign ff_testing_done_scanin = ff_tclktrain_timeout_cnt_scanout; | |
6058 | assign ff_testing_timeout_cnt_scanin = ff_testing_done_scanout ; | |
6059 | assign ff_polling_done_scanin = ff_testing_timeout_cnt_scanout; | |
6060 | assign ff_polling_timeout_cnt_scanin = ff_polling_done_scanout ; | |
6061 | assign ff_config_done_scanin = ff_polling_timeout_cnt_scanout; | |
6062 | assign ff_config_timeout_cnt_scanin = ff_config_done_scanout ; | |
6063 | assign ff_cke_reg_d1_scanin = ff_config_timeout_cnt_scanout; | |
6064 | assign ff_l0s_stall_scanin = ff_cke_reg_d1_scanout ; | |
6065 | assign ff_loopback_scanin = ff_l0s_stall_scanout ; | |
6066 | assign sync_stspll5_scanin = ff_loopback_scanout ; | |
6067 | assign sync_stspll4_scanin = sync_stspll5_scanout ; | |
6068 | assign sync_stspll3_scanin = sync_stspll4_scanout ; | |
6069 | assign sync_stspll2_scanin = sync_stspll3_scanout ; | |
6070 | assign sync_stspll1_scanin = sync_stspll2_scanout ; | |
6071 | assign sync_stspll0_scanin = sync_stspll1_scanout ; | |
6072 | assign ff_sds_test_status_scanin = sync_stspll0_scanout ; | |
6073 | assign ff_config_reg_addr_scanin = ff_sds_test_status_scanout; | |
6074 | assign ff_cnfg_access_pending_scanin = ff_config_reg_addr_scanout; | |
6075 | assign ff_cnfgreg_wr_data_scanin = ff_cnfg_access_pending_scanout; | |
6076 | assign ff_config_reg_write_d1_scanin = ff_cnfgreg_wr_data_scanout; | |
6077 | assign ff_thermal_trip_scanin = ff_config_reg_write_d1_scanout; | |
6078 | assign ff_fbu_error_scanin = ff_thermal_trip_scanout ; | |
6079 | assign ff_err_fbr_scanin = ff_fbu_error_scanout ; | |
6080 | assign ff_ts_data_scanin = ff_err_fbr_scanout ; | |
6081 | assign ff_l0_state_scanin = ff_ts_data_scanout ; | |
6082 | assign ff_l0_state_dly_scanin = ff_l0_state_scanout ; | |
6083 | assign ff_ts0_cnt_scanin = ff_l0_state_dly_scanout ; | |
6084 | assign ff_ts1_cnt_scanin = ff_ts0_cnt_scanout ; | |
6085 | assign ff_ts2_cnt_scanin = ff_ts1_cnt_scanout ; | |
6086 | assign ff_ts2_seq_id_scanin = ff_ts2_cnt_scanout ; | |
6087 | assign ff_ts3_cnt_scanin = ff_ts2_seq_id_scanout ; | |
6088 | assign ff_sequence_scanin = ff_ts3_cnt_scanout ; | |
6089 | assign ff_ts_exp_data_scanin = ff_sequence_scanout ; | |
6090 | assign ff_nb_ts2_seq_id0_scanin = ff_ts_exp_data_scanout ; | |
6091 | assign ff_nb_ts_cnt0_scanin = ff_nb_ts2_seq_id0_scanout; | |
6092 | assign ff_ts_match0_scanin = ff_nb_ts_cnt0_scanout ; | |
6093 | assign ff_ts_match0_cnt_scanin = ff_ts_match0_scanout ; | |
6094 | assign ff_nb_ts2_seq_id1_scanin = ff_ts_match0_cnt_scanout ; | |
6095 | assign ff_nb_ts_cnt1_scanin = ff_nb_ts2_seq_id1_scanout; | |
6096 | assign ff_ts_match1_scanin = ff_nb_ts_cnt1_scanout ; | |
6097 | assign ff_ts_match1_cnt_scanin = ff_ts_match1_scanout ; | |
6098 | assign ff_rt_lat_cntr0_scanin = ff_ts_match1_cnt_scanout ; | |
6099 | assign ff_rt_lat_cntr1_scanin = ff_rt_lat_cntr0_scanout ; | |
6100 | assign ff_ch0_cap_reg_scanin = ff_rt_lat_cntr1_scanout ; | |
6101 | assign ff_ch1_cap_reg_scanin = ff_ch0_cap_reg_scanout ; | |
6102 | assign ff_kp_lnk_up_d1_scanin = ff_ch1_cap_reg_scanout ; | |
6103 | assign ff_sync_frame_req_early_scanin = ff_kp_lnk_up_d1_scanout ; | |
6104 | assign ff_sync_frame_req_delay_scanin = ff_sync_frame_req_early_scanout; | |
6105 | assign ff_rd_cmd_a_d1_scanin = ff_sync_frame_req_delay_scanout; | |
6106 | assign ff_scr_dly_scanin = ff_rd_cmd_a_d1_scanout ; | |
6107 | assign ff_issue_pre_all_cmd_scanin = ff_scr_dly_scanout ; | |
6108 | assign ff_pre_all_rank_scanin = ff_issue_pre_all_cmd_scanout; | |
6109 | assign ff_f_scanin = ff_pre_all_rank_scanout ; | |
6110 | assign ff_a_cmd_scanin = ff_f_scanout ; | |
6111 | assign ff_special_cmd_scanin = ff_a_cmd_scanout ; | |
6112 | assign ff_last_trans_id0_scanin = ff_special_cmd_scanout ; | |
6113 | assign ff_last_trans_id1_scanin = ff_last_trans_id0_scanout; | |
6114 | assign ff_bc_cmd_scanin = ff_last_trans_id1_scanout; | |
6115 | assign ff_chnl_latency_cntr_scanin = ff_bc_cmd_scanout ; | |
6116 | assign ff_rddata_vld_d1_scanin = ff_chnl_latency_cntr_scanout; | |
6117 | assign ff_latq_deq_dly_scanin = ff_rddata_vld_d1_scanout ; | |
6118 | assign ff_latq_dout_reg_scanin = ff_latq_deq_dly_scanout ; | |
6119 | assign ff_status_frame_d1_scanin = ff_latq_dout_reg_scanout ; | |
6120 | assign ff_cnfgreg_data_scanin = ff_status_frame_d1_scanout; | |
6121 | assign ff_fbd_delay_scanin = ff_cnfgreg_data_scanout ; | |
6122 | assign latq_scanin = ff_fbd_delay_scanout ; | |
6123 | assign ff_fbd_error_scanin = latq_scanout ; | |
6124 | assign ff_fbd_error_dly_scanin = ff_fbd_error_scanout ; | |
6125 | assign ff_fbd_error_save_scanin = ff_fbd_error_dly_scanout ; | |
6126 | assign ff_chnl_alert_scanin = ff_fbd_error_save_scanout; | |
6127 | assign ff_crc_sel0_scanin = ff_chnl_alert_scanout ; | |
6128 | assign ff_crc_sel1_scanin = ff_crc_sel0_scanout ; | |
6129 | assign scr_qual_scanin = ff_crc_sel1_scanout ; | |
6130 | assign ff_err_fast_chnl_reset_scanin = scr_qual_scanout ; | |
6131 | assign ff_err_recov_scanin = ff_err_fast_chnl_reset_scanout; | |
6132 | assign ff_err_unrecov_scanin = ff_err_recov_scanout ; | |
6133 | assign ff_err_state_scanin = ff_err_unrecov_scanout ; | |
6134 | assign ff_sbts_cnt_scanin = ff_err_state_scanout ; | |
6135 | assign pff_ibrx_done_flag_scanin = ff_sbts_cnt_scanout ; | |
6136 | assign ff_ibist_data_scanin = pff_ibrx_done_flag_scanout; | |
6137 | assign ff_ibist_done_scanin = ff_ibist_data_scanout ; | |
6138 | assign ff_rx_s0s1_match_dly_scanin = ff_ibist_done_scanout ; | |
6139 | assign ibist_scanin = ff_rx_s0s1_match_dly_scanout; | |
6140 | assign ff_err_fbxi_scanin = ibist_scanout ; | |
6141 | assign ff_fbr_injected_scanin = ff_err_fbxi_scanout ; | |
6142 | assign ff_serdes_dtm_scanin = ff_fbr_injected_scanout ; | |
6143 | assign ff_dtm_zero_cnt_scanin = ff_serdes_dtm_scanout ; | |
6144 | assign ff_dtm_state_scanin = ff_dtm_zero_cnt_scanout ; | |
6145 | assign ff_srds_dtm_muxsel_scanin = ff_dtm_state_scanout ; | |
6146 | assign spares_scanin = ff_srds_dtm_muxsel_scanout; | |
6147 | assign fbdtm_scanin = spares_scanout ; | |
6148 | assign scan_out = fbdtm_scanout ; | |
6149 | ||
6150 | assign pff_fbd_state_wmr_scanin = wmr_scan_in ; | |
6151 | assign pff_fast_reset_wmr_scanin = pff_fbd_state_wmr_scanout; | |
6152 | assign pff_chnl_reset1_wmr_scanin = pff_fast_reset_wmr_scanout; | |
6153 | assign pff_sb2nb_map_wmr_scanin = pff_chnl_reset1_wmr_scanout; | |
6154 | assign pff_amb_test_param_wmr_scanin = pff_sb2nb_map_wmr_scanout; | |
6155 | assign pff_failover_config_wmr_scanin = pff_amb_test_param_wmr_scanout; | |
6156 | assign pff_tdisable_period_wmr_scanin = pff_failover_config_wmr_scanout; | |
6157 | assign pff_tcalibrate_period_wmr_scanin = pff_tdisable_period_wmr_scanout; | |
6158 | assign pff_tclktrain_min_wmr_scanin = pff_tcalibrate_period_wmr_scanout; | |
6159 | assign pff_tclktrain_timeout_wmr_scanin = pff_tclktrain_min_wmr_scanout; | |
6160 | assign pff_testing_timeout_wmr_scanin = pff_tclktrain_timeout_wmr_scanout; | |
6161 | assign pff_polling_timeout_wmr_scanin = pff_testing_timeout_wmr_scanout; | |
6162 | assign pff_config_timeout_wmr_scanin = pff_polling_timeout_wmr_scanout; | |
6163 | assign pff_per_rank_cke_wmr_scanin = pff_config_timeout_wmr_scanout; | |
6164 | assign pff_l0s_time_wmr_scanin = pff_per_rank_cke_wmr_scanout; | |
6165 | assign pff_mcu_syndrome_wmr_scanin = pff_l0s_time_wmr_scanout ; | |
6166 | assign pff_inj_err_src_wmr_scanin = pff_mcu_syndrome_wmr_scanout; | |
6167 | assign pff_fbr_count_wmr_scanin = pff_inj_err_src_wmr_scanout; | |
6168 | assign ff_rt_lat0_wmr_scanin = pff_fbr_count_wmr_scanout; | |
6169 | assign ff_rt_lat1_wmr_scanin = ff_rt_lat0_wmr_scanout ; | |
6170 | assign ff_lane_align_wmr_scanin = ff_rt_lat1_wmr_scanout ; | |
6171 | assign pff_sbfibportctl_wmr_scanin = ff_lane_align_wmr_scanout; | |
6172 | assign pff_ibtx_done_flag_wmr_scanin = pff_sbfibportctl_wmr_scanout; | |
6173 | assign pff_ibtx_start_wmr_scanin = pff_ibtx_done_flag_wmr_scanout; | |
6174 | assign pff_sbfibpgctl_wmr_scanin = pff_ibtx_start_wmr_scanout; | |
6175 | assign pff_sbfibpattbuf1_wmr_scanin = pff_sbfibpgctl_wmr_scanout; | |
6176 | assign pff_sbfibtxmsk_wmr_scanin = pff_sbfibpattbuf1_wmr_scanout; | |
6177 | assign pff_sbfibtxshft_wmr_scanin = pff_sbfibtxmsk_wmr_scanout; | |
6178 | assign pff_sbfibpattbuf2_wmr_scanin = pff_sbfibtxshft_wmr_scanout; | |
6179 | assign pff_sbfibpatt2en_wmr_scanin = pff_sbfibpattbuf2_wmr_scanout; | |
6180 | assign pff_sbfibinit_wmr_scanin = pff_sbfibpatt2en_wmr_scanout; | |
6181 | assign pff_sbibistmisc_wmr_scanin = pff_sbfibinit_wmr_scanout; | |
6182 | assign pff_nbfibportctl_wmr_scanin = pff_sbibistmisc_wmr_scanout; | |
6183 | assign pff_ibrx_start_wmr_scanin = pff_nbfibportctl_wmr_scanout; | |
6184 | assign pff_nbfibpgctl_wmr_scanin = pff_ibrx_start_wmr_scanout; | |
6185 | assign pff_nbfibpattbuf1_wmr_scanin = pff_nbfibpgctl_wmr_scanout; | |
6186 | assign pff_nbfibrxmsk_wmr_scanin = pff_nbfibpattbuf1_wmr_scanout; | |
6187 | assign pff_nbfibrxshft_wmr_scanin = pff_nbfibrxmsk_wmr_scanout; | |
6188 | assign pff_nbfibpattbuf2_wmr_scanin = pff_nbfibrxshft_wmr_scanout; | |
6189 | assign pff_nbfibpatt2en_wmr_scanin = pff_nbfibpattbuf2_wmr_scanout; | |
6190 | assign fbdtm_wmr_scanin = pff_nbfibpatt2en_wmr_scanout; | |
6191 | assign wmr_scan_out = fbdtm_wmr_scanout ; | |
6192 | // fixscan end: | |
6193 | endmodule | |
6194 | ||
6195 | ||
6196 | ||
6197 | ||
6198 | ||
6199 | ||
6200 | // any PARAMS parms go into naming of macro | |
6201 | ||
6202 | module mcu_fbdic_ctl_l1clkhdr_ctl_macro ( | |
6203 | l2clk, | |
6204 | l1en, | |
6205 | pce_ov, | |
6206 | stop, | |
6207 | se, | |
6208 | l1clk); | |
6209 | ||
6210 | ||
6211 | input l2clk; | |
6212 | input l1en; | |
6213 | input pce_ov; | |
6214 | input stop; | |
6215 | input se; | |
6216 | output l1clk; | |
6217 | ||
6218 | ||
6219 | ||
6220 | ||
6221 | ||
6222 | cl_sc1_l1hdr_8x c_0 ( | |
6223 | ||
6224 | ||
6225 | .l2clk(l2clk), | |
6226 | .pce(l1en), | |
6227 | .l1clk(l1clk), | |
6228 | .se(se), | |
6229 | .pce_ov(pce_ov), | |
6230 | .stop(stop) | |
6231 | ); | |
6232 | ||
6233 | ||
6234 | ||
6235 | endmodule | |
6236 | ||
6237 | ||
6238 | ||
6239 | ||
6240 | ||
6241 | ||
6242 | ||
6243 | ||
6244 | ||
6245 | ||
6246 | ||
6247 | ||
6248 | ||
6249 | // any PARAMS parms go into naming of macro | |
6250 | ||
6251 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_4 ( | |
6252 | din, | |
6253 | en, | |
6254 | l1clk, | |
6255 | scan_in, | |
6256 | siclk, | |
6257 | soclk, | |
6258 | dout, | |
6259 | scan_out); | |
6260 | wire [3:0] fdin; | |
6261 | wire [2:0] so; | |
6262 | ||
6263 | input [3:0] din; | |
6264 | input en; | |
6265 | input l1clk; | |
6266 | input scan_in; | |
6267 | ||
6268 | ||
6269 | input siclk; | |
6270 | input soclk; | |
6271 | ||
6272 | output [3:0] dout; | |
6273 | output scan_out; | |
6274 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
6275 | ||
6276 | ||
6277 | ||
6278 | ||
6279 | ||
6280 | ||
6281 | dff #(4) d0_0 ( | |
6282 | .l1clk(l1clk), | |
6283 | .siclk(siclk), | |
6284 | .soclk(soclk), | |
6285 | .d(fdin[3:0]), | |
6286 | .si({scan_in,so[2:0]}), | |
6287 | .so({so[2:0],scan_out}), | |
6288 | .q(dout[3:0]) | |
6289 | ); | |
6290 | ||
6291 | ||
6292 | ||
6293 | ||
6294 | ||
6295 | ||
6296 | ||
6297 | ||
6298 | ||
6299 | ||
6300 | ||
6301 | ||
6302 | endmodule | |
6303 | ||
6304 | ||
6305 | ||
6306 | ||
6307 | ||
6308 | ||
6309 | ||
6310 | ||
6311 | ||
6312 | ||
6313 | ||
6314 | ||
6315 | ||
6316 | // any PARAMS parms go into naming of macro | |
6317 | ||
6318 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_1 ( | |
6319 | din, | |
6320 | en, | |
6321 | l1clk, | |
6322 | scan_in, | |
6323 | siclk, | |
6324 | soclk, | |
6325 | dout, | |
6326 | scan_out); | |
6327 | wire [0:0] fdin; | |
6328 | ||
6329 | input [0:0] din; | |
6330 | input en; | |
6331 | input l1clk; | |
6332 | input scan_in; | |
6333 | ||
6334 | ||
6335 | input siclk; | |
6336 | input soclk; | |
6337 | ||
6338 | output [0:0] dout; | |
6339 | output scan_out; | |
6340 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
6341 | ||
6342 | ||
6343 | ||
6344 | ||
6345 | ||
6346 | ||
6347 | dff #(1) d0_0 ( | |
6348 | .l1clk(l1clk), | |
6349 | .siclk(siclk), | |
6350 | .soclk(soclk), | |
6351 | .d(fdin[0:0]), | |
6352 | .si(scan_in), | |
6353 | .so(scan_out), | |
6354 | .q(dout[0:0]) | |
6355 | ); | |
6356 | ||
6357 | ||
6358 | ||
6359 | ||
6360 | ||
6361 | ||
6362 | ||
6363 | ||
6364 | ||
6365 | ||
6366 | ||
6367 | ||
6368 | endmodule | |
6369 | ||
6370 | ||
6371 | ||
6372 | ||
6373 | ||
6374 | ||
6375 | ||
6376 | ||
6377 | ||
6378 | ||
6379 | ||
6380 | ||
6381 | ||
6382 | // any PARAMS parms go into naming of macro | |
6383 | ||
6384 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_3 ( | |
6385 | din, | |
6386 | en, | |
6387 | l1clk, | |
6388 | scan_in, | |
6389 | siclk, | |
6390 | soclk, | |
6391 | dout, | |
6392 | scan_out); | |
6393 | wire [2:0] fdin; | |
6394 | wire [1:0] so; | |
6395 | ||
6396 | input [2:0] din; | |
6397 | input en; | |
6398 | input l1clk; | |
6399 | input scan_in; | |
6400 | ||
6401 | ||
6402 | input siclk; | |
6403 | input soclk; | |
6404 | ||
6405 | output [2:0] dout; | |
6406 | output scan_out; | |
6407 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
6408 | ||
6409 | ||
6410 | ||
6411 | ||
6412 | ||
6413 | ||
6414 | dff #(3) d0_0 ( | |
6415 | .l1clk(l1clk), | |
6416 | .siclk(siclk), | |
6417 | .soclk(soclk), | |
6418 | .d(fdin[2:0]), | |
6419 | .si({scan_in,so[1:0]}), | |
6420 | .so({so[1:0],scan_out}), | |
6421 | .q(dout[2:0]) | |
6422 | ); | |
6423 | ||
6424 | ||
6425 | ||
6426 | ||
6427 | ||
6428 | ||
6429 | ||
6430 | ||
6431 | ||
6432 | ||
6433 | ||
6434 | ||
6435 | endmodule | |
6436 | ||
6437 | ||
6438 | ||
6439 | ||
6440 | ||
6441 | ||
6442 | ||
6443 | ||
6444 | ||
6445 | ||
6446 | ||
6447 | ||
6448 | ||
6449 | // any PARAMS parms go into naming of macro | |
6450 | ||
6451 | module mcu_fbdic_ctl_msff_ctl_macro ( | |
6452 | din, | |
6453 | l1clk, | |
6454 | scan_in, | |
6455 | siclk, | |
6456 | soclk, | |
6457 | dout, | |
6458 | scan_out); | |
6459 | wire [0:0] fdin; | |
6460 | ||
6461 | input [0:0] din; | |
6462 | input l1clk; | |
6463 | input scan_in; | |
6464 | ||
6465 | ||
6466 | input siclk; | |
6467 | input soclk; | |
6468 | ||
6469 | output [0:0] dout; | |
6470 | output scan_out; | |
6471 | assign fdin[0:0] = din[0:0]; | |
6472 | ||
6473 | ||
6474 | ||
6475 | ||
6476 | ||
6477 | ||
6478 | dff #(1) d0_0 ( | |
6479 | .l1clk(l1clk), | |
6480 | .siclk(siclk), | |
6481 | .soclk(soclk), | |
6482 | .d(fdin[0:0]), | |
6483 | .si(scan_in), | |
6484 | .so(scan_out), | |
6485 | .q(dout[0:0]) | |
6486 | ); | |
6487 | ||
6488 | ||
6489 | ||
6490 | ||
6491 | ||
6492 | ||
6493 | ||
6494 | ||
6495 | ||
6496 | ||
6497 | ||
6498 | ||
6499 | endmodule | |
6500 | ||
6501 | ||
6502 | ||
6503 | ||
6504 | ||
6505 | ||
6506 | ||
6507 | ||
6508 | ||
6509 | ||
6510 | ||
6511 | ||
6512 | ||
6513 | // any PARAMS parms go into naming of macro | |
6514 | ||
6515 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_24 ( | |
6516 | din, | |
6517 | en, | |
6518 | l1clk, | |
6519 | scan_in, | |
6520 | siclk, | |
6521 | soclk, | |
6522 | dout, | |
6523 | scan_out); | |
6524 | wire [23:0] fdin; | |
6525 | wire [22:0] so; | |
6526 | ||
6527 | input [23:0] din; | |
6528 | input en; | |
6529 | input l1clk; | |
6530 | input scan_in; | |
6531 | ||
6532 | ||
6533 | input siclk; | |
6534 | input soclk; | |
6535 | ||
6536 | output [23:0] dout; | |
6537 | output scan_out; | |
6538 | assign fdin[23:0] = (din[23:0] & {24{en}}) | (dout[23:0] & ~{24{en}}); | |
6539 | ||
6540 | ||
6541 | ||
6542 | ||
6543 | ||
6544 | ||
6545 | dff #(24) d0_0 ( | |
6546 | .l1clk(l1clk), | |
6547 | .siclk(siclk), | |
6548 | .soclk(soclk), | |
6549 | .d(fdin[23:0]), | |
6550 | .si({scan_in,so[22:0]}), | |
6551 | .so({so[22:0],scan_out}), | |
6552 | .q(dout[23:0]) | |
6553 | ); | |
6554 | ||
6555 | ||
6556 | ||
6557 | ||
6558 | ||
6559 | ||
6560 | ||
6561 | ||
6562 | ||
6563 | ||
6564 | ||
6565 | ||
6566 | endmodule | |
6567 | ||
6568 | ||
6569 | ||
6570 | ||
6571 | ||
6572 | ||
6573 | ||
6574 | ||
6575 | ||
6576 | ||
6577 | ||
6578 | ||
6579 | ||
6580 | // any PARAMS parms go into naming of macro | |
6581 | ||
6582 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_16 ( | |
6583 | din, | |
6584 | en, | |
6585 | l1clk, | |
6586 | scan_in, | |
6587 | siclk, | |
6588 | soclk, | |
6589 | dout, | |
6590 | scan_out); | |
6591 | wire [15:0] fdin; | |
6592 | wire [14:0] so; | |
6593 | ||
6594 | input [15:0] din; | |
6595 | input en; | |
6596 | input l1clk; | |
6597 | input scan_in; | |
6598 | ||
6599 | ||
6600 | input siclk; | |
6601 | input soclk; | |
6602 | ||
6603 | output [15:0] dout; | |
6604 | output scan_out; | |
6605 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); | |
6606 | ||
6607 | ||
6608 | ||
6609 | ||
6610 | ||
6611 | ||
6612 | dff #(16) d0_0 ( | |
6613 | .l1clk(l1clk), | |
6614 | .siclk(siclk), | |
6615 | .soclk(soclk), | |
6616 | .d(fdin[15:0]), | |
6617 | .si({scan_in,so[14:0]}), | |
6618 | .so({so[14:0],scan_out}), | |
6619 | .q(dout[15:0]) | |
6620 | ); | |
6621 | ||
6622 | ||
6623 | ||
6624 | ||
6625 | ||
6626 | ||
6627 | ||
6628 | ||
6629 | ||
6630 | ||
6631 | ||
6632 | ||
6633 | endmodule | |
6634 | ||
6635 | ||
6636 | ||
6637 | ||
6638 | ||
6639 | ||
6640 | ||
6641 | ||
6642 | ||
6643 | ||
6644 | ||
6645 | ||
6646 | ||
6647 | // any PARAMS parms go into naming of macro | |
6648 | ||
6649 | module mcu_fbdic_ctl_msff_ctl_macro__width_28 ( | |
6650 | din, | |
6651 | l1clk, | |
6652 | scan_in, | |
6653 | siclk, | |
6654 | soclk, | |
6655 | dout, | |
6656 | scan_out); | |
6657 | wire [27:0] fdin; | |
6658 | wire [26:0] so; | |
6659 | ||
6660 | input [27:0] din; | |
6661 | input l1clk; | |
6662 | input scan_in; | |
6663 | ||
6664 | ||
6665 | input siclk; | |
6666 | input soclk; | |
6667 | ||
6668 | output [27:0] dout; | |
6669 | output scan_out; | |
6670 | assign fdin[27:0] = din[27:0]; | |
6671 | ||
6672 | ||
6673 | ||
6674 | ||
6675 | ||
6676 | ||
6677 | dff #(28) d0_0 ( | |
6678 | .l1clk(l1clk), | |
6679 | .siclk(siclk), | |
6680 | .soclk(soclk), | |
6681 | .d(fdin[27:0]), | |
6682 | .si({scan_in,so[26:0]}), | |
6683 | .so({so[26:0],scan_out}), | |
6684 | .q(dout[27:0]) | |
6685 | ); | |
6686 | ||
6687 | ||
6688 | ||
6689 | ||
6690 | ||
6691 | ||
6692 | ||
6693 | ||
6694 | ||
6695 | ||
6696 | ||
6697 | ||
6698 | endmodule | |
6699 | ||
6700 | ||
6701 | ||
6702 | ||
6703 | ||
6704 | ||
6705 | ||
6706 | ||
6707 | ||
6708 | ||
6709 | ||
6710 | ||
6711 | ||
6712 | // any PARAMS parms go into naming of macro | |
6713 | ||
6714 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_10 ( | |
6715 | din, | |
6716 | en, | |
6717 | l1clk, | |
6718 | scan_in, | |
6719 | siclk, | |
6720 | soclk, | |
6721 | dout, | |
6722 | scan_out); | |
6723 | wire [9:0] fdin; | |
6724 | wire [8:0] so; | |
6725 | ||
6726 | input [9:0] din; | |
6727 | input en; | |
6728 | input l1clk; | |
6729 | input scan_in; | |
6730 | ||
6731 | ||
6732 | input siclk; | |
6733 | input soclk; | |
6734 | ||
6735 | output [9:0] dout; | |
6736 | output scan_out; | |
6737 | assign fdin[9:0] = (din[9:0] & {10{en}}) | (dout[9:0] & ~{10{en}}); | |
6738 | ||
6739 | ||
6740 | ||
6741 | ||
6742 | ||
6743 | ||
6744 | dff #(10) d0_0 ( | |
6745 | .l1clk(l1clk), | |
6746 | .siclk(siclk), | |
6747 | .soclk(soclk), | |
6748 | .d(fdin[9:0]), | |
6749 | .si({scan_in,so[8:0]}), | |
6750 | .so({so[8:0],scan_out}), | |
6751 | .q(dout[9:0]) | |
6752 | ); | |
6753 | ||
6754 | ||
6755 | ||
6756 | ||
6757 | ||
6758 | ||
6759 | ||
6760 | ||
6761 | ||
6762 | ||
6763 | ||
6764 | ||
6765 | endmodule | |
6766 | ||
6767 | ||
6768 | ||
6769 | ||
6770 | ||
6771 | ||
6772 | ||
6773 | ||
6774 | ||
6775 | ||
6776 | ||
6777 | ||
6778 | ||
6779 | // any PARAMS parms go into naming of macro | |
6780 | ||
6781 | module mcu_fbdic_ctl_msff_ctl_macro__en_1 ( | |
6782 | din, | |
6783 | en, | |
6784 | l1clk, | |
6785 | scan_in, | |
6786 | siclk, | |
6787 | soclk, | |
6788 | dout, | |
6789 | scan_out); | |
6790 | wire [0:0] fdin; | |
6791 | ||
6792 | input [0:0] din; | |
6793 | input en; | |
6794 | input l1clk; | |
6795 | input scan_in; | |
6796 | ||
6797 | ||
6798 | input siclk; | |
6799 | input soclk; | |
6800 | ||
6801 | output [0:0] dout; | |
6802 | output scan_out; | |
6803 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
6804 | ||
6805 | ||
6806 | ||
6807 | ||
6808 | ||
6809 | ||
6810 | dff #(1) d0_0 ( | |
6811 | .l1clk(l1clk), | |
6812 | .siclk(siclk), | |
6813 | .soclk(soclk), | |
6814 | .d(fdin[0:0]), | |
6815 | .si(scan_in), | |
6816 | .so(scan_out), | |
6817 | .q(dout[0:0]) | |
6818 | ); | |
6819 | ||
6820 | ||
6821 | ||
6822 | ||
6823 | ||
6824 | ||
6825 | ||
6826 | ||
6827 | ||
6828 | ||
6829 | ||
6830 | ||
6831 | endmodule | |
6832 | ||
6833 | ||
6834 | ||
6835 | ||
6836 | ||
6837 | ||
6838 | ||
6839 | ||
6840 | ||
6841 | ||
6842 | ||
6843 | ||
6844 | ||
6845 | // any PARAMS parms go into naming of macro | |
6846 | ||
6847 | module mcu_fbdic_ctl_msff_ctl_macro__width_10 ( | |
6848 | din, | |
6849 | l1clk, | |
6850 | scan_in, | |
6851 | siclk, | |
6852 | soclk, | |
6853 | dout, | |
6854 | scan_out); | |
6855 | wire [9:0] fdin; | |
6856 | wire [8:0] so; | |
6857 | ||
6858 | input [9:0] din; | |
6859 | input l1clk; | |
6860 | input scan_in; | |
6861 | ||
6862 | ||
6863 | input siclk; | |
6864 | input soclk; | |
6865 | ||
6866 | output [9:0] dout; | |
6867 | output scan_out; | |
6868 | assign fdin[9:0] = din[9:0]; | |
6869 | ||
6870 | ||
6871 | ||
6872 | ||
6873 | ||
6874 | ||
6875 | dff #(10) d0_0 ( | |
6876 | .l1clk(l1clk), | |
6877 | .siclk(siclk), | |
6878 | .soclk(soclk), | |
6879 | .d(fdin[9:0]), | |
6880 | .si({scan_in,so[8:0]}), | |
6881 | .so({so[8:0],scan_out}), | |
6882 | .q(dout[9:0]) | |
6883 | ); | |
6884 | ||
6885 | ||
6886 | ||
6887 | ||
6888 | ||
6889 | ||
6890 | ||
6891 | ||
6892 | ||
6893 | ||
6894 | ||
6895 | ||
6896 | endmodule | |
6897 | ||
6898 | ||
6899 | ||
6900 | ||
6901 | ||
6902 | ||
6903 | ||
6904 | ||
6905 | ||
6906 | ||
6907 | ||
6908 | ||
6909 | ||
6910 | // any PARAMS parms go into naming of macro | |
6911 | ||
6912 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_20 ( | |
6913 | din, | |
6914 | en, | |
6915 | l1clk, | |
6916 | scan_in, | |
6917 | siclk, | |
6918 | soclk, | |
6919 | dout, | |
6920 | scan_out); | |
6921 | wire [19:0] fdin; | |
6922 | wire [18:0] so; | |
6923 | ||
6924 | input [19:0] din; | |
6925 | input en; | |
6926 | input l1clk; | |
6927 | input scan_in; | |
6928 | ||
6929 | ||
6930 | input siclk; | |
6931 | input soclk; | |
6932 | ||
6933 | output [19:0] dout; | |
6934 | output scan_out; | |
6935 | assign fdin[19:0] = (din[19:0] & {20{en}}) | (dout[19:0] & ~{20{en}}); | |
6936 | ||
6937 | ||
6938 | ||
6939 | ||
6940 | ||
6941 | ||
6942 | dff #(20) d0_0 ( | |
6943 | .l1clk(l1clk), | |
6944 | .siclk(siclk), | |
6945 | .soclk(soclk), | |
6946 | .d(fdin[19:0]), | |
6947 | .si({scan_in,so[18:0]}), | |
6948 | .so({so[18:0],scan_out}), | |
6949 | .q(dout[19:0]) | |
6950 | ); | |
6951 | ||
6952 | ||
6953 | ||
6954 | ||
6955 | ||
6956 | ||
6957 | ||
6958 | ||
6959 | ||
6960 | ||
6961 | ||
6962 | ||
6963 | endmodule | |
6964 | ||
6965 | ||
6966 | ||
6967 | ||
6968 | ||
6969 | ||
6970 | ||
6971 | ||
6972 | ||
6973 | ||
6974 | ||
6975 | ||
6976 | ||
6977 | // any PARAMS parms go into naming of macro | |
6978 | ||
6979 | module mcu_fbdic_ctl_msff_ctl_macro__width_20 ( | |
6980 | din, | |
6981 | l1clk, | |
6982 | scan_in, | |
6983 | siclk, | |
6984 | soclk, | |
6985 | dout, | |
6986 | scan_out); | |
6987 | wire [19:0] fdin; | |
6988 | wire [18:0] so; | |
6989 | ||
6990 | input [19:0] din; | |
6991 | input l1clk; | |
6992 | input scan_in; | |
6993 | ||
6994 | ||
6995 | input siclk; | |
6996 | input soclk; | |
6997 | ||
6998 | output [19:0] dout; | |
6999 | output scan_out; | |
7000 | assign fdin[19:0] = din[19:0]; | |
7001 | ||
7002 | ||
7003 | ||
7004 | ||
7005 | ||
7006 | ||
7007 | dff #(20) d0_0 ( | |
7008 | .l1clk(l1clk), | |
7009 | .siclk(siclk), | |
7010 | .soclk(soclk), | |
7011 | .d(fdin[19:0]), | |
7012 | .si({scan_in,so[18:0]}), | |
7013 | .so({so[18:0],scan_out}), | |
7014 | .q(dout[19:0]) | |
7015 | ); | |
7016 | ||
7017 | ||
7018 | ||
7019 | ||
7020 | ||
7021 | ||
7022 | ||
7023 | ||
7024 | ||
7025 | ||
7026 | ||
7027 | ||
7028 | endmodule | |
7029 | ||
7030 | ||
7031 | ||
7032 | ||
7033 | ||
7034 | ||
7035 | ||
7036 | ||
7037 | ||
7038 | ||
7039 | ||
7040 | ||
7041 | ||
7042 | // any PARAMS parms go into naming of macro | |
7043 | ||
7044 | module mcu_fbdic_ctl_msff_ctl_macro__width_16 ( | |
7045 | din, | |
7046 | l1clk, | |
7047 | scan_in, | |
7048 | siclk, | |
7049 | soclk, | |
7050 | dout, | |
7051 | scan_out); | |
7052 | wire [15:0] fdin; | |
7053 | wire [14:0] so; | |
7054 | ||
7055 | input [15:0] din; | |
7056 | input l1clk; | |
7057 | input scan_in; | |
7058 | ||
7059 | ||
7060 | input siclk; | |
7061 | input soclk; | |
7062 | ||
7063 | output [15:0] dout; | |
7064 | output scan_out; | |
7065 | assign fdin[15:0] = din[15:0]; | |
7066 | ||
7067 | ||
7068 | ||
7069 | ||
7070 | ||
7071 | ||
7072 | dff #(16) d0_0 ( | |
7073 | .l1clk(l1clk), | |
7074 | .siclk(siclk), | |
7075 | .soclk(soclk), | |
7076 | .d(fdin[15:0]), | |
7077 | .si({scan_in,so[14:0]}), | |
7078 | .so({so[14:0],scan_out}), | |
7079 | .q(dout[15:0]) | |
7080 | ); | |
7081 | ||
7082 | ||
7083 | ||
7084 | ||
7085 | ||
7086 | ||
7087 | ||
7088 | ||
7089 | ||
7090 | ||
7091 | ||
7092 | ||
7093 | endmodule | |
7094 | ||
7095 | ||
7096 | ||
7097 | ||
7098 | ||
7099 | ||
7100 | ||
7101 | ||
7102 | ||
7103 | ||
7104 | ||
7105 | ||
7106 | ||
7107 | // any PARAMS parms go into naming of macro | |
7108 | ||
7109 | module mcu_fbdic_ctl_msff_ctl_macro__width_1 ( | |
7110 | din, | |
7111 | l1clk, | |
7112 | scan_in, | |
7113 | siclk, | |
7114 | soclk, | |
7115 | dout, | |
7116 | scan_out); | |
7117 | wire [0:0] fdin; | |
7118 | ||
7119 | input [0:0] din; | |
7120 | input l1clk; | |
7121 | input scan_in; | |
7122 | ||
7123 | ||
7124 | input siclk; | |
7125 | input soclk; | |
7126 | ||
7127 | output [0:0] dout; | |
7128 | output scan_out; | |
7129 | assign fdin[0:0] = din[0:0]; | |
7130 | ||
7131 | ||
7132 | ||
7133 | ||
7134 | ||
7135 | ||
7136 | dff #(1) d0_0 ( | |
7137 | .l1clk(l1clk), | |
7138 | .siclk(siclk), | |
7139 | .soclk(soclk), | |
7140 | .d(fdin[0:0]), | |
7141 | .si(scan_in), | |
7142 | .so(scan_out), | |
7143 | .q(dout[0:0]) | |
7144 | ); | |
7145 | ||
7146 | ||
7147 | ||
7148 | ||
7149 | ||
7150 | ||
7151 | ||
7152 | ||
7153 | ||
7154 | ||
7155 | ||
7156 | ||
7157 | endmodule | |
7158 | ||
7159 | ||
7160 | ||
7161 | ||
7162 | ||
7163 | ||
7164 | ||
7165 | ||
7166 | ||
7167 | ||
7168 | ||
7169 | ||
7170 | ||
7171 | // any PARAMS parms go into naming of macro | |
7172 | ||
7173 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_2 ( | |
7174 | din, | |
7175 | en, | |
7176 | l1clk, | |
7177 | scan_in, | |
7178 | siclk, | |
7179 | soclk, | |
7180 | dout, | |
7181 | scan_out); | |
7182 | wire [1:0] fdin; | |
7183 | wire [0:0] so; | |
7184 | ||
7185 | input [1:0] din; | |
7186 | input en; | |
7187 | input l1clk; | |
7188 | input scan_in; | |
7189 | ||
7190 | ||
7191 | input siclk; | |
7192 | input soclk; | |
7193 | ||
7194 | output [1:0] dout; | |
7195 | output scan_out; | |
7196 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
7197 | ||
7198 | ||
7199 | ||
7200 | ||
7201 | ||
7202 | ||
7203 | dff #(2) d0_0 ( | |
7204 | .l1clk(l1clk), | |
7205 | .siclk(siclk), | |
7206 | .soclk(soclk), | |
7207 | .d(fdin[1:0]), | |
7208 | .si({scan_in,so[0:0]}), | |
7209 | .so({so[0:0],scan_out}), | |
7210 | .q(dout[1:0]) | |
7211 | ); | |
7212 | ||
7213 | ||
7214 | ||
7215 | ||
7216 | ||
7217 | ||
7218 | ||
7219 | ||
7220 | ||
7221 | ||
7222 | ||
7223 | ||
7224 | endmodule | |
7225 | ||
7226 | ||
7227 | ||
7228 | ||
7229 | ||
7230 | ||
7231 | ||
7232 | ||
7233 | ||
7234 | ||
7235 | ||
7236 | ||
7237 | ||
7238 | // any PARAMS parms go into naming of macro | |
7239 | ||
7240 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_8 ( | |
7241 | din, | |
7242 | en, | |
7243 | l1clk, | |
7244 | scan_in, | |
7245 | siclk, | |
7246 | soclk, | |
7247 | dout, | |
7248 | scan_out); | |
7249 | wire [7:0] fdin; | |
7250 | wire [6:0] so; | |
7251 | ||
7252 | input [7:0] din; | |
7253 | input en; | |
7254 | input l1clk; | |
7255 | input scan_in; | |
7256 | ||
7257 | ||
7258 | input siclk; | |
7259 | input soclk; | |
7260 | ||
7261 | output [7:0] dout; | |
7262 | output scan_out; | |
7263 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
7264 | ||
7265 | ||
7266 | ||
7267 | ||
7268 | ||
7269 | ||
7270 | dff #(8) d0_0 ( | |
7271 | .l1clk(l1clk), | |
7272 | .siclk(siclk), | |
7273 | .soclk(soclk), | |
7274 | .d(fdin[7:0]), | |
7275 | .si({scan_in,so[6:0]}), | |
7276 | .so({so[6:0],scan_out}), | |
7277 | .q(dout[7:0]) | |
7278 | ); | |
7279 | ||
7280 | ||
7281 | ||
7282 | ||
7283 | ||
7284 | ||
7285 | ||
7286 | ||
7287 | ||
7288 | ||
7289 | ||
7290 | ||
7291 | endmodule | |
7292 | ||
7293 | ||
7294 | ||
7295 | ||
7296 | ||
7297 | ||
7298 | ||
7299 | ||
7300 | ||
7301 | ||
7302 | ||
7303 | ||
7304 | ||
7305 | // any PARAMS parms go into naming of macro | |
7306 | ||
7307 | module mcu_fbdic_ctl_msff_ctl_macro__width_8 ( | |
7308 | din, | |
7309 | l1clk, | |
7310 | scan_in, | |
7311 | siclk, | |
7312 | soclk, | |
7313 | dout, | |
7314 | scan_out); | |
7315 | wire [7:0] fdin; | |
7316 | wire [6:0] so; | |
7317 | ||
7318 | input [7:0] din; | |
7319 | input l1clk; | |
7320 | input scan_in; | |
7321 | ||
7322 | ||
7323 | input siclk; | |
7324 | input soclk; | |
7325 | ||
7326 | output [7:0] dout; | |
7327 | output scan_out; | |
7328 | assign fdin[7:0] = din[7:0]; | |
7329 | ||
7330 | ||
7331 | ||
7332 | ||
7333 | ||
7334 | ||
7335 | dff #(8) d0_0 ( | |
7336 | .l1clk(l1clk), | |
7337 | .siclk(siclk), | |
7338 | .soclk(soclk), | |
7339 | .d(fdin[7:0]), | |
7340 | .si({scan_in,so[6:0]}), | |
7341 | .so({so[6:0],scan_out}), | |
7342 | .q(dout[7:0]) | |
7343 | ); | |
7344 | ||
7345 | ||
7346 | ||
7347 | ||
7348 | ||
7349 | ||
7350 | ||
7351 | ||
7352 | ||
7353 | ||
7354 | ||
7355 | ||
7356 | endmodule | |
7357 | ||
7358 | ||
7359 | ||
7360 | ||
7361 | ||
7362 | ||
7363 | ||
7364 | ||
7365 | ||
7366 | ||
7367 | ||
7368 | ||
7369 | ||
7370 | // any PARAMS parms go into naming of macro | |
7371 | ||
7372 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_7 ( | |
7373 | din, | |
7374 | en, | |
7375 | l1clk, | |
7376 | scan_in, | |
7377 | siclk, | |
7378 | soclk, | |
7379 | dout, | |
7380 | scan_out); | |
7381 | wire [6:0] fdin; | |
7382 | wire [5:0] so; | |
7383 | ||
7384 | input [6:0] din; | |
7385 | input en; | |
7386 | input l1clk; | |
7387 | input scan_in; | |
7388 | ||
7389 | ||
7390 | input siclk; | |
7391 | input soclk; | |
7392 | ||
7393 | output [6:0] dout; | |
7394 | output scan_out; | |
7395 | assign fdin[6:0] = (din[6:0] & {7{en}}) | (dout[6:0] & ~{7{en}}); | |
7396 | ||
7397 | ||
7398 | ||
7399 | ||
7400 | ||
7401 | ||
7402 | dff #(7) d0_0 ( | |
7403 | .l1clk(l1clk), | |
7404 | .siclk(siclk), | |
7405 | .soclk(soclk), | |
7406 | .d(fdin[6:0]), | |
7407 | .si({scan_in,so[5:0]}), | |
7408 | .so({so[5:0],scan_out}), | |
7409 | .q(dout[6:0]) | |
7410 | ); | |
7411 | ||
7412 | ||
7413 | ||
7414 | ||
7415 | ||
7416 | ||
7417 | ||
7418 | ||
7419 | ||
7420 | ||
7421 | ||
7422 | ||
7423 | endmodule | |
7424 | ||
7425 | ||
7426 | ||
7427 | ||
7428 | ||
7429 | ||
7430 | ||
7431 | ||
7432 | ||
7433 | ||
7434 | ||
7435 | ||
7436 | ||
7437 | // any PARAMS parms go into naming of macro | |
7438 | ||
7439 | module mcu_fbdic_ctl_msff_ctl_macro__width_2 ( | |
7440 | din, | |
7441 | l1clk, | |
7442 | scan_in, | |
7443 | siclk, | |
7444 | soclk, | |
7445 | dout, | |
7446 | scan_out); | |
7447 | wire [1:0] fdin; | |
7448 | wire [0:0] so; | |
7449 | ||
7450 | input [1:0] din; | |
7451 | input l1clk; | |
7452 | input scan_in; | |
7453 | ||
7454 | ||
7455 | input siclk; | |
7456 | input soclk; | |
7457 | ||
7458 | output [1:0] dout; | |
7459 | output scan_out; | |
7460 | assign fdin[1:0] = din[1:0]; | |
7461 | ||
7462 | ||
7463 | ||
7464 | ||
7465 | ||
7466 | ||
7467 | dff #(2) d0_0 ( | |
7468 | .l1clk(l1clk), | |
7469 | .siclk(siclk), | |
7470 | .soclk(soclk), | |
7471 | .d(fdin[1:0]), | |
7472 | .si({scan_in,so[0:0]}), | |
7473 | .so({so[0:0],scan_out}), | |
7474 | .q(dout[1:0]) | |
7475 | ); | |
7476 | ||
7477 | ||
7478 | ||
7479 | ||
7480 | ||
7481 | ||
7482 | ||
7483 | ||
7484 | ||
7485 | ||
7486 | ||
7487 | ||
7488 | endmodule | |
7489 | ||
7490 | ||
7491 | ||
7492 | ||
7493 | ||
7494 | ||
7495 | ||
7496 | ||
7497 | ||
7498 | ||
7499 | ||
7500 | ||
7501 | ||
7502 | // any PARAMS parms go into naming of macro | |
7503 | ||
7504 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_14 ( | |
7505 | din, | |
7506 | en, | |
7507 | l1clk, | |
7508 | scan_in, | |
7509 | siclk, | |
7510 | soclk, | |
7511 | dout, | |
7512 | scan_out); | |
7513 | wire [13:0] fdin; | |
7514 | wire [12:0] so; | |
7515 | ||
7516 | input [13:0] din; | |
7517 | input en; | |
7518 | input l1clk; | |
7519 | input scan_in; | |
7520 | ||
7521 | ||
7522 | input siclk; | |
7523 | input soclk; | |
7524 | ||
7525 | output [13:0] dout; | |
7526 | output scan_out; | |
7527 | assign fdin[13:0] = (din[13:0] & {14{en}}) | (dout[13:0] & ~{14{en}}); | |
7528 | ||
7529 | ||
7530 | ||
7531 | ||
7532 | ||
7533 | ||
7534 | dff #(14) d0_0 ( | |
7535 | .l1clk(l1clk), | |
7536 | .siclk(siclk), | |
7537 | .soclk(soclk), | |
7538 | .d(fdin[13:0]), | |
7539 | .si({scan_in,so[12:0]}), | |
7540 | .so({so[12:0],scan_out}), | |
7541 | .q(dout[13:0]) | |
7542 | ); | |
7543 | ||
7544 | ||
7545 | ||
7546 | ||
7547 | ||
7548 | ||
7549 | ||
7550 | ||
7551 | ||
7552 | ||
7553 | ||
7554 | ||
7555 | endmodule | |
7556 | ||
7557 | ||
7558 | ||
7559 | ||
7560 | ||
7561 | ||
7562 | ||
7563 | ||
7564 | ||
7565 | ||
7566 | ||
7567 | ||
7568 | ||
7569 | // any PARAMS parms go into naming of macro | |
7570 | ||
7571 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_32 ( | |
7572 | din, | |
7573 | en, | |
7574 | l1clk, | |
7575 | scan_in, | |
7576 | siclk, | |
7577 | soclk, | |
7578 | dout, | |
7579 | scan_out); | |
7580 | wire [31:0] fdin; | |
7581 | wire [30:0] so; | |
7582 | ||
7583 | input [31:0] din; | |
7584 | input en; | |
7585 | input l1clk; | |
7586 | input scan_in; | |
7587 | ||
7588 | ||
7589 | input siclk; | |
7590 | input soclk; | |
7591 | ||
7592 | output [31:0] dout; | |
7593 | output scan_out; | |
7594 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); | |
7595 | ||
7596 | ||
7597 | ||
7598 | ||
7599 | ||
7600 | ||
7601 | dff #(32) d0_0 ( | |
7602 | .l1clk(l1clk), | |
7603 | .siclk(siclk), | |
7604 | .soclk(soclk), | |
7605 | .d(fdin[31:0]), | |
7606 | .si({scan_in,so[30:0]}), | |
7607 | .so({so[30:0],scan_out}), | |
7608 | .q(dout[31:0]) | |
7609 | ); | |
7610 | ||
7611 | ||
7612 | ||
7613 | ||
7614 | ||
7615 | ||
7616 | ||
7617 | ||
7618 | ||
7619 | ||
7620 | ||
7621 | ||
7622 | endmodule | |
7623 | ||
7624 | ||
7625 | ||
7626 | ||
7627 | ||
7628 | ||
7629 | ||
7630 | ||
7631 | ||
7632 | ||
7633 | ||
7634 | ||
7635 | ||
7636 | // any PARAMS parms go into naming of macro | |
7637 | ||
7638 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_48 ( | |
7639 | din, | |
7640 | en, | |
7641 | l1clk, | |
7642 | scan_in, | |
7643 | siclk, | |
7644 | soclk, | |
7645 | dout, | |
7646 | scan_out); | |
7647 | wire [47:0] fdin; | |
7648 | wire [46:0] so; | |
7649 | ||
7650 | input [47:0] din; | |
7651 | input en; | |
7652 | input l1clk; | |
7653 | input scan_in; | |
7654 | ||
7655 | ||
7656 | input siclk; | |
7657 | input soclk; | |
7658 | ||
7659 | output [47:0] dout; | |
7660 | output scan_out; | |
7661 | assign fdin[47:0] = (din[47:0] & {48{en}}) | (dout[47:0] & ~{48{en}}); | |
7662 | ||
7663 | ||
7664 | ||
7665 | ||
7666 | ||
7667 | ||
7668 | dff #(48) d0_0 ( | |
7669 | .l1clk(l1clk), | |
7670 | .siclk(siclk), | |
7671 | .soclk(soclk), | |
7672 | .d(fdin[47:0]), | |
7673 | .si({scan_in,so[46:0]}), | |
7674 | .so({so[46:0],scan_out}), | |
7675 | .q(dout[47:0]) | |
7676 | ); | |
7677 | ||
7678 | ||
7679 | ||
7680 | ||
7681 | ||
7682 | ||
7683 | ||
7684 | ||
7685 | ||
7686 | ||
7687 | ||
7688 | ||
7689 | endmodule | |
7690 | ||
7691 | ||
7692 | ||
7693 | ||
7694 | ||
7695 | ||
7696 | ||
7697 | ||
7698 | ||
7699 | ||
7700 | ||
7701 | ||
7702 | ||
7703 | // any PARAMS parms go into naming of macro | |
7704 | ||
7705 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_31 ( | |
7706 | din, | |
7707 | en, | |
7708 | l1clk, | |
7709 | scan_in, | |
7710 | siclk, | |
7711 | soclk, | |
7712 | dout, | |
7713 | scan_out); | |
7714 | wire [30:0] fdin; | |
7715 | wire [29:0] so; | |
7716 | ||
7717 | input [30:0] din; | |
7718 | input en; | |
7719 | input l1clk; | |
7720 | input scan_in; | |
7721 | ||
7722 | ||
7723 | input siclk; | |
7724 | input soclk; | |
7725 | ||
7726 | output [30:0] dout; | |
7727 | output scan_out; | |
7728 | assign fdin[30:0] = (din[30:0] & {31{en}}) | (dout[30:0] & ~{31{en}}); | |
7729 | ||
7730 | ||
7731 | ||
7732 | ||
7733 | ||
7734 | ||
7735 | dff #(31) d0_0 ( | |
7736 | .l1clk(l1clk), | |
7737 | .siclk(siclk), | |
7738 | .soclk(soclk), | |
7739 | .d(fdin[30:0]), | |
7740 | .si({scan_in,so[29:0]}), | |
7741 | .so({so[29:0],scan_out}), | |
7742 | .q(dout[30:0]) | |
7743 | ); | |
7744 | ||
7745 | ||
7746 | ||
7747 | ||
7748 | ||
7749 | ||
7750 | ||
7751 | ||
7752 | ||
7753 | ||
7754 | ||
7755 | ||
7756 | endmodule | |
7757 | ||
7758 | ||
7759 | ||
7760 | ||
7761 | ||
7762 | ||
7763 | ||
7764 | ||
7765 | ||
7766 | ||
7767 | ||
7768 | ||
7769 | ||
7770 | // any PARAMS parms go into naming of macro | |
7771 | ||
7772 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_17 ( | |
7773 | din, | |
7774 | en, | |
7775 | l1clk, | |
7776 | scan_in, | |
7777 | siclk, | |
7778 | soclk, | |
7779 | dout, | |
7780 | scan_out); | |
7781 | wire [16:0] fdin; | |
7782 | wire [15:0] so; | |
7783 | ||
7784 | input [16:0] din; | |
7785 | input en; | |
7786 | input l1clk; | |
7787 | input scan_in; | |
7788 | ||
7789 | ||
7790 | input siclk; | |
7791 | input soclk; | |
7792 | ||
7793 | output [16:0] dout; | |
7794 | output scan_out; | |
7795 | assign fdin[16:0] = (din[16:0] & {17{en}}) | (dout[16:0] & ~{17{en}}); | |
7796 | ||
7797 | ||
7798 | ||
7799 | ||
7800 | ||
7801 | ||
7802 | dff #(17) d0_0 ( | |
7803 | .l1clk(l1clk), | |
7804 | .siclk(siclk), | |
7805 | .soclk(soclk), | |
7806 | .d(fdin[16:0]), | |
7807 | .si({scan_in,so[15:0]}), | |
7808 | .so({so[15:0],scan_out}), | |
7809 | .q(dout[16:0]) | |
7810 | ); | |
7811 | ||
7812 | ||
7813 | ||
7814 | ||
7815 | ||
7816 | ||
7817 | ||
7818 | ||
7819 | ||
7820 | ||
7821 | ||
7822 | ||
7823 | endmodule | |
7824 | ||
7825 | ||
7826 | ||
7827 | ||
7828 | ||
7829 | ||
7830 | ||
7831 | ||
7832 | ||
7833 | ||
7834 | ||
7835 | ||
7836 | ||
7837 | // any PARAMS parms go into naming of macro | |
7838 | ||
7839 | module mcu_fbdic_ctl_msff_ctl_macro__width_24 ( | |
7840 | din, | |
7841 | l1clk, | |
7842 | scan_in, | |
7843 | siclk, | |
7844 | soclk, | |
7845 | dout, | |
7846 | scan_out); | |
7847 | wire [23:0] fdin; | |
7848 | wire [22:0] so; | |
7849 | ||
7850 | input [23:0] din; | |
7851 | input l1clk; | |
7852 | input scan_in; | |
7853 | ||
7854 | ||
7855 | input siclk; | |
7856 | input soclk; | |
7857 | ||
7858 | output [23:0] dout; | |
7859 | output scan_out; | |
7860 | assign fdin[23:0] = din[23:0]; | |
7861 | ||
7862 | ||
7863 | ||
7864 | ||
7865 | ||
7866 | ||
7867 | dff #(24) d0_0 ( | |
7868 | .l1clk(l1clk), | |
7869 | .siclk(siclk), | |
7870 | .soclk(soclk), | |
7871 | .d(fdin[23:0]), | |
7872 | .si({scan_in,so[22:0]}), | |
7873 | .so({so[22:0],scan_out}), | |
7874 | .q(dout[23:0]) | |
7875 | ); | |
7876 | ||
7877 | ||
7878 | ||
7879 | ||
7880 | ||
7881 | ||
7882 | ||
7883 | ||
7884 | ||
7885 | ||
7886 | ||
7887 | ||
7888 | endmodule | |
7889 | ||
7890 | ||
7891 | ||
7892 | ||
7893 | ||
7894 | ||
7895 | ||
7896 | ||
7897 | ||
7898 | ||
7899 | ||
7900 | ||
7901 | ||
7902 | // any PARAMS parms go into naming of macro | |
7903 | ||
7904 | module mcu_fbdic_ctl_msff_ctl_macro__width_3 ( | |
7905 | din, | |
7906 | l1clk, | |
7907 | scan_in, | |
7908 | siclk, | |
7909 | soclk, | |
7910 | dout, | |
7911 | scan_out); | |
7912 | wire [2:0] fdin; | |
7913 | wire [1:0] so; | |
7914 | ||
7915 | input [2:0] din; | |
7916 | input l1clk; | |
7917 | input scan_in; | |
7918 | ||
7919 | ||
7920 | input siclk; | |
7921 | input soclk; | |
7922 | ||
7923 | output [2:0] dout; | |
7924 | output scan_out; | |
7925 | assign fdin[2:0] = din[2:0]; | |
7926 | ||
7927 | ||
7928 | ||
7929 | ||
7930 | ||
7931 | ||
7932 | dff #(3) d0_0 ( | |
7933 | .l1clk(l1clk), | |
7934 | .siclk(siclk), | |
7935 | .soclk(soclk), | |
7936 | .d(fdin[2:0]), | |
7937 | .si({scan_in,so[1:0]}), | |
7938 | .so({so[1:0],scan_out}), | |
7939 | .q(dout[2:0]) | |
7940 | ); | |
7941 | ||
7942 | ||
7943 | ||
7944 | ||
7945 | ||
7946 | ||
7947 | ||
7948 | ||
7949 | ||
7950 | ||
7951 | ||
7952 | ||
7953 | endmodule | |
7954 | ||
7955 | ||
7956 | ||
7957 | ||
7958 | ||
7959 | ||
7960 | ||
7961 | ||
7962 | ||
7963 | ||
7964 | ||
7965 | ||
7966 | ||
7967 | // any PARAMS parms go into naming of macro | |
7968 | ||
7969 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_6 ( | |
7970 | din, | |
7971 | en, | |
7972 | l1clk, | |
7973 | scan_in, | |
7974 | siclk, | |
7975 | soclk, | |
7976 | dout, | |
7977 | scan_out); | |
7978 | wire [5:0] fdin; | |
7979 | wire [4:0] so; | |
7980 | ||
7981 | input [5:0] din; | |
7982 | input en; | |
7983 | input l1clk; | |
7984 | input scan_in; | |
7985 | ||
7986 | ||
7987 | input siclk; | |
7988 | input soclk; | |
7989 | ||
7990 | output [5:0] dout; | |
7991 | output scan_out; | |
7992 | assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}}); | |
7993 | ||
7994 | ||
7995 | ||
7996 | ||
7997 | ||
7998 | ||
7999 | dff #(6) d0_0 ( | |
8000 | .l1clk(l1clk), | |
8001 | .siclk(siclk), | |
8002 | .soclk(soclk), | |
8003 | .d(fdin[5:0]), | |
8004 | .si({scan_in,so[4:0]}), | |
8005 | .so({so[4:0],scan_out}), | |
8006 | .q(dout[5:0]) | |
8007 | ); | |
8008 | ||
8009 | ||
8010 | ||
8011 | ||
8012 | ||
8013 | ||
8014 | ||
8015 | ||
8016 | ||
8017 | ||
8018 | ||
8019 | ||
8020 | endmodule | |
8021 | ||
8022 | ||
8023 | ||
8024 | ||
8025 | ||
8026 | ||
8027 | ||
8028 | ||
8029 | ||
8030 | ||
8031 | ||
8032 | ||
8033 | ||
8034 | // any PARAMS parms go into naming of macro | |
8035 | ||
8036 | module mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_4 ( | |
8037 | din, | |
8038 | en, | |
8039 | clr, | |
8040 | l1clk, | |
8041 | scan_in, | |
8042 | siclk, | |
8043 | soclk, | |
8044 | dout, | |
8045 | scan_out); | |
8046 | wire [3:0] fdin; | |
8047 | wire [2:0] so; | |
8048 | ||
8049 | input [3:0] din; | |
8050 | input en; | |
8051 | input clr; | |
8052 | input l1clk; | |
8053 | input scan_in; | |
8054 | ||
8055 | ||
8056 | input siclk; | |
8057 | input soclk; | |
8058 | ||
8059 | output [3:0] dout; | |
8060 | output scan_out; | |
8061 | assign fdin[3:0] = (din[3:0] & {4{en}} & ~{4{clr}}) | (dout[3:0] & ~{4{en}} & ~{4{clr}}); | |
8062 | ||
8063 | ||
8064 | ||
8065 | ||
8066 | ||
8067 | ||
8068 | dff #(4) d0_0 ( | |
8069 | .l1clk(l1clk), | |
8070 | .siclk(siclk), | |
8071 | .soclk(soclk), | |
8072 | .d(fdin[3:0]), | |
8073 | .si({scan_in,so[2:0]}), | |
8074 | .so({so[2:0],scan_out}), | |
8075 | .q(dout[3:0]) | |
8076 | ); | |
8077 | ||
8078 | ||
8079 | ||
8080 | ||
8081 | ||
8082 | ||
8083 | ||
8084 | ||
8085 | ||
8086 | ||
8087 | ||
8088 | ||
8089 | endmodule | |
8090 | ||
8091 | ||
8092 | ||
8093 | ||
8094 | ||
8095 | ||
8096 | ||
8097 | ||
8098 | ||
8099 | ||
8100 | ||
8101 | ||
8102 | ||
8103 | // any PARAMS parms go into naming of macro | |
8104 | ||
8105 | module mcu_fbdic_ctl_msff_ctl_macro__clr_1__width_4 ( | |
8106 | din, | |
8107 | clr, | |
8108 | l1clk, | |
8109 | scan_in, | |
8110 | siclk, | |
8111 | soclk, | |
8112 | dout, | |
8113 | scan_out); | |
8114 | wire [3:0] fdin; | |
8115 | wire [2:0] so; | |
8116 | ||
8117 | input [3:0] din; | |
8118 | input clr; | |
8119 | input l1clk; | |
8120 | input scan_in; | |
8121 | ||
8122 | ||
8123 | input siclk; | |
8124 | input soclk; | |
8125 | ||
8126 | output [3:0] dout; | |
8127 | output scan_out; | |
8128 | assign fdin[3:0] = din[3:0] & ~{4{clr}}; | |
8129 | ||
8130 | ||
8131 | ||
8132 | ||
8133 | ||
8134 | ||
8135 | dff #(4) d0_0 ( | |
8136 | .l1clk(l1clk), | |
8137 | .siclk(siclk), | |
8138 | .soclk(soclk), | |
8139 | .d(fdin[3:0]), | |
8140 | .si({scan_in,so[2:0]}), | |
8141 | .so({so[2:0],scan_out}), | |
8142 | .q(dout[3:0]) | |
8143 | ); | |
8144 | ||
8145 | ||
8146 | ||
8147 | ||
8148 | ||
8149 | ||
8150 | ||
8151 | ||
8152 | ||
8153 | ||
8154 | ||
8155 | ||
8156 | endmodule | |
8157 | ||
8158 | ||
8159 | ||
8160 | ||
8161 | ||
8162 | ||
8163 | ||
8164 | ||
8165 | ||
8166 | ||
8167 | ||
8168 | ||
8169 | ||
8170 | // any PARAMS parms go into naming of macro | |
8171 | ||
8172 | module mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_8 ( | |
8173 | din, | |
8174 | en, | |
8175 | clr, | |
8176 | l1clk, | |
8177 | scan_in, | |
8178 | siclk, | |
8179 | soclk, | |
8180 | dout, | |
8181 | scan_out); | |
8182 | wire [7:0] fdin; | |
8183 | wire [6:0] so; | |
8184 | ||
8185 | input [7:0] din; | |
8186 | input en; | |
8187 | input clr; | |
8188 | input l1clk; | |
8189 | input scan_in; | |
8190 | ||
8191 | ||
8192 | input siclk; | |
8193 | input soclk; | |
8194 | ||
8195 | output [7:0] dout; | |
8196 | output scan_out; | |
8197 | assign fdin[7:0] = (din[7:0] & {8{en}} & ~{8{clr}}) | (dout[7:0] & ~{8{en}} & ~{8{clr}}); | |
8198 | ||
8199 | ||
8200 | ||
8201 | ||
8202 | ||
8203 | ||
8204 | dff #(8) d0_0 ( | |
8205 | .l1clk(l1clk), | |
8206 | .siclk(siclk), | |
8207 | .soclk(soclk), | |
8208 | .d(fdin[7:0]), | |
8209 | .si({scan_in,so[6:0]}), | |
8210 | .so({so[6:0],scan_out}), | |
8211 | .q(dout[7:0]) | |
8212 | ); | |
8213 | ||
8214 | ||
8215 | ||
8216 | ||
8217 | ||
8218 | ||
8219 | ||
8220 | ||
8221 | ||
8222 | ||
8223 | ||
8224 | ||
8225 | endmodule | |
8226 | ||
8227 | ||
8228 | ||
8229 | ||
8230 | ||
8231 | ||
8232 | ||
8233 | ||
8234 | ||
8235 | ||
8236 | ||
8237 | ||
8238 | ||
8239 | // any PARAMS parms go into naming of macro | |
8240 | ||
8241 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_5 ( | |
8242 | din, | |
8243 | en, | |
8244 | l1clk, | |
8245 | scan_in, | |
8246 | siclk, | |
8247 | soclk, | |
8248 | dout, | |
8249 | scan_out); | |
8250 | wire [4:0] fdin; | |
8251 | wire [3:0] so; | |
8252 | ||
8253 | input [4:0] din; | |
8254 | input en; | |
8255 | input l1clk; | |
8256 | input scan_in; | |
8257 | ||
8258 | ||
8259 | input siclk; | |
8260 | input soclk; | |
8261 | ||
8262 | output [4:0] dout; | |
8263 | output scan_out; | |
8264 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); | |
8265 | ||
8266 | ||
8267 | ||
8268 | ||
8269 | ||
8270 | ||
8271 | dff #(5) d0_0 ( | |
8272 | .l1clk(l1clk), | |
8273 | .siclk(siclk), | |
8274 | .soclk(soclk), | |
8275 | .d(fdin[4:0]), | |
8276 | .si({scan_in,so[3:0]}), | |
8277 | .so({so[3:0],scan_out}), | |
8278 | .q(dout[4:0]) | |
8279 | ); | |
8280 | ||
8281 | ||
8282 | ||
8283 | ||
8284 | ||
8285 | ||
8286 | ||
8287 | ||
8288 | ||
8289 | ||
8290 | ||
8291 | ||
8292 | endmodule | |
8293 | ||
8294 | ||
8295 | ||
8296 | ||
8297 | ||
8298 | ||
8299 | ||
8300 | ||
8301 | ||
8302 | ||
8303 | ||
8304 | ||
8305 | ||
8306 | // any PARAMS parms go into naming of macro | |
8307 | ||
8308 | module mcu_fbdic_ctl_msff_ctl_macro__width_4 ( | |
8309 | din, | |
8310 | l1clk, | |
8311 | scan_in, | |
8312 | siclk, | |
8313 | soclk, | |
8314 | dout, | |
8315 | scan_out); | |
8316 | wire [3:0] fdin; | |
8317 | wire [2:0] so; | |
8318 | ||
8319 | input [3:0] din; | |
8320 | input l1clk; | |
8321 | input scan_in; | |
8322 | ||
8323 | ||
8324 | input siclk; | |
8325 | input soclk; | |
8326 | ||
8327 | output [3:0] dout; | |
8328 | output scan_out; | |
8329 | assign fdin[3:0] = din[3:0]; | |
8330 | ||
8331 | ||
8332 | ||
8333 | ||
8334 | ||
8335 | ||
8336 | dff #(4) d0_0 ( | |
8337 | .l1clk(l1clk), | |
8338 | .siclk(siclk), | |
8339 | .soclk(soclk), | |
8340 | .d(fdin[3:0]), | |
8341 | .si({scan_in,so[2:0]}), | |
8342 | .so({so[2:0],scan_out}), | |
8343 | .q(dout[3:0]) | |
8344 | ); | |
8345 | ||
8346 | ||
8347 | ||
8348 | ||
8349 | ||
8350 | ||
8351 | ||
8352 | ||
8353 | ||
8354 | ||
8355 | ||
8356 | ||
8357 | endmodule | |
8358 | ||
8359 | ||
8360 | ||
8361 | ||
8362 | ||
8363 | ||
8364 | ||
8365 | ||
8366 | ||
8367 | ||
8368 | ||
8369 | ||
8370 | ||
8371 | // any PARAMS parms go into naming of macro | |
8372 | ||
8373 | module mcu_fbdic_ctl_msff_ctl_macro__width_72 ( | |
8374 | din, | |
8375 | l1clk, | |
8376 | scan_in, | |
8377 | siclk, | |
8378 | soclk, | |
8379 | dout, | |
8380 | scan_out); | |
8381 | wire [71:0] fdin; | |
8382 | wire [70:0] so; | |
8383 | ||
8384 | input [71:0] din; | |
8385 | input l1clk; | |
8386 | input scan_in; | |
8387 | ||
8388 | ||
8389 | input siclk; | |
8390 | input soclk; | |
8391 | ||
8392 | output [71:0] dout; | |
8393 | output scan_out; | |
8394 | assign fdin[71:0] = din[71:0]; | |
8395 | ||
8396 | ||
8397 | ||
8398 | ||
8399 | ||
8400 | ||
8401 | dff #(72) d0_0 ( | |
8402 | .l1clk(l1clk), | |
8403 | .siclk(siclk), | |
8404 | .soclk(soclk), | |
8405 | .d(fdin[71:0]), | |
8406 | .si({scan_in,so[70:0]}), | |
8407 | .so({so[70:0],scan_out}), | |
8408 | .q(dout[71:0]) | |
8409 | ); | |
8410 | ||
8411 | ||
8412 | ||
8413 | ||
8414 | ||
8415 | ||
8416 | ||
8417 | ||
8418 | ||
8419 | ||
8420 | ||
8421 | ||
8422 | endmodule | |
8423 | ||
8424 | ||
8425 | ||
8426 | ||
8427 | ||
8428 | ||
8429 | ||
8430 | ||
8431 | ||
8432 | ||
8433 | ||
8434 | ||
8435 | ||
8436 | // any PARAMS parms go into naming of macro | |
8437 | ||
8438 | module mcu_fbdic_ctl_msff_ctl_macro__width_34 ( | |
8439 | din, | |
8440 | l1clk, | |
8441 | scan_in, | |
8442 | siclk, | |
8443 | soclk, | |
8444 | dout, | |
8445 | scan_out); | |
8446 | wire [33:0] fdin; | |
8447 | wire [32:0] so; | |
8448 | ||
8449 | input [33:0] din; | |
8450 | input l1clk; | |
8451 | input scan_in; | |
8452 | ||
8453 | ||
8454 | input siclk; | |
8455 | input soclk; | |
8456 | ||
8457 | output [33:0] dout; | |
8458 | output scan_out; | |
8459 | assign fdin[33:0] = din[33:0]; | |
8460 | ||
8461 | ||
8462 | ||
8463 | ||
8464 | ||
8465 | ||
8466 | dff #(34) d0_0 ( | |
8467 | .l1clk(l1clk), | |
8468 | .siclk(siclk), | |
8469 | .soclk(soclk), | |
8470 | .d(fdin[33:0]), | |
8471 | .si({scan_in,so[32:0]}), | |
8472 | .so({so[32:0],scan_out}), | |
8473 | .q(dout[33:0]) | |
8474 | ); | |
8475 | ||
8476 | ||
8477 | ||
8478 | ||
8479 | ||
8480 | ||
8481 | ||
8482 | ||
8483 | ||
8484 | ||
8485 | ||
8486 | ||
8487 | endmodule | |
8488 | ||
8489 | ||
8490 | ||
8491 | ||
8492 | ||
8493 | ||
8494 | // any PARAMS parms go into naming of macro | |
8495 | ||
8496 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_12 ( | |
8497 | din, | |
8498 | en, | |
8499 | l1clk, | |
8500 | scan_in, | |
8501 | siclk, | |
8502 | soclk, | |
8503 | dout, | |
8504 | scan_out); | |
8505 | wire [11:0] fdin; | |
8506 | wire [10:0] so; | |
8507 | ||
8508 | input [11:0] din; | |
8509 | input en; | |
8510 | input l1clk; | |
8511 | input scan_in; | |
8512 | ||
8513 | ||
8514 | input siclk; | |
8515 | input soclk; | |
8516 | ||
8517 | output [11:0] dout; | |
8518 | output scan_out; | |
8519 | assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}}); | |
8520 | ||
8521 | ||
8522 | ||
8523 | ||
8524 | ||
8525 | ||
8526 | dff #(12) d0_0 ( | |
8527 | .l1clk(l1clk), | |
8528 | .siclk(siclk), | |
8529 | .soclk(soclk), | |
8530 | .d(fdin[11:0]), | |
8531 | .si({scan_in,so[10:0]}), | |
8532 | .so({so[10:0],scan_out}), | |
8533 | .q(dout[11:0]) | |
8534 | ); | |
8535 | ||
8536 | ||
8537 | ||
8538 | ||
8539 | ||
8540 | ||
8541 | ||
8542 | ||
8543 | ||
8544 | ||
8545 | ||
8546 | ||
8547 | endmodule | |
8548 | ||
8549 | ||
8550 | ||
8551 | ||
8552 | ||
8553 | ||
8554 | ||
8555 | ||
8556 | ||
8557 | ||
8558 | ||
8559 | ||
8560 | ||
8561 | // any PARAMS parms go into naming of macro | |
8562 | ||
8563 | module mcu_fbdic_ctl_msff_ctl_macro__clr_1__width_5 ( | |
8564 | din, | |
8565 | clr, | |
8566 | l1clk, | |
8567 | scan_in, | |
8568 | siclk, | |
8569 | soclk, | |
8570 | dout, | |
8571 | scan_out); | |
8572 | wire [4:0] fdin; | |
8573 | wire [3:0] so; | |
8574 | ||
8575 | input [4:0] din; | |
8576 | input clr; | |
8577 | input l1clk; | |
8578 | input scan_in; | |
8579 | ||
8580 | ||
8581 | input siclk; | |
8582 | input soclk; | |
8583 | ||
8584 | output [4:0] dout; | |
8585 | output scan_out; | |
8586 | assign fdin[4:0] = din[4:0] & ~{5{clr}}; | |
8587 | ||
8588 | ||
8589 | ||
8590 | ||
8591 | ||
8592 | ||
8593 | dff #(5) d0_0 ( | |
8594 | .l1clk(l1clk), | |
8595 | .siclk(siclk), | |
8596 | .soclk(soclk), | |
8597 | .d(fdin[4:0]), | |
8598 | .si({scan_in,so[3:0]}), | |
8599 | .so({so[3:0],scan_out}), | |
8600 | .q(dout[4:0]) | |
8601 | ); | |
8602 | ||
8603 | ||
8604 | ||
8605 | ||
8606 | ||
8607 | ||
8608 | ||
8609 | ||
8610 | ||
8611 | ||
8612 | ||
8613 | ||
8614 | endmodule | |
8615 | ||
8616 | ||
8617 | ||
8618 | ||
8619 | ||
8620 | ||
8621 | ||
8622 | ||
8623 | ||
8624 | ||
8625 | ||
8626 | ||
8627 | ||
8628 | // any PARAMS parms go into naming of macro | |
8629 | ||
8630 | module mcu_fbdic_ctl_msff_ctl_macro__clr_1__en_1__width_24 ( | |
8631 | din, | |
8632 | en, | |
8633 | clr, | |
8634 | l1clk, | |
8635 | scan_in, | |
8636 | siclk, | |
8637 | soclk, | |
8638 | dout, | |
8639 | scan_out); | |
8640 | wire [23:0] fdin; | |
8641 | wire [22:0] so; | |
8642 | ||
8643 | input [23:0] din; | |
8644 | input en; | |
8645 | input clr; | |
8646 | input l1clk; | |
8647 | input scan_in; | |
8648 | ||
8649 | ||
8650 | input siclk; | |
8651 | input soclk; | |
8652 | ||
8653 | output [23:0] dout; | |
8654 | output scan_out; | |
8655 | assign fdin[23:0] = (din[23:0] & {24{en}} & ~{24{clr}}) | (dout[23:0] & ~{24{en}} & ~{24{clr}}); | |
8656 | ||
8657 | ||
8658 | ||
8659 | ||
8660 | ||
8661 | ||
8662 | dff #(24) d0_0 ( | |
8663 | .l1clk(l1clk), | |
8664 | .siclk(siclk), | |
8665 | .soclk(soclk), | |
8666 | .d(fdin[23:0]), | |
8667 | .si({scan_in,so[22:0]}), | |
8668 | .so({so[22:0],scan_out}), | |
8669 | .q(dout[23:0]) | |
8670 | ); | |
8671 | ||
8672 | ||
8673 | ||
8674 | ||
8675 | ||
8676 | ||
8677 | ||
8678 | ||
8679 | ||
8680 | ||
8681 | ||
8682 | ||
8683 | endmodule | |
8684 | ||
8685 | ||
8686 | ||
8687 | ||
8688 | ||
8689 | ||
8690 | ||
8691 | ||
8692 | ||
8693 | ||
8694 | ||
8695 | ||
8696 | ||
8697 | // any PARAMS parms go into naming of macro | |
8698 | ||
8699 | module mcu_fbdic_ctl_msff_ctl_macro__width_5 ( | |
8700 | din, | |
8701 | l1clk, | |
8702 | scan_in, | |
8703 | siclk, | |
8704 | soclk, | |
8705 | dout, | |
8706 | scan_out); | |
8707 | wire [4:0] fdin; | |
8708 | wire [3:0] so; | |
8709 | ||
8710 | input [4:0] din; | |
8711 | input l1clk; | |
8712 | input scan_in; | |
8713 | ||
8714 | ||
8715 | input siclk; | |
8716 | input soclk; | |
8717 | ||
8718 | output [4:0] dout; | |
8719 | output scan_out; | |
8720 | assign fdin[4:0] = din[4:0]; | |
8721 | ||
8722 | ||
8723 | ||
8724 | ||
8725 | ||
8726 | ||
8727 | dff #(5) d0_0 ( | |
8728 | .l1clk(l1clk), | |
8729 | .siclk(siclk), | |
8730 | .soclk(soclk), | |
8731 | .d(fdin[4:0]), | |
8732 | .si({scan_in,so[3:0]}), | |
8733 | .so({so[3:0],scan_out}), | |
8734 | .q(dout[4:0]) | |
8735 | ); | |
8736 | ||
8737 | ||
8738 | ||
8739 | ||
8740 | ||
8741 | ||
8742 | ||
8743 | ||
8744 | ||
8745 | ||
8746 | ||
8747 | ||
8748 | endmodule | |
8749 | ||
8750 | ||
8751 | ||
8752 | ||
8753 | ||
8754 | ||
8755 | ||
8756 | ||
8757 | ||
8758 | ||
8759 | ||
8760 | ||
8761 | ||
8762 | // any PARAMS parms go into naming of macro | |
8763 | ||
8764 | module mcu_fbdic_ctl_msff_ctl_macro__width_7 ( | |
8765 | din, | |
8766 | l1clk, | |
8767 | scan_in, | |
8768 | siclk, | |
8769 | soclk, | |
8770 | dout, | |
8771 | scan_out); | |
8772 | wire [6:0] fdin; | |
8773 | wire [5:0] so; | |
8774 | ||
8775 | input [6:0] din; | |
8776 | input l1clk; | |
8777 | input scan_in; | |
8778 | ||
8779 | ||
8780 | input siclk; | |
8781 | input soclk; | |
8782 | ||
8783 | output [6:0] dout; | |
8784 | output scan_out; | |
8785 | assign fdin[6:0] = din[6:0]; | |
8786 | ||
8787 | ||
8788 | ||
8789 | ||
8790 | ||
8791 | ||
8792 | dff #(7) d0_0 ( | |
8793 | .l1clk(l1clk), | |
8794 | .siclk(siclk), | |
8795 | .soclk(soclk), | |
8796 | .d(fdin[6:0]), | |
8797 | .si({scan_in,so[5:0]}), | |
8798 | .so({so[5:0],scan_out}), | |
8799 | .q(dout[6:0]) | |
8800 | ); | |
8801 | ||
8802 | ||
8803 | ||
8804 | ||
8805 | ||
8806 | ||
8807 | ||
8808 | ||
8809 | ||
8810 | ||
8811 | ||
8812 | ||
8813 | endmodule | |
8814 | ||
8815 | ||
8816 | ||
8817 | ||
8818 | ||
8819 | ||
8820 | ||
8821 | ||
8822 | ||
8823 | ||
8824 | ||
8825 | ||
8826 | ||
8827 | // any PARAMS parms go into naming of macro | |
8828 | ||
8829 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_30 ( | |
8830 | din, | |
8831 | en, | |
8832 | l1clk, | |
8833 | scan_in, | |
8834 | siclk, | |
8835 | soclk, | |
8836 | dout, | |
8837 | scan_out); | |
8838 | wire [29:0] fdin; | |
8839 | wire [28:0] so; | |
8840 | ||
8841 | input [29:0] din; | |
8842 | input en; | |
8843 | input l1clk; | |
8844 | input scan_in; | |
8845 | ||
8846 | ||
8847 | input siclk; | |
8848 | input soclk; | |
8849 | ||
8850 | output [29:0] dout; | |
8851 | output scan_out; | |
8852 | assign fdin[29:0] = (din[29:0] & {30{en}}) | (dout[29:0] & ~{30{en}}); | |
8853 | ||
8854 | ||
8855 | ||
8856 | ||
8857 | ||
8858 | ||
8859 | dff #(30) d0_0 ( | |
8860 | .l1clk(l1clk), | |
8861 | .siclk(siclk), | |
8862 | .soclk(soclk), | |
8863 | .d(fdin[29:0]), | |
8864 | .si({scan_in,so[28:0]}), | |
8865 | .so({so[28:0],scan_out}), | |
8866 | .q(dout[29:0]) | |
8867 | ); | |
8868 | ||
8869 | endmodule | |
8870 | ||
8871 | ||
8872 | ||
8873 | // any PARAMS parms go into naming of macro | |
8874 | ||
8875 | module mcu_fbdic_ctl_msff_ctl_macro__width_6 ( | |
8876 | din, | |
8877 | l1clk, | |
8878 | scan_in, | |
8879 | siclk, | |
8880 | soclk, | |
8881 | dout, | |
8882 | scan_out); | |
8883 | wire [5:0] fdin; | |
8884 | wire [4:0] so; | |
8885 | ||
8886 | input [5:0] din; | |
8887 | input l1clk; | |
8888 | input scan_in; | |
8889 | ||
8890 | ||
8891 | input siclk; | |
8892 | input soclk; | |
8893 | ||
8894 | output [5:0] dout; | |
8895 | output scan_out; | |
8896 | assign fdin[5:0] = din[5:0]; | |
8897 | ||
8898 | ||
8899 | ||
8900 | ||
8901 | ||
8902 | ||
8903 | dff #(6) d0_0 ( | |
8904 | .l1clk(l1clk), | |
8905 | .siclk(siclk), | |
8906 | .soclk(soclk), | |
8907 | .d(fdin[5:0]), | |
8908 | .si({scan_in,so[4:0]}), | |
8909 | .so({so[4:0],scan_out}), | |
8910 | .q(dout[5:0]) | |
8911 | ); | |
8912 | ||
8913 | ||
8914 | endmodule | |
8915 | ||
8916 | ||
8917 | ||
8918 | ||
8919 | ||
8920 | ||
8921 | // any PARAMS parms go into naming of macro | |
8922 | ||
8923 | module mcu_fbdic_ctl_msff_ctl_macro__width_14 ( | |
8924 | din, | |
8925 | l1clk, | |
8926 | scan_in, | |
8927 | siclk, | |
8928 | soclk, | |
8929 | dout, | |
8930 | scan_out); | |
8931 | wire [13:0] fdin; | |
8932 | wire [12:0] so; | |
8933 | ||
8934 | input [13:0] din; | |
8935 | input l1clk; | |
8936 | input scan_in; | |
8937 | ||
8938 | ||
8939 | input siclk; | |
8940 | input soclk; | |
8941 | ||
8942 | output [13:0] dout; | |
8943 | output scan_out; | |
8944 | assign fdin[13:0] = din[13:0]; | |
8945 | ||
8946 | ||
8947 | ||
8948 | ||
8949 | ||
8950 | ||
8951 | dff #(14) d0_0 ( | |
8952 | .l1clk(l1clk), | |
8953 | .siclk(siclk), | |
8954 | .soclk(soclk), | |
8955 | .d(fdin[13:0]), | |
8956 | .si({scan_in,so[12:0]}), | |
8957 | .so({so[12:0],scan_out}), | |
8958 | .q(dout[13:0]) | |
8959 | ); | |
8960 | ||
8961 | ||
8962 | ||
8963 | ||
8964 | ||
8965 | ||
8966 | ||
8967 | ||
8968 | ||
8969 | ||
8970 | ||
8971 | ||
8972 | endmodule | |
8973 | ||
8974 | ||
8975 | ||
8976 | ||
8977 | ||
8978 | // any PARAMS parms go into naming of macro | |
8979 | ||
8980 | module mcu_fbdic_ctl_msff_ctl_macro__en_1__width_27 ( | |
8981 | din, | |
8982 | en, | |
8983 | l1clk, | |
8984 | scan_in, | |
8985 | siclk, | |
8986 | soclk, | |
8987 | dout, | |
8988 | scan_out); | |
8989 | wire [26:0] fdin; | |
8990 | wire [25:0] so; | |
8991 | ||
8992 | input [26:0] din; | |
8993 | input en; | |
8994 | input l1clk; | |
8995 | input scan_in; | |
8996 | ||
8997 | ||
8998 | input siclk; | |
8999 | input soclk; | |
9000 | ||
9001 | output [26:0] dout; | |
9002 | output scan_out; | |
9003 | assign fdin[26:0] = (din[26:0] & {27{en}}) | (dout[26:0] & ~{27{en}}); | |
9004 | ||
9005 | ||
9006 | ||
9007 | ||
9008 | ||
9009 | ||
9010 | dff #(27) d0_0 ( | |
9011 | .l1clk(l1clk), | |
9012 | .siclk(siclk), | |
9013 | .soclk(soclk), | |
9014 | .d(fdin[26:0]), | |
9015 | .si({scan_in,so[25:0]}), | |
9016 | .so({so[25:0],scan_out}), | |
9017 | .q(dout[26:0]) | |
9018 | ); | |
9019 | ||
9020 | ||
9021 | ||
9022 | ||
9023 | ||
9024 | ||
9025 | ||
9026 | ||
9027 | ||
9028 | ||
9029 | ||
9030 | ||
9031 | endmodule | |
9032 | ||
9033 | ||
9034 | ||
9035 | ||
9036 | ||
9037 | ||
9038 | ||
9039 |