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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_fbdiwr_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_fbdiwr_dp ( | |
36 | fbdiwr0_data, | |
37 | fbdiwr1_data, | |
38 | fbdiwr_dtm_crc, | |
39 | bc, | |
40 | bd0, | |
41 | bd1, | |
42 | fbdic0_ts_data, | |
43 | fbdic1_ts_data, | |
44 | fbdic_ibist_data, | |
45 | fbdic_f, | |
46 | fbdic_f_1_l, | |
47 | fbdic0_chnl_disable, | |
48 | fbdic1_chnl_disable, | |
49 | fbdic_a_cmd, | |
50 | fbdic_bc_cmd, | |
51 | fbdic0_cmd_crc_sel, | |
52 | fbdic1_cmd_crc_sel, | |
53 | fbdic0_data_crc_sel, | |
54 | fbdic1_data_crc_sel, | |
55 | fbdic_special_cmd, | |
56 | fbdic_special_cmd_l, | |
57 | fbdic0_failover_mask, | |
58 | fbdic0_failover_mask_l, | |
59 | fbdic1_failover_mask, | |
60 | fbdic1_failover_mask_l, | |
61 | wrdp_data, | |
62 | fbd0_data, | |
63 | fbd1_data, | |
64 | fbdic_data_sel, | |
65 | rdpctl_dtm_chnl_enable, | |
66 | crcsc_crc, | |
67 | crcscf_crc, | |
68 | crcsd0_crc, | |
69 | crcsdf0_crc, | |
70 | crcsd1_crc, | |
71 | crcsdf1_crc, | |
72 | drl2clk, | |
73 | scan_in, | |
74 | scan_out, | |
75 | tcu_pce_ov, | |
76 | tcu_aclk, | |
77 | tcu_bclk, | |
78 | tcu_dectest, | |
79 | tcu_muxtest, | |
80 | tcu_scan_en); | |
81 | wire pce_ov; | |
82 | wire stop; | |
83 | wire siclk; | |
84 | wire soclk; | |
85 | wire test; | |
86 | wire muxtst; | |
87 | wire se; | |
88 | wire [13:0] fbdiwr0_sbcmd_crc; | |
89 | wire [13:0] fbdiwr1_sbcmd_crc; | |
90 | wire u_ff_sbdata_crc_d1_scanin; | |
91 | wire u_ff_sbdata_crc_d1_scanout; | |
92 | wire [21:0] sbdata0_crc; | |
93 | wire [21:0] sbdata1_crc; | |
94 | wire [13:0] sbdata0_crc_d1; | |
95 | wire [13:0] sbdata1_crc_d1; | |
96 | wire [13:0] sbcmd0_crc; | |
97 | wire [13:0] sbcmd1_crc; | |
98 | wire [71:0] fbdiwr_bc_cmd_data0; | |
99 | wire [119:0] mcu_fsr0_data_in; | |
100 | wire [71:0] fbdiwr_bc_cmd_data1; | |
101 | wire [119:0] mcu_fsr1_data_in; | |
102 | wire [119:0] mux_fsr0_data; | |
103 | wire [119:0] mux_fsr1_data; | |
104 | wire [21:0] ch0_crc; | |
105 | wire [21:0] ch1_crc; | |
106 | ||
107 | ||
108 | output [119:0] fbdiwr0_data; | |
109 | output [119:0] fbdiwr1_data; | |
110 | ||
111 | output [21:0] fbdiwr_dtm_crc; | |
112 | ||
113 | output [25:0] bc; | |
114 | output [71:0] bd0; | |
115 | output [71:0] bd1; | |
116 | ||
117 | input [11:0] fbdic0_ts_data; | |
118 | input [11:0] fbdic1_ts_data; | |
119 | input [119:0] fbdic_ibist_data; | |
120 | input [1:0] fbdic_f; | |
121 | input fbdic_f_1_l; | |
122 | input fbdic0_chnl_disable; | |
123 | input fbdic1_chnl_disable; | |
124 | input [23:0] fbdic_a_cmd; | |
125 | input [71:0] fbdic_bc_cmd; | |
126 | ||
127 | input [1:0] fbdic0_cmd_crc_sel; | |
128 | input [1:0] fbdic1_cmd_crc_sel; | |
129 | input [2:0] fbdic0_data_crc_sel; | |
130 | input [2:0] fbdic1_data_crc_sel; | |
131 | input fbdic_special_cmd; | |
132 | input fbdic_special_cmd_l; | |
133 | ||
134 | input [8:0] fbdic0_failover_mask; | |
135 | input [8:0] fbdic0_failover_mask_l; | |
136 | input [8:0] fbdic1_failover_mask; | |
137 | input [8:0] fbdic1_failover_mask_l; | |
138 | ||
139 | input [143:0] wrdp_data; | |
140 | input [167:0] fbd0_data; | |
141 | input [167:0] fbd1_data; | |
142 | input [4:0] fbdic_data_sel; | |
143 | ||
144 | input [1:0] rdpctl_dtm_chnl_enable; | |
145 | ||
146 | input [13:0] crcsc_crc; | |
147 | input [9:0] crcscf_crc; | |
148 | ||
149 | input [21:0] crcsd0_crc; | |
150 | input [9:0] crcsdf0_crc; | |
151 | ||
152 | input [21:0] crcsd1_crc; | |
153 | input [9:0] crcsdf1_crc; | |
154 | ||
155 | input drl2clk; | |
156 | input scan_in; | |
157 | output scan_out; | |
158 | input tcu_pce_ov; | |
159 | input tcu_aclk; | |
160 | input tcu_bclk; | |
161 | input tcu_dectest; | |
162 | input tcu_muxtest; | |
163 | input tcu_scan_en; | |
164 | ||
165 | assign pce_ov = tcu_pce_ov; | |
166 | assign stop = 1'b0; | |
167 | assign siclk = tcu_aclk; | |
168 | assign soclk = tcu_bclk; | |
169 | assign test = tcu_dectest; | |
170 | assign muxtst = tcu_muxtest; | |
171 | assign se = tcu_scan_en; | |
172 | ||
173 | // Branch command | |
174 | ||
175 | assign bc[25:0] = { | |
176 | fbdic_f[1:0], | |
177 | fbdic_a_cmd[20], fbdic_a_cmd[21], fbdic_a_cmd[22], fbdic_a_cmd[23], fbdic_a_cmd[19:16], | |
178 | fbdic_a_cmd[12], fbdic_a_cmd[13], fbdic_a_cmd[14], fbdic_a_cmd[15], fbdic_a_cmd[11:8], | |
179 | fbdic_a_cmd[4], fbdic_a_cmd[5], fbdic_a_cmd[6], fbdic_a_cmd[7], fbdic_a_cmd[3:0]}; | |
180 | ||
181 | ////csret 11/19/2004 | |
182 | //assign sbcmd_crc[13:0] = fbdic_special_cmd ? 14'h0 : fbdic_failover ? {4'h0,crcscf_crc[9:0]} : crcsc_crc[13:0]; | |
183 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_2__width_14 u_mux_sbcmd0_crc ( | |
184 | .dout ( fbdiwr0_sbcmd_crc[13:0] ), | |
185 | .din0 ( {crcscf_crc[9:0],4'h0} ), | |
186 | .din1 ( crcsc_crc[13:0] ), | |
187 | .sel0 ( fbdic0_cmd_crc_sel[0] ), | |
188 | .sel1 ( fbdic0_cmd_crc_sel[1] )); | |
189 | ||
190 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_2__width_14 u_mux_sbcmd1_crc ( | |
191 | .dout ( fbdiwr1_sbcmd_crc[13:0] ), | |
192 | .din0 ( {crcscf_crc[9:0],4'h0} ), | |
193 | .din1 ( crcsc_crc[13:0] ), | |
194 | .sel0 ( fbdic1_cmd_crc_sel[0] ), | |
195 | .sel1 ( fbdic1_cmd_crc_sel[1] )); | |
196 | ||
197 | mcu_fbdiwr_dp_msff_macro__mux_aonpe__ports_2__width_28 u_ff_sbdata_crc_d1 ( | |
198 | .scan_in(u_ff_sbdata_crc_d1_scanin), | |
199 | .scan_out(u_ff_sbdata_crc_d1_scanout), | |
200 | .din0(28'h0), | |
201 | .din1({sbdata0_crc[13:0],sbdata1_crc[13:0]}), | |
202 | .dout({sbdata0_crc_d1[13:0],sbdata1_crc_d1[13:0]}), | |
203 | .sel0(fbdic_special_cmd), | |
204 | .sel1(fbdic_special_cmd_l), | |
205 | .en(1'b1), | |
206 | .clk(drl2clk), | |
207 | .se(se), | |
208 | .siclk(siclk), | |
209 | .soclk(soclk), | |
210 | .pce_ov(pce_ov), | |
211 | .stop(stop)); | |
212 | ||
213 | mcu_fbdiwr_dp_xor_macro__width_14 u_xor_cmd_data0_crc ( | |
214 | .din0(fbdiwr0_sbcmd_crc[13:0]), | |
215 | .din1(sbdata0_crc_d1[13:0]), | |
216 | .dout(sbcmd0_crc[13:0])); | |
217 | ||
218 | mcu_fbdiwr_dp_xor_macro__width_14 u_xor_cmd_data1_crc ( | |
219 | .din0(fbdiwr1_sbcmd_crc[13:0]), | |
220 | .din1(sbdata1_crc_d1[13:0]), | |
221 | .dout(sbcmd1_crc[13:0])); | |
222 | ||
223 | // Channel 0 Data | |
224 | ||
225 | ////csret 11/19/2004 | |
226 | //assign fbdiwr_bc_cmd_data0[71:0] = fbdic_f[1] ? wrdp_data[143:72] : fbdic_bc_cmd[71:0]; | |
227 | mcu_fbdiwr_dp_mux_macro__mux_pgpe__ports_3__width_36 u_mux_fbdiwr_bc_cmd_data0_35_0 ( | |
228 | .dout ( fbdiwr_bc_cmd_data0[35:0] ), | |
229 | .din0 ( 36'h0 ), | |
230 | .din1 ( fbdic_bc_cmd[35:0] ), | |
231 | .din2 ( wrdp_data[107:72] ), | |
232 | .sel0 ( fbdic0_chnl_disable ), | |
233 | .sel1 ( fbdic_f_1_l ), | |
234 | .muxtst(muxtst), | |
235 | .test(test) ); | |
236 | mcu_fbdiwr_dp_mux_macro__mux_pgpe__ports_3__width_36 u_mux_fbdiwr_bc_cmd_data0_71_36 ( | |
237 | .dout ( fbdiwr_bc_cmd_data0[71:36] ), | |
238 | .din0 ( 36'h0 ), | |
239 | .din1 ( fbdic_bc_cmd[71:36] ), | |
240 | .din2 ( wrdp_data[143:108] ), | |
241 | .sel0 ( fbdic0_chnl_disable ), | |
242 | .sel1 ( fbdic_f_1_l ), | |
243 | .muxtst(muxtst), | |
244 | .test(test) ); | |
245 | ||
246 | assign bd0[71:0] = { | |
247 | fbdiwr_bc_cmd_data0[7], fbdiwr_bc_cmd_data0[15], fbdiwr_bc_cmd_data0[23], fbdiwr_bc_cmd_data0[31], fbdiwr_bc_cmd_data0[39], | |
248 | fbdiwr_bc_cmd_data0[47], fbdiwr_bc_cmd_data0[55], fbdiwr_bc_cmd_data0[63], fbdiwr_bc_cmd_data0[71], | |
249 | fbdiwr_bc_cmd_data0[70], fbdiwr_bc_cmd_data0[62], fbdiwr_bc_cmd_data0[54], fbdiwr_bc_cmd_data0[46], fbdiwr_bc_cmd_data0[38], | |
250 | fbdiwr_bc_cmd_data0[30], fbdiwr_bc_cmd_data0[22], fbdiwr_bc_cmd_data0[14], fbdiwr_bc_cmd_data0[6], | |
251 | fbdiwr_bc_cmd_data0[5], fbdiwr_bc_cmd_data0[13], fbdiwr_bc_cmd_data0[21], fbdiwr_bc_cmd_data0[29], fbdiwr_bc_cmd_data0[37], | |
252 | fbdiwr_bc_cmd_data0[45], fbdiwr_bc_cmd_data0[53], fbdiwr_bc_cmd_data0[61], fbdiwr_bc_cmd_data0[69], | |
253 | fbdiwr_bc_cmd_data0[68], fbdiwr_bc_cmd_data0[60], fbdiwr_bc_cmd_data0[52], fbdiwr_bc_cmd_data0[44], fbdiwr_bc_cmd_data0[36], | |
254 | fbdiwr_bc_cmd_data0[28], fbdiwr_bc_cmd_data0[20], fbdiwr_bc_cmd_data0[12], fbdiwr_bc_cmd_data0[4], | |
255 | fbdiwr_bc_cmd_data0[3], fbdiwr_bc_cmd_data0[11], fbdiwr_bc_cmd_data0[19], fbdiwr_bc_cmd_data0[27], fbdiwr_bc_cmd_data0[35], | |
256 | fbdiwr_bc_cmd_data0[43], fbdiwr_bc_cmd_data0[51], fbdiwr_bc_cmd_data0[59], fbdiwr_bc_cmd_data0[67], | |
257 | fbdiwr_bc_cmd_data0[66], fbdiwr_bc_cmd_data0[58], fbdiwr_bc_cmd_data0[50], fbdiwr_bc_cmd_data0[42], fbdiwr_bc_cmd_data0[34], | |
258 | fbdiwr_bc_cmd_data0[26], fbdiwr_bc_cmd_data0[18], fbdiwr_bc_cmd_data0[10], fbdiwr_bc_cmd_data0[2], | |
259 | fbdiwr_bc_cmd_data0[1], fbdiwr_bc_cmd_data0[9], fbdiwr_bc_cmd_data0[17], fbdiwr_bc_cmd_data0[25], fbdiwr_bc_cmd_data0[33], | |
260 | fbdiwr_bc_cmd_data0[41], fbdiwr_bc_cmd_data0[49], fbdiwr_bc_cmd_data0[57], fbdiwr_bc_cmd_data0[65], | |
261 | fbdiwr_bc_cmd_data0[64], fbdiwr_bc_cmd_data0[56], fbdiwr_bc_cmd_data0[48], fbdiwr_bc_cmd_data0[40], fbdiwr_bc_cmd_data0[32], | |
262 | fbdiwr_bc_cmd_data0[24], fbdiwr_bc_cmd_data0[16], fbdiwr_bc_cmd_data0[8], fbdiwr_bc_cmd_data0[0]}; | |
263 | ||
264 | ////csret 11/19/2004 | |
265 | //assign sbdata0_crc[21:0] = fbdic_special_cmd ? 22'h2aaaaa : fbdic_failover ? {12'h0,crcsdf0_crc[9:0]} : crcsd0_crc[21:0]; | |
266 | ||
267 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_3__width_22 u_sbdata0_crc ( | |
268 | .din0(22'h2aaaaa), | |
269 | .din1({8'h0,crcsdf0_crc[9:0],4'h0}), | |
270 | .din2(crcsd0_crc[21:0]), | |
271 | .sel0(fbdic0_data_crc_sel[0]), | |
272 | .sel1(fbdic0_data_crc_sel[1]), | |
273 | .sel2(fbdic0_data_crc_sel[2]), | |
274 | .dout(sbdata0_crc[21:0])); | |
275 | ||
276 | assign mcu_fsr0_data_in[119:0] = | |
277 | {{sbdata0_crc[14],sbdata0_crc[15],sbdata0_crc[16],sbdata0_crc[17], | |
278 | sbdata0_crc[18],sbdata0_crc[19],sbdata0_crc[20],sbdata0_crc[21],sbcmd0_crc[3:0]}, | |
279 | {fbdiwr_bc_cmd_data0[71:64],sbcmd0_crc[4],sbcmd0_crc[5],sbcmd0_crc[6],sbcmd0_crc[7]}, | |
280 | {fbdiwr_bc_cmd_data0[63:56],sbcmd0_crc[11:8]}, | |
281 | {fbdiwr_bc_cmd_data0[55:48],sbcmd0_crc[12],sbcmd0_crc[13],fbdic_f[1:0]}, | |
282 | {fbdiwr_bc_cmd_data0[47:40],fbdic_a_cmd[23:20]}, | |
283 | {fbdiwr_bc_cmd_data0[39:32],fbdic_a_cmd[19:16]}, | |
284 | {fbdiwr_bc_cmd_data0[31:24],fbdic_a_cmd[15:12]}, | |
285 | {fbdiwr_bc_cmd_data0[23:16],fbdic_a_cmd[11:8]}, | |
286 | {fbdiwr_bc_cmd_data0[15:8],fbdic_a_cmd[7:4]}, | |
287 | {fbdiwr_bc_cmd_data0[7:0],fbdic_a_cmd[3:0]}}; | |
288 | ||
289 | //msff_macro fsr_data0 (width=120) ( | |
290 | // .scan_in(fbd_data0_scanin), | |
291 | // .scan_out(fbd_data0_scanout), | |
292 | // .din(mcu_fsr0_data_in[119:0]), | |
293 | // .dout(mcu_fsr0_data[119:0]), | |
294 | // .l1clk(l1clk)); | |
295 | ||
296 | // Channel 1 Data | |
297 | ||
298 | ////csret 11/19/2004 | |
299 | //assign fbdiwr_bc_cmd_data1[71:0] = fbdic_f[1] ? wrdp_data[71:0] : fbdic_bc_cmd[71:0]; | |
300 | mcu_fbdiwr_dp_mux_macro__mux_pgpe__ports_3__width_36 u_mux_fbdicwr_bc_cmd_data1_71_36 ( | |
301 | .dout( fbdiwr_bc_cmd_data1[71:36] ), | |
302 | .din0 ( 36'h0 ), | |
303 | .din1 ( fbdic_bc_cmd[71:36] ), | |
304 | .din2 ( wrdp_data[71:36] ), | |
305 | .sel0 ( fbdic1_chnl_disable ), | |
306 | .sel1 ( fbdic_f_1_l ), | |
307 | .muxtst(muxtst), | |
308 | .test(test) ); | |
309 | mcu_fbdiwr_dp_mux_macro__mux_pgpe__ports_3__width_36 u_mux_fbdicwr_bc_cmd_data1_35_0 ( | |
310 | .dout( fbdiwr_bc_cmd_data1[35:0] ), | |
311 | .din0 ( 36'h0 ), | |
312 | .din1 ( fbdic_bc_cmd[35:0] ), | |
313 | .din2 ( wrdp_data[35:0] ), | |
314 | .sel0 ( fbdic1_chnl_disable ), | |
315 | .sel1 ( fbdic_f_1_l ), | |
316 | .muxtst(muxtst), | |
317 | .test(test) ); | |
318 | ||
319 | assign bd1[71:0] = { | |
320 | fbdiwr_bc_cmd_data1[7], fbdiwr_bc_cmd_data1[15], fbdiwr_bc_cmd_data1[23], fbdiwr_bc_cmd_data1[31], fbdiwr_bc_cmd_data1[39], | |
321 | fbdiwr_bc_cmd_data1[47], fbdiwr_bc_cmd_data1[55], fbdiwr_bc_cmd_data1[63], fbdiwr_bc_cmd_data1[71], | |
322 | fbdiwr_bc_cmd_data1[70], fbdiwr_bc_cmd_data1[62], fbdiwr_bc_cmd_data1[54], fbdiwr_bc_cmd_data1[46], fbdiwr_bc_cmd_data1[38], | |
323 | fbdiwr_bc_cmd_data1[30], fbdiwr_bc_cmd_data1[22], fbdiwr_bc_cmd_data1[14], fbdiwr_bc_cmd_data1[6], | |
324 | fbdiwr_bc_cmd_data1[5], fbdiwr_bc_cmd_data1[13], fbdiwr_bc_cmd_data1[21], fbdiwr_bc_cmd_data1[29], fbdiwr_bc_cmd_data1[37], | |
325 | fbdiwr_bc_cmd_data1[45], fbdiwr_bc_cmd_data1[53], fbdiwr_bc_cmd_data1[61], fbdiwr_bc_cmd_data1[69], | |
326 | fbdiwr_bc_cmd_data1[68], fbdiwr_bc_cmd_data1[60], fbdiwr_bc_cmd_data1[52], fbdiwr_bc_cmd_data1[44], fbdiwr_bc_cmd_data1[36], | |
327 | fbdiwr_bc_cmd_data1[28], fbdiwr_bc_cmd_data1[20], fbdiwr_bc_cmd_data1[12], fbdiwr_bc_cmd_data1[4], | |
328 | fbdiwr_bc_cmd_data1[3], fbdiwr_bc_cmd_data1[11], fbdiwr_bc_cmd_data1[19], fbdiwr_bc_cmd_data1[27], fbdiwr_bc_cmd_data1[35], | |
329 | fbdiwr_bc_cmd_data1[43], fbdiwr_bc_cmd_data1[51], fbdiwr_bc_cmd_data1[59], fbdiwr_bc_cmd_data1[67], | |
330 | fbdiwr_bc_cmd_data1[66], fbdiwr_bc_cmd_data1[58], fbdiwr_bc_cmd_data1[50], fbdiwr_bc_cmd_data1[42], fbdiwr_bc_cmd_data1[34], | |
331 | fbdiwr_bc_cmd_data1[26], fbdiwr_bc_cmd_data1[18], fbdiwr_bc_cmd_data1[10], fbdiwr_bc_cmd_data1[2], | |
332 | fbdiwr_bc_cmd_data1[1], fbdiwr_bc_cmd_data1[9], fbdiwr_bc_cmd_data1[17], fbdiwr_bc_cmd_data1[25], fbdiwr_bc_cmd_data1[33], | |
333 | fbdiwr_bc_cmd_data1[41], fbdiwr_bc_cmd_data1[49], fbdiwr_bc_cmd_data1[57], fbdiwr_bc_cmd_data1[65], | |
334 | fbdiwr_bc_cmd_data1[64], fbdiwr_bc_cmd_data1[56], fbdiwr_bc_cmd_data1[48], fbdiwr_bc_cmd_data1[40], fbdiwr_bc_cmd_data1[32], | |
335 | fbdiwr_bc_cmd_data1[24], fbdiwr_bc_cmd_data1[16], fbdiwr_bc_cmd_data1[8], fbdiwr_bc_cmd_data1[0]}; | |
336 | ||
337 | ////csret 11/19/2004 | |
338 | //assign sbdata1_crc[21:0] = fbdic_special_cmd ? 22'h2aaaaa : fbdic_failover ? {12'h0,crcsdf1_crc[9:0]} : crcsd1_crc[21:0]; | |
339 | ||
340 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_3__width_22 u_sbdata1_crc ( | |
341 | .din0(22'h2aaaaa), | |
342 | .din1({8'h0,crcsdf1_crc[9:0],4'h0}), | |
343 | .din2(crcsd1_crc[21:0]), | |
344 | .sel0(fbdic1_data_crc_sel[0]), | |
345 | .sel1(fbdic1_data_crc_sel[1]), | |
346 | .sel2(fbdic1_data_crc_sel[2]), | |
347 | .dout(sbdata1_crc[21:0])); | |
348 | ||
349 | assign mcu_fsr1_data_in[119:0] = | |
350 | {{sbdata1_crc[14],sbdata1_crc[15],sbdata1_crc[16],sbdata1_crc[17], | |
351 | sbdata1_crc[18],sbdata1_crc[19],sbdata1_crc[20],sbdata1_crc[21],sbcmd1_crc[3:0]}, | |
352 | {fbdiwr_bc_cmd_data1[71:64],sbcmd1_crc[4],sbcmd1_crc[5],sbcmd1_crc[6],sbcmd1_crc[7]}, | |
353 | {fbdiwr_bc_cmd_data1[63:56],sbcmd1_crc[11:8]}, | |
354 | {fbdiwr_bc_cmd_data1[55:48],sbcmd1_crc[12],sbcmd1_crc[13],fbdic_f[1:0]}, | |
355 | {fbdiwr_bc_cmd_data1[47:40],fbdic_a_cmd[23:20]}, | |
356 | {fbdiwr_bc_cmd_data1[39:32],fbdic_a_cmd[19:16]}, | |
357 | {fbdiwr_bc_cmd_data1[31:24],fbdic_a_cmd[15:12]}, | |
358 | {fbdiwr_bc_cmd_data1[23:16],fbdic_a_cmd[11:8]}, | |
359 | {fbdiwr_bc_cmd_data1[15:8], fbdic_a_cmd[7:4]}, | |
360 | {fbdiwr_bc_cmd_data1[7:0], fbdic_a_cmd[3:0]}}; | |
361 | ||
362 | //msff_ctl_macro fsr_data1 (width=120) ( | |
363 | // .scan_in(fbd_data1_scanin), | |
364 | // .scan_out(fbd_data1_scanout), | |
365 | // .din(mcu_fsr1_data_in[119:0]), | |
366 | // .dout(mcu_fsr1_data[119:0]), | |
367 | // .l1clk(l1clk)); | |
368 | ||
369 | // output data muxes: 0-normal data, 1-training sequence data, 2/3-blunt-end loopback data | |
370 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_5__width_60 m_mux_fsr0_data_119_60 ( | |
371 | .din0(mcu_fsr0_data_in[119:60]), | |
372 | .din1({5{fbdic0_ts_data[11:0]}}), | |
373 | .din2(fbdic_ibist_data[119:60]), | |
374 | .din3(fbd0_data[119:60]), | |
375 | .din4(fbd0_data[167:108]), | |
376 | .sel0(fbdic_data_sel[0]), | |
377 | .sel1(fbdic_data_sel[1]), | |
378 | .sel2(fbdic_data_sel[2]), | |
379 | .sel3(fbdic_data_sel[3]), | |
380 | .sel4(fbdic_data_sel[4]), | |
381 | .dout(mux_fsr0_data[119:60])); | |
382 | ||
383 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_5__width_60 m_mux_fsr0_data_59_0 ( | |
384 | .din0(mcu_fsr0_data_in[59:0]), | |
385 | .din1({5{fbdic0_ts_data[11:0]}}), | |
386 | .din2(fbdic_ibist_data[59:0]), | |
387 | .din3(fbd0_data[59:0]), | |
388 | .din4(fbd0_data[107:48]), | |
389 | .sel0(fbdic_data_sel[0]), | |
390 | .sel1(fbdic_data_sel[1]), | |
391 | .sel2(fbdic_data_sel[2]), | |
392 | .sel3(fbdic_data_sel[3]), | |
393 | .sel4(fbdic_data_sel[4]), | |
394 | .dout(mux_fsr0_data[59:0])); | |
395 | ||
396 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_5__width_60 m_mux_fsr1_data_119_60 ( | |
397 | .din0(mcu_fsr1_data_in[119:60]), | |
398 | .din1({5{fbdic1_ts_data[11:0]}}), | |
399 | .din2(fbdic_ibist_data[119:60]), | |
400 | .din3(fbd1_data[119:60]), | |
401 | .din4(fbd1_data[167:108]), | |
402 | .sel0(fbdic_data_sel[0]), | |
403 | .sel1(fbdic_data_sel[1]), | |
404 | .sel2(fbdic_data_sel[2]), | |
405 | .sel3(fbdic_data_sel[3]), | |
406 | .sel4(fbdic_data_sel[4]), | |
407 | .dout(mux_fsr1_data[119:60])); | |
408 | ||
409 | mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_5__width_60 m_mux_fsr1_data_59_0 ( | |
410 | .din0(mcu_fsr1_data_in[59:0]), | |
411 | .din1({5{fbdic1_ts_data[11:0]}}), | |
412 | .din2(fbdic_ibist_data[59:0]), | |
413 | .din3(fbd1_data[59:0]), | |
414 | .din4(fbd1_data[107:48]), | |
415 | .sel0(fbdic_data_sel[0]), | |
416 | .sel1(fbdic_data_sel[1]), | |
417 | .sel2(fbdic_data_sel[2]), | |
418 | .sel3(fbdic_data_sel[3]), | |
419 | .sel4(fbdic_data_sel[4]), | |
420 | .dout(mux_fsr1_data[59:0])); | |
421 | ||
422 | // Channel 0 failover muxes | |
423 | assign fbdiwr0_data[11:0] = mux_fsr0_data[11:0]; | |
424 | ||
425 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_23_12 ( | |
426 | .din0(mux_fsr0_data[23:12]), | |
427 | .din1(mux_fsr0_data[11:0]), | |
428 | .sel0(fbdic0_failover_mask_l[0]), | |
429 | .sel1(fbdic0_failover_mask[0]), | |
430 | .dout(fbdiwr0_data[23:12])); | |
431 | ||
432 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_35_24 ( | |
433 | .din0(mux_fsr0_data[35:24]), | |
434 | .din1(mux_fsr0_data[23:12]), | |
435 | .sel0(fbdic0_failover_mask_l[1]), | |
436 | .sel1(fbdic0_failover_mask[1]), | |
437 | .dout(fbdiwr0_data[35:24])); | |
438 | ||
439 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_47_36 ( | |
440 | .din0(mux_fsr0_data[47:36]), | |
441 | .din1(mux_fsr0_data[35:24]), | |
442 | .sel0(fbdic0_failover_mask_l[2]), | |
443 | .sel1(fbdic0_failover_mask[2]), | |
444 | .dout(fbdiwr0_data[47:36])); | |
445 | ||
446 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_59_48 ( | |
447 | .din0(mux_fsr0_data[59:48]), | |
448 | .din1(mux_fsr0_data[47:36]), | |
449 | .sel0(fbdic0_failover_mask_l[3]), | |
450 | .sel1(fbdic0_failover_mask[3]), | |
451 | .dout(fbdiwr0_data[59:48])); | |
452 | ||
453 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_71_60 ( | |
454 | .din0(mux_fsr0_data[71:60]), | |
455 | .din1(mux_fsr0_data[59:48]), | |
456 | .sel0(fbdic0_failover_mask_l[4]), | |
457 | .sel1(fbdic0_failover_mask[4]), | |
458 | .dout(fbdiwr0_data[71:60])); | |
459 | ||
460 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_83_72 ( | |
461 | .din0(mux_fsr0_data[83:72]), | |
462 | .din1(mux_fsr0_data[71:60]), | |
463 | .sel0(fbdic0_failover_mask_l[5]), | |
464 | .sel1(fbdic0_failover_mask[5]), | |
465 | .dout(fbdiwr0_data[83:72])); | |
466 | ||
467 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_95_84 ( | |
468 | .din0(mux_fsr0_data[95:84]), | |
469 | .din1(mux_fsr0_data[83:72]), | |
470 | .sel0(fbdic0_failover_mask_l[6]), | |
471 | .sel1(fbdic0_failover_mask[6]), | |
472 | .dout(fbdiwr0_data[95:84])); | |
473 | ||
474 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_107_96 ( | |
475 | .din0(mux_fsr0_data[107:96]), | |
476 | .din1(mux_fsr0_data[95:84]), | |
477 | .sel0(fbdic0_failover_mask_l[7]), | |
478 | .sel1(fbdic0_failover_mask[7]), | |
479 | .dout(fbdiwr0_data[107:96])); | |
480 | ||
481 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover0_119_108 ( | |
482 | .din0(mux_fsr0_data[119:108]), | |
483 | .din1(mux_fsr0_data[107:96]), | |
484 | .sel0(fbdic0_failover_mask_l[8]), | |
485 | .sel1(fbdic0_failover_mask[8]), | |
486 | .dout(fbdiwr0_data[119:108])); | |
487 | ||
488 | // Channel 1 failover muxes | |
489 | assign fbdiwr1_data[11:0] = mux_fsr1_data[11:0]; | |
490 | ||
491 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_23_12 ( | |
492 | .din0(mux_fsr1_data[23:12]), | |
493 | .din1(mux_fsr1_data[11:0]), | |
494 | .sel0(fbdic1_failover_mask_l[0]), | |
495 | .sel1(fbdic1_failover_mask[0]), | |
496 | .dout(fbdiwr1_data[23:12])); | |
497 | ||
498 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_35_24 ( | |
499 | .din0(mux_fsr1_data[35:24]), | |
500 | .din1(mux_fsr1_data[23:12]), | |
501 | .sel0(fbdic1_failover_mask_l[1]), | |
502 | .sel1(fbdic1_failover_mask[1]), | |
503 | .dout(fbdiwr1_data[35:24])); | |
504 | ||
505 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_47_36 ( | |
506 | .din0(mux_fsr1_data[47:36]), | |
507 | .din1(mux_fsr1_data[35:24]), | |
508 | .sel0(fbdic1_failover_mask_l[2]), | |
509 | .sel1(fbdic1_failover_mask[2]), | |
510 | .dout(fbdiwr1_data[47:36])); | |
511 | ||
512 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_59_48 ( | |
513 | .din0(mux_fsr1_data[59:48]), | |
514 | .din1(mux_fsr1_data[47:36]), | |
515 | .sel0(fbdic1_failover_mask_l[3]), | |
516 | .sel1(fbdic1_failover_mask[3]), | |
517 | .dout(fbdiwr1_data[59:48])); | |
518 | ||
519 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_71_60 ( | |
520 | .din0(mux_fsr1_data[71:60]), | |
521 | .din1(mux_fsr1_data[59:48]), | |
522 | .sel0(fbdic1_failover_mask_l[4]), | |
523 | .sel1(fbdic1_failover_mask[4]), | |
524 | .dout(fbdiwr1_data[71:60])); | |
525 | ||
526 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_83_72 ( | |
527 | .din0(mux_fsr1_data[83:72]), | |
528 | .din1(mux_fsr1_data[71:60]), | |
529 | .sel0(fbdic1_failover_mask_l[5]), | |
530 | .sel1(fbdic1_failover_mask[5]), | |
531 | .dout(fbdiwr1_data[83:72])); | |
532 | ||
533 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_95_84 ( | |
534 | .din0(mux_fsr1_data[95:84]), | |
535 | .din1(mux_fsr1_data[83:72]), | |
536 | .sel0(fbdic1_failover_mask_l[6]), | |
537 | .sel1(fbdic1_failover_mask[6]), | |
538 | .dout(fbdiwr1_data[95:84])); | |
539 | ||
540 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_107_96 ( | |
541 | .din0(mux_fsr1_data[107:96]), | |
542 | .din1(mux_fsr1_data[95:84]), | |
543 | .sel0(fbdic1_failover_mask_l[7]), | |
544 | .sel1(fbdic1_failover_mask[7]), | |
545 | .dout(fbdiwr1_data[107:96])); | |
546 | ||
547 | mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover1_119_108 ( | |
548 | .din0(mux_fsr1_data[119:108]), | |
549 | .din1(mux_fsr1_data[107:96]), | |
550 | .sel0(fbdic1_failover_mask_l[8]), | |
551 | .sel1(fbdic1_failover_mask[8]), | |
552 | .dout(fbdiwr1_data[119:108])); | |
553 | ||
554 | // XOR of CRC for DTM | |
555 | ||
556 | mcu_fbdiwr_dp_and_macro__width_22 m_ch0_crc_mask ( | |
557 | .din0({sbcmd0_crc[13:0],sbdata0_crc[21:14]}), | |
558 | .din1({22{rdpctl_dtm_chnl_enable[0]}}), | |
559 | .dout(ch0_crc[21:0])); | |
560 | ||
561 | mcu_fbdiwr_dp_and_macro__width_22 m_ch1_crc_mask ( | |
562 | .din0({sbdata1_crc[21:14],sbcmd1_crc[13:0]}), | |
563 | .din1({22{rdpctl_dtm_chnl_enable[1]}}), | |
564 | .dout(ch1_crc[21:0])); | |
565 | ||
566 | mcu_fbdiwr_dp_xor_macro__width_22 m_dtm_crc ( | |
567 | .din0(ch0_crc[21:0]), | |
568 | .din1(ch1_crc[21:0]), | |
569 | .dout(fbdiwr_dtm_crc[21:0])); | |
570 | ||
571 | // fixscan start: | |
572 | assign u_ff_sbdata_crc_d1_scanin = scan_in ; | |
573 | assign scan_out = u_ff_sbdata_crc_d1_scanout; | |
574 | // fixscan end: | |
575 | endmodule | |
576 | ||
577 | ||
578 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
579 | // also for pass-gate with decoder | |
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
585 | // any PARAMS parms go into naming of macro | |
586 | ||
587 | module mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_2__width_14 ( | |
588 | din0, | |
589 | sel0, | |
590 | din1, | |
591 | sel1, | |
592 | dout); | |
593 | wire buffout0; | |
594 | wire buffout1; | |
595 | ||
596 | input [13:0] din0; | |
597 | input sel0; | |
598 | input [13:0] din1; | |
599 | input sel1; | |
600 | output [13:0] dout; | |
601 | ||
602 | ||
603 | ||
604 | ||
605 | ||
606 | cl_dp1_muxbuff2_8x c0_0 ( | |
607 | .in0(sel0), | |
608 | .in1(sel1), | |
609 | .out0(buffout0), | |
610 | .out1(buffout1) | |
611 | ); | |
612 | mux2s #(14) d0_0 ( | |
613 | .sel0(buffout0), | |
614 | .sel1(buffout1), | |
615 | .in0(din0[13:0]), | |
616 | .in1(din1[13:0]), | |
617 | .dout(dout[13:0]) | |
618 | ); | |
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | endmodule | |
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | // any PARAMS parms go into naming of macro | |
640 | ||
641 | module mcu_fbdiwr_dp_msff_macro__mux_aonpe__ports_2__width_28 ( | |
642 | din0, | |
643 | sel0, | |
644 | din1, | |
645 | sel1, | |
646 | clk, | |
647 | en, | |
648 | se, | |
649 | scan_in, | |
650 | siclk, | |
651 | soclk, | |
652 | pce_ov, | |
653 | stop, | |
654 | dout, | |
655 | scan_out); | |
656 | wire buffout0; | |
657 | wire buffout1; | |
658 | wire [27:0] muxout; | |
659 | wire l1clk; | |
660 | wire siclk_out; | |
661 | wire soclk_out; | |
662 | wire [26:0] so; | |
663 | ||
664 | input [27:0] din0; | |
665 | input sel0; | |
666 | input [27:0] din1; | |
667 | input sel1; | |
668 | ||
669 | ||
670 | input clk; | |
671 | input en; | |
672 | input se; | |
673 | input scan_in; | |
674 | input siclk; | |
675 | input soclk; | |
676 | input pce_ov; | |
677 | input stop; | |
678 | ||
679 | ||
680 | ||
681 | output [27:0] dout; | |
682 | ||
683 | ||
684 | output scan_out; | |
685 | ||
686 | ||
687 | ||
688 | ||
689 | cl_dp1_muxbuff2_8x c1_0 ( | |
690 | .in0(sel0), | |
691 | .in1(sel1), | |
692 | .out0(buffout0), | |
693 | .out1(buffout1) | |
694 | ); | |
695 | mux2s #(28) d1_0 ( | |
696 | .sel0(buffout0), | |
697 | .sel1(buffout1), | |
698 | .in0(din0[27:0]), | |
699 | .in1(din1[27:0]), | |
700 | .dout(muxout[27:0]) | |
701 | ); | |
702 | cl_dp1_l1hdr_8x c0_0 ( | |
703 | .l2clk(clk), | |
704 | .pce(en), | |
705 | .aclk(siclk), | |
706 | .bclk(soclk), | |
707 | .l1clk(l1clk), | |
708 | .se(se), | |
709 | .pce_ov(pce_ov), | |
710 | .stop(stop), | |
711 | .siclk_out(siclk_out), | |
712 | .soclk_out(soclk_out) | |
713 | ); | |
714 | dff #(28) d0_0 ( | |
715 | .l1clk(l1clk), | |
716 | .siclk(siclk_out), | |
717 | .soclk(soclk_out), | |
718 | .d(muxout[27:0]), | |
719 | .si({scan_in,so[26:0]}), | |
720 | .so({so[26:0],scan_out}), | |
721 | .q(dout[27:0]) | |
722 | ); | |
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | ||
731 | ||
732 | ||
733 | ||
734 | ||
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | endmodule | |
744 | ||
745 | ||
746 | ||
747 | ||
748 | ||
749 | ||
750 | ||
751 | ||
752 | ||
753 | // | |
754 | // xor macro for ports = 2,3 | |
755 | // | |
756 | // | |
757 | ||
758 | ||
759 | ||
760 | ||
761 | ||
762 | module mcu_fbdiwr_dp_xor_macro__width_14 ( | |
763 | din0, | |
764 | din1, | |
765 | dout); | |
766 | input [13:0] din0; | |
767 | input [13:0] din1; | |
768 | output [13:0] dout; | |
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | xor2 #(14) d0_0 ( | |
775 | .in0(din0[13:0]), | |
776 | .in1(din1[13:0]), | |
777 | .out(dout[13:0]) | |
778 | ); | |
779 | ||
780 | ||
781 | ||
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 | endmodule | |
788 | ||
789 | ||
790 | ||
791 | ||
792 | ||
793 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
794 | // also for pass-gate with decoder | |
795 | ||
796 | ||
797 | ||
798 | ||
799 | ||
800 | // any PARAMS parms go into naming of macro | |
801 | ||
802 | module mcu_fbdiwr_dp_mux_macro__mux_pgpe__ports_3__width_36 ( | |
803 | din0, | |
804 | din1, | |
805 | din2, | |
806 | sel0, | |
807 | sel1, | |
808 | muxtst, | |
809 | test, | |
810 | dout); | |
811 | wire psel0; | |
812 | wire psel1; | |
813 | wire psel2; | |
814 | ||
815 | input [35:0] din0; | |
816 | input [35:0] din1; | |
817 | input [35:0] din2; | |
818 | input sel0; | |
819 | input sel1; | |
820 | input muxtst; | |
821 | input test; | |
822 | output [35:0] dout; | |
823 | ||
824 | ||
825 | ||
826 | ||
827 | ||
828 | cl_dp1_penc3_8x c0_0 ( | |
829 | .sel0(sel0), | |
830 | .sel1(sel1), | |
831 | .psel0(psel0), | |
832 | .psel1(psel1), | |
833 | .psel2(psel2), | |
834 | .test(test) | |
835 | ); | |
836 | ||
837 | mux3 #(36) d0_0 ( | |
838 | .sel0(psel0), | |
839 | .sel1(psel1), | |
840 | .sel2(psel2), | |
841 | .in0(din0[35:0]), | |
842 | .in1(din1[35:0]), | |
843 | .in2(din2[35:0]), | |
844 | .dout(dout[35:0]), | |
845 | .muxtst(muxtst) | |
846 | ); | |
847 | ||
848 | ||
849 | ||
850 | ||
851 | ||
852 | ||
853 | ||
854 | ||
855 | ||
856 | ||
857 | ||
858 | ||
859 | ||
860 | endmodule | |
861 | ||
862 | ||
863 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
864 | // also for pass-gate with decoder | |
865 | ||
866 | ||
867 | ||
868 | ||
869 | ||
870 | // any PARAMS parms go into naming of macro | |
871 | ||
872 | module mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_3__width_22 ( | |
873 | din0, | |
874 | sel0, | |
875 | din1, | |
876 | sel1, | |
877 | din2, | |
878 | sel2, | |
879 | dout); | |
880 | wire buffout0; | |
881 | wire buffout1; | |
882 | wire buffout2; | |
883 | ||
884 | input [21:0] din0; | |
885 | input sel0; | |
886 | input [21:0] din1; | |
887 | input sel1; | |
888 | input [21:0] din2; | |
889 | input sel2; | |
890 | output [21:0] dout; | |
891 | ||
892 | ||
893 | ||
894 | ||
895 | ||
896 | cl_dp1_muxbuff3_8x c0_0 ( | |
897 | .in0(sel0), | |
898 | .in1(sel1), | |
899 | .in2(sel2), | |
900 | .out0(buffout0), | |
901 | .out1(buffout1), | |
902 | .out2(buffout2) | |
903 | ); | |
904 | mux3s #(22) d0_0 ( | |
905 | .sel0(buffout0), | |
906 | .sel1(buffout1), | |
907 | .sel2(buffout2), | |
908 | .in0(din0[21:0]), | |
909 | .in1(din1[21:0]), | |
910 | .in2(din2[21:0]), | |
911 | .dout(dout[21:0]) | |
912 | ); | |
913 | ||
914 | ||
915 | ||
916 | ||
917 | ||
918 | ||
919 | ||
920 | ||
921 | ||
922 | ||
923 | ||
924 | ||
925 | ||
926 | endmodule | |
927 | ||
928 | ||
929 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
930 | // also for pass-gate with decoder | |
931 | ||
932 | ||
933 | ||
934 | ||
935 | ||
936 | // any PARAMS parms go into naming of macro | |
937 | ||
938 | module mcu_fbdiwr_dp_mux_macro__mux_aonpe__ports_5__width_60 ( | |
939 | din0, | |
940 | sel0, | |
941 | din1, | |
942 | sel1, | |
943 | din2, | |
944 | sel2, | |
945 | din3, | |
946 | sel3, | |
947 | din4, | |
948 | sel4, | |
949 | dout); | |
950 | wire buffout0; | |
951 | wire buffout1; | |
952 | wire buffout2; | |
953 | wire buffout3; | |
954 | wire buffout4; | |
955 | ||
956 | input [59:0] din0; | |
957 | input sel0; | |
958 | input [59:0] din1; | |
959 | input sel1; | |
960 | input [59:0] din2; | |
961 | input sel2; | |
962 | input [59:0] din3; | |
963 | input sel3; | |
964 | input [59:0] din4; | |
965 | input sel4; | |
966 | output [59:0] dout; | |
967 | ||
968 | ||
969 | ||
970 | ||
971 | ||
972 | cl_dp1_muxbuff5_8x c0_0 ( | |
973 | .in0(sel0), | |
974 | .in1(sel1), | |
975 | .in2(sel2), | |
976 | .in3(sel3), | |
977 | .in4(sel4), | |
978 | .out0(buffout0), | |
979 | .out1(buffout1), | |
980 | .out2(buffout2), | |
981 | .out3(buffout3), | |
982 | .out4(buffout4) | |
983 | ); | |
984 | mux5s #(60) d0_0 ( | |
985 | .sel0(buffout0), | |
986 | .sel1(buffout1), | |
987 | .sel2(buffout2), | |
988 | .sel3(buffout3), | |
989 | .sel4(buffout4), | |
990 | .in0(din0[59:0]), | |
991 | .in1(din1[59:0]), | |
992 | .in2(din2[59:0]), | |
993 | .in3(din3[59:0]), | |
994 | .in4(din4[59:0]), | |
995 | .dout(dout[59:0]) | |
996 | ); | |
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | ||
1010 | endmodule | |
1011 | ||
1012 | ||
1013 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1014 | // also for pass-gate with decoder | |
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | // any PARAMS parms go into naming of macro | |
1021 | ||
1022 | module mcu_fbdiwr_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 ( | |
1023 | din0, | |
1024 | sel0, | |
1025 | din1, | |
1026 | sel1, | |
1027 | dout); | |
1028 | input [11:0] din0; | |
1029 | input sel0; | |
1030 | input [11:0] din1; | |
1031 | input sel1; | |
1032 | output [11:0] dout; | |
1033 | ||
1034 | ||
1035 | ||
1036 | ||
1037 | ||
1038 | mux2s #(12) d0_0 ( | |
1039 | .sel0(sel0), | |
1040 | .sel1(sel1), | |
1041 | .in0(din0[11:0]), | |
1042 | .in1(din1[11:0]), | |
1043 | .dout(dout[11:0]) | |
1044 | ); | |
1045 | ||
1046 | ||
1047 | ||
1048 | ||
1049 | ||
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | ||
1057 | ||
1058 | endmodule | |
1059 | ||
1060 | ||
1061 | // | |
1062 | // and macro for ports = 2,3,4 | |
1063 | // | |
1064 | // | |
1065 | ||
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | module mcu_fbdiwr_dp_and_macro__width_22 ( | |
1071 | din0, | |
1072 | din1, | |
1073 | dout); | |
1074 | input [21:0] din0; | |
1075 | input [21:0] din1; | |
1076 | output [21:0] dout; | |
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | ||
1083 | and2 #(22) d0_0 ( | |
1084 | .in0(din0[21:0]), | |
1085 | .in1(din1[21:0]), | |
1086 | .out(dout[21:0]) | |
1087 | ); | |
1088 | ||
1089 | ||
1090 | ||
1091 | ||
1092 | ||
1093 | ||
1094 | ||
1095 | ||
1096 | ||
1097 | endmodule | |
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | // | |
1104 | // xor macro for ports = 2,3 | |
1105 | // | |
1106 | // | |
1107 | ||
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | module mcu_fbdiwr_dp_xor_macro__width_22 ( | |
1113 | din0, | |
1114 | din1, | |
1115 | dout); | |
1116 | input [21:0] din0; | |
1117 | input [21:0] din1; | |
1118 | output [21:0] dout; | |
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | ||
1124 | xor2 #(22) d0_0 ( | |
1125 | .in0(din0[21:0]), | |
1126 | .in1(din1[21:0]), | |
1127 | .out(dout[21:0]) | |
1128 | ); | |
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | endmodule | |
1138 | ||
1139 | ||
1140 | ||
1141 |