projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: mcu_fdoklu_ctl.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module mcu_fdoklu_ctl ( | |
| 36 | fdout0_frame_lock_sync, | |
| 37 | fdout1_frame_lock_sync, | |
| 38 | fdout0_rptr0, | |
| 39 | fdout0_rptr1, | |
| 40 | fdout0_rptr2, | |
| 41 | fdout0_rptr3, | |
| 42 | fdout0_rptr4, | |
| 43 | fdout0_rptr5, | |
| 44 | fdout0_rptr6, | |
| 45 | fdout0_rptr7, | |
| 46 | fdout0_rptr8, | |
| 47 | fdout0_rptr9, | |
| 48 | fdout0_rptr10, | |
| 49 | fdout0_rptr11, | |
| 50 | fdout0_rptr12, | |
| 51 | fdout0_rptr13, | |
| 52 | fdout1_rptr0, | |
| 53 | fdout1_rptr1, | |
| 54 | fdout1_rptr2, | |
| 55 | fdout1_rptr3, | |
| 56 | fdout1_rptr4, | |
| 57 | fdout1_rptr5, | |
| 58 | fdout1_rptr6, | |
| 59 | fdout1_rptr7, | |
| 60 | fdout1_rptr8, | |
| 61 | fdout1_rptr9, | |
| 62 | fdout1_rptr10, | |
| 63 | fdout1_rptr11, | |
| 64 | fdout1_rptr12, | |
| 65 | fdout1_rptr13, | |
| 66 | fdout_idle_lfsr, | |
| 67 | fdout_idle_lfsr_l_0, | |
| 68 | fdout_link_cnt, | |
| 69 | fbdic_link_cnt_eq_0_d1, | |
| 70 | rdpctl_kp_lnk_up, | |
| 71 | fbdic_link_cnt_en, | |
| 72 | fbdic_idle_lfsr_reset, | |
| 73 | fbdic_link_cnt_reset, | |
| 74 | fbdic_l0_state, | |
| 75 | fbd0_frame_lock, | |
| 76 | fbd1_frame_lock, | |
| 77 | tcu_mcu_fbd_clk_stop, | |
| 78 | tcu_atpg_mode, | |
| 79 | drl2clk, | |
| 80 | scan_in, | |
| 81 | scan_out, | |
| 82 | tcu_aclk, | |
| 83 | tcu_bclk, | |
| 84 | tcu_scan_en, | |
| 85 | tcu_pce_ov, | |
| 86 | tcu_mcu_testmode); | |
| 87 | wire pce_ov; | |
| 88 | wire siclk; | |
| 89 | wire soclk; | |
| 90 | wire se; | |
| 91 | wire stop; | |
| 92 | wire drl2clk_buf; | |
| 93 | wire l1clk; | |
| 94 | wire [5:0] fdout_link_cnt_in; | |
| 95 | wire fbdic_link_cnt_eq_0; | |
| 96 | wire ff_link_cnt_scanin; | |
| 97 | wire ff_link_cnt_scanout; | |
| 98 | wire ff_link_cnt_eq_0_d1_scanin; | |
| 99 | wire ff_link_cnt_eq_0_d1_scanout; | |
| 100 | wire sync_fbd0_framelock0_scanin; | |
| 101 | wire sync_fbd0_framelock0_scanout; | |
| 102 | wire sync_fbd0_framelock1_scanin; | |
| 103 | wire sync_fbd0_framelock1_scanout; | |
| 104 | wire sync_fbd0_framelock2_scanin; | |
| 105 | wire sync_fbd0_framelock2_scanout; | |
| 106 | wire sync_fbd0_framelock3_scanin; | |
| 107 | wire sync_fbd0_framelock3_scanout; | |
| 108 | wire sync_fbd0_framelock4_scanin; | |
| 109 | wire sync_fbd0_framelock4_scanout; | |
| 110 | wire sync_fbd0_framelock5_scanin; | |
| 111 | wire sync_fbd0_framelock5_scanout; | |
| 112 | wire sync_fbd0_framelock6_scanin; | |
| 113 | wire sync_fbd0_framelock6_scanout; | |
| 114 | wire sync_fbd0_framelock7_scanin; | |
| 115 | wire sync_fbd0_framelock7_scanout; | |
| 116 | wire sync_fbd0_framelock8_scanin; | |
| 117 | wire sync_fbd0_framelock8_scanout; | |
| 118 | wire sync_fbd0_framelock9_scanin; | |
| 119 | wire sync_fbd0_framelock9_scanout; | |
| 120 | wire sync_fbd0_framelock10_scanin; | |
| 121 | wire sync_fbd0_framelock10_scanout; | |
| 122 | wire sync_fbd0_framelock11_scanin; | |
| 123 | wire sync_fbd0_framelock11_scanout; | |
| 124 | wire sync_fbd0_framelock12_scanin; | |
| 125 | wire sync_fbd0_framelock12_scanout; | |
| 126 | wire sync_fbd0_framelock13_scanin; | |
| 127 | wire sync_fbd0_framelock13_scanout; | |
| 128 | wire sync_fbd1_framelock0_scanin; | |
| 129 | wire sync_fbd1_framelock0_scanout; | |
| 130 | wire sync_fbd1_framelock1_scanin; | |
| 131 | wire sync_fbd1_framelock1_scanout; | |
| 132 | wire sync_fbd1_framelock2_scanin; | |
| 133 | wire sync_fbd1_framelock2_scanout; | |
| 134 | wire sync_fbd1_framelock3_scanin; | |
| 135 | wire sync_fbd1_framelock3_scanout; | |
| 136 | wire sync_fbd1_framelock4_scanin; | |
| 137 | wire sync_fbd1_framelock4_scanout; | |
| 138 | wire sync_fbd1_framelock5_scanin; | |
| 139 | wire sync_fbd1_framelock5_scanout; | |
| 140 | wire sync_fbd1_framelock6_scanin; | |
| 141 | wire sync_fbd1_framelock6_scanout; | |
| 142 | wire sync_fbd1_framelock7_scanin; | |
| 143 | wire sync_fbd1_framelock7_scanout; | |
| 144 | wire sync_fbd1_framelock8_scanin; | |
| 145 | wire sync_fbd1_framelock8_scanout; | |
| 146 | wire sync_fbd1_framelock9_scanin; | |
| 147 | wire sync_fbd1_framelock9_scanout; | |
| 148 | wire sync_fbd1_framelock10_scanin; | |
| 149 | wire sync_fbd1_framelock10_scanout; | |
| 150 | wire sync_fbd1_framelock11_scanin; | |
| 151 | wire sync_fbd1_framelock11_scanout; | |
| 152 | wire sync_fbd1_framelock12_scanin; | |
| 153 | wire sync_fbd1_framelock12_scanout; | |
| 154 | wire sync_fbd1_framelock13_scanin; | |
| 155 | wire sync_fbd1_framelock13_scanout; | |
| 156 | wire [1:0] fdout0_rptr0_in; | |
| 157 | wire [1:0] fdout0_rptr1_in; | |
| 158 | wire [1:0] fdout0_rptr2_in; | |
| 159 | wire [1:0] fdout0_rptr3_in; | |
| 160 | wire [1:0] fdout0_rptr4_in; | |
| 161 | wire [1:0] fdout0_rptr5_in; | |
| 162 | wire [1:0] fdout0_rptr6_in; | |
| 163 | wire [1:0] fdout0_rptr7_in; | |
| 164 | wire [1:0] fdout0_rptr8_in; | |
| 165 | wire [1:0] fdout0_rptr9_in; | |
| 166 | wire [1:0] fdout0_rptr10_in; | |
| 167 | wire [1:0] fdout0_rptr11_in; | |
| 168 | wire [1:0] fdout0_rptr12_in; | |
| 169 | wire [1:0] fdout0_rptr13_in; | |
| 170 | wire ff0_rptr0_scanin; | |
| 171 | wire ff0_rptr0_scanout; | |
| 172 | wire ff0_rptr1_scanin; | |
| 173 | wire ff0_rptr1_scanout; | |
| 174 | wire ff0_rptr2_scanin; | |
| 175 | wire ff0_rptr2_scanout; | |
| 176 | wire ff0_rptr3_scanin; | |
| 177 | wire ff0_rptr3_scanout; | |
| 178 | wire ff0_rptr4_scanin; | |
| 179 | wire ff0_rptr4_scanout; | |
| 180 | wire ff0_rptr5_scanin; | |
| 181 | wire ff0_rptr5_scanout; | |
| 182 | wire ff0_rptr6_scanin; | |
| 183 | wire ff0_rptr6_scanout; | |
| 184 | wire ff0_rptr7_scanin; | |
| 185 | wire ff0_rptr7_scanout; | |
| 186 | wire ff0_rptr8_scanin; | |
| 187 | wire ff0_rptr8_scanout; | |
| 188 | wire ff0_rptr9_scanin; | |
| 189 | wire ff0_rptr9_scanout; | |
| 190 | wire ff0_rptr10_scanin; | |
| 191 | wire ff0_rptr10_scanout; | |
| 192 | wire ff0_rptr11_scanin; | |
| 193 | wire ff0_rptr11_scanout; | |
| 194 | wire ff0_rptr12_scanin; | |
| 195 | wire ff0_rptr12_scanout; | |
| 196 | wire ff0_rptr13_scanin; | |
| 197 | wire ff0_rptr13_scanout; | |
| 198 | wire [1:0] fdout1_rptr0_in; | |
| 199 | wire [1:0] fdout1_rptr1_in; | |
| 200 | wire [1:0] fdout1_rptr2_in; | |
| 201 | wire [1:0] fdout1_rptr3_in; | |
| 202 | wire [1:0] fdout1_rptr4_in; | |
| 203 | wire [1:0] fdout1_rptr5_in; | |
| 204 | wire [1:0] fdout1_rptr6_in; | |
| 205 | wire [1:0] fdout1_rptr7_in; | |
| 206 | wire [1:0] fdout1_rptr8_in; | |
| 207 | wire [1:0] fdout1_rptr9_in; | |
| 208 | wire [1:0] fdout1_rptr10_in; | |
| 209 | wire [1:0] fdout1_rptr11_in; | |
| 210 | wire [1:0] fdout1_rptr12_in; | |
| 211 | wire [1:0] fdout1_rptr13_in; | |
| 212 | wire ff1_rptr0_scanin; | |
| 213 | wire ff1_rptr0_scanout; | |
| 214 | wire ff1_rptr1_scanin; | |
| 215 | wire ff1_rptr1_scanout; | |
| 216 | wire ff1_rptr2_scanin; | |
| 217 | wire ff1_rptr2_scanout; | |
| 218 | wire ff1_rptr3_scanin; | |
| 219 | wire ff1_rptr3_scanout; | |
| 220 | wire ff1_rptr4_scanin; | |
| 221 | wire ff1_rptr4_scanout; | |
| 222 | wire ff1_rptr5_scanin; | |
| 223 | wire ff1_rptr5_scanout; | |
| 224 | wire ff1_rptr6_scanin; | |
| 225 | wire ff1_rptr6_scanout; | |
| 226 | wire ff1_rptr7_scanin; | |
| 227 | wire ff1_rptr7_scanout; | |
| 228 | wire ff1_rptr8_scanin; | |
| 229 | wire ff1_rptr8_scanout; | |
| 230 | wire ff1_rptr9_scanin; | |
| 231 | wire ff1_rptr9_scanout; | |
| 232 | wire ff1_rptr10_scanin; | |
| 233 | wire ff1_rptr10_scanout; | |
| 234 | wire ff1_rptr11_scanin; | |
| 235 | wire ff1_rptr11_scanout; | |
| 236 | wire ff1_rptr12_scanin; | |
| 237 | wire ff1_rptr12_scanout; | |
| 238 | wire ff1_rptr13_scanin; | |
| 239 | wire ff1_rptr13_scanout; | |
| 240 | wire [11:0] fdout_idle_lfsr_in; | |
| 241 | wire ff_idle_lfsr_scanin; | |
| 242 | wire ff_idle_lfsr_scanout; | |
| 243 | wire spares_scanin; | |
| 244 | wire spares_scanout; | |
| 245 | ||
| 246 | ||
| 247 | output [13:0] fdout0_frame_lock_sync; | |
| 248 | output [13:0] fdout1_frame_lock_sync; | |
| 249 | ||
| 250 | output [1:0] fdout0_rptr0; | |
| 251 | output [1:0] fdout0_rptr1; | |
| 252 | output [1:0] fdout0_rptr2; | |
| 253 | output [1:0] fdout0_rptr3; | |
| 254 | output [1:0] fdout0_rptr4; | |
| 255 | output [1:0] fdout0_rptr5; | |
| 256 | output [1:0] fdout0_rptr6; | |
| 257 | output [1:0] fdout0_rptr7; | |
| 258 | output [1:0] fdout0_rptr8; | |
| 259 | output [1:0] fdout0_rptr9; | |
| 260 | output [1:0] fdout0_rptr10; | |
| 261 | output [1:0] fdout0_rptr11; | |
| 262 | output [1:0] fdout0_rptr12; | |
| 263 | output [1:0] fdout0_rptr13; | |
| 264 | ||
| 265 | output [1:0] fdout1_rptr0; | |
| 266 | output [1:0] fdout1_rptr1; | |
| 267 | output [1:0] fdout1_rptr2; | |
| 268 | output [1:0] fdout1_rptr3; | |
| 269 | output [1:0] fdout1_rptr4; | |
| 270 | output [1:0] fdout1_rptr5; | |
| 271 | output [1:0] fdout1_rptr6; | |
| 272 | output [1:0] fdout1_rptr7; | |
| 273 | output [1:0] fdout1_rptr8; | |
| 274 | output [1:0] fdout1_rptr9; | |
| 275 | output [1:0] fdout1_rptr10; | |
| 276 | output [1:0] fdout1_rptr11; | |
| 277 | output [1:0] fdout1_rptr12; | |
| 278 | output [1:0] fdout1_rptr13; | |
| 279 | ||
| 280 | output [11:0] fdout_idle_lfsr; | |
| 281 | output fdout_idle_lfsr_l_0; | |
| 282 | ||
| 283 | output [5:0] fdout_link_cnt; | |
| 284 | ||
| 285 | output fbdic_link_cnt_eq_0_d1; | |
| 286 | ||
| 287 | input rdpctl_kp_lnk_up; | |
| 288 | input fbdic_link_cnt_en; | |
| 289 | input fbdic_idle_lfsr_reset; | |
| 290 | input [5:0] fbdic_link_cnt_reset; | |
| 291 | input fbdic_l0_state; | |
| 292 | ||
| 293 | input [13:0] fbd0_frame_lock; | |
| 294 | input [13:0] fbd1_frame_lock; | |
| 295 | ||
| 296 | input tcu_mcu_fbd_clk_stop; | |
| 297 | input tcu_atpg_mode; | |
| 298 | ||
| 299 | input drl2clk; | |
| 300 | input scan_in; | |
| 301 | output scan_out; | |
| 302 | input tcu_aclk; | |
| 303 | input tcu_bclk; | |
| 304 | input tcu_scan_en; | |
| 305 | input tcu_pce_ov; | |
| 306 | input tcu_mcu_testmode; | |
| 307 | ||
| 308 | // Scan reassigns | |
| 309 | assign pce_ov = tcu_pce_ov; | |
| 310 | assign siclk = tcu_aclk & tcu_mcu_testmode; | |
| 311 | assign soclk = tcu_bclk & tcu_mcu_testmode; | |
| 312 | assign se = tcu_scan_en & tcu_mcu_testmode; | |
| 313 | assign stop = tcu_mcu_fbd_clk_stop & ~tcu_atpg_mode; | |
| 314 | ||
| 315 | cl_sc1_clk_inv_8x inv_drl2clk ( | |
| 316 | .clkin(drl2clk), | |
| 317 | .clkout(drl2clk_buf)); | |
| 318 | ||
| 319 | mcu_fdoklu_ctl_l1clkhdr_ctl_macro clkgen ( | |
| 320 | .l2clk(drl2clk_buf), | |
| 321 | .l1en (1'b1 ), | |
| 322 | .l1clk(l1clk), | |
| 323 | .pce_ov(pce_ov), | |
| 324 | .stop(stop), | |
| 325 | .se(se)); | |
| 326 | ||
| 327 | assign fdout_link_cnt_in[5:0] = {6{fbdic_link_cnt_en}} & | |
| 328 | (fbdic_link_cnt_eq_0 ? fbdic_link_cnt_reset[5:0] - 6'h1 : fdout_link_cnt[5:0] - 6'h1); | |
| 329 | ||
| 330 | mcu_fdoklu_ctl_msff_ctl_macro__width_6 ff_link_cnt ( | |
| 331 | .scan_in(ff_link_cnt_scanin), | |
| 332 | .scan_out(ff_link_cnt_scanout), | |
| 333 | .din(fdout_link_cnt_in[5:0]), | |
| 334 | .dout(fdout_link_cnt[5:0]), | |
| 335 | .l1clk(l1clk), | |
| 336 | .siclk(siclk), | |
| 337 | .soclk(soclk)); | |
| 338 | ||
| 339 | assign fbdic_link_cnt_eq_0 = fdout_link_cnt[5:0] == 6'h0; | |
| 340 | mcu_fdoklu_ctl_msff_ctl_macro ff_link_cnt_eq_0_d1 ( | |
| 341 | .scan_in(ff_link_cnt_eq_0_d1_scanin), | |
| 342 | .scan_out(ff_link_cnt_eq_0_d1_scanout), | |
| 343 | .din(fbdic_link_cnt_eq_0), | |
| 344 | .dout(fbdic_link_cnt_eq_0_d1), | |
| 345 | .l1clk(l1clk), | |
| 346 | .siclk(siclk), | |
| 347 | .soclk(soclk)); | |
| 348 | ||
| 349 | // Frame lock synchronizers | |
| 350 | ||
| 351 | cl_sc1_clksyncff_4x sync_fbd0_framelock0 ( | |
| 352 | .d(fbd0_frame_lock[0]), | |
| 353 | .q(fdout0_frame_lock_sync[0]), | |
| 354 | .si(sync_fbd0_framelock0_scanin), | |
| 355 | .so(sync_fbd0_framelock0_scanout), | |
| 356 | .l1clk(l1clk), | |
| 357 | .siclk(siclk), | |
| 358 | .soclk(soclk)); | |
| 359 | ||
| 360 | cl_sc1_clksyncff_4x sync_fbd0_framelock1 ( | |
| 361 | .d(fbd0_frame_lock[1]), | |
| 362 | .q(fdout0_frame_lock_sync[1]), | |
| 363 | .si(sync_fbd0_framelock1_scanin), | |
| 364 | .so(sync_fbd0_framelock1_scanout), | |
| 365 | .l1clk(l1clk), | |
| 366 | .siclk(siclk), | |
| 367 | .soclk(soclk)); | |
| 368 | ||
| 369 | cl_sc1_clksyncff_4x sync_fbd0_framelock2 ( | |
| 370 | .d(fbd0_frame_lock[2]), | |
| 371 | .q(fdout0_frame_lock_sync[2]), | |
| 372 | .si(sync_fbd0_framelock2_scanin), | |
| 373 | .so(sync_fbd0_framelock2_scanout), | |
| 374 | .l1clk(l1clk), | |
| 375 | .siclk(siclk), | |
| 376 | .soclk(soclk)); | |
| 377 | ||
| 378 | cl_sc1_clksyncff_4x sync_fbd0_framelock3 ( | |
| 379 | .d(fbd0_frame_lock[3]), | |
| 380 | .q(fdout0_frame_lock_sync[3]), | |
| 381 | .si(sync_fbd0_framelock3_scanin), | |
| 382 | .so(sync_fbd0_framelock3_scanout), | |
| 383 | .l1clk(l1clk), | |
| 384 | .siclk(siclk), | |
| 385 | .soclk(soclk)); | |
| 386 | ||
| 387 | cl_sc1_clksyncff_4x sync_fbd0_framelock4 ( | |
| 388 | .d(fbd0_frame_lock[4]), | |
| 389 | .q(fdout0_frame_lock_sync[4]), | |
| 390 | .si(sync_fbd0_framelock4_scanin), | |
| 391 | .so(sync_fbd0_framelock4_scanout), | |
| 392 | .l1clk(l1clk), | |
| 393 | .siclk(siclk), | |
| 394 | .soclk(soclk)); | |
| 395 | ||
| 396 | cl_sc1_clksyncff_4x sync_fbd0_framelock5 ( | |
| 397 | .d(fbd0_frame_lock[5]), | |
| 398 | .q(fdout0_frame_lock_sync[5]), | |
| 399 | .si(sync_fbd0_framelock5_scanin), | |
| 400 | .so(sync_fbd0_framelock5_scanout), | |
| 401 | .l1clk(l1clk), | |
| 402 | .siclk(siclk), | |
| 403 | .soclk(soclk)); | |
| 404 | ||
| 405 | cl_sc1_clksyncff_4x sync_fbd0_framelock6 ( | |
| 406 | .d(fbd0_frame_lock[6]), | |
| 407 | .q(fdout0_frame_lock_sync[6]), | |
| 408 | .si(sync_fbd0_framelock6_scanin), | |
| 409 | .so(sync_fbd0_framelock6_scanout), | |
| 410 | .l1clk(l1clk), | |
| 411 | .siclk(siclk), | |
| 412 | .soclk(soclk)); | |
| 413 | ||
| 414 | cl_sc1_clksyncff_4x sync_fbd0_framelock7 ( | |
| 415 | .d(fbd0_frame_lock[7]), | |
| 416 | .q(fdout0_frame_lock_sync[7]), | |
| 417 | .si(sync_fbd0_framelock7_scanin), | |
| 418 | .so(sync_fbd0_framelock7_scanout), | |
| 419 | .l1clk(l1clk), | |
| 420 | .siclk(siclk), | |
| 421 | .soclk(soclk)); | |
| 422 | ||
| 423 | cl_sc1_clksyncff_4x sync_fbd0_framelock8 ( | |
| 424 | .d(fbd0_frame_lock[8]), | |
| 425 | .q(fdout0_frame_lock_sync[8]), | |
| 426 | .si(sync_fbd0_framelock8_scanin), | |
| 427 | .so(sync_fbd0_framelock8_scanout), | |
| 428 | .l1clk(l1clk), | |
| 429 | .siclk(siclk), | |
| 430 | .soclk(soclk)); | |
| 431 | ||
| 432 | cl_sc1_clksyncff_4x sync_fbd0_framelock9 ( | |
| 433 | .d(fbd0_frame_lock[9]), | |
| 434 | .q(fdout0_frame_lock_sync[9]), | |
| 435 | .si(sync_fbd0_framelock9_scanin), | |
| 436 | .so(sync_fbd0_framelock9_scanout), | |
| 437 | .l1clk(l1clk), | |
| 438 | .siclk(siclk), | |
| 439 | .soclk(soclk)); | |
| 440 | ||
| 441 | cl_sc1_clksyncff_4x sync_fbd0_framelock10 ( | |
| 442 | .d(fbd0_frame_lock[10]), | |
| 443 | .q(fdout0_frame_lock_sync[10]), | |
| 444 | .si(sync_fbd0_framelock10_scanin), | |
| 445 | .so(sync_fbd0_framelock10_scanout), | |
| 446 | .l1clk(l1clk), | |
| 447 | .siclk(siclk), | |
| 448 | .soclk(soclk)); | |
| 449 | ||
| 450 | cl_sc1_clksyncff_4x sync_fbd0_framelock11 ( | |
| 451 | .d(fbd0_frame_lock[11]), | |
| 452 | .q(fdout0_frame_lock_sync[11]), | |
| 453 | .si(sync_fbd0_framelock11_scanin), | |
| 454 | .so(sync_fbd0_framelock11_scanout), | |
| 455 | .l1clk(l1clk), | |
| 456 | .siclk(siclk), | |
| 457 | .soclk(soclk)); | |
| 458 | ||
| 459 | cl_sc1_clksyncff_4x sync_fbd0_framelock12 ( | |
| 460 | .d(fbd0_frame_lock[12]), | |
| 461 | .q(fdout0_frame_lock_sync[12]), | |
| 462 | .si(sync_fbd0_framelock12_scanin), | |
| 463 | .so(sync_fbd0_framelock12_scanout), | |
| 464 | .l1clk(l1clk), | |
| 465 | .siclk(siclk), | |
| 466 | .soclk(soclk)); | |
| 467 | ||
| 468 | cl_sc1_clksyncff_4x sync_fbd0_framelock13 ( | |
| 469 | .d(fbd0_frame_lock[13]), | |
| 470 | .q(fdout0_frame_lock_sync[13]), | |
| 471 | .si(sync_fbd0_framelock13_scanin), | |
| 472 | .so(sync_fbd0_framelock13_scanout), | |
| 473 | .l1clk(l1clk), | |
| 474 | .siclk(siclk), | |
| 475 | .soclk(soclk)); | |
| 476 | ||
| 477 | cl_sc1_clksyncff_4x sync_fbd1_framelock0 ( | |
| 478 | .d(fbd1_frame_lock[0]), | |
| 479 | .q(fdout1_frame_lock_sync[0]), | |
| 480 | .si(sync_fbd1_framelock0_scanin), | |
| 481 | .so(sync_fbd1_framelock0_scanout), | |
| 482 | .l1clk(l1clk), | |
| 483 | .siclk(siclk), | |
| 484 | .soclk(soclk)); | |
| 485 | ||
| 486 | cl_sc1_clksyncff_4x sync_fbd1_framelock1 ( | |
| 487 | .d(fbd1_frame_lock[1]), | |
| 488 | .q(fdout1_frame_lock_sync[1]), | |
| 489 | .si(sync_fbd1_framelock1_scanin), | |
| 490 | .so(sync_fbd1_framelock1_scanout), | |
| 491 | .l1clk(l1clk), | |
| 492 | .siclk(siclk), | |
| 493 | .soclk(soclk)); | |
| 494 | ||
| 495 | cl_sc1_clksyncff_4x sync_fbd1_framelock2 ( | |
| 496 | .d(fbd1_frame_lock[2]), | |
| 497 | .q(fdout1_frame_lock_sync[2]), | |
| 498 | .si(sync_fbd1_framelock2_scanin), | |
| 499 | .so(sync_fbd1_framelock2_scanout), | |
| 500 | .l1clk(l1clk), | |
| 501 | .siclk(siclk), | |
| 502 | .soclk(soclk)); | |
| 503 | ||
| 504 | cl_sc1_clksyncff_4x sync_fbd1_framelock3 ( | |
| 505 | .d(fbd1_frame_lock[3]), | |
| 506 | .q(fdout1_frame_lock_sync[3]), | |
| 507 | .si(sync_fbd1_framelock3_scanin), | |
| 508 | .so(sync_fbd1_framelock3_scanout), | |
| 509 | .l1clk(l1clk), | |
| 510 | .siclk(siclk), | |
| 511 | .soclk(soclk)); | |
| 512 | ||
| 513 | cl_sc1_clksyncff_4x sync_fbd1_framelock4 ( | |
| 514 | .d(fbd1_frame_lock[4]), | |
| 515 | .q(fdout1_frame_lock_sync[4]), | |
| 516 | .si(sync_fbd1_framelock4_scanin), | |
| 517 | .so(sync_fbd1_framelock4_scanout), | |
| 518 | .l1clk(l1clk), | |
| 519 | .siclk(siclk), | |
| 520 | .soclk(soclk)); | |
| 521 | ||
| 522 | cl_sc1_clksyncff_4x sync_fbd1_framelock5 ( | |
| 523 | .d(fbd1_frame_lock[5]), | |
| 524 | .q(fdout1_frame_lock_sync[5]), | |
| 525 | .si(sync_fbd1_framelock5_scanin), | |
| 526 | .so(sync_fbd1_framelock5_scanout), | |
| 527 | .l1clk(l1clk), | |
| 528 | .siclk(siclk), | |
| 529 | .soclk(soclk)); | |
| 530 | ||
| 531 | cl_sc1_clksyncff_4x sync_fbd1_framelock6 ( | |
| 532 | .d(fbd1_frame_lock[6]), | |
| 533 | .q(fdout1_frame_lock_sync[6]), | |
| 534 | .si(sync_fbd1_framelock6_scanin), | |
| 535 | .so(sync_fbd1_framelock6_scanout), | |
| 536 | .l1clk(l1clk), | |
| 537 | .siclk(siclk), | |
| 538 | .soclk(soclk)); | |
| 539 | ||
| 540 | cl_sc1_clksyncff_4x sync_fbd1_framelock7 ( | |
| 541 | .d(fbd1_frame_lock[7]), | |
| 542 | .q(fdout1_frame_lock_sync[7]), | |
| 543 | .si(sync_fbd1_framelock7_scanin), | |
| 544 | .so(sync_fbd1_framelock7_scanout), | |
| 545 | .l1clk(l1clk), | |
| 546 | .siclk(siclk), | |
| 547 | .soclk(soclk)); | |
| 548 | ||
| 549 | cl_sc1_clksyncff_4x sync_fbd1_framelock8 ( | |
| 550 | .d(fbd1_frame_lock[8]), | |
| 551 | .q(fdout1_frame_lock_sync[8]), | |
| 552 | .si(sync_fbd1_framelock8_scanin), | |
| 553 | .so(sync_fbd1_framelock8_scanout), | |
| 554 | .l1clk(l1clk), | |
| 555 | .siclk(siclk), | |
| 556 | .soclk(soclk)); | |
| 557 | ||
| 558 | cl_sc1_clksyncff_4x sync_fbd1_framelock9 ( | |
| 559 | .d(fbd1_frame_lock[9]), | |
| 560 | .q(fdout1_frame_lock_sync[9]), | |
| 561 | .si(sync_fbd1_framelock9_scanin), | |
| 562 | .so(sync_fbd1_framelock9_scanout), | |
| 563 | .l1clk(l1clk), | |
| 564 | .siclk(siclk), | |
| 565 | .soclk(soclk)); | |
| 566 | ||
| 567 | cl_sc1_clksyncff_4x sync_fbd1_framelock10 ( | |
| 568 | .d(fbd1_frame_lock[10]), | |
| 569 | .q(fdout1_frame_lock_sync[10]), | |
| 570 | .si(sync_fbd1_framelock10_scanin), | |
| 571 | .so(sync_fbd1_framelock10_scanout), | |
| 572 | .l1clk(l1clk), | |
| 573 | .siclk(siclk), | |
| 574 | .soclk(soclk)); | |
| 575 | ||
| 576 | cl_sc1_clksyncff_4x sync_fbd1_framelock11 ( | |
| 577 | .d(fbd1_frame_lock[11]), | |
| 578 | .q(fdout1_frame_lock_sync[11]), | |
| 579 | .si(sync_fbd1_framelock11_scanin), | |
| 580 | .so(sync_fbd1_framelock11_scanout), | |
| 581 | .l1clk(l1clk), | |
| 582 | .siclk(siclk), | |
| 583 | .soclk(soclk)); | |
| 584 | ||
| 585 | cl_sc1_clksyncff_4x sync_fbd1_framelock12 ( | |
| 586 | .d(fbd1_frame_lock[12]), | |
| 587 | .q(fdout1_frame_lock_sync[12]), | |
| 588 | .si(sync_fbd1_framelock12_scanin), | |
| 589 | .so(sync_fbd1_framelock12_scanout), | |
| 590 | .l1clk(l1clk), | |
| 591 | .siclk(siclk), | |
| 592 | .soclk(soclk)); | |
| 593 | ||
| 594 | cl_sc1_clksyncff_4x sync_fbd1_framelock13 ( | |
| 595 | .d(fbd1_frame_lock[13]), | |
| 596 | .q(fdout1_frame_lock_sync[13]), | |
| 597 | .si(sync_fbd1_framelock13_scanin), | |
| 598 | .so(sync_fbd1_framelock13_scanout), | |
| 599 | .l1clk(l1clk), | |
| 600 | .siclk(siclk), | |
| 601 | .soclk(soclk)); | |
| 602 | ||
| 603 | // Cross domain FIFO read pointers | |
| 604 | ||
| 605 | assign fdout0_rptr0_in[1:0] = {fdout0_rptr0[0],~fdout0_rptr0[1]} & {2{fdout0_frame_lock_sync[0]}}; | |
| 606 | assign fdout0_rptr1_in[1:0] = {fdout0_rptr1[0],~fdout0_rptr1[1]} & {2{fdout0_frame_lock_sync[1]}}; | |
| 607 | assign fdout0_rptr2_in[1:0] = {fdout0_rptr2[0],~fdout0_rptr2[1]} & {2{fdout0_frame_lock_sync[2]}}; | |
| 608 | assign fdout0_rptr3_in[1:0] = {fdout0_rptr3[0],~fdout0_rptr3[1]} & {2{fdout0_frame_lock_sync[3]}}; | |
| 609 | assign fdout0_rptr4_in[1:0] = {fdout0_rptr4[0],~fdout0_rptr4[1]} & {2{fdout0_frame_lock_sync[4]}}; | |
| 610 | assign fdout0_rptr5_in[1:0] = {fdout0_rptr5[0],~fdout0_rptr5[1]} & {2{fdout0_frame_lock_sync[5]}}; | |
| 611 | assign fdout0_rptr6_in[1:0] = {fdout0_rptr6[0],~fdout0_rptr6[1]} & {2{fdout0_frame_lock_sync[6]}}; | |
| 612 | assign fdout0_rptr7_in[1:0] = {fdout0_rptr7[0],~fdout0_rptr7[1]} & {2{fdout0_frame_lock_sync[7]}}; | |
| 613 | assign fdout0_rptr8_in[1:0] = {fdout0_rptr8[0],~fdout0_rptr8[1]} & {2{fdout0_frame_lock_sync[8]}}; | |
| 614 | assign fdout0_rptr9_in[1:0] = {fdout0_rptr9[0],~fdout0_rptr9[1]} & {2{fdout0_frame_lock_sync[9]}}; | |
| 615 | assign fdout0_rptr10_in[1:0] = {fdout0_rptr10[0],~fdout0_rptr10[1]} & {2{fdout0_frame_lock_sync[10]}}; | |
| 616 | assign fdout0_rptr11_in[1:0] = {fdout0_rptr11[0],~fdout0_rptr11[1]} & {2{fdout0_frame_lock_sync[11]}}; | |
| 617 | assign fdout0_rptr12_in[1:0] = {fdout0_rptr12[0],~fdout0_rptr12[1]} & {2{fdout0_frame_lock_sync[12]}}; | |
| 618 | assign fdout0_rptr13_in[1:0] = {fdout0_rptr13[0],~fdout0_rptr13[1]} & {2{fdout0_frame_lock_sync[13]}}; | |
| 619 | ||
| 620 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr0 ( | |
| 621 | .scan_in(ff0_rptr0_scanin), | |
| 622 | .scan_out(ff0_rptr0_scanout), | |
| 623 | .din(fdout0_rptr0_in[1:0]), | |
| 624 | .dout(fdout0_rptr0[1:0]), | |
| 625 | .l1clk(l1clk), | |
| 626 | .siclk(siclk), | |
| 627 | .soclk(soclk)); | |
| 628 | ||
| 629 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr1 ( | |
| 630 | .scan_in(ff0_rptr1_scanin), | |
| 631 | .scan_out(ff0_rptr1_scanout), | |
| 632 | .din(fdout0_rptr1_in[1:0]), | |
| 633 | .dout(fdout0_rptr1[1:0]), | |
| 634 | .l1clk(l1clk), | |
| 635 | .siclk(siclk), | |
| 636 | .soclk(soclk)); | |
| 637 | ||
| 638 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr2 ( | |
| 639 | .scan_in(ff0_rptr2_scanin), | |
| 640 | .scan_out(ff0_rptr2_scanout), | |
| 641 | .din(fdout0_rptr2_in[1:0]), | |
| 642 | .dout(fdout0_rptr2[1:0]), | |
| 643 | .l1clk(l1clk), | |
| 644 | .siclk(siclk), | |
| 645 | .soclk(soclk)); | |
| 646 | ||
| 647 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr3 ( | |
| 648 | .scan_in(ff0_rptr3_scanin), | |
| 649 | .scan_out(ff0_rptr3_scanout), | |
| 650 | .din(fdout0_rptr3_in[1:0]), | |
| 651 | .dout(fdout0_rptr3[1:0]), | |
| 652 | .l1clk(l1clk), | |
| 653 | .siclk(siclk), | |
| 654 | .soclk(soclk)); | |
| 655 | ||
| 656 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr4 ( | |
| 657 | .scan_in(ff0_rptr4_scanin), | |
| 658 | .scan_out(ff0_rptr4_scanout), | |
| 659 | .din(fdout0_rptr4_in[1:0]), | |
| 660 | .dout(fdout0_rptr4[1:0]), | |
| 661 | .l1clk(l1clk), | |
| 662 | .siclk(siclk), | |
| 663 | .soclk(soclk)); | |
| 664 | ||
| 665 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr5 ( | |
| 666 | .scan_in(ff0_rptr5_scanin), | |
| 667 | .scan_out(ff0_rptr5_scanout), | |
| 668 | .din(fdout0_rptr5_in[1:0]), | |
| 669 | .dout(fdout0_rptr5[1:0]), | |
| 670 | .l1clk(l1clk), | |
| 671 | .siclk(siclk), | |
| 672 | .soclk(soclk)); | |
| 673 | ||
| 674 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr6 ( | |
| 675 | .scan_in(ff0_rptr6_scanin), | |
| 676 | .scan_out(ff0_rptr6_scanout), | |
| 677 | .din(fdout0_rptr6_in[1:0]), | |
| 678 | .dout(fdout0_rptr6[1:0]), | |
| 679 | .l1clk(l1clk), | |
| 680 | .siclk(siclk), | |
| 681 | .soclk(soclk)); | |
| 682 | ||
| 683 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr7 ( | |
| 684 | .scan_in(ff0_rptr7_scanin), | |
| 685 | .scan_out(ff0_rptr7_scanout), | |
| 686 | .din(fdout0_rptr7_in[1:0]), | |
| 687 | .dout(fdout0_rptr7[1:0]), | |
| 688 | .l1clk(l1clk), | |
| 689 | .siclk(siclk), | |
| 690 | .soclk(soclk)); | |
| 691 | ||
| 692 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr8 ( | |
| 693 | .scan_in(ff0_rptr8_scanin), | |
| 694 | .scan_out(ff0_rptr8_scanout), | |
| 695 | .din(fdout0_rptr8_in[1:0]), | |
| 696 | .dout(fdout0_rptr8[1:0]), | |
| 697 | .l1clk(l1clk), | |
| 698 | .siclk(siclk), | |
| 699 | .soclk(soclk)); | |
| 700 | ||
| 701 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr9 ( | |
| 702 | .scan_in(ff0_rptr9_scanin), | |
| 703 | .scan_out(ff0_rptr9_scanout), | |
| 704 | .din(fdout0_rptr9_in[1:0]), | |
| 705 | .dout(fdout0_rptr9[1:0]), | |
| 706 | .l1clk(l1clk), | |
| 707 | .siclk(siclk), | |
| 708 | .soclk(soclk)); | |
| 709 | ||
| 710 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr10 ( | |
| 711 | .scan_in(ff0_rptr10_scanin), | |
| 712 | .scan_out(ff0_rptr10_scanout), | |
| 713 | .din(fdout0_rptr10_in[1:0]), | |
| 714 | .dout(fdout0_rptr10[1:0]), | |
| 715 | .l1clk(l1clk), | |
| 716 | .siclk(siclk), | |
| 717 | .soclk(soclk)); | |
| 718 | ||
| 719 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr11 ( | |
| 720 | .scan_in(ff0_rptr11_scanin), | |
| 721 | .scan_out(ff0_rptr11_scanout), | |
| 722 | .din(fdout0_rptr11_in[1:0]), | |
| 723 | .dout(fdout0_rptr11[1:0]), | |
| 724 | .l1clk(l1clk), | |
| 725 | .siclk(siclk), | |
| 726 | .soclk(soclk)); | |
| 727 | ||
| 728 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr12 ( | |
| 729 | .scan_in(ff0_rptr12_scanin), | |
| 730 | .scan_out(ff0_rptr12_scanout), | |
| 731 | .din(fdout0_rptr12_in[1:0]), | |
| 732 | .dout(fdout0_rptr12[1:0]), | |
| 733 | .l1clk(l1clk), | |
| 734 | .siclk(siclk), | |
| 735 | .soclk(soclk)); | |
| 736 | ||
| 737 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff0_rptr13 ( | |
| 738 | .scan_in(ff0_rptr13_scanin), | |
| 739 | .scan_out(ff0_rptr13_scanout), | |
| 740 | .din(fdout0_rptr13_in[1:0]), | |
| 741 | .dout(fdout0_rptr13[1:0]), | |
| 742 | .l1clk(l1clk), | |
| 743 | .siclk(siclk), | |
| 744 | .soclk(soclk)); | |
| 745 | ||
| 746 | // ------------------------------------------- | |
| 747 | ||
| 748 | assign fdout1_rptr0_in[1:0] = {fdout1_rptr0[0],~fdout1_rptr0[1]} & {2{fdout1_frame_lock_sync[0]}}; | |
| 749 | assign fdout1_rptr1_in[1:0] = {fdout1_rptr1[0],~fdout1_rptr1[1]} & {2{fdout1_frame_lock_sync[1]}}; | |
| 750 | assign fdout1_rptr2_in[1:0] = {fdout1_rptr2[0],~fdout1_rptr2[1]} & {2{fdout1_frame_lock_sync[2]}}; | |
| 751 | assign fdout1_rptr3_in[1:0] = {fdout1_rptr3[0],~fdout1_rptr3[1]} & {2{fdout1_frame_lock_sync[3]}}; | |
| 752 | assign fdout1_rptr4_in[1:0] = {fdout1_rptr4[0],~fdout1_rptr4[1]} & {2{fdout1_frame_lock_sync[4]}}; | |
| 753 | assign fdout1_rptr5_in[1:0] = {fdout1_rptr5[0],~fdout1_rptr5[1]} & {2{fdout1_frame_lock_sync[5]}}; | |
| 754 | assign fdout1_rptr6_in[1:0] = {fdout1_rptr6[0],~fdout1_rptr6[1]} & {2{fdout1_frame_lock_sync[6]}}; | |
| 755 | assign fdout1_rptr7_in[1:0] = {fdout1_rptr7[0],~fdout1_rptr7[1]} & {2{fdout1_frame_lock_sync[7]}}; | |
| 756 | assign fdout1_rptr8_in[1:0] = {fdout1_rptr8[0],~fdout1_rptr8[1]} & {2{fdout1_frame_lock_sync[8]}}; | |
| 757 | assign fdout1_rptr9_in[1:0] = {fdout1_rptr9[0],~fdout1_rptr9[1]} & {2{fdout1_frame_lock_sync[9]}}; | |
| 758 | assign fdout1_rptr10_in[1:0] = {fdout1_rptr10[0],~fdout1_rptr10[1]} & {2{fdout1_frame_lock_sync[10]}}; | |
| 759 | assign fdout1_rptr11_in[1:0] = {fdout1_rptr11[0],~fdout1_rptr11[1]} & {2{fdout1_frame_lock_sync[11]}}; | |
| 760 | assign fdout1_rptr12_in[1:0] = {fdout1_rptr12[0],~fdout1_rptr12[1]} & {2{fdout1_frame_lock_sync[12]}}; | |
| 761 | assign fdout1_rptr13_in[1:0] = {fdout1_rptr13[0],~fdout1_rptr13[1]} & {2{fdout1_frame_lock_sync[13]}}; | |
| 762 | ||
| 763 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr0 ( | |
| 764 | .scan_in(ff1_rptr0_scanin), | |
| 765 | .scan_out(ff1_rptr0_scanout), | |
| 766 | .din(fdout1_rptr0_in[1:0]), | |
| 767 | .dout(fdout1_rptr0[1:0]), | |
| 768 | .l1clk(l1clk), | |
| 769 | .siclk(siclk), | |
| 770 | .soclk(soclk)); | |
| 771 | ||
| 772 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr1 ( | |
| 773 | .scan_in(ff1_rptr1_scanin), | |
| 774 | .scan_out(ff1_rptr1_scanout), | |
| 775 | .din(fdout1_rptr1_in[1:0]), | |
| 776 | .dout(fdout1_rptr1[1:0]), | |
| 777 | .l1clk(l1clk), | |
| 778 | .siclk(siclk), | |
| 779 | .soclk(soclk)); | |
| 780 | ||
| 781 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr2 ( | |
| 782 | .scan_in(ff1_rptr2_scanin), | |
| 783 | .scan_out(ff1_rptr2_scanout), | |
| 784 | .din(fdout1_rptr2_in[1:0]), | |
| 785 | .dout(fdout1_rptr2[1:0]), | |
| 786 | .l1clk(l1clk), | |
| 787 | .siclk(siclk), | |
| 788 | .soclk(soclk)); | |
| 789 | ||
| 790 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr3 ( | |
| 791 | .scan_in(ff1_rptr3_scanin), | |
| 792 | .scan_out(ff1_rptr3_scanout), | |
| 793 | .din(fdout1_rptr3_in[1:0]), | |
| 794 | .dout(fdout1_rptr3[1:0]), | |
| 795 | .l1clk(l1clk), | |
| 796 | .siclk(siclk), | |
| 797 | .soclk(soclk)); | |
| 798 | ||
| 799 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr4 ( | |
| 800 | .scan_in(ff1_rptr4_scanin), | |
| 801 | .scan_out(ff1_rptr4_scanout), | |
| 802 | .din(fdout1_rptr4_in[1:0]), | |
| 803 | .dout(fdout1_rptr4[1:0]), | |
| 804 | .l1clk(l1clk), | |
| 805 | .siclk(siclk), | |
| 806 | .soclk(soclk)); | |
| 807 | ||
| 808 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr5 ( | |
| 809 | .scan_in(ff1_rptr5_scanin), | |
| 810 | .scan_out(ff1_rptr5_scanout), | |
| 811 | .din(fdout1_rptr5_in[1:0]), | |
| 812 | .dout(fdout1_rptr5[1:0]), | |
| 813 | .l1clk(l1clk), | |
| 814 | .siclk(siclk), | |
| 815 | .soclk(soclk)); | |
| 816 | ||
| 817 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr6 ( | |
| 818 | .scan_in(ff1_rptr6_scanin), | |
| 819 | .scan_out(ff1_rptr6_scanout), | |
| 820 | .din(fdout1_rptr6_in[1:0]), | |
| 821 | .dout(fdout1_rptr6[1:0]), | |
| 822 | .l1clk(l1clk), | |
| 823 | .siclk(siclk), | |
| 824 | .soclk(soclk)); | |
| 825 | ||
| 826 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr7 ( | |
| 827 | .scan_in(ff1_rptr7_scanin), | |
| 828 | .scan_out(ff1_rptr7_scanout), | |
| 829 | .din(fdout1_rptr7_in[1:0]), | |
| 830 | .dout(fdout1_rptr7[1:0]), | |
| 831 | .l1clk(l1clk), | |
| 832 | .siclk(siclk), | |
| 833 | .soclk(soclk)); | |
| 834 | ||
| 835 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr8 ( | |
| 836 | .scan_in(ff1_rptr8_scanin), | |
| 837 | .scan_out(ff1_rptr8_scanout), | |
| 838 | .din(fdout1_rptr8_in[1:0]), | |
| 839 | .dout(fdout1_rptr8[1:0]), | |
| 840 | .l1clk(l1clk), | |
| 841 | .siclk(siclk), | |
| 842 | .soclk(soclk)); | |
| 843 | ||
| 844 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr9 ( | |
| 845 | .scan_in(ff1_rptr9_scanin), | |
| 846 | .scan_out(ff1_rptr9_scanout), | |
| 847 | .din(fdout1_rptr9_in[1:0]), | |
| 848 | .dout(fdout1_rptr9[1:0]), | |
| 849 | .l1clk(l1clk), | |
| 850 | .siclk(siclk), | |
| 851 | .soclk(soclk)); | |
| 852 | ||
| 853 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr10 ( | |
| 854 | .scan_in(ff1_rptr10_scanin), | |
| 855 | .scan_out(ff1_rptr10_scanout), | |
| 856 | .din(fdout1_rptr10_in[1:0]), | |
| 857 | .dout(fdout1_rptr10[1:0]), | |
| 858 | .l1clk(l1clk), | |
| 859 | .siclk(siclk), | |
| 860 | .soclk(soclk)); | |
| 861 | ||
| 862 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr11 ( | |
| 863 | .scan_in(ff1_rptr11_scanin), | |
| 864 | .scan_out(ff1_rptr11_scanout), | |
| 865 | .din(fdout1_rptr11_in[1:0]), | |
| 866 | .dout(fdout1_rptr11[1:0]), | |
| 867 | .l1clk(l1clk), | |
| 868 | .siclk(siclk), | |
| 869 | .soclk(soclk)); | |
| 870 | ||
| 871 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr12 ( | |
| 872 | .scan_in(ff1_rptr12_scanin), | |
| 873 | .scan_out(ff1_rptr12_scanout), | |
| 874 | .din(fdout1_rptr12_in[1:0]), | |
| 875 | .dout(fdout1_rptr12[1:0]), | |
| 876 | .l1clk(l1clk), | |
| 877 | .siclk(siclk), | |
| 878 | .soclk(soclk)); | |
| 879 | ||
| 880 | mcu_fdoklu_ctl_msff_ctl_macro__width_2 ff1_rptr13 ( | |
| 881 | .scan_in(ff1_rptr13_scanin), | |
| 882 | .scan_out(ff1_rptr13_scanout), | |
| 883 | .din(fdout1_rptr13_in[1:0]), | |
| 884 | .dout(fdout1_rptr13[1:0]), | |
| 885 | .l1clk(l1clk), | |
| 886 | .siclk(siclk), | |
| 887 | .soclk(soclk)); | |
| 888 | ||
| 889 | // LFSR | |
| 890 | assign fdout_idle_lfsr_in[11:0] = fbdic_idle_lfsr_reset ? 12'h001 : | |
| 891 | {fdout_idle_lfsr[7] ^ fdout_idle_lfsr[4] ^ fdout_idle_lfsr[3] ^ fdout_idle_lfsr[0], fdout_idle_lfsr[11:1]}; | |
| 892 | ||
| 893 | mcu_fdoklu_ctl_msff_ctl_macro__width_12 ff_idle_lfsr ( | |
| 894 | .scan_in(ff_idle_lfsr_scanin), | |
| 895 | .scan_out(ff_idle_lfsr_scanout), | |
| 896 | .din(fdout_idle_lfsr_in[11:0]), | |
| 897 | .dout(fdout_idle_lfsr[11:0]), | |
| 898 | .l1clk(l1clk), | |
| 899 | .siclk(siclk), | |
| 900 | .soclk(soclk)); | |
| 901 | ||
| 902 | mcu_fdoklu_ctl_spare_ctl_macro__num_2 spares ( | |
| 903 | .scan_in(spares_scanin), | |
| 904 | .scan_out(spares_scanout), | |
| 905 | .l1clk(l1clk), | |
| 906 | .siclk(siclk), | |
| 907 | .soclk(soclk) | |
| 908 | ); | |
| 909 | ||
| 910 | assign fdout_idle_lfsr_l_0 = ~fdout_idle_lfsr[0]; | |
| 911 | ||
| 912 | assign ff_link_cnt_scanin = scan_in ; | |
| 913 | assign ff_link_cnt_eq_0_d1_scanin = ff_link_cnt_scanout ; | |
| 914 | assign sync_fbd0_framelock0_scanin = ff_link_cnt_eq_0_d1_scanout ; | |
| 915 | assign sync_fbd0_framelock1_scanin = sync_fbd0_framelock0_scanout; | |
| 916 | assign sync_fbd0_framelock2_scanin = sync_fbd0_framelock1_scanout; | |
| 917 | assign sync_fbd0_framelock3_scanin = sync_fbd0_framelock2_scanout; | |
| 918 | assign sync_fbd0_framelock4_scanin = sync_fbd0_framelock3_scanout; | |
| 919 | assign sync_fbd0_framelock5_scanin = sync_fbd0_framelock4_scanout; | |
| 920 | assign sync_fbd0_framelock6_scanin = sync_fbd0_framelock5_scanout; | |
| 921 | assign sync_fbd0_framelock7_scanin = sync_fbd0_framelock6_scanout; | |
| 922 | assign sync_fbd0_framelock8_scanin = sync_fbd0_framelock7_scanout; | |
| 923 | assign sync_fbd0_framelock9_scanin = sync_fbd0_framelock8_scanout; | |
| 924 | assign sync_fbd0_framelock10_scanin = sync_fbd0_framelock9_scanout; | |
| 925 | assign sync_fbd0_framelock11_scanin = sync_fbd0_framelock10_scanout; | |
| 926 | assign sync_fbd0_framelock12_scanin = sync_fbd0_framelock11_scanout; | |
| 927 | assign sync_fbd0_framelock13_scanin = sync_fbd0_framelock12_scanout; | |
| 928 | assign sync_fbd1_framelock0_scanin = sync_fbd0_framelock13_scanout; | |
| 929 | assign sync_fbd1_framelock1_scanin = sync_fbd1_framelock0_scanout; | |
| 930 | assign sync_fbd1_framelock2_scanin = sync_fbd1_framelock1_scanout; | |
| 931 | assign sync_fbd1_framelock3_scanin = sync_fbd1_framelock2_scanout; | |
| 932 | assign sync_fbd1_framelock4_scanin = sync_fbd1_framelock3_scanout; | |
| 933 | assign sync_fbd1_framelock5_scanin = sync_fbd1_framelock4_scanout; | |
| 934 | assign sync_fbd1_framelock6_scanin = sync_fbd1_framelock5_scanout; | |
| 935 | assign sync_fbd1_framelock7_scanin = sync_fbd1_framelock6_scanout; | |
| 936 | assign sync_fbd1_framelock8_scanin = sync_fbd1_framelock7_scanout; | |
| 937 | assign sync_fbd1_framelock9_scanin = sync_fbd1_framelock8_scanout; | |
| 938 | assign sync_fbd1_framelock10_scanin = sync_fbd1_framelock9_scanout; | |
| 939 | assign sync_fbd1_framelock11_scanin = sync_fbd1_framelock10_scanout; | |
| 940 | assign sync_fbd1_framelock12_scanin = sync_fbd1_framelock11_scanout; | |
| 941 | assign sync_fbd1_framelock13_scanin = sync_fbd1_framelock12_scanout; | |
| 942 | assign ff0_rptr0_scanin = sync_fbd1_framelock13_scanout; | |
| 943 | assign ff0_rptr1_scanin = ff0_rptr0_scanout ; | |
| 944 | assign ff0_rptr2_scanin = ff0_rptr1_scanout ; | |
| 945 | assign ff0_rptr3_scanin = ff0_rptr2_scanout ; | |
| 946 | assign ff0_rptr4_scanin = ff0_rptr3_scanout ; | |
| 947 | assign ff0_rptr5_scanin = ff0_rptr4_scanout ; | |
| 948 | assign ff0_rptr6_scanin = ff0_rptr5_scanout ; | |
| 949 | assign ff0_rptr7_scanin = ff0_rptr6_scanout ; | |
| 950 | assign ff0_rptr8_scanin = ff0_rptr7_scanout ; | |
| 951 | assign ff0_rptr9_scanin = ff0_rptr8_scanout ; | |
| 952 | assign ff0_rptr10_scanin = ff0_rptr9_scanout ; | |
| 953 | assign ff0_rptr11_scanin = ff0_rptr10_scanout ; | |
| 954 | assign ff0_rptr12_scanin = ff0_rptr11_scanout ; | |
| 955 | assign ff0_rptr13_scanin = ff0_rptr12_scanout ; | |
| 956 | assign ff1_rptr0_scanin = ff0_rptr13_scanout ; | |
| 957 | assign ff1_rptr1_scanin = ff1_rptr0_scanout ; | |
| 958 | assign ff1_rptr2_scanin = ff1_rptr1_scanout ; | |
| 959 | assign ff1_rptr3_scanin = ff1_rptr2_scanout ; | |
| 960 | assign ff1_rptr4_scanin = ff1_rptr3_scanout ; | |
| 961 | assign ff1_rptr5_scanin = ff1_rptr4_scanout ; | |
| 962 | assign ff1_rptr6_scanin = ff1_rptr5_scanout ; | |
| 963 | assign ff1_rptr7_scanin = ff1_rptr6_scanout ; | |
| 964 | assign ff1_rptr8_scanin = ff1_rptr7_scanout ; | |
| 965 | assign ff1_rptr9_scanin = ff1_rptr8_scanout ; | |
| 966 | assign ff1_rptr10_scanin = ff1_rptr9_scanout ; | |
| 967 | assign ff1_rptr11_scanin = ff1_rptr10_scanout ; | |
| 968 | assign ff1_rptr12_scanin = ff1_rptr11_scanout ; | |
| 969 | assign ff1_rptr13_scanin = ff1_rptr12_scanout ; | |
| 970 | assign ff_idle_lfsr_scanin = ff1_rptr13_scanout ; | |
| 971 | assign spares_scanin = ff_idle_lfsr_scanout ; | |
| 972 | assign scan_out = tcu_mcu_testmode ? spares_scanout : scan_in ; | |
| 973 | ||
| 974 | endmodule | |
| 975 | ||
| 976 | ||
| 977 | ||
| 978 | ||
| 979 | ||
| 980 | ||
| 981 | // any PARAMS parms go into naming of macro | |
| 982 | ||
| 983 | module mcu_fdoklu_ctl_l1clkhdr_ctl_macro ( | |
| 984 | l2clk, | |
| 985 | l1en, | |
| 986 | pce_ov, | |
| 987 | stop, | |
| 988 | se, | |
| 989 | l1clk); | |
| 990 | ||
| 991 | ||
| 992 | input l2clk; | |
| 993 | input l1en; | |
| 994 | input pce_ov; | |
| 995 | input stop; | |
| 996 | input se; | |
| 997 | output l1clk; | |
| 998 | ||
| 999 | ||
| 1000 | ||
| 1001 | ||
| 1002 | ||
| 1003 | cl_sc1_l1hdr_8x c_0 ( | |
| 1004 | ||
| 1005 | ||
| 1006 | .l2clk(l2clk), | |
| 1007 | .pce(l1en), | |
| 1008 | .l1clk(l1clk), | |
| 1009 | .se(se), | |
| 1010 | .pce_ov(pce_ov), | |
| 1011 | .stop(stop) | |
| 1012 | ); | |
| 1013 | ||
| 1014 | ||
| 1015 | ||
| 1016 | endmodule | |
| 1017 | ||
| 1018 | ||
| 1019 | ||
| 1020 | ||
| 1021 | ||
| 1022 | ||
| 1023 | ||
| 1024 | ||
| 1025 | ||
| 1026 | ||
| 1027 | ||
| 1028 | ||
| 1029 | ||
| 1030 | // any PARAMS parms go into naming of macro | |
| 1031 | ||
| 1032 | module mcu_fdoklu_ctl_msff_ctl_macro__width_6 ( | |
| 1033 | din, | |
| 1034 | l1clk, | |
| 1035 | scan_in, | |
| 1036 | siclk, | |
| 1037 | soclk, | |
| 1038 | dout, | |
| 1039 | scan_out); | |
| 1040 | wire [5:0] fdin; | |
| 1041 | wire [4:0] so; | |
| 1042 | ||
| 1043 | input [5:0] din; | |
| 1044 | input l1clk; | |
| 1045 | input scan_in; | |
| 1046 | ||
| 1047 | ||
| 1048 | input siclk; | |
| 1049 | input soclk; | |
| 1050 | ||
| 1051 | output [5:0] dout; | |
| 1052 | output scan_out; | |
| 1053 | assign fdin[5:0] = din[5:0]; | |
| 1054 | ||
| 1055 | ||
| 1056 | ||
| 1057 | ||
| 1058 | ||
| 1059 | ||
| 1060 | dff #(6) d0_0 ( | |
| 1061 | .l1clk(l1clk), | |
| 1062 | .siclk(siclk), | |
| 1063 | .soclk(soclk), | |
| 1064 | .d(fdin[5:0]), | |
| 1065 | .si({scan_in,so[4:0]}), | |
| 1066 | .so({so[4:0],scan_out}), | |
| 1067 | .q(dout[5:0]) | |
| 1068 | ); | |
| 1069 | ||
| 1070 | ||
| 1071 | ||
| 1072 | ||
| 1073 | ||
| 1074 | ||
| 1075 | ||
| 1076 | ||
| 1077 | ||
| 1078 | ||
| 1079 | ||
| 1080 | ||
| 1081 | endmodule | |
| 1082 | ||
| 1083 | ||
| 1084 | ||
| 1085 | ||
| 1086 | ||
| 1087 | ||
| 1088 | ||
| 1089 | ||
| 1090 | ||
| 1091 | ||
| 1092 | ||
| 1093 | ||
| 1094 | ||
| 1095 | // any PARAMS parms go into naming of macro | |
| 1096 | ||
| 1097 | module mcu_fdoklu_ctl_msff_ctl_macro ( | |
| 1098 | din, | |
| 1099 | l1clk, | |
| 1100 | scan_in, | |
| 1101 | siclk, | |
| 1102 | soclk, | |
| 1103 | dout, | |
| 1104 | scan_out); | |
| 1105 | wire [0:0] fdin; | |
| 1106 | ||
| 1107 | input [0:0] din; | |
| 1108 | input l1clk; | |
| 1109 | input scan_in; | |
| 1110 | ||
| 1111 | ||
| 1112 | input siclk; | |
| 1113 | input soclk; | |
| 1114 | ||
| 1115 | output [0:0] dout; | |
| 1116 | output scan_out; | |
| 1117 | assign fdin[0:0] = din[0:0]; | |
| 1118 | ||
| 1119 | ||
| 1120 | ||
| 1121 | ||
| 1122 | ||
| 1123 | ||
| 1124 | dff #(1) d0_0 ( | |
| 1125 | .l1clk(l1clk), | |
| 1126 | .siclk(siclk), | |
| 1127 | .soclk(soclk), | |
| 1128 | .d(fdin[0:0]), | |
| 1129 | .si(scan_in), | |
| 1130 | .so(scan_out), | |
| 1131 | .q(dout[0:0]) | |
| 1132 | ); | |
| 1133 | ||
| 1134 | ||
| 1135 | ||
| 1136 | ||
| 1137 | ||
| 1138 | ||
| 1139 | ||
| 1140 | ||
| 1141 | ||
| 1142 | ||
| 1143 | ||
| 1144 | ||
| 1145 | endmodule | |
| 1146 | ||
| 1147 | ||
| 1148 | ||
| 1149 | ||
| 1150 | ||
| 1151 | ||
| 1152 | ||
| 1153 | ||
| 1154 | ||
| 1155 | ||
| 1156 | ||
| 1157 | ||
| 1158 | ||
| 1159 | // any PARAMS parms go into naming of macro | |
| 1160 | ||
| 1161 | module mcu_fdoklu_ctl_msff_ctl_macro__width_2 ( | |
| 1162 | din, | |
| 1163 | l1clk, | |
| 1164 | scan_in, | |
| 1165 | siclk, | |
| 1166 | soclk, | |
| 1167 | dout, | |
| 1168 | scan_out); | |
| 1169 | wire [1:0] fdin; | |
| 1170 | wire [0:0] so; | |
| 1171 | ||
| 1172 | input [1:0] din; | |
| 1173 | input l1clk; | |
| 1174 | input scan_in; | |
| 1175 | ||
| 1176 | ||
| 1177 | input siclk; | |
| 1178 | input soclk; | |
| 1179 | ||
| 1180 | output [1:0] dout; | |
| 1181 | output scan_out; | |
| 1182 | assign fdin[1:0] = din[1:0]; | |
| 1183 | ||
| 1184 | ||
| 1185 | ||
| 1186 | ||
| 1187 | ||
| 1188 | ||
| 1189 | dff #(2) d0_0 ( | |
| 1190 | .l1clk(l1clk), | |
| 1191 | .siclk(siclk), | |
| 1192 | .soclk(soclk), | |
| 1193 | .d(fdin[1:0]), | |
| 1194 | .si({scan_in,so[0:0]}), | |
| 1195 | .so({so[0:0],scan_out}), | |
| 1196 | .q(dout[1:0]) | |
| 1197 | ); | |
| 1198 | ||
| 1199 | ||
| 1200 | ||
| 1201 | ||
| 1202 | ||
| 1203 | ||
| 1204 | ||
| 1205 | ||
| 1206 | ||
| 1207 | ||
| 1208 | ||
| 1209 | ||
| 1210 | endmodule | |
| 1211 | ||
| 1212 | ||
| 1213 | ||
| 1214 | ||
| 1215 | ||
| 1216 | ||
| 1217 | ||
| 1218 | ||
| 1219 | ||
| 1220 | ||
| 1221 | ||
| 1222 | ||
| 1223 | ||
| 1224 | // any PARAMS parms go into naming of macro | |
| 1225 | ||
| 1226 | module mcu_fdoklu_ctl_msff_ctl_macro__width_12 ( | |
| 1227 | din, | |
| 1228 | l1clk, | |
| 1229 | scan_in, | |
| 1230 | siclk, | |
| 1231 | soclk, | |
| 1232 | dout, | |
| 1233 | scan_out); | |
| 1234 | wire [11:0] fdin; | |
| 1235 | wire [10:0] so; | |
| 1236 | ||
| 1237 | input [11:0] din; | |
| 1238 | input l1clk; | |
| 1239 | input scan_in; | |
| 1240 | ||
| 1241 | ||
| 1242 | input siclk; | |
| 1243 | input soclk; | |
| 1244 | ||
| 1245 | output [11:0] dout; | |
| 1246 | output scan_out; | |
| 1247 | assign fdin[11:0] = din[11:0]; | |
| 1248 | ||
| 1249 | ||
| 1250 | ||
| 1251 | ||
| 1252 | ||
| 1253 | ||
| 1254 | dff #(12) d0_0 ( | |
| 1255 | .l1clk(l1clk), | |
| 1256 | .siclk(siclk), | |
| 1257 | .soclk(soclk), | |
| 1258 | .d(fdin[11:0]), | |
| 1259 | .si({scan_in,so[10:0]}), | |
| 1260 | .so({so[10:0],scan_out}), | |
| 1261 | .q(dout[11:0]) | |
| 1262 | ); | |
| 1263 | ||
| 1264 | ||
| 1265 | ||
| 1266 | ||
| 1267 | ||
| 1268 | ||
| 1269 | ||
| 1270 | ||
| 1271 | ||
| 1272 | ||
| 1273 | ||
| 1274 | ||
| 1275 | endmodule | |
| 1276 | ||
| 1277 | ||
| 1278 | ||
| 1279 | ||
| 1280 | ||
| 1281 | ||
| 1282 | ||
| 1283 | ||
| 1284 | ||
| 1285 | // Description: Spare gate macro for control blocks | |
| 1286 | // | |
| 1287 | // Param num controls the number of times the macro is added | |
| 1288 | // flops=0 can be used to use only combination spare logic | |
| 1289 | ||
| 1290 | ||
| 1291 | module mcu_fdoklu_ctl_spare_ctl_macro__num_2 ( | |
| 1292 | l1clk, | |
| 1293 | scan_in, | |
| 1294 | siclk, | |
| 1295 | soclk, | |
| 1296 | scan_out); | |
| 1297 | wire si_0; | |
| 1298 | wire so_0; | |
| 1299 | wire spare0_flop_unused; | |
| 1300 | wire spare0_buf_32x_unused; | |
| 1301 | wire spare0_nand3_8x_unused; | |
| 1302 | wire spare0_inv_8x_unused; | |
| 1303 | wire spare0_aoi22_4x_unused; | |
| 1304 | wire spare0_buf_8x_unused; | |
| 1305 | wire spare0_oai22_4x_unused; | |
| 1306 | wire spare0_inv_16x_unused; | |
| 1307 | wire spare0_nand2_16x_unused; | |
| 1308 | wire spare0_nor3_4x_unused; | |
| 1309 | wire spare0_nand2_8x_unused; | |
| 1310 | wire spare0_buf_16x_unused; | |
| 1311 | wire spare0_nor2_16x_unused; | |
| 1312 | wire spare0_inv_32x_unused; | |
| 1313 | wire si_1; | |
| 1314 | wire so_1; | |
| 1315 | wire spare1_flop_unused; | |
| 1316 | wire spare1_buf_32x_unused; | |
| 1317 | wire spare1_nand3_8x_unused; | |
| 1318 | wire spare1_inv_8x_unused; | |
| 1319 | wire spare1_aoi22_4x_unused; | |
| 1320 | wire spare1_buf_8x_unused; | |
| 1321 | wire spare1_oai22_4x_unused; | |
| 1322 | wire spare1_inv_16x_unused; | |
| 1323 | wire spare1_nand2_16x_unused; | |
| 1324 | wire spare1_nor3_4x_unused; | |
| 1325 | wire spare1_nand2_8x_unused; | |
| 1326 | wire spare1_buf_16x_unused; | |
| 1327 | wire spare1_nor2_16x_unused; | |
| 1328 | wire spare1_inv_32x_unused; | |
| 1329 | ||
| 1330 | ||
| 1331 | input l1clk; | |
| 1332 | input scan_in; | |
| 1333 | input siclk; | |
| 1334 | input soclk; | |
| 1335 | output scan_out; | |
| 1336 | ||
| 1337 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
| 1338 | .siclk(siclk), | |
| 1339 | .soclk(soclk), | |
| 1340 | .si(si_0), | |
| 1341 | .so(so_0), | |
| 1342 | .d(1'b0), | |
| 1343 | .q(spare0_flop_unused)); | |
| 1344 | assign si_0 = scan_in; | |
| 1345 | ||
| 1346 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
| 1347 | .out(spare0_buf_32x_unused)); | |
| 1348 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
| 1349 | .in1(1'b1), | |
| 1350 | .in2(1'b1), | |
| 1351 | .out(spare0_nand3_8x_unused)); | |
| 1352 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
| 1353 | .out(spare0_inv_8x_unused)); | |
| 1354 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
| 1355 | .in01(1'b1), | |
| 1356 | .in10(1'b1), | |
| 1357 | .in11(1'b1), | |
| 1358 | .out(spare0_aoi22_4x_unused)); | |
| 1359 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
| 1360 | .out(spare0_buf_8x_unused)); | |
| 1361 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
| 1362 | .in01(1'b1), | |
| 1363 | .in10(1'b1), | |
| 1364 | .in11(1'b1), | |
| 1365 | .out(spare0_oai22_4x_unused)); | |
| 1366 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
| 1367 | .out(spare0_inv_16x_unused)); | |
| 1368 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
| 1369 | .in1(1'b1), | |
| 1370 | .out(spare0_nand2_16x_unused)); | |
| 1371 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
| 1372 | .in1(1'b0), | |
| 1373 | .in2(1'b0), | |
| 1374 | .out(spare0_nor3_4x_unused)); | |
| 1375 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
| 1376 | .in1(1'b1), | |
| 1377 | .out(spare0_nand2_8x_unused)); | |
| 1378 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
| 1379 | .out(spare0_buf_16x_unused)); | |
| 1380 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
| 1381 | .in1(1'b0), | |
| 1382 | .out(spare0_nor2_16x_unused)); | |
| 1383 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
| 1384 | .out(spare0_inv_32x_unused)); | |
| 1385 | ||
| 1386 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
| 1387 | .siclk(siclk), | |
| 1388 | .soclk(soclk), | |
| 1389 | .si(si_1), | |
| 1390 | .so(so_1), | |
| 1391 | .d(1'b0), | |
| 1392 | .q(spare1_flop_unused)); | |
| 1393 | assign si_1 = so_0; | |
| 1394 | ||
| 1395 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
| 1396 | .out(spare1_buf_32x_unused)); | |
| 1397 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
| 1398 | .in1(1'b1), | |
| 1399 | .in2(1'b1), | |
| 1400 | .out(spare1_nand3_8x_unused)); | |
| 1401 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
| 1402 | .out(spare1_inv_8x_unused)); | |
| 1403 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
| 1404 | .in01(1'b1), | |
| 1405 | .in10(1'b1), | |
| 1406 | .in11(1'b1), | |
| 1407 | .out(spare1_aoi22_4x_unused)); | |
| 1408 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
| 1409 | .out(spare1_buf_8x_unused)); | |
| 1410 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
| 1411 | .in01(1'b1), | |
| 1412 | .in10(1'b1), | |
| 1413 | .in11(1'b1), | |
| 1414 | .out(spare1_oai22_4x_unused)); | |
| 1415 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
| 1416 | .out(spare1_inv_16x_unused)); | |
| 1417 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
| 1418 | .in1(1'b1), | |
| 1419 | .out(spare1_nand2_16x_unused)); | |
| 1420 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
| 1421 | .in1(1'b0), | |
| 1422 | .in2(1'b0), | |
| 1423 | .out(spare1_nor3_4x_unused)); | |
| 1424 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
| 1425 | .in1(1'b1), | |
| 1426 | .out(spare1_nand2_8x_unused)); | |
| 1427 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
| 1428 | .out(spare1_buf_16x_unused)); | |
| 1429 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
| 1430 | .in1(1'b0), | |
| 1431 | .out(spare1_nor2_16x_unused)); | |
| 1432 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
| 1433 | .out(spare1_inv_32x_unused)); | |
| 1434 | assign scan_out = so_1; | |
| 1435 | ||
| 1436 | ||
| 1437 | ||
| 1438 | endmodule | |
| 1439 |