Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_fdout_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_fdout_ctl ( | |
36 | mcu_fsr0_data, | |
37 | mcu_fsr1_data, | |
38 | fbdiwr0_data, | |
39 | fbdiwr1_data, | |
40 | rdpctl_kp_lnk_up, | |
41 | fbdic_link_cnt_eq_0_d1, | |
42 | tcu_mcu_fbd_clk_stop, | |
43 | tcu_atpg_mode, | |
44 | drl2clk, | |
45 | scan_in, | |
46 | scan_out, | |
47 | tcu_aclk, | |
48 | tcu_bclk, | |
49 | tcu_scan_en, | |
50 | tcu_pce_ov, | |
51 | tcu_mcu_testmode); | |
52 | wire pce_ov; | |
53 | wire siclk; | |
54 | wire soclk; | |
55 | wire se; | |
56 | wire stop; | |
57 | wire l1clk; | |
58 | wire [119:0] fdout_link_data; | |
59 | wire fbdic_link_cnt_eq_0_d1_reg; | |
60 | wire [119:0] mcu_fsr0_data_in; | |
61 | wire ff_fsr0_data_scanin; | |
62 | wire ff_fsr0_data_scanout; | |
63 | wire [119:0] mcu_fsr1_data_in; | |
64 | wire ff_fsr1_data_scanin; | |
65 | wire ff_fsr1_data_scanout; | |
66 | wire si_0; | |
67 | wire so_0; | |
68 | wire spares_scanin; | |
69 | wire spare0_buf_32x_unused; | |
70 | wire spare0_nand3_8x_unused; | |
71 | wire spare0_inv_8x_unused; | |
72 | wire spare0_aoi22_4x_unused; | |
73 | wire spare0_buf_8x_unused; | |
74 | wire spare0_oai22_4x_unused; | |
75 | wire spare0_inv_16x_unused; | |
76 | wire spare0_nand2_16x_unused; | |
77 | wire spare0_nor3_4x_unused; | |
78 | wire spare0_nand2_8x_unused; | |
79 | wire spare0_buf_16x_unused; | |
80 | wire spare0_nor2_16x_unused; | |
81 | wire spare0_inv_32x_unused; | |
82 | wire spares_scanout; | |
83 | ||
84 | ||
85 | output [119:0] mcu_fsr0_data; | |
86 | output [119:0] mcu_fsr1_data; | |
87 | ||
88 | input [119:0] fbdiwr0_data; | |
89 | input [119:0] fbdiwr1_data; | |
90 | ||
91 | input rdpctl_kp_lnk_up; | |
92 | input fbdic_link_cnt_eq_0_d1; | |
93 | ||
94 | input tcu_mcu_fbd_clk_stop; | |
95 | input tcu_atpg_mode; | |
96 | ||
97 | input drl2clk; | |
98 | input scan_in; | |
99 | output scan_out; | |
100 | input tcu_aclk; | |
101 | input tcu_bclk; | |
102 | input tcu_scan_en; | |
103 | input tcu_pce_ov; | |
104 | input tcu_mcu_testmode; | |
105 | ||
106 | // Scan reassigns | |
107 | assign pce_ov = tcu_pce_ov; | |
108 | assign siclk = tcu_aclk & tcu_mcu_testmode; | |
109 | assign soclk = tcu_bclk & tcu_mcu_testmode; | |
110 | assign se = tcu_scan_en & tcu_mcu_testmode; | |
111 | assign stop = tcu_mcu_fbd_clk_stop & ~tcu_atpg_mode; | |
112 | ||
113 | mcu_fdout_ctl_l1clkhdr_ctl_macro clkgen ( | |
114 | .l2clk(drl2clk), | |
115 | .l1en (1'b1 ), | |
116 | .l1clk(l1clk), | |
117 | .pce_ov(pce_ov), | |
118 | .stop(stop), | |
119 | .se(se)); | |
120 | ||
121 | assign fdout_link_data[119:0] = fbdic_link_cnt_eq_0_d1_reg ? 120'h55_0aaa_557a_a455_0aa0_554a_a055_0aa0 : 120'h0; | |
122 | ||
123 | assign mcu_fsr0_data_in[119:0] = rdpctl_kp_lnk_up ? fdout_link_data[119:0] : fbdiwr0_data[119:0]; | |
124 | ||
125 | mcu_fdout_ctl_msff_ctl_macro__width_120 ff_fsr0_data ( | |
126 | .scan_in(ff_fsr0_data_scanin), | |
127 | .scan_out(ff_fsr0_data_scanout), | |
128 | .din(mcu_fsr0_data_in[119:0]), | |
129 | .dout(mcu_fsr0_data[119:0]), | |
130 | .l1clk(l1clk), | |
131 | .siclk(siclk), | |
132 | .soclk(soclk)); | |
133 | ||
134 | assign mcu_fsr1_data_in[119:0] = rdpctl_kp_lnk_up ? fdout_link_data[119:0] : fbdiwr1_data[119:0]; | |
135 | ||
136 | mcu_fdout_ctl_msff_ctl_macro__width_120 ff_fsr1_data ( | |
137 | .scan_in(ff_fsr1_data_scanin), | |
138 | .scan_out(ff_fsr1_data_scanout), | |
139 | .din(mcu_fsr1_data_in[119:0]), | |
140 | .dout(mcu_fsr1_data[119:0]), | |
141 | .l1clk(l1clk), | |
142 | .siclk(siclk), | |
143 | .soclk(soclk)); | |
144 | ||
145 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
146 | .siclk(siclk), | |
147 | .soclk(soclk), | |
148 | .si(si_0), | |
149 | .so(so_0), | |
150 | .d(fbdic_link_cnt_eq_0_d1), | |
151 | .q(fbdic_link_cnt_eq_0_d1_reg)); | |
152 | assign si_0 = spares_scanin; | |
153 | ||
154 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
155 | .out(spare0_buf_32x_unused)); | |
156 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
157 | .in1(1'b1), | |
158 | .in2(1'b1), | |
159 | .out(spare0_nand3_8x_unused)); | |
160 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
161 | .out(spare0_inv_8x_unused)); | |
162 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
163 | .in01(1'b1), | |
164 | .in10(1'b1), | |
165 | .in11(1'b1), | |
166 | .out(spare0_aoi22_4x_unused)); | |
167 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
168 | .out(spare0_buf_8x_unused)); | |
169 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
170 | .in01(1'b1), | |
171 | .in10(1'b1), | |
172 | .in11(1'b1), | |
173 | .out(spare0_oai22_4x_unused)); | |
174 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
175 | .out(spare0_inv_16x_unused)); | |
176 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
177 | .in1(1'b1), | |
178 | .out(spare0_nand2_16x_unused)); | |
179 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
180 | .in1(1'b0), | |
181 | .in2(1'b0), | |
182 | .out(spare0_nor3_4x_unused)); | |
183 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
184 | .in1(1'b1), | |
185 | .out(spare0_nand2_8x_unused)); | |
186 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
187 | .out(spare0_buf_16x_unused)); | |
188 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
189 | .in1(1'b0), | |
190 | .out(spare0_nor2_16x_unused)); | |
191 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
192 | .out(spare0_inv_32x_unused)); | |
193 | assign spares_scanout = so_0; | |
194 | ||
195 | assign ff_fsr0_data_scanin = scan_in ; | |
196 | assign ff_fsr1_data_scanin = ff_fsr0_data_scanout ; | |
197 | assign spares_scanin = ff_fsr1_data_scanout ; | |
198 | assign scan_out = tcu_mcu_testmode ? spares_scanout : scan_in ; | |
199 | ||
200 | endmodule | |
201 | ||
202 | ||
203 | ||
204 | ||
205 | ||
206 | ||
207 | // any PARAMS parms go into naming of macro | |
208 | ||
209 | module mcu_fdout_ctl_l1clkhdr_ctl_macro ( | |
210 | l2clk, | |
211 | l1en, | |
212 | pce_ov, | |
213 | stop, | |
214 | se, | |
215 | l1clk); | |
216 | ||
217 | ||
218 | input l2clk; | |
219 | input l1en; | |
220 | input pce_ov; | |
221 | input stop; | |
222 | input se; | |
223 | output l1clk; | |
224 | ||
225 | ||
226 | ||
227 | ||
228 | ||
229 | cl_sc1_l1hdr_8x c_0 ( | |
230 | ||
231 | ||
232 | .l2clk(l2clk), | |
233 | .pce(l1en), | |
234 | .l1clk(l1clk), | |
235 | .se(se), | |
236 | .pce_ov(pce_ov), | |
237 | .stop(stop) | |
238 | ); | |
239 | ||
240 | ||
241 | ||
242 | endmodule | |
243 | ||
244 | ||
245 | ||
246 | ||
247 | ||
248 | ||
249 | ||
250 | ||
251 | ||
252 | ||
253 | ||
254 | ||
255 | ||
256 | // any PARAMS parms go into naming of macro | |
257 | ||
258 | module mcu_fdout_ctl_msff_ctl_macro__width_120 ( | |
259 | din, | |
260 | l1clk, | |
261 | scan_in, | |
262 | siclk, | |
263 | soclk, | |
264 | dout, | |
265 | scan_out); | |
266 | wire [119:0] fdin; | |
267 | wire [118:0] so; | |
268 | ||
269 | input [119:0] din; | |
270 | input l1clk; | |
271 | input scan_in; | |
272 | ||
273 | ||
274 | input siclk; | |
275 | input soclk; | |
276 | ||
277 | output [119:0] dout; | |
278 | output scan_out; | |
279 | assign fdin[119:0] = din[119:0]; | |
280 | ||
281 | ||
282 | ||
283 | ||
284 | ||
285 | ||
286 | dff #(120) d0_0 ( | |
287 | .l1clk(l1clk), | |
288 | .siclk(siclk), | |
289 | .soclk(soclk), | |
290 | .d(fdin[119:0]), | |
291 | .si({scan_in,so[118:0]}), | |
292 | .so({so[118:0],scan_out}), | |
293 | .q(dout[119:0]) | |
294 | ); | |
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | ||
307 | endmodule | |
308 | ||
309 | ||
310 | ||
311 | ||
312 | ||
313 | ||
314 | ||
315 |