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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_ibtx_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define DRIF_MCU_STATE_00 5'd0 | |
36 | `define DRIF_MCU_STATE_01 5'd1 | |
37 | `define DRIF_MCU_STATE_02 5'd2 | |
38 | `define DRIF_MCU_STATE_03 5'd3 | |
39 | `define DRIF_MCU_STATE_04 5'd4 | |
40 | `define DRIF_MCU_STATE_05 5'd5 | |
41 | `define DRIF_MCU_STATE_06 5'd6 | |
42 | `define DRIF_MCU_STATE_07 5'd7 | |
43 | `define DRIF_MCU_STATE_08 5'd8 | |
44 | `define DRIF_MCU_STATE_09 5'd9 | |
45 | `define DRIF_MCU_STATE_10 5'd10 | |
46 | `define DRIF_MCU_STATE_11 5'd11 | |
47 | `define DRIF_MCU_STATE_12 5'd12 | |
48 | `define DRIF_MCU_STATE_13 5'd13 | |
49 | `define DRIF_MCU_STATE_14 5'd14 | |
50 | `define DRIF_MCU_STATE_15 5'd15 | |
51 | `define DRIF_MCU_STATE_16 5'd16 | |
52 | `define DRIF_MCU_STATE_17 5'd17 | |
53 | `define DRIF_MCU_STATE_18 5'd18 | |
54 | `define DRIF_MCU_STATE_19 5'd19 | |
55 | `define DRIF_MCU_STATE_20 5'd20 | |
56 | `define DRIF_MCU_STATE_21 5'd21 | |
57 | `define DRIF_MCU_STATE_22 5'd22 | |
58 | `define DRIF_MCU_STATE_23 5'd23 | |
59 | `define DRIF_MCU_STATE_24 5'd24 | |
60 | `define DRIF_MCU_STATE_25 5'd25 | |
61 | `define DRIF_MCU_STATE_26 5'd26 | |
62 | ||
63 | `define DRIF_MCU_STATE_MAX 4 | |
64 | `define DRIF_MCU_STATE_WIDTH 5 | |
65 | ||
66 | // | |
67 | // UCB Packet Type | |
68 | // =============== | |
69 | // | |
70 | `define UCB_READ_NACK 4'b0000 // ack/nack types | |
71 | `define UCB_READ_ACK 4'b0001 | |
72 | `define UCB_WRITE_ACK 4'b0010 | |
73 | `define UCB_IFILL_ACK 4'b0011 | |
74 | `define UCB_IFILL_NACK 4'b0111 | |
75 | ||
76 | `define UCB_READ_REQ 4'b0100 // req types | |
77 | `define UCB_WRITE_REQ 4'b0101 | |
78 | `define UCB_IFILL_REQ 4'b0110 | |
79 | ||
80 | `define UCB_INT 4'b1000 // plain interrupt | |
81 | `define UCB_INT_VEC 4'b1100 // interrupt with vector | |
82 | `define UCB_RESET_VEC 4'b1101 // reset with vector | |
83 | `define UCB_IDLE_VEC 4'b1110 // idle with vector | |
84 | `define UCB_RESUME_VEC 4'b1111 // resume with vector | |
85 | ||
86 | ||
87 | // | |
88 | // UCB Data Packet Format | |
89 | // ====================== | |
90 | // | |
91 | `define UCB_NOPAY_PKT_WIDTH 64 // packet without payload | |
92 | `define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload | |
93 | `define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload | |
94 | ||
95 | `define UCB_DATA_EXT_HI 191 // (64) extended data | |
96 | `define UCB_DATA_EXT_LO 128 | |
97 | `define UCB_DATA_HI 127 // (64) data | |
98 | `define UCB_DATA_LO 64 | |
99 | `define UCB_RSV_HI 63 // (9) reserved bits | |
100 | `define UCB_RSV_LO 55 | |
101 | `define UCB_ADDR_HI 54 // (40) bit address | |
102 | `define UCB_ADDR_LO 15 | |
103 | `define UCB_SIZE_HI 14 // (3) request size | |
104 | `define UCB_SIZE_LO 12 | |
105 | `define UCB_BUF_HI 11 // (2) buffer ID | |
106 | `define UCB_BUF_LO 10 | |
107 | `define UCB_THR_HI 9 // (6) cpu/thread ID | |
108 | `define UCB_THR_LO 4 | |
109 | `define UCB_PKT_HI 3 // (4) packet type | |
110 | `define UCB_PKT_LO 0 | |
111 | ||
112 | `define UCB_DATA_EXT_WIDTH 64 | |
113 | `define UCB_DATA_WIDTH 64 | |
114 | `define UCB_RSV_WIDTH 9 | |
115 | `define UCB_ADDR_WIDTH 40 | |
116 | `define UCB_SIZE_WIDTH 3 | |
117 | `define UCB_BUF_WIDTH 2 | |
118 | `define UCB_THR_WIDTH 6 | |
119 | `define UCB_PKT_WIDTH 4 | |
120 | ||
121 | // Size encoding for the UCB_SIZE_HI/LO field | |
122 | // 000 - byte | |
123 | // 001 - half-word | |
124 | // 010 - word | |
125 | // 011 - double-word | |
126 | `define UCB_SIZE_1B 3'b000 | |
127 | `define UCB_SIZE_2B 3'b001 | |
128 | `define UCB_SIZE_4B 3'b010 | |
129 | `define UCB_SIZE_8B 3'b011 | |
130 | `define UCB_SIZE_16B 3'b100 | |
131 | ||
132 | ||
133 | // | |
134 | // UCB Interrupt Packet Format | |
135 | // =========================== | |
136 | // | |
137 | `define UCB_INT_PKT_WIDTH 64 | |
138 | ||
139 | `define UCB_INT_RSV_HI 63 // (7) reserved bits | |
140 | `define UCB_INT_RSV_LO 57 | |
141 | `define UCB_INT_VEC_HI 56 // (6) interrupt vector | |
142 | `define UCB_INT_VEC_LO 51 | |
143 | `define UCB_INT_STAT_HI 50 // (32) interrupt status | |
144 | `define UCB_INT_STAT_LO 19 | |
145 | `define UCB_INT_DEV_HI 18 // (9) device ID | |
146 | `define UCB_INT_DEV_LO 10 | |
147 | //`define UCB_THR_HI 9 // (6) cpu/thread ID shared with | |
148 | //`define UCB_THR_LO 4 data packet format | |
149 | //`define UCB_PKT_HI 3 // (4) packet type shared with | |
150 | //`define UCB_PKT_LO 0 // data packet format | |
151 | ||
152 | `define UCB_INT_RSV_WIDTH 7 | |
153 | `define UCB_INT_VEC_WIDTH 6 | |
154 | `define UCB_INT_STAT_WIDTH 32 | |
155 | `define UCB_INT_DEV_WIDTH 9 | |
156 | ||
157 | ||
158 | `define MCU_CAS_BIT2_SEL_PA10 4'h1 | |
159 | `define MCU_CAS_BIT2_SEL_PA32 4'h2 | |
160 | `define MCU_CAS_BIT2_SEL_PA33 4'h4 | |
161 | `define MCU_CAS_BIT2_SEL_PA34 4'h8 | |
162 | ||
163 | `define MCU_CAS_BIT3_SEL_PA11 4'h1 | |
164 | `define MCU_CAS_BIT3_SEL_PA33 4'h2 | |
165 | `define MCU_CAS_BIT3_SEL_PA34 4'h4 | |
166 | `define MCU_CAS_BIT3_SEL_PA35 4'h8 | |
167 | ||
168 | `define MCU_CAS_BIT4_SEL_PA12 3'h1 | |
169 | `define MCU_CAS_BIT4_SEL_PA35 3'h2 | |
170 | `define MCU_CAS_BIT4_SEL_PA36 3'h4 | |
171 | ||
172 | `define MCU_DIMMHI_SEL_ZERO 6'h01 | |
173 | `define MCU_DIMMHI_SEL_PA32 6'h02 | |
174 | `define MCU_DIMMHI_SEL_PA33 6'h04 | |
175 | `define MCU_DIMMHI_SEL_PA34 6'h08 | |
176 | `define MCU_DIMMHI_SEL_PA35 6'h10 | |
177 | `define MCU_DIMMHI_SEL_PA36 6'h20 | |
178 | ||
179 | `define MCU_DIMMLO_SEL_ZERO 4'h1 | |
180 | `define MCU_DIMMLO_SEL_PA10 4'h2 | |
181 | `define MCU_DIMMLO_SEL_PA11 4'h4 | |
182 | `define MCU_DIMMLO_SEL_PA12 4'h8 | |
183 | ||
184 | `define MCU_RANK_SEL_ZERO 7'h01 | |
185 | `define MCU_RANK_SEL_PA32 7'h02 | |
186 | `define MCU_RANK_SEL_PA33 7'h04 | |
187 | `define MCU_RANK_SEL_PA34 7'h08 | |
188 | `define MCU_RANK_SEL_PA35 7'h10 | |
189 | `define MCU_RANK_SEL_PA10 7'h20 | |
190 | `define MCU_RANK_SEL_PA11 7'h40 | |
191 | ||
192 | `define MCU_ADDR_ERR_SEL_39_32 6'h01 | |
193 | `define MCU_ADDR_ERR_SEL_39_33 6'h02 | |
194 | `define MCU_ADDR_ERR_SEL_39_34 6'h04 | |
195 | `define MCU_ADDR_ERR_SEL_39_35 6'h08 | |
196 | `define MCU_ADDR_ERR_SEL_39_36 6'h10 | |
197 | `define MCU_ADDR_ERR_SEL_39_37 6'h20 | |
198 | ||
199 | `define DRIF_ERR_IDLE 0 | |
200 | `define DRIF_ERR_IDLE_ST 5'h1 | |
201 | `define DRIF_ERR_READ0 1 | |
202 | `define DRIF_ERR_READ0_ST 5'h2 | |
203 | `define DRIF_ERR_WRITE 2 | |
204 | `define DRIF_ERR_WRITE_ST 5'h4 | |
205 | `define DRIF_ERR_READ1 3 | |
206 | `define DRIF_ERR_READ1_ST 5'h8 | |
207 | `define DRIF_ERR_CRC_FR 4 | |
208 | `define DRIF_ERR_CRC_FR_ST 5'h10 | |
209 | ||
210 | `define MCU_WDQ_RF_DATA_WIDTH 72 | |
211 | `define MCU_WDQ_RF_ADDR_WIDTH 5 | |
212 | `define MCU_WDQ_RF_DEPTH 32 | |
213 | ||
214 | // FBDIMM header defines | |
215 | `define FBD_TS0_HDR 12'hbfe | |
216 | `define FBD_TS1_HDR 12'hffe | |
217 | `define FBD_TS2_HDR 12'h7fe | |
218 | `define FBD_TS3_HDR 12'h3fe | |
219 | ||
220 | // MCU FBDIMM Channel commands | |
221 | `define FBD_DRAM_CMD_NOP 3'h0 | |
222 | `define FBD_DRAM_CMD_OTHER 3'h1 | |
223 | `define FBD_DRAM_CMD_RD 3'h2 | |
224 | `define FBD_DRAM_CMD_WR 3'h3 | |
225 | `define FBD_DRAM_CMD_ACT 3'h4 | |
226 | `define FBD_DRAM_CMD_WDATA 3'h5 | |
227 | ||
228 | `define FBD_DRAM_CMD_OTHER_REF 3'h5 | |
229 | `define FBD_DRAM_CMD_OTHER_SRE 3'h4 | |
230 | `define FBD_DRAM_CMD_OTHER_PDE 3'h2 | |
231 | `define FBD_DRAM_CMD_OTHER_SRPDX 3'h3 | |
232 | ||
233 | `define FBD_CHNL_CMD_NOP 2'h0 | |
234 | `define FBD_CHNL_CMD_SYNC 2'h1 | |
235 | `define FBD_CHNL_CMD_SCRST 2'h2 | |
236 | ||
237 | `define FBDIC_ERR_IDLE_ST 7'h01 | |
238 | `define FBDIC_ERR_IDLE 0 | |
239 | ||
240 | `define FBDIC_ERR_STS_ST 7'h02 | |
241 | `define FBDIC_ERR_STS 1 | |
242 | ||
243 | `define FBDIC_ERR_SCRST_ST 7'h04 | |
244 | `define FBDIC_ERR_SCRST 2 | |
245 | ||
246 | `define FBDIC_ERR_SCRST_STS_ST 7'h08 | |
247 | `define FBDIC_ERR_SCRST_STS 3 | |
248 | ||
249 | `define FBDIC_ERR_STS2_ST 7'h10 | |
250 | `define FBDIC_ERR_STS2 4 | |
251 | ||
252 | `define FBDIC_ERR_FASTRST_ST 7'h20 | |
253 | `define FBDIC_ERR_FASTRST 5 | |
254 | ||
255 | `define FBDIC_ERR_FASTRST_STS_ST 7'h40 | |
256 | `define FBDIC_ERR_FASTRST_STS 6 | |
257 | ||
258 | ||
259 | // IBIST DEFINITION | |
260 | ||
261 | `define L_2_0 12'h555 | |
262 | `define L_2_1 12'h555 | |
263 | `define L_4_0 12'h333 | |
264 | `define L_4_1 12'h333 | |
265 | `define L_6_0 12'h1c7 | |
266 | `define L_6_1 12'h1c7 | |
267 | `define L_8_0 12'h0f0 | |
268 | `define L_8_1 12'hf0f | |
269 | `define L_24_0 12'h000 | |
270 | `define L_24_1 12'hfff | |
271 | ||
272 | `define idle 4'h0 | |
273 | ||
274 | `define error_0 4'h1 | |
275 | `define error_1 4'h2 | |
276 | ||
277 | `define start1_0 4'h3 | |
278 | `define start1_1 4'h4 | |
279 | `define start2_0 4'h5 | |
280 | `define start2_1 4'h6 | |
281 | ||
282 | `define pat1_0 4'h7 | |
283 | `define pat1_1 4'h8 | |
284 | ||
285 | `define clkpat_0 4'h9 | |
286 | `define clkpat_1 4'ha | |
287 | ||
288 | `define const_0 4'hb | |
289 | `define const_1 4'hc | |
290 | ||
291 | `define stop1_0 4'h1 | |
292 | `define stop1_1 4'h2 | |
293 | ||
294 | `define stop2_0 4'hd | |
295 | `define stop2_1 4'he | |
296 | `define error 4'hf | |
297 | ||
298 | `define IBTX_STATE_IDLE 0 | |
299 | `define IBTX_STATE_PATT 1 | |
300 | `define IBTX_STATE_MODN 2 | |
301 | `define IBTX_STATE_CONST 3 | |
302 | ||
303 | `define IBRX_STATE_IDLE 0 | |
304 | `define IBRX_STATE_PATT 1 | |
305 | `define IBRX_STATE_MODN 2 | |
306 | `define IBRX_STATE_CONST 3 | |
307 | ||
308 | ||
309 | ||
310 | module mcu_ibtx_ctl ( | |
311 | ibist_txdata, | |
312 | ibtx_done, | |
313 | fbdic_sbfibportctl, | |
314 | fbdic_sbfibpgctl, | |
315 | fbdic_sbfibpattbuf1, | |
316 | fbdic_sbfibtxmsk, | |
317 | fbdic_sbfibtxshft, | |
318 | fbdic_sbfibpattbuf2, | |
319 | fbdic_sbfibpatt2en, | |
320 | fbdic_txstart, | |
321 | scan_in, | |
322 | tcu_aclk, | |
323 | tcu_bclk, | |
324 | tcu_scan_en, | |
325 | l1clk, | |
326 | scan_out); | |
327 | wire siclk; | |
328 | wire soclk; | |
329 | wire se; | |
330 | wire ibtx_loopcon; | |
331 | wire ibtx_autoinvswpen; | |
332 | wire ibtx_ovrloop_disable; | |
333 | wire ibtx_ovrloopcnt_is_zero; | |
334 | wire [5:0] ibtx_ovrloopcnt; | |
335 | wire ibtx_ovrloopcnt_dec; | |
336 | wire [4:0] ibtx_cnstgencnt; | |
337 | wire [6:0] ibtx_modloopcnt; | |
338 | wire [6:0] ibtx_pattloopcnt; | |
339 | wire [5:0] ibtx_ovrloopcnt_in; | |
340 | wire [3:0] ibtx_state; | |
341 | wire ff_ovrloopcnt_scanin; | |
342 | wire ff_ovrloopcnt_scanout; | |
343 | wire ibtx_cnstgen_disable; | |
344 | wire ibtx_cnstgencnt_dec; | |
345 | wire ibtx_lo_bits_sel; | |
346 | wire [4:0] ibtx_cnstgencnt_in; | |
347 | wire ff_cnstgencnt_scanin; | |
348 | wire ff_cnstgencnt_scanout; | |
349 | wire ibtx_cnstgenset; | |
350 | wire ibtx_modloop_disable; | |
351 | wire ibtx_modloopcnt_dec; | |
352 | wire [6:0] ibtx_modloopcnt_in; | |
353 | wire ff_modloopcnt_scanin; | |
354 | wire ff_modloopcnt_scanout; | |
355 | wire [2:0] ibtx_modperiod; | |
356 | wire ibtx_pattloop_disable; | |
357 | wire ibtx_pattloopcnt_dec; | |
358 | wire [6:0] ibtx_pattloopcnt_in; | |
359 | wire ff_pattloopcnt_scanin; | |
360 | wire ff_pattloopcnt_scanout; | |
361 | wire [2:0] ibtx_ptgenord; | |
362 | wire ibtx_ptgenord_pmc; | |
363 | wire ibtx_ptgenord_pcm; | |
364 | wire ibtx_ptgenord_mpc; | |
365 | wire ibtx_ptgenord_mcp; | |
366 | wire ibtx_ptgenord_cpm; | |
367 | wire ibtx_ptgenord_cmp; | |
368 | wire ibtx_idle_to_patt; | |
369 | wire ibtx_idle_to_modn; | |
370 | wire ibtx_idle_to_const; | |
371 | wire ibtx_idle_to_idle; | |
372 | wire ibtx_patt_to_patt; | |
373 | wire ibtx_patt_to_modn; | |
374 | wire ibtx_patt_to_const; | |
375 | wire ibtx_patt_to_idle; | |
376 | wire ibtx_modn_to_patt; | |
377 | wire ibtx_modn_to_modn; | |
378 | wire ibtx_modn_to_const; | |
379 | wire ibtx_modn_to_idle; | |
380 | wire ibtx_const_to_patt; | |
381 | wire ibtx_const_to_modn; | |
382 | wire ibtx_const_to_const; | |
383 | wire ibtx_const_to_idle; | |
384 | wire [1:0] ibtx_start_cnt_in; | |
385 | wire [1:0] ibtx_start_cnt; | |
386 | wire ff_start_cnt_scanin; | |
387 | wire ff_start_cnt_scanout; | |
388 | wire [11:0] ibtx_start_data; | |
389 | wire ibtx_lo_bits_sel_in; | |
390 | wire ff_hiword_sel_scanin; | |
391 | wire ff_hiword_sel_scanout; | |
392 | wire ff_state_scanin; | |
393 | wire ff_state_scanout; | |
394 | wire [3:0] ibtx_state_in; | |
395 | wire [3:0] ibtx_state_out; | |
396 | wire [9:0] ibtx_txinvshft_in; | |
397 | wire [9:0] ibtx_txinvshft; | |
398 | wire ff_txinvshft_scanin; | |
399 | wire ff_txinvshft_scanout; | |
400 | wire [11:0] ibtx_modn_data; | |
401 | wire [11:0] ibtx_patt1_data; | |
402 | wire [11:0] ibtx_data; | |
403 | wire [11:0] ibtx_data_l; | |
404 | wire [11:0] ibtx_patt2_data; | |
405 | wire [119:0] ibtx_txdata; | |
406 | ||
407 | ||
408 | output [119:0] ibist_txdata; | |
409 | output ibtx_done; | |
410 | ||
411 | input [23:0] fbdic_sbfibportctl; | |
412 | input [31:0] fbdic_sbfibpgctl; | |
413 | input [23:0] fbdic_sbfibpattbuf1; | |
414 | input [9:0] fbdic_sbfibtxmsk; | |
415 | input [9:0] fbdic_sbfibtxshft; | |
416 | input [23:0] fbdic_sbfibpattbuf2; | |
417 | input [9:0] fbdic_sbfibpatt2en; | |
418 | input fbdic_txstart; | |
419 | ||
420 | input scan_in ; | |
421 | input tcu_aclk ; | |
422 | input tcu_bclk ; | |
423 | input tcu_scan_en ; | |
424 | ||
425 | input l1clk ; | |
426 | ||
427 | output scan_out ; | |
428 | ||
429 | assign siclk = tcu_aclk; | |
430 | assign soclk = tcu_bclk; | |
431 | assign se = tcu_scan_en; | |
432 | ||
433 | // Port control register signals | |
434 | assign ibtx_loopcon = fbdic_sbfibportctl[3]; | |
435 | assign ibtx_autoinvswpen = fbdic_sbfibportctl[5]; | |
436 | ||
437 | // Pattern generation counters | |
438 | assign ibtx_ovrloop_disable = fbdic_sbfibpgctl[31:26] == 6'h0; | |
439 | assign ibtx_ovrloopcnt_is_zero = ibtx_ovrloopcnt[5:0] == 6'h0 & ~ibtx_loopcon; | |
440 | assign ibtx_ovrloopcnt_dec = ibtx_cnstgencnt[4:0] == 5'h0 & ibtx_modloopcnt[6:0] == 7'h0 & | |
441 | ibtx_pattloopcnt[6:0] == 7'h0 & ~ibtx_ovrloopcnt_is_zero; | |
442 | assign ibtx_ovrloopcnt_in[5:0] = fbdic_txstart | ibtx_cnstgencnt[4:0] == 5'h0 & | |
443 | ibtx_modloopcnt[6:0] == 7'h0 & | |
444 | ibtx_pattloopcnt[6:0] == 7'h0 & | |
445 | ibtx_ovrloopcnt[5:0] == 6'h0 & ~ibtx_state[`IBTX_STATE_IDLE] & | |
446 | ibtx_loopcon ? fbdic_sbfibpgctl[31:26] - 6'h1 : | |
447 | ibtx_ovrloopcnt_dec ? ibtx_ovrloopcnt[5:0] - 6'h1 : ibtx_ovrloopcnt[5:0]; | |
448 | mcu_ibtx_ctl_msff_ctl_macro__width_6 ff_ovrloopcnt ( | |
449 | .scan_in(ff_ovrloopcnt_scanin), | |
450 | .scan_out(ff_ovrloopcnt_scanout), | |
451 | .din(ibtx_ovrloopcnt_in[5:0]), | |
452 | .dout(ibtx_ovrloopcnt[5:0]), | |
453 | .l1clk(l1clk), | |
454 | .siclk(siclk), | |
455 | .soclk(soclk)); | |
456 | ||
457 | // Constant generation | |
458 | assign ibtx_cnstgen_disable = fbdic_sbfibpgctl[25:21] == 5'h0; | |
459 | assign ibtx_cnstgencnt_dec = ibtx_state[`IBTX_STATE_CONST] & ibtx_lo_bits_sel; | |
460 | assign ibtx_cnstgencnt_in[4:0] = fbdic_txstart | ibtx_ovrloopcnt_dec ? fbdic_sbfibpgctl[25:21] : | |
461 | ibtx_cnstgencnt_dec ? ibtx_cnstgencnt[4:0] - 5'h1 : ibtx_cnstgencnt[4:0]; | |
462 | mcu_ibtx_ctl_msff_ctl_macro__width_5 ff_cnstgencnt ( | |
463 | .scan_in(ff_cnstgencnt_scanin), | |
464 | .scan_out(ff_cnstgencnt_scanout), | |
465 | .din(ibtx_cnstgencnt_in[4:0]), | |
466 | .dout(ibtx_cnstgencnt[4:0]), | |
467 | .l1clk(l1clk), | |
468 | .siclk(siclk), | |
469 | .soclk(soclk)); | |
470 | ||
471 | assign ibtx_cnstgenset = fbdic_sbfibpgctl[20]; | |
472 | ||
473 | // Mod-N pattern | |
474 | assign ibtx_modloop_disable = fbdic_sbfibpgctl[19:13] == 7'h0; | |
475 | assign ibtx_modloopcnt_dec = ibtx_state[`IBTX_STATE_MODN] & ibtx_lo_bits_sel; | |
476 | assign ibtx_modloopcnt_in[6:0] = fbdic_txstart | ibtx_ovrloopcnt_dec ? fbdic_sbfibpgctl[19:13] : | |
477 | ibtx_modloopcnt_dec ? ibtx_modloopcnt[6:0] - 7'h1 : ibtx_modloopcnt[6:0]; | |
478 | mcu_ibtx_ctl_msff_ctl_macro__width_7 ff_modloopcnt ( | |
479 | .scan_in(ff_modloopcnt_scanin), | |
480 | .scan_out(ff_modloopcnt_scanout), | |
481 | .din(ibtx_modloopcnt_in[6:0]), | |
482 | .dout(ibtx_modloopcnt[6:0]), | |
483 | .l1clk(l1clk), | |
484 | .siclk(siclk), | |
485 | .soclk(soclk)); | |
486 | ||
487 | assign ibtx_modperiod[2:0] = fbdic_sbfibpgctl[12:10]; | |
488 | ||
489 | // Pattern Register 1 | |
490 | assign ibtx_pattloop_disable = fbdic_sbfibpgctl[9:3] == 7'h0; | |
491 | assign ibtx_pattloopcnt_dec = ibtx_state[`IBTX_STATE_PATT] & ibtx_lo_bits_sel; | |
492 | assign ibtx_pattloopcnt_in[6:0] = fbdic_txstart | ibtx_ovrloopcnt_dec ? fbdic_sbfibpgctl[9:3] : | |
493 | ibtx_pattloopcnt_dec ? ibtx_pattloopcnt[6:0] - 7'h1 : ibtx_pattloopcnt[6:0]; | |
494 | mcu_ibtx_ctl_msff_ctl_macro__width_7 ff_pattloopcnt ( | |
495 | .scan_in(ff_pattloopcnt_scanin), | |
496 | .scan_out(ff_pattloopcnt_scanout), | |
497 | .din(ibtx_pattloopcnt_in[6:0]), | |
498 | .dout(ibtx_pattloopcnt[6:0]), | |
499 | .l1clk(l1clk), | |
500 | .siclk(siclk), | |
501 | .soclk(soclk)); | |
502 | ||
503 | // | |
504 | assign ibtx_ptgenord[2:0] = fbdic_sbfibpgctl[2:0]; | |
505 | assign ibtx_ptgenord_pmc = ibtx_ptgenord[2:0] == 3'h0; | |
506 | assign ibtx_ptgenord_pcm = ibtx_ptgenord[2:0] == 3'h1; | |
507 | assign ibtx_ptgenord_mpc = ibtx_ptgenord[2:0] == 3'h2; | |
508 | assign ibtx_ptgenord_mcp = ibtx_ptgenord[2:0] == 3'h3; | |
509 | assign ibtx_ptgenord_cpm = ibtx_ptgenord[2:0] == 3'h4; | |
510 | assign ibtx_ptgenord_cmp = ibtx_ptgenord[2:0] == 3'h5; | |
511 | ||
512 | // State machine arcs | |
513 | // Idle/Start state | |
514 | assign ibtx_idle_to_patt = ~ibtx_pattloop_disable & | |
515 | (ibtx_ptgenord_pmc | ibtx_ptgenord_pcm | | |
516 | ibtx_ptgenord_mpc & ibtx_modloop_disable | | |
517 | ibtx_ptgenord_mcp & ibtx_cnstgen_disable & ibtx_modloop_disable | | |
518 | ibtx_ptgenord_cpm & ibtx_cnstgen_disable | | |
519 | ibtx_ptgenord_cmp & ibtx_cnstgen_disable & ibtx_modloop_disable); | |
520 | assign ibtx_idle_to_modn = ~ibtx_modloop_disable & | |
521 | (ibtx_ptgenord_mpc | ibtx_ptgenord_mcp | | |
522 | ibtx_ptgenord_pmc & ibtx_pattloop_disable | | |
523 | ibtx_ptgenord_pcm & ibtx_pattloop_disable & ibtx_cnstgen_disable | | |
524 | ibtx_ptgenord_cpm & ibtx_pattloop_disable & ibtx_cnstgen_disable | | |
525 | ibtx_ptgenord_cmp & ibtx_cnstgen_disable); | |
526 | assign ibtx_idle_to_const = ~ibtx_cnstgen_disable & | |
527 | (ibtx_ptgenord_cpm | ibtx_ptgenord_cmp | | |
528 | ibtx_ptgenord_pmc & ibtx_pattloop_disable & ibtx_modloop_disable | | |
529 | ibtx_ptgenord_pcm & ibtx_pattloop_disable | | |
530 | ibtx_ptgenord_mpc & ibtx_modloop_disable & ibtx_pattloop_disable | | |
531 | ibtx_ptgenord_mcp & ibtx_modloop_disable); | |
532 | assign ibtx_idle_to_idle = ibtx_pattloop_disable & ibtx_modloop_disable & ibtx_cnstgen_disable | ibtx_ovrloop_disable; | |
533 | ||
534 | // Pattern state | |
535 | assign ibtx_patt_to_patt = ibtx_modloop_disable & ibtx_cnstgen_disable & ~ibtx_ovrloopcnt_is_zero; | |
536 | assign ibtx_patt_to_modn = ~ibtx_modloop_disable & | |
537 | (ibtx_ptgenord_pmc | ibtx_ptgenord_cpm | | |
538 | ibtx_ptgenord_pcm & ibtx_cnstgen_disable | | |
539 | ibtx_ptgenord_mpc & ibtx_cnstgen_disable & ~ibtx_ovrloopcnt_is_zero | | |
540 | ibtx_ptgenord_mcp & ~ibtx_ovrloopcnt_is_zero | | |
541 | ibtx_ptgenord_cmp & ibtx_cnstgen_disable & ~ibtx_ovrloopcnt_is_zero); | |
542 | assign ibtx_patt_to_const = ~ibtx_cnstgen_disable & | |
543 | (ibtx_ptgenord_pmc & ibtx_modloop_disable | | |
544 | ibtx_ptgenord_cpm & ibtx_modloop_disable & ~ibtx_ovrloopcnt_is_zero | | |
545 | ibtx_ptgenord_pcm | | |
546 | ibtx_ptgenord_mpc | | |
547 | ibtx_ptgenord_mcp & ibtx_modloop_disable & ~ibtx_ovrloopcnt_is_zero | | |
548 | ibtx_ptgenord_cmp & ~ibtx_ovrloopcnt_is_zero); | |
549 | assign ibtx_patt_to_idle = ibtx_ovrloopcnt_is_zero & | |
550 | (ibtx_ptgenord_pmc & ibtx_cnstgen_disable & ibtx_modloop_disable | | |
551 | ibtx_ptgenord_cpm & ibtx_modloop_disable | | |
552 | ibtx_ptgenord_pcm & ibtx_cnstgen_disable & ibtx_modloop_disable | | |
553 | ibtx_ptgenord_mpc & ibtx_cnstgen_disable | | |
554 | ibtx_ptgenord_mcp | | |
555 | ibtx_ptgenord_cmp); | |
556 | ||
557 | // MOD-N state | |
558 | assign ibtx_modn_to_patt = ~ibtx_pattloop_disable & | |
559 | (ibtx_ptgenord_pmc & ibtx_cnstgen_disable & ~ibtx_ovrloopcnt_is_zero | | |
560 | ibtx_ptgenord_cpm & ibtx_cnstgen_disable & ~ibtx_ovrloopcnt_is_zero | | |
561 | ibtx_ptgenord_pcm & ~ibtx_ovrloopcnt_is_zero | | |
562 | ibtx_ptgenord_mpc | | |
563 | ibtx_ptgenord_mcp & ibtx_cnstgen_disable | | |
564 | ibtx_ptgenord_cmp); | |
565 | assign ibtx_modn_to_modn = ~ibtx_modloop_disable & ibtx_cnstgen_disable & ibtx_pattloop_disable; | |
566 | assign ibtx_modn_to_const = ~ibtx_cnstgen_disable & | |
567 | (ibtx_ptgenord_pmc | | |
568 | ibtx_ptgenord_mcp | | |
569 | ibtx_ptgenord_cpm & ~ibtx_ovrloopcnt_is_zero | | |
570 | ibtx_ptgenord_pcm & ~ibtx_ovrloopcnt_is_zero & ibtx_pattloop_disable | | |
571 | ibtx_ptgenord_mpc & ibtx_pattloop_disable| | |
572 | ibtx_ptgenord_cmp & ~ibtx_ovrloopcnt_is_zero & ibtx_pattloop_disable); | |
573 | assign ibtx_modn_to_idle = ibtx_ovrloopcnt_is_zero & | |
574 | (ibtx_ptgenord_pmc & ibtx_cnstgen_disable | | |
575 | ibtx_ptgenord_cpm | | |
576 | ibtx_ptgenord_pcm | | |
577 | ibtx_ptgenord_mpc & ibtx_cnstgen_disable & ibtx_pattloop_disable | | |
578 | ibtx_ptgenord_mcp & ibtx_cnstgen_disable & ibtx_pattloop_disable | | |
579 | ibtx_ptgenord_cmp & ibtx_pattloop_disable); | |
580 | ||
581 | // Constant state | |
582 | assign ibtx_const_to_patt = ~ibtx_pattloop_disable & | |
583 | (ibtx_ptgenord_pmc & ~ibtx_ovrloopcnt_is_zero | | |
584 | ibtx_ptgenord_cpm | | |
585 | ibtx_ptgenord_pcm & ~ibtx_ovrloopcnt_is_zero & ibtx_modloop_disable | | |
586 | ibtx_ptgenord_mpc & ~ibtx_ovrloopcnt_is_zero & ibtx_modloop_disable | | |
587 | ibtx_ptgenord_mcp | | |
588 | ibtx_ptgenord_cmp & ibtx_modloop_disable); | |
589 | assign ibtx_const_to_modn = ~ibtx_modloop_disable & | |
590 | (ibtx_ptgenord_pmc & ~ibtx_ovrloopcnt_is_zero & ibtx_pattloop_disable | | |
591 | ibtx_ptgenord_cpm & ibtx_pattloop_disable | | |
592 | ibtx_ptgenord_pcm | | |
593 | ibtx_ptgenord_mpc & ~ibtx_ovrloopcnt_is_zero | | |
594 | ibtx_ptgenord_mcp & ~ibtx_ovrloopcnt_is_zero & ibtx_pattloop_disable | | |
595 | ibtx_ptgenord_cmp); | |
596 | assign ibtx_const_to_const = ~ibtx_ovrloopcnt_is_zero & ibtx_modloop_disable & ibtx_pattloop_disable; | |
597 | assign ibtx_const_to_idle = ibtx_ovrloopcnt_is_zero & | |
598 | (ibtx_ptgenord_pmc | | |
599 | ibtx_ptgenord_cpm & ibtx_modloop_disable & ibtx_pattloop_disable | | |
600 | ibtx_ptgenord_pcm & ibtx_modloop_disable | | |
601 | ibtx_ptgenord_mpc | | |
602 | ibtx_ptgenord_mcp & ibtx_pattloop_disable | | |
603 | ibtx_ptgenord_cmp & ibtx_modloop_disable & ibtx_pattloop_disable); | |
604 | ||
605 | // Counter to send out start delimiters | |
606 | assign ibtx_start_cnt_in[1:0] = fbdic_txstart | (|ibtx_start_cnt[1:0]) ? ibtx_start_cnt[1:0] + 2'h1 : 2'h0; | |
607 | mcu_ibtx_ctl_msff_ctl_macro__width_2 ff_start_cnt ( | |
608 | .scan_in(ff_start_cnt_scanin), | |
609 | .scan_out(ff_start_cnt_scanout), | |
610 | .din(ibtx_start_cnt_in[1:0]), | |
611 | .dout(ibtx_start_cnt[1:0]), | |
612 | .l1clk(l1clk), | |
613 | .siclk(siclk), | |
614 | .soclk(soclk)); | |
615 | ||
616 | assign ibtx_start_data[11:0] = ibtx_start_cnt[0] ? 12'h876 : 12'h543; | |
617 | ||
618 | // Bit to select between high and low 12 bits of pattern data | |
619 | assign ibtx_lo_bits_sel_in = ~ibtx_state[`IBTX_STATE_IDLE] & ~ibtx_lo_bits_sel; | |
620 | mcu_ibtx_ctl_msff_ctl_macro ff_hiword_sel ( | |
621 | .scan_in(ff_hiword_sel_scanin), | |
622 | .scan_out(ff_hiword_sel_scanout), | |
623 | .din(ibtx_lo_bits_sel_in), | |
624 | .dout(ibtx_lo_bits_sel), | |
625 | .l1clk(l1clk), | |
626 | .siclk(siclk), | |
627 | .soclk(soclk)); | |
628 | ||
629 | // state machine | |
630 | reg [3:0] ibtx_state_next; | |
631 | ||
632 | // 0in one_hot -var ibtx_state[3:0] | |
633 | mcu_ibtx_ctl_msff_ctl_macro__width_4 ff_state ( | |
634 | .scan_in(ff_state_scanin), | |
635 | .scan_out(ff_state_scanout), | |
636 | .din(ibtx_state_in[3:0]), | |
637 | .dout(ibtx_state_out[3:0]), | |
638 | .l1clk(l1clk), | |
639 | .siclk(siclk), | |
640 | .soclk(soclk)); | |
641 | ||
642 | assign ibtx_state_in[3:0] = ibtx_state_next[3:0] ^ 4'h1; | |
643 | assign ibtx_state[3:0] = ibtx_state_out[3:0] ^ 4'h1; | |
644 | ||
645 | always @(ibtx_state or ibtx_idle_to_const or ibtx_idle_to_modn or ibtx_idle_to_patt or ibtx_idle_to_idle | |
646 | or ibtx_patt_to_const or ibtx_patt_to_modn or ibtx_patt_to_patt or ibtx_patt_to_idle | |
647 | or ibtx_const_to_const or ibtx_const_to_modn or ibtx_const_to_patt or ibtx_const_to_idle | |
648 | or ibtx_modn_to_const or ibtx_modn_to_modn or ibtx_modn_to_patt or ibtx_modn_to_idle | |
649 | or ibtx_start_cnt or ibtx_cnstgencnt or ibtx_modloopcnt or ibtx_pattloopcnt or ibtx_lo_bits_sel) | |
650 | begin | |
651 | ||
652 | ibtx_state_next[3:0] = 4'h0; | |
653 | ||
654 | case (1'b1) | |
655 | ibtx_state[`IBTX_STATE_IDLE]: begin | |
656 | if (ibtx_start_cnt[1:0] == 2'h3) begin | |
657 | ibtx_state_next[3:0] = {ibtx_idle_to_const, ibtx_idle_to_modn, | |
658 | ibtx_idle_to_patt, ibtx_idle_to_idle}; | |
659 | end | |
660 | else begin | |
661 | ibtx_state_next[`IBTX_STATE_IDLE] = 1'b1; | |
662 | end | |
663 | end | |
664 | ibtx_state[`IBTX_STATE_CONST]: begin | |
665 | if (ibtx_cnstgencnt[4:0] == 5'h1 & ibtx_lo_bits_sel) begin | |
666 | ibtx_state_next[3:0] = {ibtx_const_to_const, ibtx_const_to_modn, | |
667 | ibtx_const_to_patt, ibtx_const_to_idle}; | |
668 | end | |
669 | else begin | |
670 | ibtx_state_next[`IBTX_STATE_CONST] = 1'b1; | |
671 | end | |
672 | end | |
673 | ibtx_state[`IBTX_STATE_MODN]: begin | |
674 | if (ibtx_modloopcnt[6:0] == 7'h1 & ibtx_lo_bits_sel) begin | |
675 | ibtx_state_next[3:0] = {ibtx_modn_to_const, ibtx_modn_to_modn, | |
676 | ibtx_modn_to_patt, ibtx_modn_to_idle}; | |
677 | end | |
678 | else begin | |
679 | ibtx_state_next[`IBTX_STATE_MODN] = 1'b1; | |
680 | end | |
681 | end | |
682 | ibtx_state[`IBTX_STATE_PATT]: begin | |
683 | if (ibtx_pattloopcnt[6:0] == 7'h1 & ibtx_lo_bits_sel) begin | |
684 | ibtx_state_next[3:0] = {ibtx_patt_to_const, ibtx_patt_to_modn, | |
685 | ibtx_patt_to_patt, ibtx_patt_to_idle}; | |
686 | end | |
687 | else begin | |
688 | ibtx_state_next[`IBTX_STATE_PATT] = 1'b1; | |
689 | end | |
690 | end | |
691 | default: ; | |
692 | endcase | |
693 | end | |
694 | ||
695 | assign ibtx_done = ~ibtx_state[0] & ibtx_state_next[0]; | |
696 | ||
697 | // inversion shift register | |
698 | assign ibtx_txinvshft_in[9:0] = fbdic_txstart ? fbdic_sbfibtxshft[9:0] : | |
699 | ibtx_ovrloopcnt_dec & ibtx_autoinvswpen ? | |
700 | {ibtx_txinvshft[8:0],ibtx_txinvshft[9]} : ibtx_txinvshft[9:0]; | |
701 | mcu_ibtx_ctl_msff_ctl_macro__width_10 ff_txinvshft ( | |
702 | .scan_in(ff_txinvshft_scanin), | |
703 | .scan_out(ff_txinvshft_scanout), | |
704 | .din(ibtx_txinvshft_in[9:0]), | |
705 | .dout(ibtx_txinvshft[9:0]), | |
706 | .l1clk(l1clk), | |
707 | .siclk(siclk), | |
708 | .soclk(soclk)); | |
709 | ||
710 | assign ibtx_modn_data[11:0] = {12{ibtx_modperiod[2:0] == 3'h1}} & 12'h555 | | |
711 | {12{ibtx_modperiod[2:0] == 3'h2}} & 12'h333 | | |
712 | {12{ibtx_modperiod[2:0] == 3'h3}} & 12'h1c7 | | |
713 | {12{ibtx_modperiod[2:0] == 3'h4}} & (ibtx_lo_bits_sel ? 12'hf0f : 12'h0f0) | | |
714 | {12{ibtx_modperiod[2:0] == 3'h6}} & (ibtx_lo_bits_sel ? 12'hfff : 12'h000); | |
715 | ||
716 | assign ibtx_patt1_data[11:0] = ibtx_lo_bits_sel ? fbdic_sbfibpattbuf1[11:0] : fbdic_sbfibpattbuf1[23:12]; | |
717 | ||
718 | assign ibtx_data[11:0] = {12{ibtx_state[`IBTX_STATE_CONST]}} & {12{ibtx_cnstgenset}} | | |
719 | {12{ibtx_state[`IBTX_STATE_PATT]}} & ibtx_patt1_data[11:0] | | |
720 | {12{ibtx_state[`IBTX_STATE_MODN]}} & ibtx_modn_data[11:0]; | |
721 | assign ibtx_data_l[11:0] = ~ibtx_data[11:0]; | |
722 | ||
723 | assign ibtx_patt2_data[11:0] = ibtx_lo_bits_sel ? fbdic_sbfibpattbuf2[11:0] : fbdic_sbfibpattbuf2[23:12]; | |
724 | ||
725 | assign ibtx_txdata[119:108] = {12{fbdic_sbfibtxmsk[9]}} & (fbdic_sbfibpatt2en[9] ? ibtx_patt2_data[11:0] : | |
726 | ibtx_txinvshft[9] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
727 | assign ibtx_txdata[107:96] = {12{fbdic_sbfibtxmsk[8]}} & (fbdic_sbfibpatt2en[8] ? ibtx_patt2_data[11:0] : | |
728 | ibtx_txinvshft[8] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
729 | assign ibtx_txdata[95:84] = {12{fbdic_sbfibtxmsk[7]}} & (fbdic_sbfibpatt2en[7] ? ibtx_patt2_data[11:0] : | |
730 | ibtx_txinvshft[7] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
731 | assign ibtx_txdata[83:72] = {12{fbdic_sbfibtxmsk[6]}} & (fbdic_sbfibpatt2en[6] ? ibtx_patt2_data[11:0] : | |
732 | ibtx_txinvshft[6] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
733 | assign ibtx_txdata[71:60] = {12{fbdic_sbfibtxmsk[5]}} & (fbdic_sbfibpatt2en[5] ? ibtx_patt2_data[11:0] : | |
734 | ibtx_txinvshft[5] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
735 | assign ibtx_txdata[59:48] = {12{fbdic_sbfibtxmsk[4]}} & (fbdic_sbfibpatt2en[4] ? ibtx_patt2_data[11:0] : | |
736 | ibtx_txinvshft[4] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
737 | assign ibtx_txdata[47:36] = {12{fbdic_sbfibtxmsk[3]}} & (fbdic_sbfibpatt2en[3] ? ibtx_patt2_data[11:0] : | |
738 | ibtx_txinvshft[3] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
739 | assign ibtx_txdata[35:24] = {12{fbdic_sbfibtxmsk[2]}} & (fbdic_sbfibpatt2en[2] ? ibtx_patt2_data[11:0] : | |
740 | ibtx_txinvshft[2] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
741 | assign ibtx_txdata[23:12] = {12{fbdic_sbfibtxmsk[1]}} & (fbdic_sbfibpatt2en[1] ? ibtx_patt2_data[11:0] : | |
742 | ibtx_txinvshft[1] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
743 | assign ibtx_txdata[11:0] = {12{fbdic_sbfibtxmsk[0]}} & (fbdic_sbfibpatt2en[0] ? ibtx_patt2_data[11:0] : | |
744 | ibtx_txinvshft[0] ? ibtx_data_l[11:0] : ibtx_data[11:0]); | |
745 | ||
746 | assign ibist_txdata[119:0] = ibtx_state[`IBTX_STATE_IDLE] ? {10{ibtx_start_data[11:0]}}: ibtx_txdata[119:0]; | |
747 | ||
748 | // fixscan start: | |
749 | assign ff_ovrloopcnt_scanin = scan_in ; | |
750 | assign ff_cnstgencnt_scanin = ff_ovrloopcnt_scanout ; | |
751 | assign ff_modloopcnt_scanin = ff_cnstgencnt_scanout ; | |
752 | assign ff_pattloopcnt_scanin = ff_modloopcnt_scanout ; | |
753 | assign ff_start_cnt_scanin = ff_pattloopcnt_scanout ; | |
754 | assign ff_hiword_sel_scanin = ff_start_cnt_scanout ; | |
755 | assign ff_state_scanin = ff_hiword_sel_scanout ; | |
756 | assign ff_txinvshft_scanin = ff_state_scanout ; | |
757 | assign scan_out = ff_txinvshft_scanout ; | |
758 | // fixscan end: | |
759 | endmodule | |
760 | ||
761 | ||
762 | ||
763 | ||
764 | ||
765 | ||
766 | // any PARAMS parms go into naming of macro | |
767 | ||
768 | module mcu_ibtx_ctl_msff_ctl_macro__width_6 ( | |
769 | din, | |
770 | l1clk, | |
771 | scan_in, | |
772 | siclk, | |
773 | soclk, | |
774 | dout, | |
775 | scan_out); | |
776 | wire [5:0] fdin; | |
777 | wire [4:0] so; | |
778 | ||
779 | input [5:0] din; | |
780 | input l1clk; | |
781 | input scan_in; | |
782 | ||
783 | ||
784 | input siclk; | |
785 | input soclk; | |
786 | ||
787 | output [5:0] dout; | |
788 | output scan_out; | |
789 | assign fdin[5:0] = din[5:0]; | |
790 | ||
791 | ||
792 | ||
793 | ||
794 | ||
795 | ||
796 | dff #(6) d0_0 ( | |
797 | .l1clk(l1clk), | |
798 | .siclk(siclk), | |
799 | .soclk(soclk), | |
800 | .d(fdin[5:0]), | |
801 | .si({scan_in,so[4:0]}), | |
802 | .so({so[4:0],scan_out}), | |
803 | .q(dout[5:0]) | |
804 | ); | |
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | ||
813 | ||
814 | ||
815 | ||
816 | ||
817 | endmodule | |
818 | ||
819 | ||
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | ||
826 | ||
827 | ||
828 | ||
829 | ||
830 | ||
831 | // any PARAMS parms go into naming of macro | |
832 | ||
833 | module mcu_ibtx_ctl_msff_ctl_macro__width_5 ( | |
834 | din, | |
835 | l1clk, | |
836 | scan_in, | |
837 | siclk, | |
838 | soclk, | |
839 | dout, | |
840 | scan_out); | |
841 | wire [4:0] fdin; | |
842 | wire [3:0] so; | |
843 | ||
844 | input [4:0] din; | |
845 | input l1clk; | |
846 | input scan_in; | |
847 | ||
848 | ||
849 | input siclk; | |
850 | input soclk; | |
851 | ||
852 | output [4:0] dout; | |
853 | output scan_out; | |
854 | assign fdin[4:0] = din[4:0]; | |
855 | ||
856 | ||
857 | ||
858 | ||
859 | ||
860 | ||
861 | dff #(5) d0_0 ( | |
862 | .l1clk(l1clk), | |
863 | .siclk(siclk), | |
864 | .soclk(soclk), | |
865 | .d(fdin[4:0]), | |
866 | .si({scan_in,so[3:0]}), | |
867 | .so({so[3:0],scan_out}), | |
868 | .q(dout[4:0]) | |
869 | ); | |
870 | ||
871 | ||
872 | ||
873 | ||
874 | ||
875 | ||
876 | ||
877 | ||
878 | ||
879 | ||
880 | ||
881 | ||
882 | endmodule | |
883 | ||
884 | ||
885 | ||
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | ||
894 | ||
895 | ||
896 | // any PARAMS parms go into naming of macro | |
897 | ||
898 | module mcu_ibtx_ctl_msff_ctl_macro__width_7 ( | |
899 | din, | |
900 | l1clk, | |
901 | scan_in, | |
902 | siclk, | |
903 | soclk, | |
904 | dout, | |
905 | scan_out); | |
906 | wire [6:0] fdin; | |
907 | wire [5:0] so; | |
908 | ||
909 | input [6:0] din; | |
910 | input l1clk; | |
911 | input scan_in; | |
912 | ||
913 | ||
914 | input siclk; | |
915 | input soclk; | |
916 | ||
917 | output [6:0] dout; | |
918 | output scan_out; | |
919 | assign fdin[6:0] = din[6:0]; | |
920 | ||
921 | ||
922 | ||
923 | ||
924 | ||
925 | ||
926 | dff #(7) d0_0 ( | |
927 | .l1clk(l1clk), | |
928 | .siclk(siclk), | |
929 | .soclk(soclk), | |
930 | .d(fdin[6:0]), | |
931 | .si({scan_in,so[5:0]}), | |
932 | .so({so[5:0],scan_out}), | |
933 | .q(dout[6:0]) | |
934 | ); | |
935 | ||
936 | ||
937 | ||
938 | ||
939 | ||
940 | ||
941 | ||
942 | ||
943 | ||
944 | ||
945 | ||
946 | ||
947 | endmodule | |
948 | ||
949 | ||
950 | ||
951 | ||
952 | ||
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | ||
960 | ||
961 | // any PARAMS parms go into naming of macro | |
962 | ||
963 | module mcu_ibtx_ctl_msff_ctl_macro__width_2 ( | |
964 | din, | |
965 | l1clk, | |
966 | scan_in, | |
967 | siclk, | |
968 | soclk, | |
969 | dout, | |
970 | scan_out); | |
971 | wire [1:0] fdin; | |
972 | wire [0:0] so; | |
973 | ||
974 | input [1:0] din; | |
975 | input l1clk; | |
976 | input scan_in; | |
977 | ||
978 | ||
979 | input siclk; | |
980 | input soclk; | |
981 | ||
982 | output [1:0] dout; | |
983 | output scan_out; | |
984 | assign fdin[1:0] = din[1:0]; | |
985 | ||
986 | ||
987 | ||
988 | ||
989 | ||
990 | ||
991 | dff #(2) d0_0 ( | |
992 | .l1clk(l1clk), | |
993 | .siclk(siclk), | |
994 | .soclk(soclk), | |
995 | .d(fdin[1:0]), | |
996 | .si({scan_in,so[0:0]}), | |
997 | .so({so[0:0],scan_out}), | |
998 | .q(dout[1:0]) | |
999 | ); | |
1000 | ||
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | endmodule | |
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | ||
1025 | ||
1026 | // any PARAMS parms go into naming of macro | |
1027 | ||
1028 | module mcu_ibtx_ctl_msff_ctl_macro ( | |
1029 | din, | |
1030 | l1clk, | |
1031 | scan_in, | |
1032 | siclk, | |
1033 | soclk, | |
1034 | dout, | |
1035 | scan_out); | |
1036 | wire [0:0] fdin; | |
1037 | ||
1038 | input [0:0] din; | |
1039 | input l1clk; | |
1040 | input scan_in; | |
1041 | ||
1042 | ||
1043 | input siclk; | |
1044 | input soclk; | |
1045 | ||
1046 | output [0:0] dout; | |
1047 | output scan_out; | |
1048 | assign fdin[0:0] = din[0:0]; | |
1049 | ||
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | dff #(1) d0_0 ( | |
1056 | .l1clk(l1clk), | |
1057 | .siclk(siclk), | |
1058 | .soclk(soclk), | |
1059 | .d(fdin[0:0]), | |
1060 | .si(scan_in), | |
1061 | .so(scan_out), | |
1062 | .q(dout[0:0]) | |
1063 | ); | |
1064 | ||
1065 | ||
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | endmodule | |
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | // any PARAMS parms go into naming of macro | |
1091 | ||
1092 | module mcu_ibtx_ctl_msff_ctl_macro__width_4 ( | |
1093 | din, | |
1094 | l1clk, | |
1095 | scan_in, | |
1096 | siclk, | |
1097 | soclk, | |
1098 | dout, | |
1099 | scan_out); | |
1100 | wire [3:0] fdin; | |
1101 | wire [2:0] so; | |
1102 | ||
1103 | input [3:0] din; | |
1104 | input l1clk; | |
1105 | input scan_in; | |
1106 | ||
1107 | ||
1108 | input siclk; | |
1109 | input soclk; | |
1110 | ||
1111 | output [3:0] dout; | |
1112 | output scan_out; | |
1113 | assign fdin[3:0] = din[3:0]; | |
1114 | ||
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | ||
1120 | dff #(4) d0_0 ( | |
1121 | .l1clk(l1clk), | |
1122 | .siclk(siclk), | |
1123 | .soclk(soclk), | |
1124 | .d(fdin[3:0]), | |
1125 | .si({scan_in,so[2:0]}), | |
1126 | .so({so[2:0],scan_out}), | |
1127 | .q(dout[3:0]) | |
1128 | ); | |
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | ||
1141 | endmodule | |
1142 | ||
1143 | ||
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | // any PARAMS parms go into naming of macro | |
1156 | ||
1157 | module mcu_ibtx_ctl_msff_ctl_macro__width_10 ( | |
1158 | din, | |
1159 | l1clk, | |
1160 | scan_in, | |
1161 | siclk, | |
1162 | soclk, | |
1163 | dout, | |
1164 | scan_out); | |
1165 | wire [9:0] fdin; | |
1166 | wire [8:0] so; | |
1167 | ||
1168 | input [9:0] din; | |
1169 | input l1clk; | |
1170 | input scan_in; | |
1171 | ||
1172 | ||
1173 | input siclk; | |
1174 | input soclk; | |
1175 | ||
1176 | output [9:0] dout; | |
1177 | output scan_out; | |
1178 | assign fdin[9:0] = din[9:0]; | |
1179 | ||
1180 | ||
1181 | ||
1182 | ||
1183 | ||
1184 | ||
1185 | dff #(10) d0_0 ( | |
1186 | .l1clk(l1clk), | |
1187 | .siclk(siclk), | |
1188 | .soclk(soclk), | |
1189 | .d(fdin[9:0]), | |
1190 | .si({scan_in,so[8:0]}), | |
1191 | .so({so[8:0],scan_out}), | |
1192 | .q(dout[9:0]) | |
1193 | ); | |
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | endmodule | |
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 |