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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_l2if_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_l2if_ctl ( | |
36 | mcu_ucb_rd_req_in, | |
37 | mcu_ucb_wr_req_in, | |
38 | mcu_l2t_rd_ack, | |
39 | mcu_l2t_wr_ack, | |
40 | l2if_mcu_data_mecc, | |
41 | l2if_data_wr_addr, | |
42 | l2if_wdq_rd_inh, | |
43 | l2if_wdq_we, | |
44 | l2if_wdq_wadr, | |
45 | l2if_wdq_in_cntr, | |
46 | l2if_wr_req, | |
47 | l2if_rd_req, | |
48 | l2if_rd_dummy_req, | |
49 | l2if_rd_dummy_req_addr5, | |
50 | l2if_rd_dummy_req_id, | |
51 | l2if_rd_dummy_addr_err, | |
52 | l2if_rd_rank_adr, | |
53 | l2if_rd_dimm_adr, | |
54 | l2if_rd_bank_adr, | |
55 | l2if_rd_ras_adr, | |
56 | l2if_rd_cas_adr, | |
57 | l2if_rd_addr_err, | |
58 | l2if_rd_addr_parity, | |
59 | l2if_rd_req_id, | |
60 | l2if_wr_rank_adr, | |
61 | l2if_wr_dimm_adr, | |
62 | l2if_wr_bank_adr, | |
63 | l2if_wr_ras_adr, | |
64 | l2if_wr_cas_adr, | |
65 | l2if_wr_addr_err, | |
66 | l2if_wr_addr_parity, | |
67 | l2t_mcu_rd_req, | |
68 | l2t_mcu_rd_dummy_req, | |
69 | l2t_mcu_rd_req_id, | |
70 | l2t_mcu_addr, | |
71 | l2t_mcu_wr_req, | |
72 | l2b_mcu_data_vld, | |
73 | l2b_mcu_data_mecc, | |
74 | drq_rdq_free, | |
75 | woq_wdq_entry_free, | |
76 | drif_stacked_dimm, | |
77 | drif_addr_bank_low_sel, | |
78 | drif_mem_type, | |
79 | drif_num_dimms, | |
80 | drif_single_channel_mode, | |
81 | rdata_pm_1mcu, | |
82 | rdata_pm_2mcu, | |
83 | rdpctl_dummy_data_valid, | |
84 | mbist_run, | |
85 | mbist_addr, | |
86 | mbist_wdata_0, | |
87 | mbist_wdqrf0_wr_en, | |
88 | mbist_wdqrf1_wr_en, | |
89 | ccu_mcu_ddr_cmp_sync_en, | |
90 | ccu_mcu_cmp_ddr_sync_en, | |
91 | ccu_mcu_cmp_io_sync_en, | |
92 | l2clk, | |
93 | scan_in, | |
94 | scan_out, | |
95 | tcu_pce_ov, | |
96 | tcu_aclk, | |
97 | tcu_bclk, | |
98 | tcu_scan_en); | |
99 | wire pce_ov; | |
100 | wire siclk; | |
101 | wire soclk; | |
102 | wire se; | |
103 | wire l1clk; | |
104 | wire ff_mcu_sync_pulses_scanin; | |
105 | wire ff_mcu_sync_pulses_scanout; | |
106 | wire l2if_ddr_cmp_sync_en; | |
107 | wire l2if_cmp_ddr_sync_en; | |
108 | wire l2if_ddr_cmp_sync_en_d1; | |
109 | wire ff_mcu_iosync_pulse_scanin; | |
110 | wire ff_mcu_iosync_pulse_scanout; | |
111 | wire l2if_cmp_io_sync_en; | |
112 | wire ff_wr_req_d1_scanin; | |
113 | wire ff_wr_req_d1_scanout; | |
114 | wire l2if_wr_req_d1; | |
115 | wire ff_wr_req_cpu_scanin; | |
116 | wire ff_wr_req_cpu_scanout; | |
117 | wire l2if_wr_req_cpu; | |
118 | wire l2if_wr_ack; | |
119 | wire ff_rd_req_d1_scanin; | |
120 | wire ff_rd_req_d1_scanout; | |
121 | wire l2t_mcu_rd_req_d1; | |
122 | wire l2t_mcu_rd_dummy_req_d1; | |
123 | wire [2:0] l2t_mcu_rd_req_id_d1; | |
124 | wire ff_addr_scanin; | |
125 | wire ff_addr_scanout; | |
126 | wire [39:5] l2if_addr; | |
127 | wire l2if_pm_l_in; | |
128 | wire ff_partial_mode_scanin; | |
129 | wire ff_partial_mode_scanout; | |
130 | wire l2if_pm_l; | |
131 | wire l2if_pm_1mcu; | |
132 | wire l2if_pm_2mcu; | |
133 | wire ff_mbist_signals_scanin; | |
134 | wire ff_mbist_run_d1_scanout; | |
135 | wire mbist_run_d1; | |
136 | wire ff_mbist_signals_scanout; | |
137 | wire [4:0] mbist_addr_d1; | |
138 | wire mbist_wdata_0_d1; | |
139 | wire mbist_wdqrf0_wr_en_d1; | |
140 | wire mbist_wdqrf1_wr_en_d1; | |
141 | wire l2if_rd_dummy_req_en; | |
142 | wire l2if_rd_dummy_req_clr; | |
143 | wire l2if_rd_dummy_req_cpu; | |
144 | wire ff_l2if_rd_dummy_req_scanin; | |
145 | wire ff_l2if_rd_dummy_req_scanout; | |
146 | wire ff_dummy_req_cpu_scanin; | |
147 | wire ff_dummy_req_cpu_scanout; | |
148 | wire adrgen_addr_err; | |
149 | wire [2:0] l2if_rd_dummy_req_id_cpu; | |
150 | wire l2if_rd_dummy_req_addr5_cpu; | |
151 | wire l2if_rd_dummy_addr_err_cpu; | |
152 | wire ff_dummy_req_data_scanin; | |
153 | wire ff_dummy_req_data_scanout; | |
154 | wire ff_dummy_data_valid_d1_scanin; | |
155 | wire ff_dummy_data_valid_d1_scanout; | |
156 | wire l2if_dummy_data_valid; | |
157 | wire l2if_dummy_data_valid_d1; | |
158 | wire l2if_rd_req_cpu; | |
159 | wire [2:0] l2if_ibuf_state; | |
160 | wire [3:0] l2if_rdq_cnt; | |
161 | wire ff_l2wrreqflop_mcu_scanin; | |
162 | wire ff_l2wrreqflop_mcu_scanout; | |
163 | wire ff_wr_addr_scanin; | |
164 | wire ff_wr_addr_scanout; | |
165 | wire [5:0] l2if_wr_b0_data_addr; | |
166 | wire ff_drq_free_scanin; | |
167 | wire ff_drq_free_scanout; | |
168 | wire l2if_rdq_free_cpu; | |
169 | wire l2if_rdq_free; | |
170 | wire ff_wdq_entry_free_scanin; | |
171 | wire ff_wdq_entry_free_scanout; | |
172 | wire [7:0] l2if_wdq_entry_free; | |
173 | wire ff_dummy_data_valid_scanin; | |
174 | wire ff_dummy_data_valid_scanout; | |
175 | wire ff_addr_mode_scanin; | |
176 | wire ff_addr_mode_scanout; | |
177 | wire l2if_stacked_dimm; | |
178 | wire l2if_addr_bank_low_sel; | |
179 | wire [1:0] l2if_mem_type; | |
180 | wire [2:0] l2if_num_dimms; | |
181 | wire l2if_single_channel_mode; | |
182 | wire [3:0] l2if_rdq_cnt_in; | |
183 | wire l2if_mcu_rd_ack; | |
184 | wire ff_rdq_cnt_scanin; | |
185 | wire ff_rdq_cnt_scanout; | |
186 | wire mcu_l2t_rd_ack_in; | |
187 | wire mcu_l2t_rd_ack_p1; | |
188 | wire ff_rd_ack0_scanin; | |
189 | wire ff_rd_ack0_scanout; | |
190 | wire l2if_wr_entry0; | |
191 | wire l2if_wr_entry1; | |
192 | wire l2if_wr_entry2; | |
193 | wire l2if_wr_entry3; | |
194 | wire l2if_wr_entry4; | |
195 | wire l2if_wr_entry5; | |
196 | wire l2if_wr_entry6; | |
197 | wire l2if_wr_entry7; | |
198 | wire ff_wr_ack_scanin; | |
199 | wire ff_wr_ack_scanout; | |
200 | wire [3:0] l2if_wdq_in_cntr_in; | |
201 | wire l2if_wdq_in_cntr_en; | |
202 | wire l2if_b0_data_vld_d1; | |
203 | wire l2if_b0_data_vld; | |
204 | wire ff_wdq_in_cntr_cpu_scanin; | |
205 | wire ff_wdq_in_cntr_cpu_scanout; | |
206 | wire [3:0] l2if_wdq_in_cntr_cpu; | |
207 | wire ff_wdq_in_cntr_scanin; | |
208 | wire ff_wdq_in_cntr_scanout; | |
209 | wire l2if_mcu_data_mecc_out; | |
210 | wire ff_data_vld_scanin; | |
211 | wire ff_data_vld_scanout; | |
212 | wire [5:0] l2if_wr_b0_data_addr_in; | |
213 | wire [2:0] l2if_first_wdq_entry_free; | |
214 | wire ff_b0_data_addr_scanin; | |
215 | wire ff_b0_data_addr_scanout; | |
216 | wire l2if_mem_rd_inh_in; | |
217 | wire l2if_mem_rd_inh; | |
218 | wire ff_mem_rd_inh_scanin; | |
219 | wire ff_mem_rd_inh_scanout; | |
220 | wire l2if_wdq_rd_inh_in; | |
221 | wire ff_wdq_rd_inh_scanin; | |
222 | wire ff_wdq_rd_inh_scanout; | |
223 | wire l2if_wr_entry0_en; | |
224 | wire l2if_wr_entry0_in; | |
225 | wire ff_wr_ent0_scanin; | |
226 | wire ff_wr_ent0_scanout; | |
227 | wire l2if_wr_entry1_en; | |
228 | wire l2if_wr_entry1_in; | |
229 | wire ff_wr_ent1_scanin; | |
230 | wire ff_wr_ent1_scanout; | |
231 | wire l2if_wr_entry2_en; | |
232 | wire l2if_wr_entry2_in; | |
233 | wire ff_wr_ent2_scanin; | |
234 | wire ff_wr_ent2_scanout; | |
235 | wire l2if_wr_entry3_en; | |
236 | wire l2if_wr_entry3_in; | |
237 | wire ff_wr_ent3_scanin; | |
238 | wire ff_wr_ent3_scanout; | |
239 | wire l2if_wr_entry4_en; | |
240 | wire l2if_wr_entry4_in; | |
241 | wire ff_wr_ent4_scanin; | |
242 | wire ff_wr_ent4_scanout; | |
243 | wire l2if_wr_entry5_en; | |
244 | wire l2if_wr_entry5_in; | |
245 | wire ff_wr_ent5_scanin; | |
246 | wire ff_wr_ent5_scanout; | |
247 | wire l2if_wr_entry6_en; | |
248 | wire l2if_wr_entry6_in; | |
249 | wire ff_wr_ent6_scanin; | |
250 | wire ff_wr_ent6_scanout; | |
251 | wire l2if_wr_entry7_en; | |
252 | wire l2if_wr_entry7_in; | |
253 | wire ff_wr_ent7_scanin; | |
254 | wire ff_wr_ent7_scanout; | |
255 | wire [6:5] l2if_addr_6to5; | |
256 | wire [39:9] l2if_addr_39to9; | |
257 | wire adrgen_addr_err_out; | |
258 | wire adrgen_scanin; | |
259 | wire adrgen_scanout; | |
260 | wire adrgen_rank_adr; | |
261 | wire [2:0] adrgen_dimm_adr; | |
262 | wire [2:0] adrgen_bank_adr; | |
263 | wire [14:0] adrgen_ras_adr; | |
264 | wire [10:0] adrgen_cas_adr; | |
265 | wire adrgen_addr_parity; | |
266 | wire [37:0] l2if_ibuf1_in; | |
267 | wire ff_ibuf1_scanin; | |
268 | wire ff_ibuf1_scanout; | |
269 | wire [37:0] l2if_ibuf1; | |
270 | wire l2if_rd_adr_qfifo1_en; | |
271 | wire [37:0] l2if_ibuf0_in; | |
272 | wire l2if_rd_adr_qfifo0_sel; | |
273 | wire ff_ibuf0_scanin; | |
274 | wire ff_ibuf0_scanout; | |
275 | wire [37:0] l2if_ibuf0; | |
276 | wire l2if_rd_adr_qfifo0_en; | |
277 | wire [0:0] inv_next_l2if_ibuf_state; | |
278 | wire [2:0] next_l2if_ibuf_state; | |
279 | wire [0:0] inv_l2if_ibuf_state; | |
280 | wire ff_ibuf_state_scanin; | |
281 | wire ff_ibuf_state_scanout; | |
282 | wire l2if_wr_adr_qfifo0_en; | |
283 | wire l2if_mcu_rd_req; | |
284 | wire [10:0] adrgen_wr_cas_adr; | |
285 | wire ff_wraddr_scanin; | |
286 | wire ff_wraddr_scanout; | |
287 | wire ucb_l2t_mcu_rd_req_d1; | |
288 | wire [3:0] mcu_ucb_rd_req_in_l1clk_o; | |
289 | wire [2:0] ucb_l2t_mcu_rd_req_id_d1; | |
290 | wire ff_ucb_rd_req_in_scanin; | |
291 | wire ff_ucb_rd_req_in_scanout; | |
292 | wire ff_ucb_sync_rd_req_in_scanin; | |
293 | wire ff_ucb_sync_rd_req_in_scanout; | |
294 | wire ucb_l2t_mcu_wr_req_d1; | |
295 | wire mcu_ucb_wr_req_in_l1clk; | |
296 | wire ff_ucb_wr_req_in_scanin; | |
297 | wire ff_ucb_wr_req_in_scanout; | |
298 | wire ff_ucb_sync_wr_req_in_scanin; | |
299 | wire ff_ucb_sync_wr_req_in_scanout; | |
300 | wire spares_scanin; | |
301 | wire spares_scanout; | |
302 | ||
303 | ||
304 | output [3:0] mcu_ucb_rd_req_in; // signals to send to dbg via ucb | |
305 | output mcu_ucb_wr_req_in; // signals to dbg via ucb | |
306 | ||
307 | output mcu_l2t_rd_ack; // read acknowledge to L2 cache | |
308 | output mcu_l2t_wr_ack; // write acknowledge to L2 cache | |
309 | ||
310 | output l2if_mcu_data_mecc; // To wdq for poisoning write data ecc | |
311 | ||
312 | // write data queue address | |
313 | output [2:0] l2if_data_wr_addr; // wdq write address to write request queue | |
314 | output l2if_wdq_rd_inh; | |
315 | output [1:0] l2if_wdq_we; // write data queue bank write enables | |
316 | output [4:0] l2if_wdq_wadr; // write data queue write address | |
317 | output [3:0] l2if_wdq_in_cntr; // pointer is incremented when all data for a write | |
318 | // has been written to wdq | |
319 | ||
320 | ||
321 | // Going to mcu clk domain | |
322 | output l2if_wr_req; // write request to drif | |
323 | output l2if_rd_req; // read request to drif | |
324 | ||
325 | output l2if_rd_dummy_req; // dummy request info to rdata | |
326 | output l2if_rd_dummy_req_addr5; // dummy request addr bit 5 for qword offset generation | |
327 | output [2:0] l2if_rd_dummy_req_id; // dummy request id to rdata | |
328 | output l2if_rd_dummy_addr_err; // address error bit for mecc generation | |
329 | ||
330 | output l2if_rd_rank_adr; | |
331 | output [2:0] l2if_rd_dimm_adr; | |
332 | output [2:0] l2if_rd_bank_adr; | |
333 | output [14:0] l2if_rd_ras_adr; | |
334 | output [10:0] l2if_rd_cas_adr; | |
335 | output l2if_rd_addr_err; | |
336 | output l2if_rd_addr_parity; | |
337 | output [2:0] l2if_rd_req_id; | |
338 | ||
339 | output l2if_wr_rank_adr; | |
340 | output [2:0] l2if_wr_dimm_adr; | |
341 | output [2:0] l2if_wr_bank_adr; | |
342 | output [14:0] l2if_wr_ras_adr; | |
343 | output [10:0] l2if_wr_cas_adr; | |
344 | output l2if_wr_addr_err; | |
345 | output l2if_wr_addr_parity; | |
346 | ||
347 | // rd interface | |
348 | input l2t_mcu_rd_req; // incoming read request | |
349 | input l2t_mcu_rd_dummy_req; // incoming dummy read request | |
350 | input [2:0] l2t_mcu_rd_req_id; // incoming read request id | |
351 | input [39:5] l2t_mcu_addr; | |
352 | ||
353 | // wr interface | |
354 | input l2t_mcu_wr_req; // incoming write request | |
355 | input l2b_mcu_data_vld; // data valid for write data | |
356 | input l2b_mcu_data_mecc; // poison signal to flip ecc bits for write data | |
357 | ||
358 | input drq_rdq_free; // entry freed in read request queue | |
359 | input [7:0] woq_wdq_entry_free; // write data queue entry to free | |
360 | ||
361 | // address mapping signals | |
362 | input drif_stacked_dimm; | |
363 | input drif_addr_bank_low_sel; | |
364 | input [1:0] drif_mem_type; | |
365 | input [2:0] drif_num_dimms; | |
366 | input drif_single_channel_mode; | |
367 | ||
368 | input rdata_pm_1mcu; | |
369 | input rdata_pm_2mcu; | |
370 | ||
371 | input rdpctl_dummy_data_valid; // pending rdata_ctl dummy read request clear | |
372 | ||
373 | input mbist_run; | |
374 | input [4:0] mbist_addr; | |
375 | input mbist_wdata_0; | |
376 | input mbist_wdqrf0_wr_en; | |
377 | input mbist_wdqrf1_wr_en; | |
378 | ||
379 | // SYNC Pulse | |
380 | input ccu_mcu_ddr_cmp_sync_en; // clock synchonizing signal from mcu to cpu | |
381 | input ccu_mcu_cmp_ddr_sync_en; // clock synchonizing signal from cpu to mcu | |
382 | //## | |
383 | input ccu_mcu_cmp_io_sync_en; // clock synchonizing signal from cpu to mcu | |
384 | ||
385 | // Global Signals | |
386 | input l2clk; | |
387 | input scan_in; | |
388 | output scan_out; | |
389 | input tcu_pce_ov; | |
390 | input tcu_aclk; | |
391 | input tcu_bclk; | |
392 | input tcu_scan_en; | |
393 | ||
394 | // Code | |
395 | assign pce_ov = tcu_pce_ov; | |
396 | assign siclk = tcu_aclk; | |
397 | assign soclk = tcu_bclk; | |
398 | assign se = tcu_scan_en; | |
399 | ||
400 | // 0in set_clock l2clk -default | |
401 | mcu_l2if_ctl_l1clkhdr_ctl_macro clkgen ( | |
402 | .l2clk(l2clk), | |
403 | .l1en (1'b1 ), | |
404 | .stop(1'b0), | |
405 | .l1clk(l1clk), | |
406 | .pce_ov(pce_ov), | |
407 | .se(se)); | |
408 | ||
409 | ////////////////////////////////////////////////////////////////// | |
410 | // Flop L2 input requests | |
411 | ////////////////////////////////////////////////////////////////// | |
412 | ||
413 | mcu_l2if_ctl_msff_ctl_macro__width_3 ff_mcu_sync_pulses ( | |
414 | .scan_in(ff_mcu_sync_pulses_scanin), | |
415 | .scan_out(ff_mcu_sync_pulses_scanout), | |
416 | .din ({ccu_mcu_ddr_cmp_sync_en, ccu_mcu_cmp_ddr_sync_en, l2if_ddr_cmp_sync_en}), | |
417 | .dout ({l2if_ddr_cmp_sync_en, l2if_cmp_ddr_sync_en, l2if_ddr_cmp_sync_en_d1}), | |
418 | .l1clk (l1clk), | |
419 | .siclk(siclk), | |
420 | .soclk(soclk)); | |
421 | //## register the cmp_io_sync_en | |
422 | mcu_l2if_ctl_msff_ctl_macro__width_1 ff_mcu_iosync_pulse ( | |
423 | .scan_in(ff_mcu_iosync_pulse_scanin), | |
424 | .scan_out(ff_mcu_iosync_pulse_scanout), | |
425 | .din (ccu_mcu_cmp_io_sync_en), | |
426 | .dout (l2if_cmp_io_sync_en), | |
427 | .l1clk (l1clk), | |
428 | .siclk(siclk), | |
429 | .soclk(soclk)); | |
430 | ||
431 | mcu_l2if_ctl_msff_ctl_macro__width_1 ff_wr_req_d1 ( | |
432 | .scan_in(ff_wr_req_d1_scanin), | |
433 | .scan_out(ff_wr_req_d1_scanout), | |
434 | .din(l2t_mcu_wr_req), | |
435 | .dout(l2if_wr_req_d1), | |
436 | .l1clk(l1clk), | |
437 | .siclk(siclk), | |
438 | .soclk(soclk)); | |
439 | ||
440 | mcu_l2if_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_wr_req_cpu ( | |
441 | .scan_in(ff_wr_req_cpu_scanin), | |
442 | .scan_out(ff_wr_req_cpu_scanout), | |
443 | .din(l2if_wr_req_d1), | |
444 | .dout(l2if_wr_req_cpu), | |
445 | .en(l2if_wr_req_d1), | |
446 | .clr(l2if_wr_ack), | |
447 | .l1clk(l1clk), | |
448 | .siclk(siclk), | |
449 | .soclk(soclk)); | |
450 | ||
451 | mcu_l2if_ctl_msff_ctl_macro__width_5 ff_rd_req_d1 ( | |
452 | .scan_in(ff_rd_req_d1_scanin), | |
453 | .scan_out(ff_rd_req_d1_scanout), | |
454 | .din({l2t_mcu_rd_req,l2t_mcu_rd_dummy_req,l2t_mcu_rd_req_id[2:0]}), | |
455 | .dout({l2t_mcu_rd_req_d1,l2t_mcu_rd_dummy_req_d1,l2t_mcu_rd_req_id_d1[2:0]}), .l1clk(l1clk), | |
456 | .siclk(siclk), | |
457 | .soclk(soclk)); | |
458 | ||
459 | //assign l2if_rd_req_id[2:0] = l2t_mcu_rd_req_id_d1[2:0]; | |
460 | ||
461 | mcu_l2if_ctl_msff_ctl_macro__width_35 ff_addr ( | |
462 | .scan_in(ff_addr_scanin), | |
463 | .scan_out(ff_addr_scanout), | |
464 | .din(l2t_mcu_addr[39:5]), | |
465 | .dout(l2if_addr[39:5]), | |
466 | .l1clk(l1clk), | |
467 | .siclk(siclk), | |
468 | .soclk(soclk)); | |
469 | ||
470 | assign l2if_pm_l_in = ~(rdata_pm_1mcu | rdata_pm_2mcu); | |
471 | mcu_l2if_ctl_msff_ctl_macro__width_3 ff_partial_mode ( | |
472 | .scan_in(ff_partial_mode_scanin), | |
473 | .scan_out(ff_partial_mode_scanout), | |
474 | .din({l2if_pm_l_in, rdata_pm_1mcu, rdata_pm_2mcu}), | |
475 | .dout({l2if_pm_l, l2if_pm_1mcu, l2if_pm_2mcu}), | |
476 | .l1clk(l1clk), | |
477 | .siclk(siclk), | |
478 | .soclk(soclk)); | |
479 | ||
480 | mcu_l2if_ctl_msff_ctl_macro ff_mbist_run_d1 ( | |
481 | .scan_in(ff_mbist_signals_scanin), | |
482 | .scan_out(ff_mbist_run_d1_scanout), | |
483 | .din(mbist_run), | |
484 | .dout(mbist_run_d1), | |
485 | .l1clk(l1clk), | |
486 | .siclk(siclk), | |
487 | .soclk(soclk)); | |
488 | ||
489 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_8 ff_mbist_signals ( | |
490 | .scan_in(ff_mbist_run_d1_scanout), | |
491 | .scan_out(ff_mbist_signals_scanout), | |
492 | .din({mbist_addr[4:0],mbist_wdata_0,mbist_wdqrf0_wr_en,mbist_wdqrf1_wr_en}), | |
493 | .dout({mbist_addr_d1[4:0],mbist_wdata_0_d1,mbist_wdqrf0_wr_en_d1,mbist_wdqrf1_wr_en_d1}), | |
494 | .en(mbist_run), | |
495 | .l1clk(l1clk), | |
496 | .siclk(siclk), | |
497 | .soclk(soclk)); | |
498 | ||
499 | ||
500 | /////////////////////////////////////////////////////////////////// | |
501 | // dummy request: held until request response goes out; one outstanding | |
502 | // dummy read permitted | |
503 | /////////////////////////////////////////////////////////////////// | |
504 | ||
505 | assign l2if_rd_dummy_req_en = l2t_mcu_rd_req_d1 & l2t_mcu_rd_dummy_req_d1; | |
506 | assign l2if_rd_dummy_req_clr = l2if_rd_dummy_req_cpu & l2if_cmp_ddr_sync_en; | |
507 | mcu_l2if_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_l2if_rd_dummy_req ( | |
508 | .scan_in(ff_l2if_rd_dummy_req_scanin), | |
509 | .scan_out(ff_l2if_rd_dummy_req_scanout), | |
510 | .din(1'b1), | |
511 | .dout(l2if_rd_dummy_req_cpu), | |
512 | .en(l2if_rd_dummy_req_en), | |
513 | .clr(l2if_rd_dummy_req_clr), | |
514 | .l1clk(l1clk), | |
515 | .siclk(siclk), | |
516 | .soclk(soclk)); | |
517 | ||
518 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_5 ff_dummy_req_cpu ( | |
519 | .scan_in(ff_dummy_req_cpu_scanin), | |
520 | .scan_out(ff_dummy_req_cpu_scanout), | |
521 | .din({l2t_mcu_rd_req_id_d1[2:0],l2if_addr[5],adrgen_addr_err}), | |
522 | .dout({l2if_rd_dummy_req_id_cpu[2:0],l2if_rd_dummy_req_addr5_cpu,l2if_rd_dummy_addr_err_cpu}), | |
523 | .en(l2if_rd_dummy_req_en), | |
524 | .l1clk(l1clk), | |
525 | .siclk(siclk), | |
526 | .soclk(soclk)); | |
527 | ||
528 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_6 ff_dummy_req_data ( | |
529 | .scan_in(ff_dummy_req_data_scanin), | |
530 | .scan_out(ff_dummy_req_data_scanout), | |
531 | .din({l2if_rd_dummy_req_cpu,l2if_rd_dummy_req_id_cpu[2:0],l2if_rd_dummy_req_addr5_cpu,l2if_rd_dummy_addr_err_cpu}), | |
532 | .dout({l2if_rd_dummy_req,l2if_rd_dummy_req_id[2:0],l2if_rd_dummy_req_addr5,l2if_rd_dummy_addr_err}), | |
533 | .en(l2if_cmp_ddr_sync_en), | |
534 | .l1clk(l1clk), | |
535 | .siclk(siclk), | |
536 | .soclk(soclk)); | |
537 | ||
538 | mcu_l2if_ctl_msff_ctl_macro ff_dummy_data_valid_d1 ( | |
539 | .scan_in(ff_dummy_data_valid_d1_scanin), | |
540 | .scan_out(ff_dummy_data_valid_d1_scanout), | |
541 | .din(l2if_dummy_data_valid), | |
542 | .dout(l2if_dummy_data_valid_d1), | |
543 | .l1clk(l1clk), | |
544 | .siclk(siclk), | |
545 | .soclk(soclk)); | |
546 | ||
547 | ///////////////////////////////////////////////// | |
548 | // SIGNALS FROM CPU CLK TO DRAM CLK | |
549 | ///////////////////////////////////////////////// | |
550 | ||
551 | assign l2if_rd_req_cpu = ~l2if_ibuf_state[0] & ~l2if_rdq_cnt[3]; | |
552 | ||
553 | // write and read req valids | |
554 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_2 ff_l2wrreqflop_mcu ( | |
555 | .scan_in(ff_l2wrreqflop_mcu_scanin), | |
556 | .scan_out(ff_l2wrreqflop_mcu_scanout), | |
557 | .din({l2if_wr_ack,l2if_rd_req_cpu}), | |
558 | .dout({l2if_wr_req,l2if_rd_req}), | |
559 | .en(l2if_cmp_ddr_sync_en), | |
560 | .l1clk(l1clk), | |
561 | .siclk(siclk), | |
562 | .soclk(soclk)); | |
563 | ||
564 | // data write address into mem | |
565 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_3 ff_wr_addr ( | |
566 | .scan_in(ff_wr_addr_scanin), | |
567 | .scan_out(ff_wr_addr_scanout), | |
568 | .din(l2if_wr_b0_data_addr[5:3]), | |
569 | .dout(l2if_data_wr_addr[2:0]), | |
570 | .en(l2if_cmp_ddr_sync_en), | |
571 | .l1clk(l1clk), | |
572 | .siclk(siclk), | |
573 | .soclk(soclk)); | |
574 | ||
575 | ///////////////////////////////////////////////// | |
576 | // SIGNALS FROM DRAM CLK TO CPU CLK | |
577 | ///////////////////////////////////////////////// | |
578 | ||
579 | // mcu to cpu clk domain of the buffer valids | |
580 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_drq_free ( | |
581 | .scan_in(ff_drq_free_scanin), | |
582 | .scan_out(ff_drq_free_scanout), | |
583 | .din(drq_rdq_free), | |
584 | .dout(l2if_rdq_free_cpu), | |
585 | .en(l2if_ddr_cmp_sync_en), | |
586 | .l1clk(l1clk), | |
587 | .siclk(siclk), | |
588 | .soclk(soclk)); | |
589 | ||
590 | assign l2if_rdq_free = l2if_rdq_free_cpu & l2if_ddr_cmp_sync_en_d1; | |
591 | ||
592 | // flop write data entry free | |
593 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_8 ff_wdq_entry_free ( | |
594 | .scan_in(ff_wdq_entry_free_scanin), | |
595 | .scan_out(ff_wdq_entry_free_scanout), | |
596 | .din(woq_wdq_entry_free[7:0]), | |
597 | .dout(l2if_wdq_entry_free[7:0]), | |
598 | .en(l2if_ddr_cmp_sync_en), | |
599 | .l1clk(l1clk), | |
600 | .siclk(siclk), | |
601 | .soclk(soclk)); | |
602 | ||
603 | mcu_l2if_ctl_msff_ctl_macro__en_1 ff_dummy_data_valid ( | |
604 | .scan_in(ff_dummy_data_valid_scanin), | |
605 | .scan_out(ff_dummy_data_valid_scanout), | |
606 | .din(rdpctl_dummy_data_valid), | |
607 | .dout(l2if_dummy_data_valid), | |
608 | .en(l2if_ddr_cmp_sync_en), | |
609 | .l1clk(l1clk), | |
610 | .siclk(siclk), | |
611 | .soclk(soclk)); | |
612 | ||
613 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_8 ff_addr_mode ( | |
614 | .scan_in(ff_addr_mode_scanin), | |
615 | .scan_out(ff_addr_mode_scanout), | |
616 | .din({drif_stacked_dimm,drif_addr_bank_low_sel,drif_mem_type[1:0],drif_num_dimms[2:0],drif_single_channel_mode}), | |
617 | .dout({l2if_stacked_dimm,l2if_addr_bank_low_sel,l2if_mem_type[1:0],l2if_num_dimms[2:0],l2if_single_channel_mode}), | |
618 | .en(l2if_ddr_cmp_sync_en), | |
619 | .l1clk(l1clk), | |
620 | .siclk(siclk), | |
621 | .soclk(soclk)); | |
622 | ||
623 | ////////////////////////////////////////////////////////////////// | |
624 | // Generate the ack for L2 | |
625 | ////////////////////////////////////////////////////////////////// | |
626 | ||
627 | // keep track of outstanding read requests; L2 may send another request before req id is cleared | |
628 | // from read request queue | |
629 | assign l2if_rdq_cnt_in[3:0] = l2if_mcu_rd_ack & ~l2if_rdq_free ? l2if_rdq_cnt[3:0] + 4'h1 : | |
630 | ~l2if_mcu_rd_ack & l2if_rdq_free ? l2if_rdq_cnt[3:0] - 4'h1 : l2if_rdq_cnt[3:0]; | |
631 | ||
632 | mcu_l2if_ctl_msff_ctl_macro__width_4 ff_rdq_cnt ( | |
633 | .scan_in(ff_rdq_cnt_scanin), | |
634 | .scan_out(ff_rdq_cnt_scanout), | |
635 | .din(l2if_rdq_cnt_in[3:0]), | |
636 | .dout(l2if_rdq_cnt[3:0]), | |
637 | .l1clk(l1clk), | |
638 | .siclk(siclk), | |
639 | .soclk(soclk)); | |
640 | ||
641 | // Read Ack | |
642 | ||
643 | // domain crossing ack - input to 2-deep read request buffer state machine | |
644 | assign l2if_mcu_rd_ack = l2if_rd_req_cpu & l2if_cmp_ddr_sync_en; | |
645 | ||
646 | // ack based on 2-deep buffer requests | |
647 | assign mcu_l2t_rd_ack_in = mcu_l2t_rd_ack_p1 | l2if_dummy_data_valid & ~l2if_dummy_data_valid_d1; | |
648 | mcu_l2if_ctl_msff_ctl_macro__width_1 ff_rd_ack0 ( | |
649 | .scan_in(ff_rd_ack0_scanin), | |
650 | .scan_out(ff_rd_ack0_scanout), | |
651 | .din(mcu_l2t_rd_ack_in), | |
652 | .dout(mcu_l2t_rd_ack), | |
653 | .l1clk(l1clk), | |
654 | .siclk(siclk), | |
655 | .soclk(soclk)); | |
656 | ||
657 | // Write Ack logic | |
658 | assign l2if_wr_ack = ~(l2if_wr_entry0 & l2if_wr_entry1 & l2if_wr_entry2 & l2if_wr_entry3 & | |
659 | l2if_wr_entry4 & l2if_wr_entry5 & l2if_wr_entry6 & l2if_wr_entry7) & | |
660 | l2if_wr_req_cpu & l2if_cmp_ddr_sync_en; | |
661 | ||
662 | mcu_l2if_ctl_msff_ctl_macro__width_1 ff_wr_ack ( | |
663 | .scan_in(ff_wr_ack_scanin), | |
664 | .scan_out(ff_wr_ack_scanout), | |
665 | .din(l2if_wr_ack), | |
666 | .dout(mcu_l2t_wr_ack), | |
667 | .l1clk(l1clk), | |
668 | .siclk(siclk), | |
669 | .soclk(soclk)); | |
670 | ||
671 | // Find falling edge of data valid signal to increment wdq pointer. This counter | |
672 | // value is used by drq in mcu clock domain to know when all write data is in the | |
673 | // wdq. | |
674 | ||
675 | assign l2if_wdq_in_cntr_in[3:0] = l2if_wdq_in_cntr[3:0] + 4'h1; | |
676 | assign l2if_wdq_in_cntr_en = l2if_b0_data_vld_d1 & ~l2if_b0_data_vld & ~l2if_wr_addr_err; | |
677 | ||
678 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_4 ff_wdq_in_cntr_cpu ( | |
679 | .scan_in(ff_wdq_in_cntr_cpu_scanin), | |
680 | .scan_out(ff_wdq_in_cntr_cpu_scanout), | |
681 | .din(l2if_wdq_in_cntr_in[3:0]), | |
682 | .dout(l2if_wdq_in_cntr_cpu[3:0]), | |
683 | .en(l2if_wdq_in_cntr_en), | |
684 | .l1clk(l1clk), | |
685 | .siclk(siclk), | |
686 | .soclk(soclk)); | |
687 | ||
688 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_4 ff_wdq_in_cntr ( | |
689 | .scan_in(ff_wdq_in_cntr_scanin), | |
690 | .scan_out(ff_wdq_in_cntr_scanout), | |
691 | .din(l2if_wdq_in_cntr_cpu[3:0]), | |
692 | .dout(l2if_wdq_in_cntr[3:0]), | |
693 | .en(l2if_cmp_ddr_sync_en), | |
694 | .l1clk(l1clk), | |
695 | .siclk(siclk), | |
696 | .soclk(soclk)); | |
697 | ||
698 | ////////////////////////////////////////////////////////////////// | |
699 | // Generate address and enable for writing data into arrays. | |
700 | ////////////////////////////////////////////////////////////////// | |
701 | ||
702 | assign l2if_mcu_data_mecc = mbist_run_d1 ? mbist_wdata_0_d1 : l2if_mcu_data_mecc_out; | |
703 | ||
704 | // stage data valid | |
705 | mcu_l2if_ctl_msff_ctl_macro__width_3 ff_data_vld ( | |
706 | .scan_in(ff_data_vld_scanin), | |
707 | .scan_out(ff_data_vld_scanout), | |
708 | .din({l2b_mcu_data_vld, l2if_b0_data_vld, l2b_mcu_data_mecc}), | |
709 | .dout({l2if_b0_data_vld, l2if_b0_data_vld_d1, l2if_mcu_data_mecc_out}), | |
710 | .l1clk(l1clk), | |
711 | .siclk(siclk), | |
712 | .soclk(soclk)); | |
713 | ||
714 | // generate enable for write | |
715 | assign l2if_wdq_we[1:0] = mbist_run_d1 ? {mbist_wdqrf1_wr_en_d1, mbist_wdqrf0_wr_en_d1} : {2{l2if_b0_data_vld}} & {~l2if_wr_b0_data_addr[0],l2if_wr_b0_data_addr[0]}; | |
716 | ||
717 | // generate the index into the array | |
718 | // When data valid is high just increment the address to write into that location. | |
719 | // When its low, eval only when the data valid is just gone low and there is no pending req at that time | |
720 | // and also tha there is some entry empty. If all entries are occupied, then check for entry that's | |
721 | // getting free and make that as free entry. By default it will keep its old value. | |
722 | assign l2if_wr_b0_data_addr_in[5:0] = l2if_b0_data_vld ? {l2if_wr_b0_data_addr[5:3], l2if_wr_b0_data_addr[2:0] + 3'h1} : | |
723 | (~l2if_wr_entry0 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h0 : | |
724 | ~l2if_wr_entry1 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h8 : | |
725 | ~l2if_wr_entry2 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h10 : | |
726 | ~l2if_wr_entry3 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h18 : | |
727 | ~l2if_wr_entry4 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h20 : | |
728 | ~l2if_wr_entry5 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h28 : | |
729 | ~l2if_wr_entry6 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h30 : | |
730 | ~l2if_wr_entry7 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h38 : | |
731 | l2if_wr_entry0 & l2if_wr_entry1 & l2if_wr_entry2 & l2if_wr_entry3 & | |
732 | l2if_wr_entry4 & l2if_wr_entry5 & l2if_wr_entry6 & l2if_wr_entry7 & | |
733 | (|l2if_wdq_entry_free[7:0]) ? {l2if_first_wdq_entry_free[2:0],3'h0} : | |
734 | l2if_wr_b0_data_addr[5:0]); | |
735 | ||
736 | assign l2if_first_wdq_entry_free[2:0] = l2if_wdq_entry_free[1] ? 3'h1 : | |
737 | l2if_wdq_entry_free[2] ? 3'h2 : | |
738 | l2if_wdq_entry_free[3] ? 3'h3 : | |
739 | l2if_wdq_entry_free[4] ? 3'h4 : | |
740 | l2if_wdq_entry_free[5] ? 3'h5 : | |
741 | l2if_wdq_entry_free[6] ? 3'h6 : | |
742 | l2if_wdq_entry_free[7] ? 3'h7 : 3'h0; | |
743 | ||
744 | mcu_l2if_ctl_msff_ctl_macro__width_6 ff_b0_data_addr ( | |
745 | .scan_in(ff_b0_data_addr_scanin), | |
746 | .scan_out(ff_b0_data_addr_scanout), | |
747 | .din(l2if_wr_b0_data_addr_in[5:0]), | |
748 | .dout(l2if_wr_b0_data_addr[5:0]), | |
749 | .l1clk(l1clk), | |
750 | .siclk(siclk), | |
751 | .soclk(soclk)); | |
752 | ||
753 | assign l2if_wdq_wadr[4:0] = mbist_run_d1 ? mbist_addr_d1[4:0] : l2if_wr_b0_data_addr[5:1]; | |
754 | ||
755 | assign l2if_mem_rd_inh_in = l2if_wr_ack ? 1'b1 : l2if_wr_b0_data_addr[2:0] == 3'h7 ? 1'b0 : l2if_mem_rd_inh; | |
756 | ||
757 | mcu_l2if_ctl_msff_ctl_macro ff_mem_rd_inh ( | |
758 | .scan_in(ff_mem_rd_inh_scanin), | |
759 | .scan_out(ff_mem_rd_inh_scanout), | |
760 | .din(l2if_mem_rd_inh_in), | |
761 | .dout(l2if_mem_rd_inh), | |
762 | .l1clk(l1clk), | |
763 | .siclk(siclk), | |
764 | .soclk(soclk)); | |
765 | ||
766 | assign l2if_wdq_rd_inh_in = l2if_wr_ack | l2if_mem_rd_inh; | |
767 | mcu_l2if_ctl_msff_ctl_macro__en_1 ff_wdq_rd_inh ( | |
768 | .scan_in(ff_wdq_rd_inh_scanin), | |
769 | .scan_out(ff_wdq_rd_inh_scanout), | |
770 | .din(l2if_wdq_rd_inh_in), | |
771 | .dout(l2if_wdq_rd_inh), | |
772 | .en(l2if_cmp_ddr_sync_en), | |
773 | .l1clk(l1clk), | |
774 | .siclk(siclk), | |
775 | .soclk(soclk)); | |
776 | ||
777 | // Keep track of in use wdq entries. A 1 means its in use or else free. | |
778 | // Keep it free if there was address error in write address. The write is silently dropped. | |
779 | assign l2if_wr_entry0_en = l2if_wdq_entry_free[0] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
780 | (l2if_wr_b0_data_addr[5:3] == 3'h0); | |
781 | assign l2if_wr_entry0_in = ~l2if_wdq_entry_free[0]; | |
782 | ||
783 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent0 ( | |
784 | .scan_in(ff_wr_ent0_scanin), | |
785 | .scan_out(ff_wr_ent0_scanout), | |
786 | .din(l2if_wr_entry0_in), | |
787 | .dout(l2if_wr_entry0), | |
788 | .en(l2if_wr_entry0_en), | |
789 | .l1clk(l1clk), | |
790 | .siclk(siclk), | |
791 | .soclk(soclk)); | |
792 | ||
793 | assign l2if_wr_entry1_en = l2if_wdq_entry_free[1] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
794 | (l2if_wr_b0_data_addr[5:3] == 3'h1); | |
795 | assign l2if_wr_entry1_in = ~l2if_wdq_entry_free[1]; | |
796 | ||
797 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent1 ( | |
798 | .scan_in(ff_wr_ent1_scanin), | |
799 | .scan_out(ff_wr_ent1_scanout), | |
800 | .din(l2if_wr_entry1_in), | |
801 | .dout(l2if_wr_entry1), | |
802 | .en(l2if_wr_entry1_en), | |
803 | .l1clk(l1clk), | |
804 | .siclk(siclk), | |
805 | .soclk(soclk)); | |
806 | ||
807 | assign l2if_wr_entry2_en = l2if_wdq_entry_free[2] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
808 | (l2if_wr_b0_data_addr[5:3] == 3'h2); | |
809 | assign l2if_wr_entry2_in = ~l2if_wdq_entry_free[2]; | |
810 | ||
811 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent2 ( | |
812 | .scan_in(ff_wr_ent2_scanin), | |
813 | .scan_out(ff_wr_ent2_scanout), | |
814 | .din(l2if_wr_entry2_in), | |
815 | .dout(l2if_wr_entry2), | |
816 | .en(l2if_wr_entry2_en), | |
817 | .l1clk(l1clk), | |
818 | .siclk(siclk), | |
819 | .soclk(soclk)); | |
820 | ||
821 | assign l2if_wr_entry3_en = l2if_wdq_entry_free[3] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
822 | (l2if_wr_b0_data_addr[5:3] == 3'h3); | |
823 | assign l2if_wr_entry3_in = ~l2if_wdq_entry_free[3]; | |
824 | ||
825 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent3 ( | |
826 | .scan_in(ff_wr_ent3_scanin), | |
827 | .scan_out(ff_wr_ent3_scanout), | |
828 | .din(l2if_wr_entry3_in), | |
829 | .dout(l2if_wr_entry3), | |
830 | .en(l2if_wr_entry3_en), | |
831 | .l1clk(l1clk), | |
832 | .siclk(siclk), | |
833 | .soclk(soclk)); | |
834 | ||
835 | assign l2if_wr_entry4_en = l2if_wdq_entry_free[4] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
836 | (l2if_wr_b0_data_addr[5:3] == 3'h4); | |
837 | assign l2if_wr_entry4_in = ~l2if_wdq_entry_free[4]; | |
838 | ||
839 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent4 ( | |
840 | .scan_in(ff_wr_ent4_scanin), | |
841 | .scan_out(ff_wr_ent4_scanout), | |
842 | .din(l2if_wr_entry4_in), | |
843 | .dout(l2if_wr_entry4), | |
844 | .en(l2if_wr_entry4_en), | |
845 | .l1clk(l1clk), | |
846 | .siclk(siclk), | |
847 | .soclk(soclk)); | |
848 | ||
849 | assign l2if_wr_entry5_en = l2if_wdq_entry_free[5] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
850 | (l2if_wr_b0_data_addr[5:3] == 3'h5); | |
851 | assign l2if_wr_entry5_in = ~l2if_wdq_entry_free[5]; | |
852 | ||
853 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent5 ( | |
854 | .scan_in(ff_wr_ent5_scanin), | |
855 | .scan_out(ff_wr_ent5_scanout), | |
856 | .din(l2if_wr_entry5_in), | |
857 | .dout(l2if_wr_entry5), | |
858 | .en(l2if_wr_entry5_en), | |
859 | .l1clk(l1clk), | |
860 | .siclk(siclk), | |
861 | .soclk(soclk)); | |
862 | ||
863 | assign l2if_wr_entry6_en = l2if_wdq_entry_free[6] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
864 | (l2if_wr_b0_data_addr[5:3] == 3'h6); | |
865 | assign l2if_wr_entry6_in = ~l2if_wdq_entry_free[6]; | |
866 | ||
867 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent6 ( | |
868 | .scan_in(ff_wr_ent6_scanin), | |
869 | .scan_out(ff_wr_ent6_scanout), | |
870 | .din(l2if_wr_entry6_in), | |
871 | .dout(l2if_wr_entry6), | |
872 | .en(l2if_wr_entry6_en), | |
873 | .l1clk(l1clk), | |
874 | .siclk(siclk), | |
875 | .soclk(soclk)); | |
876 | ||
877 | assign l2if_wr_entry7_en = l2if_wdq_entry_free[7] | ~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 & | |
878 | (l2if_wr_b0_data_addr[5:3] == 3'h7); | |
879 | assign l2if_wr_entry7_in = ~l2if_wdq_entry_free[7]; | |
880 | ||
881 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_wr_ent7 ( | |
882 | .scan_in(ff_wr_ent7_scanin), | |
883 | .scan_out(ff_wr_ent7_scanout), | |
884 | .din(l2if_wr_entry7_in), | |
885 | .dout(l2if_wr_entry7), | |
886 | .en(l2if_wr_entry7_en), | |
887 | .l1clk(l1clk), | |
888 | .siclk(siclk), | |
889 | .soclk(soclk)); | |
890 | ||
891 | ////////////////////////////////////////////////////////////////////// | |
892 | // Address mapping | |
893 | ////////////////////////////////////////////////////////////////////// | |
894 | ||
895 | assign l2if_addr_6to5[6:5] = l2if_addr[6:5]; | |
896 | assign l2if_addr_39to9[39:9] = {31{l2if_pm_l}} & l2if_addr[39:9] | | |
897 | {31{l2if_pm_2mcu}} & l2if_addr[38:8] | | |
898 | {31{l2if_pm_1mcu}} & l2if_addr[37:7]; | |
899 | ||
900 | assign adrgen_addr_err = adrgen_addr_err_out | | |
901 | l2if_addr[39] & (l2if_pm_2mcu | l2if_pm_1mcu | l2if_single_channel_mode) | | |
902 | l2if_addr[38] & (l2if_pm_1mcu | l2if_pm_2mcu & l2if_single_channel_mode) | | |
903 | l2if_addr[37] & l2if_pm_1mcu & l2if_single_channel_mode; | |
904 | ||
905 | mcu_adrgen_ctl adrgen ( | |
906 | .scan_in(adrgen_scanin), | |
907 | .scan_out(adrgen_scanout), | |
908 | .l1clk(l1clk), | |
909 | .adrgen_rank(adrgen_rank_adr), | |
910 | .adrgen_dimm(adrgen_dimm_adr[2:0]), | |
911 | .adrgen_bank(adrgen_bank_adr[2:0]), | |
912 | .adrgen_row_addr(adrgen_ras_adr[14:0]), | |
913 | .adrgen_col_addr(adrgen_cas_adr[10:0]), | |
914 | .adrgen_addr_err(adrgen_addr_err_out), | |
915 | .adrgen_addr_parity(adrgen_addr_parity), | |
916 | .addr_39to9(l2if_addr_39to9[39:9]), | |
917 | .addr_6to5(l2if_addr_6to5[6:5]), | |
918 | .stacked_dimm(l2if_stacked_dimm), | |
919 | .addr_bank_low_sel(l2if_addr_bank_low_sel), | |
920 | .mem_type(l2if_mem_type[1:0]), | |
921 | .sngl_chnl_mode(l2if_single_channel_mode), | |
922 | .num_dimms(l2if_num_dimms[2:0]), | |
923 | .tcu_aclk(tcu_aclk), | |
924 | .tcu_bclk(tcu_bclk), | |
925 | .tcu_scan_en(tcu_scan_en) | |
926 | ); | |
927 | ||
928 | ////////////////////////////////////////////////////////////////////// | |
929 | // Two-entry input fifo for read requests | |
930 | ////////////////////////////////////////////////////////////////////// | |
931 | ||
932 | assign l2if_ibuf1_in[37:0] = {adrgen_addr_err,adrgen_addr_parity,adrgen_rank_adr,adrgen_dimm_adr[2:0], | |
933 | adrgen_bank_adr[2:0],adrgen_ras_adr[14:0],adrgen_cas_adr[10:0],l2t_mcu_rd_req_id_d1[2:0]}; | |
934 | ||
935 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_38 ff_ibuf1 ( | |
936 | .scan_in(ff_ibuf1_scanin), | |
937 | .scan_out(ff_ibuf1_scanout), | |
938 | .din(l2if_ibuf1_in[37:0]), | |
939 | .dout(l2if_ibuf1[37:0]), | |
940 | .en(l2if_rd_adr_qfifo1_en), | |
941 | .l1clk(l1clk), | |
942 | .siclk(siclk), | |
943 | .soclk(soclk)); | |
944 | ||
945 | assign l2if_ibuf0_in[37:0] = l2if_rd_adr_qfifo0_sel ? l2if_ibuf1[37:0] : l2if_ibuf1_in[37:0]; | |
946 | ||
947 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_38 ff_ibuf0 ( | |
948 | .scan_in(ff_ibuf0_scanin), | |
949 | .scan_out(ff_ibuf0_scanout), | |
950 | .din(l2if_ibuf0_in[37:0]), | |
951 | .dout(l2if_ibuf0[37:0]), | |
952 | .en(l2if_rd_adr_qfifo0_en), | |
953 | .l1clk(l1clk), | |
954 | .siclk(siclk), | |
955 | .soclk(soclk)); | |
956 | ||
957 | assign {l2if_rd_addr_err,l2if_rd_addr_parity,l2if_rd_rank_adr,l2if_rd_dimm_adr[2:0],l2if_rd_bank_adr[2:0], | |
958 | l2if_rd_ras_adr[14:0], l2if_rd_cas_adr[10:0],l2if_rd_req_id[2:0]} = l2if_ibuf0[37:0]; | |
959 | ||
960 | ////////////////////////////////////////////////////////////////////// | |
961 | // State machine to control the two-entry input fifo for read requests | |
962 | ////////////////////////////////////////////////////////////////////// | |
963 | ||
964 | assign inv_next_l2if_ibuf_state[0] = ~next_l2if_ibuf_state[0]; | |
965 | assign l2if_ibuf_state[0] = ~inv_l2if_ibuf_state[0]; | |
966 | ||
967 | // 0in one_hot -var l2if_ibuf_state[2:0] | |
968 | mcu_l2if_ctl_msff_ctl_macro__width_3 ff_ibuf_state ( | |
969 | .scan_in(ff_ibuf_state_scanin), | |
970 | .scan_out(ff_ibuf_state_scanout), | |
971 | .din({next_l2if_ibuf_state[2:1],inv_next_l2if_ibuf_state[0]}), | |
972 | .dout({l2if_ibuf_state[2:1],inv_l2if_ibuf_state[0]}), | |
973 | .l1clk(l1clk), | |
974 | .siclk(siclk), | |
975 | .soclk(soclk)); | |
976 | ||
977 | assign l2if_wr_adr_qfifo0_en = l2if_wr_req_d1; | |
978 | assign l2if_mcu_rd_req = l2t_mcu_rd_req_d1 & ~l2t_mcu_rd_dummy_req_d1; | |
979 | ||
980 | assign mcu_l2t_rd_ack_p1 = l2if_ibuf_state[0] & l2if_mcu_rd_req | | |
981 | l2if_ibuf_state[1] & l2if_mcu_rd_ack & l2if_mcu_rd_req | | |
982 | l2if_ibuf_state[2] & l2if_mcu_rd_ack; | |
983 | assign l2if_rd_adr_qfifo0_en = mcu_l2t_rd_ack_p1; | |
984 | assign l2if_rd_adr_qfifo0_sel = l2if_ibuf_state[2] & l2if_mcu_rd_ack; | |
985 | assign l2if_rd_adr_qfifo1_en = l2if_ibuf_state[1] & l2if_mcu_rd_req & ~l2if_mcu_rd_ack; | |
986 | ||
987 | assign next_l2if_ibuf_state[2] = l2if_ibuf_state[1] & l2if_mcu_rd_req & ~l2if_mcu_rd_ack | | |
988 | l2if_ibuf_state[2] & ~l2if_mcu_rd_ack; | |
989 | assign next_l2if_ibuf_state[1] = l2if_ibuf_state[0] & l2if_mcu_rd_req | | |
990 | l2if_ibuf_state[1] & (l2if_mcu_rd_ack & l2if_mcu_rd_req | ~l2if_mcu_rd_ack & ~l2if_mcu_rd_req) | | |
991 | l2if_ibuf_state[2] & l2if_mcu_rd_ack; | |
992 | assign next_l2if_ibuf_state[0] = l2if_ibuf_state[1] & l2if_mcu_rd_ack & ~l2if_mcu_rd_req | | |
993 | l2if_ibuf_state[0] & ~l2if_mcu_rd_req; | |
994 | ||
995 | /////////////////////////////////////////////////////// | |
996 | // Input register for write address | |
997 | /////////////////////////////////////////////////////// | |
998 | ||
999 | // mask off bit 2 (32-byte alignment bit) if in single channel mode | |
1000 | // bits 1 and 0 are always 1'b0 for writes | |
1001 | assign adrgen_wr_cas_adr[10:0] = {adrgen_cas_adr[10:3], adrgen_cas_adr[2] & ~l2if_single_channel_mode, 2'h0}; | |
1002 | ||
1003 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_35 ff_wraddr ( | |
1004 | .scan_in(ff_wraddr_scanin), | |
1005 | .scan_out(ff_wraddr_scanout), | |
1006 | .din({adrgen_addr_err,adrgen_addr_parity,adrgen_rank_adr,adrgen_dimm_adr[2:0], | |
1007 | adrgen_bank_adr[2:0],adrgen_ras_adr[14:0], adrgen_wr_cas_adr[10:0]}), | |
1008 | .dout({l2if_wr_addr_err,l2if_wr_addr_parity,l2if_wr_rank_adr,l2if_wr_dimm_adr[2:0], | |
1009 | l2if_wr_bank_adr[2:0],l2if_wr_ras_adr[14:0],l2if_wr_cas_adr[10:0]}), | |
1010 | .en(l2if_wr_adr_qfifo0_en), | |
1011 | .l1clk(l1clk), | |
1012 | .siclk(siclk), | |
1013 | .soclk(soclk)); | |
1014 | ||
1015 | //always @(l2if_mcu_rd_req or l2if_mcu_rd_ack or l2if_ibuf_state) begin | |
1016 | // next_l2if_ibuf_state[2:0] = l2if_ibuf_state[2:0]; | |
1017 | // l2if_rd_adr_qfifo0_en = 1'b0; | |
1018 | // l2if_rd_adr_qfifo0_sel = 1'b0; | |
1019 | // l2if_rd_adr_qfifo1_en = 1'b0; | |
1020 | // mcu_l2t_rd_ack_p1 = 1'b0; | |
1021 | // | |
1022 | // case (1'b1) // synopsys full_case parallel_case | |
1023 | // | |
1024 | // // No entries used | |
1025 | // l2if_ibuf_state[0]: if (l2if_mcu_rd_req) begin | |
1026 | // next_l2if_ibuf_state[2:0] = 3'b010; | |
1027 | // l2if_rd_adr_qfifo0_en = 1'b1; | |
1028 | // l2if_rd_adr_qfifo0_sel = 1'b0; | |
1029 | // mcu_l2t_rd_ack_p1 = 1'b1; | |
1030 | // end | |
1031 | // | |
1032 | // // One entry used | |
1033 | // l2if_ibuf_state[1]: if (l2if_mcu_rd_req & ~l2if_mcu_rd_ack) begin | |
1034 | // next_l2if_ibuf_state[2:0] = 3'b100; | |
1035 | // l2if_rd_adr_qfifo1_en = 1'b1; | |
1036 | // end | |
1037 | // else if (l2if_mcu_rd_ack & ~l2if_mcu_rd_req) begin | |
1038 | // next_l2if_ibuf_state[2:0] = 3'b001; | |
1039 | // end | |
1040 | // else if (l2if_mcu_rd_ack & l2if_mcu_rd_req) begin | |
1041 | // next_l2if_ibuf_state[2:0] = 3'b010; | |
1042 | // l2if_rd_adr_qfifo0_en = 1'b1; | |
1043 | // l2if_rd_adr_qfifo0_sel = 1'b0; | |
1044 | // mcu_l2t_rd_ack_p1 = 1'b1; | |
1045 | // end | |
1046 | // | |
1047 | // // Both entries used | |
1048 | // l2if_ibuf_state[2]: if (l2if_mcu_rd_ack) begin | |
1049 | // next_l2if_ibuf_state[2:0] = 3'b010; | |
1050 | // l2if_rd_adr_qfifo0_en = 1'b1; | |
1051 | // l2if_rd_adr_qfifo0_sel = 1'b1; | |
1052 | // mcu_l2t_rd_ack_p1 = 1'b1; | |
1053 | // end | |
1054 | // | |
1055 | // default: ; | |
1056 | // | |
1057 | // endcase | |
1058 | //end | |
1059 | ||
1060 | //## implement the crossing domain logic | |
1061 | assign ucb_l2t_mcu_rd_req_d1 = l2t_mcu_rd_req_d1 ? 1'b1 : l2if_cmp_io_sync_en ? 1'b0 : mcu_ucb_rd_req_in_l1clk_o[3]; | |
1062 | assign ucb_l2t_mcu_rd_req_id_d1[2:0] = l2t_mcu_rd_req_d1 ? l2t_mcu_rd_req_id_d1[2:0] : | |
1063 | l2if_cmp_io_sync_en ? 3'h0 : mcu_ucb_rd_req_in_l1clk_o[2:0]; | |
1064 | ||
1065 | mcu_l2if_ctl_msff_ctl_macro__width_4 ff_ucb_rd_req_in ( | |
1066 | .scan_in(ff_ucb_rd_req_in_scanin), | |
1067 | .scan_out(ff_ucb_rd_req_in_scanout), | |
1068 | .din({ucb_l2t_mcu_rd_req_d1, ucb_l2t_mcu_rd_req_id_d1[2:0]}), | |
1069 | .dout(mcu_ucb_rd_req_in_l1clk_o[3:0]), | |
1070 | .l1clk(l1clk), | |
1071 | .siclk(siclk), | |
1072 | .soclk(soclk)); | |
1073 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_4 ff_ucb_sync_rd_req_in ( | |
1074 | .scan_in(ff_ucb_sync_rd_req_in_scanin), | |
1075 | .scan_out(ff_ucb_sync_rd_req_in_scanout), | |
1076 | .din (mcu_ucb_rd_req_in_l1clk_o[3:0]), | |
1077 | .dout (mcu_ucb_rd_req_in[3:0]), | |
1078 | .en (l2if_cmp_io_sync_en), | |
1079 | .l1clk(l1clk), | |
1080 | .siclk(siclk), | |
1081 | .soclk(soclk)); | |
1082 | ||
1083 | assign ucb_l2t_mcu_wr_req_d1 = l2if_wr_req_d1 ? 1'b1 : l2if_cmp_io_sync_en ? 1'b0 : mcu_ucb_wr_req_in_l1clk ; | |
1084 | ||
1085 | mcu_l2if_ctl_msff_ctl_macro__width_1 ff_ucb_wr_req_in ( | |
1086 | .scan_in(ff_ucb_wr_req_in_scanin), | |
1087 | .scan_out(ff_ucb_wr_req_in_scanout), | |
1088 | .din(ucb_l2t_mcu_wr_req_d1), | |
1089 | .dout(mcu_ucb_wr_req_in_l1clk), | |
1090 | .l1clk(l1clk), | |
1091 | .siclk(siclk), | |
1092 | .soclk(soclk)); | |
1093 | ||
1094 | mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ff_ucb_sync_wr_req_in ( | |
1095 | .scan_in(ff_ucb_sync_wr_req_in_scanin), | |
1096 | .scan_out(ff_ucb_sync_wr_req_in_scanout), | |
1097 | .din(mcu_ucb_wr_req_in_l1clk), | |
1098 | .dout(mcu_ucb_wr_req_in), | |
1099 | .en (l2if_cmp_io_sync_en), | |
1100 | .l1clk(l1clk), | |
1101 | .siclk(siclk), | |
1102 | .soclk(soclk)); | |
1103 | ||
1104 | // spare gates | |
1105 | mcu_l2if_ctl_spare_ctl_macro__num_4 spares ( | |
1106 | .scan_in(spares_scanin), | |
1107 | .scan_out(spares_scanout), | |
1108 | .l1clk(l1clk), | |
1109 | .siclk(siclk), | |
1110 | .soclk(soclk) | |
1111 | ); | |
1112 | ||
1113 | // fixscan start: | |
1114 | assign ff_mcu_sync_pulses_scanin = scan_in ; | |
1115 | assign ff_mcu_iosync_pulse_scanin = ff_mcu_sync_pulses_scanout; | |
1116 | assign ff_wr_req_d1_scanin = ff_mcu_iosync_pulse_scanout; | |
1117 | assign ff_wr_req_cpu_scanin = ff_wr_req_d1_scanout ; | |
1118 | assign ff_rd_req_d1_scanin = ff_wr_req_cpu_scanout ; | |
1119 | assign ff_addr_scanin = ff_rd_req_d1_scanout ; | |
1120 | assign ff_partial_mode_scanin = ff_addr_scanout ; | |
1121 | assign ff_mbist_signals_scanin = ff_partial_mode_scanout ; | |
1122 | assign ff_l2if_rd_dummy_req_scanin = ff_mbist_signals_scanout ; | |
1123 | assign ff_dummy_req_cpu_scanin = ff_l2if_rd_dummy_req_scanout; | |
1124 | assign ff_dummy_req_data_scanin = ff_dummy_req_cpu_scanout ; | |
1125 | assign ff_dummy_data_valid_d1_scanin = ff_dummy_req_data_scanout; | |
1126 | assign ff_l2wrreqflop_mcu_scanin = ff_dummy_data_valid_d1_scanout; | |
1127 | assign ff_wr_addr_scanin = ff_l2wrreqflop_mcu_scanout; | |
1128 | assign ff_drq_free_scanin = ff_wr_addr_scanout ; | |
1129 | assign ff_wdq_entry_free_scanin = ff_drq_free_scanout ; | |
1130 | assign ff_dummy_data_valid_scanin = ff_wdq_entry_free_scanout; | |
1131 | assign ff_addr_mode_scanin = ff_dummy_data_valid_scanout; | |
1132 | assign ff_rdq_cnt_scanin = ff_addr_mode_scanout ; | |
1133 | assign ff_rd_ack0_scanin = ff_rdq_cnt_scanout ; | |
1134 | assign ff_wr_ack_scanin = ff_rd_ack0_scanout ; | |
1135 | assign ff_wdq_in_cntr_cpu_scanin = ff_wr_ack_scanout ; | |
1136 | assign ff_wdq_in_cntr_scanin = ff_wdq_in_cntr_cpu_scanout; | |
1137 | assign ff_data_vld_scanin = ff_wdq_in_cntr_scanout ; | |
1138 | assign ff_b0_data_addr_scanin = ff_data_vld_scanout ; | |
1139 | assign ff_mem_rd_inh_scanin = ff_b0_data_addr_scanout ; | |
1140 | assign ff_wdq_rd_inh_scanin = ff_mem_rd_inh_scanout ; | |
1141 | assign ff_wr_ent0_scanin = ff_wdq_rd_inh_scanout ; | |
1142 | assign ff_wr_ent1_scanin = ff_wr_ent0_scanout ; | |
1143 | assign ff_wr_ent2_scanin = ff_wr_ent1_scanout ; | |
1144 | assign ff_wr_ent3_scanin = ff_wr_ent2_scanout ; | |
1145 | assign ff_wr_ent4_scanin = ff_wr_ent3_scanout ; | |
1146 | assign ff_wr_ent5_scanin = ff_wr_ent4_scanout ; | |
1147 | assign ff_wr_ent6_scanin = ff_wr_ent5_scanout ; | |
1148 | assign ff_wr_ent7_scanin = ff_wr_ent6_scanout ; | |
1149 | assign adrgen_scanin = ff_wr_ent7_scanout ; | |
1150 | assign ff_ibuf1_scanin = adrgen_scanout ; | |
1151 | assign ff_ibuf0_scanin = ff_ibuf1_scanout ; | |
1152 | assign ff_ibuf_state_scanin = ff_ibuf0_scanout ; | |
1153 | assign ff_wraddr_scanin = ff_ibuf_state_scanout ; | |
1154 | assign ff_ucb_rd_req_in_scanin = ff_wraddr_scanout ; | |
1155 | assign ff_ucb_sync_rd_req_in_scanin = ff_ucb_rd_req_in_scanout ; | |
1156 | assign ff_ucb_wr_req_in_scanin = ff_ucb_sync_rd_req_in_scanout; | |
1157 | assign ff_ucb_sync_wr_req_in_scanin = ff_ucb_wr_req_in_scanout ; | |
1158 | assign spares_scanin = ff_ucb_sync_wr_req_in_scanout; | |
1159 | assign scan_out = spares_scanout ; | |
1160 | // fixscan end: | |
1161 | endmodule // mcu_l2if | |
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | // any PARAMS parms go into naming of macro | |
1169 | ||
1170 | module mcu_l2if_ctl_l1clkhdr_ctl_macro ( | |
1171 | l2clk, | |
1172 | l1en, | |
1173 | pce_ov, | |
1174 | stop, | |
1175 | se, | |
1176 | l1clk); | |
1177 | ||
1178 | ||
1179 | input l2clk; | |
1180 | input l1en; | |
1181 | input pce_ov; | |
1182 | input stop; | |
1183 | input se; | |
1184 | output l1clk; | |
1185 | ||
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | cl_sc1_l1hdr_8x c_0 ( | |
1191 | ||
1192 | ||
1193 | .l2clk(l2clk), | |
1194 | .pce(l1en), | |
1195 | .l1clk(l1clk), | |
1196 | .se(se), | |
1197 | .pce_ov(pce_ov), | |
1198 | .stop(stop) | |
1199 | ); | |
1200 | ||
1201 | ||
1202 | ||
1203 | endmodule | |
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | // any PARAMS parms go into naming of macro | |
1218 | ||
1219 | module mcu_l2if_ctl_msff_ctl_macro__width_3 ( | |
1220 | din, | |
1221 | l1clk, | |
1222 | scan_in, | |
1223 | siclk, | |
1224 | soclk, | |
1225 | dout, | |
1226 | scan_out); | |
1227 | wire [2:0] fdin; | |
1228 | wire [1:0] so; | |
1229 | ||
1230 | input [2:0] din; | |
1231 | input l1clk; | |
1232 | input scan_in; | |
1233 | ||
1234 | ||
1235 | input siclk; | |
1236 | input soclk; | |
1237 | ||
1238 | output [2:0] dout; | |
1239 | output scan_out; | |
1240 | assign fdin[2:0] = din[2:0]; | |
1241 | ||
1242 | ||
1243 | ||
1244 | ||
1245 | ||
1246 | ||
1247 | dff #(3) d0_0 ( | |
1248 | .l1clk(l1clk), | |
1249 | .siclk(siclk), | |
1250 | .soclk(soclk), | |
1251 | .d(fdin[2:0]), | |
1252 | .si({scan_in,so[1:0]}), | |
1253 | .so({so[1:0],scan_out}), | |
1254 | .q(dout[2:0]) | |
1255 | ); | |
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | endmodule | |
1269 | ||
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | ||
1280 | ||
1281 | ||
1282 | // any PARAMS parms go into naming of macro | |
1283 | ||
1284 | module mcu_l2if_ctl_msff_ctl_macro__width_1 ( | |
1285 | din, | |
1286 | l1clk, | |
1287 | scan_in, | |
1288 | siclk, | |
1289 | soclk, | |
1290 | dout, | |
1291 | scan_out); | |
1292 | wire [0:0] fdin; | |
1293 | ||
1294 | input [0:0] din; | |
1295 | input l1clk; | |
1296 | input scan_in; | |
1297 | ||
1298 | ||
1299 | input siclk; | |
1300 | input soclk; | |
1301 | ||
1302 | output [0:0] dout; | |
1303 | output scan_out; | |
1304 | assign fdin[0:0] = din[0:0]; | |
1305 | ||
1306 | ||
1307 | ||
1308 | ||
1309 | ||
1310 | ||
1311 | dff #(1) d0_0 ( | |
1312 | .l1clk(l1clk), | |
1313 | .siclk(siclk), | |
1314 | .soclk(soclk), | |
1315 | .d(fdin[0:0]), | |
1316 | .si(scan_in), | |
1317 | .so(scan_out), | |
1318 | .q(dout[0:0]) | |
1319 | ); | |
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | endmodule | |
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | // any PARAMS parms go into naming of macro | |
1347 | ||
1348 | module mcu_l2if_ctl_msff_ctl_macro__clr_1__en_1__width_1 ( | |
1349 | din, | |
1350 | en, | |
1351 | clr, | |
1352 | l1clk, | |
1353 | scan_in, | |
1354 | siclk, | |
1355 | soclk, | |
1356 | dout, | |
1357 | scan_out); | |
1358 | wire [0:0] fdin; | |
1359 | ||
1360 | input [0:0] din; | |
1361 | input en; | |
1362 | input clr; | |
1363 | input l1clk; | |
1364 | input scan_in; | |
1365 | ||
1366 | ||
1367 | input siclk; | |
1368 | input soclk; | |
1369 | ||
1370 | output [0:0] dout; | |
1371 | output scan_out; | |
1372 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}}); | |
1373 | ||
1374 | ||
1375 | ||
1376 | ||
1377 | ||
1378 | ||
1379 | dff #(1) d0_0 ( | |
1380 | .l1clk(l1clk), | |
1381 | .siclk(siclk), | |
1382 | .soclk(soclk), | |
1383 | .d(fdin[0:0]), | |
1384 | .si(scan_in), | |
1385 | .so(scan_out), | |
1386 | .q(dout[0:0]) | |
1387 | ); | |
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | ||
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | endmodule | |
1401 | ||
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | // any PARAMS parms go into naming of macro | |
1415 | ||
1416 | module mcu_l2if_ctl_msff_ctl_macro__width_5 ( | |
1417 | din, | |
1418 | l1clk, | |
1419 | scan_in, | |
1420 | siclk, | |
1421 | soclk, | |
1422 | dout, | |
1423 | scan_out); | |
1424 | wire [4:0] fdin; | |
1425 | wire [3:0] so; | |
1426 | ||
1427 | input [4:0] din; | |
1428 | input l1clk; | |
1429 | input scan_in; | |
1430 | ||
1431 | ||
1432 | input siclk; | |
1433 | input soclk; | |
1434 | ||
1435 | output [4:0] dout; | |
1436 | output scan_out; | |
1437 | assign fdin[4:0] = din[4:0]; | |
1438 | ||
1439 | ||
1440 | ||
1441 | ||
1442 | ||
1443 | ||
1444 | dff #(5) d0_0 ( | |
1445 | .l1clk(l1clk), | |
1446 | .siclk(siclk), | |
1447 | .soclk(soclk), | |
1448 | .d(fdin[4:0]), | |
1449 | .si({scan_in,so[3:0]}), | |
1450 | .so({so[3:0],scan_out}), | |
1451 | .q(dout[4:0]) | |
1452 | ); | |
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | endmodule | |
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | ||
1476 | ||
1477 | ||
1478 | ||
1479 | // any PARAMS parms go into naming of macro | |
1480 | ||
1481 | module mcu_l2if_ctl_msff_ctl_macro__width_35 ( | |
1482 | din, | |
1483 | l1clk, | |
1484 | scan_in, | |
1485 | siclk, | |
1486 | soclk, | |
1487 | dout, | |
1488 | scan_out); | |
1489 | wire [34:0] fdin; | |
1490 | wire [33:0] so; | |
1491 | ||
1492 | input [34:0] din; | |
1493 | input l1clk; | |
1494 | input scan_in; | |
1495 | ||
1496 | ||
1497 | input siclk; | |
1498 | input soclk; | |
1499 | ||
1500 | output [34:0] dout; | |
1501 | output scan_out; | |
1502 | assign fdin[34:0] = din[34:0]; | |
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | dff #(35) d0_0 ( | |
1510 | .l1clk(l1clk), | |
1511 | .siclk(siclk), | |
1512 | .soclk(soclk), | |
1513 | .d(fdin[34:0]), | |
1514 | .si({scan_in,so[33:0]}), | |
1515 | .so({so[33:0],scan_out}), | |
1516 | .q(dout[34:0]) | |
1517 | ); | |
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | endmodule | |
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | // any PARAMS parms go into naming of macro | |
1545 | ||
1546 | module mcu_l2if_ctl_msff_ctl_macro ( | |
1547 | din, | |
1548 | l1clk, | |
1549 | scan_in, | |
1550 | siclk, | |
1551 | soclk, | |
1552 | dout, | |
1553 | scan_out); | |
1554 | wire [0:0] fdin; | |
1555 | ||
1556 | input [0:0] din; | |
1557 | input l1clk; | |
1558 | input scan_in; | |
1559 | ||
1560 | ||
1561 | input siclk; | |
1562 | input soclk; | |
1563 | ||
1564 | output [0:0] dout; | |
1565 | output scan_out; | |
1566 | assign fdin[0:0] = din[0:0]; | |
1567 | ||
1568 | ||
1569 | ||
1570 | ||
1571 | ||
1572 | ||
1573 | dff #(1) d0_0 ( | |
1574 | .l1clk(l1clk), | |
1575 | .siclk(siclk), | |
1576 | .soclk(soclk), | |
1577 | .d(fdin[0:0]), | |
1578 | .si(scan_in), | |
1579 | .so(scan_out), | |
1580 | .q(dout[0:0]) | |
1581 | ); | |
1582 | ||
1583 | ||
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | ||
1589 | ||
1590 | ||
1591 | ||
1592 | ||
1593 | ||
1594 | endmodule | |
1595 | ||
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | // any PARAMS parms go into naming of macro | |
1609 | ||
1610 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_8 ( | |
1611 | din, | |
1612 | en, | |
1613 | l1clk, | |
1614 | scan_in, | |
1615 | siclk, | |
1616 | soclk, | |
1617 | dout, | |
1618 | scan_out); | |
1619 | wire [7:0] fdin; | |
1620 | wire [6:0] so; | |
1621 | ||
1622 | input [7:0] din; | |
1623 | input en; | |
1624 | input l1clk; | |
1625 | input scan_in; | |
1626 | ||
1627 | ||
1628 | input siclk; | |
1629 | input soclk; | |
1630 | ||
1631 | output [7:0] dout; | |
1632 | output scan_out; | |
1633 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
1634 | ||
1635 | ||
1636 | ||
1637 | ||
1638 | ||
1639 | ||
1640 | dff #(8) d0_0 ( | |
1641 | .l1clk(l1clk), | |
1642 | .siclk(siclk), | |
1643 | .soclk(soclk), | |
1644 | .d(fdin[7:0]), | |
1645 | .si({scan_in,so[6:0]}), | |
1646 | .so({so[6:0],scan_out}), | |
1647 | .q(dout[7:0]) | |
1648 | ); | |
1649 | ||
1650 | ||
1651 | ||
1652 | ||
1653 | ||
1654 | ||
1655 | ||
1656 | ||
1657 | ||
1658 | ||
1659 | ||
1660 | ||
1661 | endmodule | |
1662 | ||
1663 | ||
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | ||
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | // any PARAMS parms go into naming of macro | |
1676 | ||
1677 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_5 ( | |
1678 | din, | |
1679 | en, | |
1680 | l1clk, | |
1681 | scan_in, | |
1682 | siclk, | |
1683 | soclk, | |
1684 | dout, | |
1685 | scan_out); | |
1686 | wire [4:0] fdin; | |
1687 | wire [3:0] so; | |
1688 | ||
1689 | input [4:0] din; | |
1690 | input en; | |
1691 | input l1clk; | |
1692 | input scan_in; | |
1693 | ||
1694 | ||
1695 | input siclk; | |
1696 | input soclk; | |
1697 | ||
1698 | output [4:0] dout; | |
1699 | output scan_out; | |
1700 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); | |
1701 | ||
1702 | ||
1703 | ||
1704 | ||
1705 | ||
1706 | ||
1707 | dff #(5) d0_0 ( | |
1708 | .l1clk(l1clk), | |
1709 | .siclk(siclk), | |
1710 | .soclk(soclk), | |
1711 | .d(fdin[4:0]), | |
1712 | .si({scan_in,so[3:0]}), | |
1713 | .so({so[3:0],scan_out}), | |
1714 | .q(dout[4:0]) | |
1715 | ); | |
1716 | ||
1717 | ||
1718 | ||
1719 | ||
1720 | ||
1721 | ||
1722 | ||
1723 | ||
1724 | ||
1725 | ||
1726 | ||
1727 | ||
1728 | endmodule | |
1729 | ||
1730 | ||
1731 | ||
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | ||
1741 | ||
1742 | // any PARAMS parms go into naming of macro | |
1743 | ||
1744 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_6 ( | |
1745 | din, | |
1746 | en, | |
1747 | l1clk, | |
1748 | scan_in, | |
1749 | siclk, | |
1750 | soclk, | |
1751 | dout, | |
1752 | scan_out); | |
1753 | wire [5:0] fdin; | |
1754 | wire [4:0] so; | |
1755 | ||
1756 | input [5:0] din; | |
1757 | input en; | |
1758 | input l1clk; | |
1759 | input scan_in; | |
1760 | ||
1761 | ||
1762 | input siclk; | |
1763 | input soclk; | |
1764 | ||
1765 | output [5:0] dout; | |
1766 | output scan_out; | |
1767 | assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}}); | |
1768 | ||
1769 | ||
1770 | ||
1771 | ||
1772 | ||
1773 | ||
1774 | dff #(6) d0_0 ( | |
1775 | .l1clk(l1clk), | |
1776 | .siclk(siclk), | |
1777 | .soclk(soclk), | |
1778 | .d(fdin[5:0]), | |
1779 | .si({scan_in,so[4:0]}), | |
1780 | .so({so[4:0],scan_out}), | |
1781 | .q(dout[5:0]) | |
1782 | ); | |
1783 | ||
1784 | ||
1785 | ||
1786 | ||
1787 | ||
1788 | ||
1789 | ||
1790 | ||
1791 | ||
1792 | ||
1793 | ||
1794 | ||
1795 | endmodule | |
1796 | ||
1797 | ||
1798 | ||
1799 | ||
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | ||
1809 | // any PARAMS parms go into naming of macro | |
1810 | ||
1811 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_2 ( | |
1812 | din, | |
1813 | en, | |
1814 | l1clk, | |
1815 | scan_in, | |
1816 | siclk, | |
1817 | soclk, | |
1818 | dout, | |
1819 | scan_out); | |
1820 | wire [1:0] fdin; | |
1821 | wire [0:0] so; | |
1822 | ||
1823 | input [1:0] din; | |
1824 | input en; | |
1825 | input l1clk; | |
1826 | input scan_in; | |
1827 | ||
1828 | ||
1829 | input siclk; | |
1830 | input soclk; | |
1831 | ||
1832 | output [1:0] dout; | |
1833 | output scan_out; | |
1834 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
1835 | ||
1836 | ||
1837 | ||
1838 | ||
1839 | ||
1840 | ||
1841 | dff #(2) d0_0 ( | |
1842 | .l1clk(l1clk), | |
1843 | .siclk(siclk), | |
1844 | .soclk(soclk), | |
1845 | .d(fdin[1:0]), | |
1846 | .si({scan_in,so[0:0]}), | |
1847 | .so({so[0:0],scan_out}), | |
1848 | .q(dout[1:0]) | |
1849 | ); | |
1850 | ||
1851 | ||
1852 | ||
1853 | ||
1854 | ||
1855 | ||
1856 | ||
1857 | ||
1858 | ||
1859 | ||
1860 | ||
1861 | ||
1862 | endmodule | |
1863 | ||
1864 | ||
1865 | ||
1866 | ||
1867 | ||
1868 | ||
1869 | ||
1870 | ||
1871 | ||
1872 | ||
1873 | ||
1874 | ||
1875 | ||
1876 | // any PARAMS parms go into naming of macro | |
1877 | ||
1878 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_3 ( | |
1879 | din, | |
1880 | en, | |
1881 | l1clk, | |
1882 | scan_in, | |
1883 | siclk, | |
1884 | soclk, | |
1885 | dout, | |
1886 | scan_out); | |
1887 | wire [2:0] fdin; | |
1888 | wire [1:0] so; | |
1889 | ||
1890 | input [2:0] din; | |
1891 | input en; | |
1892 | input l1clk; | |
1893 | input scan_in; | |
1894 | ||
1895 | ||
1896 | input siclk; | |
1897 | input soclk; | |
1898 | ||
1899 | output [2:0] dout; | |
1900 | output scan_out; | |
1901 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
1902 | ||
1903 | ||
1904 | ||
1905 | ||
1906 | ||
1907 | ||
1908 | dff #(3) d0_0 ( | |
1909 | .l1clk(l1clk), | |
1910 | .siclk(siclk), | |
1911 | .soclk(soclk), | |
1912 | .d(fdin[2:0]), | |
1913 | .si({scan_in,so[1:0]}), | |
1914 | .so({so[1:0],scan_out}), | |
1915 | .q(dout[2:0]) | |
1916 | ); | |
1917 | ||
1918 | ||
1919 | ||
1920 | ||
1921 | ||
1922 | ||
1923 | ||
1924 | ||
1925 | ||
1926 | ||
1927 | ||
1928 | ||
1929 | endmodule | |
1930 | ||
1931 | ||
1932 | ||
1933 | ||
1934 | ||
1935 | ||
1936 | ||
1937 | ||
1938 | ||
1939 | ||
1940 | ||
1941 | ||
1942 | ||
1943 | // any PARAMS parms go into naming of macro | |
1944 | ||
1945 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_1 ( | |
1946 | din, | |
1947 | en, | |
1948 | l1clk, | |
1949 | scan_in, | |
1950 | siclk, | |
1951 | soclk, | |
1952 | dout, | |
1953 | scan_out); | |
1954 | wire [0:0] fdin; | |
1955 | ||
1956 | input [0:0] din; | |
1957 | input en; | |
1958 | input l1clk; | |
1959 | input scan_in; | |
1960 | ||
1961 | ||
1962 | input siclk; | |
1963 | input soclk; | |
1964 | ||
1965 | output [0:0] dout; | |
1966 | output scan_out; | |
1967 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
1968 | ||
1969 | ||
1970 | ||
1971 | ||
1972 | ||
1973 | ||
1974 | dff #(1) d0_0 ( | |
1975 | .l1clk(l1clk), | |
1976 | .siclk(siclk), | |
1977 | .soclk(soclk), | |
1978 | .d(fdin[0:0]), | |
1979 | .si(scan_in), | |
1980 | .so(scan_out), | |
1981 | .q(dout[0:0]) | |
1982 | ); | |
1983 | ||
1984 | ||
1985 | ||
1986 | ||
1987 | ||
1988 | ||
1989 | ||
1990 | ||
1991 | ||
1992 | ||
1993 | ||
1994 | ||
1995 | endmodule | |
1996 | ||
1997 | ||
1998 | ||
1999 | ||
2000 | ||
2001 | ||
2002 | ||
2003 | ||
2004 | ||
2005 | ||
2006 | ||
2007 | ||
2008 | ||
2009 | // any PARAMS parms go into naming of macro | |
2010 | ||
2011 | module mcu_l2if_ctl_msff_ctl_macro__en_1 ( | |
2012 | din, | |
2013 | en, | |
2014 | l1clk, | |
2015 | scan_in, | |
2016 | siclk, | |
2017 | soclk, | |
2018 | dout, | |
2019 | scan_out); | |
2020 | wire [0:0] fdin; | |
2021 | ||
2022 | input [0:0] din; | |
2023 | input en; | |
2024 | input l1clk; | |
2025 | input scan_in; | |
2026 | ||
2027 | ||
2028 | input siclk; | |
2029 | input soclk; | |
2030 | ||
2031 | output [0:0] dout; | |
2032 | output scan_out; | |
2033 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
2034 | ||
2035 | ||
2036 | ||
2037 | ||
2038 | ||
2039 | ||
2040 | dff #(1) d0_0 ( | |
2041 | .l1clk(l1clk), | |
2042 | .siclk(siclk), | |
2043 | .soclk(soclk), | |
2044 | .d(fdin[0:0]), | |
2045 | .si(scan_in), | |
2046 | .so(scan_out), | |
2047 | .q(dout[0:0]) | |
2048 | ); | |
2049 | ||
2050 | ||
2051 | ||
2052 | ||
2053 | ||
2054 | ||
2055 | ||
2056 | ||
2057 | ||
2058 | ||
2059 | ||
2060 | ||
2061 | endmodule | |
2062 | ||
2063 | ||
2064 | ||
2065 | ||
2066 | ||
2067 | ||
2068 | ||
2069 | ||
2070 | ||
2071 | ||
2072 | ||
2073 | ||
2074 | ||
2075 | // any PARAMS parms go into naming of macro | |
2076 | ||
2077 | module mcu_l2if_ctl_msff_ctl_macro__width_4 ( | |
2078 | din, | |
2079 | l1clk, | |
2080 | scan_in, | |
2081 | siclk, | |
2082 | soclk, | |
2083 | dout, | |
2084 | scan_out); | |
2085 | wire [3:0] fdin; | |
2086 | wire [2:0] so; | |
2087 | ||
2088 | input [3:0] din; | |
2089 | input l1clk; | |
2090 | input scan_in; | |
2091 | ||
2092 | ||
2093 | input siclk; | |
2094 | input soclk; | |
2095 | ||
2096 | output [3:0] dout; | |
2097 | output scan_out; | |
2098 | assign fdin[3:0] = din[3:0]; | |
2099 | ||
2100 | ||
2101 | ||
2102 | ||
2103 | ||
2104 | ||
2105 | dff #(4) d0_0 ( | |
2106 | .l1clk(l1clk), | |
2107 | .siclk(siclk), | |
2108 | .soclk(soclk), | |
2109 | .d(fdin[3:0]), | |
2110 | .si({scan_in,so[2:0]}), | |
2111 | .so({so[2:0],scan_out}), | |
2112 | .q(dout[3:0]) | |
2113 | ); | |
2114 | ||
2115 | ||
2116 | ||
2117 | ||
2118 | ||
2119 | ||
2120 | ||
2121 | ||
2122 | ||
2123 | ||
2124 | ||
2125 | ||
2126 | endmodule | |
2127 | ||
2128 | ||
2129 | ||
2130 | ||
2131 | ||
2132 | ||
2133 | ||
2134 | ||
2135 | ||
2136 | ||
2137 | ||
2138 | ||
2139 | ||
2140 | // any PARAMS parms go into naming of macro | |
2141 | ||
2142 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_4 ( | |
2143 | din, | |
2144 | en, | |
2145 | l1clk, | |
2146 | scan_in, | |
2147 | siclk, | |
2148 | soclk, | |
2149 | dout, | |
2150 | scan_out); | |
2151 | wire [3:0] fdin; | |
2152 | wire [2:0] so; | |
2153 | ||
2154 | input [3:0] din; | |
2155 | input en; | |
2156 | input l1clk; | |
2157 | input scan_in; | |
2158 | ||
2159 | ||
2160 | input siclk; | |
2161 | input soclk; | |
2162 | ||
2163 | output [3:0] dout; | |
2164 | output scan_out; | |
2165 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
2166 | ||
2167 | ||
2168 | ||
2169 | ||
2170 | ||
2171 | ||
2172 | dff #(4) d0_0 ( | |
2173 | .l1clk(l1clk), | |
2174 | .siclk(siclk), | |
2175 | .soclk(soclk), | |
2176 | .d(fdin[3:0]), | |
2177 | .si({scan_in,so[2:0]}), | |
2178 | .so({so[2:0],scan_out}), | |
2179 | .q(dout[3:0]) | |
2180 | ); | |
2181 | ||
2182 | ||
2183 | ||
2184 | ||
2185 | ||
2186 | ||
2187 | ||
2188 | ||
2189 | ||
2190 | ||
2191 | ||
2192 | ||
2193 | endmodule | |
2194 | ||
2195 | ||
2196 | ||
2197 | ||
2198 | ||
2199 | ||
2200 | ||
2201 | ||
2202 | ||
2203 | ||
2204 | ||
2205 | ||
2206 | ||
2207 | // any PARAMS parms go into naming of macro | |
2208 | ||
2209 | module mcu_l2if_ctl_msff_ctl_macro__width_6 ( | |
2210 | din, | |
2211 | l1clk, | |
2212 | scan_in, | |
2213 | siclk, | |
2214 | soclk, | |
2215 | dout, | |
2216 | scan_out); | |
2217 | wire [5:0] fdin; | |
2218 | wire [4:0] so; | |
2219 | ||
2220 | input [5:0] din; | |
2221 | input l1clk; | |
2222 | input scan_in; | |
2223 | ||
2224 | ||
2225 | input siclk; | |
2226 | input soclk; | |
2227 | ||
2228 | output [5:0] dout; | |
2229 | output scan_out; | |
2230 | assign fdin[5:0] = din[5:0]; | |
2231 | ||
2232 | ||
2233 | ||
2234 | ||
2235 | ||
2236 | ||
2237 | dff #(6) d0_0 ( | |
2238 | .l1clk(l1clk), | |
2239 | .siclk(siclk), | |
2240 | .soclk(soclk), | |
2241 | .d(fdin[5:0]), | |
2242 | .si({scan_in,so[4:0]}), | |
2243 | .so({so[4:0],scan_out}), | |
2244 | .q(dout[5:0]) | |
2245 | ); | |
2246 | ||
2247 | ||
2248 | endmodule | |
2249 | ||
2250 | ||
2251 | ||
2252 | // any PARAMS parms go into naming of macro | |
2253 | ||
2254 | module mcu_l2if_ctl_msff_ctl_macro__width_8 ( | |
2255 | din, | |
2256 | l1clk, | |
2257 | scan_in, | |
2258 | siclk, | |
2259 | soclk, | |
2260 | dout, | |
2261 | scan_out); | |
2262 | wire [7:0] fdin; | |
2263 | wire [6:0] so; | |
2264 | ||
2265 | input [7:0] din; | |
2266 | input l1clk; | |
2267 | input scan_in; | |
2268 | ||
2269 | ||
2270 | input siclk; | |
2271 | input soclk; | |
2272 | ||
2273 | output [7:0] dout; | |
2274 | output scan_out; | |
2275 | assign fdin[7:0] = din[7:0]; | |
2276 | ||
2277 | ||
2278 | ||
2279 | ||
2280 | ||
2281 | ||
2282 | dff #(8) d0_0 ( | |
2283 | .l1clk(l1clk), | |
2284 | .siclk(siclk), | |
2285 | .soclk(soclk), | |
2286 | .d(fdin[7:0]), | |
2287 | .si({scan_in,so[6:0]}), | |
2288 | .so({so[6:0],scan_out}), | |
2289 | .q(dout[7:0]) | |
2290 | ); | |
2291 | ||
2292 | ||
2293 | ||
2294 | ||
2295 | ||
2296 | ||
2297 | ||
2298 | ||
2299 | ||
2300 | ||
2301 | ||
2302 | ||
2303 | endmodule | |
2304 | ||
2305 | ||
2306 | ||
2307 | ||
2308 | ||
2309 | ||
2310 | ||
2311 | ||
2312 | ||
2313 | ||
2314 | ||
2315 | ||
2316 | ||
2317 | // any PARAMS parms go into naming of macro | |
2318 | ||
2319 | module mcu_l2if_ctl_msff_ctl_macro__width_9 ( | |
2320 | din, | |
2321 | l1clk, | |
2322 | scan_in, | |
2323 | siclk, | |
2324 | soclk, | |
2325 | dout, | |
2326 | scan_out); | |
2327 | wire [8:0] fdin; | |
2328 | wire [7:0] so; | |
2329 | ||
2330 | input [8:0] din; | |
2331 | input l1clk; | |
2332 | input scan_in; | |
2333 | ||
2334 | ||
2335 | input siclk; | |
2336 | input soclk; | |
2337 | ||
2338 | output [8:0] dout; | |
2339 | output scan_out; | |
2340 | assign fdin[8:0] = din[8:0]; | |
2341 | ||
2342 | ||
2343 | ||
2344 | ||
2345 | ||
2346 | ||
2347 | dff #(9) d0_0 ( | |
2348 | .l1clk(l1clk), | |
2349 | .siclk(siclk), | |
2350 | .soclk(soclk), | |
2351 | .d(fdin[8:0]), | |
2352 | .si({scan_in,so[7:0]}), | |
2353 | .so({so[7:0],scan_out}), | |
2354 | .q(dout[8:0]) | |
2355 | ); | |
2356 | ||
2357 | ||
2358 | ||
2359 | ||
2360 | ||
2361 | ||
2362 | ||
2363 | ||
2364 | ||
2365 | ||
2366 | ||
2367 | ||
2368 | endmodule | |
2369 | ||
2370 | ||
2371 | ||
2372 | ||
2373 | ||
2374 | ||
2375 | ||
2376 | ||
2377 | ||
2378 | ||
2379 | ||
2380 | ||
2381 | ||
2382 | // any PARAMS parms go into naming of macro | |
2383 | ||
2384 | module mcu_l2if_ctl_msff_ctl_macro__width_7 ( | |
2385 | din, | |
2386 | l1clk, | |
2387 | scan_in, | |
2388 | siclk, | |
2389 | soclk, | |
2390 | dout, | |
2391 | scan_out); | |
2392 | wire [6:0] fdin; | |
2393 | wire [5:0] so; | |
2394 | ||
2395 | input [6:0] din; | |
2396 | input l1clk; | |
2397 | input scan_in; | |
2398 | ||
2399 | ||
2400 | input siclk; | |
2401 | input soclk; | |
2402 | ||
2403 | output [6:0] dout; | |
2404 | output scan_out; | |
2405 | assign fdin[6:0] = din[6:0]; | |
2406 | ||
2407 | ||
2408 | ||
2409 | ||
2410 | ||
2411 | ||
2412 | dff #(7) d0_0 ( | |
2413 | .l1clk(l1clk), | |
2414 | .siclk(siclk), | |
2415 | .soclk(soclk), | |
2416 | .d(fdin[6:0]), | |
2417 | .si({scan_in,so[5:0]}), | |
2418 | .so({so[5:0],scan_out}), | |
2419 | .q(dout[6:0]) | |
2420 | ); | |
2421 | ||
2422 | ||
2423 | ||
2424 | ||
2425 | ||
2426 | ||
2427 | ||
2428 | ||
2429 | ||
2430 | ||
2431 | ||
2432 | ||
2433 | endmodule | |
2434 | ||
2435 | ||
2436 | ||
2437 | ||
2438 | ||
2439 | ||
2440 | ||
2441 | ||
2442 | ||
2443 | ||
2444 | ||
2445 | ||
2446 | ||
2447 | // any PARAMS parms go into naming of macro | |
2448 | ||
2449 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_38 ( | |
2450 | din, | |
2451 | en, | |
2452 | l1clk, | |
2453 | scan_in, | |
2454 | siclk, | |
2455 | soclk, | |
2456 | dout, | |
2457 | scan_out); | |
2458 | wire [37:0] fdin; | |
2459 | wire [36:0] so; | |
2460 | ||
2461 | input [37:0] din; | |
2462 | input en; | |
2463 | input l1clk; | |
2464 | input scan_in; | |
2465 | ||
2466 | ||
2467 | input siclk; | |
2468 | input soclk; | |
2469 | ||
2470 | output [37:0] dout; | |
2471 | output scan_out; | |
2472 | assign fdin[37:0] = (din[37:0] & {38{en}}) | (dout[37:0] & ~{38{en}}); | |
2473 | ||
2474 | ||
2475 | ||
2476 | ||
2477 | ||
2478 | ||
2479 | dff #(38) d0_0 ( | |
2480 | .l1clk(l1clk), | |
2481 | .siclk(siclk), | |
2482 | .soclk(soclk), | |
2483 | .d(fdin[37:0]), | |
2484 | .si({scan_in,so[36:0]}), | |
2485 | .so({so[36:0],scan_out}), | |
2486 | .q(dout[37:0]) | |
2487 | ); | |
2488 | ||
2489 | ||
2490 | ||
2491 | ||
2492 | ||
2493 | ||
2494 | ||
2495 | ||
2496 | ||
2497 | ||
2498 | ||
2499 | ||
2500 | endmodule | |
2501 | ||
2502 | ||
2503 | ||
2504 | ||
2505 | ||
2506 | ||
2507 | ||
2508 | ||
2509 | ||
2510 | ||
2511 | ||
2512 | ||
2513 | ||
2514 | // any PARAMS parms go into naming of macro | |
2515 | ||
2516 | module mcu_l2if_ctl_msff_ctl_macro__en_1__width_35 ( | |
2517 | din, | |
2518 | en, | |
2519 | l1clk, | |
2520 | scan_in, | |
2521 | siclk, | |
2522 | soclk, | |
2523 | dout, | |
2524 | scan_out); | |
2525 | wire [34:0] fdin; | |
2526 | wire [33:0] so; | |
2527 | ||
2528 | input [34:0] din; | |
2529 | input en; | |
2530 | input l1clk; | |
2531 | input scan_in; | |
2532 | ||
2533 | ||
2534 | input siclk; | |
2535 | input soclk; | |
2536 | ||
2537 | output [34:0] dout; | |
2538 | output scan_out; | |
2539 | assign fdin[34:0] = (din[34:0] & {35{en}}) | (dout[34:0] & ~{35{en}}); | |
2540 | ||
2541 | ||
2542 | ||
2543 | ||
2544 | ||
2545 | ||
2546 | dff #(35) d0_0 ( | |
2547 | .l1clk(l1clk), | |
2548 | .siclk(siclk), | |
2549 | .soclk(soclk), | |
2550 | .d(fdin[34:0]), | |
2551 | .si({scan_in,so[33:0]}), | |
2552 | .so({so[33:0],scan_out}), | |
2553 | .q(dout[34:0]) | |
2554 | ); | |
2555 | ||
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | ||
2562 | ||
2563 | ||
2564 | ||
2565 | ||
2566 | ||
2567 | endmodule | |
2568 | ||
2569 | ||
2570 | ||
2571 | ||
2572 | ||
2573 | ||
2574 | ||
2575 | ||
2576 | ||
2577 | // Description: Spare gate macro for control blocks | |
2578 | // | |
2579 | // Param num controls the number of times the macro is added | |
2580 | // flops=0 can be used to use only combination spare logic | |
2581 | ||
2582 | ||
2583 | module mcu_l2if_ctl_spare_ctl_macro__num_4 ( | |
2584 | l1clk, | |
2585 | scan_in, | |
2586 | siclk, | |
2587 | soclk, | |
2588 | scan_out); | |
2589 | wire si_0; | |
2590 | wire so_0; | |
2591 | wire spare0_flop_unused; | |
2592 | wire spare0_buf_32x_unused; | |
2593 | wire spare0_nand3_8x_unused; | |
2594 | wire spare0_inv_8x_unused; | |
2595 | wire spare0_aoi22_4x_unused; | |
2596 | wire spare0_buf_8x_unused; | |
2597 | wire spare0_oai22_4x_unused; | |
2598 | wire spare0_inv_16x_unused; | |
2599 | wire spare0_nand2_16x_unused; | |
2600 | wire spare0_nor3_4x_unused; | |
2601 | wire spare0_nand2_8x_unused; | |
2602 | wire spare0_buf_16x_unused; | |
2603 | wire spare0_nor2_16x_unused; | |
2604 | wire spare0_inv_32x_unused; | |
2605 | wire si_1; | |
2606 | wire so_1; | |
2607 | wire spare1_flop_unused; | |
2608 | wire spare1_buf_32x_unused; | |
2609 | wire spare1_nand3_8x_unused; | |
2610 | wire spare1_inv_8x_unused; | |
2611 | wire spare1_aoi22_4x_unused; | |
2612 | wire spare1_buf_8x_unused; | |
2613 | wire spare1_oai22_4x_unused; | |
2614 | wire spare1_inv_16x_unused; | |
2615 | wire spare1_nand2_16x_unused; | |
2616 | wire spare1_nor3_4x_unused; | |
2617 | wire spare1_nand2_8x_unused; | |
2618 | wire spare1_buf_16x_unused; | |
2619 | wire spare1_nor2_16x_unused; | |
2620 | wire spare1_inv_32x_unused; | |
2621 | wire si_2; | |
2622 | wire so_2; | |
2623 | wire spare2_flop_unused; | |
2624 | wire spare2_buf_32x_unused; | |
2625 | wire spare2_nand3_8x_unused; | |
2626 | wire spare2_inv_8x_unused; | |
2627 | wire spare2_aoi22_4x_unused; | |
2628 | wire spare2_buf_8x_unused; | |
2629 | wire spare2_oai22_4x_unused; | |
2630 | wire spare2_inv_16x_unused; | |
2631 | wire spare2_nand2_16x_unused; | |
2632 | wire spare2_nor3_4x_unused; | |
2633 | wire spare2_nand2_8x_unused; | |
2634 | wire spare2_buf_16x_unused; | |
2635 | wire spare2_nor2_16x_unused; | |
2636 | wire spare2_inv_32x_unused; | |
2637 | wire si_3; | |
2638 | wire so_3; | |
2639 | wire spare3_flop_unused; | |
2640 | wire spare3_buf_32x_unused; | |
2641 | wire spare3_nand3_8x_unused; | |
2642 | wire spare3_inv_8x_unused; | |
2643 | wire spare3_aoi22_4x_unused; | |
2644 | wire spare3_buf_8x_unused; | |
2645 | wire spare3_oai22_4x_unused; | |
2646 | wire spare3_inv_16x_unused; | |
2647 | wire spare3_nand2_16x_unused; | |
2648 | wire spare3_nor3_4x_unused; | |
2649 | wire spare3_nand2_8x_unused; | |
2650 | wire spare3_buf_16x_unused; | |
2651 | wire spare3_nor2_16x_unused; | |
2652 | wire spare3_inv_32x_unused; | |
2653 | ||
2654 | ||
2655 | input l1clk; | |
2656 | input scan_in; | |
2657 | input siclk; | |
2658 | input soclk; | |
2659 | output scan_out; | |
2660 | ||
2661 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
2662 | .siclk(siclk), | |
2663 | .soclk(soclk), | |
2664 | .si(si_0), | |
2665 | .so(so_0), | |
2666 | .d(1'b0), | |
2667 | .q(spare0_flop_unused)); | |
2668 | assign si_0 = scan_in; | |
2669 | ||
2670 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
2671 | .out(spare0_buf_32x_unused)); | |
2672 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
2673 | .in1(1'b1), | |
2674 | .in2(1'b1), | |
2675 | .out(spare0_nand3_8x_unused)); | |
2676 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
2677 | .out(spare0_inv_8x_unused)); | |
2678 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
2679 | .in01(1'b1), | |
2680 | .in10(1'b1), | |
2681 | .in11(1'b1), | |
2682 | .out(spare0_aoi22_4x_unused)); | |
2683 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
2684 | .out(spare0_buf_8x_unused)); | |
2685 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
2686 | .in01(1'b1), | |
2687 | .in10(1'b1), | |
2688 | .in11(1'b1), | |
2689 | .out(spare0_oai22_4x_unused)); | |
2690 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
2691 | .out(spare0_inv_16x_unused)); | |
2692 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
2693 | .in1(1'b1), | |
2694 | .out(spare0_nand2_16x_unused)); | |
2695 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
2696 | .in1(1'b0), | |
2697 | .in2(1'b0), | |
2698 | .out(spare0_nor3_4x_unused)); | |
2699 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
2700 | .in1(1'b1), | |
2701 | .out(spare0_nand2_8x_unused)); | |
2702 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
2703 | .out(spare0_buf_16x_unused)); | |
2704 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
2705 | .in1(1'b0), | |
2706 | .out(spare0_nor2_16x_unused)); | |
2707 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
2708 | .out(spare0_inv_32x_unused)); | |
2709 | ||
2710 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
2711 | .siclk(siclk), | |
2712 | .soclk(soclk), | |
2713 | .si(si_1), | |
2714 | .so(so_1), | |
2715 | .d(1'b0), | |
2716 | .q(spare1_flop_unused)); | |
2717 | assign si_1 = so_0; | |
2718 | ||
2719 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
2720 | .out(spare1_buf_32x_unused)); | |
2721 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
2722 | .in1(1'b1), | |
2723 | .in2(1'b1), | |
2724 | .out(spare1_nand3_8x_unused)); | |
2725 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
2726 | .out(spare1_inv_8x_unused)); | |
2727 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
2728 | .in01(1'b1), | |
2729 | .in10(1'b1), | |
2730 | .in11(1'b1), | |
2731 | .out(spare1_aoi22_4x_unused)); | |
2732 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
2733 | .out(spare1_buf_8x_unused)); | |
2734 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
2735 | .in01(1'b1), | |
2736 | .in10(1'b1), | |
2737 | .in11(1'b1), | |
2738 | .out(spare1_oai22_4x_unused)); | |
2739 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
2740 | .out(spare1_inv_16x_unused)); | |
2741 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
2742 | .in1(1'b1), | |
2743 | .out(spare1_nand2_16x_unused)); | |
2744 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
2745 | .in1(1'b0), | |
2746 | .in2(1'b0), | |
2747 | .out(spare1_nor3_4x_unused)); | |
2748 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
2749 | .in1(1'b1), | |
2750 | .out(spare1_nand2_8x_unused)); | |
2751 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
2752 | .out(spare1_buf_16x_unused)); | |
2753 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
2754 | .in1(1'b0), | |
2755 | .out(spare1_nor2_16x_unused)); | |
2756 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
2757 | .out(spare1_inv_32x_unused)); | |
2758 | ||
2759 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
2760 | .siclk(siclk), | |
2761 | .soclk(soclk), | |
2762 | .si(si_2), | |
2763 | .so(so_2), | |
2764 | .d(1'b0), | |
2765 | .q(spare2_flop_unused)); | |
2766 | assign si_2 = so_1; | |
2767 | ||
2768 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
2769 | .out(spare2_buf_32x_unused)); | |
2770 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
2771 | .in1(1'b1), | |
2772 | .in2(1'b1), | |
2773 | .out(spare2_nand3_8x_unused)); | |
2774 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
2775 | .out(spare2_inv_8x_unused)); | |
2776 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
2777 | .in01(1'b1), | |
2778 | .in10(1'b1), | |
2779 | .in11(1'b1), | |
2780 | .out(spare2_aoi22_4x_unused)); | |
2781 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
2782 | .out(spare2_buf_8x_unused)); | |
2783 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
2784 | .in01(1'b1), | |
2785 | .in10(1'b1), | |
2786 | .in11(1'b1), | |
2787 | .out(spare2_oai22_4x_unused)); | |
2788 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
2789 | .out(spare2_inv_16x_unused)); | |
2790 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
2791 | .in1(1'b1), | |
2792 | .out(spare2_nand2_16x_unused)); | |
2793 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
2794 | .in1(1'b0), | |
2795 | .in2(1'b0), | |
2796 | .out(spare2_nor3_4x_unused)); | |
2797 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
2798 | .in1(1'b1), | |
2799 | .out(spare2_nand2_8x_unused)); | |
2800 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
2801 | .out(spare2_buf_16x_unused)); | |
2802 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
2803 | .in1(1'b0), | |
2804 | .out(spare2_nor2_16x_unused)); | |
2805 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
2806 | .out(spare2_inv_32x_unused)); | |
2807 | ||
2808 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
2809 | .siclk(siclk), | |
2810 | .soclk(soclk), | |
2811 | .si(si_3), | |
2812 | .so(so_3), | |
2813 | .d(1'b0), | |
2814 | .q(spare3_flop_unused)); | |
2815 | assign si_3 = so_2; | |
2816 | ||
2817 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
2818 | .out(spare3_buf_32x_unused)); | |
2819 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
2820 | .in1(1'b1), | |
2821 | .in2(1'b1), | |
2822 | .out(spare3_nand3_8x_unused)); | |
2823 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
2824 | .out(spare3_inv_8x_unused)); | |
2825 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
2826 | .in01(1'b1), | |
2827 | .in10(1'b1), | |
2828 | .in11(1'b1), | |
2829 | .out(spare3_aoi22_4x_unused)); | |
2830 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
2831 | .out(spare3_buf_8x_unused)); | |
2832 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
2833 | .in01(1'b1), | |
2834 | .in10(1'b1), | |
2835 | .in11(1'b1), | |
2836 | .out(spare3_oai22_4x_unused)); | |
2837 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
2838 | .out(spare3_inv_16x_unused)); | |
2839 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
2840 | .in1(1'b1), | |
2841 | .out(spare3_nand2_16x_unused)); | |
2842 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
2843 | .in1(1'b0), | |
2844 | .in2(1'b0), | |
2845 | .out(spare3_nor3_4x_unused)); | |
2846 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
2847 | .in1(1'b1), | |
2848 | .out(spare3_nand2_8x_unused)); | |
2849 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
2850 | .out(spare3_buf_16x_unused)); | |
2851 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
2852 | .in1(1'b0), | |
2853 | .out(spare3_nor2_16x_unused)); | |
2854 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
2855 | .out(spare3_inv_32x_unused)); | |
2856 | assign scan_out = so_3; | |
2857 | ||
2858 | ||
2859 | ||
2860 | endmodule | |
2861 |